1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include "debug.h"
6 #include "fw.h"
7 #include "mac.h"
8 #include "phy.h"
9 #include "ps.h"
10 #include "reg.h"
11 #include "sar.h"
12 #include "coex.h"
13
get_max_amsdu_len(struct rtw89_dev * rtwdev,const struct rtw89_ra_report * report)14 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev,
15 const struct rtw89_ra_report *report)
16 {
17 u32 bit_rate = report->bit_rate;
18
19 /* lower than ofdm, do not aggregate */
20 if (bit_rate < 550)
21 return 1;
22
23 /* avoid AMSDU for legacy rate */
24 if (report->might_fallback_legacy)
25 return 1;
26
27 /* lower than 20M vht 2ss mcs8, make it small */
28 if (bit_rate < 1800)
29 return 1200;
30
31 /* lower than 40M vht 2ss mcs9, make it medium */
32 if (bit_rate < 4000)
33 return 2600;
34
35 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */
36 if (bit_rate < 7000)
37 return 3500;
38
39 return rtwdev->chip->max_amsdu_limit;
40 }
41
get_mcs_ra_mask(u16 mcs_map,u8 highest_mcs,u8 gap)42 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap)
43 {
44 u64 ra_mask = 0;
45 u8 mcs_cap;
46 int i, nss;
47
48 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) {
49 mcs_cap = mcs_map & 0x3;
50 switch (mcs_cap) {
51 case 2:
52 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss;
53 break;
54 case 1:
55 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss;
56 break;
57 case 0:
58 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss;
59 break;
60 default:
61 break;
62 }
63 }
64
65 return ra_mask;
66 }
67
get_he_ra_mask(struct ieee80211_sta * sta)68 static u64 get_he_ra_mask(struct ieee80211_sta *sta)
69 {
70 struct ieee80211_sta_he_cap cap = sta->deflink.he_cap;
71 u16 mcs_map;
72
73 switch (sta->deflink.bandwidth) {
74 case IEEE80211_STA_RX_BW_160:
75 if (cap.he_cap_elem.phy_cap_info[0] &
76 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G)
77 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80);
78 else
79 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160);
80 break;
81 default:
82 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80);
83 }
84
85 /* MCS11, MCS9, MCS7 */
86 return get_mcs_ra_mask(mcs_map, 11, 2);
87 }
88
89 #define RA_FLOOR_TABLE_SIZE 7
90 #define RA_FLOOR_UP_GAP 3
rtw89_phy_ra_mask_rssi(struct rtw89_dev * rtwdev,u8 rssi,u8 ratr_state)91 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi,
92 u8 ratr_state)
93 {
94 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100};
95 u8 rssi_lv = 0;
96 u8 i;
97
98 rssi >>= 1;
99 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
100 if (i >= ratr_state)
101 rssi_lv_t[i] += RA_FLOOR_UP_GAP;
102 if (rssi < rssi_lv_t[i]) {
103 rssi_lv = i;
104 break;
105 }
106 }
107 if (rssi_lv == 0)
108 return 0xffffffffffffffffULL;
109 else if (rssi_lv == 1)
110 return 0xfffffffffffffff0ULL;
111 else if (rssi_lv == 2)
112 return 0xffffffffffffefe0ULL;
113 else if (rssi_lv == 3)
114 return 0xffffffffffffcfc0ULL;
115 else if (rssi_lv == 4)
116 return 0xffffffffffff8f80ULL;
117 else if (rssi_lv >= 5)
118 return 0xffffffffffff0f00ULL;
119
120 return 0xffffffffffffffffULL;
121 }
122
rtw89_phy_ra_mask_recover(u64 ra_mask,u64 ra_mask_bak)123 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak)
124 {
125 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0)
126 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
127
128 if (ra_mask == 0)
129 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
130
131 return ra_mask;
132 }
133
rtw89_phy_ra_mask_cfg(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta)134 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta)
135 {
136 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
137 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
138 struct cfg80211_bitrate_mask *mask = &rtwsta->mask;
139 enum nl80211_band band;
140 u64 cfg_mask;
141
142 if (!rtwsta->use_cfg_mask)
143 return -1;
144
145 switch (chan->band_type) {
146 case RTW89_BAND_2G:
147 band = NL80211_BAND_2GHZ;
148 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy,
149 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES);
150 break;
151 case RTW89_BAND_5G:
152 band = NL80211_BAND_5GHZ;
153 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy,
154 RA_MASK_OFDM_RATES);
155 break;
156 case RTW89_BAND_6G:
157 band = NL80211_BAND_6GHZ;
158 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy,
159 RA_MASK_OFDM_RATES);
160 break;
161 default:
162 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type);
163 return -1;
164 }
165
166 if (sta->deflink.he_cap.has_he) {
167 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0],
168 RA_MASK_HE_1SS_RATES);
169 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1],
170 RA_MASK_HE_2SS_RATES);
171 } else if (sta->deflink.vht_cap.vht_supported) {
172 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
173 RA_MASK_VHT_1SS_RATES);
174 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
175 RA_MASK_VHT_2SS_RATES);
176 } else if (sta->deflink.ht_cap.ht_supported) {
177 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
178 RA_MASK_HT_1SS_RATES);
179 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
180 RA_MASK_HT_2SS_RATES);
181 }
182
183 return cfg_mask;
184 }
185
186 static const u64
187 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES,
188 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES};
189 static const u64
190 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES,
191 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES};
192 static const u64
193 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES,
194 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES};
195
rtw89_phy_ra_sta_update(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,bool csi)196 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev,
197 struct ieee80211_sta *sta, bool csi)
198 {
199 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
200 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
201 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern;
202 struct rtw89_ra_info *ra = &rtwsta->ra;
203 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
204 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates;
205 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi);
206 u64 ra_mask = 0;
207 u64 ra_mask_bak;
208 u8 mode = 0;
209 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY;
210 u8 bw_mode = 0;
211 u8 stbc_en = 0;
212 u8 ldpc_en = 0;
213 u8 i;
214 bool sgi = false;
215
216 memset(ra, 0, sizeof(*ra));
217 /* Set the ra mask from sta's capability */
218 if (sta->deflink.he_cap.has_he) {
219 mode |= RTW89_RA_MODE_HE;
220 csi_mode = RTW89_RA_RPT_MODE_HE;
221 ra_mask |= get_he_ra_mask(sta);
222 high_rate_masks = rtw89_ra_mask_he_rates;
223 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[2] &
224 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ)
225 stbc_en = 1;
226 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[1] &
227 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD)
228 ldpc_en = 1;
229 } else if (sta->deflink.vht_cap.vht_supported) {
230 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map);
231
232 mode |= RTW89_RA_MODE_VHT;
233 csi_mode = RTW89_RA_RPT_MODE_VHT;
234 /* MCS9, MCS8, MCS7 */
235 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1);
236 high_rate_masks = rtw89_ra_mask_vht_rates;
237 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
238 stbc_en = 1;
239 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
240 ldpc_en = 1;
241 } else if (sta->deflink.ht_cap.ht_supported) {
242 mode |= RTW89_RA_MODE_HT;
243 csi_mode = RTW89_RA_RPT_MODE_HT;
244 ra_mask |= ((u64)sta->deflink.ht_cap.mcs.rx_mask[3] << 48) |
245 ((u64)sta->deflink.ht_cap.mcs.rx_mask[2] << 36) |
246 (sta->deflink.ht_cap.mcs.rx_mask[1] << 24) |
247 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
248 high_rate_masks = rtw89_ra_mask_ht_rates;
249 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
250 stbc_en = 1;
251 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
252 ldpc_en = 1;
253 }
254
255 switch (chan->band_type) {
256 case RTW89_BAND_2G:
257 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ];
258 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] <= 0xf)
259 mode |= RTW89_RA_MODE_CCK;
260 else
261 mode |= RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM;
262 break;
263 case RTW89_BAND_5G:
264 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4;
265 mode |= RTW89_RA_MODE_OFDM;
266 break;
267 case RTW89_BAND_6G:
268 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_6GHZ] << 4;
269 mode |= RTW89_RA_MODE_OFDM;
270 break;
271 default:
272 rtw89_err(rtwdev, "Unknown band type\n");
273 break;
274 }
275
276 ra_mask_bak = ra_mask;
277
278 if (mode >= RTW89_RA_MODE_HT) {
279 u64 mask = 0;
280 for (i = 0; i < rtwdev->hal.tx_nss; i++)
281 mask |= high_rate_masks[i];
282 if (mode & RTW89_RA_MODE_OFDM)
283 mask |= RA_MASK_SUBOFDM_RATES;
284 if (mode & RTW89_RA_MODE_CCK)
285 mask |= RA_MASK_SUBCCK_RATES;
286 ra_mask &= mask;
287 } else if (mode & RTW89_RA_MODE_OFDM) {
288 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES);
289 }
290
291 if (mode != RTW89_RA_MODE_CCK)
292 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0);
293
294 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak);
295 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta);
296
297 switch (sta->deflink.bandwidth) {
298 case IEEE80211_STA_RX_BW_160:
299 bw_mode = RTW89_CHANNEL_WIDTH_160;
300 sgi = sta->deflink.vht_cap.vht_supported &&
301 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160);
302 break;
303 case IEEE80211_STA_RX_BW_80:
304 bw_mode = RTW89_CHANNEL_WIDTH_80;
305 sgi = sta->deflink.vht_cap.vht_supported &&
306 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
307 break;
308 case IEEE80211_STA_RX_BW_40:
309 bw_mode = RTW89_CHANNEL_WIDTH_40;
310 sgi = sta->deflink.ht_cap.ht_supported &&
311 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
312 break;
313 default:
314 bw_mode = RTW89_CHANNEL_WIDTH_20;
315 sgi = sta->deflink.ht_cap.ht_supported &&
316 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
317 break;
318 }
319
320 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] &
321 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM)
322 ra->dcm_cap = 1;
323
324 if (rate_pattern->enable) {
325 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta);
326 ra_mask &= rate_pattern->ra_mask;
327 mode = rate_pattern->ra_mode;
328 }
329
330 ra->bw_cap = bw_mode;
331 ra->mode_ctrl = mode;
332 ra->macid = rtwsta->mac_id;
333 ra->stbc_cap = stbc_en;
334 ra->ldpc_cap = ldpc_en;
335 ra->ss_num = min(sta->deflink.rx_nss, rtwdev->hal.tx_nss) - 1;
336 ra->en_sgi = sgi;
337 ra->ra_mask = ra_mask;
338
339 if (!csi)
340 return;
341
342 ra->fixed_csi_rate_en = false;
343 ra->ra_csi_rate_en = true;
344 ra->cr_tbl_sel = false;
345 ra->band_num = rtwvif->phy_idx;
346 ra->csi_bw = bw_mode;
347 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32;
348 ra->csi_mcs_ss_idx = 5;
349 ra->csi_mode = csi_mode;
350 }
351
rtw89_phy_ra_updata_sta(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,u32 changed)352 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta,
353 u32 changed)
354 {
355 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
356 struct rtw89_ra_info *ra = &rtwsta->ra;
357
358 rtw89_phy_ra_sta_update(rtwdev, sta, false);
359
360 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED)
361 ra->upd_mask = 1;
362 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED))
363 ra->upd_bw_nss_mask = 1;
364
365 rtw89_debug(rtwdev, RTW89_DBG_RA,
366 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d",
367 ra->macid,
368 ra->bw_cap,
369 ra->ss_num,
370 ra->en_sgi,
371 ra->giltf);
372
373 rtw89_fw_h2c_ra(rtwdev, ra, false);
374 }
375
__check_rate_pattern(struct rtw89_phy_rate_pattern * next,u16 rate_base,u64 ra_mask,u8 ra_mode,u32 rate_ctrl,u32 ctrl_skip,bool force)376 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next,
377 u16 rate_base, u64 ra_mask, u8 ra_mode,
378 u32 rate_ctrl, u32 ctrl_skip, bool force)
379 {
380 u8 n, c;
381
382 if (rate_ctrl == ctrl_skip)
383 return true;
384
385 n = hweight32(rate_ctrl);
386 if (n == 0)
387 return true;
388
389 if (force && n != 1)
390 return false;
391
392 if (next->enable)
393 return false;
394
395 c = __fls(rate_ctrl);
396 next->rate = rate_base + c;
397 next->ra_mode = ra_mode;
398 next->ra_mask = ra_mask;
399 next->enable = true;
400
401 return true;
402 }
403
rtw89_phy_rate_pattern_vif(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,const struct cfg80211_bitrate_mask * mask)404 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
405 struct ieee80211_vif *vif,
406 const struct cfg80211_bitrate_mask *mask)
407 {
408 struct ieee80211_supported_band *sband;
409 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
410 struct rtw89_phy_rate_pattern next_pattern = {0};
411 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
412 static const u16 hw_rate_he[] = {RTW89_HW_RATE_HE_NSS1_MCS0,
413 RTW89_HW_RATE_HE_NSS2_MCS0,
414 RTW89_HW_RATE_HE_NSS3_MCS0,
415 RTW89_HW_RATE_HE_NSS4_MCS0};
416 static const u16 hw_rate_vht[] = {RTW89_HW_RATE_VHT_NSS1_MCS0,
417 RTW89_HW_RATE_VHT_NSS2_MCS0,
418 RTW89_HW_RATE_VHT_NSS3_MCS0,
419 RTW89_HW_RATE_VHT_NSS4_MCS0};
420 static const u16 hw_rate_ht[] = {RTW89_HW_RATE_MCS0,
421 RTW89_HW_RATE_MCS8,
422 RTW89_HW_RATE_MCS16,
423 RTW89_HW_RATE_MCS24};
424 u8 band = chan->band_type;
425 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
426 u8 tx_nss = rtwdev->hal.tx_nss;
427 u8 i;
428
429 for (i = 0; i < tx_nss; i++)
430 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i],
431 RA_MASK_HE_RATES, RTW89_RA_MODE_HE,
432 mask->control[nl_band].he_mcs[i],
433 0, true))
434 goto out;
435
436 for (i = 0; i < tx_nss; i++)
437 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i],
438 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT,
439 mask->control[nl_band].vht_mcs[i],
440 0, true))
441 goto out;
442
443 for (i = 0; i < tx_nss; i++)
444 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i],
445 RA_MASK_HT_RATES, RTW89_RA_MODE_HT,
446 mask->control[nl_band].ht_mcs[i],
447 0, true))
448 goto out;
449
450 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and
451 * require at least one basic rate for ieee80211_set_bitrate_mask,
452 * so the decision just depends on if all bitrates are set or not.
453 */
454 sband = rtwdev->hw->wiphy->bands[nl_band];
455 if (band == RTW89_BAND_2G) {
456 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1,
457 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES,
458 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM,
459 mask->control[nl_band].legacy,
460 BIT(sband->n_bitrates) - 1, false))
461 goto out;
462 } else {
463 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6,
464 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM,
465 mask->control[nl_band].legacy,
466 BIT(sband->n_bitrates) - 1, false))
467 goto out;
468 }
469
470 if (!next_pattern.enable)
471 goto out;
472
473 rtwvif->rate_pattern = next_pattern;
474 rtw89_debug(rtwdev, RTW89_DBG_RA,
475 #if defined(__linux__)
476 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n",
477 #elif defined(__FreeBSD__)
478 "configure pattern: rate 0x%x, mask 0x%jx, mode 0x%x\n",
479 #endif
480 next_pattern.rate,
481 #if defined(__FreeBSD__)
482 (uintmax_t)
483 #endif
484 next_pattern.ra_mask,
485 next_pattern.ra_mode);
486 return;
487
488 out:
489 rtwvif->rate_pattern.enable = false;
490 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n");
491 }
492
rtw89_phy_ra_updata_sta_iter(void * data,struct ieee80211_sta * sta)493 static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta)
494 {
495 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data;
496
497 rtw89_phy_ra_updata_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED);
498 }
499
rtw89_phy_ra_update(struct rtw89_dev * rtwdev)500 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev)
501 {
502 ieee80211_iterate_stations_atomic(rtwdev->hw,
503 rtw89_phy_ra_updata_sta_iter,
504 rtwdev);
505 }
506
rtw89_phy_ra_assoc(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)507 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta)
508 {
509 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
510 struct rtw89_ra_info *ra = &rtwsta->ra;
511 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR;
512 bool csi = rtw89_sta_has_beamformer_cap(sta);
513
514 rtw89_phy_ra_sta_update(rtwdev, sta, csi);
515
516 if (rssi > 40)
517 ra->init_rate_lv = 1;
518 else if (rssi > 20)
519 ra->init_rate_lv = 2;
520 else if (rssi > 1)
521 ra->init_rate_lv = 3;
522 else
523 ra->init_rate_lv = 0;
524 ra->upd_all = 1;
525 rtw89_debug(rtwdev, RTW89_DBG_RA,
526 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d",
527 ra->macid,
528 ra->mode_ctrl,
529 ra->bw_cap,
530 ra->ss_num,
531 ra->init_rate_lv);
532 rtw89_debug(rtwdev, RTW89_DBG_RA,
533 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d",
534 ra->dcm_cap,
535 ra->er_cap,
536 ra->ldpc_cap,
537 ra->stbc_cap,
538 ra->en_sgi,
539 ra->giltf);
540
541 rtw89_fw_h2c_ra(rtwdev, ra, csi);
542 }
543
rtw89_phy_get_txsc(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_bandwidth dbw)544 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev,
545 const struct rtw89_chan *chan,
546 enum rtw89_bandwidth dbw)
547 {
548 enum rtw89_bandwidth cbw = chan->band_width;
549 u8 pri_ch = chan->primary_channel;
550 u8 central_ch = chan->channel;
551 u8 txsc_idx = 0;
552 u8 tmp = 0;
553
554 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20)
555 return txsc_idx;
556
557 switch (cbw) {
558 case RTW89_CHANNEL_WIDTH_40:
559 txsc_idx = pri_ch > central_ch ? 1 : 2;
560 break;
561 case RTW89_CHANNEL_WIDTH_80:
562 if (dbw == RTW89_CHANNEL_WIDTH_20) {
563 if (pri_ch > central_ch)
564 txsc_idx = (pri_ch - central_ch) >> 1;
565 else
566 txsc_idx = ((central_ch - pri_ch) >> 1) + 1;
567 } else {
568 txsc_idx = pri_ch > central_ch ? 9 : 10;
569 }
570 break;
571 case RTW89_CHANNEL_WIDTH_160:
572 if (pri_ch > central_ch)
573 tmp = (pri_ch - central_ch) >> 1;
574 else
575 tmp = ((central_ch - pri_ch) >> 1) + 1;
576
577 if (dbw == RTW89_CHANNEL_WIDTH_20) {
578 txsc_idx = tmp;
579 } else if (dbw == RTW89_CHANNEL_WIDTH_40) {
580 if (tmp == 1 || tmp == 3)
581 txsc_idx = 9;
582 else if (tmp == 5 || tmp == 7)
583 txsc_idx = 11;
584 else if (tmp == 2 || tmp == 4)
585 txsc_idx = 10;
586 else if (tmp == 6 || tmp == 8)
587 txsc_idx = 12;
588 else
589 return 0xff;
590 } else {
591 txsc_idx = pri_ch > central_ch ? 13 : 14;
592 }
593 break;
594 case RTW89_CHANNEL_WIDTH_80_80:
595 if (dbw == RTW89_CHANNEL_WIDTH_20) {
596 if (pri_ch > central_ch)
597 txsc_idx = (10 - (pri_ch - central_ch)) >> 1;
598 else
599 txsc_idx = ((central_ch - pri_ch) >> 1) + 5;
600 } else if (dbw == RTW89_CHANNEL_WIDTH_40) {
601 txsc_idx = pri_ch > central_ch ? 10 : 12;
602 } else {
603 txsc_idx = 14;
604 }
605 break;
606 default:
607 break;
608 }
609
610 return txsc_idx;
611 }
612 EXPORT_SYMBOL(rtw89_phy_get_txsc);
613
rtw89_phy_check_swsi_busy(struct rtw89_dev * rtwdev)614 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev)
615 {
616 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) ||
617 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1);
618 }
619
rtw89_phy_read_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)620 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
621 u32 addr, u32 mask)
622 {
623 const struct rtw89_chip_info *chip = rtwdev->chip;
624 const u32 *base_addr = chip->rf_base_addr;
625 u32 val, direct_addr;
626
627 if (rf_path >= rtwdev->chip->rf_path_num) {
628 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
629 return INV_RF_DATA;
630 }
631
632 addr &= 0xff;
633 direct_addr = base_addr[rf_path] + (addr << 2);
634 mask &= RFREG_MASK;
635
636 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask);
637
638 return val;
639 }
640 EXPORT_SYMBOL(rtw89_phy_read_rf);
641
rtw89_phy_read_rf_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)642 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev,
643 enum rtw89_rf_path rf_path, u32 addr, u32 mask)
644 {
645 bool busy;
646 bool done;
647 u32 val;
648 int ret;
649
650 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy,
651 1, 30, false, rtwdev);
652 if (ret) {
653 rtw89_err(rtwdev, "read rf busy swsi\n");
654 return INV_RF_DATA;
655 }
656
657 mask &= RFREG_MASK;
658
659 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) |
660 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr);
661 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val);
662 udelay(2);
663
664 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1,
665 30, false, rtwdev, R_SWSI_V1,
666 B_SWSI_R_DATA_DONE_V1);
667 if (ret) {
668 rtw89_err(rtwdev, "read swsi busy\n");
669 return INV_RF_DATA;
670 }
671
672 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask);
673 }
674
rtw89_phy_read_rf_v1(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)675 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
676 u32 addr, u32 mask)
677 {
678 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr);
679
680 if (rf_path >= rtwdev->chip->rf_path_num) {
681 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
682 return INV_RF_DATA;
683 }
684
685 if (ad_sel)
686 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask);
687 else
688 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask);
689 }
690 EXPORT_SYMBOL(rtw89_phy_read_rf_v1);
691
rtw89_phy_write_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)692 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
693 u32 addr, u32 mask, u32 data)
694 {
695 const struct rtw89_chip_info *chip = rtwdev->chip;
696 const u32 *base_addr = chip->rf_base_addr;
697 u32 direct_addr;
698
699 if (rf_path >= rtwdev->chip->rf_path_num) {
700 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
701 return false;
702 }
703
704 addr &= 0xff;
705 direct_addr = base_addr[rf_path] + (addr << 2);
706 mask &= RFREG_MASK;
707
708 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data);
709
710 /* delay to ensure writing properly */
711 udelay(1);
712
713 return true;
714 }
715 EXPORT_SYMBOL(rtw89_phy_write_rf);
716
rtw89_phy_write_rf_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)717 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev,
718 enum rtw89_rf_path rf_path, u32 addr, u32 mask,
719 u32 data)
720 {
721 u8 bit_shift;
722 u32 val;
723 bool busy, b_msk_en = false;
724 int ret;
725
726 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy,
727 1, 30, false, rtwdev);
728 if (ret) {
729 rtw89_err(rtwdev, "write rf busy swsi\n");
730 return false;
731 }
732
733 data &= RFREG_MASK;
734 mask &= RFREG_MASK;
735
736 if (mask != RFREG_MASK) {
737 b_msk_en = true;
738 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK,
739 mask);
740 bit_shift = __ffs(mask);
741 data = (data << bit_shift) & RFREG_MASK;
742 }
743
744 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) |
745 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) |
746 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) |
747 FIELD_PREP(B_SWSI_DATA_VAL_V1, data);
748
749 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val);
750
751 return true;
752 }
753
rtw89_phy_write_rf_v1(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)754 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
755 u32 addr, u32 mask, u32 data)
756 {
757 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr);
758
759 if (rf_path >= rtwdev->chip->rf_path_num) {
760 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
761 return false;
762 }
763
764 if (ad_sel)
765 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data);
766 else
767 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data);
768 }
769 EXPORT_SYMBOL(rtw89_phy_write_rf_v1);
770
rtw89_phy_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)771 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev,
772 enum rtw89_phy_idx phy_idx)
773 {
774 const struct rtw89_chip_info *chip = rtwdev->chip;
775
776 chip->ops->bb_reset(rtwdev, phy_idx);
777 }
778
rtw89_phy_config_bb_reg(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)779 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev,
780 const struct rtw89_reg2_def *reg,
781 enum rtw89_rf_path rf_path,
782 void *extra_data)
783 {
784 if (reg->addr == 0xfe)
785 mdelay(50);
786 else if (reg->addr == 0xfd)
787 mdelay(5);
788 else if (reg->addr == 0xfc)
789 mdelay(1);
790 else if (reg->addr == 0xfb)
791 udelay(50);
792 else if (reg->addr == 0xfa)
793 udelay(5);
794 else if (reg->addr == 0xf9)
795 udelay(1);
796 else
797 rtw89_phy_write32(rtwdev, reg->addr, reg->data);
798 }
799
800 union rtw89_phy_bb_gain_arg {
801 u32 addr;
802 struct {
803 union {
804 u8 type;
805 struct {
806 u8 rxsc_start:4;
807 u8 bw:4;
808 };
809 };
810 u8 path;
811 u8 gain_band;
812 u8 cfg_type;
813 };
814 } __packed;
815
816 static void
rtw89_phy_cfg_bb_gain_error(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)817 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev,
818 union rtw89_phy_bb_gain_arg arg, u32 data)
819 {
820 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
821 u8 type = arg.type;
822 u8 path = arg.path;
823 u8 gband = arg.gain_band;
824 int i;
825
826 switch (type) {
827 case 0:
828 for (i = 0; i < 4; i++, data >>= 8)
829 gain->lna_gain[gband][path][i] = data & 0xff;
830 break;
831 case 1:
832 for (i = 4; i < 7; i++, data >>= 8)
833 gain->lna_gain[gband][path][i] = data & 0xff;
834 break;
835 case 2:
836 for (i = 0; i < 2; i++, data >>= 8)
837 gain->tia_gain[gband][path][i] = data & 0xff;
838 break;
839 default:
840 rtw89_warn(rtwdev,
841 "bb gain error {0x%x:0x%x} with unknown type: %d\n",
842 arg.addr, data, type);
843 break;
844 }
845 }
846
847 enum rtw89_phy_bb_rxsc_start_idx {
848 RTW89_BB_RXSC_START_IDX_FULL = 0,
849 RTW89_BB_RXSC_START_IDX_20 = 1,
850 RTW89_BB_RXSC_START_IDX_20_1 = 5,
851 RTW89_BB_RXSC_START_IDX_40 = 9,
852 RTW89_BB_RXSC_START_IDX_80 = 13,
853 };
854
855 static void
rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)856 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev,
857 union rtw89_phy_bb_gain_arg arg, u32 data)
858 {
859 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
860 u8 rxsc_start = arg.rxsc_start;
861 u8 bw = arg.bw;
862 u8 path = arg.path;
863 u8 gband = arg.gain_band;
864 u8 rxsc;
865 s8 ofst;
866 int i;
867
868 switch (bw) {
869 case RTW89_CHANNEL_WIDTH_20:
870 gain->rpl_ofst_20[gband][path] = (s8)data;
871 break;
872 case RTW89_CHANNEL_WIDTH_40:
873 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
874 gain->rpl_ofst_40[gband][path][0] = (s8)data;
875 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
876 for (i = 0; i < 2; i++, data >>= 8) {
877 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
878 ofst = (s8)(data & 0xff);
879 gain->rpl_ofst_40[gband][path][rxsc] = ofst;
880 }
881 }
882 break;
883 case RTW89_CHANNEL_WIDTH_80:
884 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
885 gain->rpl_ofst_80[gband][path][0] = (s8)data;
886 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
887 for (i = 0; i < 4; i++, data >>= 8) {
888 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
889 ofst = (s8)(data & 0xff);
890 gain->rpl_ofst_80[gband][path][rxsc] = ofst;
891 }
892 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) {
893 for (i = 0; i < 2; i++, data >>= 8) {
894 rxsc = RTW89_BB_RXSC_START_IDX_40 + i;
895 ofst = (s8)(data & 0xff);
896 gain->rpl_ofst_80[gband][path][rxsc] = ofst;
897 }
898 }
899 break;
900 case RTW89_CHANNEL_WIDTH_160:
901 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
902 gain->rpl_ofst_160[gband][path][0] = (s8)data;
903 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
904 for (i = 0; i < 4; i++, data >>= 8) {
905 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
906 ofst = (s8)(data & 0xff);
907 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
908 }
909 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) {
910 for (i = 0; i < 4; i++, data >>= 8) {
911 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i;
912 ofst = (s8)(data & 0xff);
913 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
914 }
915 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) {
916 for (i = 0; i < 4; i++, data >>= 8) {
917 rxsc = RTW89_BB_RXSC_START_IDX_40 + i;
918 ofst = (s8)(data & 0xff);
919 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
920 }
921 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) {
922 for (i = 0; i < 2; i++, data >>= 8) {
923 rxsc = RTW89_BB_RXSC_START_IDX_80 + i;
924 ofst = (s8)(data & 0xff);
925 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
926 }
927 }
928 break;
929 default:
930 rtw89_warn(rtwdev,
931 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n",
932 arg.addr, data, bw);
933 break;
934 }
935 }
936
937 static void
rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)938 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev,
939 union rtw89_phy_bb_gain_arg arg, u32 data)
940 {
941 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
942 u8 type = arg.type;
943 u8 path = arg.path;
944 u8 gband = arg.gain_band;
945 int i;
946
947 switch (type) {
948 case 0:
949 for (i = 0; i < 4; i++, data >>= 8)
950 gain->lna_gain_bypass[gband][path][i] = data & 0xff;
951 break;
952 case 1:
953 for (i = 4; i < 7; i++, data >>= 8)
954 gain->lna_gain_bypass[gband][path][i] = data & 0xff;
955 break;
956 default:
957 rtw89_warn(rtwdev,
958 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n",
959 arg.addr, data, type);
960 break;
961 }
962 }
963
964 static void
rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)965 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev,
966 union rtw89_phy_bb_gain_arg arg, u32 data)
967 {
968 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
969 u8 type = arg.type;
970 u8 path = arg.path;
971 u8 gband = arg.gain_band;
972 int i;
973
974 switch (type) {
975 case 0:
976 for (i = 0; i < 4; i++, data >>= 8)
977 gain->lna_op1db[gband][path][i] = data & 0xff;
978 break;
979 case 1:
980 for (i = 4; i < 7; i++, data >>= 8)
981 gain->lna_op1db[gband][path][i] = data & 0xff;
982 break;
983 case 2:
984 for (i = 0; i < 4; i++, data >>= 8)
985 gain->tia_lna_op1db[gband][path][i] = data & 0xff;
986 break;
987 case 3:
988 for (i = 4; i < 8; i++, data >>= 8)
989 gain->tia_lna_op1db[gband][path][i] = data & 0xff;
990 break;
991 default:
992 rtw89_warn(rtwdev,
993 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n",
994 arg.addr, data, type);
995 break;
996 }
997 }
998
rtw89_phy_config_bb_gain(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)999 static void rtw89_phy_config_bb_gain(struct rtw89_dev *rtwdev,
1000 const struct rtw89_reg2_def *reg,
1001 enum rtw89_rf_path rf_path,
1002 void *extra_data)
1003 {
1004 const struct rtw89_chip_info *chip = rtwdev->chip;
1005 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr };
1006
1007 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR)
1008 return;
1009
1010 if (arg.path >= chip->rf_path_num)
1011 return;
1012
1013 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) {
1014 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n");
1015 return;
1016 }
1017
1018 switch (arg.cfg_type) {
1019 case 0:
1020 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data);
1021 break;
1022 case 1:
1023 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data);
1024 break;
1025 case 2:
1026 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data);
1027 break;
1028 case 3:
1029 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data);
1030 break;
1031 default:
1032 rtw89_warn(rtwdev,
1033 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n",
1034 arg.addr, reg->data, arg.cfg_type);
1035 break;
1036 }
1037 }
1038
1039 static void
rtw89_phy_cofig_rf_reg_store(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,struct rtw89_fw_h2c_rf_reg_info * info)1040 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev,
1041 const struct rtw89_reg2_def *reg,
1042 enum rtw89_rf_path rf_path,
1043 struct rtw89_fw_h2c_rf_reg_info *info)
1044 {
1045 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE;
1046 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE;
1047
1048 if (page >= RTW89_H2C_RF_PAGE_NUM) {
1049 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d",
1050 rf_path, info->curr_idx);
1051 return;
1052 }
1053
1054 info->rtw89_phy_config_rf_h2c[page][idx] =
1055 cpu_to_le32((reg->addr << 20) | reg->data);
1056 info->curr_idx++;
1057 }
1058
rtw89_phy_config_rf_reg_fw(struct rtw89_dev * rtwdev,struct rtw89_fw_h2c_rf_reg_info * info)1059 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev,
1060 struct rtw89_fw_h2c_rf_reg_info *info)
1061 {
1062 u16 remain = info->curr_idx;
1063 u16 len = 0;
1064 u8 i;
1065 int ret = 0;
1066
1067 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) {
1068 rtw89_warn(rtwdev,
1069 "rf reg h2c total len %d larger than %d\n",
1070 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE);
1071 ret = -EINVAL;
1072 goto out;
1073 }
1074
1075 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) {
1076 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain;
1077 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i);
1078 if (ret)
1079 goto out;
1080 }
1081 out:
1082 info->curr_idx = 0;
1083
1084 return ret;
1085 }
1086
rtw89_phy_config_rf_reg(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1087 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev,
1088 const struct rtw89_reg2_def *reg,
1089 enum rtw89_rf_path rf_path,
1090 void *extra_data)
1091 {
1092 if (reg->addr == 0xfe) {
1093 mdelay(50);
1094 } else if (reg->addr == 0xfd) {
1095 mdelay(5);
1096 } else if (reg->addr == 0xfc) {
1097 mdelay(1);
1098 } else if (reg->addr == 0xfb) {
1099 udelay(50);
1100 } else if (reg->addr == 0xfa) {
1101 udelay(5);
1102 } else if (reg->addr == 0xf9) {
1103 udelay(1);
1104 } else {
1105 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data);
1106 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1107 (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1108 }
1109 }
1110
rtw89_phy_config_rf_reg_v1(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1111 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
1112 const struct rtw89_reg2_def *reg,
1113 enum rtw89_rf_path rf_path,
1114 void *extra_data)
1115 {
1116 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data);
1117
1118 if (reg->addr < 0x100)
1119 return;
1120
1121 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1122 (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1123 }
1124 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1);
1125
rtw89_phy_sel_headline(struct rtw89_dev * rtwdev,const struct rtw89_phy_table * table,u32 * headline_size,u32 * headline_idx,u8 rfe,u8 cv)1126 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev,
1127 const struct rtw89_phy_table *table,
1128 u32 *headline_size, u32 *headline_idx,
1129 u8 rfe, u8 cv)
1130 {
1131 const struct rtw89_reg2_def *reg;
1132 u32 headline;
1133 u32 compare, target;
1134 u8 rfe_para, cv_para;
1135 u8 cv_max = 0;
1136 bool case_matched = false;
1137 u32 i;
1138
1139 for (i = 0; i < table->n_regs; i++) {
1140 reg = &table->regs[i];
1141 headline = get_phy_headline(reg->addr);
1142 if (headline != PHY_HEADLINE_VALID)
1143 break;
1144 }
1145 *headline_size = i;
1146 if (*headline_size == 0)
1147 return 0;
1148
1149 /* case 1: RFE match, CV match */
1150 compare = get_phy_compare(rfe, cv);
1151 for (i = 0; i < *headline_size; i++) {
1152 reg = &table->regs[i];
1153 target = get_phy_target(reg->addr);
1154 if (target == compare) {
1155 *headline_idx = i;
1156 return 0;
1157 }
1158 }
1159
1160 /* case 2: RFE match, CV don't care */
1161 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE);
1162 for (i = 0; i < *headline_size; i++) {
1163 reg = &table->regs[i];
1164 target = get_phy_target(reg->addr);
1165 if (target == compare) {
1166 *headline_idx = i;
1167 return 0;
1168 }
1169 }
1170
1171 /* case 3: RFE match, CV max in table */
1172 for (i = 0; i < *headline_size; i++) {
1173 reg = &table->regs[i];
1174 rfe_para = get_phy_cond_rfe(reg->addr);
1175 cv_para = get_phy_cond_cv(reg->addr);
1176 if (rfe_para == rfe) {
1177 if (cv_para >= cv_max) {
1178 cv_max = cv_para;
1179 *headline_idx = i;
1180 case_matched = true;
1181 }
1182 }
1183 }
1184
1185 if (case_matched)
1186 return 0;
1187
1188 /* case 4: RFE don't care, CV max in table */
1189 for (i = 0; i < *headline_size; i++) {
1190 reg = &table->regs[i];
1191 rfe_para = get_phy_cond_rfe(reg->addr);
1192 cv_para = get_phy_cond_cv(reg->addr);
1193 if (rfe_para == PHY_COND_DONT_CARE) {
1194 if (cv_para >= cv_max) {
1195 cv_max = cv_para;
1196 *headline_idx = i;
1197 case_matched = true;
1198 }
1199 }
1200 }
1201
1202 if (case_matched)
1203 return 0;
1204
1205 return -EINVAL;
1206 }
1207
rtw89_phy_init_reg(struct rtw89_dev * rtwdev,const struct rtw89_phy_table * table,void (* config)(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * data),void * extra_data)1208 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev,
1209 const struct rtw89_phy_table *table,
1210 void (*config)(struct rtw89_dev *rtwdev,
1211 const struct rtw89_reg2_def *reg,
1212 enum rtw89_rf_path rf_path,
1213 void *data),
1214 void *extra_data)
1215 {
1216 const struct rtw89_reg2_def *reg;
1217 enum rtw89_rf_path rf_path = table->rf_path;
1218 u8 rfe = rtwdev->efuse.rfe_type;
1219 u8 cv = rtwdev->hal.cv;
1220 u32 i;
1221 u32 headline_size = 0, headline_idx = 0;
1222 u32 target = 0, cfg_target;
1223 u8 cond;
1224 bool is_matched = true;
1225 bool target_found = false;
1226 int ret;
1227
1228 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size,
1229 &headline_idx, rfe, cv);
1230 if (ret) {
1231 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv);
1232 return;
1233 }
1234
1235 cfg_target = get_phy_target(table->regs[headline_idx].addr);
1236 for (i = headline_size; i < table->n_regs; i++) {
1237 reg = &table->regs[i];
1238 cond = get_phy_cond(reg->addr);
1239 switch (cond) {
1240 case PHY_COND_BRANCH_IF:
1241 case PHY_COND_BRANCH_ELIF:
1242 target = get_phy_target(reg->addr);
1243 break;
1244 case PHY_COND_BRANCH_ELSE:
1245 is_matched = false;
1246 if (!target_found) {
1247 rtw89_warn(rtwdev, "failed to load CR %x/%x\n",
1248 reg->addr, reg->data);
1249 return;
1250 }
1251 break;
1252 case PHY_COND_BRANCH_END:
1253 is_matched = true;
1254 target_found = false;
1255 break;
1256 case PHY_COND_CHECK:
1257 if (target_found) {
1258 is_matched = false;
1259 break;
1260 }
1261
1262 if (target == cfg_target) {
1263 is_matched = true;
1264 target_found = true;
1265 } else {
1266 is_matched = false;
1267 target_found = false;
1268 }
1269 break;
1270 default:
1271 if (is_matched)
1272 config(rtwdev, reg, rf_path, extra_data);
1273 break;
1274 }
1275 }
1276 }
1277
rtw89_phy_init_bb_reg(struct rtw89_dev * rtwdev)1278 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev)
1279 {
1280 const struct rtw89_chip_info *chip = rtwdev->chip;
1281 const struct rtw89_phy_table *bb_table = chip->bb_table;
1282 const struct rtw89_phy_table *bb_gain_table = chip->bb_gain_table;
1283
1284 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL);
1285 rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0);
1286 if (bb_gain_table)
1287 rtw89_phy_init_reg(rtwdev, bb_gain_table,
1288 rtw89_phy_config_bb_gain, NULL);
1289 rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0);
1290 }
1291
rtw89_phy_nctl_poll(struct rtw89_dev * rtwdev)1292 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev)
1293 {
1294 rtw89_phy_write32(rtwdev, 0x8080, 0x4);
1295 udelay(1);
1296 return rtw89_phy_read32(rtwdev, 0x8080);
1297 }
1298
rtw89_phy_init_rf_reg(struct rtw89_dev * rtwdev)1299 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev)
1300 {
1301 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
1302 enum rtw89_rf_path rf_path, void *data);
1303 const struct rtw89_chip_info *chip = rtwdev->chip;
1304 const struct rtw89_phy_table *rf_table;
1305 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info;
1306 u8 path;
1307
1308 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL);
1309 if (!rf_reg_info)
1310 return;
1311
1312 for (path = RF_PATH_A; path < chip->rf_path_num; path++) {
1313 rf_table = chip->rf_table[path];
1314 rf_reg_info->rf_path = rf_table->rf_path;
1315 config = rf_table->config ? rf_table->config : rtw89_phy_config_rf_reg;
1316 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info);
1317 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info))
1318 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n",
1319 rf_reg_info->rf_path);
1320 }
1321 kfree(rf_reg_info);
1322 }
1323
rtw89_phy_init_rf_nctl(struct rtw89_dev * rtwdev)1324 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev)
1325 {
1326 const struct rtw89_chip_info *chip = rtwdev->chip;
1327 const struct rtw89_phy_table *nctl_table;
1328 u32 val;
1329 int ret;
1330
1331 /* IQK/DPK clock & reset */
1332 rtw89_phy_write32_set(rtwdev, 0x0c60, 0x3);
1333 rtw89_phy_write32_set(rtwdev, 0x0c6c, 0x1);
1334 rtw89_phy_write32_set(rtwdev, 0x58ac, 0x8000000);
1335 rtw89_phy_write32_set(rtwdev, 0x78ac, 0x8000000);
1336
1337 /* check 0x8080 */
1338 rtw89_phy_write32(rtwdev, 0x8000, 0x8);
1339
1340 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10,
1341 1000, false, rtwdev);
1342 if (ret)
1343 #if defined(__linux__)
1344 rtw89_err(rtwdev, "failed to poll nctl block\n");
1345 #elif defined(__FreeBSD__)
1346 rtw89_err(rtwdev, "failed to poll nctl block: ret %d val %#06x\n", ret, val);
1347 #endif
1348
1349 nctl_table = chip->nctl_table;
1350 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL);
1351 }
1352
rtw89_phy0_phy1_offset(struct rtw89_dev * rtwdev,u32 addr)1353 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr)
1354 {
1355 u32 phy_page = addr >> 8;
1356 u32 ofst = 0;
1357
1358 switch (phy_page) {
1359 case 0x6:
1360 case 0x7:
1361 case 0x8:
1362 case 0x9:
1363 case 0xa:
1364 case 0xb:
1365 case 0xc:
1366 case 0xd:
1367 case 0x19:
1368 case 0x1a:
1369 case 0x1b:
1370 ofst = 0x2000;
1371 break;
1372 default:
1373 /* warning case */
1374 ofst = 0;
1375 break;
1376 }
1377
1378 if (phy_page >= 0x40 && phy_page <= 0x4f)
1379 ofst = 0x2000;
1380
1381 return ofst;
1382 }
1383
rtw89_phy_write32_idx(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data,enum rtw89_phy_idx phy_idx)1384 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1385 u32 data, enum rtw89_phy_idx phy_idx)
1386 {
1387 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1388 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1389 rtw89_phy_write32_mask(rtwdev, addr, mask, data);
1390 }
1391 EXPORT_SYMBOL(rtw89_phy_write32_idx);
1392
rtw89_phy_set_phy_regs(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 val)1393 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1394 u32 val)
1395 {
1396 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0);
1397
1398 if (!rtwdev->dbcc_en)
1399 return;
1400
1401 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1);
1402 }
1403
rtw89_phy_write_reg3_tbl(struct rtw89_dev * rtwdev,const struct rtw89_phy_reg3_tbl * tbl)1404 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
1405 const struct rtw89_phy_reg3_tbl *tbl)
1406 {
1407 const struct rtw89_reg3_def *reg3;
1408 int i;
1409
1410 for (i = 0; i < tbl->size; i++) {
1411 reg3 = &tbl->reg3[i];
1412 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data);
1413 }
1414 }
1415 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl);
1416
1417 const u8 rtw89_rs_idx_max[] = {
1418 [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX,
1419 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX,
1420 [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX,
1421 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX,
1422 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX,
1423 };
1424 EXPORT_SYMBOL(rtw89_rs_idx_max);
1425
1426 const u8 rtw89_rs_nss_max[] = {
1427 [RTW89_RS_CCK] = 1,
1428 [RTW89_RS_OFDM] = 1,
1429 [RTW89_RS_MCS] = RTW89_NSS_MAX,
1430 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX,
1431 [RTW89_RS_OFFSET] = 1,
1432 };
1433 EXPORT_SYMBOL(rtw89_rs_nss_max);
1434
1435 static const u8 _byr_of_rs[] = {
1436 [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck),
1437 [RTW89_RS_OFDM] = offsetof(struct rtw89_txpwr_byrate, ofdm),
1438 [RTW89_RS_MCS] = offsetof(struct rtw89_txpwr_byrate, mcs),
1439 [RTW89_RS_HEDCM] = offsetof(struct rtw89_txpwr_byrate, hedcm),
1440 [RTW89_RS_OFFSET] = offsetof(struct rtw89_txpwr_byrate, offset),
1441 };
1442
1443 #define _byr_seek(rs, raw) ((s8 *)(raw) + _byr_of_rs[rs])
1444 #define _byr_idx(rs, nss, idx) ((nss) * rtw89_rs_idx_max[rs] + (idx))
1445 #define _byr_chk(rs, nss, idx) \
1446 ((nss) < rtw89_rs_nss_max[rs] && (idx) < rtw89_rs_idx_max[rs])
1447
rtw89_phy_load_txpwr_byrate(struct rtw89_dev * rtwdev,const struct rtw89_txpwr_table * tbl)1448 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
1449 const struct rtw89_txpwr_table *tbl)
1450 {
1451 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data;
1452 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size;
1453 s8 *byr;
1454 u32 data;
1455 u8 i, idx;
1456
1457 for (; cfg < end; cfg++) {
1458 byr = _byr_seek(cfg->rs, &rtwdev->byr[cfg->band]);
1459 data = cfg->data;
1460
1461 for (i = 0; i < cfg->len; i++, data >>= 8) {
1462 idx = _byr_idx(cfg->rs, cfg->nss, (cfg->shf + i));
1463 byr[idx] = (s8)(data & 0xff);
1464 }
1465 }
1466 }
1467 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate);
1468
1469 #define _phy_txpwr_rf_to_mac(rtwdev, txpwr_rf) \
1470 ({ \
1471 const struct rtw89_chip_info *__c = (rtwdev)->chip; \
1472 (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \
1473 })
1474
rtw89_phy_read_txpwr_byrate(struct rtw89_dev * rtwdev,u8 band,const struct rtw89_rate_desc * rate_desc)1475 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band,
1476 const struct rtw89_rate_desc *rate_desc)
1477 {
1478 s8 *byr;
1479 u8 idx;
1480
1481 if (rate_desc->rs == RTW89_RS_CCK)
1482 band = RTW89_BAND_2G;
1483
1484 if (!_byr_chk(rate_desc->rs, rate_desc->nss, rate_desc->idx)) {
1485 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1486 "[TXPWR] unknown byrate desc rs=%d nss=%d idx=%d\n",
1487 rate_desc->rs, rate_desc->nss, rate_desc->idx);
1488
1489 return 0;
1490 }
1491
1492 byr = _byr_seek(rate_desc->rs, &rtwdev->byr[band]);
1493 idx = _byr_idx(rate_desc->rs, rate_desc->nss, rate_desc->idx);
1494
1495 return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]);
1496 }
1497 EXPORT_SYMBOL(rtw89_phy_read_txpwr_byrate);
1498
rtw89_channel_6g_to_idx(struct rtw89_dev * rtwdev,u8 channel_6g)1499 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g)
1500 {
1501 switch (channel_6g) {
1502 case 1 ... 29:
1503 return (channel_6g - 1) / 2;
1504 case 33 ... 61:
1505 return (channel_6g - 3) / 2;
1506 case 65 ... 93:
1507 return (channel_6g - 5) / 2;
1508 case 97 ... 125:
1509 return (channel_6g - 7) / 2;
1510 case 129 ... 157:
1511 return (channel_6g - 9) / 2;
1512 case 161 ... 189:
1513 return (channel_6g - 11) / 2;
1514 case 193 ... 221:
1515 return (channel_6g - 13) / 2;
1516 case 225 ... 253:
1517 return (channel_6g - 15) / 2;
1518 default:
1519 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g);
1520 return 0;
1521 }
1522 }
1523
rtw89_channel_to_idx(struct rtw89_dev * rtwdev,u8 band,u8 channel)1524 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel)
1525 {
1526 if (band == RTW89_BAND_6G)
1527 return rtw89_channel_6g_to_idx(rtwdev, channel);
1528
1529 switch (channel) {
1530 case 1 ... 14:
1531 return channel - 1;
1532 case 36 ... 64:
1533 return (channel - 36) / 2;
1534 case 100 ... 144:
1535 return ((channel - 100) / 2) + 15;
1536 case 149 ... 177:
1537 return ((channel - 149) / 2) + 38;
1538 default:
1539 rtw89_warn(rtwdev, "unknown channel: %d\n", channel);
1540 return 0;
1541 }
1542 }
1543
rtw89_phy_read_txpwr_limit(struct rtw89_dev * rtwdev,u8 band,u8 bw,u8 ntx,u8 rs,u8 bf,u8 ch)1544 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
1545 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch)
1546 {
1547 const struct rtw89_chip_info *chip = rtwdev->chip;
1548 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
1549 u8 regd = rtw89_regd_get(rtwdev, band);
1550 s8 lmt = 0, sar;
1551
1552 switch (band) {
1553 case RTW89_BAND_2G:
1554 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf][regd][ch_idx];
1555 if (!lmt)
1556 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf]
1557 [RTW89_WW][ch_idx];
1558 break;
1559 case RTW89_BAND_5G:
1560 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf][regd][ch_idx];
1561 if (!lmt)
1562 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf]
1563 [RTW89_WW][ch_idx];
1564 break;
1565 case RTW89_BAND_6G:
1566 lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf][regd][ch_idx];
1567 if (!lmt)
1568 lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf]
1569 [RTW89_WW][ch_idx];
1570 break;
1571 default:
1572 rtw89_warn(rtwdev, "unknown band type: %d\n", band);
1573 return 0;
1574 }
1575
1576 lmt = _phy_txpwr_rf_to_mac(rtwdev, lmt);
1577 sar = rtw89_query_sar(rtwdev);
1578
1579 return min(lmt, sar);
1580 }
1581 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit);
1582
1583 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \
1584 do { \
1585 u8 __i; \
1586 for (__i = 0; __i < RTW89_BF_NUM; __i++) \
1587 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \
1588 band, \
1589 bw, ntx, \
1590 rs, __i, \
1591 (ch)); \
1592 } while (0)
1593
rtw89_phy_fill_txpwr_limit_20m(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit * lmt,u8 band,u8 ntx,u8 ch)1594 static void rtw89_phy_fill_txpwr_limit_20m(struct rtw89_dev *rtwdev,
1595 struct rtw89_txpwr_limit *lmt,
1596 u8 band, u8 ntx, u8 ch)
1597 {
1598 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20,
1599 ntx, RTW89_RS_CCK, ch);
1600 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40,
1601 ntx, RTW89_RS_CCK, ch);
1602 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
1603 ntx, RTW89_RS_OFDM, ch);
1604 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
1605 RTW89_CHANNEL_WIDTH_20,
1606 ntx, RTW89_RS_MCS, ch);
1607 }
1608
rtw89_phy_fill_txpwr_limit_40m(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)1609 static void rtw89_phy_fill_txpwr_limit_40m(struct rtw89_dev *rtwdev,
1610 struct rtw89_txpwr_limit *lmt,
1611 u8 band, u8 ntx, u8 ch, u8 pri_ch)
1612 {
1613 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20,
1614 ntx, RTW89_RS_CCK, ch - 2);
1615 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40,
1616 ntx, RTW89_RS_CCK, ch);
1617 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
1618 ntx, RTW89_RS_OFDM, pri_ch);
1619 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
1620 RTW89_CHANNEL_WIDTH_20,
1621 ntx, RTW89_RS_MCS, ch - 2);
1622 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
1623 RTW89_CHANNEL_WIDTH_20,
1624 ntx, RTW89_RS_MCS, ch + 2);
1625 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
1626 RTW89_CHANNEL_WIDTH_40,
1627 ntx, RTW89_RS_MCS, ch);
1628 }
1629
rtw89_phy_fill_txpwr_limit_80m(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)1630 static void rtw89_phy_fill_txpwr_limit_80m(struct rtw89_dev *rtwdev,
1631 struct rtw89_txpwr_limit *lmt,
1632 u8 band, u8 ntx, u8 ch, u8 pri_ch)
1633 {
1634 s8 val_0p5_n[RTW89_BF_NUM];
1635 s8 val_0p5_p[RTW89_BF_NUM];
1636 u8 i;
1637
1638 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
1639 ntx, RTW89_RS_OFDM, pri_ch);
1640 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
1641 RTW89_CHANNEL_WIDTH_20,
1642 ntx, RTW89_RS_MCS, ch - 6);
1643 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
1644 RTW89_CHANNEL_WIDTH_20,
1645 ntx, RTW89_RS_MCS, ch - 2);
1646 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band,
1647 RTW89_CHANNEL_WIDTH_20,
1648 ntx, RTW89_RS_MCS, ch + 2);
1649 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band,
1650 RTW89_CHANNEL_WIDTH_20,
1651 ntx, RTW89_RS_MCS, ch + 6);
1652 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
1653 RTW89_CHANNEL_WIDTH_40,
1654 ntx, RTW89_RS_MCS, ch - 4);
1655 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band,
1656 RTW89_CHANNEL_WIDTH_40,
1657 ntx, RTW89_RS_MCS, ch + 4);
1658 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band,
1659 RTW89_CHANNEL_WIDTH_80,
1660 ntx, RTW89_RS_MCS, ch);
1661
1662 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40,
1663 ntx, RTW89_RS_MCS, ch - 4);
1664 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40,
1665 ntx, RTW89_RS_MCS, ch + 4);
1666
1667 for (i = 0; i < RTW89_BF_NUM; i++)
1668 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]);
1669 }
1670
rtw89_phy_fill_txpwr_limit_160m(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)1671 static void rtw89_phy_fill_txpwr_limit_160m(struct rtw89_dev *rtwdev,
1672 struct rtw89_txpwr_limit *lmt,
1673 u8 band, u8 ntx, u8 ch, u8 pri_ch)
1674 {
1675 s8 val_0p5_n[RTW89_BF_NUM];
1676 s8 val_0p5_p[RTW89_BF_NUM];
1677 s8 val_2p5_n[RTW89_BF_NUM];
1678 s8 val_2p5_p[RTW89_BF_NUM];
1679 u8 i;
1680
1681 /* fill ofdm section */
1682 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
1683 ntx, RTW89_RS_OFDM, pri_ch);
1684
1685 /* fill mcs 20m section */
1686 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
1687 RTW89_CHANNEL_WIDTH_20,
1688 ntx, RTW89_RS_MCS, ch - 14);
1689 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
1690 RTW89_CHANNEL_WIDTH_20,
1691 ntx, RTW89_RS_MCS, ch - 10);
1692 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band,
1693 RTW89_CHANNEL_WIDTH_20,
1694 ntx, RTW89_RS_MCS, ch - 6);
1695 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band,
1696 RTW89_CHANNEL_WIDTH_20,
1697 ntx, RTW89_RS_MCS, ch - 2);
1698 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band,
1699 RTW89_CHANNEL_WIDTH_20,
1700 ntx, RTW89_RS_MCS, ch + 2);
1701 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band,
1702 RTW89_CHANNEL_WIDTH_20,
1703 ntx, RTW89_RS_MCS, ch + 6);
1704 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band,
1705 RTW89_CHANNEL_WIDTH_20,
1706 ntx, RTW89_RS_MCS, ch + 10);
1707 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band,
1708 RTW89_CHANNEL_WIDTH_20,
1709 ntx, RTW89_RS_MCS, ch + 14);
1710
1711 /* fill mcs 40m section */
1712 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
1713 RTW89_CHANNEL_WIDTH_40,
1714 ntx, RTW89_RS_MCS, ch - 12);
1715 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band,
1716 RTW89_CHANNEL_WIDTH_40,
1717 ntx, RTW89_RS_MCS, ch - 4);
1718 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band,
1719 RTW89_CHANNEL_WIDTH_40,
1720 ntx, RTW89_RS_MCS, ch + 4);
1721 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band,
1722 RTW89_CHANNEL_WIDTH_40,
1723 ntx, RTW89_RS_MCS, ch + 12);
1724
1725 /* fill mcs 80m section */
1726 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band,
1727 RTW89_CHANNEL_WIDTH_80,
1728 ntx, RTW89_RS_MCS, ch - 8);
1729 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band,
1730 RTW89_CHANNEL_WIDTH_80,
1731 ntx, RTW89_RS_MCS, ch + 8);
1732
1733 /* fill mcs 160m section */
1734 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band,
1735 RTW89_CHANNEL_WIDTH_160,
1736 ntx, RTW89_RS_MCS, ch);
1737
1738 /* fill mcs 40m 0p5 section */
1739 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40,
1740 ntx, RTW89_RS_MCS, ch - 4);
1741 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40,
1742 ntx, RTW89_RS_MCS, ch + 4);
1743
1744 for (i = 0; i < RTW89_BF_NUM; i++)
1745 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]);
1746
1747 /* fill mcs 40m 2p5 section */
1748 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40,
1749 ntx, RTW89_RS_MCS, ch - 8);
1750 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40,
1751 ntx, RTW89_RS_MCS, ch + 8);
1752
1753 for (i = 0; i < RTW89_BF_NUM; i++)
1754 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]);
1755 }
1756
rtw89_phy_fill_txpwr_limit(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,struct rtw89_txpwr_limit * lmt,u8 ntx)1757 void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev,
1758 const struct rtw89_chan *chan,
1759 struct rtw89_txpwr_limit *lmt,
1760 u8 ntx)
1761 {
1762 u8 band = chan->band_type;
1763 u8 pri_ch = chan->primary_channel;
1764 u8 ch = chan->channel;
1765 u8 bw = chan->band_width;
1766
1767 memset(lmt, 0, sizeof(*lmt));
1768
1769 switch (bw) {
1770 case RTW89_CHANNEL_WIDTH_20:
1771 rtw89_phy_fill_txpwr_limit_20m(rtwdev, lmt, band, ntx, ch);
1772 break;
1773 case RTW89_CHANNEL_WIDTH_40:
1774 rtw89_phy_fill_txpwr_limit_40m(rtwdev, lmt, band, ntx, ch,
1775 pri_ch);
1776 break;
1777 case RTW89_CHANNEL_WIDTH_80:
1778 rtw89_phy_fill_txpwr_limit_80m(rtwdev, lmt, band, ntx, ch,
1779 pri_ch);
1780 break;
1781 case RTW89_CHANNEL_WIDTH_160:
1782 rtw89_phy_fill_txpwr_limit_160m(rtwdev, lmt, band, ntx, ch,
1783 pri_ch);
1784 break;
1785 }
1786 }
1787 EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit);
1788
rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev * rtwdev,u8 band,u8 ru,u8 ntx,u8 ch)1789 static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band,
1790 u8 ru, u8 ntx, u8 ch)
1791 {
1792 const struct rtw89_chip_info *chip = rtwdev->chip;
1793 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
1794 u8 regd = rtw89_regd_get(rtwdev, band);
1795 s8 lmt_ru = 0, sar;
1796
1797 switch (band) {
1798 case RTW89_BAND_2G:
1799 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx][regd][ch_idx];
1800 if (!lmt_ru)
1801 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx]
1802 [RTW89_WW][ch_idx];
1803 break;
1804 case RTW89_BAND_5G:
1805 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx][regd][ch_idx];
1806 if (!lmt_ru)
1807 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx]
1808 [RTW89_WW][ch_idx];
1809 break;
1810 case RTW89_BAND_6G:
1811 lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx][regd][ch_idx];
1812 if (!lmt_ru)
1813 lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx]
1814 [RTW89_WW][ch_idx];
1815 break;
1816 default:
1817 rtw89_warn(rtwdev, "unknown band type: %d\n", band);
1818 return 0;
1819 }
1820
1821 lmt_ru = _phy_txpwr_rf_to_mac(rtwdev, lmt_ru);
1822 sar = rtw89_query_sar(rtwdev);
1823
1824 return min(lmt_ru, sar);
1825 }
1826
1827 static void
rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru * lmt_ru,u8 band,u8 ntx,u8 ch)1828 rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev *rtwdev,
1829 struct rtw89_txpwr_limit_ru *lmt_ru,
1830 u8 band, u8 ntx, u8 ch)
1831 {
1832 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1833 RTW89_RU26,
1834 ntx, ch);
1835 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1836 RTW89_RU52,
1837 ntx, ch);
1838 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1839 RTW89_RU106,
1840 ntx, ch);
1841 }
1842
1843 static void
rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru * lmt_ru,u8 band,u8 ntx,u8 ch)1844 rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev *rtwdev,
1845 struct rtw89_txpwr_limit_ru *lmt_ru,
1846 u8 band, u8 ntx, u8 ch)
1847 {
1848 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1849 RTW89_RU26,
1850 ntx, ch - 2);
1851 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1852 RTW89_RU26,
1853 ntx, ch + 2);
1854 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1855 RTW89_RU52,
1856 ntx, ch - 2);
1857 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1858 RTW89_RU52,
1859 ntx, ch + 2);
1860 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1861 RTW89_RU106,
1862 ntx, ch - 2);
1863 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1864 RTW89_RU106,
1865 ntx, ch + 2);
1866 }
1867
1868 static void
rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru * lmt_ru,u8 band,u8 ntx,u8 ch)1869 rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev *rtwdev,
1870 struct rtw89_txpwr_limit_ru *lmt_ru,
1871 u8 band, u8 ntx, u8 ch)
1872 {
1873 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1874 RTW89_RU26,
1875 ntx, ch - 6);
1876 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1877 RTW89_RU26,
1878 ntx, ch - 2);
1879 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1880 RTW89_RU26,
1881 ntx, ch + 2);
1882 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1883 RTW89_RU26,
1884 ntx, ch + 6);
1885 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1886 RTW89_RU52,
1887 ntx, ch - 6);
1888 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1889 RTW89_RU52,
1890 ntx, ch - 2);
1891 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1892 RTW89_RU52,
1893 ntx, ch + 2);
1894 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1895 RTW89_RU52,
1896 ntx, ch + 6);
1897 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1898 RTW89_RU106,
1899 ntx, ch - 6);
1900 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1901 RTW89_RU106,
1902 ntx, ch - 2);
1903 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1904 RTW89_RU106,
1905 ntx, ch + 2);
1906 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1907 RTW89_RU106,
1908 ntx, ch + 6);
1909 }
1910
1911 static void
rtw89_phy_fill_txpwr_limit_ru_160m(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru * lmt_ru,u8 band,u8 ntx,u8 ch)1912 rtw89_phy_fill_txpwr_limit_ru_160m(struct rtw89_dev *rtwdev,
1913 struct rtw89_txpwr_limit_ru *lmt_ru,
1914 u8 band, u8 ntx, u8 ch)
1915 {
1916 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 };
1917 int i;
1918
1919 #if defined(__linux__)
1920 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM);
1921 #elif defined(__FreeBSD__)
1922 rtw89_static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM);
1923 #endif
1924 for (i = 0; i < RTW89_RU_SEC_NUM; i++) {
1925 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1926 RTW89_RU26,
1927 ntx,
1928 ch + ofst[i]);
1929 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1930 RTW89_RU52,
1931 ntx,
1932 ch + ofst[i]);
1933 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
1934 RTW89_RU106,
1935 ntx,
1936 ch + ofst[i]);
1937 }
1938 }
1939
rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,struct rtw89_txpwr_limit_ru * lmt_ru,u8 ntx)1940 void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev,
1941 const struct rtw89_chan *chan,
1942 struct rtw89_txpwr_limit_ru *lmt_ru,
1943 u8 ntx)
1944 {
1945 u8 band = chan->band_type;
1946 u8 ch = chan->channel;
1947 u8 bw = chan->band_width;
1948
1949 memset(lmt_ru, 0, sizeof(*lmt_ru));
1950
1951 switch (bw) {
1952 case RTW89_CHANNEL_WIDTH_20:
1953 rtw89_phy_fill_txpwr_limit_ru_20m(rtwdev, lmt_ru, band, ntx,
1954 ch);
1955 break;
1956 case RTW89_CHANNEL_WIDTH_40:
1957 rtw89_phy_fill_txpwr_limit_ru_40m(rtwdev, lmt_ru, band, ntx,
1958 ch);
1959 break;
1960 case RTW89_CHANNEL_WIDTH_80:
1961 rtw89_phy_fill_txpwr_limit_ru_80m(rtwdev, lmt_ru, band, ntx,
1962 ch);
1963 break;
1964 case RTW89_CHANNEL_WIDTH_160:
1965 rtw89_phy_fill_txpwr_limit_ru_160m(rtwdev, lmt_ru, band, ntx,
1966 ch);
1967 break;
1968 }
1969 }
1970 EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit_ru);
1971
1972 struct rtw89_phy_iter_ra_data {
1973 struct rtw89_dev *rtwdev;
1974 struct sk_buff *c2h;
1975 };
1976
rtw89_phy_c2h_ra_rpt_iter(void * data,struct ieee80211_sta * sta)1977 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta)
1978 {
1979 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data;
1980 struct rtw89_dev *rtwdev = ra_data->rtwdev;
1981 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
1982 struct rtw89_ra_report *ra_report = &rtwsta->ra_report;
1983 struct sk_buff *c2h = ra_data->c2h;
1984 u8 mode, rate, bw, giltf, mac_id;
1985 u16 legacy_bitrate;
1986 bool valid;
1987 u8 mcs = 0;
1988
1989 mac_id = RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h->data);
1990 if (mac_id != rtwsta->mac_id)
1991 return;
1992
1993 rate = RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h->data);
1994 bw = RTW89_GET_PHY_C2H_RA_RPT_BW(c2h->data);
1995 giltf = RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h->data);
1996 mode = RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h->data);
1997
1998 if (mode == RTW89_RA_RPT_MODE_LEGACY) {
1999 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate);
2000 if (!valid)
2001 return;
2002 }
2003
2004 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate));
2005
2006 switch (mode) {
2007 case RTW89_RA_RPT_MODE_LEGACY:
2008 ra_report->txrate.legacy = legacy_bitrate;
2009 break;
2010 case RTW89_RA_RPT_MODE_HT:
2011 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS;
2012 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw))
2013 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate),
2014 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate));
2015 else
2016 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate);
2017 ra_report->txrate.mcs = rate;
2018 if (giltf)
2019 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
2020 mcs = ra_report->txrate.mcs & 0x07;
2021 break;
2022 case RTW89_RA_RPT_MODE_VHT:
2023 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS;
2024 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate);
2025 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1;
2026 if (giltf)
2027 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
2028 mcs = ra_report->txrate.mcs;
2029 break;
2030 case RTW89_RA_RPT_MODE_HE:
2031 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS;
2032 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate);
2033 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1;
2034 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08)
2035 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8;
2036 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16)
2037 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6;
2038 else
2039 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2;
2040 mcs = ra_report->txrate.mcs;
2041 break;
2042 }
2043
2044 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw);
2045 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate);
2046 ra_report->hw_rate = FIELD_PREP(RTW89_HW_RATE_MASK_MOD, mode) |
2047 FIELD_PREP(RTW89_HW_RATE_MASK_VAL, rate);
2048 ra_report->might_fallback_legacy = mcs <= 2;
2049 sta->max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report);
2050 rtwsta->max_agg_wait = sta->max_rc_amsdu_len / 1500 - 1;
2051 }
2052
2053 static void
rtw89_phy_c2h_ra_rpt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)2054 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
2055 {
2056 struct rtw89_phy_iter_ra_data ra_data;
2057
2058 ra_data.rtwdev = rtwdev;
2059 ra_data.c2h = c2h;
2060 ieee80211_iterate_stations_atomic(rtwdev->hw,
2061 rtw89_phy_c2h_ra_rpt_iter,
2062 &ra_data);
2063 }
2064
2065 static
2066 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev,
2067 struct sk_buff *c2h, u32 len) = {
2068 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt,
2069 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL,
2070 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL,
2071 };
2072
rtw89_phy_c2h_handle(struct rtw89_dev * rtwdev,struct sk_buff * skb,u32 len,u8 class,u8 func)2073 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
2074 u32 len, u8 class, u8 func)
2075 {
2076 void (*handler)(struct rtw89_dev *rtwdev,
2077 struct sk_buff *c2h, u32 len) = NULL;
2078
2079 switch (class) {
2080 case RTW89_PHY_C2H_CLASS_RA:
2081 if (func < RTW89_PHY_C2H_FUNC_RA_MAX)
2082 handler = rtw89_phy_c2h_ra_handler[func];
2083 break;
2084 default:
2085 rtw89_info(rtwdev, "c2h class %d not support\n", class);
2086 return;
2087 }
2088 if (!handler) {
2089 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class,
2090 func);
2091 return;
2092 }
2093 handler(rtwdev, skb, len);
2094 }
2095
rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev * rtwdev,bool sc_xo)2096 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo)
2097 {
2098 u32 reg_mask;
2099
2100 if (sc_xo)
2101 reg_mask = B_AX_XTAL_SC_XO_MASK;
2102 else
2103 reg_mask = B_AX_XTAL_SC_XI_MASK;
2104
2105 return (u8)rtw89_read32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask);
2106 }
2107
rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev * rtwdev,bool sc_xo,u8 val)2108 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo,
2109 u8 val)
2110 {
2111 u32 reg_mask;
2112
2113 if (sc_xo)
2114 reg_mask = B_AX_XTAL_SC_XO_MASK;
2115 else
2116 reg_mask = B_AX_XTAL_SC_XI_MASK;
2117
2118 rtw89_write32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask, val);
2119 }
2120
rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev * rtwdev,u8 crystal_cap,bool force)2121 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev,
2122 u8 crystal_cap, bool force)
2123 {
2124 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2125 const struct rtw89_chip_info *chip = rtwdev->chip;
2126 u8 sc_xi_val, sc_xo_val;
2127
2128 if (!force && cfo->crystal_cap == crystal_cap)
2129 return;
2130 crystal_cap = clamp_t(u8, crystal_cap, 0, 127);
2131 if (chip->chip_id == RTL8852A) {
2132 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap);
2133 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap);
2134 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true);
2135 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false);
2136 } else {
2137 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO,
2138 crystal_cap, XTAL_SC_XO_MASK);
2139 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI,
2140 crystal_cap, XTAL_SC_XI_MASK);
2141 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val);
2142 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val);
2143 }
2144 cfo->crystal_cap = sc_xi_val;
2145 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap);
2146
2147 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val);
2148 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val);
2149 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n",
2150 cfo->x_cap_ofst);
2151 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n");
2152 }
2153
rtw89_phy_cfo_reset(struct rtw89_dev * rtwdev)2154 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev)
2155 {
2156 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2157 u8 cap;
2158
2159 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK;
2160 cfo->is_adjust = false;
2161 if (cfo->crystal_cap == cfo->def_x_cap)
2162 return;
2163 cap = cfo->crystal_cap;
2164 cap += (cap > cfo->def_x_cap ? -1 : 1);
2165 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false);
2166 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2167 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap,
2168 cfo->def_x_cap);
2169 }
2170
rtw89_dcfo_comp(struct rtw89_dev * rtwdev,s32 curr_cfo)2171 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo)
2172 {
2173 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp;
2174 bool is_linked = rtwdev->total_sta_assoc > 0;
2175 s32 cfo_avg_312;
2176 s32 dcfo_comp_val;
2177 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft;
2178 int sign;
2179
2180 if (!is_linked) {
2181 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n",
2182 is_linked);
2183 return;
2184 }
2185 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo);
2186 if (curr_cfo == 0)
2187 return;
2188 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO);
2189 sign = curr_cfo > 0 ? 1 : -1;
2190 cfo_avg_312 = (curr_cfo << dcfo_comp_sft) / 5 + sign * dcfo_comp_val;
2191 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: avg_cfo=%d\n", cfo_avg_312);
2192 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV)
2193 cfo_avg_312 = -cfo_avg_312;
2194 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask,
2195 cfo_avg_312);
2196 }
2197
rtw89_dcfo_comp_init(struct rtw89_dev * rtwdev)2198 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev)
2199 {
2200 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_OPT, B_DCFO_OPT_EN, 1);
2201 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_WEIGHT, B_DCFO_WEIGHT_MSK, 8);
2202 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, B_AX_PWR_UL_CFO_MASK);
2203 }
2204
rtw89_phy_cfo_init(struct rtw89_dev * rtwdev)2205 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev)
2206 {
2207 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2208 struct rtw89_efuse *efuse = &rtwdev->efuse;
2209
2210 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK;
2211 cfo->crystal_cap = cfo->crystal_cap_default;
2212 cfo->def_x_cap = cfo->crystal_cap;
2213 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f);
2214 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1);
2215 cfo->is_adjust = false;
2216 cfo->divergence_lock_en = false;
2217 cfo->x_cap_ofst = 0;
2218 cfo->lock_cnt = 0;
2219 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE;
2220 cfo->apply_compensation = false;
2221 cfo->residual_cfo_acc = 0;
2222 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n",
2223 cfo->crystal_cap_default);
2224 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true);
2225 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1);
2226 rtw89_dcfo_comp_init(rtwdev);
2227 cfo->cfo_timer_ms = 2000;
2228 cfo->cfo_trig_by_timer_en = false;
2229 cfo->phy_cfo_trk_cnt = 0;
2230 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
2231 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE;
2232 }
2233
rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev * rtwdev,s32 curr_cfo)2234 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev,
2235 s32 curr_cfo)
2236 {
2237 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2238 s8 crystal_cap = cfo->crystal_cap;
2239 s32 cfo_abs = abs(curr_cfo);
2240 int sign;
2241
2242 if (!cfo->is_adjust) {
2243 if (cfo_abs > CFO_TRK_ENABLE_TH)
2244 cfo->is_adjust = true;
2245 } else {
2246 if (cfo_abs < CFO_TRK_STOP_TH)
2247 cfo->is_adjust = false;
2248 }
2249 if (!cfo->is_adjust) {
2250 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n");
2251 return;
2252 }
2253 sign = curr_cfo > 0 ? 1 : -1;
2254 if (cfo_abs > CFO_TRK_STOP_TH_4)
2255 crystal_cap += 7 * sign;
2256 else if (cfo_abs > CFO_TRK_STOP_TH_3)
2257 crystal_cap += 5 * sign;
2258 else if (cfo_abs > CFO_TRK_STOP_TH_2)
2259 crystal_cap += 3 * sign;
2260 else if (cfo_abs > CFO_TRK_STOP_TH_1)
2261 crystal_cap += 1 * sign;
2262 else
2263 return;
2264 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false);
2265 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2266 "X_cap{Curr,Default}={0x%x,0x%x}\n",
2267 cfo->crystal_cap, cfo->def_x_cap);
2268 }
2269
rtw89_phy_average_cfo_calc(struct rtw89_dev * rtwdev)2270 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev)
2271 {
2272 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2273 s32 cfo_khz_all = 0;
2274 s32 cfo_cnt_all = 0;
2275 s32 cfo_all_avg = 0;
2276 u8 i;
2277
2278 if (rtwdev->total_sta_assoc != 1)
2279 return 0;
2280 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n");
2281 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
2282 if (cfo->cfo_cnt[i] == 0)
2283 continue;
2284 cfo_khz_all += cfo->cfo_tail[i];
2285 cfo_cnt_all += cfo->cfo_cnt[i];
2286 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all);
2287 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i];
2288 }
2289 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2290 "CFO track for macid = %d\n", i);
2291 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2292 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n",
2293 cfo_khz_all, cfo_cnt_all, cfo_all_avg);
2294 return cfo_all_avg;
2295 }
2296
rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev * rtwdev)2297 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev)
2298 {
2299 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2300 struct rtw89_traffic_stats *stats = &rtwdev->stats;
2301 s32 target_cfo = 0;
2302 s32 cfo_khz_all = 0;
2303 s32 cfo_khz_all_tp_wgt = 0;
2304 s32 cfo_avg = 0;
2305 s32 max_cfo_lb = BIT(31);
2306 s32 min_cfo_ub = GENMASK(30, 0);
2307 u16 cfo_cnt_all = 0;
2308 u8 active_entry_cnt = 0;
2309 u8 sta_cnt = 0;
2310 u32 tp_all = 0;
2311 u8 i;
2312 u8 cfo_tol = 0;
2313
2314 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n");
2315 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) {
2316 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n");
2317 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
2318 if (cfo->cfo_cnt[i] == 0)
2319 continue;
2320 cfo_khz_all += cfo->cfo_tail[i];
2321 cfo_cnt_all += cfo->cfo_cnt[i];
2322 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all);
2323 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2324 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n",
2325 cfo_khz_all, cfo_cnt_all, cfo_avg);
2326 target_cfo = cfo_avg;
2327 }
2328 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) {
2329 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n");
2330 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
2331 if (cfo->cfo_cnt[i] == 0)
2332 continue;
2333 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i],
2334 (s32)cfo->cfo_cnt[i]);
2335 cfo_khz_all += cfo->cfo_avg[i];
2336 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2337 "Macid=%d, cfo_avg=%d\n", i,
2338 cfo->cfo_avg[i]);
2339 }
2340 sta_cnt = rtwdev->total_sta_assoc;
2341 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt);
2342 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2343 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n",
2344 cfo_khz_all, sta_cnt, cfo_avg);
2345 target_cfo = cfo_avg;
2346 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) {
2347 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n");
2348 cfo_tol = cfo->sta_cfo_tolerance;
2349 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
2350 sta_cnt++;
2351 if (cfo->cfo_cnt[i] != 0) {
2352 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i],
2353 (s32)cfo->cfo_cnt[i]);
2354 active_entry_cnt++;
2355 } else {
2356 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i];
2357 }
2358 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb);
2359 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub);
2360 cfo_khz_all += cfo->cfo_avg[i];
2361 /* need tp for each entry */
2362 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2363 "[%d] cfo_avg=%d, tp=tbd\n",
2364 i, cfo->cfo_avg[i]);
2365 if (sta_cnt >= rtwdev->total_sta_assoc)
2366 break;
2367 }
2368 tp_all = stats->rx_throughput; /* need tp for each entry */
2369 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all);
2370
2371 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n",
2372 sta_cnt);
2373 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n",
2374 active_entry_cnt);
2375 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2376 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n",
2377 cfo_khz_all_tp_wgt, cfo_avg);
2378 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n",
2379 max_cfo_lb, min_cfo_ub);
2380 if (max_cfo_lb <= min_cfo_ub) {
2381 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2382 "cfo win_size=%d\n",
2383 min_cfo_ub - max_cfo_lb);
2384 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub);
2385 } else {
2386 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2387 "No intersection of cfo tolerance windows\n");
2388 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt);
2389 }
2390 for (i = 0; i < CFO_TRACK_MAX_USER; i++)
2391 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i];
2392 }
2393 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo);
2394 return target_cfo;
2395 }
2396
rtw89_phy_cfo_statistics_reset(struct rtw89_dev * rtwdev)2397 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev)
2398 {
2399 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2400
2401 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail));
2402 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt));
2403 cfo->packet_count = 0;
2404 cfo->packet_count_pre = 0;
2405 cfo->cfo_avg_pre = 0;
2406 }
2407
rtw89_phy_cfo_dm(struct rtw89_dev * rtwdev)2408 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev)
2409 {
2410 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2411 s32 new_cfo = 0;
2412 bool x_cap_update = false;
2413 u8 pre_x_cap = cfo->crystal_cap;
2414
2415 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n",
2416 rtwdev->total_sta_assoc);
2417 if (rtwdev->total_sta_assoc == 0) {
2418 rtw89_phy_cfo_reset(rtwdev);
2419 return;
2420 }
2421 if (cfo->packet_count == 0) {
2422 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n");
2423 return;
2424 }
2425 if (cfo->packet_count == cfo->packet_count_pre) {
2426 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n");
2427 return;
2428 }
2429 if (rtwdev->total_sta_assoc == 1)
2430 new_cfo = rtw89_phy_average_cfo_calc(rtwdev);
2431 else
2432 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev);
2433 if (new_cfo == 0) {
2434 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n");
2435 return;
2436 }
2437 if (cfo->divergence_lock_en) {
2438 cfo->lock_cnt++;
2439 if (cfo->lock_cnt > CFO_PERIOD_CNT) {
2440 cfo->divergence_lock_en = false;
2441 cfo->lock_cnt = 0;
2442 } else {
2443 rtw89_phy_cfo_reset(rtwdev);
2444 }
2445 return;
2446 }
2447 if (cfo->crystal_cap >= cfo->x_cap_ub ||
2448 cfo->crystal_cap <= cfo->x_cap_lb) {
2449 cfo->divergence_lock_en = true;
2450 rtw89_phy_cfo_reset(rtwdev);
2451 return;
2452 }
2453
2454 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo);
2455 cfo->cfo_avg_pre = new_cfo;
2456 x_cap_update = cfo->crystal_cap != pre_x_cap;
2457 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update);
2458 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n",
2459 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap,
2460 cfo->x_cap_ofst);
2461 if (x_cap_update) {
2462 if (new_cfo > 0)
2463 new_cfo -= CFO_SW_COMP_FINE_TUNE;
2464 else
2465 new_cfo += CFO_SW_COMP_FINE_TUNE;
2466 }
2467 rtw89_dcfo_comp(rtwdev, new_cfo);
2468 rtw89_phy_cfo_statistics_reset(rtwdev);
2469 }
2470
rtw89_phy_cfo_track_work(struct work_struct * work)2471 void rtw89_phy_cfo_track_work(struct work_struct *work)
2472 {
2473 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
2474 cfo_track_work.work);
2475 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2476
2477 mutex_lock(&rtwdev->mutex);
2478 if (!cfo->cfo_trig_by_timer_en)
2479 goto out;
2480 rtw89_leave_ps_mode(rtwdev);
2481 rtw89_phy_cfo_dm(rtwdev);
2482 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work,
2483 msecs_to_jiffies(cfo->cfo_timer_ms));
2484 out:
2485 mutex_unlock(&rtwdev->mutex);
2486 }
2487
rtw89_phy_cfo_start_work(struct rtw89_dev * rtwdev)2488 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev)
2489 {
2490 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2491
2492 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work,
2493 msecs_to_jiffies(cfo->cfo_timer_ms));
2494 }
2495
rtw89_phy_cfo_track(struct rtw89_dev * rtwdev)2496 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev)
2497 {
2498 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2499 struct rtw89_traffic_stats *stats = &rtwdev->stats;
2500 bool is_ul_ofdma = false, ofdma_acc_en = false;
2501
2502 if (stats->rx_tf_periodic > CFO_TF_CNT_TH)
2503 is_ul_ofdma = true;
2504 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE &&
2505 is_ul_ofdma)
2506 ofdma_acc_en = true;
2507
2508 switch (cfo->phy_cfo_status) {
2509 case RTW89_PHY_DCFO_STATE_NORMAL:
2510 if (stats->tx_throughput >= CFO_TP_UPPER) {
2511 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE;
2512 cfo->cfo_trig_by_timer_en = true;
2513 cfo->cfo_timer_ms = CFO_COMP_PERIOD;
2514 rtw89_phy_cfo_start_work(rtwdev);
2515 }
2516 break;
2517 case RTW89_PHY_DCFO_STATE_ENHANCE:
2518 if (stats->tx_throughput <= CFO_TP_LOWER)
2519 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
2520 else if (ofdma_acc_en &&
2521 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT)
2522 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD;
2523 else
2524 cfo->phy_cfo_trk_cnt++;
2525
2526 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) {
2527 cfo->phy_cfo_trk_cnt = 0;
2528 cfo->cfo_trig_by_timer_en = false;
2529 }
2530 break;
2531 case RTW89_PHY_DCFO_STATE_HOLD:
2532 if (stats->tx_throughput <= CFO_TP_LOWER) {
2533 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
2534 cfo->phy_cfo_trk_cnt = 0;
2535 cfo->cfo_trig_by_timer_en = false;
2536 } else {
2537 cfo->phy_cfo_trk_cnt++;
2538 }
2539 break;
2540 default:
2541 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
2542 cfo->phy_cfo_trk_cnt = 0;
2543 break;
2544 }
2545 rtw89_debug(rtwdev, RTW89_DBG_CFO,
2546 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n",
2547 stats->tx_throughput, cfo->phy_cfo_status,
2548 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt,
2549 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0]));
2550 if (cfo->cfo_trig_by_timer_en)
2551 return;
2552 rtw89_phy_cfo_dm(rtwdev);
2553 }
2554
rtw89_phy_cfo_parse(struct rtw89_dev * rtwdev,s16 cfo_val,struct rtw89_rx_phy_ppdu * phy_ppdu)2555 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val,
2556 struct rtw89_rx_phy_ppdu *phy_ppdu)
2557 {
2558 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
2559 u8 macid = phy_ppdu->mac_id;
2560
2561 if (macid >= CFO_TRACK_MAX_USER) {
2562 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid);
2563 return;
2564 }
2565
2566 cfo->cfo_tail[macid] += cfo_val;
2567 cfo->cfo_cnt[macid]++;
2568 cfo->packet_count++;
2569 }
2570
rtw89_phy_stat_thermal_update(struct rtw89_dev * rtwdev)2571 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev)
2572 {
2573 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
2574 int i;
2575 u8 th;
2576
2577 for (i = 0; i < rtwdev->chip->rf_path_num; i++) {
2578 th = rtw89_chip_get_thermal(rtwdev, i);
2579 if (th)
2580 ewma_thermal_add(&phystat->avg_thermal[i], th);
2581
2582 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
2583 "path(%d) thermal cur=%u avg=%ld", i, th,
2584 ewma_thermal_read(&phystat->avg_thermal[i]));
2585 }
2586 }
2587
2588 struct rtw89_phy_iter_rssi_data {
2589 struct rtw89_dev *rtwdev;
2590 struct rtw89_phy_ch_info *ch_info;
2591 bool rssi_changed;
2592 };
2593
rtw89_phy_stat_rssi_update_iter(void * data,struct ieee80211_sta * sta)2594 static void rtw89_phy_stat_rssi_update_iter(void *data,
2595 struct ieee80211_sta *sta)
2596 {
2597 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
2598 struct rtw89_phy_iter_rssi_data *rssi_data =
2599 (struct rtw89_phy_iter_rssi_data *)data;
2600 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info;
2601 unsigned long rssi_curr;
2602
2603 rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi);
2604
2605 if (rssi_curr < ch_info->rssi_min) {
2606 ch_info->rssi_min = rssi_curr;
2607 ch_info->rssi_min_macid = rtwsta->mac_id;
2608 }
2609
2610 if (rtwsta->prev_rssi == 0) {
2611 rtwsta->prev_rssi = rssi_curr;
2612 } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) {
2613 rtwsta->prev_rssi = rssi_curr;
2614 rssi_data->rssi_changed = true;
2615 }
2616 }
2617
rtw89_phy_stat_rssi_update(struct rtw89_dev * rtwdev)2618 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev)
2619 {
2620 struct rtw89_phy_iter_rssi_data rssi_data = {0};
2621
2622 rssi_data.rtwdev = rtwdev;
2623 rssi_data.ch_info = &rtwdev->ch_info;
2624 rssi_data.ch_info->rssi_min = U8_MAX;
2625 ieee80211_iterate_stations_atomic(rtwdev->hw,
2626 rtw89_phy_stat_rssi_update_iter,
2627 &rssi_data);
2628 if (rssi_data.rssi_changed)
2629 rtw89_btc_ntfy_wl_sta(rtwdev);
2630 }
2631
rtw89_phy_stat_init(struct rtw89_dev * rtwdev)2632 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev)
2633 {
2634 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
2635 int i;
2636
2637 for (i = 0; i < rtwdev->chip->rf_path_num; i++)
2638 ewma_thermal_init(&phystat->avg_thermal[i]);
2639
2640 rtw89_phy_stat_thermal_update(rtwdev);
2641
2642 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat));
2643 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat));
2644 }
2645
rtw89_phy_stat_track(struct rtw89_dev * rtwdev)2646 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev)
2647 {
2648 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
2649
2650 rtw89_phy_stat_thermal_update(rtwdev);
2651 rtw89_phy_stat_rssi_update(rtwdev);
2652
2653 phystat->last_pkt_stat = phystat->cur_pkt_stat;
2654 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat));
2655 }
2656
rtw89_phy_ccx_us_to_idx(struct rtw89_dev * rtwdev,u32 time_us)2657 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us)
2658 {
2659 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2660
2661 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx);
2662 }
2663
rtw89_phy_ccx_idx_to_us(struct rtw89_dev * rtwdev,u16 idx)2664 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx)
2665 {
2666 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2667
2668 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx);
2669 }
2670
rtw89_phy_ccx_top_setting_init(struct rtw89_dev * rtwdev)2671 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev)
2672 {
2673 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2674
2675 env->ccx_manual_ctrl = false;
2676 env->ccx_ongoing = false;
2677 env->ccx_rac_lv = RTW89_RAC_RELEASE;
2678 env->ccx_rpt_stamp = 0;
2679 env->ccx_period = 0;
2680 env->ccx_unit_idx = RTW89_CCX_32_US;
2681 env->ccx_trigger_time = 0;
2682 env->ccx_edcca_opt_bw_idx = RTW89_CCX_EDCCA_BW20_0;
2683
2684 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EN_MSK, 1);
2685 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_TRIG_OPT_MSK, 1);
2686 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1);
2687 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EDCCA_OPT_MSK,
2688 RTW89_CCX_EDCCA_BW20_0);
2689 }
2690
rtw89_phy_ccx_get_report(struct rtw89_dev * rtwdev,u16 report,u16 score)2691 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report,
2692 u16 score)
2693 {
2694 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2695 u32 numer = 0;
2696 u16 ret = 0;
2697
2698 numer = report * score + (env->ccx_period >> 1);
2699 if (env->ccx_period)
2700 ret = numer / env->ccx_period;
2701
2702 return ret >= score ? score - 1 : ret;
2703 }
2704
rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev * rtwdev,u16 time_ms,u32 * period,u32 * unit_idx)2705 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev,
2706 u16 time_ms, u32 *period,
2707 u32 *unit_idx)
2708 {
2709 u32 idx;
2710 u8 quotient;
2711
2712 if (time_ms >= CCX_MAX_PERIOD)
2713 time_ms = CCX_MAX_PERIOD;
2714
2715 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD;
2716
2717 if (quotient < 4)
2718 idx = RTW89_CCX_4_US;
2719 else if (quotient < 8)
2720 idx = RTW89_CCX_8_US;
2721 else if (quotient < 16)
2722 idx = RTW89_CCX_16_US;
2723 else
2724 idx = RTW89_CCX_32_US;
2725
2726 *unit_idx = idx;
2727 *period = (time_ms * MS_TO_4US_RATIO) >> idx;
2728
2729 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2730 "[Trigger Time] period:%d, unit_idx:%d\n",
2731 *period, *unit_idx);
2732 }
2733
rtw89_phy_ccx_racing_release(struct rtw89_dev * rtwdev)2734 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev)
2735 {
2736 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2737
2738 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2739 "lv:(%d)->(0)\n", env->ccx_rac_lv);
2740
2741 env->ccx_ongoing = false;
2742 env->ccx_rac_lv = RTW89_RAC_RELEASE;
2743 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
2744 }
2745
rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev * rtwdev,struct rtw89_ccx_para_info * para)2746 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev,
2747 struct rtw89_ccx_para_info *para)
2748 {
2749 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2750 bool is_update = env->ifs_clm_app != para->ifs_clm_app;
2751 u8 i = 0;
2752 u16 *ifs_th_l = env->ifs_clm_th_l;
2753 u16 *ifs_th_h = env->ifs_clm_th_h;
2754 u32 ifs_th0_us = 0, ifs_th_times = 0;
2755 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0};
2756
2757 if (!is_update)
2758 goto ifs_update_finished;
2759
2760 switch (para->ifs_clm_app) {
2761 case RTW89_IFS_CLM_INIT:
2762 case RTW89_IFS_CLM_BACKGROUND:
2763 case RTW89_IFS_CLM_ACS:
2764 case RTW89_IFS_CLM_DBG:
2765 case RTW89_IFS_CLM_DIG:
2766 case RTW89_IFS_CLM_TDMA_DIG:
2767 ifs_th0_us = IFS_CLM_TH0_UPPER;
2768 ifs_th_times = IFS_CLM_TH_MUL;
2769 break;
2770 case RTW89_IFS_CLM_DBG_MANUAL:
2771 ifs_th0_us = para->ifs_clm_manual_th0;
2772 ifs_th_times = para->ifs_clm_manual_th_times;
2773 break;
2774 default:
2775 break;
2776 }
2777
2778 /* Set sampling threshold for 4 different regions, unit in idx_cnt.
2779 * low[i] = high[i-1] + 1
2780 * high[i] = high[i-1] * ifs_th_times
2781 */
2782 ifs_th_l[IFS_CLM_TH_START_IDX] = 0;
2783 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us;
2784 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev,
2785 ifs_th0_us);
2786 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) {
2787 ifs_th_l[i] = ifs_th_h[i - 1] + 1;
2788 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times;
2789 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]);
2790 }
2791
2792 ifs_update_finished:
2793 if (!is_update)
2794 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2795 "No need to update IFS_TH\n");
2796
2797 return is_update;
2798 }
2799
rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev * rtwdev)2800 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev)
2801 {
2802 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2803 u8 i = 0;
2804
2805 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_LOW_MSK,
2806 env->ifs_clm_th_l[0]);
2807 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_LOW_MSK,
2808 env->ifs_clm_th_l[1]);
2809 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_LOW_MSK,
2810 env->ifs_clm_th_l[2]);
2811 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_LOW_MSK,
2812 env->ifs_clm_th_l[3]);
2813
2814 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_HIGH_MSK,
2815 env->ifs_clm_th_h[0]);
2816 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_HIGH_MSK,
2817 env->ifs_clm_th_h[1]);
2818 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_HIGH_MSK,
2819 env->ifs_clm_th_h[2]);
2820 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_HIGH_MSK,
2821 env->ifs_clm_th_h[3]);
2822
2823 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
2824 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2825 "Update IFS_T%d_th{low, high} : {%d, %d}\n",
2826 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]);
2827 }
2828
rtw89_phy_ifs_clm_setting_init(struct rtw89_dev * rtwdev)2829 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev)
2830 {
2831 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2832 struct rtw89_ccx_para_info para = {0};
2833
2834 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
2835 env->ifs_clm_mntr_time = 0;
2836
2837 para.ifs_clm_app = RTW89_IFS_CLM_INIT;
2838 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶))
2839 rtw89_phy_ifs_clm_set_th_reg(rtwdev);
2840
2841 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COLLECT_EN,
2842 true);
2843 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_EN_MSK, true);
2844 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_EN_MSK, true);
2845 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_EN_MSK, true);
2846 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_EN_MSK, true);
2847 }
2848
rtw89_phy_ccx_racing_ctrl(struct rtw89_dev * rtwdev,enum rtw89_env_racing_lv level)2849 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev,
2850 enum rtw89_env_racing_lv level)
2851 {
2852 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2853 int ret = 0;
2854
2855 if (level >= RTW89_RAC_MAX_NUM) {
2856 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2857 "[WARNING] Wrong LV=%d\n", level);
2858 return -EINVAL;
2859 }
2860
2861 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2862 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing,
2863 env->ccx_rac_lv, level);
2864
2865 if (env->ccx_ongoing) {
2866 if (level <= env->ccx_rac_lv)
2867 ret = -EINVAL;
2868 else
2869 env->ccx_ongoing = false;
2870 }
2871
2872 if (ret == 0)
2873 env->ccx_rac_lv = level;
2874
2875 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n",
2876 !ret);
2877
2878 return ret;
2879 }
2880
rtw89_phy_ccx_trigger(struct rtw89_dev * rtwdev)2881 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev)
2882 {
2883 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2884
2885 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 0);
2886 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 0);
2887 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 1);
2888 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1);
2889
2890 env->ccx_rpt_stamp++;
2891 env->ccx_ongoing = true;
2892 }
2893
rtw89_phy_ifs_clm_get_utility(struct rtw89_dev * rtwdev)2894 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev)
2895 {
2896 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2897 u8 i = 0;
2898 u32 res = 0;
2899
2900 env->ifs_clm_tx_ratio =
2901 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT);
2902 env->ifs_clm_edcca_excl_cca_ratio =
2903 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca,
2904 PERCENT);
2905 env->ifs_clm_cck_fa_ratio =
2906 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT);
2907 env->ifs_clm_ofdm_fa_ratio =
2908 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT);
2909 env->ifs_clm_cck_cca_excl_fa_ratio =
2910 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa,
2911 PERCENT);
2912 env->ifs_clm_ofdm_cca_excl_fa_ratio =
2913 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa,
2914 PERCENT);
2915 env->ifs_clm_cck_fa_permil =
2916 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL);
2917 env->ifs_clm_ofdm_fa_permil =
2918 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL);
2919
2920 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) {
2921 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) {
2922 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD;
2923 } else {
2924 env->ifs_clm_ifs_avg[i] =
2925 rtw89_phy_ccx_idx_to_us(rtwdev,
2926 env->ifs_clm_avg[i]);
2927 }
2928
2929 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]);
2930 res += env->ifs_clm_his[i] >> 1;
2931 if (env->ifs_clm_his[i])
2932 res /= env->ifs_clm_his[i];
2933 else
2934 res = 0;
2935 env->ifs_clm_cca_avg[i] = res;
2936 }
2937
2938 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2939 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n",
2940 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio);
2941 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2942 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n",
2943 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio);
2944 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2945 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n",
2946 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil);
2947 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2948 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n",
2949 env->ifs_clm_cck_cca_excl_fa_ratio,
2950 env->ifs_clm_ofdm_cca_excl_fa_ratio);
2951 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2952 "Time:[his, ifs_avg(us), cca_avg(us)]\n");
2953 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
2954 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n",
2955 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i],
2956 env->ifs_clm_cca_avg[i]);
2957 }
2958
rtw89_phy_ifs_clm_get_result(struct rtw89_dev * rtwdev)2959 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev)
2960 {
2961 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
2962 u8 i = 0;
2963
2964 if (rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_DONE_MSK) == 0) {
2965 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
2966 "Get IFS_CLM report Fail\n");
2967 return false;
2968 }
2969
2970 env->ifs_clm_tx =
2971 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT,
2972 B_IFS_CLM_TX_CNT_MSK);
2973 env->ifs_clm_edcca_excl_cca =
2974 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT,
2975 B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK);
2976 env->ifs_clm_cckcca_excl_fa =
2977 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA,
2978 B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK);
2979 env->ifs_clm_ofdmcca_excl_fa =
2980 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA,
2981 B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK);
2982 env->ifs_clm_cckfa =
2983 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA,
2984 B_IFS_CLM_CCK_FA_MSK);
2985 env->ifs_clm_ofdmfa =
2986 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA,
2987 B_IFS_CLM_OFDM_FA_MSK);
2988
2989 env->ifs_clm_his[0] =
2990 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T1_HIS_MSK);
2991 env->ifs_clm_his[1] =
2992 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T2_HIS_MSK);
2993 env->ifs_clm_his[2] =
2994 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T3_HIS_MSK);
2995 env->ifs_clm_his[3] =
2996 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T4_HIS_MSK);
2997
2998 env->ifs_clm_avg[0] =
2999 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T1_AVG_MSK);
3000 env->ifs_clm_avg[1] =
3001 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T2_AVG_MSK);
3002 env->ifs_clm_avg[2] =
3003 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T3_AVG_MSK);
3004 env->ifs_clm_avg[3] =
3005 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T4_AVG_MSK);
3006
3007 env->ifs_clm_cca[0] =
3008 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T1_CCA_MSK);
3009 env->ifs_clm_cca[1] =
3010 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T2_CCA_MSK);
3011 env->ifs_clm_cca[2] =
3012 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T3_CCA_MSK);
3013 env->ifs_clm_cca[3] =
3014 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T4_CCA_MSK);
3015
3016 env->ifs_clm_total_ifs =
3017 rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_TOTAL_CNT_MSK);
3018
3019 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n",
3020 env->ifs_clm_total_ifs);
3021 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
3022 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n",
3023 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca);
3024 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
3025 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n",
3026 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa);
3027 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
3028 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n",
3029 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa);
3030
3031 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n");
3032 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
3033 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
3034 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i],
3035 env->ifs_clm_avg[i], env->ifs_clm_cca[i]);
3036
3037 rtw89_phy_ifs_clm_get_utility(rtwdev);
3038
3039 return true;
3040 }
3041
rtw89_phy_ifs_clm_set(struct rtw89_dev * rtwdev,struct rtw89_ccx_para_info * para)3042 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev,
3043 struct rtw89_ccx_para_info *para)
3044 {
3045 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
3046 u32 period = 0;
3047 u32 unit_idx = 0;
3048
3049 if (para->mntr_time == 0) {
3050 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
3051 "[WARN] MNTR_TIME is 0\n");
3052 return -EINVAL;
3053 }
3054
3055 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv))
3056 return -EINVAL;
3057
3058 if (para->mntr_time != env->ifs_clm_mntr_time) {
3059 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time,
3060 &period, &unit_idx);
3061 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER,
3062 B_IFS_CLM_PERIOD_MSK, period);
3063 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER,
3064 B_IFS_CLM_COUNTER_UNIT_MSK, unit_idx);
3065
3066 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
3067 "Update IFS-CLM time ((%d)) -> ((%d))\n",
3068 env->ifs_clm_mntr_time, para->mntr_time);
3069
3070 env->ifs_clm_mntr_time = para->mntr_time;
3071 env->ccx_period = (u16)period;
3072 env->ccx_unit_idx = (u8)unit_idx;
3073 }
3074
3075 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) {
3076 env->ifs_clm_app = para->ifs_clm_app;
3077 rtw89_phy_ifs_clm_set_th_reg(rtwdev);
3078 }
3079
3080 return 0;
3081 }
3082
rtw89_phy_env_monitor_track(struct rtw89_dev * rtwdev)3083 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev)
3084 {
3085 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
3086 struct rtw89_ccx_para_info para = {0};
3087 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL;
3088
3089 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL;
3090 if (env->ccx_manual_ctrl) {
3091 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
3092 "CCX in manual ctrl\n");
3093 return;
3094 }
3095
3096 /* only ifs_clm for now */
3097 if (rtw89_phy_ifs_clm_get_result(rtwdev))
3098 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM;
3099
3100 rtw89_phy_ccx_racing_release(rtwdev);
3101 para.mntr_time = 1900;
3102 para.rac_lv = RTW89_RAC_LV_1;
3103 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
3104
3105 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0)
3106 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM;
3107 if (chk_result)
3108 rtw89_phy_ccx_trigger(rtwdev);
3109
3110 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
3111 "get_result=0x%x, chk_result:0x%x\n",
3112 env->ccx_watchdog_result, chk_result);
3113 }
3114
rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap * ie_page)3115 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page)
3116 {
3117 if (*ie_page > RTW89_PHYSTS_BITMAP_NUM ||
3118 *ie_page == RTW89_RSVD_9)
3119 return false;
3120 else if (*ie_page > RTW89_RSVD_9)
3121 *ie_page -= 1;
3122
3123 return true;
3124 }
3125
rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page)3126 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page)
3127 {
3128 static const u8 ie_page_shift = 2;
3129
3130 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift);
3131 }
3132
rtw89_physts_get_ie_bitmap(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap ie_page)3133 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev,
3134 enum rtw89_phy_status_bitmap ie_page)
3135 {
3136 u32 addr;
3137
3138 if (!rtw89_physts_ie_page_valid(&ie_page))
3139 return 0;
3140
3141 addr = rtw89_phy_get_ie_bitmap_addr(ie_page);
3142
3143 return rtw89_phy_read32(rtwdev, addr);
3144 }
3145
rtw89_physts_set_ie_bitmap(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap ie_page,u32 val)3146 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev,
3147 enum rtw89_phy_status_bitmap ie_page,
3148 u32 val)
3149 {
3150 const struct rtw89_chip_info *chip = rtwdev->chip;
3151 u32 addr;
3152
3153 if (!rtw89_physts_ie_page_valid(&ie_page))
3154 return;
3155
3156 if (chip->chip_id == RTL8852A)
3157 val &= B_PHY_STS_BITMAP_MSK_52A;
3158
3159 addr = rtw89_phy_get_ie_bitmap_addr(ie_page);
3160 rtw89_phy_write32(rtwdev, addr, val);
3161 }
3162
rtw89_physts_enable_ie_bitmap(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap bitmap,enum rtw89_phy_status_ie_type ie,bool enable)3163 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev,
3164 enum rtw89_phy_status_bitmap bitmap,
3165 enum rtw89_phy_status_ie_type ie,
3166 bool enable)
3167 {
3168 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap);
3169
3170 if (enable)
3171 val |= BIT(ie);
3172 else
3173 val &= ~BIT(ie);
3174
3175 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val);
3176 }
3177
rtw89_physts_enable_fail_report(struct rtw89_dev * rtwdev,bool enable,enum rtw89_phy_idx phy_idx)3178 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev,
3179 bool enable,
3180 enum rtw89_phy_idx phy_idx)
3181 {
3182 if (enable) {
3183 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM,
3184 B_STS_DIS_TRIG_BY_FAIL);
3185 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM,
3186 B_STS_DIS_TRIG_BY_BRK);
3187 } else {
3188 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM,
3189 B_STS_DIS_TRIG_BY_FAIL);
3190 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM,
3191 B_STS_DIS_TRIG_BY_BRK);
3192 }
3193 }
3194
rtw89_physts_parsing_init(struct rtw89_dev * rtwdev)3195 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev)
3196 {
3197 u8 i;
3198
3199 rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0);
3200
3201 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) {
3202 if (i >= RTW89_CCK_PKT)
3203 rtw89_physts_enable_ie_bitmap(rtwdev, i,
3204 RTW89_PHYSTS_IE09_FTR_0,
3205 true);
3206 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) ||
3207 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT))
3208 continue;
3209 rtw89_physts_enable_ie_bitmap(rtwdev, i,
3210 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A,
3211 true);
3212 }
3213 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT,
3214 RTW89_PHYSTS_IE13_DL_MU_DEF, true);
3215 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT,
3216 RTW89_PHYSTS_IE13_DL_MU_DEF, true);
3217
3218 /* force IE01 for channel index, only channel field is valid */
3219 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT,
3220 RTW89_PHYSTS_IE01_CMN_OFDM, true);
3221 }
3222
rtw89_phy_dig_read_gain_table(struct rtw89_dev * rtwdev,int type)3223 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type)
3224 {
3225 const struct rtw89_chip_info *chip = rtwdev->chip;
3226 struct rtw89_dig_info *dig = &rtwdev->dig;
3227 const struct rtw89_phy_dig_gain_cfg *cfg;
3228 const char *msg;
3229 u8 i;
3230 s8 gain_base;
3231 s8 *gain_arr;
3232 u32 tmp;
3233
3234 switch (type) {
3235 case RTW89_DIG_GAIN_LNA_G:
3236 gain_arr = dig->lna_gain_g;
3237 gain_base = LNA0_GAIN;
3238 cfg = chip->dig_table->cfg_lna_g;
3239 msg = "lna_gain_g";
3240 break;
3241 case RTW89_DIG_GAIN_TIA_G:
3242 gain_arr = dig->tia_gain_g;
3243 gain_base = TIA0_GAIN_G;
3244 cfg = chip->dig_table->cfg_tia_g;
3245 msg = "tia_gain_g";
3246 break;
3247 case RTW89_DIG_GAIN_LNA_A:
3248 gain_arr = dig->lna_gain_a;
3249 gain_base = LNA0_GAIN;
3250 cfg = chip->dig_table->cfg_lna_a;
3251 msg = "lna_gain_a";
3252 break;
3253 case RTW89_DIG_GAIN_TIA_A:
3254 gain_arr = dig->tia_gain_a;
3255 gain_base = TIA0_GAIN_A;
3256 cfg = chip->dig_table->cfg_tia_a;
3257 msg = "tia_gain_a";
3258 break;
3259 default:
3260 return;
3261 }
3262
3263 for (i = 0; i < cfg->size; i++) {
3264 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr,
3265 cfg->table[i].mask);
3266 tmp >>= DIG_GAIN_SHIFT;
3267 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base;
3268 gain_base += DIG_GAIN;
3269
3270 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n",
3271 msg, i, gain_arr[i]);
3272 }
3273 }
3274
rtw89_phy_dig_update_gain_para(struct rtw89_dev * rtwdev)3275 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev)
3276 {
3277 struct rtw89_dig_info *dig = &rtwdev->dig;
3278 u32 tmp;
3279 u8 i;
3280
3281 if (!rtwdev->hal.support_igi)
3282 return;
3283
3284 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW,
3285 B_PATH0_IB_PKPW_MSK);
3286 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT);
3287 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK,
3288 B_PATH0_IB_PBK_MSK);
3289 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n",
3290 dig->ib_pkpwr, dig->ib_pbk);
3291
3292 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++)
3293 rtw89_phy_dig_read_gain_table(rtwdev, i);
3294 }
3295
3296 static const u8 rssi_nolink = 22;
3297 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104};
3298 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88};
3299 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16};
3300 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528};
3301
rtw89_phy_dig_update_rssi_info(struct rtw89_dev * rtwdev)3302 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev)
3303 {
3304 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info;
3305 struct rtw89_dig_info *dig = &rtwdev->dig;
3306 bool is_linked = rtwdev->total_sta_assoc > 0;
3307
3308 if (is_linked) {
3309 dig->igi_rssi = ch_info->rssi_min >> 1;
3310 } else {
3311 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n");
3312 dig->igi_rssi = rssi_nolink;
3313 }
3314 }
3315
rtw89_phy_dig_update_para(struct rtw89_dev * rtwdev)3316 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev)
3317 {
3318 struct rtw89_dig_info *dig = &rtwdev->dig;
3319 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
3320 bool is_linked = rtwdev->total_sta_assoc > 0;
3321 const u16 *fa_th_src = NULL;
3322
3323 switch (chan->band_type) {
3324 case RTW89_BAND_2G:
3325 dig->lna_gain = dig->lna_gain_g;
3326 dig->tia_gain = dig->tia_gain_g;
3327 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink;
3328 dig->force_gaincode_idx_en = false;
3329 dig->dyn_pd_th_en = true;
3330 break;
3331 case RTW89_BAND_5G:
3332 default:
3333 dig->lna_gain = dig->lna_gain_a;
3334 dig->tia_gain = dig->tia_gain_a;
3335 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink;
3336 dig->force_gaincode_idx_en = true;
3337 dig->dyn_pd_th_en = true;
3338 break;
3339 }
3340 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th));
3341 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th));
3342 }
3343
3344 static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20;
3345 static const u8 igi_max_performance_mode = 0x5a;
3346 static const u8 dynamic_pd_threshold_max;
3347
rtw89_phy_dig_para_reset(struct rtw89_dev * rtwdev)3348 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev)
3349 {
3350 struct rtw89_dig_info *dig = &rtwdev->dig;
3351
3352 dig->cur_gaincode.lna_idx = LNA_IDX_MAX;
3353 dig->cur_gaincode.tia_idx = TIA_IDX_MAX;
3354 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX;
3355 dig->force_gaincode.lna_idx = LNA_IDX_MAX;
3356 dig->force_gaincode.tia_idx = TIA_IDX_MAX;
3357 dig->force_gaincode.rxb_idx = RXB_IDX_MAX;
3358
3359 dig->dyn_igi_max = igi_max_performance_mode;
3360 dig->dyn_igi_min = dynamic_igi_min;
3361 dig->dyn_pd_th_max = dynamic_pd_threshold_max;
3362 dig->pd_low_th_ofst = pd_low_th_offset;
3363 dig->is_linked_pre = false;
3364 }
3365
rtw89_phy_dig_init(struct rtw89_dev * rtwdev)3366 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev)
3367 {
3368 rtw89_phy_dig_update_gain_para(rtwdev);
3369 rtw89_phy_dig_reset(rtwdev);
3370 }
3371
rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev * rtwdev,u8 rssi)3372 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi)
3373 {
3374 struct rtw89_dig_info *dig = &rtwdev->dig;
3375 u8 lna_idx;
3376
3377 if (rssi < dig->igi_rssi_th[0])
3378 lna_idx = RTW89_DIG_GAIN_LNA_IDX6;
3379 else if (rssi < dig->igi_rssi_th[1])
3380 lna_idx = RTW89_DIG_GAIN_LNA_IDX5;
3381 else if (rssi < dig->igi_rssi_th[2])
3382 lna_idx = RTW89_DIG_GAIN_LNA_IDX4;
3383 else if (rssi < dig->igi_rssi_th[3])
3384 lna_idx = RTW89_DIG_GAIN_LNA_IDX3;
3385 else if (rssi < dig->igi_rssi_th[4])
3386 lna_idx = RTW89_DIG_GAIN_LNA_IDX2;
3387 else
3388 lna_idx = RTW89_DIG_GAIN_LNA_IDX1;
3389
3390 return lna_idx;
3391 }
3392
rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev * rtwdev,u8 rssi)3393 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi)
3394 {
3395 struct rtw89_dig_info *dig = &rtwdev->dig;
3396 u8 tia_idx;
3397
3398 if (rssi < dig->igi_rssi_th[0])
3399 tia_idx = RTW89_DIG_GAIN_TIA_IDX1;
3400 else
3401 tia_idx = RTW89_DIG_GAIN_TIA_IDX0;
3402
3403 return tia_idx;
3404 }
3405
3406 #define IB_PBK_BASE 110
3407 #define WB_RSSI_BASE 10
rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev * rtwdev,u8 rssi,struct rtw89_agc_gaincode_set * set)3408 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi,
3409 struct rtw89_agc_gaincode_set *set)
3410 {
3411 struct rtw89_dig_info *dig = &rtwdev->dig;
3412 s8 lna_gain = dig->lna_gain[set->lna_idx];
3413 s8 tia_gain = dig->tia_gain[set->tia_idx];
3414 s32 wb_rssi = rssi + lna_gain + tia_gain;
3415 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE;
3416 u8 rxb_idx;
3417
3418 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi;
3419 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX);
3420
3421 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n",
3422 wb_rssi, rxb_idx_tmp);
3423
3424 return rxb_idx;
3425 }
3426
rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev * rtwdev,u8 rssi,struct rtw89_agc_gaincode_set * set)3427 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi,
3428 struct rtw89_agc_gaincode_set *set)
3429 {
3430 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi);
3431 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi);
3432 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set);
3433
3434 rtw89_debug(rtwdev, RTW89_DBG_DIG,
3435 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n",
3436 rssi, set->lna_idx, set->tia_idx, set->rxb_idx);
3437 }
3438
3439 #define IGI_OFFSET_MAX 25
3440 #define IGI_OFFSET_MUL 2
rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev * rtwdev)3441 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev)
3442 {
3443 struct rtw89_dig_info *dig = &rtwdev->dig;
3444 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
3445 enum rtw89_dig_noisy_level noisy_lv;
3446 u8 igi_offset = dig->fa_rssi_ofst;
3447 u16 fa_ratio = 0;
3448
3449 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil;
3450
3451 if (fa_ratio < dig->fa_th[0])
3452 noisy_lv = RTW89_DIG_NOISY_LEVEL0;
3453 else if (fa_ratio < dig->fa_th[1])
3454 noisy_lv = RTW89_DIG_NOISY_LEVEL1;
3455 else if (fa_ratio < dig->fa_th[2])
3456 noisy_lv = RTW89_DIG_NOISY_LEVEL2;
3457 else if (fa_ratio < dig->fa_th[3])
3458 noisy_lv = RTW89_DIG_NOISY_LEVEL3;
3459 else
3460 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX;
3461
3462 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2)
3463 igi_offset = 0;
3464 else
3465 igi_offset += noisy_lv * IGI_OFFSET_MUL;
3466
3467 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX);
3468 dig->fa_rssi_ofst = igi_offset;
3469
3470 rtw89_debug(rtwdev, RTW89_DBG_DIG,
3471 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n",
3472 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]);
3473
3474 rtw89_debug(rtwdev, RTW89_DBG_DIG,
3475 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n",
3476 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil,
3477 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil,
3478 noisy_lv, igi_offset);
3479 }
3480
rtw89_phy_dig_set_lna_idx(struct rtw89_dev * rtwdev,u8 lna_idx)3481 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx)
3482 {
3483 rtw89_phy_write32_mask(rtwdev, R_PATH0_LNA_INIT,
3484 B_PATH0_LNA_INIT_IDX_MSK, lna_idx);
3485 rtw89_phy_write32_mask(rtwdev, R_PATH1_LNA_INIT,
3486 B_PATH1_LNA_INIT_IDX_MSK, lna_idx);
3487 }
3488
rtw89_phy_dig_set_tia_idx(struct rtw89_dev * rtwdev,u8 tia_idx)3489 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx)
3490 {
3491 rtw89_phy_write32_mask(rtwdev, R_PATH0_TIA_INIT,
3492 B_PATH0_TIA_INIT_IDX_MSK, tia_idx);
3493 rtw89_phy_write32_mask(rtwdev, R_PATH1_TIA_INIT,
3494 B_PATH1_TIA_INIT_IDX_MSK, tia_idx);
3495 }
3496
rtw89_phy_dig_set_rxb_idx(struct rtw89_dev * rtwdev,u8 rxb_idx)3497 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx)
3498 {
3499 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXB_INIT,
3500 B_PATH0_RXB_INIT_IDX_MSK, rxb_idx);
3501 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXB_INIT,
3502 B_PATH1_RXB_INIT_IDX_MSK, rxb_idx);
3503 }
3504
rtw89_phy_dig_set_igi_cr(struct rtw89_dev * rtwdev,const struct rtw89_agc_gaincode_set set)3505 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev,
3506 const struct rtw89_agc_gaincode_set set)
3507 {
3508 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx);
3509 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx);
3510 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx);
3511
3512 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n",
3513 set.lna_idx, set.tia_idx, set.rxb_idx);
3514 }
3515
3516 static const struct rtw89_reg_def sdagc_config[4] = {
3517 {R_PATH0_P20_FOLLOW_BY_PAGCUGC, B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
3518 {R_PATH0_S20_FOLLOW_BY_PAGCUGC, B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
3519 {R_PATH1_P20_FOLLOW_BY_PAGCUGC, B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
3520 {R_PATH1_S20_FOLLOW_BY_PAGCUGC, B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
3521 };
3522
rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev * rtwdev,bool enable)3523 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev,
3524 bool enable)
3525 {
3526 u8 i = 0;
3527
3528 for (i = 0; i < ARRAY_SIZE(sdagc_config); i++)
3529 rtw89_phy_write32_mask(rtwdev, sdagc_config[i].addr,
3530 sdagc_config[i].mask, enable);
3531
3532 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable);
3533 }
3534
rtw89_phy_dig_config_igi(struct rtw89_dev * rtwdev)3535 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev)
3536 {
3537 struct rtw89_dig_info *dig = &rtwdev->dig;
3538
3539 if (!rtwdev->hal.support_igi)
3540 return;
3541
3542 if (dig->force_gaincode_idx_en) {
3543 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode);
3544 rtw89_debug(rtwdev, RTW89_DBG_DIG,
3545 "Force gaincode index enabled.\n");
3546 } else {
3547 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi,
3548 &dig->cur_gaincode);
3549 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode);
3550 }
3551 }
3552
rtw89_phy_dig_dyn_pd_th(struct rtw89_dev * rtwdev,u8 rssi,bool enable)3553 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi,
3554 bool enable)
3555 {
3556 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
3557 enum rtw89_bandwidth cbw = chan->band_width;
3558 struct rtw89_dig_info *dig = &rtwdev->dig;
3559 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst;
3560 u8 ofdm_cca_th;
3561 s8 cck_cca_th;
3562 u32 pd_val = 0;
3563
3564 under_region += PD_TH_SB_FLTR_CMP_VAL;
3565
3566 switch (cbw) {
3567 case RTW89_CHANNEL_WIDTH_40:
3568 under_region += PD_TH_BW40_CMP_VAL;
3569 break;
3570 case RTW89_CHANNEL_WIDTH_80:
3571 under_region += PD_TH_BW80_CMP_VAL;
3572 break;
3573 case RTW89_CHANNEL_WIDTH_160:
3574 under_region += PD_TH_BW160_CMP_VAL;
3575 break;
3576 case RTW89_CHANNEL_WIDTH_20:
3577 fallthrough;
3578 default:
3579 under_region += PD_TH_BW20_CMP_VAL;
3580 break;
3581 }
3582
3583 dig->dyn_pd_th_max = dig->igi_rssi;
3584
3585 final_rssi = min_t(u8, rssi, dig->igi_rssi);
3586 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region,
3587 PD_TH_MAX_RSSI + under_region);
3588
3589 if (enable) {
3590 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1;
3591 rtw89_debug(rtwdev, RTW89_DBG_DIG,
3592 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n",
3593 final_rssi, ofdm_cca_th, under_region, pd_val);
3594 } else {
3595 rtw89_debug(rtwdev, RTW89_DBG_DIG,
3596 "Dynamic PD th disabled, Set PD_low_bd=0\n");
3597 }
3598
3599 rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD, B_SEG0R_PD_LOWER_BOUND_MSK,
3600 pd_val);
3601 rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD,
3602 B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, enable);
3603
3604 if (!rtwdev->hal.support_cckpd)
3605 return;
3606
3607 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI);
3608 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX);
3609
3610 rtw89_debug(rtwdev, RTW89_DBG_DIG,
3611 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n",
3612 final_rssi, cck_cca_th, under_region, pd_val);
3613
3614 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_EN_V1,
3615 B_BMODE_PDTH_LIMIT_EN_MSK_V1, enable);
3616 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_V1,
3617 B_BMODE_PDTH_LOWER_BOUND_MSK_V1, pd_val);
3618 }
3619
rtw89_phy_dig_reset(struct rtw89_dev * rtwdev)3620 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev)
3621 {
3622 struct rtw89_dig_info *dig = &rtwdev->dig;
3623
3624 dig->bypass_dig = false;
3625 rtw89_phy_dig_para_reset(rtwdev);
3626 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode);
3627 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false);
3628 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false);
3629 rtw89_phy_dig_update_para(rtwdev);
3630 }
3631
3632 #define IGI_RSSI_MIN 10
rtw89_phy_dig(struct rtw89_dev * rtwdev)3633 void rtw89_phy_dig(struct rtw89_dev *rtwdev)
3634 {
3635 struct rtw89_dig_info *dig = &rtwdev->dig;
3636 bool is_linked = rtwdev->total_sta_assoc > 0;
3637
3638 if (unlikely(dig->bypass_dig)) {
3639 dig->bypass_dig = false;
3640 return;
3641 }
3642
3643 if (!dig->is_linked_pre && is_linked) {
3644 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n");
3645 rtw89_phy_dig_update_para(rtwdev);
3646 } else if (dig->is_linked_pre && !is_linked) {
3647 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n");
3648 rtw89_phy_dig_update_para(rtwdev);
3649 }
3650 dig->is_linked_pre = is_linked;
3651
3652 rtw89_phy_dig_igi_offset_by_env(rtwdev);
3653 rtw89_phy_dig_update_rssi_info(rtwdev);
3654
3655 dig->dyn_igi_min = (dig->igi_rssi > IGI_RSSI_MIN) ?
3656 dig->igi_rssi - IGI_RSSI_MIN : 0;
3657 dig->dyn_igi_max = dig->dyn_igi_min + IGI_OFFSET_MAX;
3658 dig->igi_fa_rssi = dig->dyn_igi_min + dig->fa_rssi_ofst;
3659
3660 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min,
3661 dig->dyn_igi_max);
3662
3663 rtw89_debug(rtwdev, RTW89_DBG_DIG,
3664 "rssi=%03d, dyn(max,min)=(%d,%d), final_rssi=%d\n",
3665 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min,
3666 dig->igi_fa_rssi);
3667
3668 rtw89_phy_dig_config_igi(rtwdev);
3669
3670 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en);
3671
3672 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max)
3673 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true);
3674 else
3675 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false);
3676 }
3677
rtw89_phy_env_monitor_init(struct rtw89_dev * rtwdev)3678 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev)
3679 {
3680 rtw89_phy_ccx_top_setting_init(rtwdev);
3681 rtw89_phy_ifs_clm_setting_init(rtwdev);
3682 }
3683
rtw89_phy_dm_init(struct rtw89_dev * rtwdev)3684 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev)
3685 {
3686 const struct rtw89_chip_info *chip = rtwdev->chip;
3687
3688 rtw89_phy_stat_init(rtwdev);
3689
3690 rtw89_chip_bb_sethw(rtwdev);
3691
3692 rtw89_phy_env_monitor_init(rtwdev);
3693 rtw89_physts_parsing_init(rtwdev);
3694 rtw89_phy_dig_init(rtwdev);
3695 rtw89_phy_cfo_init(rtwdev);
3696
3697 rtw89_phy_init_rf_nctl(rtwdev);
3698 rtw89_chip_rfk_init(rtwdev);
3699 rtw89_load_txpwr_table(rtwdev, chip->byr_table);
3700 rtw89_chip_set_txpwr_ctrl(rtwdev);
3701 rtw89_chip_power_trim(rtwdev);
3702 rtw89_chip_cfg_txrx_path(rtwdev);
3703 }
3704
rtw89_phy_set_bss_color(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif)3705 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif)
3706 {
3707 enum rtw89_phy_idx phy_idx = RTW89_PHY_0;
3708 u8 bss_color;
3709
3710 if (!vif->bss_conf.he_support || !vif->cfg.assoc)
3711 return;
3712
3713 bss_color = vif->bss_conf.he_bss_color.color;
3714
3715 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0, 0x1,
3716 phy_idx);
3717 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_TGT, bss_color,
3718 phy_idx);
3719 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_STAID,
3720 vif->cfg.aid, phy_idx);
3721 }
3722
3723 static void
_rfk_write_rf(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)3724 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
3725 {
3726 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data);
3727 }
3728
3729 static void
_rfk_write32_mask(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)3730 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
3731 {
3732 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
3733 }
3734
3735 static void
_rfk_write32_set(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)3736 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
3737 {
3738 rtw89_phy_write32_set(rtwdev, def->addr, def->mask);
3739 }
3740
3741 static void
_rfk_write32_clr(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)3742 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
3743 {
3744 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask);
3745 }
3746
3747 static void
_rfk_delay(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)3748 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
3749 {
3750 udelay(def->data);
3751 }
3752
3753 static void
3754 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = {
3755 [RTW89_RFK_F_WRF] = _rfk_write_rf,
3756 [RTW89_RFK_F_WM] = _rfk_write32_mask,
3757 [RTW89_RFK_F_WS] = _rfk_write32_set,
3758 [RTW89_RFK_F_WC] = _rfk_write32_clr,
3759 [RTW89_RFK_F_DELAY] = _rfk_delay,
3760 };
3761
3762 #if defined(__linux__)
3763 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM);
3764 #elif defined(__FreeBSD__)
3765 rtw89_static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM);
3766 #endif
3767
3768 void
rtw89_rfk_parser(struct rtw89_dev * rtwdev,const struct rtw89_rfk_tbl * tbl)3769 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl)
3770 {
3771 const struct rtw89_reg5_def *p = tbl->defs;
3772 const struct rtw89_reg5_def *end = tbl->defs + tbl->size;
3773
3774 for (; p < end; p++)
3775 _rfk_handler[p->flag](rtwdev, p);
3776 }
3777 EXPORT_SYMBOL(rtw89_rfk_parser);
3778
3779 #define RTW89_TSSI_FAST_MODE_NUM 4
3780
3781 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = {
3782 {0xD934, 0xff0000},
3783 {0xD934, 0xff000000},
3784 {0xD938, 0xff},
3785 {0xD934, 0xff00},
3786 };
3787
3788 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = {
3789 {0xD930, 0xff0000},
3790 {0xD930, 0xff000000},
3791 {0xD934, 0xff},
3792 {0xD930, 0xff00},
3793 };
3794
3795 static
rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx,enum rtw89_tssi_bandedge_cfg bandedge_cfg,u32 val)3796 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev,
3797 enum rtw89_mac_idx mac_idx,
3798 enum rtw89_tssi_bandedge_cfg bandedge_cfg,
3799 u32 val)
3800 {
3801 const struct rtw89_reg_def *regs;
3802 u32 reg;
3803 int i;
3804
3805 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT)
3806 regs = rtw89_tssi_fastmode_regs_flat;
3807 else
3808 regs = rtw89_tssi_fastmode_regs_level;
3809
3810 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) {
3811 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx);
3812 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val);
3813 }
3814 }
3815
3816 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = {
3817 {0xD91C, 0xff000000},
3818 {0xD920, 0xff},
3819 {0xD920, 0xff00},
3820 {0xD920, 0xff0000},
3821 {0xD920, 0xff000000},
3822 {0xD924, 0xff},
3823 {0xD924, 0xff00},
3824 {0xD914, 0xff000000},
3825 {0xD918, 0xff},
3826 {0xD918, 0xff00},
3827 {0xD918, 0xff0000},
3828 {0xD918, 0xff000000},
3829 {0xD91C, 0xff},
3830 {0xD91C, 0xff00},
3831 {0xD91C, 0xff0000},
3832 };
3833
3834 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = {
3835 {0xD910, 0xff},
3836 {0xD910, 0xff00},
3837 {0xD910, 0xff0000},
3838 {0xD910, 0xff000000},
3839 {0xD914, 0xff},
3840 {0xD914, 0xff00},
3841 {0xD914, 0xff0000},
3842 {0xD908, 0xff},
3843 {0xD908, 0xff00},
3844 {0xD908, 0xff0000},
3845 {0xD908, 0xff000000},
3846 {0xD90C, 0xff},
3847 {0xD90C, 0xff00},
3848 {0xD90C, 0xff0000},
3849 {0xD90C, 0xff000000},
3850 };
3851
rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx,enum rtw89_tssi_bandedge_cfg bandedge_cfg)3852 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
3853 enum rtw89_mac_idx mac_idx,
3854 enum rtw89_tssi_bandedge_cfg bandedge_cfg)
3855 {
3856 const struct rtw89_chip_info *chip = rtwdev->chip;
3857 const struct rtw89_reg_def *regs;
3858 const u32 *data;
3859 u32 reg;
3860 int i;
3861
3862 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM)
3863 return;
3864
3865 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT)
3866 regs = rtw89_tssi_bandedge_regs_flat;
3867 else
3868 regs = rtw89_tssi_bandedge_regs_level;
3869
3870 data = chip->tssi_dbw_table->data[bandedge_cfg];
3871
3872 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) {
3873 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx);
3874 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]);
3875 }
3876
3877 reg = rtw89_mac_reg_by_idx(R_AX_BANDEDGE_CFG, mac_idx);
3878 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg);
3879
3880 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg,
3881 data[RTW89_TSSI_SBW20]);
3882 }
3883 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg);
3884