1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #if defined(__FreeBSD__)
6 #define LINUXKPI_PARAM_PREFIX rtw89_
7 #endif
8
9 #include <linux/ip.h>
10 #include <linux/udp.h>
11
12 #include "cam.h"
13 #include "chan.h"
14 #include "coex.h"
15 #include "core.h"
16 #include "efuse.h"
17 #include "fw.h"
18 #include "mac.h"
19 #include "phy.h"
20 #include "ps.h"
21 #include "reg.h"
22 #include "sar.h"
23 #include "ser.h"
24 #include "txrx.h"
25 #include "util.h"
26 #include "wow.h"
27
28 static bool rtw89_disable_ps_mode;
29 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644);
30 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode");
31
32 #if defined(__FreeBSD__)
33 static bool rtw_ht_support = false;
34 module_param_named(support_ht, rtw_ht_support, bool, 0644);
35 MODULE_PARM_DESC(support_ht, "Set to Y to enable HT support");
36
37 static bool rtw_vht_support = false;
38 module_param_named(support_vht, rtw_vht_support, bool, 0644);
39 MODULE_PARM_DESC(support_vht, "Set to Y to enable VHT support");
40
41 static bool rtw_eht_support = false;
42 module_param_named(support_eht, rtw_eht_support, bool, 0644);
43 MODULE_PARM_DESC(support_eht, "Set to Y to enable EHT support");
44 #endif
45
46
47 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \
48 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, }
49 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \
50 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ)
51 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \
52 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ)
53 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \
54 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ)
55 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \
56 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ)
57
58 static struct ieee80211_channel rtw89_channels_2ghz[] = {
59 RTW89_DEF_CHAN_2G(2412, 1),
60 RTW89_DEF_CHAN_2G(2417, 2),
61 RTW89_DEF_CHAN_2G(2422, 3),
62 RTW89_DEF_CHAN_2G(2427, 4),
63 RTW89_DEF_CHAN_2G(2432, 5),
64 RTW89_DEF_CHAN_2G(2437, 6),
65 RTW89_DEF_CHAN_2G(2442, 7),
66 RTW89_DEF_CHAN_2G(2447, 8),
67 RTW89_DEF_CHAN_2G(2452, 9),
68 RTW89_DEF_CHAN_2G(2457, 10),
69 RTW89_DEF_CHAN_2G(2462, 11),
70 RTW89_DEF_CHAN_2G(2467, 12),
71 RTW89_DEF_CHAN_2G(2472, 13),
72 RTW89_DEF_CHAN_2G(2484, 14),
73 };
74
75 static struct ieee80211_channel rtw89_channels_5ghz[] = {
76 RTW89_DEF_CHAN_5G(5180, 36),
77 RTW89_DEF_CHAN_5G(5200, 40),
78 RTW89_DEF_CHAN_5G(5220, 44),
79 RTW89_DEF_CHAN_5G(5240, 48),
80 RTW89_DEF_CHAN_5G(5260, 52),
81 RTW89_DEF_CHAN_5G(5280, 56),
82 RTW89_DEF_CHAN_5G(5300, 60),
83 RTW89_DEF_CHAN_5G(5320, 64),
84 RTW89_DEF_CHAN_5G(5500, 100),
85 RTW89_DEF_CHAN_5G(5520, 104),
86 RTW89_DEF_CHAN_5G(5540, 108),
87 RTW89_DEF_CHAN_5G(5560, 112),
88 RTW89_DEF_CHAN_5G(5580, 116),
89 RTW89_DEF_CHAN_5G(5600, 120),
90 RTW89_DEF_CHAN_5G(5620, 124),
91 RTW89_DEF_CHAN_5G(5640, 128),
92 RTW89_DEF_CHAN_5G(5660, 132),
93 RTW89_DEF_CHAN_5G(5680, 136),
94 RTW89_DEF_CHAN_5G(5700, 140),
95 RTW89_DEF_CHAN_5G(5720, 144),
96 RTW89_DEF_CHAN_5G(5745, 149),
97 RTW89_DEF_CHAN_5G(5765, 153),
98 RTW89_DEF_CHAN_5G(5785, 157),
99 RTW89_DEF_CHAN_5G(5805, 161),
100 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165),
101 RTW89_DEF_CHAN_5G(5845, 169),
102 RTW89_DEF_CHAN_5G(5865, 173),
103 RTW89_DEF_CHAN_5G(5885, 177),
104 };
105
106 static_assert(RTW89_5GHZ_UNII4_START_INDEX + RTW89_5GHZ_UNII4_CHANNEL_NUM ==
107 ARRAY_SIZE(rtw89_channels_5ghz));
108
109 static struct ieee80211_channel rtw89_channels_6ghz[] = {
110 RTW89_DEF_CHAN_6G(5955, 1),
111 RTW89_DEF_CHAN_6G(5975, 5),
112 RTW89_DEF_CHAN_6G(5995, 9),
113 RTW89_DEF_CHAN_6G(6015, 13),
114 RTW89_DEF_CHAN_6G(6035, 17),
115 RTW89_DEF_CHAN_6G(6055, 21),
116 RTW89_DEF_CHAN_6G(6075, 25),
117 RTW89_DEF_CHAN_6G(6095, 29),
118 RTW89_DEF_CHAN_6G(6115, 33),
119 RTW89_DEF_CHAN_6G(6135, 37),
120 RTW89_DEF_CHAN_6G(6155, 41),
121 RTW89_DEF_CHAN_6G(6175, 45),
122 RTW89_DEF_CHAN_6G(6195, 49),
123 RTW89_DEF_CHAN_6G(6215, 53),
124 RTW89_DEF_CHAN_6G(6235, 57),
125 RTW89_DEF_CHAN_6G(6255, 61),
126 RTW89_DEF_CHAN_6G(6275, 65),
127 RTW89_DEF_CHAN_6G(6295, 69),
128 RTW89_DEF_CHAN_6G(6315, 73),
129 RTW89_DEF_CHAN_6G(6335, 77),
130 RTW89_DEF_CHAN_6G(6355, 81),
131 RTW89_DEF_CHAN_6G(6375, 85),
132 RTW89_DEF_CHAN_6G(6395, 89),
133 RTW89_DEF_CHAN_6G(6415, 93),
134 RTW89_DEF_CHAN_6G(6435, 97),
135 RTW89_DEF_CHAN_6G(6455, 101),
136 RTW89_DEF_CHAN_6G(6475, 105),
137 RTW89_DEF_CHAN_6G(6495, 109),
138 RTW89_DEF_CHAN_6G(6515, 113),
139 RTW89_DEF_CHAN_6G(6535, 117),
140 RTW89_DEF_CHAN_6G(6555, 121),
141 RTW89_DEF_CHAN_6G(6575, 125),
142 RTW89_DEF_CHAN_6G(6595, 129),
143 RTW89_DEF_CHAN_6G(6615, 133),
144 RTW89_DEF_CHAN_6G(6635, 137),
145 RTW89_DEF_CHAN_6G(6655, 141),
146 RTW89_DEF_CHAN_6G(6675, 145),
147 RTW89_DEF_CHAN_6G(6695, 149),
148 RTW89_DEF_CHAN_6G(6715, 153),
149 RTW89_DEF_CHAN_6G(6735, 157),
150 RTW89_DEF_CHAN_6G(6755, 161),
151 RTW89_DEF_CHAN_6G(6775, 165),
152 RTW89_DEF_CHAN_6G(6795, 169),
153 RTW89_DEF_CHAN_6G(6815, 173),
154 RTW89_DEF_CHAN_6G(6835, 177),
155 RTW89_DEF_CHAN_6G(6855, 181),
156 RTW89_DEF_CHAN_6G(6875, 185),
157 RTW89_DEF_CHAN_6G(6895, 189),
158 RTW89_DEF_CHAN_6G(6915, 193),
159 RTW89_DEF_CHAN_6G(6935, 197),
160 RTW89_DEF_CHAN_6G(6955, 201),
161 RTW89_DEF_CHAN_6G(6975, 205),
162 RTW89_DEF_CHAN_6G(6995, 209),
163 RTW89_DEF_CHAN_6G(7015, 213),
164 RTW89_DEF_CHAN_6G(7035, 217),
165 RTW89_DEF_CHAN_6G(7055, 221),
166 RTW89_DEF_CHAN_6G(7075, 225),
167 RTW89_DEF_CHAN_6G(7095, 229),
168 RTW89_DEF_CHAN_6G(7115, 233),
169 };
170
171 static struct ieee80211_rate rtw89_bitrates[] = {
172 { .bitrate = 10, .hw_value = 0x00, },
173 { .bitrate = 20, .hw_value = 0x01, },
174 { .bitrate = 55, .hw_value = 0x02, },
175 { .bitrate = 110, .hw_value = 0x03, },
176 { .bitrate = 60, .hw_value = 0x04, },
177 { .bitrate = 90, .hw_value = 0x05, },
178 { .bitrate = 120, .hw_value = 0x06, },
179 { .bitrate = 180, .hw_value = 0x07, },
180 { .bitrate = 240, .hw_value = 0x08, },
181 { .bitrate = 360, .hw_value = 0x09, },
182 { .bitrate = 480, .hw_value = 0x0a, },
183 { .bitrate = 540, .hw_value = 0x0b, },
184 };
185
186 static const struct ieee80211_iface_limit rtw89_iface_limits[] = {
187 {
188 .max = 1,
189 .types = BIT(NL80211_IFTYPE_STATION),
190 },
191 {
192 .max = 1,
193 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
194 BIT(NL80211_IFTYPE_P2P_GO) |
195 BIT(NL80211_IFTYPE_AP),
196 },
197 };
198
199 static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = {
200 {
201 .max = 1,
202 .types = BIT(NL80211_IFTYPE_STATION),
203 },
204 {
205 .max = 1,
206 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
207 BIT(NL80211_IFTYPE_P2P_GO),
208 },
209 };
210
211 static const struct ieee80211_iface_combination rtw89_iface_combs[] = {
212 {
213 .limits = rtw89_iface_limits,
214 .n_limits = ARRAY_SIZE(rtw89_iface_limits),
215 .max_interfaces = RTW89_MAX_INTERFACE_NUM,
216 .num_different_channels = 1,
217 },
218 {
219 .limits = rtw89_iface_limits_mcc,
220 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc),
221 .max_interfaces = RTW89_MAX_INTERFACE_NUM,
222 .num_different_channels = 2,
223 },
224 };
225
226 #define RTW89_6GHZ_SPAN_HEAD 6145
227 #define RTW89_6GHZ_SPAN_IDX(center_freq) \
228 ((((int)(center_freq) - RTW89_6GHZ_SPAN_HEAD) / 5) / 2)
229
230 #define RTW89_DECL_6GHZ_SPAN(center_freq, subband_l, subband_h) \
231 [RTW89_6GHZ_SPAN_IDX(center_freq)] = { \
232 .sar_subband_low = RTW89_SAR_6GHZ_ ## subband_l, \
233 .sar_subband_high = RTW89_SAR_6GHZ_ ## subband_h, \
234 .ant_gain_subband_low = RTW89_ANT_GAIN_6GHZ_ ## subband_l, \
235 .ant_gain_subband_high = RTW89_ANT_GAIN_6GHZ_ ## subband_h, \
236 }
237
238 /* Since 6GHz subbands are not edge aligned, some cases span two subbands.
239 * In the following, we describe each of them with rtw89_6ghz_span.
240 */
241 static const struct rtw89_6ghz_span rtw89_overlapping_6ghz[] = {
242 RTW89_DECL_6GHZ_SPAN(6145, SUBBAND_5_L, SUBBAND_5_H),
243 RTW89_DECL_6GHZ_SPAN(6165, SUBBAND_5_L, SUBBAND_5_H),
244 RTW89_DECL_6GHZ_SPAN(6185, SUBBAND_5_L, SUBBAND_5_H),
245 RTW89_DECL_6GHZ_SPAN(6505, SUBBAND_6, SUBBAND_7_L),
246 RTW89_DECL_6GHZ_SPAN(6525, SUBBAND_6, SUBBAND_7_L),
247 RTW89_DECL_6GHZ_SPAN(6545, SUBBAND_6, SUBBAND_7_L),
248 RTW89_DECL_6GHZ_SPAN(6665, SUBBAND_7_L, SUBBAND_7_H),
249 RTW89_DECL_6GHZ_SPAN(6705, SUBBAND_7_L, SUBBAND_7_H),
250 RTW89_DECL_6GHZ_SPAN(6825, SUBBAND_7_H, SUBBAND_8),
251 RTW89_DECL_6GHZ_SPAN(6865, SUBBAND_7_H, SUBBAND_8),
252 RTW89_DECL_6GHZ_SPAN(6875, SUBBAND_7_H, SUBBAND_8),
253 RTW89_DECL_6GHZ_SPAN(6885, SUBBAND_7_H, SUBBAND_8),
254 };
255
256 const struct rtw89_6ghz_span *
rtw89_get_6ghz_span(struct rtw89_dev * rtwdev,u32 center_freq)257 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq)
258 {
259 int idx;
260
261 if (center_freq >= RTW89_6GHZ_SPAN_HEAD) {
262 idx = RTW89_6GHZ_SPAN_IDX(center_freq);
263 /* To decrease size of rtw89_overlapping_6ghz[],
264 * RTW89_6GHZ_SPAN_IDX() truncates the leading NULLs
265 * to make first span as index 0 of the table. So, if center
266 * frequency is less than the first one, it will get netative.
267 */
268 if (idx >= 0 && idx < ARRAY_SIZE(rtw89_overlapping_6ghz))
269 return &rtw89_overlapping_6ghz[idx];
270 }
271
272 return NULL;
273 }
274
rtw89_ra_report_to_bitrate(struct rtw89_dev * rtwdev,u8 rpt_rate,u16 * bitrate)275 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate)
276 {
277 struct ieee80211_rate rate;
278
279 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) {
280 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate);
281 return false;
282 }
283
284 rate = rtw89_bitrates[rpt_rate];
285 *bitrate = rate.bitrate;
286
287 return true;
288 }
289
290 static const struct ieee80211_supported_band rtw89_sband_2ghz = {
291 .band = NL80211_BAND_2GHZ,
292 .channels = rtw89_channels_2ghz,
293 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz),
294 .bitrates = rtw89_bitrates,
295 .n_bitrates = ARRAY_SIZE(rtw89_bitrates),
296 .ht_cap = {0},
297 .vht_cap = {0},
298 };
299
300 static const struct ieee80211_supported_band rtw89_sband_5ghz = {
301 .band = NL80211_BAND_5GHZ,
302 .channels = rtw89_channels_5ghz,
303 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz),
304
305 /* 5G has no CCK rates, 1M/2M/5.5M/11M */
306 .bitrates = rtw89_bitrates + 4,
307 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4,
308 .ht_cap = {0},
309 .vht_cap = {0},
310 };
311
312 static const struct ieee80211_supported_band rtw89_sband_6ghz = {
313 .band = NL80211_BAND_6GHZ,
314 .channels = rtw89_channels_6ghz,
315 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz),
316
317 /* 6G has no CCK rates, 1M/2M/5.5M/11M */
318 .bitrates = rtw89_bitrates + 4,
319 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4,
320 };
321
rtw89_traffic_stats_accu(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats,struct sk_buff * skb,bool tx)322 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev,
323 struct rtw89_traffic_stats *stats,
324 struct sk_buff *skb, bool tx)
325 {
326 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
327
328 if (tx && ieee80211_is_assoc_req(hdr->frame_control))
329 rtw89_wow_parse_akm(rtwdev, skb);
330
331 if (!ieee80211_is_data(hdr->frame_control))
332 return;
333
334 if (is_broadcast_ether_addr(hdr->addr1) ||
335 is_multicast_ether_addr(hdr->addr1))
336 return;
337
338 if (tx) {
339 stats->tx_cnt++;
340 stats->tx_unicast += skb->len;
341 } else {
342 stats->rx_cnt++;
343 stats->rx_unicast += skb->len;
344 }
345 }
346
rtw89_get_default_chandef(struct cfg80211_chan_def * chandef)347 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef)
348 {
349 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0],
350 NL80211_CHAN_NO_HT);
351 }
352
rtw89_get_channel_params(const struct cfg80211_chan_def * chandef,struct rtw89_chan * chan)353 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef,
354 struct rtw89_chan *chan)
355 {
356 struct ieee80211_channel *channel = chandef->chan;
357 enum nl80211_chan_width width = chandef->width;
358 u32 primary_freq, center_freq;
359 u8 center_chan;
360 u8 bandwidth = RTW89_CHANNEL_WIDTH_20;
361 u32 offset;
362 u8 band;
363
364 center_chan = channel->hw_value;
365 primary_freq = channel->center_freq;
366 center_freq = chandef->center_freq1;
367
368 switch (width) {
369 case NL80211_CHAN_WIDTH_20_NOHT:
370 case NL80211_CHAN_WIDTH_20:
371 bandwidth = RTW89_CHANNEL_WIDTH_20;
372 break;
373 case NL80211_CHAN_WIDTH_40:
374 bandwidth = RTW89_CHANNEL_WIDTH_40;
375 if (primary_freq > center_freq) {
376 center_chan -= 2;
377 } else {
378 center_chan += 2;
379 }
380 break;
381 case NL80211_CHAN_WIDTH_80:
382 case NL80211_CHAN_WIDTH_160:
383 bandwidth = nl_to_rtw89_bandwidth(width);
384 if (primary_freq > center_freq) {
385 offset = (primary_freq - center_freq - 10) / 20;
386 center_chan -= 2 + offset * 4;
387 } else {
388 offset = (center_freq - primary_freq - 10) / 20;
389 center_chan += 2 + offset * 4;
390 }
391 break;
392 default:
393 center_chan = 0;
394 break;
395 }
396
397 switch (channel->band) {
398 default:
399 case NL80211_BAND_2GHZ:
400 band = RTW89_BAND_2G;
401 break;
402 case NL80211_BAND_5GHZ:
403 band = RTW89_BAND_5G;
404 break;
405 case NL80211_BAND_6GHZ:
406 band = RTW89_BAND_6G;
407 break;
408 }
409
410 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth);
411 }
412
__rtw89_core_set_chip_txpwr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)413 static void __rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev,
414 const struct rtw89_chan *chan,
415 enum rtw89_phy_idx phy_idx)
416 {
417 const struct rtw89_chip_info *chip = rtwdev->chip;
418 bool entity_active;
419
420 entity_active = rtw89_get_entity_state(rtwdev, phy_idx);
421 if (!entity_active)
422 return;
423
424 chip->ops->set_txpwr(rtwdev, chan, phy_idx);
425 }
426
rtw89_core_set_chip_txpwr(struct rtw89_dev * rtwdev)427 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev)
428 {
429 const struct rtw89_chan *chan;
430
431 chan = rtw89_mgnt_chan_get(rtwdev, 0);
432 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_0);
433
434 if (!rtwdev->support_mlo)
435 return;
436
437 chan = rtw89_mgnt_chan_get(rtwdev, 1);
438 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_1);
439 }
440
__rtw89_set_channel(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)441 static void __rtw89_set_channel(struct rtw89_dev *rtwdev,
442 const struct rtw89_chan *chan,
443 enum rtw89_mac_idx mac_idx,
444 enum rtw89_phy_idx phy_idx)
445 {
446 const struct rtw89_chip_info *chip = rtwdev->chip;
447 const struct rtw89_chan_rcd *chan_rcd;
448 struct rtw89_channel_help_params bak;
449 bool entity_active;
450
451 entity_active = rtw89_get_entity_state(rtwdev, phy_idx);
452
453 chan_rcd = rtw89_chan_rcd_get_by_chan(chan);
454
455 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx);
456
457 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx);
458
459 chip->ops->set_txpwr(rtwdev, chan, phy_idx);
460
461 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx);
462
463 if (!entity_active || chan_rcd->band_changed) {
464 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type);
465 rtw89_chip_rfk_band_changed(rtwdev, phy_idx, chan);
466 }
467
468 rtw89_set_entity_state(rtwdev, phy_idx, true);
469 }
470
rtw89_set_channel(struct rtw89_dev * rtwdev)471 int rtw89_set_channel(struct rtw89_dev *rtwdev)
472 {
473 const struct rtw89_chan *chan;
474 enum rtw89_entity_mode mode;
475
476 mode = rtw89_entity_recalc(rtwdev);
477 if (mode < 0 || mode >= NUM_OF_RTW89_ENTITY_MODE) {
478 WARN(1, "Invalid ent mode: %d\n", mode);
479 return -EINVAL;
480 }
481
482 chan = rtw89_mgnt_chan_get(rtwdev, 0);
483 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_0, RTW89_PHY_0);
484
485 if (!rtwdev->support_mlo)
486 return 0;
487
488 chan = rtw89_mgnt_chan_get(rtwdev, 1);
489 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_1, RTW89_PHY_1);
490
491 return 0;
492 }
493
494 static enum rtw89_core_tx_type
rtw89_core_get_tx_type(struct rtw89_dev * rtwdev,struct sk_buff * skb)495 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev,
496 struct sk_buff *skb)
497 {
498 struct ieee80211_hdr *hdr = (void *)skb->data;
499 __le16 fc = hdr->frame_control;
500
501 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc))
502 return RTW89_CORE_TX_TYPE_MGMT;
503
504 return RTW89_CORE_TX_TYPE_DATA;
505 }
506
507 static void
rtw89_core_tx_update_ampdu_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)508 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev,
509 struct rtw89_core_tx_request *tx_req,
510 enum btc_pkt_type pkt_type)
511 {
512 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
513 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
514 struct ieee80211_link_sta *link_sta;
515 struct sk_buff *skb = tx_req->skb;
516 struct rtw89_sta *rtwsta;
517 u8 ampdu_num;
518 u8 tid;
519
520 if (pkt_type == PACKET_EAPOL) {
521 desc_info->bk = true;
522 return;
523 }
524
525 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU))
526 return;
527
528 if (!rtwsta_link) {
529 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n");
530 return;
531 }
532
533 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
534 rtwsta = rtwsta_link->rtwsta;
535
536 rcu_read_lock();
537
538 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
539 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ?
540 rtwsta->ampdu_params[tid].agg_num :
541 4 << link_sta->ht_cap.ampdu_factor) - 1);
542
543 desc_info->agg_en = true;
544 desc_info->ampdu_density = link_sta->ht_cap.ampdu_density;
545 desc_info->ampdu_num = ampdu_num;
546
547 rcu_read_unlock();
548 }
549
550 static void
rtw89_core_tx_update_sec_key(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)551 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev,
552 struct rtw89_core_tx_request *tx_req)
553 {
554 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
555 const struct rtw89_chip_info *chip = rtwdev->chip;
556 const struct rtw89_sec_cam_entry *sec_cam;
557 struct ieee80211_tx_info *info;
558 struct ieee80211_key_conf *key;
559 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
560 struct sk_buff *skb = tx_req->skb;
561 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE;
562 u8 sec_cam_idx;
563 u64 pn64;
564
565 info = IEEE80211_SKB_CB(skb);
566 key = info->control.hw_key;
567 sec_cam_idx = key->hw_key_idx;
568 sec_cam = cam_info->sec_entries[sec_cam_idx];
569 if (!sec_cam) {
570 rtw89_warn(rtwdev, "sec cam entry is empty\n");
571 return;
572 }
573
574 switch (key->cipher) {
575 case WLAN_CIPHER_SUITE_WEP40:
576 sec_type = RTW89_SEC_KEY_TYPE_WEP40;
577 break;
578 case WLAN_CIPHER_SUITE_WEP104:
579 sec_type = RTW89_SEC_KEY_TYPE_WEP104;
580 break;
581 case WLAN_CIPHER_SUITE_TKIP:
582 sec_type = RTW89_SEC_KEY_TYPE_TKIP;
583 break;
584 case WLAN_CIPHER_SUITE_CCMP:
585 sec_type = RTW89_SEC_KEY_TYPE_CCMP128;
586 break;
587 case WLAN_CIPHER_SUITE_CCMP_256:
588 sec_type = RTW89_SEC_KEY_TYPE_CCMP256;
589 break;
590 case WLAN_CIPHER_SUITE_GCMP:
591 sec_type = RTW89_SEC_KEY_TYPE_GCMP128;
592 break;
593 case WLAN_CIPHER_SUITE_GCMP_256:
594 sec_type = RTW89_SEC_KEY_TYPE_GCMP256;
595 break;
596 default:
597 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher);
598 return;
599 }
600
601 desc_info->sec_en = true;
602 desc_info->sec_keyid = key->keyidx;
603 desc_info->sec_type = sec_type;
604 desc_info->sec_cam_idx = sec_cam->sec_cam_idx;
605
606 if (!chip->hw_sec_hdr)
607 return;
608
609 pn64 = atomic64_inc_return(&key->tx_pn);
610 desc_info->sec_seq[0] = pn64;
611 desc_info->sec_seq[1] = pn64 >> 8;
612 desc_info->sec_seq[2] = pn64 >> 16;
613 desc_info->sec_seq[3] = pn64 >> 24;
614 desc_info->sec_seq[4] = pn64 >> 32;
615 desc_info->sec_seq[5] = pn64 >> 40;
616 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */
617 }
618
rtw89_core_get_mgmt_rate(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,const struct rtw89_chan * chan)619 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev,
620 struct rtw89_core_tx_request *tx_req,
621 const struct rtw89_chan *chan)
622 {
623 struct sk_buff *skb = tx_req->skb;
624 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
625 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
626 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
627 struct ieee80211_vif *vif = tx_info->control.vif;
628 struct ieee80211_bss_conf *bss_conf;
629 u16 lowest_rate;
630 u16 rate;
631
632 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE ||
633 (vif && vif->p2p))
634 lowest_rate = RTW89_HW_RATE_OFDM6;
635 else if (chan->band_type == RTW89_BAND_2G)
636 lowest_rate = RTW89_HW_RATE_CCK1;
637 else
638 lowest_rate = RTW89_HW_RATE_OFDM6;
639
640 if (!rtwvif_link)
641 return lowest_rate;
642
643 rcu_read_lock();
644
645 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
646 if (!bss_conf->basic_rates || !rtwsta_link) {
647 rate = lowest_rate;
648 goto out;
649 }
650
651 rate = __ffs(bss_conf->basic_rates) + lowest_rate;
652
653 out:
654 rcu_read_unlock();
655
656 return rate;
657 }
658
rtw89_core_tx_get_mac_id(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)659 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev,
660 struct rtw89_core_tx_request *tx_req)
661 {
662 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
663 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
664
665 if (!rtwsta_link)
666 return rtwvif_link->mac_id;
667
668 return rtwsta_link->mac_id;
669 }
670
rtw89_core_tx_update_llc_hdr(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,struct sk_buff * skb)671 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev,
672 struct rtw89_tx_desc_info *desc_info,
673 struct sk_buff *skb)
674 {
675 struct ieee80211_hdr *hdr = (void *)skb->data;
676 __le16 fc = hdr->frame_control;
677
678 desc_info->hdr_llc_len = ieee80211_hdrlen(fc);
679 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */
680 }
681
682 static void
rtw89_core_tx_update_mgmt_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)683 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev,
684 struct rtw89_core_tx_request *tx_req)
685 {
686 const struct rtw89_chip_info *chip = rtwdev->chip;
687 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
688 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
689 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
690 rtwvif_link->chanctx_idx);
691 struct sk_buff *skb = tx_req->skb;
692 u8 qsel, ch_dma;
693
694 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT;
695 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
696
697 desc_info->qsel = qsel;
698 desc_info->ch_dma = ch_dma;
699 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0;
700 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req);
701 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL;
702 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE;
703
704 /* fixed data rate for mgmt frames */
705 desc_info->en_wd_info = true;
706 desc_info->use_rate = true;
707 desc_info->dis_data_fb = true;
708 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan);
709
710 if (chip->hw_mgmt_tx_encrypt && IEEE80211_SKB_CB(skb)->control.hw_key) {
711 rtw89_core_tx_update_sec_key(rtwdev, tx_req);
712 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb);
713 }
714
715 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
716 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n",
717 desc_info->data_rate, chan->channel, chan->band_type,
718 chan->band_width);
719 }
720
721 static void
rtw89_core_tx_update_h2c_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)722 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev,
723 struct rtw89_core_tx_request *tx_req)
724 {
725 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
726
727 desc_info->is_bmc = false;
728 desc_info->wd_page = false;
729 desc_info->ch_dma = RTW89_DMA_H2C;
730 }
731
rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev * rtwdev,__le32 * htc,const struct rtw89_chan * chan)732 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc,
733 const struct rtw89_chan *chan)
734 {
735 static const u8 rtw89_bandwidth_to_om[] = {
736 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20,
737 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40,
738 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80,
739 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80,
740 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80,
741 };
742 const struct rtw89_chip_info *chip = rtwdev->chip;
743 struct rtw89_hal *hal = &rtwdev->hal;
744 u8 om_bandwidth;
745
746 if (!chip->dis_2g_40m_ul_ofdma ||
747 chan->band_type != RTW89_BAND_2G ||
748 chan->band_width != RTW89_CHANNEL_WIDTH_40)
749 return;
750
751 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ?
752 rtw89_bandwidth_to_om[chan->band_width] : 0;
753 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) |
754 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) |
755 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) |
756 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) |
757 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) |
758 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) |
759 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) |
760 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) |
761 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS);
762 }
763
764 static bool
__rtw89_core_tx_check_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)765 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev,
766 struct rtw89_core_tx_request *tx_req,
767 enum btc_pkt_type pkt_type)
768 {
769 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
770 struct sk_buff *skb = tx_req->skb;
771 struct ieee80211_hdr *hdr = (void *)skb->data;
772 struct ieee80211_link_sta *link_sta;
773 __le16 fc = hdr->frame_control;
774
775 /* AP IOT issue with EAPoL, ARP and DHCP */
776 if (pkt_type < PACKET_MAX)
777 return false;
778
779 if (!rtwsta_link)
780 return false;
781
782 rcu_read_lock();
783
784 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
785 if (!link_sta->he_cap.has_he) {
786 rcu_read_unlock();
787 return false;
788 }
789
790 rcu_read_unlock();
791
792 if (!ieee80211_is_data_qos(fc))
793 return false;
794
795 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN)
796 return false;
797
798 if (rtwsta_link && rtwsta_link->ra_report.might_fallback_legacy)
799 return false;
800
801 return true;
802 }
803
804 static void
__rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)805 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev,
806 struct rtw89_core_tx_request *tx_req)
807 {
808 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
809 struct sk_buff *skb = tx_req->skb;
810 struct ieee80211_hdr *hdr = (void *)skb->data;
811 __le16 fc = hdr->frame_control;
812 void *data;
813 __le32 *htc;
814 u8 *qc;
815 int hdr_len;
816
817 hdr_len = ieee80211_has_a4(fc) ? 32 : 26;
818 data = skb_push(skb, IEEE80211_HT_CTL_LEN);
819 #if defined(__linux__)
820 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len);
821 #elif defined(__FreeBSD__)
822 memmove(data, (u8 *)data + IEEE80211_HT_CTL_LEN, hdr_len);
823 #endif
824
825 hdr = data;
826 #if defined(__linux__)
827 htc = data + hdr_len;
828 #elif defined(__FreeBSD__)
829 htc = (__le32 *)((u8 *)data + hdr_len);
830 #endif
831 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER);
832 *htc = rtwsta_link->htc_template ? rtwsta_link->htc_template :
833 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) |
834 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID);
835
836 #if defined(__linux__)
837 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN;
838 #elif defined(__FreeBSD__)
839 qc = (u8 *)data + hdr_len - IEEE80211_QOS_CTL_LEN;
840 #endif
841 qc[0] |= IEEE80211_QOS_CTL_EOSP;
842 }
843
844 static void
rtw89_core_tx_update_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)845 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev,
846 struct rtw89_core_tx_request *tx_req,
847 enum btc_pkt_type pkt_type)
848 {
849 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
850 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
851
852 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type))
853 goto desc_bk;
854
855 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req);
856
857 desc_info->pkt_size += IEEE80211_HT_CTL_LEN;
858 desc_info->a_ctrl_bsr = true;
859
860 desc_bk:
861 if (!rtwvif_link || rtwvif_link->last_a_ctrl == desc_info->a_ctrl_bsr)
862 return;
863
864 rtwvif_link->last_a_ctrl = desc_info->a_ctrl_bsr;
865 desc_info->bk = true;
866 }
867
rtw89_core_get_data_rate(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)868 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev,
869 struct rtw89_core_tx_request *tx_req)
870 {
871 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
872 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
873 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
874 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern;
875 enum rtw89_chanctx_idx idx = rtwvif_link->chanctx_idx;
876 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx);
877 struct ieee80211_link_sta *link_sta;
878 u16 lowest_rate;
879 u16 rate;
880
881 if (rate_pattern->enable)
882 return rate_pattern->rate;
883
884 if (vif->p2p)
885 lowest_rate = RTW89_HW_RATE_OFDM6;
886 else if (chan->band_type == RTW89_BAND_2G)
887 lowest_rate = RTW89_HW_RATE_CCK1;
888 else
889 lowest_rate = RTW89_HW_RATE_OFDM6;
890
891 if (!rtwsta_link)
892 return lowest_rate;
893
894 rcu_read_lock();
895
896 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
897 if (!link_sta->supp_rates[chan->band_type]) {
898 rate = lowest_rate;
899 goto out;
900 }
901
902 rate = __ffs(link_sta->supp_rates[chan->band_type]) + lowest_rate;
903
904 out:
905 rcu_read_unlock();
906
907 return rate;
908 }
909
910 static void
rtw89_core_tx_update_data_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)911 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev,
912 struct rtw89_core_tx_request *tx_req)
913 {
914 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
915 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
916 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
917 struct sk_buff *skb = tx_req->skb;
918 u8 tid, tid_indicate;
919 u8 qsel, ch_dma;
920
921 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
922 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid);
923 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid);
924 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
925
926 desc_info->ch_dma = ch_dma;
927 desc_info->tid_indicate = tid_indicate;
928 desc_info->qsel = qsel;
929 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req);
930 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0;
931 desc_info->er_cap = rtwsta_link ? rtwsta_link->er_cap : false;
932 desc_info->stbc = rtwsta_link ? rtwsta_link->ra.stbc_cap : false;
933 desc_info->ldpc = rtwsta_link ? rtwsta_link->ra.ldpc_cap : false;
934
935 /* enable wd_info for AMPDU */
936 desc_info->en_wd_info = true;
937
938 if (IEEE80211_SKB_CB(skb)->control.hw_key)
939 rtw89_core_tx_update_sec_key(rtwdev, tx_req);
940
941 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req);
942 }
943
944 static enum btc_pkt_type
rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)945 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev,
946 struct rtw89_core_tx_request *tx_req)
947 {
948 struct sk_buff *skb = tx_req->skb;
949 struct udphdr *udphdr;
950
951 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) {
952 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work);
953 return PACKET_EAPOL;
954 }
955
956 if (skb->protocol == htons(ETH_P_ARP)) {
957 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work);
958 return PACKET_ARP;
959 }
960
961 if (skb->protocol == htons(ETH_P_IP) &&
962 ip_hdr(skb)->protocol == IPPROTO_UDP) {
963 udphdr = udp_hdr(skb);
964 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) ||
965 (udphdr->source == htons(68) && udphdr->dest == htons(67))) &&
966 skb->len > 282) {
967 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work);
968 return PACKET_DHCP;
969 }
970 }
971
972 if (skb->protocol == htons(ETH_P_IP) &&
973 ip_hdr(skb)->protocol == IPPROTO_ICMP) {
974 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work);
975 return PACKET_ICMP;
976 }
977
978 return PACKET_MAX;
979 }
980
981 static void
rtw89_core_tx_wake(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)982 rtw89_core_tx_wake(struct rtw89_dev *rtwdev,
983 struct rtw89_core_tx_request *tx_req)
984 {
985 const struct rtw89_chip_info *chip = rtwdev->chip;
986
987 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw))
988 return;
989
990 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags))
991 return;
992
993 if (chip->chip_id != RTL8852C &&
994 tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT)
995 return;
996
997 rtw89_mac_notify_wake(rtwdev);
998 }
999
1000 static void
rtw89_core_tx_update_desc_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)1001 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev,
1002 struct rtw89_core_tx_request *tx_req)
1003 {
1004 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
1005 struct sk_buff *skb = tx_req->skb;
1006 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1007 struct ieee80211_hdr *hdr = (void *)skb->data;
1008 struct rtw89_addr_cam_entry *addr_cam;
1009 enum rtw89_core_tx_type tx_type;
1010 enum btc_pkt_type pkt_type;
1011 bool upd_wlan_hdr = false;
1012 bool is_bmc;
1013 u16 seq;
1014
1015 if (tx_req->sta)
1016 desc_info->mlo = tx_req->sta->mlo;
1017 else if (tx_req->vif)
1018 desc_info->mlo = ieee80211_vif_is_mld(tx_req->vif);
1019
1020 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
1021 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) {
1022 tx_type = rtw89_core_get_tx_type(rtwdev, skb);
1023 tx_req->tx_type = tx_type;
1024
1025 addr_cam = rtw89_get_addr_cam_of(tx_req->rtwvif_link,
1026 tx_req->rtwsta_link);
1027 if (addr_cam->valid && desc_info->mlo)
1028 upd_wlan_hdr = true;
1029 }
1030 is_bmc = (is_broadcast_ether_addr(hdr->addr1) ||
1031 is_multicast_ether_addr(hdr->addr1));
1032
1033 desc_info->seq = seq;
1034 desc_info->pkt_size = skb->len;
1035 desc_info->is_bmc = is_bmc;
1036 desc_info->wd_page = true;
1037 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM;
1038 desc_info->upd_wlan_hdr = upd_wlan_hdr;
1039
1040 switch (tx_req->tx_type) {
1041 case RTW89_CORE_TX_TYPE_MGMT:
1042 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req);
1043 break;
1044 case RTW89_CORE_TX_TYPE_DATA:
1045 rtw89_core_tx_update_data_info(rtwdev, tx_req);
1046 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req);
1047 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type);
1048 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type);
1049 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb);
1050 break;
1051 case RTW89_CORE_TX_TYPE_FWCMD:
1052 rtw89_core_tx_update_h2c_info(rtwdev, tx_req);
1053 break;
1054 }
1055 }
1056
rtw89_core_tx_kick_off(struct rtw89_dev * rtwdev,u8 qsel)1057 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel)
1058 {
1059 u8 ch_dma;
1060
1061 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
1062
1063 rtw89_hci_tx_kick_off(rtwdev, ch_dma);
1064 }
1065
rtw89_core_tx_kick_off_and_wait(struct rtw89_dev * rtwdev,struct sk_buff * skb,int qsel,unsigned int timeout)1066 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
1067 int qsel, unsigned int timeout)
1068 {
1069 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb);
1070 struct rtw89_tx_wait_info *wait;
1071 unsigned long time_left;
1072 int ret = 0;
1073
1074 wait = kzalloc(sizeof(*wait), GFP_KERNEL);
1075 if (!wait) {
1076 rtw89_core_tx_kick_off(rtwdev, qsel);
1077 return 0;
1078 }
1079
1080 init_completion(&wait->completion);
1081 rcu_assign_pointer(skb_data->wait, wait);
1082
1083 rtw89_core_tx_kick_off(rtwdev, qsel);
1084 time_left = wait_for_completion_timeout(&wait->completion,
1085 msecs_to_jiffies(timeout));
1086 if (time_left == 0)
1087 ret = -ETIMEDOUT;
1088 else if (!wait->tx_done)
1089 ret = -EAGAIN;
1090
1091 rcu_assign_pointer(skb_data->wait, NULL);
1092 kfree_rcu(wait, rcu_head);
1093
1094 return ret;
1095 }
1096
rtw89_h2c_tx(struct rtw89_dev * rtwdev,struct sk_buff * skb,bool fwdl)1097 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
1098 struct sk_buff *skb, bool fwdl)
1099 {
1100 struct rtw89_core_tx_request tx_req = {0};
1101 u32 cnt;
1102 int ret;
1103
1104 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) {
1105 rtw89_debug(rtwdev, RTW89_DBG_FW,
1106 "ignore h2c due to power is off with firmware state=%d\n",
1107 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags));
1108 dev_kfree_skb(skb);
1109 return 0;
1110 }
1111
1112 tx_req.skb = skb;
1113 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD;
1114 if (fwdl)
1115 tx_req.desc_info.fw_dl = true;
1116
1117 rtw89_core_tx_update_desc_info(rtwdev, &tx_req);
1118
1119 if (!fwdl)
1120 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len);
1121
1122 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12);
1123 if (cnt == 0) {
1124 rtw89_err(rtwdev, "no tx fwcmd resource\n");
1125 return -ENOSPC;
1126 }
1127
1128 ret = rtw89_hci_tx_write(rtwdev, &tx_req);
1129 if (ret) {
1130 rtw89_err(rtwdev, "failed to transmit skb to HCI\n");
1131 return ret;
1132 }
1133 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12);
1134
1135 return 0;
1136 }
1137
rtw89_core_tx_write(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct sk_buff * skb,int * qsel)1138 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
1139 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel)
1140 {
1141 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
1142 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
1143 struct rtw89_core_tx_request tx_req = {0};
1144 struct rtw89_sta_link *rtwsta_link = NULL;
1145 struct rtw89_vif_link *rtwvif_link;
1146 int ret;
1147
1148 /* By default, driver writes tx via the link on HW-0. And then,
1149 * according to links' status, HW can change tx to another link.
1150 */
1151
1152 if (rtwsta) {
1153 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0);
1154 if (unlikely(!rtwsta_link)) {
1155 rtw89_err(rtwdev, "tx: find no sta link on HW-0\n");
1156 return -ENOLINK;
1157 }
1158 }
1159
1160 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, 0);
1161 if (unlikely(!rtwvif_link)) {
1162 rtw89_err(rtwdev, "tx: find no vif link on HW-0\n");
1163 return -ENOLINK;
1164 }
1165
1166 tx_req.skb = skb;
1167 tx_req.vif = vif;
1168 tx_req.sta = sta;
1169 tx_req.rtwvif_link = rtwvif_link;
1170 tx_req.rtwsta_link = rtwsta_link;
1171
1172 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true);
1173 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true);
1174 rtw89_core_tx_update_desc_info(rtwdev, &tx_req);
1175 rtw89_core_tx_wake(rtwdev, &tx_req);
1176
1177 ret = rtw89_hci_tx_write(rtwdev, &tx_req);
1178 if (ret) {
1179 rtw89_err(rtwdev, "failed to transmit skb to HCI\n");
1180 return ret;
1181 }
1182
1183 if (qsel)
1184 *qsel = tx_req.desc_info.qsel;
1185
1186 return 0;
1187 }
1188
rtw89_build_txwd_body0(struct rtw89_tx_desc_info * desc_info)1189 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info)
1190 {
1191 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) |
1192 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) |
1193 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) |
1194 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1195 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) |
1196 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) |
1197 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) |
1198 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode);
1199
1200 return cpu_to_le32(dword);
1201 }
1202
rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info * desc_info)1203 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info)
1204 {
1205 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) |
1206 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) |
1207 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) |
1208 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1209 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) |
1210 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl);
1211
1212 return cpu_to_le32(dword);
1213 }
1214
rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info * desc_info)1215 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info)
1216 {
1217 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) |
1218 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) |
1219 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type);
1220
1221 return cpu_to_le32(dword);
1222 }
1223
rtw89_build_txwd_body2(struct rtw89_tx_desc_info * desc_info)1224 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info)
1225 {
1226 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) |
1227 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) |
1228 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) |
1229 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id);
1230
1231 return cpu_to_le32(dword);
1232 }
1233
rtw89_build_txwd_body3(struct rtw89_tx_desc_info * desc_info)1234 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info)
1235 {
1236 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) |
1237 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) |
1238 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk);
1239
1240 return cpu_to_le32(dword);
1241 }
1242
rtw89_build_txwd_body4(struct rtw89_tx_desc_info * desc_info)1243 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info)
1244 {
1245 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) |
1246 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]);
1247
1248 return cpu_to_le32(dword);
1249 }
1250
rtw89_build_txwd_body5(struct rtw89_tx_desc_info * desc_info)1251 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info)
1252 {
1253 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) |
1254 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) |
1255 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) |
1256 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]);
1257
1258 return cpu_to_le32(dword);
1259 }
1260
rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info * desc_info)1261 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info)
1262 {
1263 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) |
1264 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate);
1265
1266 return cpu_to_le32(dword);
1267 }
1268
rtw89_build_txwd_info0(struct rtw89_tx_desc_info * desc_info)1269 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info)
1270 {
1271 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) |
1272 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) |
1273 FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) |
1274 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) |
1275 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1276 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port);
1277
1278 return cpu_to_le32(dword);
1279 }
1280
rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info * desc_info)1281 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info)
1282 {
1283 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) |
1284 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) |
1285 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1286 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) |
1287 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) |
1288 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0);
1289
1290 return cpu_to_le32(dword);
1291 }
1292
rtw89_build_txwd_info1(struct rtw89_tx_desc_info * desc_info)1293 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info)
1294 {
1295 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) |
1296 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) |
1297 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE,
1298 desc_info->data_retry_lowest_rate);
1299
1300 return cpu_to_le32(dword);
1301 }
1302
rtw89_build_txwd_info2(struct rtw89_tx_desc_info * desc_info)1303 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info)
1304 {
1305 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1306 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) |
1307 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) |
1308 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1309
1310 return cpu_to_le32(dword);
1311 }
1312
rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info * desc_info)1313 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info)
1314 {
1315 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1316 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) |
1317 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1318
1319 return cpu_to_le32(dword);
1320 }
1321
rtw89_build_txwd_info4(struct rtw89_tx_desc_info * desc_info)1322 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info)
1323 {
1324 bool rts_en = !desc_info->is_bmc;
1325 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) |
1326 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1);
1327
1328 return cpu_to_le32(dword);
1329 }
1330
rtw89_core_fill_txdesc(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1331 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
1332 struct rtw89_tx_desc_info *desc_info,
1333 void *txdesc)
1334 {
1335 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc;
1336 struct rtw89_txwd_info *txwd_info;
1337
1338 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info);
1339 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info);
1340 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info);
1341
1342 if (!desc_info->en_wd_info)
1343 return;
1344
1345 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1);
1346 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info);
1347 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info);
1348 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info);
1349 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info);
1350
1351 }
1352 EXPORT_SYMBOL(rtw89_core_fill_txdesc);
1353
rtw89_core_fill_txdesc_v1(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1354 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
1355 struct rtw89_tx_desc_info *desc_info,
1356 void *txdesc)
1357 {
1358 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc;
1359 struct rtw89_txwd_info *txwd_info;
1360
1361 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info);
1362 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info);
1363 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info);
1364 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info);
1365 if (desc_info->sec_en) {
1366 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info);
1367 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info);
1368 }
1369 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info);
1370
1371 if (!desc_info->en_wd_info)
1372 return;
1373
1374 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1);
1375 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info);
1376 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info);
1377 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info);
1378 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info);
1379 }
1380 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1);
1381
rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info * desc_info)1382 static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info)
1383 {
1384 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) |
1385 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) |
1386 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) |
1387 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1388 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page);
1389
1390 return cpu_to_le32(dword);
1391 }
1392
rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info * desc_info)1393 static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info)
1394 {
1395 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) |
1396 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) |
1397 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type);
1398
1399 return cpu_to_le32(dword);
1400 }
1401
rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info * desc_info)1402 static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info)
1403 {
1404 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) |
1405 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) |
1406 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) |
1407 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) |
1408 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) |
1409 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id);
1410
1411 return cpu_to_le32(dword);
1412 }
1413
rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info * desc_info)1414 static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info)
1415 {
1416 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq);
1417
1418 return cpu_to_le32(dword);
1419 }
1420
rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info * desc_info)1421 static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info)
1422 {
1423 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) |
1424 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]);
1425
1426 return cpu_to_le32(dword);
1427 }
1428
rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info * desc_info)1429 static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info)
1430 {
1431 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) |
1432 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) |
1433 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) |
1434 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]);
1435
1436 return cpu_to_le32(dword);
1437 }
1438
rtw89_build_txwd_body6_v2(struct rtw89_tx_desc_info * desc_info)1439 static __le32 rtw89_build_txwd_body6_v2(struct rtw89_tx_desc_info *desc_info)
1440 {
1441 u32 dword = FIELD_PREP(BE_TXD_BODY6_UPD_WLAN_HDR, desc_info->upd_wlan_hdr);
1442
1443 return cpu_to_le32(dword);
1444 }
1445
rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info * desc_info)1446 static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info)
1447 {
1448 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) |
1449 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) |
1450 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) |
1451 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate);
1452
1453 return cpu_to_le32(dword);
1454 }
1455
rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info * desc_info)1456 static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info)
1457 {
1458 u32 dword = FIELD_PREP(BE_TXD_INFO0_DATA_STBC, desc_info->stbc) |
1459 FIELD_PREP(BE_TXD_INFO0_DATA_LDPC, desc_info->ldpc) |
1460 FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1461 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port);
1462
1463 return cpu_to_le32(dword);
1464 }
1465
rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info * desc_info)1466 static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info)
1467 {
1468 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) |
1469 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) |
1470 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE,
1471 desc_info->data_retry_lowest_rate);
1472
1473 return cpu_to_le32(dword);
1474 }
1475
rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info * desc_info)1476 static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info)
1477 {
1478 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1479 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) |
1480 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1481
1482 return cpu_to_le32(dword);
1483 }
1484
rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info * desc_info)1485 static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info)
1486 {
1487 bool rts_en = !desc_info->is_bmc;
1488 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, rts_en) |
1489 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1);
1490
1491 return cpu_to_le32(dword);
1492 }
1493
rtw89_core_fill_txdesc_v2(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1494 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev,
1495 struct rtw89_tx_desc_info *desc_info,
1496 void *txdesc)
1497 {
1498 struct rtw89_txwd_body_v2 *txwd_body = txdesc;
1499 struct rtw89_txwd_info_v2 *txwd_info;
1500
1501 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info);
1502 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info);
1503 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info);
1504 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info);
1505 if (desc_info->sec_en) {
1506 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info);
1507 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info);
1508 }
1509 txwd_body->dword6 = rtw89_build_txwd_body6_v2(desc_info);
1510 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info);
1511
1512 if (!desc_info->en_wd_info)
1513 return;
1514
1515 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1);
1516 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info);
1517 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info);
1518 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info);
1519 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info);
1520 }
1521 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2);
1522
rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info * desc_info)1523 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info)
1524 {
1525 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) |
1526 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ?
1527 RTW89_CORE_RX_TYPE_FWDL :
1528 RTW89_CORE_RX_TYPE_H2C);
1529
1530 return cpu_to_le32(dword);
1531 }
1532
rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1533 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
1534 struct rtw89_tx_desc_info *desc_info,
1535 void *txdesc)
1536 {
1537 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc;
1538
1539 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info);
1540 }
1541 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1);
1542
rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info * desc_info)1543 static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info)
1544 {
1545 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) |
1546 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ?
1547 RTW89_CORE_RX_TYPE_FWDL :
1548 RTW89_CORE_RX_TYPE_H2C);
1549
1550 return cpu_to_le32(dword);
1551 }
1552
rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1553 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev,
1554 struct rtw89_tx_desc_info *desc_info,
1555 void *txdesc)
1556 {
1557 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc;
1558
1559 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info);
1560 }
1561 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2);
1562
rtw89_core_rx_process_mac_ppdu(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct rtw89_rx_phy_ppdu * phy_ppdu)1563 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev,
1564 struct sk_buff *skb,
1565 struct rtw89_rx_phy_ppdu *phy_ppdu)
1566 {
1567 const struct rtw89_chip_info *chip = rtwdev->chip;
1568 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data;
1569 const struct rtw89_rxinfo_user *user;
1570 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
1571 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE;
1572 bool rx_cnt_valid = false;
1573 bool invalid = false;
1574 u8 plcp_size = 0;
1575 u8 *phy_sts;
1576 u8 usr_num;
1577 int i;
1578
1579 if (chip_gen == RTW89_CHIP_BE) {
1580 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1);
1581 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1;
1582 }
1583
1584 if (invalid)
1585 return -EINVAL;
1586
1587 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD);
1588 if (chip_gen == RTW89_CHIP_BE) {
1589 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3;
1590 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1);
1591 } else {
1592 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3;
1593 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM);
1594 }
1595 if (usr_num > chip->ppdu_max_usr) {
1596 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n",
1597 usr_num);
1598 return -EINVAL;
1599 }
1600
1601 for (i = 0; i < usr_num; i++) {
1602 user = &rxinfo->user[i];
1603 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID))
1604 continue;
1605 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set
1606 * by hardware, so update mac_id by rxinfo_user[].mac_id.
1607 */
1608 if (chip_gen == RTW89_CHIP_BE)
1609 phy_ppdu->mac_id =
1610 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID);
1611 phy_ppdu->has_data =
1612 le32_get_bits(user->w0, RTW89_RXINFO_USER_DATA);
1613 phy_ppdu->has_bcn =
1614 le32_get_bits(user->w0, RTW89_RXINFO_USER_BCN);
1615 break;
1616 }
1617
1618 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE;
1619 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE;
1620 /* 8-byte alignment */
1621 if (usr_num & BIT(0))
1622 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE;
1623 if (rx_cnt_valid)
1624 phy_sts += rx_cnt_size;
1625 phy_sts += plcp_size;
1626
1627 if (phy_sts > skb->data + skb->len)
1628 return -EINVAL;
1629
1630 phy_ppdu->buf = phy_sts;
1631 phy_ppdu->len = skb->data + skb->len - phy_sts;
1632
1633 return 0;
1634 }
1635
rtw89_get_data_rate_nss(struct rtw89_dev * rtwdev,u16 data_rate)1636 static u8 rtw89_get_data_rate_nss(struct rtw89_dev *rtwdev, u16 data_rate)
1637 {
1638 u8 data_rate_mode;
1639
1640 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
1641 switch (data_rate_mode) {
1642 case DATA_RATE_MODE_NON_HT:
1643 return 1;
1644 case DATA_RATE_MODE_HT:
1645 return rtw89_get_data_ht_nss(rtwdev, data_rate) + 1;
1646 case DATA_RATE_MODE_VHT:
1647 case DATA_RATE_MODE_HE:
1648 case DATA_RATE_MODE_EHT:
1649 return rtw89_get_data_nss(rtwdev, data_rate) + 1;
1650 default:
1651 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
1652 return 0;
1653 }
1654 }
1655
rtw89_core_rx_process_phy_ppdu_iter(void * data,struct ieee80211_sta * sta)1656 static void rtw89_core_rx_process_phy_ppdu_iter(void *data,
1657 struct ieee80211_sta *sta)
1658 {
1659 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data;
1660 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
1661 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
1662 struct rtw89_hal *hal = &rtwdev->hal;
1663 struct rtw89_sta_link *rtwsta_link;
1664 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
1665 u8 ant_pos = U8_MAX;
1666 u8 evm_pos = 0;
1667 int i;
1668
1669 /* FIXME: For single link, taking link on HW-0 here is okay. But, when
1670 * enabling multiple active links, we should determine the right link.
1671 */
1672 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0);
1673 if (unlikely(!rtwsta_link))
1674 return;
1675
1676 if (rtwsta_link->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self)
1677 return;
1678
1679 if (hal->ant_diversity && hal->antenna_rx) {
1680 ant_pos = __ffs(hal->antenna_rx);
1681 evm_pos = ant_pos;
1682 }
1683
1684 ewma_rssi_add(&rtwsta_link->avg_rssi, phy_ppdu->rssi_avg);
1685
1686 if (ant_pos < ant_num) {
1687 ewma_rssi_add(&rtwsta_link->rssi[ant_pos], phy_ppdu->rssi[0]);
1688 } else {
1689 for (i = 0; i < rtwdev->chip->rf_path_num; i++)
1690 ewma_rssi_add(&rtwsta_link->rssi[i], phy_ppdu->rssi[i]);
1691 }
1692
1693 if (phy_ppdu->ofdm.has && (phy_ppdu->has_data || phy_ppdu->has_bcn)) {
1694 ewma_snr_add(&rtwsta_link->avg_snr, phy_ppdu->ofdm.avg_snr);
1695 if (rtw89_get_data_rate_nss(rtwdev, phy_ppdu->rate) == 1) {
1696 ewma_evm_add(&rtwsta_link->evm_1ss, phy_ppdu->ofdm.evm_min);
1697 } else {
1698 ewma_evm_add(&rtwsta_link->evm_min[evm_pos],
1699 phy_ppdu->ofdm.evm_min);
1700 ewma_evm_add(&rtwsta_link->evm_max[evm_pos],
1701 phy_ppdu->ofdm.evm_max);
1702 }
1703 }
1704 }
1705
1706 #define VAR_LEN 0xff
1707 #define VAR_LEN_UNIT 8
rtw89_core_get_phy_status_ie_len(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr)1708 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev,
1709 const struct rtw89_phy_sts_iehdr *iehdr)
1710 {
1711 static const u8 physts_ie_len_tabs[RTW89_CHIP_GEN_NUM][32] = {
1712 [RTW89_CHIP_AX] = {
1713 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN,
1714 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN,
1715 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32
1716 },
1717 [RTW89_CHIP_BE] = {
1718 32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN,
1719 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN,
1720 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32
1721 },
1722 };
1723 const u8 *physts_ie_len_tab;
1724 u16 ie_len;
1725 u8 ie;
1726
1727 physts_ie_len_tab = physts_ie_len_tabs[rtwdev->chip->chip_gen];
1728
1729 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE);
1730 if (physts_ie_len_tab[ie] != VAR_LEN)
1731 ie_len = physts_ie_len_tab[ie];
1732 else
1733 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT;
1734
1735 return ie_len;
1736 }
1737
rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1738 static void rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev *rtwdev,
1739 const struct rtw89_phy_sts_iehdr *iehdr,
1740 struct rtw89_rx_phy_ppdu *phy_ppdu)
1741 {
1742 const struct rtw89_phy_sts_ie01_v2 *ie;
1743 u8 *rpl_fd = phy_ppdu->rpl_fd;
1744
1745 ie = (const struct rtw89_phy_sts_ie01_v2 *)iehdr;
1746 rpl_fd[RF_PATH_A] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_A);
1747 rpl_fd[RF_PATH_B] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_B);
1748 rpl_fd[RF_PATH_C] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_C);
1749 rpl_fd[RF_PATH_D] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_D);
1750
1751 phy_ppdu->bw_idx = le32_get_bits(ie->w5, RTW89_PHY_STS_IE01_V2_W5_BW_IDX);
1752 }
1753
rtw89_core_parse_phy_status_ie01(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1754 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev,
1755 const struct rtw89_phy_sts_iehdr *iehdr,
1756 struct rtw89_rx_phy_ppdu *phy_ppdu)
1757 {
1758 const struct rtw89_phy_sts_ie01 *ie = (const struct rtw89_phy_sts_ie01 *)iehdr;
1759 s16 cfo;
1760 u32 t;
1761
1762 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX);
1763
1764 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
1765 phy_ppdu->ldpc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_LDPC);
1766 phy_ppdu->stbc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_STBC);
1767 }
1768
1769 if (!phy_ppdu->hdr_2_en)
1770 phy_ppdu->rx_path_en =
1771 le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RX_PATH_EN);
1772
1773 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6)
1774 return;
1775
1776 if (!phy_ppdu->to_self)
1777 return;
1778
1779 phy_ppdu->rpl_avg = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RSSI_AVG_FD);
1780 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR);
1781 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX);
1782 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN);
1783 phy_ppdu->ofdm.has = true;
1784
1785 /* sign conversion for S(12,2) */
1786 if (rtwdev->chip->cfo_src_fd) {
1787 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO);
1788 cfo = sign_extend32(t, 11);
1789 } else {
1790 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO);
1791 cfo = sign_extend32(t, 11);
1792 }
1793
1794 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu);
1795
1796 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
1797 rtw89_core_parse_phy_status_ie01_v2(rtwdev, iehdr, phy_ppdu);
1798 }
1799
rtw89_core_parse_phy_status_ie00(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1800 static void rtw89_core_parse_phy_status_ie00(struct rtw89_dev *rtwdev,
1801 const struct rtw89_phy_sts_iehdr *iehdr,
1802 struct rtw89_rx_phy_ppdu *phy_ppdu)
1803 {
1804 const struct rtw89_phy_sts_ie00 *ie = (const struct rtw89_phy_sts_ie00 *)iehdr;
1805 u16 tmp_rpl;
1806
1807 tmp_rpl = le32_get_bits(ie->w0, RTW89_PHY_STS_IE00_W0_RPL);
1808 phy_ppdu->rpl_avg = tmp_rpl >> 1;
1809 }
1810
rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1811 static void rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev *rtwdev,
1812 const struct rtw89_phy_sts_iehdr *iehdr,
1813 struct rtw89_rx_phy_ppdu *phy_ppdu)
1814 {
1815 const struct rtw89_phy_sts_ie00_v2 *ie;
1816 u8 *rpl_path = phy_ppdu->rpl_path;
1817 u16 tmp_rpl[RF_PATH_MAX];
1818 u8 i;
1819
1820 ie = (const struct rtw89_phy_sts_ie00_v2 *)iehdr;
1821 tmp_rpl[RF_PATH_A] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_A);
1822 tmp_rpl[RF_PATH_B] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_B);
1823 tmp_rpl[RF_PATH_C] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_C);
1824 tmp_rpl[RF_PATH_D] = le32_get_bits(ie->w5, RTW89_PHY_STS_IE00_V2_W5_RPL_TD_D);
1825
1826 for (i = 0; i < RF_PATH_MAX; i++)
1827 rpl_path[i] = tmp_rpl[i] >> 1;
1828 }
1829
rtw89_core_process_phy_status_ie(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1830 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev,
1831 const struct rtw89_phy_sts_iehdr *iehdr,
1832 struct rtw89_rx_phy_ppdu *phy_ppdu)
1833 {
1834 u8 ie;
1835
1836 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE);
1837
1838 switch (ie) {
1839 case RTW89_PHYSTS_IE00_CMN_CCK:
1840 rtw89_core_parse_phy_status_ie00(rtwdev, iehdr, phy_ppdu);
1841 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
1842 rtw89_core_parse_phy_status_ie00_v2(rtwdev, iehdr, phy_ppdu);
1843 break;
1844 case RTW89_PHYSTS_IE01_CMN_OFDM:
1845 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu);
1846 break;
1847 default:
1848 break;
1849 }
1850
1851 return 0;
1852 }
1853
rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu * phy_ppdu)1854 static void rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu *phy_ppdu)
1855 {
1856 #if defined(__linux__)
1857 const struct rtw89_phy_sts_hdr_v2 *hdr = phy_ppdu->buf + PHY_STS_HDR_LEN;
1858 #elif defined(__FreeBSD__)
1859 const struct rtw89_phy_sts_hdr_v2 *hdr = (void *)((u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN);
1860 #endif
1861
1862 phy_ppdu->rx_path_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_V2_W0_PATH_EN);
1863 }
1864
rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu * phy_ppdu)1865 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu)
1866 {
1867 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf;
1868 u8 *rssi = phy_ppdu->rssi;
1869
1870 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP);
1871 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG);
1872 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A);
1873 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B);
1874 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C);
1875 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D);
1876
1877 phy_ppdu->hdr_2_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_HDR_2_EN);
1878 if (phy_ppdu->hdr_2_en)
1879 rtw89_core_update_phy_ppdu_hdr_v2(phy_ppdu);
1880 }
1881
rtw89_core_rx_process_phy_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1882 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev,
1883 struct rtw89_rx_phy_ppdu *phy_ppdu)
1884 {
1885 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf;
1886 u32 len_from_header;
1887 bool physts_valid;
1888
1889 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID);
1890 if (!physts_valid)
1891 return -EINVAL;
1892
1893 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3;
1894
1895 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
1896 len_from_header += PHY_STS_HDR_LEN;
1897
1898 if (len_from_header != phy_ppdu->len) {
1899 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n");
1900 return -EINVAL;
1901 }
1902 rtw89_core_update_phy_ppdu(phy_ppdu);
1903
1904 return 0;
1905 }
1906
rtw89_core_rx_parse_phy_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1907 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev,
1908 struct rtw89_rx_phy_ppdu *phy_ppdu)
1909 {
1910 u16 ie_len;
1911 #if defined(__linux__)
1912 void *pos, *end;
1913 #elif defined(__FreeBSD__)
1914 u8 *pos, *end;
1915 #endif
1916
1917 /* mark invalid reports and bypass them */
1918 if (phy_ppdu->ie < RTW89_CCK_PKT)
1919 return -EINVAL;
1920
1921 #if defined(__linux__)
1922 pos = phy_ppdu->buf + PHY_STS_HDR_LEN;
1923 end = phy_ppdu->buf + phy_ppdu->len;
1924 #elif defined(__FreeBSD__)
1925 pos = (u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN;
1926 end = (u8 *)phy_ppdu->buf + phy_ppdu->len;
1927 #endif
1928 while (pos < end) {
1929 #if defined(__linux__)
1930 const struct rtw89_phy_sts_iehdr *iehdr = pos;
1931 #elif defined(__FreeBSD__)
1932 const struct rtw89_phy_sts_iehdr *iehdr = (void *)pos;
1933 #endif
1934
1935 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr);
1936 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu);
1937 pos += ie_len;
1938 if (pos > end || ie_len == 0) {
1939 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
1940 "phy status parse failed\n");
1941 return -EINVAL;
1942 }
1943 }
1944
1945 rtw89_chip_convert_rpl_to_rssi(rtwdev, phy_ppdu);
1946 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu);
1947
1948 return 0;
1949 }
1950
rtw89_core_rx_process_phy_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1951 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev,
1952 struct rtw89_rx_phy_ppdu *phy_ppdu)
1953 {
1954 int ret;
1955
1956 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu);
1957 if (ret)
1958 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n");
1959 else
1960 phy_ppdu->valid = true;
1961
1962 ieee80211_iterate_stations_atomic(rtwdev->hw,
1963 rtw89_core_rx_process_phy_ppdu_iter,
1964 phy_ppdu);
1965 }
1966
rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev * rtwdev,u8 desc_info_gi,bool rx_status)1967 static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev,
1968 u8 desc_info_gi,
1969 bool rx_status)
1970 {
1971 switch (desc_info_gi) {
1972 case RTW89_GILTF_SGI_4XHE08:
1973 case RTW89_GILTF_2XHE08:
1974 case RTW89_GILTF_1XHE08:
1975 return NL80211_RATE_INFO_HE_GI_0_8;
1976 case RTW89_GILTF_2XHE16:
1977 case RTW89_GILTF_1XHE16:
1978 return NL80211_RATE_INFO_HE_GI_1_6;
1979 case RTW89_GILTF_LGI_4XHE32:
1980 return NL80211_RATE_INFO_HE_GI_3_2;
1981 default:
1982 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi);
1983 if (rx_status)
1984 return NL80211_RATE_INFO_HE_GI_3_2;
1985 return U8_MAX;
1986 }
1987 }
1988
rtw89_rxdesc_to_nl_eht_gi(struct rtw89_dev * rtwdev,u8 desc_info_gi,bool rx_status)1989 static u8 rtw89_rxdesc_to_nl_eht_gi(struct rtw89_dev *rtwdev,
1990 u8 desc_info_gi,
1991 bool rx_status)
1992 {
1993 switch (desc_info_gi) {
1994 case RTW89_GILTF_SGI_4XHE08:
1995 case RTW89_GILTF_2XHE08:
1996 case RTW89_GILTF_1XHE08:
1997 return NL80211_RATE_INFO_EHT_GI_0_8;
1998 case RTW89_GILTF_2XHE16:
1999 case RTW89_GILTF_1XHE16:
2000 return NL80211_RATE_INFO_EHT_GI_1_6;
2001 case RTW89_GILTF_LGI_4XHE32:
2002 return NL80211_RATE_INFO_EHT_GI_3_2;
2003 default:
2004 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi);
2005 if (rx_status)
2006 return NL80211_RATE_INFO_EHT_GI_3_2;
2007 return U8_MAX;
2008 }
2009 }
2010
rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev * rtwdev,u8 desc_info_gi,bool rx_status,bool eht)2011 static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev,
2012 u8 desc_info_gi,
2013 bool rx_status, bool eht)
2014 {
2015 return eht ? rtw89_rxdesc_to_nl_eht_gi(rtwdev, desc_info_gi, rx_status) :
2016 rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info_gi, rx_status);
2017 }
2018
2019 static
rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status * status,u8 gi_ltf,bool eht)2020 bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf,
2021 bool eht)
2022 {
2023 if (eht)
2024 return status->eht.gi == gi_ltf;
2025
2026 return status->he_gi == gi_ltf;
2027 }
2028
rtw89_core_rx_ppdu_match(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * status)2029 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev,
2030 struct rtw89_rx_desc_info *desc_info,
2031 struct ieee80211_rx_status *status)
2032 {
2033 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
2034 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf;
2035 bool eht = false;
2036 u16 data_rate;
2037 bool ret;
2038
2039 data_rate = desc_info->data_rate;
2040 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
2041 if (data_rate_mode == DATA_RATE_MODE_NON_HT) {
2042 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate);
2043 /* rate_idx is still hardware value here */
2044 } else if (data_rate_mode == DATA_RATE_MODE_HT) {
2045 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate);
2046 } else if (data_rate_mode == DATA_RATE_MODE_VHT ||
2047 data_rate_mode == DATA_RATE_MODE_HE ||
2048 data_rate_mode == DATA_RATE_MODE_EHT) {
2049 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
2050 } else {
2051 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
2052 }
2053
2054 eht = data_rate_mode == DATA_RATE_MODE_EHT;
2055 bw = rtw89_hw_to_rate_info_bw(desc_info->bw);
2056 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, false, eht);
2057 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt &&
2058 status->rate_idx == rate_idx &&
2059 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) &&
2060 status->bw == bw;
2061
2062 return ret;
2063 }
2064
2065 struct rtw89_vif_rx_stats_iter_data {
2066 struct rtw89_dev *rtwdev;
2067 struct rtw89_rx_phy_ppdu *phy_ppdu;
2068 struct rtw89_rx_desc_info *desc_info;
2069 struct sk_buff *skb;
2070 const u8 *bssid;
2071 };
2072
rtw89_stats_trigger_frame(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct ieee80211_bss_conf * bss_conf,struct sk_buff * skb)2073 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev,
2074 struct rtw89_vif_link *rtwvif_link,
2075 struct ieee80211_bss_conf *bss_conf,
2076 struct sk_buff *skb)
2077 {
2078 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data;
2079 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
2080 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
2081 u8 *pos, *end, type, tf_bw;
2082 u16 aid, tf_rua;
2083
2084 if (!ether_addr_equal(bss_conf->bssid, tf->ta) ||
2085 rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION ||
2086 rtwvif_link->net_type == RTW89_NET_TYPE_NO_LINK)
2087 return;
2088
2089 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK);
2090 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR)
2091 return;
2092
2093 end = (u8 *)tf + skb->len;
2094 pos = tf->variable;
2095
2096 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) {
2097 aid = RTW89_GET_TF_USER_INFO_AID12(pos);
2098 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos);
2099 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK);
2100 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2101 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n",
2102 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos),
2103 tf_rua, tf_bw);
2104
2105 if (aid == RTW89_TF_PAD)
2106 break;
2107
2108 if (aid == vif->cfg.aid) {
2109 enum nl80211_he_ru_alloc rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1);
2110
2111 rtwvif->stats.rx_tf_acc++;
2112 rtwdev->stats.rx_tf_acc++;
2113 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ &&
2114 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106)
2115 rtwvif_link->pwr_diff_en = true;
2116 break;
2117 }
2118
2119 pos += RTW89_TF_BASIC_USER_INFO_SZ;
2120 }
2121 }
2122
rtw89_cancel_6ghz_probe_work(struct work_struct * work)2123 static void rtw89_cancel_6ghz_probe_work(struct work_struct *work)
2124 {
2125 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
2126 cancel_6ghz_probe_work);
2127 struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
2128 struct rtw89_pktofld_info *info;
2129
2130 mutex_lock(&rtwdev->mutex);
2131
2132 if (!rtwdev->scanning)
2133 goto out;
2134
2135 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) {
2136 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload))
2137 continue;
2138
2139 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
2140
2141 /* Don't delete/free info from pkt_list at this moment. Let it
2142 * be deleted/freed in rtw89_release_pkt_list() after scanning,
2143 * since if during scanning, pkt_list is accessed in bottom half.
2144 */
2145 }
2146
2147 out:
2148 mutex_unlock(&rtwdev->mutex);
2149 }
2150
rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev * rtwdev,struct sk_buff * skb)2151 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev,
2152 struct sk_buff *skb)
2153 {
2154 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
2155 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
2156 struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
2157 struct rtw89_pktofld_info *info;
2158 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie;
2159 bool queue_work = false;
2160
2161 if (rx_status->band != NL80211_BAND_6GHZ)
2162 return;
2163
2164 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len);
2165
2166 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) {
2167 if (ether_addr_equal(info->bssid, mgmt->bssid)) {
2168 info->cancel = true;
2169 queue_work = true;
2170 continue;
2171 }
2172
2173 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0)
2174 continue;
2175
2176 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) {
2177 info->cancel = true;
2178 queue_work = true;
2179 }
2180 }
2181
2182 if (queue_work)
2183 ieee80211_queue_work(rtwdev->hw, &rtwdev->cancel_6ghz_probe_work);
2184 }
2185
rtw89_vif_sync_bcn_tsf(struct rtw89_vif_link * rtwvif_link,struct ieee80211_hdr * hdr,size_t len)2186 static void rtw89_vif_sync_bcn_tsf(struct rtw89_vif_link *rtwvif_link,
2187 struct ieee80211_hdr *hdr, size_t len)
2188 {
2189 struct ieee80211_mgmt *mgmt = (typeof(mgmt))hdr;
2190
2191 if (len < offsetof(typeof(*mgmt), u.beacon.variable))
2192 return;
2193
2194 WRITE_ONCE(rtwvif_link->sync_bcn_tsf, le64_to_cpu(mgmt->u.beacon.timestamp));
2195 }
2196
rtw89_vif_rx_stats_iter(void * data,u8 * mac,struct ieee80211_vif * vif)2197 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac,
2198 struct ieee80211_vif *vif)
2199 {
2200 struct rtw89_vif_rx_stats_iter_data *iter_data = data;
2201 struct rtw89_dev *rtwdev = iter_data->rtwdev;
2202 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
2203 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat;
2204 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info;
2205 struct sk_buff *skb = iter_data->skb;
2206 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2207 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu;
2208 struct ieee80211_bss_conf *bss_conf;
2209 struct rtw89_vif_link *rtwvif_link;
2210 const u8 *bssid = iter_data->bssid;
2211
2212 if (rtwdev->scanning &&
2213 (ieee80211_is_beacon(hdr->frame_control) ||
2214 ieee80211_is_probe_resp(hdr->frame_control)))
2215 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb);
2216
2217 rcu_read_lock();
2218
2219 /* FIXME: For single link, taking link on HW-0 here is okay. But, when
2220 * enabling multiple active links, we should determine the right link.
2221 */
2222 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, 0);
2223 if (unlikely(!rtwvif_link))
2224 goto out;
2225
2226 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
2227 if (!bss_conf->bssid)
2228 goto out;
2229
2230 if (ieee80211_is_trigger(hdr->frame_control)) {
2231 rtw89_stats_trigger_frame(rtwdev, rtwvif_link, bss_conf, skb);
2232 goto out;
2233 }
2234
2235 if (!ether_addr_equal(bss_conf->bssid, bssid))
2236 goto out;
2237
2238 if (ieee80211_is_beacon(hdr->frame_control)) {
2239 if (vif->type == NL80211_IFTYPE_STATION &&
2240 !test_bit(RTW89_FLAG_WOWLAN, rtwdev->flags)) {
2241 rtw89_vif_sync_bcn_tsf(rtwvif_link, hdr, skb->len);
2242 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu);
2243 }
2244 pkt_stat->beacon_nr++;
2245
2246 if (phy_ppdu)
2247 ewma_rssi_add(&rtwdev->phystat.bcn_rssi, phy_ppdu->rssi_avg);
2248
2249 pkt_stat->beacon_rate = desc_info->data_rate;
2250 }
2251
2252 if (!ether_addr_equal(bss_conf->addr, hdr->addr1))
2253 goto out;
2254
2255 if (desc_info->data_rate < RTW89_HW_RATE_NR)
2256 pkt_stat->rx_rate_cnt[desc_info->data_rate]++;
2257
2258 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false);
2259
2260 out:
2261 rcu_read_unlock();
2262 }
2263
rtw89_core_rx_stats(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2264 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev,
2265 struct rtw89_rx_phy_ppdu *phy_ppdu,
2266 struct rtw89_rx_desc_info *desc_info,
2267 struct sk_buff *skb)
2268 {
2269 struct rtw89_vif_rx_stats_iter_data iter_data;
2270
2271 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false);
2272
2273 iter_data.rtwdev = rtwdev;
2274 iter_data.phy_ppdu = phy_ppdu;
2275 iter_data.desc_info = desc_info;
2276 iter_data.skb = skb;
2277 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data);
2278 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data);
2279 }
2280
rtw89_correct_cck_chan(struct rtw89_dev * rtwdev,struct ieee80211_rx_status * status)2281 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev,
2282 struct ieee80211_rx_status *status)
2283 {
2284 const struct rtw89_chan_rcd *rcd =
2285 rtw89_chan_rcd_get(rtwdev, RTW89_CHANCTX_0);
2286 u16 chan = rcd->prev_primary_channel;
2287 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type);
2288
2289 if (status->band != NL80211_BAND_2GHZ &&
2290 status->encoding == RX_ENC_LEGACY &&
2291 status->rate_idx < RTW89_HW_RATE_OFDM6) {
2292 status->freq = ieee80211_channel_to_frequency(chan, band);
2293 status->band = band;
2294 }
2295 }
2296
rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status * rx_status)2297 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status)
2298 {
2299 if (rx_status->band == NL80211_BAND_2GHZ ||
2300 rx_status->encoding != RX_ENC_LEGACY)
2301 return;
2302
2303 /* Some control frames' freq(ACKs in this case) are reported wrong due
2304 * to FW notify timing, set to lowest rate to prevent overflow.
2305 */
2306 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) {
2307 rx_status->rate_idx = 0;
2308 return;
2309 }
2310
2311 /* No 4 CCK rates for non-2G */
2312 rx_status->rate_idx -= 4;
2313 }
2314
2315 static
rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev * rtwdev,struct ieee80211_rx_status * rx_status,struct rtw89_rx_phy_ppdu * phy_ppdu)2316 void rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev *rtwdev,
2317 struct ieee80211_rx_status *rx_status,
2318 struct rtw89_rx_phy_ppdu *phy_ppdu)
2319 {
2320 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR))
2321 return;
2322
2323 if (!phy_ppdu)
2324 return;
2325
2326 if (phy_ppdu->ldpc)
2327 rx_status->enc_flags |= RX_ENC_FLAG_LDPC;
2328 if (phy_ppdu->stbc)
2329 rx_status->enc_flags |= u8_encode_bits(1, RX_ENC_FLAG_STBC_MASK);
2330 }
2331
2332 static const u8 rx_status_bw_to_radiotap_eht_usig[] = {
2333 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ,
2334 [RATE_INFO_BW_5] = U8_MAX,
2335 [RATE_INFO_BW_10] = U8_MAX,
2336 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ,
2337 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ,
2338 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ,
2339 [RATE_INFO_BW_HE_RU] = U8_MAX,
2340 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1,
2341 [RATE_INFO_BW_EHT_RU] = U8_MAX,
2342 };
2343
rtw89_core_update_radiotap_eht(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status)2344 static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev,
2345 struct sk_buff *skb,
2346 struct ieee80211_rx_status *rx_status)
2347 {
2348 struct ieee80211_radiotap_eht_usig *usig;
2349 struct ieee80211_radiotap_eht *eht;
2350 struct ieee80211_radiotap_tlv *tlv;
2351 int eht_len = struct_size(eht, user_info, 1);
2352 int usig_len = sizeof(*usig);
2353 int len;
2354 u8 bw;
2355
2356 len = sizeof(*tlv) + ALIGN(eht_len, 4) +
2357 sizeof(*tlv) + ALIGN(usig_len, 4);
2358
2359 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END;
2360 skb_reset_mac_header(skb);
2361
2362 /* EHT */
2363 tlv = skb_push(skb, len);
2364 memset(tlv, 0, len);
2365 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT);
2366 tlv->len = cpu_to_le16(eht_len);
2367
2368 eht = (struct ieee80211_radiotap_eht *)tlv->data;
2369 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI);
2370 eht->data[0] =
2371 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI);
2372
2373 eht->user_info[0] =
2374 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN |
2375 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O |
2376 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN);
2377 eht->user_info[0] |=
2378 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) |
2379 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O);
2380 if (rx_status->enc_flags & RX_ENC_FLAG_LDPC)
2381 eht->user_info[0] |=
2382 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_CODING);
2383
2384 /* U-SIG */
2385 #if defined(__linux__)
2386 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4);
2387 #elif defined(__FreeBSD__)
2388 tlv = (void *)((u8 *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4));
2389 #endif
2390 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG);
2391 tlv->len = cpu_to_le16(usig_len);
2392
2393 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig))
2394 return;
2395
2396 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw];
2397 if (bw == U8_MAX)
2398 return;
2399
2400 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data;
2401 usig->common =
2402 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) |
2403 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW);
2404 }
2405
rtw89_core_update_radiotap(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status)2406 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev,
2407 struct sk_buff *skb,
2408 struct ieee80211_rx_status *rx_status)
2409 {
2410 static const struct ieee80211_radiotap_he known_he = {
2411 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2412 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN |
2413 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN |
2414 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2415 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2416 };
2417 struct ieee80211_radiotap_he *he;
2418
2419 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR))
2420 return;
2421
2422 if (rx_status->encoding == RX_ENC_HE) {
2423 rx_status->flag |= RX_FLAG_RADIOTAP_HE;
2424 he = skb_push(skb, sizeof(*he));
2425 *he = known_he;
2426 } else if (rx_status->encoding == RX_ENC_EHT) {
2427 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status);
2428 }
2429 }
2430
rtw89_core_validate_rx_signal(struct ieee80211_rx_status * rx_status)2431 static void rtw89_core_validate_rx_signal(struct ieee80211_rx_status *rx_status)
2432 {
2433 if (!rx_status->signal)
2434 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
2435 }
2436
rtw89_core_rx_to_mac80211(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb_ppdu,struct ieee80211_rx_status * rx_status)2437 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev,
2438 struct rtw89_rx_phy_ppdu *phy_ppdu,
2439 struct rtw89_rx_desc_info *desc_info,
2440 struct sk_buff *skb_ppdu,
2441 struct ieee80211_rx_status *rx_status)
2442 {
2443 struct napi_struct *napi = &rtwdev->napi;
2444
2445 /* In low power mode, napi isn't scheduled. Receive it to netif. */
2446 if (unlikely(!napi_is_scheduled(napi)))
2447 napi = NULL;
2448
2449 rtw89_core_hw_to_sband_rate(rx_status);
2450 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu);
2451 rtw89_core_update_rx_status_by_ppdu(rtwdev, rx_status, phy_ppdu);
2452 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status);
2453 rtw89_core_validate_rx_signal(rx_status);
2454
2455 /* In low power mode, it does RX in thread context. */
2456 local_bh_disable();
2457 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi);
2458 local_bh_enable();
2459 rtwdev->napi_budget_countdown--;
2460 }
2461
rtw89_core_rx_pending_skb(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2462 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev,
2463 struct rtw89_rx_phy_ppdu *phy_ppdu,
2464 struct rtw89_rx_desc_info *desc_info,
2465 struct sk_buff *skb)
2466 {
2467 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
2468 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band];
2469 struct sk_buff *skb_ppdu = NULL, *tmp;
2470 struct ieee80211_rx_status *rx_status;
2471
2472 if (curr > RTW89_MAX_PPDU_CNT)
2473 return;
2474
2475 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) {
2476 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]);
2477 rx_status = IEEE80211_SKB_RXCB(skb_ppdu);
2478 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status))
2479 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status);
2480 rtw89_correct_cck_chan(rtwdev, rx_status);
2481 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status);
2482 }
2483 }
2484
rtw89_core_rx_process_ppdu_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2485 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev,
2486 struct rtw89_rx_desc_info *desc_info,
2487 struct sk_buff *skb)
2488 {
2489 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false,
2490 .len = skb->len,
2491 .to_self = desc_info->addr1_match,
2492 .rate = desc_info->data_rate,
2493 .mac_id = desc_info->mac_id};
2494 int ret;
2495
2496 if (desc_info->mac_info_valid) {
2497 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu);
2498 if (ret)
2499 goto out;
2500 }
2501
2502 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu);
2503 if (ret)
2504 goto out;
2505
2506 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu);
2507
2508 out:
2509 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb);
2510 dev_kfree_skb_any(skb);
2511 }
2512
rtw89_core_rx_process_report(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2513 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev,
2514 struct rtw89_rx_desc_info *desc_info,
2515 struct sk_buff *skb)
2516 {
2517 switch (desc_info->pkt_type) {
2518 case RTW89_CORE_RX_TYPE_C2H:
2519 rtw89_fw_c2h_irqsafe(rtwdev, skb);
2520 break;
2521 case RTW89_CORE_RX_TYPE_PPDU_STAT:
2522 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb);
2523 break;
2524 default:
2525 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n",
2526 desc_info->pkt_type);
2527 dev_kfree_skb_any(skb);
2528 break;
2529 }
2530 }
2531
rtw89_core_query_rxdesc(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)2532 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
2533 struct rtw89_rx_desc_info *desc_info,
2534 u8 *data, u32 data_offset)
2535 {
2536 const struct rtw89_chip_info *chip = rtwdev->chip;
2537 struct rtw89_rxdesc_short *rxd_s;
2538 struct rtw89_rxdesc_long *rxd_l;
2539 u8 shift_len, drv_info_len;
2540
2541 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset);
2542 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK);
2543 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK);
2544 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD);
2545 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK);
2546 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD);
2547 if (chip->chip_id == RTL8852C)
2548 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK);
2549 else
2550 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK);
2551 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK);
2552 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK);
2553 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK);
2554 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN);
2555 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK);
2556 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK);
2557 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK);
2558 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR);
2559 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR);
2560 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC);
2561 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC);
2562 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH);
2563
2564 shift_len = desc_info->shift << 1; /* 2-byte unit */
2565 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
2566 desc_info->offset = data_offset + shift_len + drv_info_len;
2567 if (desc_info->long_rxdesc)
2568 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long);
2569 else
2570 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short);
2571 desc_info->ready = true;
2572
2573 if (!desc_info->long_rxdesc)
2574 return;
2575
2576 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset);
2577 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK);
2578 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD);
2579 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK);
2580 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK);
2581 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK);
2582 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK);
2583 }
2584 EXPORT_SYMBOL(rtw89_core_query_rxdesc);
2585
rtw89_core_query_rxdesc_v2(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)2586 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev,
2587 struct rtw89_rx_desc_info *desc_info,
2588 u8 *data, u32 data_offset)
2589 {
2590 struct rtw89_rxdesc_phy_rpt_v2 *rxd_rpt;
2591 struct rtw89_rxdesc_short_v2 *rxd_s;
2592 struct rtw89_rxdesc_long_v2 *rxd_l;
2593 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len;
2594
2595 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset);
2596
2597 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK);
2598 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK);
2599 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK);
2600 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK);
2601 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK);
2602 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD);
2603 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK);
2604 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT)
2605 desc_info->mac_info_valid = true;
2606
2607 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK);
2608 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK);
2609 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD);
2610
2611 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR);
2612 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR);
2613 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC);
2614 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC);
2615 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH);
2616
2617 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK);
2618 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK);
2619 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK);
2620 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK);
2621 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK);
2622
2623 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5);
2624
2625 shift_len = desc_info->shift << 1; /* 2-byte unit */
2626 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
2627 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */
2628 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */
2629 desc_info->offset = data_offset + shift_len + drv_info_len +
2630 phy_rtp_len + hdr_cnv_len;
2631
2632 if (desc_info->long_rxdesc)
2633 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2);
2634 else
2635 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2);
2636 desc_info->ready = true;
2637
2638 if (phy_rtp_len == sizeof(*rxd_rpt)) {
2639 rxd_rpt = (struct rtw89_rxdesc_phy_rpt_v2 *)(data + data_offset +
2640 desc_info->rxd_len);
2641 desc_info->rssi = le32_get_bits(rxd_rpt->dword0, BE_RXD_PHY_RSSI);
2642 }
2643
2644 if (!desc_info->long_rxdesc)
2645 return;
2646
2647 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset);
2648
2649 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN);
2650 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK);
2651 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK);
2652 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK);
2653
2654 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK);
2655 }
2656 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2);
2657
2658 struct rtw89_core_iter_rx_status {
2659 struct rtw89_dev *rtwdev;
2660 struct ieee80211_rx_status *rx_status;
2661 struct rtw89_rx_desc_info *desc_info;
2662 u8 mac_id;
2663 };
2664
2665 static
rtw89_core_stats_sta_rx_status_iter(void * data,struct ieee80211_sta * sta)2666 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta)
2667 {
2668 struct rtw89_core_iter_rx_status *iter_data =
2669 (struct rtw89_core_iter_rx_status *)data;
2670 struct ieee80211_rx_status *rx_status = iter_data->rx_status;
2671 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info;
2672 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
2673 struct rtw89_sta_link *rtwsta_link;
2674 u8 mac_id = iter_data->mac_id;
2675
2676 /* FIXME: For single link, taking link on HW-0 here is okay. But, when
2677 * enabling multiple active links, we should determine the right link.
2678 */
2679 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0);
2680 if (unlikely(!rtwsta_link))
2681 return;
2682
2683 if (mac_id != rtwsta_link->mac_id)
2684 return;
2685
2686 rtwsta_link->rx_status = *rx_status;
2687 rtwsta_link->rx_hw_rate = desc_info->data_rate;
2688 }
2689
rtw89_core_stats_sta_rx_status(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)2690 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev,
2691 struct rtw89_rx_desc_info *desc_info,
2692 struct ieee80211_rx_status *rx_status)
2693 {
2694 struct rtw89_core_iter_rx_status iter_data;
2695
2696 if (!desc_info->addr1_match || !desc_info->long_rxdesc)
2697 return;
2698
2699 if (desc_info->frame_type != RTW89_RX_TYPE_DATA)
2700 return;
2701
2702 iter_data.rtwdev = rtwdev;
2703 iter_data.rx_status = rx_status;
2704 iter_data.desc_info = desc_info;
2705 iter_data.mac_id = desc_info->mac_id;
2706 ieee80211_iterate_stations_atomic(rtwdev->hw,
2707 rtw89_core_stats_sta_rx_status_iter,
2708 &iter_data);
2709 }
2710
rtw89_core_update_rx_status(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)2711 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev,
2712 struct rtw89_rx_desc_info *desc_info,
2713 struct ieee80211_rx_status *rx_status)
2714 {
2715 const struct cfg80211_chan_def *chandef =
2716 rtw89_chandef_get(rtwdev, RTW89_CHANCTX_0);
2717 u16 data_rate;
2718 u8 data_rate_mode;
2719 bool eht = false;
2720 u8 gi;
2721
2722 /* currently using single PHY */
2723 rx_status->freq = chandef->chan->center_freq;
2724 rx_status->band = chandef->chan->band;
2725
2726 if (rtwdev->scanning &&
2727 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) {
2728 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev);
2729 u8 chan = cur->primary_channel;
2730 u8 band = cur->band_type;
2731 enum nl80211_band nl_band;
2732
2733 nl_band = rtw89_hw_to_nl80211_band(band);
2734 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band);
2735 rx_status->band = nl_band;
2736 }
2737
2738 if (desc_info->icv_err || desc_info->crc32_err)
2739 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2740
2741 if (desc_info->hw_dec &&
2742 !(desc_info->sw_dec || desc_info->icv_err))
2743 rx_status->flag |= RX_FLAG_DECRYPTED;
2744
2745 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw);
2746
2747 data_rate = desc_info->data_rate;
2748 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
2749 if (data_rate_mode == DATA_RATE_MODE_NON_HT) {
2750 rx_status->encoding = RX_ENC_LEGACY;
2751 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate);
2752 /* convert rate_idx after we get the correct band */
2753 } else if (data_rate_mode == DATA_RATE_MODE_HT) {
2754 rx_status->encoding = RX_ENC_HT;
2755 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate);
2756 if (desc_info->gi_ltf)
2757 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2758 } else if (data_rate_mode == DATA_RATE_MODE_VHT) {
2759 rx_status->encoding = RX_ENC_VHT;
2760 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
2761 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
2762 if (desc_info->gi_ltf)
2763 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2764 } else if (data_rate_mode == DATA_RATE_MODE_HE) {
2765 rx_status->encoding = RX_ENC_HE;
2766 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
2767 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
2768 } else if (data_rate_mode == DATA_RATE_MODE_EHT) {
2769 rx_status->encoding = RX_ENC_EHT;
2770 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
2771 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
2772 eht = true;
2773 } else {
2774 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
2775 }
2776
2777 /* he_gi is used to match ppdu, so we always fill it. */
2778 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht);
2779 if (eht)
2780 rx_status->eht.gi = gi;
2781 else
2782 rx_status->he_gi = gi;
2783 rx_status->flag |= RX_FLAG_MACTIME_START;
2784 rx_status->mactime = desc_info->free_run_cnt;
2785
2786 rtw89_chip_phy_rpt_to_rssi(rtwdev, desc_info, rx_status);
2787 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status);
2788 }
2789
rtw89_update_ps_mode(struct rtw89_dev * rtwdev)2790 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev)
2791 {
2792 const struct rtw89_chip_info *chip = rtwdev->chip;
2793
2794 if (rtw89_disable_ps_mode || !chip->ps_mode_supported ||
2795 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw))
2796 return RTW89_PS_MODE_NONE;
2797
2798 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) &&
2799 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw))
2800 return RTW89_PS_MODE_PWR_GATED;
2801
2802 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED))
2803 return RTW89_PS_MODE_CLK_GATED;
2804
2805 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF))
2806 return RTW89_PS_MODE_RFOFF;
2807
2808 return RTW89_PS_MODE_NONE;
2809 }
2810
rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info)2811 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev,
2812 struct rtw89_rx_desc_info *desc_info)
2813 {
2814 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts;
2815 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
2816 struct ieee80211_rx_status *rx_status;
2817 struct sk_buff *skb_ppdu, *tmp;
2818
2819 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) {
2820 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]);
2821 rx_status = IEEE80211_SKB_RXCB(skb_ppdu);
2822 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status);
2823 }
2824 }
2825
2826 static
rtw89_core_rx_pkt_hdl(struct rtw89_dev * rtwdev,const struct sk_buff * skb,const struct rtw89_rx_desc_info * desc)2827 void rtw89_core_rx_pkt_hdl(struct rtw89_dev *rtwdev, const struct sk_buff *skb,
2828 const struct rtw89_rx_desc_info *desc)
2829 {
2830 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2831 struct rtw89_sta_link *rtwsta_link;
2832 struct ieee80211_sta *sta;
2833 struct rtw89_sta *rtwsta;
2834 u8 macid = desc->mac_id;
2835
2836 if (!refcount_read(&rtwdev->refcount_ap_info))
2837 return;
2838
2839 rcu_read_lock();
2840
2841 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, macid);
2842 if (!rtwsta_link)
2843 goto out;
2844
2845 rtwsta = rtwsta_link->rtwsta;
2846 if (!test_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags))
2847 goto out;
2848
2849 sta = rtwsta_to_sta(rtwsta);
2850 if (ieee80211_is_pspoll(hdr->frame_control))
2851 ieee80211_sta_pspoll(sta);
2852 else if (ieee80211_has_pm(hdr->frame_control) &&
2853 (ieee80211_is_data_qos(hdr->frame_control) ||
2854 ieee80211_is_qos_nullfunc(hdr->frame_control)))
2855 ieee80211_sta_uapsd_trigger(sta, ieee80211_get_tid(hdr));
2856
2857 out:
2858 rcu_read_unlock();
2859 }
2860
rtw89_core_rx(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2861 void rtw89_core_rx(struct rtw89_dev *rtwdev,
2862 struct rtw89_rx_desc_info *desc_info,
2863 struct sk_buff *skb)
2864 {
2865 struct ieee80211_rx_status *rx_status;
2866 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts;
2867 u8 ppdu_cnt = desc_info->ppdu_cnt;
2868 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
2869
2870 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) {
2871 rtw89_core_rx_process_report(rtwdev, desc_info, skb);
2872 return;
2873 }
2874
2875 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) {
2876 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info);
2877 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt;
2878 }
2879
2880 rx_status = IEEE80211_SKB_RXCB(skb);
2881 memset(rx_status, 0, sizeof(*rx_status));
2882 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status);
2883 rtw89_core_rx_pkt_hdl(rtwdev, skb, desc_info);
2884 if (desc_info->long_rxdesc &&
2885 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP)
2886 skb_queue_tail(&ppdu_sts->rx_queue[band], skb);
2887 else
2888 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status);
2889 }
2890 EXPORT_SYMBOL(rtw89_core_rx);
2891
rtw89_core_napi_start(struct rtw89_dev * rtwdev)2892 void rtw89_core_napi_start(struct rtw89_dev *rtwdev)
2893 {
2894 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags))
2895 return;
2896
2897 napi_enable(&rtwdev->napi);
2898 }
2899 EXPORT_SYMBOL(rtw89_core_napi_start);
2900
rtw89_core_napi_stop(struct rtw89_dev * rtwdev)2901 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev)
2902 {
2903 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags))
2904 return;
2905
2906 napi_synchronize(&rtwdev->napi);
2907 napi_disable(&rtwdev->napi);
2908 }
2909 EXPORT_SYMBOL(rtw89_core_napi_stop);
2910
rtw89_core_napi_init(struct rtw89_dev * rtwdev)2911 int rtw89_core_napi_init(struct rtw89_dev *rtwdev)
2912 {
2913 rtwdev->netdev = alloc_netdev_dummy(0);
2914 if (!rtwdev->netdev)
2915 return -ENOMEM;
2916
2917 netif_napi_add(rtwdev->netdev, &rtwdev->napi,
2918 rtwdev->hci.ops->napi_poll);
2919 return 0;
2920 }
2921 EXPORT_SYMBOL(rtw89_core_napi_init);
2922
rtw89_core_napi_deinit(struct rtw89_dev * rtwdev)2923 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev)
2924 {
2925 rtw89_core_napi_stop(rtwdev);
2926 netif_napi_del(&rtwdev->napi);
2927 free_netdev(rtwdev->netdev);
2928 }
2929 EXPORT_SYMBOL(rtw89_core_napi_deinit);
2930
rtw89_core_ba_work(struct work_struct * work)2931 static void rtw89_core_ba_work(struct work_struct *work)
2932 {
2933 struct rtw89_dev *rtwdev =
2934 container_of(work, struct rtw89_dev, ba_work);
2935 struct rtw89_txq *rtwtxq, *tmp;
2936 int ret;
2937
2938 spin_lock_bh(&rtwdev->ba_lock);
2939 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) {
2940 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2941 struct ieee80211_sta *sta = txq->sta;
2942 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
2943 u8 tid = txq->tid;
2944
2945 if (!sta) {
2946 rtw89_warn(rtwdev, "cannot start BA without sta\n");
2947 goto skip_ba_work;
2948 }
2949
2950 if (rtwsta->disassoc) {
2951 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2952 "cannot start BA with disassoc sta\n");
2953 goto skip_ba_work;
2954 }
2955
2956 ret = ieee80211_start_tx_ba_session(sta, tid, 0);
2957 if (ret) {
2958 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2959 "failed to setup BA session for %pM:%2d: %d\n",
2960 sta->addr, tid, ret);
2961 if (ret == -EINVAL)
2962 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags);
2963 }
2964 skip_ba_work:
2965 list_del_init(&rtwtxq->list);
2966 }
2967 spin_unlock_bh(&rtwdev->ba_lock);
2968 }
2969
rtw89_core_free_sta_pending_ba(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)2970 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev,
2971 struct ieee80211_sta *sta)
2972 {
2973 struct rtw89_txq *rtwtxq, *tmp;
2974
2975 spin_lock_bh(&rtwdev->ba_lock);
2976 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) {
2977 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2978
2979 if (sta == txq->sta)
2980 list_del_init(&rtwtxq->list);
2981 }
2982 spin_unlock_bh(&rtwdev->ba_lock);
2983 }
2984
rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)2985 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev,
2986 struct ieee80211_sta *sta)
2987 {
2988 struct rtw89_txq *rtwtxq, *tmp;
2989
2990 spin_lock_bh(&rtwdev->ba_lock);
2991 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) {
2992 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2993
2994 if (sta == txq->sta) {
2995 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
2996 list_del_init(&rtwtxq->list);
2997 }
2998 }
2999 spin_unlock_bh(&rtwdev->ba_lock);
3000 }
3001
rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)3002 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev,
3003 struct ieee80211_sta *sta)
3004 {
3005 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
3006 struct sk_buff *skb, *tmp;
3007
3008 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) {
3009 skb_unlink(skb, &rtwsta->roc_queue);
3010 dev_kfree_skb_any(skb);
3011 }
3012 }
3013
rtw89_core_stop_tx_ba_session(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq)3014 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev,
3015 struct rtw89_txq *rtwtxq)
3016 {
3017 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
3018 struct ieee80211_sta *sta = txq->sta;
3019 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
3020
3021 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc))
3022 return;
3023
3024 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) ||
3025 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
3026 return;
3027
3028 spin_lock_bh(&rtwdev->ba_lock);
3029 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
3030 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list);
3031 spin_unlock_bh(&rtwdev->ba_lock);
3032
3033 ieee80211_stop_tx_ba_session(sta, txq->tid);
3034 cancel_delayed_work(&rtwdev->forbid_ba_work);
3035 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work,
3036 RTW89_FORBID_BA_TIMER);
3037 }
3038
rtw89_core_txq_check_agg(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq,struct sk_buff * skb)3039 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev,
3040 struct rtw89_txq *rtwtxq,
3041 struct sk_buff *skb)
3042 {
3043 struct ieee80211_hw *hw = rtwdev->hw;
3044 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
3045 struct ieee80211_sta *sta = txq->sta;
3046 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
3047
3048 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
3049 return;
3050
3051 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
3052 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq);
3053 return;
3054 }
3055
3056 if (unlikely(!sta))
3057 return;
3058
3059 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags)))
3060 return;
3061
3062 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) {
3063 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU;
3064 return;
3065 }
3066
3067 spin_lock_bh(&rtwdev->ba_lock);
3068 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) {
3069 list_add_tail(&rtwtxq->list, &rtwdev->ba_list);
3070 ieee80211_queue_work(hw, &rtwdev->ba_work);
3071 }
3072 spin_unlock_bh(&rtwdev->ba_lock);
3073 }
3074
rtw89_core_txq_push(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq,unsigned long frame_cnt,unsigned long byte_cnt)3075 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev,
3076 struct rtw89_txq *rtwtxq,
3077 unsigned long frame_cnt,
3078 unsigned long byte_cnt)
3079 {
3080 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
3081 struct ieee80211_vif *vif = txq->vif;
3082 struct ieee80211_sta *sta = txq->sta;
3083 struct sk_buff *skb;
3084 unsigned long i;
3085 int ret;
3086
3087 rcu_read_lock();
3088 for (i = 0; i < frame_cnt; i++) {
3089 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq);
3090 if (!skb) {
3091 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n");
3092 goto out;
3093 }
3094 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb);
3095 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL);
3096 if (ret) {
3097 rtw89_err(rtwdev, "failed to push txq: %d\n", ret);
3098 ieee80211_free_txskb(rtwdev->hw, skb);
3099 break;
3100 }
3101 }
3102 out:
3103 rcu_read_unlock();
3104 }
3105
rtw89_check_and_reclaim_tx_resource(struct rtw89_dev * rtwdev,u8 tid)3106 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid)
3107 {
3108 u8 qsel, ch_dma;
3109
3110 qsel = rtw89_core_get_qsel(rtwdev, tid);
3111 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
3112
3113 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma);
3114 }
3115
rtw89_core_txq_agg_wait(struct rtw89_dev * rtwdev,struct ieee80211_txq * txq,unsigned long * frame_cnt,bool * sched_txq,bool * reinvoke)3116 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev,
3117 struct ieee80211_txq *txq,
3118 unsigned long *frame_cnt,
3119 bool *sched_txq, bool *reinvoke)
3120 {
3121 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv;
3122 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(txq->sta);
3123 struct rtw89_sta_link *rtwsta_link;
3124
3125 if (!rtwsta)
3126 return false;
3127
3128 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0);
3129 if (unlikely(!rtwsta_link)) {
3130 rtw89_err(rtwdev, "agg wait: find no link on HW-0\n");
3131 return false;
3132 }
3133
3134 if (rtwsta_link->max_agg_wait <= 0)
3135 return false;
3136
3137 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID)
3138 return false;
3139
3140 if (*frame_cnt > 1) {
3141 *frame_cnt -= 1;
3142 *sched_txq = true;
3143 *reinvoke = true;
3144 rtwtxq->wait_cnt = 1;
3145 return false;
3146 }
3147
3148 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta_link->max_agg_wait) {
3149 *reinvoke = true;
3150 rtwtxq->wait_cnt++;
3151 return true;
3152 }
3153
3154 rtwtxq->wait_cnt = 0;
3155 return false;
3156 }
3157
rtw89_core_txq_schedule(struct rtw89_dev * rtwdev,u8 ac,bool * reinvoke)3158 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke)
3159 {
3160 struct ieee80211_hw *hw = rtwdev->hw;
3161 struct ieee80211_txq *txq;
3162 struct rtw89_vif *rtwvif;
3163 struct rtw89_txq *rtwtxq;
3164 unsigned long frame_cnt;
3165 unsigned long byte_cnt;
3166 u32 tx_resource;
3167 bool sched_txq;
3168
3169 ieee80211_txq_schedule_start(hw, ac);
3170 while ((txq = ieee80211_next_txq(hw, ac))) {
3171 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
3172 rtwvif = vif_to_rtwvif(txq->vif);
3173
3174 if (rtwvif->offchan) {
3175 ieee80211_return_txq(hw, txq, true);
3176 continue;
3177 }
3178 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid);
3179 sched_txq = false;
3180
3181 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt);
3182 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) {
3183 ieee80211_return_txq(hw, txq, true);
3184 continue;
3185 }
3186 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource);
3187 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt);
3188 ieee80211_return_txq(hw, txq, sched_txq);
3189 if (frame_cnt != 0)
3190 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid));
3191
3192 /* bound of tx_resource could get stuck due to burst traffic */
3193 if (frame_cnt == tx_resource)
3194 *reinvoke = true;
3195 }
3196 ieee80211_txq_schedule_end(hw, ac);
3197 }
3198
rtw89_ips_work(struct work_struct * work)3199 static void rtw89_ips_work(struct work_struct *work)
3200 {
3201 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
3202 ips_work);
3203 mutex_lock(&rtwdev->mutex);
3204 rtw89_enter_ips_by_hwflags(rtwdev);
3205 mutex_unlock(&rtwdev->mutex);
3206 }
3207
rtw89_core_txq_work(struct work_struct * w)3208 static void rtw89_core_txq_work(struct work_struct *w)
3209 {
3210 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work);
3211 bool reinvoke = false;
3212 u8 ac;
3213
3214 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
3215 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke);
3216
3217 if (reinvoke) {
3218 /* reinvoke to process the last frame */
3219 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1);
3220 }
3221 }
3222
rtw89_core_txq_reinvoke_work(struct work_struct * w)3223 static void rtw89_core_txq_reinvoke_work(struct work_struct *w)
3224 {
3225 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev,
3226 txq_reinvoke_work.work);
3227
3228 queue_work(rtwdev->txq_wq, &rtwdev->txq_work);
3229 }
3230
rtw89_forbid_ba_work(struct work_struct * w)3231 static void rtw89_forbid_ba_work(struct work_struct *w)
3232 {
3233 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev,
3234 forbid_ba_work.work);
3235 struct rtw89_txq *rtwtxq, *tmp;
3236
3237 spin_lock_bh(&rtwdev->ba_lock);
3238 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) {
3239 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
3240 list_del_init(&rtwtxq->list);
3241 }
3242 spin_unlock_bh(&rtwdev->ba_lock);
3243 }
3244
rtw89_core_sta_pending_tx_iter(void * data,struct ieee80211_sta * sta)3245 static void rtw89_core_sta_pending_tx_iter(void *data,
3246 struct ieee80211_sta *sta)
3247 {
3248 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
3249 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
3250 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
3251 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
3252 struct rtw89_vif_link *target = data;
3253 struct rtw89_vif_link *rtwvif_link;
3254 struct sk_buff *skb, *tmp;
3255 unsigned int link_id;
3256 int qsel, ret;
3257
3258 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
3259 if (rtwvif_link->chanctx_idx == target->chanctx_idx)
3260 goto bottom;
3261
3262 return;
3263
3264 bottom:
3265 if (skb_queue_len(&rtwsta->roc_queue) == 0)
3266 return;
3267
3268 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) {
3269 skb_unlink(skb, &rtwsta->roc_queue);
3270
3271 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel);
3272 if (ret) {
3273 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret);
3274 dev_kfree_skb_any(skb);
3275 } else {
3276 rtw89_core_tx_kick_off(rtwdev, qsel);
3277 }
3278 }
3279 }
3280
rtw89_core_handle_sta_pending_tx(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)3281 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev,
3282 struct rtw89_vif_link *rtwvif_link)
3283 {
3284 ieee80211_iterate_stations_atomic(rtwdev->hw,
3285 rtw89_core_sta_pending_tx_iter,
3286 rtwvif_link);
3287 }
3288
rtw89_core_send_nullfunc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool qos,bool ps)3289 static int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev,
3290 struct rtw89_vif_link *rtwvif_link, bool qos, bool ps)
3291 {
3292 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3293 int link_id = ieee80211_vif_is_mld(vif) ? rtwvif_link->link_id : -1;
3294 struct ieee80211_sta *sta;
3295 struct ieee80211_hdr *hdr;
3296 struct sk_buff *skb;
3297 int ret, qsel;
3298
3299 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc)
3300 return 0;
3301
3302 rcu_read_lock();
3303 sta = ieee80211_find_sta(vif, vif->cfg.ap_addr);
3304 if (!sta) {
3305 ret = -EINVAL;
3306 goto out;
3307 }
3308
3309 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, link_id, qos);
3310 if (!skb) {
3311 ret = -ENOMEM;
3312 goto out;
3313 }
3314
3315 hdr = (struct ieee80211_hdr *)skb->data;
3316 if (ps)
3317 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
3318
3319 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel);
3320 if (ret) {
3321 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret);
3322 dev_kfree_skb_any(skb);
3323 goto out;
3324 }
3325
3326 rcu_read_unlock();
3327
3328 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, qsel,
3329 RTW89_ROC_TX_TIMEOUT);
3330 out:
3331 rcu_read_unlock();
3332
3333 return ret;
3334 }
3335
rtw89_roc_start(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3336 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
3337 {
3338 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3339 struct ieee80211_hw *hw = rtwdev->hw;
3340 struct rtw89_roc *roc = &rtwvif->roc;
3341 struct rtw89_vif_link *rtwvif_link;
3342 struct cfg80211_chan_def roc_chan;
3343 struct rtw89_vif *tmp_vif;
3344 u32 reg;
3345 int ret;
3346
3347 lockdep_assert_held(&rtwdev->mutex);
3348
3349 rtw89_leave_ips_by_hwflags(rtwdev);
3350 rtw89_leave_lps(rtwdev);
3351
3352 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, RTW89_ROC_BY_LINK_INDEX);
3353 if (unlikely(!rtwvif_link)) {
3354 rtw89_err(rtwdev, "roc start: find no link on HW-%u\n",
3355 RTW89_ROC_BY_LINK_INDEX);
3356 return;
3357 }
3358
3359 rtw89_chanctx_pause(rtwdev, RTW89_CHANCTX_PAUSE_REASON_ROC);
3360
3361 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, true);
3362 if (ret)
3363 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
3364 "roc send null-1 failed: %d\n", ret);
3365
3366 rtw89_for_each_rtwvif(rtwdev, tmp_vif) {
3367 struct rtw89_vif_link *tmp_link;
3368 unsigned int link_id;
3369
3370 rtw89_vif_for_each_link(tmp_vif, tmp_link, link_id) {
3371 if (tmp_link->chanctx_idx == rtwvif_link->chanctx_idx) {
3372 tmp_vif->offchan = true;
3373 break;
3374 }
3375 }
3376 }
3377
3378 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT);
3379 rtw89_config_roc_chandef(rtwdev, rtwvif_link->chanctx_idx, &roc_chan);
3380 rtw89_set_channel(rtwdev);
3381
3382 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx);
3383 rtw89_write32_clr(rtwdev, reg, B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH);
3384
3385 ieee80211_ready_on_channel(hw);
3386 cancel_delayed_work(&rtwvif->roc.roc_work);
3387 ieee80211_queue_delayed_work(hw, &rtwvif->roc.roc_work,
3388 msecs_to_jiffies(rtwvif->roc.duration));
3389 }
3390
rtw89_roc_end(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3391 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
3392 {
3393 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3394 struct ieee80211_hw *hw = rtwdev->hw;
3395 struct rtw89_roc *roc = &rtwvif->roc;
3396 struct rtw89_vif_link *rtwvif_link;
3397 struct rtw89_vif *tmp_vif;
3398 u32 reg;
3399 int ret;
3400
3401 lockdep_assert_held(&rtwdev->mutex);
3402
3403 ieee80211_remain_on_channel_expired(hw);
3404
3405 rtw89_leave_ips_by_hwflags(rtwdev);
3406 rtw89_leave_lps(rtwdev);
3407
3408 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, RTW89_ROC_BY_LINK_INDEX);
3409 if (unlikely(!rtwvif_link)) {
3410 rtw89_err(rtwdev, "roc end: find no link on HW-%u\n",
3411 RTW89_ROC_BY_LINK_INDEX);
3412 return;
3413 }
3414
3415 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx);
3416 rtw89_write32_mask(rtwdev, reg, B_AX_RX_FLTR_CFG_MASK, rtwdev->hal.rx_fltr);
3417
3418 roc->state = RTW89_ROC_IDLE;
3419 rtw89_config_roc_chandef(rtwdev, rtwvif_link->chanctx_idx, NULL);
3420 rtw89_chanctx_proceed(rtwdev, NULL);
3421 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, false);
3422 if (ret)
3423 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
3424 "roc send null-0 failed: %d\n", ret);
3425
3426 rtw89_for_each_rtwvif(rtwdev, tmp_vif)
3427 tmp_vif->offchan = false;
3428
3429 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif_link);
3430 queue_work(rtwdev->txq_wq, &rtwdev->txq_work);
3431
3432 if (hw->conf.flags & IEEE80211_CONF_IDLE)
3433 ieee80211_queue_delayed_work(hw, &roc->roc_work,
3434 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT));
3435 }
3436
rtw89_roc_work(struct work_struct * work)3437 void rtw89_roc_work(struct work_struct *work)
3438 {
3439 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif,
3440 roc.roc_work.work);
3441 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
3442 struct rtw89_roc *roc = &rtwvif->roc;
3443
3444 mutex_lock(&rtwdev->mutex);
3445
3446 switch (roc->state) {
3447 case RTW89_ROC_IDLE:
3448 rtw89_enter_ips_by_hwflags(rtwdev);
3449 break;
3450 case RTW89_ROC_MGMT:
3451 case RTW89_ROC_NORMAL:
3452 rtw89_roc_end(rtwdev, rtwvif);
3453 break;
3454 default:
3455 break;
3456 }
3457
3458 mutex_unlock(&rtwdev->mutex);
3459 }
3460
rtw89_get_traffic_level(struct rtw89_dev * rtwdev,u32 throughput,u64 cnt)3461 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev,
3462 u32 throughput, u64 cnt)
3463 {
3464 if (cnt < 100)
3465 return RTW89_TFC_IDLE;
3466 if (throughput > 50)
3467 return RTW89_TFC_HIGH;
3468 if (throughput > 10)
3469 return RTW89_TFC_MID;
3470 if (throughput > 2)
3471 return RTW89_TFC_LOW;
3472 return RTW89_TFC_ULTRA_LOW;
3473 }
3474
rtw89_traffic_stats_calc(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats)3475 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev,
3476 struct rtw89_traffic_stats *stats)
3477 {
3478 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv;
3479 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv;
3480
3481 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT);
3482 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT);
3483
3484 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw);
3485 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw);
3486
3487 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
3488 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
3489 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput,
3490 stats->tx_cnt);
3491 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput,
3492 stats->rx_cnt);
3493 stats->tx_avg_len = stats->tx_cnt ?
3494 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0;
3495 stats->rx_avg_len = stats->rx_cnt ?
3496 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0;
3497
3498 stats->tx_unicast = 0;
3499 stats->rx_unicast = 0;
3500 stats->tx_cnt = 0;
3501 stats->rx_cnt = 0;
3502 stats->rx_tf_periodic = stats->rx_tf_acc;
3503 stats->rx_tf_acc = 0;
3504
3505 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv)
3506 return true;
3507
3508 return false;
3509 }
3510
rtw89_traffic_stats_track(struct rtw89_dev * rtwdev)3511 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev)
3512 {
3513 struct rtw89_vif_link *rtwvif_link;
3514 struct rtw89_vif *rtwvif;
3515 unsigned int link_id;
3516 bool tfc_changed;
3517
3518 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats);
3519
3520 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
3521 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats);
3522
3523 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
3524 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif_link);
3525 }
3526
3527 return tfc_changed;
3528 }
3529
rtw89_enter_lps_track(struct rtw89_dev * rtwdev)3530 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev)
3531 {
3532 struct ieee80211_vif *vif;
3533 struct rtw89_vif *rtwvif;
3534
3535 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
3536 if (rtwvif->tdls_peer)
3537 continue;
3538 if (rtwvif->offchan)
3539 continue;
3540
3541 if (rtwvif->stats.tx_tfc_lv != RTW89_TFC_IDLE ||
3542 rtwvif->stats.rx_tfc_lv != RTW89_TFC_IDLE)
3543 continue;
3544
3545 vif = rtwvif_to_vif(rtwvif);
3546
3547 if (!(vif->type == NL80211_IFTYPE_STATION ||
3548 vif->type == NL80211_IFTYPE_P2P_CLIENT))
3549 continue;
3550
3551 rtw89_enter_lps(rtwdev, rtwvif, true);
3552 }
3553 }
3554
rtw89_core_rfk_track(struct rtw89_dev * rtwdev)3555 static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev)
3556 {
3557 enum rtw89_entity_mode mode;
3558
3559 mode = rtw89_get_entity_mode(rtwdev);
3560 if (mode == RTW89_ENTITY_MODE_MCC)
3561 return;
3562
3563 rtw89_chip_rfk_track(rtwdev);
3564 }
3565
rtw89_core_update_p2p_ps(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct ieee80211_bss_conf * bss_conf)3566 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev,
3567 struct rtw89_vif_link *rtwvif_link,
3568 struct ieee80211_bss_conf *bss_conf)
3569 {
3570 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev);
3571
3572 if (mode == RTW89_ENTITY_MODE_MCC)
3573 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE);
3574 else
3575 rtw89_process_p2p_ps(rtwdev, rtwvif_link, bss_conf);
3576 }
3577
rtw89_traffic_stats_init(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats)3578 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
3579 struct rtw89_traffic_stats *stats)
3580 {
3581 stats->tx_unicast = 0;
3582 stats->rx_unicast = 0;
3583 stats->tx_cnt = 0;
3584 stats->rx_cnt = 0;
3585 ewma_tp_init(&stats->tx_ewma_tp);
3586 ewma_tp_init(&stats->rx_ewma_tp);
3587 }
3588
rtw89_track_work(struct work_struct * work)3589 static void rtw89_track_work(struct work_struct *work)
3590 {
3591 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
3592 track_work.work);
3593 bool tfc_changed;
3594
3595 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags))
3596 return;
3597
3598 mutex_lock(&rtwdev->mutex);
3599
3600 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
3601 goto out;
3602
3603 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work,
3604 RTW89_TRACK_WORK_PERIOD);
3605
3606 tfc_changed = rtw89_traffic_stats_track(rtwdev);
3607 if (rtwdev->scanning)
3608 goto out;
3609
3610 rtw89_leave_lps(rtwdev);
3611
3612 if (tfc_changed) {
3613 rtw89_hci_recalc_int_mit(rtwdev);
3614 rtw89_btc_ntfy_wl_sta(rtwdev);
3615 }
3616 rtw89_mac_bf_monitor_track(rtwdev);
3617 rtw89_phy_stat_track(rtwdev);
3618 rtw89_phy_env_monitor_track(rtwdev);
3619 rtw89_phy_dig(rtwdev);
3620 rtw89_core_rfk_track(rtwdev);
3621 rtw89_phy_ra_update(rtwdev);
3622 rtw89_phy_cfo_track(rtwdev);
3623 rtw89_phy_tx_path_div_track(rtwdev);
3624 rtw89_phy_antdiv_track(rtwdev);
3625 rtw89_phy_ul_tb_ctrl_track(rtwdev);
3626 rtw89_phy_edcca_track(rtwdev);
3627 rtw89_tas_track(rtwdev);
3628 rtw89_chanctx_track(rtwdev);
3629 rtw89_core_rfkill_poll(rtwdev, false);
3630
3631 if (rtwdev->lps_enabled && !rtwdev->btc.lps)
3632 rtw89_enter_lps_track(rtwdev);
3633
3634 out:
3635 mutex_unlock(&rtwdev->mutex);
3636 }
3637
rtw89_core_acquire_bit_map(unsigned long * addr,unsigned long size)3638 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size)
3639 {
3640 unsigned long bit;
3641
3642 bit = find_first_zero_bit(addr, size);
3643 if (bit < size)
3644 set_bit(bit, addr);
3645
3646 return bit;
3647 }
3648
rtw89_core_release_bit_map(unsigned long * addr,u8 bit)3649 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit)
3650 {
3651 clear_bit(bit, addr);
3652 }
3653
rtw89_core_release_all_bits_map(unsigned long * addr,unsigned int nbits)3654 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits)
3655 {
3656 bitmap_zero(addr, nbits);
3657 }
3658
rtw89_core_acquire_sta_ba_entry(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,u8 tid,u8 * cam_idx)3659 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
3660 struct rtw89_sta_link *rtwsta_link, u8 tid,
3661 u8 *cam_idx)
3662 {
3663 const struct rtw89_chip_info *chip = rtwdev->chip;
3664 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
3665 struct rtw89_ba_cam_entry *entry = NULL, *tmp;
3666 u8 idx;
3667 int i;
3668
3669 lockdep_assert_held(&rtwdev->mutex);
3670
3671 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num);
3672 if (idx == chip->bacam_num) {
3673 /* allocate a static BA CAM to tid=0/5, so replace the existing
3674 * one if BA CAM is full. Hardware will process the original tid
3675 * automatically.
3676 */
3677 if (tid != 0 && tid != 5)
3678 return -ENOSPC;
3679
3680 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) {
3681 tmp = &cam_info->ba_cam_entry[i];
3682 if (tmp->tid == 0 || tmp->tid == 5)
3683 continue;
3684
3685 idx = i;
3686 entry = tmp;
3687 list_del(&entry->list);
3688 break;
3689 }
3690
3691 if (!entry)
3692 return -ENOSPC;
3693 } else {
3694 entry = &cam_info->ba_cam_entry[idx];
3695 }
3696
3697 entry->tid = tid;
3698 list_add_tail(&entry->list, &rtwsta_link->ba_cam_list);
3699
3700 *cam_idx = idx;
3701
3702 return 0;
3703 }
3704
rtw89_core_release_sta_ba_entry(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,u8 tid,u8 * cam_idx)3705 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
3706 struct rtw89_sta_link *rtwsta_link, u8 tid,
3707 u8 *cam_idx)
3708 {
3709 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
3710 struct rtw89_ba_cam_entry *entry = NULL, *tmp;
3711 u8 idx;
3712
3713 lockdep_assert_held(&rtwdev->mutex);
3714
3715 list_for_each_entry_safe(entry, tmp, &rtwsta_link->ba_cam_list, list) {
3716 if (entry->tid != tid)
3717 continue;
3718
3719 idx = entry - cam_info->ba_cam_entry;
3720 list_del(&entry->list);
3721
3722 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx);
3723 *cam_idx = idx;
3724 return 0;
3725 }
3726
3727 return -ENOENT;
3728 }
3729
3730 #define RTW89_TYPE_MAPPING(_type) \
3731 case NL80211_IFTYPE_ ## _type: \
3732 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_ ## _type; \
3733 break
rtw89_vif_type_mapping(struct rtw89_vif_link * rtwvif_link,bool assoc)3734 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc)
3735 {
3736 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3737 const struct ieee80211_bss_conf *bss_conf;
3738
3739 switch (vif->type) {
3740 case NL80211_IFTYPE_STATION:
3741 if (vif->p2p)
3742 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT;
3743 else
3744 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_STATION;
3745 break;
3746 case NL80211_IFTYPE_AP:
3747 if (vif->p2p)
3748 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_GO;
3749 else
3750 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_AP;
3751 break;
3752 RTW89_TYPE_MAPPING(ADHOC);
3753 RTW89_TYPE_MAPPING(MONITOR);
3754 RTW89_TYPE_MAPPING(MESH_POINT);
3755 default:
3756 WARN_ON(1);
3757 break;
3758 }
3759
3760 switch (vif->type) {
3761 case NL80211_IFTYPE_AP:
3762 case NL80211_IFTYPE_MESH_POINT:
3763 rtwvif_link->net_type = RTW89_NET_TYPE_AP_MODE;
3764 rtwvif_link->self_role = RTW89_SELF_ROLE_AP;
3765 break;
3766 case NL80211_IFTYPE_ADHOC:
3767 rtwvif_link->net_type = RTW89_NET_TYPE_AD_HOC;
3768 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT;
3769 break;
3770 case NL80211_IFTYPE_STATION:
3771 if (assoc) {
3772 rtwvif_link->net_type = RTW89_NET_TYPE_INFRA;
3773
3774 rcu_read_lock();
3775 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
3776 rtwvif_link->trigger = bss_conf->he_support;
3777 rcu_read_unlock();
3778 } else {
3779 rtwvif_link->net_type = RTW89_NET_TYPE_NO_LINK;
3780 rtwvif_link->trigger = false;
3781 }
3782 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT;
3783 rtwvif_link->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL;
3784 break;
3785 case NL80211_IFTYPE_MONITOR:
3786 break;
3787 default:
3788 WARN_ON(1);
3789 break;
3790 }
3791 }
3792
rtw89_core_sta_link_add(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)3793 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev,
3794 struct rtw89_vif_link *rtwvif_link,
3795 struct rtw89_sta_link *rtwsta_link)
3796 {
3797 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3798 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
3799 struct rtw89_hal *hal = &rtwdev->hal;
3800 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
3801 int i;
3802 int ret;
3803
3804 rtwsta_link->prev_rssi = 0;
3805 INIT_LIST_HEAD(&rtwsta_link->ba_cam_list);
3806 ewma_rssi_init(&rtwsta_link->avg_rssi);
3807 ewma_snr_init(&rtwsta_link->avg_snr);
3808 ewma_evm_init(&rtwsta_link->evm_1ss);
3809 for (i = 0; i < ant_num; i++) {
3810 ewma_rssi_init(&rtwsta_link->rssi[i]);
3811 ewma_evm_init(&rtwsta_link->evm_min[i]);
3812 ewma_evm_init(&rtwsta_link->evm_max[i]);
3813 }
3814
3815 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
3816 /* must do rtw89_reg_6ghz_recalc() before rfk channel */
3817 ret = rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, true);
3818 if (ret)
3819 return ret;
3820
3821 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link,
3822 BTC_ROLE_MSTS_STA_CONN_START);
3823 rtw89_chip_rfk_channel(rtwdev, rtwvif_link);
3824 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
3825 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta_link->mac_id, false);
3826 if (ret) {
3827 rtw89_warn(rtwdev, "failed to send h2c macid pause\n");
3828 return ret;
3829 }
3830
3831 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link,
3832 RTW89_ROLE_CREATE);
3833 if (ret) {
3834 rtw89_warn(rtwdev, "failed to send h2c role info\n");
3835 return ret;
3836 }
3837
3838 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
3839 if (ret)
3840 return ret;
3841
3842 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
3843 if (ret)
3844 return ret;
3845 }
3846
3847 return 0;
3848 }
3849
rtw89_core_sta_link_disassoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)3850 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev,
3851 struct rtw89_vif_link *rtwvif_link,
3852 struct rtw89_sta_link *rtwsta_link)
3853 {
3854 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3855
3856 rtw89_assoc_link_clr(rtwsta_link);
3857
3858 if (vif->type == NL80211_IFTYPE_STATION)
3859 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, false);
3860
3861 return 0;
3862 }
3863
rtw89_core_sta_link_disconnect(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)3864 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev,
3865 struct rtw89_vif_link *rtwvif_link,
3866 struct rtw89_sta_link *rtwsta_link)
3867 {
3868 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3869 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
3870 int ret;
3871
3872 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, true);
3873 rtw89_mac_bf_disassoc(rtwdev, rtwvif_link, rtwsta_link);
3874
3875 if (vif->type == NL80211_IFTYPE_AP || sta->tdls)
3876 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta_link->addr_cam);
3877 if (sta->tdls)
3878 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta_link->bssid_cam);
3879
3880 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
3881 rtw89_vif_type_mapping(rtwvif_link, false);
3882 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif_link, true);
3883 }
3884
3885 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
3886 if (ret) {
3887 rtw89_warn(rtwdev, "failed to send h2c cmac table\n");
3888 return ret;
3889 }
3890
3891 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, true);
3892 if (ret) {
3893 rtw89_warn(rtwdev, "failed to send h2c join info\n");
3894 return ret;
3895 }
3896
3897 /* update cam aid mac_id net_type */
3898 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL);
3899 if (ret) {
3900 rtw89_warn(rtwdev, "failed to send h2c cam\n");
3901 return ret;
3902 }
3903
3904 return ret;
3905 }
3906
rtw89_sta_link_can_er(struct rtw89_dev * rtwdev,struct ieee80211_bss_conf * bss_conf,struct ieee80211_link_sta * link_sta)3907 static bool rtw89_sta_link_can_er(struct rtw89_dev *rtwdev,
3908 struct ieee80211_bss_conf *bss_conf,
3909 struct ieee80211_link_sta *link_sta)
3910 {
3911 if (!bss_conf->he_support ||
3912 bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE)
3913 return false;
3914
3915 if (rtwdev->chip->chip_id == RTL8852C &&
3916 rtw89_sta_link_has_su_mu_4xhe08(link_sta) &&
3917 !rtw89_sta_link_has_er_su_4xhe08(link_sta))
3918 return false;
3919
3920 return true;
3921 }
3922
rtw89_core_sta_link_assoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)3923 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev,
3924 struct rtw89_vif_link *rtwvif_link,
3925 struct rtw89_sta_link *rtwsta_link)
3926 {
3927 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3928 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
3929 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif_link,
3930 rtwsta_link);
3931 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
3932 rtwvif_link->chanctx_idx);
3933 struct ieee80211_link_sta *link_sta;
3934 int ret;
3935
3936 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
3937 if (sta->tdls) {
3938 rcu_read_lock();
3939
3940 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
3941 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif_link, bssid_cam,
3942 link_sta->addr);
3943 if (ret) {
3944 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n");
3945 rcu_read_unlock();
3946 return ret;
3947 }
3948
3949 rcu_read_unlock();
3950 }
3951
3952 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta_link->addr_cam, bssid_cam);
3953 if (ret) {
3954 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n");
3955 return ret;
3956 }
3957 }
3958
3959 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
3960 if (ret) {
3961 rtw89_warn(rtwdev, "failed to send h2c cmac table\n");
3962 return ret;
3963 }
3964
3965 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, false);
3966 if (ret) {
3967 rtw89_warn(rtwdev, "failed to send h2c join info\n");
3968 return ret;
3969 }
3970
3971 /* update cam aid mac_id net_type */
3972 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL);
3973 if (ret) {
3974 rtw89_warn(rtwdev, "failed to send h2c cam\n");
3975 return ret;
3976 }
3977
3978 rtw89_phy_ra_assoc(rtwdev, rtwsta_link);
3979 rtw89_mac_bf_assoc(rtwdev, rtwvif_link, rtwsta_link);
3980 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, false);
3981
3982 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
3983 struct ieee80211_bss_conf *bss_conf;
3984
3985 rcu_read_lock();
3986
3987 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
3988 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
3989 rtwsta_link->er_cap = rtw89_sta_link_can_er(rtwdev, bss_conf, link_sta);
3990
3991 rcu_read_unlock();
3992
3993 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link,
3994 BTC_ROLE_MSTS_STA_CONN_END);
3995 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta_link->htc_template, chan);
3996 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif_link);
3997
3998 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif_link, rtwsta_link->mac_id);
3999 if (ret) {
4000 rtw89_warn(rtwdev, "failed to send h2c general packet\n");
4001 return ret;
4002 }
4003
4004 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true);
4005 }
4006
4007 rtw89_assoc_link_set(rtwsta_link);
4008 return ret;
4009 }
4010
rtw89_core_sta_link_remove(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)4011 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev,
4012 struct rtw89_vif_link *rtwvif_link,
4013 struct rtw89_sta_link *rtwsta_link)
4014 {
4015 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
4016 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
4017 int ret;
4018
4019 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
4020 rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, false);
4021 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link,
4022 BTC_ROLE_MSTS_STA_DIS_CONN);
4023 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
4024 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link,
4025 RTW89_ROLE_REMOVE);
4026 if (ret) {
4027 rtw89_warn(rtwdev, "failed to send h2c role info\n");
4028 return ret;
4029 }
4030 }
4031
4032 return 0;
4033 }
4034
_rtw89_core_set_tid_config(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,struct cfg80211_tid_cfg * tid_conf)4035 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
4036 struct ieee80211_sta *sta,
4037 struct cfg80211_tid_cfg *tid_conf)
4038 {
4039 struct ieee80211_txq *txq;
4040 struct rtw89_txq *rtwtxq;
4041 u32 mask = tid_conf->mask;
4042 u8 tids = tid_conf->tids;
4043 int tids_nbit = BITS_PER_BYTE;
4044 int i;
4045
4046 for (i = 0; i < tids_nbit; i++, tids >>= 1) {
4047 if (!tids)
4048 break;
4049
4050 if (!(tids & BIT(0)))
4051 continue;
4052
4053 txq = sta->txq[i];
4054 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
4055
4056 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) {
4057 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) {
4058 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
4059 } else {
4060 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags))
4061 ieee80211_stop_tx_ba_session(sta, txq->tid);
4062 spin_lock_bh(&rtwdev->ba_lock);
4063 list_del_init(&rtwtxq->list);
4064 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
4065 spin_unlock_bh(&rtwdev->ba_lock);
4066 }
4067 }
4068
4069 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) {
4070 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE)
4071 sta->max_amsdu_subframes = 0;
4072 else
4073 sta->max_amsdu_subframes = 1;
4074 }
4075 }
4076 }
4077
rtw89_core_set_tid_config(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,struct cfg80211_tid_config * tid_config)4078 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
4079 struct ieee80211_sta *sta,
4080 struct cfg80211_tid_config *tid_config)
4081 {
4082 int i;
4083
4084 for (i = 0; i < tid_config->n_tid_conf; i++)
4085 _rtw89_core_set_tid_config(rtwdev, sta,
4086 &tid_config->tid_conf[i]);
4087 }
4088
rtw89_init_ht_cap(struct rtw89_dev * rtwdev,struct ieee80211_sta_ht_cap * ht_cap)4089 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev,
4090 struct ieee80211_sta_ht_cap *ht_cap)
4091 {
4092 static const __le16 highest[RF_PATH_MAX] = {
4093 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600),
4094 };
4095 struct rtw89_hal *hal = &rtwdev->hal;
4096 u8 nss = hal->rx_nss;
4097 int i;
4098
4099 ht_cap->ht_supported = true;
4100 ht_cap->cap = 0;
4101 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
4102 IEEE80211_HT_CAP_MAX_AMSDU |
4103 IEEE80211_HT_CAP_TX_STBC |
4104 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
4105 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
4106 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4107 IEEE80211_HT_CAP_DSSSCCK40 |
4108 IEEE80211_HT_CAP_SGI_40;
4109 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
4110 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
4111 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
4112 for (i = 0; i < nss; i++)
4113 ht_cap->mcs.rx_mask[i] = 0xFF;
4114 ht_cap->mcs.rx_mask[4] = 0x01;
4115 ht_cap->mcs.rx_highest = highest[nss - 1];
4116 }
4117
rtw89_init_vht_cap(struct rtw89_dev * rtwdev,struct ieee80211_sta_vht_cap * vht_cap)4118 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev,
4119 struct ieee80211_sta_vht_cap *vht_cap)
4120 {
4121 static const __le16 highest_bw80[RF_PATH_MAX] = {
4122 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733),
4123 };
4124 static const __le16 highest_bw160[RF_PATH_MAX] = {
4125 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467),
4126 };
4127 const struct rtw89_chip_info *chip = rtwdev->chip;
4128 const __le16 *highest = chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160) ?
4129 highest_bw160 : highest_bw80;
4130 struct rtw89_hal *hal = &rtwdev->hal;
4131 u16 tx_mcs_map = 0, rx_mcs_map = 0;
4132 u8 sts_cap = 3;
4133 int i;
4134
4135 for (i = 0; i < 8; i++) {
4136 if (i < hal->tx_nss)
4137 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
4138 else
4139 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
4140 if (i < hal->rx_nss)
4141 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
4142 else
4143 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
4144 }
4145
4146 vht_cap->vht_supported = true;
4147 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
4148 IEEE80211_VHT_CAP_SHORT_GI_80 |
4149 IEEE80211_VHT_CAP_RXSTBC_1 |
4150 IEEE80211_VHT_CAP_HTC_VHT |
4151 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
4152 0;
4153 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
4154 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
4155 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
4156 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
4157 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT;
4158 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
4159 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
4160 IEEE80211_VHT_CAP_SHORT_GI_160;
4161 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map);
4162 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map);
4163 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1];
4164 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1];
4165
4166 if (ieee80211_hw_check(rtwdev->hw, SUPPORTS_VHT_EXT_NSS_BW))
4167 vht_cap->vht_mcs.tx_highest |=
4168 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE);
4169 }
4170
rtw89_init_he_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,enum nl80211_iftype iftype,struct ieee80211_sband_iftype_data * iftype_data)4171 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev,
4172 enum nl80211_band band,
4173 enum nl80211_iftype iftype,
4174 struct ieee80211_sband_iftype_data *iftype_data)
4175 {
4176 const struct rtw89_chip_info *chip = rtwdev->chip;
4177 struct rtw89_hal *hal = &rtwdev->hal;
4178 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) ||
4179 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV);
4180 struct ieee80211_sta_he_cap *he_cap;
4181 int nss = hal->rx_nss;
4182 u8 *mac_cap_info;
4183 u8 *phy_cap_info;
4184 u16 mcs_map = 0;
4185 int i;
4186
4187 for (i = 0; i < 8; i++) {
4188 if (i < nss)
4189 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2);
4190 else
4191 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2);
4192 }
4193
4194 he_cap = &iftype_data->he_cap;
4195 mac_cap_info = he_cap->he_cap_elem.mac_cap_info;
4196 phy_cap_info = he_cap->he_cap_elem.phy_cap_info;
4197
4198 he_cap->has_he = true;
4199 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE;
4200 if (iftype == NL80211_IFTYPE_STATION)
4201 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US;
4202 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK |
4203 IEEE80211_HE_MAC_CAP2_BSR;
4204 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2;
4205 if (iftype == NL80211_IFTYPE_AP)
4206 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL;
4207 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS |
4208 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU;
4209 if (iftype == NL80211_IFTYPE_STATION)
4210 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX;
4211 if (band == NL80211_BAND_2GHZ) {
4212 phy_cap_info[0] =
4213 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
4214 } else {
4215 phy_cap_info[0] =
4216 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G;
4217 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
4218 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
4219 }
4220 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
4221 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD |
4222 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US;
4223 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
4224 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ |
4225 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ |
4226 IEEE80211_HE_PHY_CAP2_DOPPLER_TX;
4227 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM;
4228 if (iftype == NL80211_IFTYPE_STATION)
4229 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM |
4230 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2;
4231 if (iftype == NL80211_IFTYPE_AP)
4232 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU;
4233 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
4234 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4;
4235 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
4236 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4;
4237 phy_cap_info[5] = no_ng16 ? 0 :
4238 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK |
4239 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK;
4240 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU |
4241 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU |
4242 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
4243 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE;
4244 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
4245 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
4246 IEEE80211_HE_PHY_CAP7_MAX_NC_1;
4247 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
4248 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI |
4249 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996;
4250 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
4251 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
4252 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU;
4253 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM |
4254 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU |
4255 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
4256 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
4257 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US,
4258 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK);
4259 if (iftype == NL80211_IFTYPE_STATION)
4260 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU;
4261 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map);
4262 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map);
4263 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) {
4264 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map);
4265 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map);
4266 }
4267
4268 if (band == NL80211_BAND_6GHZ) {
4269 __le16 capa;
4270
4271 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE,
4272 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) |
4273 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K,
4274 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) |
4275 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
4276 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
4277 iftype_data->he_6ghz_capa.capa = capa;
4278 }
4279 }
4280
rtw89_init_eht_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,enum nl80211_iftype iftype,struct ieee80211_sband_iftype_data * iftype_data)4281 static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev,
4282 enum nl80211_band band,
4283 enum nl80211_iftype iftype,
4284 struct ieee80211_sband_iftype_data *iftype_data)
4285 {
4286 const struct rtw89_chip_info *chip = rtwdev->chip;
4287 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem;
4288 struct ieee80211_eht_mcs_nss_supp *eht_nss;
4289 struct ieee80211_sta_eht_cap *eht_cap;
4290 struct rtw89_hal *hal = &rtwdev->hal;
4291 bool support_mcs_12_13 = true;
4292 bool support_320mhz = false;
4293 u8 val, val_mcs13;
4294 int sts = 8;
4295
4296 if (chip->chip_gen == RTW89_CHIP_AX)
4297 return;
4298
4299 if (hal->no_mcs_12_13)
4300 support_mcs_12_13 = false;
4301
4302 if (band == NL80211_BAND_6GHZ &&
4303 chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_320))
4304 support_320mhz = true;
4305
4306 eht_cap = &iftype_data->eht_cap;
4307 eht_cap_elem = &eht_cap->eht_cap_elem;
4308 eht_nss = &eht_cap->eht_mcs_nss_supp;
4309
4310 eht_cap->has_eht = true;
4311
4312 eht_cap_elem->mac_cap_info[0] =
4313 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991,
4314 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK);
4315 eht_cap_elem->mac_cap_info[1] = 0;
4316
4317 eht_cap_elem->phy_cap_info[0] =
4318 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI |
4319 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE;
4320 if (support_320mhz)
4321 eht_cap_elem->phy_cap_info[0] |=
4322 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ;
4323
4324 eht_cap_elem->phy_cap_info[0] |=
4325 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)),
4326 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK);
4327 eht_cap_elem->phy_cap_info[1] =
4328 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)),
4329 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) |
4330 u8_encode_bits(sts - 1,
4331 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK);
4332 if (support_320mhz)
4333 eht_cap_elem->phy_cap_info[1] |=
4334 u8_encode_bits(sts - 1,
4335 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK);
4336
4337 eht_cap_elem->phy_cap_info[2] = 0;
4338
4339 eht_cap_elem->phy_cap_info[3] =
4340 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK |
4341 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK |
4342 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK |
4343 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK;
4344
4345 eht_cap_elem->phy_cap_info[4] =
4346 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP |
4347 u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK);
4348
4349 eht_cap_elem->phy_cap_info[5] =
4350 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US,
4351 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK);
4352
4353 eht_cap_elem->phy_cap_info[6] = 0;
4354 eht_cap_elem->phy_cap_info[7] = 0;
4355 eht_cap_elem->phy_cap_info[8] = 0;
4356
4357 val = u8_encode_bits(hal->rx_nss, IEEE80211_EHT_MCS_NSS_RX) |
4358 u8_encode_bits(hal->tx_nss, IEEE80211_EHT_MCS_NSS_TX);
4359 val_mcs13 = support_mcs_12_13 ? val : 0;
4360
4361 eht_nss->bw._80.rx_tx_mcs9_max_nss = val;
4362 eht_nss->bw._80.rx_tx_mcs11_max_nss = val;
4363 eht_nss->bw._80.rx_tx_mcs13_max_nss = val_mcs13;
4364 eht_nss->bw._160.rx_tx_mcs9_max_nss = val;
4365 eht_nss->bw._160.rx_tx_mcs11_max_nss = val;
4366 eht_nss->bw._160.rx_tx_mcs13_max_nss = val_mcs13;
4367 if (support_320mhz) {
4368 eht_nss->bw._320.rx_tx_mcs9_max_nss = val;
4369 eht_nss->bw._320.rx_tx_mcs11_max_nss = val;
4370 eht_nss->bw._320.rx_tx_mcs13_max_nss = val_mcs13;
4371 }
4372 }
4373
4374 #define RTW89_SBAND_IFTYPES_NR 2
4375
rtw89_init_he_eht_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,struct ieee80211_supported_band * sband)4376 static void rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev,
4377 enum nl80211_band band,
4378 struct ieee80211_supported_band *sband)
4379 {
4380 struct ieee80211_sband_iftype_data *iftype_data;
4381 enum nl80211_iftype iftype;
4382 int idx = 0;
4383
4384 iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL);
4385 if (!iftype_data)
4386 return;
4387
4388 for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) {
4389 switch (iftype) {
4390 case NL80211_IFTYPE_STATION:
4391 case NL80211_IFTYPE_AP:
4392 break;
4393 default:
4394 continue;
4395 }
4396
4397 if (idx >= RTW89_SBAND_IFTYPES_NR) {
4398 rtw89_warn(rtwdev, "run out of iftype_data\n");
4399 break;
4400 }
4401
4402 iftype_data[idx].types_mask = BIT(iftype);
4403
4404 rtw89_init_he_cap(rtwdev, band, iftype, &iftype_data[idx]);
4405 rtw89_init_eht_cap(rtwdev, band, iftype, &iftype_data[idx]);
4406
4407 idx++;
4408 }
4409
4410 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx);
4411 }
4412
rtw89_core_set_supported_band(struct rtw89_dev * rtwdev)4413 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev)
4414 {
4415 struct ieee80211_hw *hw = rtwdev->hw;
4416 struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL;
4417 struct ieee80211_supported_band *sband_6ghz = NULL;
4418 u32 size = sizeof(struct ieee80211_supported_band);
4419 u8 support_bands = rtwdev->chip->support_bands;
4420
4421 if (support_bands & BIT(NL80211_BAND_2GHZ)) {
4422 sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL);
4423 if (!sband_2ghz)
4424 goto err;
4425 #if defined(__FreeBSD__)
4426 if (rtw_ht_support)
4427 #endif
4428 rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap);
4429 #if defined(__FreeBSD__)
4430 if (rtw_eht_support)
4431 #endif
4432 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz);
4433 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz;
4434 }
4435
4436 if (support_bands & BIT(NL80211_BAND_5GHZ)) {
4437 sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL);
4438 if (!sband_5ghz)
4439 goto err;
4440 #if defined(__FreeBSD__)
4441 if (rtw_ht_support)
4442 #endif
4443 rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap);
4444 #if defined(__FreeBSD__)
4445 if (rtw_vht_support)
4446 #endif
4447 rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap);
4448 #if defined(__FreeBSD__)
4449 if (rtw_eht_support)
4450 #endif
4451 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz);
4452 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz;
4453 }
4454
4455 if (support_bands & BIT(NL80211_BAND_6GHZ)) {
4456 sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL);
4457 if (!sband_6ghz)
4458 goto err;
4459 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz);
4460 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz;
4461 }
4462
4463 return 0;
4464
4465 err:
4466 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL;
4467 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL;
4468 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL;
4469 if (sband_2ghz)
4470 kfree((__force void *)sband_2ghz->iftype_data);
4471 if (sband_5ghz)
4472 kfree((__force void *)sband_5ghz->iftype_data);
4473 if (sband_6ghz)
4474 kfree((__force void *)sband_6ghz->iftype_data);
4475 kfree(sband_2ghz);
4476 kfree(sband_5ghz);
4477 kfree(sband_6ghz);
4478 return -ENOMEM;
4479 }
4480
rtw89_core_clr_supported_band(struct rtw89_dev * rtwdev)4481 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev)
4482 {
4483 struct ieee80211_hw *hw = rtwdev->hw;
4484
4485 if (hw->wiphy->bands[NL80211_BAND_2GHZ])
4486 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data);
4487 if (hw->wiphy->bands[NL80211_BAND_5GHZ])
4488 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data);
4489 if (hw->wiphy->bands[NL80211_BAND_6GHZ])
4490 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data);
4491 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]);
4492 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]);
4493 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]);
4494 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL;
4495 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL;
4496 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL;
4497 }
4498
rtw89_core_ppdu_sts_init(struct rtw89_dev * rtwdev)4499 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev)
4500 {
4501 int i;
4502
4503 for (i = 0; i < RTW89_PHY_MAX; i++)
4504 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]);
4505 for (i = 0; i < RTW89_PHY_MAX; i++)
4506 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX;
4507 }
4508
rtw89_core_update_beacon_work(struct work_struct * work)4509 void rtw89_core_update_beacon_work(struct work_struct *work)
4510 {
4511 struct rtw89_dev *rtwdev;
4512 struct rtw89_vif_link *rtwvif_link = container_of(work, struct rtw89_vif_link,
4513 update_beacon_work);
4514
4515 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE)
4516 return;
4517
4518 rtwdev = rtwvif_link->rtwvif->rtwdev;
4519
4520 mutex_lock(&rtwdev->mutex);
4521 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link);
4522 mutex_unlock(&rtwdev->mutex);
4523 }
4524
rtw89_wait_for_cond(struct rtw89_wait_info * wait,unsigned int cond)4525 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond)
4526 {
4527 struct completion *cmpl = &wait->completion;
4528 unsigned long time_left;
4529 unsigned int cur;
4530
4531 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond);
4532 if (cur != RTW89_WAIT_COND_IDLE)
4533 return -EBUSY;
4534
4535 time_left = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT);
4536 if (time_left == 0) {
4537 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
4538 return -ETIMEDOUT;
4539 }
4540
4541 if (wait->data.err)
4542 return -EFAULT;
4543
4544 return 0;
4545 }
4546
rtw89_complete_cond(struct rtw89_wait_info * wait,unsigned int cond,const struct rtw89_completion_data * data)4547 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
4548 const struct rtw89_completion_data *data)
4549 {
4550 unsigned int cur;
4551
4552 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE);
4553 if (cur != cond)
4554 return;
4555
4556 wait->data = *data;
4557 complete(&wait->completion);
4558 }
4559
rtw89_core_ntfy_btc_event(struct rtw89_dev * rtwdev,enum rtw89_btc_hmsg event)4560 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event)
4561 {
4562 u16 bt_req_len;
4563
4564 switch (event) {
4565 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT:
4566 bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0);
4567 rtw89_debug(rtwdev, RTW89_DBG_BTC,
4568 "coex updates BT req len to %d TU\n", bt_req_len);
4569 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE);
4570 break;
4571 default:
4572 if (event < NUM_OF_RTW89_BTC_HMSG)
4573 rtw89_debug(rtwdev, RTW89_DBG_BTC,
4574 "unhandled BTC HMSG event: %d\n", event);
4575 else
4576 rtw89_warn(rtwdev,
4577 "unrecognized BTC HMSG event: %d\n", event);
4578 break;
4579 }
4580 }
4581
rtw89_check_quirks(struct rtw89_dev * rtwdev,const struct dmi_system_id * quirks)4582 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks)
4583 {
4584 const struct dmi_system_id *match;
4585 enum rtw89_quirks quirk;
4586
4587 if (!quirks)
4588 return;
4589
4590 for (match = dmi_first_match(quirks); match; match = dmi_first_match(match + 1)) {
4591 quirk = (uintptr_t)match->driver_data;
4592 if (quirk >= NUM_OF_RTW89_QUIRKS)
4593 continue;
4594
4595 set_bit(quirk, rtwdev->quirks);
4596 }
4597 }
4598 EXPORT_SYMBOL(rtw89_check_quirks);
4599
rtw89_core_start(struct rtw89_dev * rtwdev)4600 int rtw89_core_start(struct rtw89_dev *rtwdev)
4601 {
4602 int ret;
4603
4604 ret = rtw89_mac_init(rtwdev);
4605 if (ret) {
4606 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret);
4607 return ret;
4608 }
4609
4610 rtw89_btc_ntfy_poweron(rtwdev);
4611
4612 /* efuse process */
4613
4614 /* pre-config BB/RF, BB reset/RFC reset */
4615 ret = rtw89_chip_reset_bb_rf(rtwdev);
4616 if (ret)
4617 return ret;
4618
4619 rtw89_phy_init_bb_reg(rtwdev);
4620 rtw89_chip_bb_postinit(rtwdev);
4621 rtw89_phy_init_rf_reg(rtwdev, false);
4622
4623 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL);
4624
4625 rtw89_phy_dm_init(rtwdev);
4626
4627 rtw89_mac_cfg_ppdu_status_bands(rtwdev, true);
4628 rtw89_mac_cfg_phy_rpt_bands(rtwdev, true);
4629 rtw89_mac_update_rts_threshold(rtwdev);
4630
4631 rtw89_tas_reset(rtwdev);
4632
4633 ret = rtw89_hci_start(rtwdev);
4634 if (ret) {
4635 rtw89_err(rtwdev, "failed to start hci\n");
4636 return ret;
4637 }
4638
4639 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work,
4640 RTW89_TRACK_WORK_PERIOD);
4641
4642 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
4643
4644 rtw89_chip_rfk_init_late(rtwdev);
4645 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON);
4646 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable);
4647 rtw89_fw_h2c_init_ba_cam(rtwdev);
4648
4649 return 0;
4650 }
4651
rtw89_core_stop(struct rtw89_dev * rtwdev)4652 void rtw89_core_stop(struct rtw89_dev *rtwdev)
4653 {
4654 struct rtw89_btc *btc = &rtwdev->btc;
4655
4656 /* Prvent to stop twice; enter_ips and ops_stop */
4657 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
4658 return;
4659
4660 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF);
4661
4662 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
4663
4664 mutex_unlock(&rtwdev->mutex);
4665
4666 cancel_work_sync(&rtwdev->c2h_work);
4667 cancel_work_sync(&rtwdev->cancel_6ghz_probe_work);
4668 cancel_work_sync(&btc->eapol_notify_work);
4669 cancel_work_sync(&btc->arp_notify_work);
4670 cancel_work_sync(&btc->dhcp_notify_work);
4671 cancel_work_sync(&btc->icmp_notify_work);
4672 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work);
4673 cancel_delayed_work_sync(&rtwdev->track_work);
4674 cancel_delayed_work_sync(&rtwdev->chanctx_work);
4675 cancel_delayed_work_sync(&rtwdev->coex_act1_work);
4676 cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work);
4677 cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work);
4678 cancel_delayed_work_sync(&rtwdev->cfo_track_work);
4679 cancel_delayed_work_sync(&rtwdev->forbid_ba_work);
4680 cancel_delayed_work_sync(&rtwdev->antdiv_work);
4681
4682 mutex_lock(&rtwdev->mutex);
4683
4684 rtw89_btc_ntfy_poweroff(rtwdev);
4685 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true);
4686 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true);
4687 rtw89_hci_stop(rtwdev);
4688 rtw89_hci_deinit(rtwdev);
4689 rtw89_mac_pwr_off(rtwdev);
4690 rtw89_hci_reset(rtwdev);
4691 }
4692
rtw89_acquire_mac_id(struct rtw89_dev * rtwdev)4693 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev)
4694 {
4695 const struct rtw89_chip_info *chip = rtwdev->chip;
4696 u8 mac_id_num;
4697 u8 mac_id;
4698
4699 if (rtwdev->support_mlo)
4700 mac_id_num = chip->support_macid_num / chip->support_link_num;
4701 else
4702 mac_id_num = chip->support_macid_num;
4703
4704 mac_id = find_first_zero_bit(rtwdev->mac_id_map, mac_id_num);
4705 if (mac_id == mac_id_num)
4706 return RTW89_MAX_MAC_ID_NUM;
4707
4708 set_bit(mac_id, rtwdev->mac_id_map);
4709 return mac_id;
4710 }
4711
rtw89_release_mac_id(struct rtw89_dev * rtwdev,u8 mac_id)4712 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id)
4713 {
4714 clear_bit(mac_id, rtwdev->mac_id_map);
4715 }
4716
rtw89_init_vif(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u8 mac_id,u8 port)4717 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4718 u8 mac_id, u8 port)
4719 {
4720 const struct rtw89_chip_info *chip = rtwdev->chip;
4721 u8 support_link_num = chip->support_link_num;
4722 u8 support_mld_num = 0;
4723 unsigned int link_id;
4724 u8 index;
4725
4726 bitmap_zero(rtwvif->links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
4727 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++)
4728 rtwvif->links[link_id] = NULL;
4729
4730 rtwvif->rtwdev = rtwdev;
4731
4732 if (rtwdev->support_mlo) {
4733 rtwvif->links_inst_valid_num = support_link_num;
4734 support_mld_num = chip->support_macid_num / support_link_num;
4735 } else {
4736 rtwvif->links_inst_valid_num = 1;
4737 }
4738
4739 for (index = 0; index < rtwvif->links_inst_valid_num; index++) {
4740 struct rtw89_vif_link *inst = &rtwvif->links_inst[index];
4741
4742 inst->rtwvif = rtwvif;
4743 inst->mac_id = mac_id + index * support_mld_num;
4744 inst->mac_idx = RTW89_MAC_0 + index;
4745 inst->phy_idx = RTW89_PHY_0 + index;
4746
4747 /* multi-link use the same port id on different HW bands */
4748 inst->port = port;
4749 }
4750 }
4751
rtw89_init_sta(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta,u8 mac_id)4752 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4753 struct rtw89_sta *rtwsta, u8 mac_id)
4754 {
4755 const struct rtw89_chip_info *chip = rtwdev->chip;
4756 u8 support_link_num = chip->support_link_num;
4757 u8 support_mld_num = 0;
4758 unsigned int link_id;
4759 u8 index;
4760
4761 bitmap_zero(rtwsta->links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
4762 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++)
4763 rtwsta->links[link_id] = NULL;
4764
4765 rtwsta->rtwdev = rtwdev;
4766 rtwsta->rtwvif = rtwvif;
4767
4768 if (rtwdev->support_mlo) {
4769 rtwsta->links_inst_valid_num = support_link_num;
4770 support_mld_num = chip->support_macid_num / support_link_num;
4771 } else {
4772 rtwsta->links_inst_valid_num = 1;
4773 }
4774
4775 for (index = 0; index < rtwsta->links_inst_valid_num; index++) {
4776 struct rtw89_sta_link *inst = &rtwsta->links_inst[index];
4777
4778 inst->rtwvif_link = &rtwvif->links_inst[index];
4779
4780 inst->rtwsta = rtwsta;
4781 inst->mac_id = mac_id + index * support_mld_num;
4782 }
4783 }
4784
rtw89_vif_set_link(struct rtw89_vif * rtwvif,unsigned int link_id)4785 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif,
4786 unsigned int link_id)
4787 {
4788 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id];
4789 u8 index;
4790 int ret;
4791
4792 if (rtwvif_link)
4793 return rtwvif_link;
4794
4795 index = find_first_zero_bit(rtwvif->links_inst_map,
4796 rtwvif->links_inst_valid_num);
4797 if (index == rtwvif->links_inst_valid_num) {
4798 ret = -EBUSY;
4799 goto err;
4800 }
4801
4802 rtwvif_link = &rtwvif->links_inst[index];
4803 rtwvif_link->link_id = link_id;
4804
4805 set_bit(index, rtwvif->links_inst_map);
4806 rtwvif->links[link_id] = rtwvif_link;
4807 return rtwvif_link;
4808
4809 err:
4810 rtw89_err(rtwvif->rtwdev, "vif (link_id %u) failed to set link: %d\n",
4811 link_id, ret);
4812 return NULL;
4813 }
4814
rtw89_vif_unset_link(struct rtw89_vif * rtwvif,unsigned int link_id)4815 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id)
4816 {
4817 struct rtw89_vif_link **container = &rtwvif->links[link_id];
4818 struct rtw89_vif_link *link = *container;
4819 u8 index;
4820
4821 if (!link)
4822 return;
4823
4824 index = rtw89_vif_link_inst_get_index(link);
4825 clear_bit(index, rtwvif->links_inst_map);
4826 *container = NULL;
4827 }
4828
rtw89_sta_set_link(struct rtw89_sta * rtwsta,unsigned int link_id)4829 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta,
4830 unsigned int link_id)
4831 {
4832 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
4833 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id];
4834 struct rtw89_sta_link *rtwsta_link = rtwsta->links[link_id];
4835 u8 index;
4836 int ret;
4837
4838 if (rtwsta_link)
4839 return rtwsta_link;
4840
4841 if (!rtwvif_link) {
4842 ret = -ENOLINK;
4843 goto err;
4844 }
4845
4846 index = rtw89_vif_link_inst_get_index(rtwvif_link);
4847 if (test_bit(index, rtwsta->links_inst_map)) {
4848 ret = -EBUSY;
4849 goto err;
4850 }
4851
4852 rtwsta_link = &rtwsta->links_inst[index];
4853 rtwsta_link->link_id = link_id;
4854
4855 set_bit(index, rtwsta->links_inst_map);
4856 rtwsta->links[link_id] = rtwsta_link;
4857 return rtwsta_link;
4858
4859 err:
4860 rtw89_err(rtwsta->rtwdev, "sta (link_id %u) failed to set link: %d\n",
4861 link_id, ret);
4862 return NULL;
4863 }
4864
rtw89_sta_unset_link(struct rtw89_sta * rtwsta,unsigned int link_id)4865 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id)
4866 {
4867 struct rtw89_sta_link **container = &rtwsta->links[link_id];
4868 struct rtw89_sta_link *link = *container;
4869 u8 index;
4870
4871 if (!link)
4872 return;
4873
4874 index = rtw89_sta_link_inst_get_index(link);
4875 clear_bit(index, rtwsta->links_inst_map);
4876 *container = NULL;
4877 }
4878
rtw89_core_init(struct rtw89_dev * rtwdev)4879 int rtw89_core_init(struct rtw89_dev *rtwdev)
4880 {
4881 struct rtw89_btc *btc = &rtwdev->btc;
4882 u8 band;
4883
4884 INIT_LIST_HEAD(&rtwdev->ba_list);
4885 INIT_LIST_HEAD(&rtwdev->forbid_ba_list);
4886 INIT_LIST_HEAD(&rtwdev->rtwvifs_list);
4887 INIT_LIST_HEAD(&rtwdev->early_h2c_list);
4888 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) {
4889 if (!(rtwdev->chip->support_bands & BIT(band)))
4890 continue;
4891 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]);
4892 }
4893 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work);
4894 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work);
4895 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work);
4896 INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work);
4897 INIT_DELAYED_WORK(&rtwdev->chanctx_work, rtw89_chanctx_work);
4898 INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work);
4899 INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work);
4900 INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work);
4901 INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work);
4902 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work);
4903 INIT_DELAYED_WORK(&rtwdev->antdiv_work, rtw89_phy_antdiv_work);
4904 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0);
4905 if (!rtwdev->txq_wq)
4906 return -ENOMEM;
4907 spin_lock_init(&rtwdev->ba_lock);
4908 spin_lock_init(&rtwdev->rpwm_lock);
4909 mutex_init(&rtwdev->mutex);
4910 mutex_init(&rtwdev->rf_mutex);
4911 rtwdev->total_sta_assoc = 0;
4912
4913 rtw89_init_wait(&rtwdev->mcc.wait);
4914 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait);
4915 rtw89_init_wait(&rtwdev->wow.wait);
4916 rtw89_init_wait(&rtwdev->mac.ps_wait);
4917
4918 INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work);
4919 INIT_WORK(&rtwdev->ips_work, rtw89_ips_work);
4920 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work);
4921 INIT_WORK(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work);
4922
4923 skb_queue_head_init(&rtwdev->c2h_queue);
4924 rtw89_core_ppdu_sts_init(rtwdev);
4925 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats);
4926
4927 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR;
4928 rtwdev->dbcc_en = false;
4929 rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT;
4930 rtwdev->mac.qta_mode = RTW89_QTA_SCC;
4931
4932 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) {
4933 rtwdev->dbcc_en = true;
4934 rtwdev->mac.qta_mode = RTW89_QTA_DBCC;
4935 rtwdev->mlo_dbcc_mode = MLO_2_PLUS_0_1RF;
4936 }
4937
4938 INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work);
4939 INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work);
4940 INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work);
4941 INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work);
4942
4943 init_completion(&rtwdev->fw.req.completion);
4944 init_completion(&rtwdev->rfk_wait.completion);
4945
4946 schedule_work(&rtwdev->load_firmware_work);
4947
4948 rtw89_ser_init(rtwdev);
4949 rtw89_entity_init(rtwdev);
4950 rtw89_tas_init(rtwdev);
4951 rtw89_phy_ant_gain_init(rtwdev);
4952
4953 return 0;
4954 }
4955 EXPORT_SYMBOL(rtw89_core_init);
4956
rtw89_core_deinit(struct rtw89_dev * rtwdev)4957 void rtw89_core_deinit(struct rtw89_dev *rtwdev)
4958 {
4959 rtw89_ser_deinit(rtwdev);
4960 rtw89_unload_firmware(rtwdev);
4961 rtw89_fw_free_all_early_h2c(rtwdev);
4962
4963 destroy_workqueue(rtwdev->txq_wq);
4964 mutex_destroy(&rtwdev->rf_mutex);
4965 mutex_destroy(&rtwdev->mutex);
4966 }
4967 EXPORT_SYMBOL(rtw89_core_deinit);
4968
rtw89_core_scan_start(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,const u8 * mac_addr,bool hw_scan)4969 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4970 const u8 *mac_addr, bool hw_scan)
4971 {
4972 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
4973 rtwvif_link->chanctx_idx);
4974
4975 rtwdev->scanning = true;
4976 rtw89_leave_lps(rtwdev);
4977 if (hw_scan)
4978 rtw89_leave_ips_by_hwflags(rtwdev);
4979
4980 ether_addr_copy(rtwvif_link->mac_addr, mac_addr);
4981 rtw89_btc_ntfy_scan_start(rtwdev, rtwvif_link->phy_idx, chan->band_type);
4982 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, true);
4983 rtw89_hci_recalc_int_mit(rtwdev);
4984 rtw89_phy_config_edcca(rtwdev, true);
4985
4986 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, mac_addr);
4987 }
4988
rtw89_core_scan_complete(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool hw_scan)4989 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
4990 struct rtw89_vif_link *rtwvif_link, bool hw_scan)
4991 {
4992 struct ieee80211_bss_conf *bss_conf;
4993
4994 if (!rtwvif_link)
4995 return;
4996
4997 rcu_read_lock();
4998
4999 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
5000 ether_addr_copy(rtwvif_link->mac_addr, bss_conf->addr);
5001
5002 rcu_read_unlock();
5003
5004 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL);
5005
5006 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, false);
5007 rtw89_btc_ntfy_scan_finish(rtwdev, rtwvif_link->phy_idx);
5008 rtw89_phy_config_edcca(rtwdev, false);
5009
5010 rtwdev->scanning = false;
5011 rtwdev->dig.bypass_dig = true;
5012 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE))
5013 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work);
5014 }
5015
rtw89_read_chip_ver(struct rtw89_dev * rtwdev)5016 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev)
5017 {
5018 const struct rtw89_chip_info *chip = rtwdev->chip;
5019 int ret;
5020 u8 val;
5021 u8 cv;
5022
5023 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK);
5024 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) {
5025 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD)
5026 cv = CHIP_CAV;
5027 else
5028 cv = CHIP_CBV;
5029 }
5030
5031 rtwdev->hal.cv = cv;
5032
5033 if (rtw89_is_rtl885xb(rtwdev)) {
5034 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val);
5035 if (ret)
5036 return;
5037
5038 rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK);
5039 }
5040 }
5041
rtw89_core_setup_phycap(struct rtw89_dev * rtwdev)5042 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev)
5043 {
5044 const struct rtw89_chip_info *chip = rtwdev->chip;
5045
5046 rtwdev->hal.support_cckpd =
5047 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) &&
5048 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV);
5049 rtwdev->hal.support_igi =
5050 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV;
5051
5052 if (test_bit(RTW89_QUIRK_THERMAL_PROT_120C, rtwdev->quirks))
5053 rtwdev->hal.thermal_prot_th = chip->thermal_th[1];
5054 else if (test_bit(RTW89_QUIRK_THERMAL_PROT_110C, rtwdev->quirks))
5055 rtwdev->hal.thermal_prot_th = chip->thermal_th[0];
5056 else
5057 rtwdev->hal.thermal_prot_th = 0;
5058 }
5059
rtw89_core_setup_rfe_parms(struct rtw89_dev * rtwdev)5060 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev)
5061 {
5062 const struct rtw89_chip_info *chip = rtwdev->chip;
5063 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf;
5064 struct rtw89_efuse *efuse = &rtwdev->efuse;
5065 const struct rtw89_rfe_parms *sel;
5066 u8 rfe_type = efuse->rfe_type;
5067
5068 if (!conf) {
5069 sel = chip->dflt_parms;
5070 goto out;
5071 }
5072
5073 while (conf->rfe_parms) {
5074 if (rfe_type == conf->rfe_type) {
5075 sel = conf->rfe_parms;
5076 goto out;
5077 }
5078 conf++;
5079 }
5080
5081 sel = chip->dflt_parms;
5082
5083 out:
5084 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel);
5085 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl);
5086 }
5087
rtw89_chip_efuse_info_setup(struct rtw89_dev * rtwdev)5088 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev)
5089 {
5090 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
5091 int ret;
5092
5093 ret = rtw89_mac_partial_init(rtwdev, false);
5094 if (ret)
5095 return ret;
5096
5097 ret = mac->parse_efuse_map(rtwdev);
5098 if (ret)
5099 return ret;
5100
5101 ret = mac->parse_phycap_map(rtwdev);
5102 if (ret)
5103 return ret;
5104
5105 ret = rtw89_mac_setup_phycap(rtwdev);
5106 if (ret)
5107 return ret;
5108
5109 rtw89_core_setup_phycap(rtwdev);
5110
5111 rtw89_hci_mac_pre_deinit(rtwdev);
5112
5113 rtw89_mac_pwr_off(rtwdev);
5114
5115 return 0;
5116 }
5117
rtw89_chip_board_info_setup(struct rtw89_dev * rtwdev)5118 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev)
5119 {
5120 rtw89_chip_fem_setup(rtwdev);
5121
5122 return 0;
5123 }
5124
rtw89_chip_has_rfkill(struct rtw89_dev * rtwdev)5125 static bool rtw89_chip_has_rfkill(struct rtw89_dev *rtwdev)
5126 {
5127 return !!rtwdev->chip->rfkill_init;
5128 }
5129
rtw89_core_rfkill_init(struct rtw89_dev * rtwdev)5130 static void rtw89_core_rfkill_init(struct rtw89_dev *rtwdev)
5131 {
5132 const struct rtw89_rfkill_regs *regs = rtwdev->chip->rfkill_init;
5133
5134 rtw89_write16_mask(rtwdev, regs->pinmux.addr,
5135 regs->pinmux.mask, regs->pinmux.data);
5136 rtw89_write16_mask(rtwdev, regs->mode.addr,
5137 regs->mode.mask, regs->mode.data);
5138 }
5139
rtw89_core_rfkill_get(struct rtw89_dev * rtwdev)5140 static bool rtw89_core_rfkill_get(struct rtw89_dev *rtwdev)
5141 {
5142 const struct rtw89_reg_def *reg = &rtwdev->chip->rfkill_get;
5143
5144 return !rtw89_read8_mask(rtwdev, reg->addr, reg->mask);
5145 }
5146
rtw89_rfkill_polling_init(struct rtw89_dev * rtwdev)5147 static void rtw89_rfkill_polling_init(struct rtw89_dev *rtwdev)
5148 {
5149 if (!rtw89_chip_has_rfkill(rtwdev))
5150 return;
5151
5152 rtw89_core_rfkill_init(rtwdev);
5153 rtw89_core_rfkill_poll(rtwdev, true);
5154 wiphy_rfkill_start_polling(rtwdev->hw->wiphy);
5155 }
5156
rtw89_rfkill_polling_deinit(struct rtw89_dev * rtwdev)5157 static void rtw89_rfkill_polling_deinit(struct rtw89_dev *rtwdev)
5158 {
5159 if (!rtw89_chip_has_rfkill(rtwdev))
5160 return;
5161
5162 wiphy_rfkill_stop_polling(rtwdev->hw->wiphy);
5163 }
5164
rtw89_core_rfkill_poll(struct rtw89_dev * rtwdev,bool force)5165 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force)
5166 {
5167 bool prev, blocked;
5168
5169 if (!rtw89_chip_has_rfkill(rtwdev))
5170 return;
5171
5172 prev = test_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags);
5173 blocked = rtw89_core_rfkill_get(rtwdev);
5174
5175 if (!force && prev == blocked)
5176 return;
5177
5178 rtw89_info(rtwdev, "rfkill hardware state changed to %s\n",
5179 blocked ? "disable" : "enable");
5180
5181 if (blocked)
5182 set_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags);
5183 else
5184 clear_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags);
5185
5186 wiphy_rfkill_set_hw_state(rtwdev->hw->wiphy, blocked);
5187 }
5188
rtw89_chip_info_setup(struct rtw89_dev * rtwdev)5189 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev)
5190 {
5191 int ret;
5192
5193 rtw89_read_chip_ver(rtwdev);
5194
5195 ret = rtw89_wait_firmware_completion(rtwdev);
5196 if (ret) {
5197 rtw89_err(rtwdev, "failed to wait firmware completion\n");
5198 return ret;
5199 }
5200
5201 ret = rtw89_fw_recognize(rtwdev);
5202 if (ret) {
5203 rtw89_err(rtwdev, "failed to recognize firmware\n");
5204 return ret;
5205 }
5206
5207 ret = rtw89_chip_efuse_info_setup(rtwdev);
5208 if (ret)
5209 return ret;
5210
5211 ret = rtw89_fw_recognize_elements(rtwdev);
5212 if (ret) {
5213 rtw89_err(rtwdev, "failed to recognize firmware elements\n");
5214 return ret;
5215 }
5216
5217 ret = rtw89_chip_board_info_setup(rtwdev);
5218 if (ret)
5219 return ret;
5220
5221 rtw89_core_setup_rfe_parms(rtwdev);
5222 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev);
5223
5224 return 0;
5225 }
5226 EXPORT_SYMBOL(rtw89_chip_info_setup);
5227
rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)5228 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
5229 struct rtw89_vif_link *rtwvif_link)
5230 {
5231 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
5232 const struct rtw89_chip_info *chip = rtwdev->chip;
5233 struct ieee80211_bss_conf *bss_conf;
5234
5235 rcu_read_lock();
5236
5237 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
5238 if (!bss_conf->he_support || !vif->cfg.assoc) {
5239 rcu_read_unlock();
5240 return;
5241 }
5242
5243 rcu_read_unlock();
5244
5245 if (chip->ops->set_txpwr_ul_tb_offset)
5246 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif_link->mac_idx);
5247 }
5248
rtw89_core_register_hw(struct rtw89_dev * rtwdev)5249 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev)
5250 {
5251 const struct rtw89_chip_info *chip = rtwdev->chip;
5252 u8 n = rtwdev->support_mlo ? chip->support_link_num : 1;
5253 struct ieee80211_hw *hw = rtwdev->hw;
5254 struct rtw89_efuse *efuse = &rtwdev->efuse;
5255 struct rtw89_hal *hal = &rtwdev->hal;
5256 int ret;
5257 int tx_headroom = IEEE80211_HT_CTL_LEN;
5258
5259 hw->vif_data_size = struct_size_t(struct rtw89_vif, links_inst, n);
5260 hw->sta_data_size = struct_size_t(struct rtw89_sta, links_inst, n);
5261 hw->txq_data_size = sizeof(struct rtw89_txq);
5262 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg);
5263
5264 SET_IEEE80211_PERM_ADDR(hw, efuse->addr);
5265
5266 hw->extra_tx_headroom = tx_headroom;
5267 hw->queues = IEEE80211_NUM_ACS;
5268 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM;
5269 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM;
5270 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL;
5271
5272 hw->radiotap_mcs_details |= IEEE80211_RADIOTAP_MCS_HAVE_FEC |
5273 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
5274 hw->radiotap_vht_details |= IEEE80211_RADIOTAP_VHT_KNOWN_STBC;
5275
5276 ieee80211_hw_set(hw, SIGNAL_DBM);
5277 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
5278 ieee80211_hw_set(hw, MFP_CAPABLE);
5279 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
5280 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
5281 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
5282 ieee80211_hw_set(hw, TX_AMSDU);
5283 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
5284 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
5285 ieee80211_hw_set(hw, SUPPORTS_PS);
5286 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
5287 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
5288 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID);
5289 ieee80211_hw_set(hw, WANT_MONITOR_VIF);
5290
5291 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
5292 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW);
5293
5294 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw))
5295 ieee80211_hw_set(hw, CONNECTION_MONITOR);
5296
5297 if (RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &rtwdev->fw))
5298 ieee80211_hw_set(hw, AP_LINK_PS);
5299
5300 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
5301 BIT(NL80211_IFTYPE_AP) |
5302 BIT(NL80211_IFTYPE_P2P_CLIENT) |
5303 BIT(NL80211_IFTYPE_P2P_GO);
5304
5305 if (hal->ant_diversity) {
5306 hw->wiphy->available_antennas_tx = 0x3;
5307 hw->wiphy->available_antennas_rx = 0x3;
5308 } else {
5309 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1;
5310 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1;
5311 }
5312
5313 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
5314 WIPHY_FLAG_TDLS_EXTERNAL_SETUP |
5315 WIPHY_FLAG_AP_UAPSD |
5316 WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK;
5317
5318 if (!chip->support_rnr)
5319 hw->wiphy->flags |= WIPHY_FLAG_SPLIT_SCAN_6GHZ;
5320
5321 if (chip->chip_gen == RTW89_CHIP_BE)
5322 hw->wiphy->flags |= WIPHY_FLAG_DISABLE_WEXT;
5323
5324 if (rtwdev->support_mlo)
5325 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_MLO;
5326
5327 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
5328
5329 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID;
5330 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN;
5331
5332 #ifdef CONFIG_PM
5333 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
5334 hw->wiphy->max_sched_scan_ssids = RTW89_SCANOFLD_MAX_SSID;
5335 #endif
5336
5337 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
5338 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
5339 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL);
5340 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL);
5341 hw->wiphy->max_remain_on_channel_duration = 1000;
5342
5343 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
5344 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN);
5345 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL);
5346
5347 ret = rtw89_core_set_supported_band(rtwdev);
5348 if (ret) {
5349 rtw89_err(rtwdev, "failed to set supported band\n");
5350 return ret;
5351 }
5352
5353 ret = rtw89_regd_setup(rtwdev);
5354 if (ret) {
5355 rtw89_err(rtwdev, "failed to set up regd\n");
5356 goto err_free_supported_band;
5357 }
5358
5359 hw->wiphy->sar_capa = &rtw89_sar_capa;
5360
5361 ret = ieee80211_register_hw(hw);
5362 if (ret) {
5363 rtw89_err(rtwdev, "failed to register hw\n");
5364 goto err_free_supported_band;
5365 }
5366
5367 ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier);
5368 if (ret) {
5369 rtw89_err(rtwdev, "failed to init regd\n");
5370 goto err_unregister_hw;
5371 }
5372
5373 rtw89_rfkill_polling_init(rtwdev);
5374
5375 return 0;
5376
5377 err_unregister_hw:
5378 ieee80211_unregister_hw(hw);
5379 err_free_supported_band:
5380 rtw89_core_clr_supported_band(rtwdev);
5381
5382 return ret;
5383 }
5384
rtw89_core_unregister_hw(struct rtw89_dev * rtwdev)5385 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev)
5386 {
5387 struct ieee80211_hw *hw = rtwdev->hw;
5388
5389 rtw89_rfkill_polling_deinit(rtwdev);
5390 ieee80211_unregister_hw(hw);
5391 rtw89_core_clr_supported_band(rtwdev);
5392 }
5393
rtw89_core_register(struct rtw89_dev * rtwdev)5394 int rtw89_core_register(struct rtw89_dev *rtwdev)
5395 {
5396 int ret;
5397
5398 ret = rtw89_core_register_hw(rtwdev);
5399 if (ret) {
5400 rtw89_err(rtwdev, "failed to register core hw\n");
5401 return ret;
5402 }
5403
5404 rtw89_debugfs_init(rtwdev);
5405
5406 return 0;
5407 }
5408 EXPORT_SYMBOL(rtw89_core_register);
5409
rtw89_core_unregister(struct rtw89_dev * rtwdev)5410 void rtw89_core_unregister(struct rtw89_dev *rtwdev)
5411 {
5412 rtw89_core_unregister_hw(rtwdev);
5413
5414 rtw89_debugfs_deinit(rtwdev);
5415 }
5416 EXPORT_SYMBOL(rtw89_core_unregister);
5417
rtw89_alloc_ieee80211_hw(struct device * device,u32 bus_data_size,const struct rtw89_chip_info * chip,const struct rtw89_chip_variant * variant)5418 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
5419 u32 bus_data_size,
5420 const struct rtw89_chip_info *chip,
5421 const struct rtw89_chip_variant *variant)
5422 {
5423 struct rtw89_fw_info early_fw = {};
5424 const struct firmware *firmware;
5425 struct ieee80211_hw *hw;
5426 struct rtw89_dev *rtwdev;
5427 struct ieee80211_ops *ops;
5428 u32 driver_data_size;
5429 int fw_format = -1;
5430 bool support_mlo;
5431 bool no_chanctx;
5432
5433 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format);
5434
5435 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL);
5436 if (!ops)
5437 goto err;
5438
5439 no_chanctx = chip->support_chanctx_num == 0 ||
5440 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) ||
5441 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw);
5442
5443 if (no_chanctx) {
5444 ops->add_chanctx = ieee80211_emulate_add_chanctx;
5445 ops->remove_chanctx = ieee80211_emulate_remove_chanctx;
5446 ops->change_chanctx = ieee80211_emulate_change_chanctx;
5447 ops->switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx;
5448 ops->assign_vif_chanctx = NULL;
5449 ops->unassign_vif_chanctx = NULL;
5450 ops->remain_on_channel = NULL;
5451 ops->cancel_remain_on_channel = NULL;
5452 }
5453
5454 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size;
5455 hw = ieee80211_alloc_hw(driver_data_size, ops);
5456 if (!hw)
5457 goto err;
5458
5459 /* TODO: When driver MLO arch. is done, determine whether to support MLO
5460 * according to the following conditions.
5461 * 1. run with chanctx_ops
5462 * 2. chip->support_link_num != 0
5463 * 3. FW feature supports AP_LINK_PS
5464 */
5465 support_mlo = false;
5466
5467 hw->wiphy->iface_combinations = rtw89_iface_combs;
5468
5469 if (no_chanctx || chip->support_chanctx_num == 1)
5470 hw->wiphy->n_iface_combinations = 1;
5471 else
5472 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs);
5473
5474 rtwdev = hw->priv;
5475 rtwdev->hw = hw;
5476 rtwdev->dev = device;
5477 rtwdev->ops = ops;
5478 rtwdev->chip = chip;
5479 rtwdev->variant = variant;
5480 rtwdev->fw.req.firmware = firmware;
5481 rtwdev->fw.fw_format = fw_format;
5482 rtwdev->support_mlo = support_mlo;
5483
5484 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s chanctx\n",
5485 no_chanctx ? "without" : "with");
5486 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s MLO cap\n",
5487 support_mlo ? "with" : "without");
5488
5489 return rtwdev;
5490
5491 err:
5492 kfree(ops);
5493 release_firmware(firmware);
5494 return NULL;
5495 }
5496 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw);
5497
rtw89_free_ieee80211_hw(struct rtw89_dev * rtwdev)5498 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev)
5499 {
5500 kfree(rtwdev->ops);
5501 kfree(rtwdev->rfe_data);
5502 release_firmware(rtwdev->fw.req.firmware);
5503 ieee80211_free_hw(rtwdev->hw);
5504 }
5505 EXPORT_SYMBOL(rtw89_free_ieee80211_hw);
5506
5507 MODULE_AUTHOR("Realtek Corporation");
5508 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module");
5509 MODULE_LICENSE("Dual BSD/GPL");
5510