1 /* $FreeBSD: head/sys/dev/usb/controller/xhci.h 276799 2015-01-08 00:12:54Z hselasky $ */ 2 3 /*- 4 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #ifndef _XHCI_H_ 29 #define _XHCI_H_ 30 31 #define XHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128) 32 #define XHCI_MAX_ENDPOINTS 32 /* hardcoded - do not change */ 33 #define XHCI_MAX_SCRATCHPADS 32 34 #define XHCI_MAX_EVENTS (16 * 13) 35 #define XHCI_MAX_COMMANDS (16 * 1) 36 #define XHCI_MAX_RSEG 1 37 #define XHCI_MAX_TRANSFERS 4 38 #if USB_MAX_EP_STREAMS == 8 39 #define XHCI_MAX_STREAMS 8 40 #define XHCI_MAX_STREAMS_LOG 3 41 #elif USB_MAX_EP_STREAMS == 1 42 #define XHCI_MAX_STREAMS 1 43 #define XHCI_MAX_STREAMS_LOG 0 44 #else 45 #error "The USB_MAX_EP_STREAMS value is not supported." 46 #endif 47 #define XHCI_DEV_CTX_ADDR_ALIGN 64 /* bytes */ 48 #define XHCI_DEV_CTX_ALIGN 64 /* bytes */ 49 #define XHCI_INPUT_CTX_ALIGN 64 /* bytes */ 50 #define XHCI_SLOT_CTX_ALIGN 32 /* bytes */ 51 #define XHCI_ENDP_CTX_ALIGN 32 /* bytes */ 52 #define XHCI_STREAM_CTX_ALIGN 16 /* bytes */ 53 #define XHCI_TRANS_RING_SEG_ALIGN 16 /* bytes */ 54 #define XHCI_CMD_RING_SEG_ALIGN 64 /* bytes */ 55 #define XHCI_EVENT_RING_SEG_ALIGN 64 /* bytes */ 56 #define XHCI_SCRATCH_BUF_ARRAY_ALIGN 64 /* bytes */ 57 #define XHCI_SCRATCH_BUFFER_ALIGN USB_PAGE_SIZE 58 #define XHCI_TRB_ALIGN 16 /* bytes */ 59 #define XHCI_TD_ALIGN 64 /* bytes */ 60 #define XHCI_PAGE_SIZE 4096 /* bytes */ 61 62 struct xhci_dev_ctx_addr { 63 volatile uint64_t qwBaaDevCtxAddr[USB_MAX_DEVICES + 1]; 64 struct { 65 volatile uint64_t dummy; 66 } __aligned(64) padding; 67 volatile uint64_t qwSpBufPtr[XHCI_MAX_SCRATCHPADS]; 68 }; 69 70 #define XHCI_EPNO2EPID(x) \ 71 ((((x) & UE_DIR_IN) ? 1 : 0) | (2 * ((x) & UE_ADDR))) 72 73 struct xhci_slot_ctx { 74 volatile uint32_t dwSctx0; 75 #define XHCI_SCTX_0_ROUTE_SET(x) ((x) & 0xFFFFF) 76 #define XHCI_SCTX_0_ROUTE_GET(x) ((x) & 0xFFFFF) 77 #define XHCI_SCTX_0_SPEED_SET(x) (((x) & 0xF) << 20) 78 #define XHCI_SCTX_0_SPEED_GET(x) (((x) >> 20) & 0xF) 79 #define XHCI_SCTX_0_MTT_SET(x) (((x) & 0x1) << 25) 80 #define XHCI_SCTX_0_MTT_GET(x) (((x) >> 25) & 0x1) 81 #define XHCI_SCTX_0_HUB_SET(x) (((x) & 0x1) << 26) 82 #define XHCI_SCTX_0_HUB_GET(x) (((x) >> 26) & 0x1) 83 #define XHCI_SCTX_0_CTX_NUM_SET(x) (((x) & 0x1F) << 27) 84 #define XHCI_SCTX_0_CTX_NUM_GET(x) (((x) >> 27) & 0x1F) 85 volatile uint32_t dwSctx1; 86 #define XHCI_SCTX_1_MAX_EL_SET(x) ((x) & 0xFFFF) 87 #define XHCI_SCTX_1_MAX_EL_GET(x) ((x) & 0xFFFF) 88 #define XHCI_SCTX_1_RH_PORT_SET(x) (((x) & 0xFF) << 16) 89 #define XHCI_SCTX_1_RH_PORT_GET(x) (((x) >> 16) & 0xFF) 90 #define XHCI_SCTX_1_NUM_PORTS_SET(x) (((x) & 0xFF) << 24) 91 #define XHCI_SCTX_1_NUM_PORTS_GET(x) (((x) >> 24) & 0xFF) 92 volatile uint32_t dwSctx2; 93 #define XHCI_SCTX_2_TT_HUB_SID_SET(x) ((x) & 0xFF) 94 #define XHCI_SCTX_2_TT_HUB_SID_GET(x) ((x) & 0xFF) 95 #define XHCI_SCTX_2_TT_PORT_NUM_SET(x) (((x) & 0xFF) << 8) 96 #define XHCI_SCTX_2_TT_PORT_NUM_GET(x) (((x) >> 8) & 0xFF) 97 #define XHCI_SCTX_2_TT_THINK_TIME_SET(x) (((x) & 0x3) << 16) 98 #define XHCI_SCTX_2_TT_THINK_TIME_GET(x) (((x) >> 16) & 0x3) 99 #define XHCI_SCTX_2_IRQ_TARGET_SET(x) (((x) & 0x3FF) << 22) 100 #define XHCI_SCTX_2_IRQ_TARGET_GET(x) (((x) >> 22) & 0x3FF) 101 volatile uint32_t dwSctx3; 102 #define XHCI_SCTX_3_DEV_ADDR_SET(x) ((x) & 0xFF) 103 #define XHCI_SCTX_3_DEV_ADDR_GET(x) ((x) & 0xFF) 104 #define XHCI_SCTX_3_SLOT_STATE_SET(x) (((x) & 0x1F) << 27) 105 #define XHCI_SCTX_3_SLOT_STATE_GET(x) (((x) >> 27) & 0x1F) 106 volatile uint32_t dwSctx4; 107 volatile uint32_t dwSctx5; 108 volatile uint32_t dwSctx6; 109 volatile uint32_t dwSctx7; 110 }; 111 112 struct xhci_endp_ctx { 113 volatile uint32_t dwEpCtx0; 114 #define XHCI_EPCTX_0_EPSTATE_SET(x) ((x) & 0x7) 115 #define XHCI_EPCTX_0_EPSTATE_GET(x) ((x) & 0x7) 116 #define XHCI_EPCTX_0_MULT_SET(x) (((x) & 0x3) << 8) 117 #define XHCI_EPCTX_0_MULT_GET(x) (((x) >> 8) & 0x3) 118 #define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) (((x) & 0x1F) << 10) 119 #define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) (((x) >> 10) & 0x1F) 120 #define XHCI_EPCTX_0_LSA_SET(x) (((x) & 0x1) << 15) 121 #define XHCI_EPCTX_0_LSA_GET(x) (((x) >> 15) & 0x1) 122 #define XHCI_EPCTX_0_IVAL_SET(x) (((x) & 0xFF) << 16) 123 #define XHCI_EPCTX_0_IVAL_GET(x) (((x) >> 16) & 0xFF) 124 volatile uint32_t dwEpCtx1; 125 #define XHCI_EPCTX_1_CERR_SET(x) (((x) & 0x3) << 1) 126 #define XHCI_EPCTX_1_CERR_GET(x) (((x) >> 1) & 0x3) 127 #define XHCI_EPCTX_1_EPTYPE_SET(x) (((x) & 0x7) << 3) 128 #define XHCI_EPCTX_1_EPTYPE_GET(x) (((x) >> 3) & 0x7) 129 #define XHCI_EPCTX_1_HID_SET(x) (((x) & 0x1) << 7) 130 #define XHCI_EPCTX_1_HID_GET(x) (((x) >> 7) & 0x1) 131 #define XHCI_EPCTX_1_MAXB_SET(x) (((x) & 0xFF) << 8) 132 #define XHCI_EPCTX_1_MAXB_GET(x) (((x) >> 8) & 0xFF) 133 #define XHCI_EPCTX_1_MAXP_SIZE_SET(x) (((x) & 0xFFFF) << 16) 134 #define XHCI_EPCTX_1_MAXP_SIZE_GET(x) (((x) >> 16) & 0xFFFF) 135 volatile uint64_t qwEpCtx2; 136 #define XHCI_EPCTX_2_DCS_SET(x) ((x) & 0x1) 137 #define XHCI_EPCTX_2_DCS_GET(x) ((x) & 0x1) 138 #define XHCI_EPCTX_2_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U 139 volatile uint32_t dwEpCtx4; 140 #define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) ((x) & 0xFFFF) 141 #define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) ((x) & 0xFFFF) 142 #define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) (((x) & 0xFFFF) << 16) 143 #define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) (((x) >> 16) & 0xFFFF) 144 volatile uint32_t dwEpCtx5; 145 volatile uint32_t dwEpCtx6; 146 volatile uint32_t dwEpCtx7; 147 }; 148 149 struct xhci_input_ctx { 150 #define XHCI_INCTX_NON_CTRL_MASK 0xFFFFFFFCU 151 volatile uint32_t dwInCtx0; 152 #define XHCI_INCTX_0_DROP_MASK(n) (1U << (n)) 153 volatile uint32_t dwInCtx1; 154 #define XHCI_INCTX_1_ADD_MASK(n) (1U << (n)) 155 volatile uint32_t dwInCtx2; 156 volatile uint32_t dwInCtx3; 157 volatile uint32_t dwInCtx4; 158 volatile uint32_t dwInCtx5; 159 volatile uint32_t dwInCtx6; 160 volatile uint32_t dwInCtx7; 161 }; 162 163 struct xhci_input_dev_ctx { 164 struct xhci_input_ctx ctx_input; 165 struct xhci_slot_ctx ctx_slot; 166 struct xhci_endp_ctx ctx_ep[XHCI_MAX_ENDPOINTS - 1]; 167 }; 168 169 struct xhci_dev_ctx { 170 struct xhci_slot_ctx ctx_slot; 171 struct xhci_endp_ctx ctx_ep[XHCI_MAX_ENDPOINTS - 1]; 172 } __aligned(XHCI_DEV_CTX_ALIGN); 173 174 struct xhci_stream_ctx { 175 volatile uint64_t qwSctx0; 176 #define XHCI_SCTX_0_DCS_GET(x) ((x) & 0x1) 177 #define XHCI_SCTX_0_DCS_SET(x) ((x) & 0x1) 178 #define XHCI_SCTX_0_SCT_SET(x) (((x) & 0x7) << 1) 179 #define XHCI_SCTX_0_SCT_GET(x) (((x) >> 1) & 0x7) 180 #define XHCI_SCTX_0_SCT_SEC_TR_RING 0x0 181 #define XHCI_SCTX_0_SCT_PRIM_TR_RING 0x1 182 #define XHCI_SCTX_0_SCT_PRIM_SSA_8 0x2 183 #define XHCI_SCTX_0_SCT_PRIM_SSA_16 0x3 184 #define XHCI_SCTX_0_SCT_PRIM_SSA_32 0x4 185 #define XHCI_SCTX_0_SCT_PRIM_SSA_64 0x5 186 #define XHCI_SCTX_0_SCT_PRIM_SSA_128 0x6 187 #define XHCI_SCTX_0_SCT_PRIM_SSA_256 0x7 188 #define XHCI_SCTX_0_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U 189 volatile uint32_t dwSctx2; 190 volatile uint32_t dwSctx3; 191 }; 192 193 struct xhci_trb { 194 volatile uint64_t qwTrb0; 195 #define XHCI_TRB_0_DIR_IN_MASK (0x80ULL << 0) 196 #define XHCI_TRB_0_WLENGTH_MASK (0xFFFFULL << 48) 197 volatile uint32_t dwTrb2; 198 #define XHCI_TRB_2_ERROR_GET(x) (((x) >> 24) & 0xFF) 199 #define XHCI_TRB_2_ERROR_SET(x) (((x) & 0xFF) << 24) 200 #define XHCI_TRB_2_TDSZ_GET(x) (((x) >> 17) & 0x1F) 201 #define XHCI_TRB_2_TDSZ_SET(x) (((x) & 0x1F) << 17) 202 #define XHCI_TRB_2_REM_GET(x) ((x) & 0xFFFFFF) 203 #define XHCI_TRB_2_REM_SET(x) ((x) & 0xFFFFFF) 204 #define XHCI_TRB_2_BYTES_GET(x) ((x) & 0x1FFFF) 205 #define XHCI_TRB_2_BYTES_SET(x) ((x) & 0x1FFFF) 206 #define XHCI_TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF) 207 #define XHCI_TRB_2_IRQ_SET(x) (((x) & 0x3FF) << 22) 208 #define XHCI_TRB_2_STREAM_GET(x) (((x) >> 16) & 0xFFFF) 209 #define XHCI_TRB_2_STREAM_SET(x) (((x) & 0xFFFF) << 16) 210 211 volatile uint32_t dwTrb3; 212 #define XHCI_TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F) 213 #define XHCI_TRB_3_TYPE_SET(x) (((x) & 0x3F) << 10) 214 #define XHCI_TRB_3_CYCLE_BIT (1U << 0) 215 #define XHCI_TRB_3_TC_BIT (1U << 1) /* command ring only */ 216 #define XHCI_TRB_3_ENT_BIT (1U << 1) /* transfer ring only */ 217 #define XHCI_TRB_3_ISP_BIT (1U << 2) 218 #define XHCI_TRB_3_NSNOOP_BIT (1U << 3) 219 #define XHCI_TRB_3_CHAIN_BIT (1U << 4) 220 #define XHCI_TRB_3_IOC_BIT (1U << 5) 221 #define XHCI_TRB_3_IDT_BIT (1U << 6) 222 #define XHCI_TRB_3_TBC_GET(x) (((x) >> 7) & 3) 223 #define XHCI_TRB_3_TBC_SET(x) (((x) & 3) << 7) 224 #define XHCI_TRB_3_BEI_BIT (1U << 9) 225 #define XHCI_TRB_3_DCEP_BIT (1U << 9) 226 #define XHCI_TRB_3_PRSV_BIT (1U << 9) 227 #define XHCI_TRB_3_BSR_BIT (1U << 9) 228 #define XHCI_TRB_3_TRT_MASK (3U << 16) 229 #define XHCI_TRB_3_TRT_NONE (0U << 16) 230 #define XHCI_TRB_3_TRT_OUT (2U << 16) 231 #define XHCI_TRB_3_TRT_IN (3U << 16) 232 #define XHCI_TRB_3_DIR_IN (1U << 16) 233 #define XHCI_TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xF) 234 #define XHCI_TRB_3_TLBPC_SET(x) (((x) & 0xF) << 16) 235 #define XHCI_TRB_3_EP_GET(x) (((x) >> 16) & 0x1F) 236 #define XHCI_TRB_3_EP_SET(x) (((x) & 0x1F) << 16) 237 #define XHCI_TRB_3_FRID_GET(x) (((x) >> 20) & 0x7FF) 238 #define XHCI_TRB_3_FRID_SET(x) (((x) & 0x7FF) << 20) 239 #define XHCI_TRB_3_ISO_SIA_BIT (1U << 31) 240 #define XHCI_TRB_3_SUSP_EP_BIT (1U << 23) 241 #define XHCI_TRB_3_SLOT_GET(x) (((x) >> 24) & 0xFF) 242 #define XHCI_TRB_3_SLOT_SET(x) (((x) & 0xFF) << 24) 243 244 /* Commands */ 245 #define XHCI_TRB_TYPE_RESERVED 0x00 246 #define XHCI_TRB_TYPE_NORMAL 0x01 247 #define XHCI_TRB_TYPE_SETUP_STAGE 0x02 248 #define XHCI_TRB_TYPE_DATA_STAGE 0x03 249 #define XHCI_TRB_TYPE_STATUS_STAGE 0x04 250 #define XHCI_TRB_TYPE_ISOCH 0x05 251 #define XHCI_TRB_TYPE_LINK 0x06 252 #define XHCI_TRB_TYPE_EVENT_DATA 0x07 253 #define XHCI_TRB_TYPE_NOOP 0x08 254 #define XHCI_TRB_TYPE_ENABLE_SLOT 0x09 255 #define XHCI_TRB_TYPE_DISABLE_SLOT 0x0A 256 #define XHCI_TRB_TYPE_ADDRESS_DEVICE 0x0B 257 #define XHCI_TRB_TYPE_CONFIGURE_EP 0x0C 258 #define XHCI_TRB_TYPE_EVALUATE_CTX 0x0D 259 #define XHCI_TRB_TYPE_RESET_EP 0x0E 260 #define XHCI_TRB_TYPE_STOP_EP 0x0F 261 #define XHCI_TRB_TYPE_SET_TR_DEQUEUE 0x10 262 #define XHCI_TRB_TYPE_RESET_DEVICE 0x11 263 #define XHCI_TRB_TYPE_FORCE_EVENT 0x12 264 #define XHCI_TRB_TYPE_NEGOTIATE_BW 0x13 265 #define XHCI_TRB_TYPE_SET_LATENCY_TOL 0x14 266 #define XHCI_TRB_TYPE_GET_PORT_BW 0x15 267 #define XHCI_TRB_TYPE_FORCE_HEADER 0x16 268 #define XHCI_TRB_TYPE_NOOP_CMD 0x17 269 270 /* Events */ 271 #define XHCI_TRB_EVENT_TRANSFER 0x20 272 #define XHCI_TRB_EVENT_CMD_COMPLETE 0x21 273 #define XHCI_TRB_EVENT_PORT_STS_CHANGE 0x22 274 #define XHCI_TRB_EVENT_BW_REQUEST 0x23 275 #define XHCI_TRB_EVENT_DOORBELL 0x24 276 #define XHCI_TRB_EVENT_HOST_CTRL 0x25 277 #define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26 278 #define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27 279 280 /* Error codes */ 281 #define XHCI_TRB_ERROR_INVALID 0x00 282 #define XHCI_TRB_ERROR_SUCCESS 0x01 283 #define XHCI_TRB_ERROR_DATA_BUF 0x02 284 #define XHCI_TRB_ERROR_BABBLE 0x03 285 #define XHCI_TRB_ERROR_XACT 0x04 286 #define XHCI_TRB_ERROR_TRB 0x05 287 #define XHCI_TRB_ERROR_STALL 0x06 288 #define XHCI_TRB_ERROR_RESOURCE 0x07 289 #define XHCI_TRB_ERROR_BANDWIDTH 0x08 290 #define XHCI_TRB_ERROR_NO_SLOTS 0x09 291 #define XHCI_TRB_ERROR_STREAM_TYPE 0x0A 292 #define XHCI_TRB_ERROR_SLOT_NOT_ON 0x0B 293 #define XHCI_TRB_ERROR_ENDP_NOT_ON 0x0C 294 #define XHCI_TRB_ERROR_SHORT_PKT 0x0D 295 #define XHCI_TRB_ERROR_RING_UNDERRUN 0x0E 296 #define XHCI_TRB_ERROR_RING_OVERRUN 0x0F 297 #define XHCI_TRB_ERROR_VF_RING_FULL 0x10 298 #define XHCI_TRB_ERROR_PARAMETER 0x11 299 #define XHCI_TRB_ERROR_BW_OVERRUN 0x12 300 #define XHCI_TRB_ERROR_CONTEXT_STATE 0x13 301 #define XHCI_TRB_ERROR_NO_PING_RESP 0x14 302 #define XHCI_TRB_ERROR_EV_RING_FULL 0x15 303 #define XHCI_TRB_ERROR_INCOMPAT_DEV 0x16 304 #define XHCI_TRB_ERROR_MISSED_SERVICE 0x17 305 #define XHCI_TRB_ERROR_CMD_RING_STOP 0x18 306 #define XHCI_TRB_ERROR_CMD_ABORTED 0x19 307 #define XHCI_TRB_ERROR_STOPPED 0x1A 308 #define XHCI_TRB_ERROR_LENGTH 0x1B 309 #define XHCI_TRB_ERROR_BAD_MELAT 0x1D 310 #define XHCI_TRB_ERROR_ISOC_OVERRUN 0x1F 311 #define XHCI_TRB_ERROR_EVENT_LOST 0x20 312 #define XHCI_TRB_ERROR_UNDEFINED 0x21 313 #define XHCI_TRB_ERROR_INVALID_SID 0x22 314 #define XHCI_TRB_ERROR_SEC_BW 0x23 315 #define XHCI_TRB_ERROR_SPLIT_XACT 0x24 316 } __aligned(4); 317 318 struct xhci_dev_endpoint_trbs { 319 struct xhci_trb trb[(XHCI_MAX_STREAMS * 320 XHCI_MAX_TRANSFERS) + XHCI_MAX_STREAMS]; 321 }; 322 323 #if (USB_PAGE_SIZE < 4096) 324 #error "The XHCI driver needs a pagesize above or equal to 4K" 325 #endif 326 327 /* Define the maximum payload which we will handle in a single TRB */ 328 #define XHCI_TD_PAYLOAD_MAX 65536 /* bytes */ 329 330 /* Define the maximum payload of a single scatter-gather list element */ 331 #define XHCI_TD_PAGE_SIZE \ 332 ((USB_PAGE_SIZE < XHCI_TD_PAYLOAD_MAX) ? USB_PAGE_SIZE : XHCI_TD_PAYLOAD_MAX) 333 334 /* Define the maximum length of the scatter-gather list */ 335 #define XHCI_TD_PAGE_NBUF \ 336 (((XHCI_TD_PAYLOAD_MAX + XHCI_TD_PAGE_SIZE - 1) / XHCI_TD_PAGE_SIZE) + 1) 337 338 struct xhci_td { 339 /* one LINK TRB has been added to the TRB array */ 340 struct xhci_trb td_trb[XHCI_TD_PAGE_NBUF + 1]; 341 342 /* 343 * Extra information needed: 344 */ 345 uint64_t td_self; 346 struct xhci_td *next; 347 struct xhci_td *alt_next; 348 struct xhci_td *obj_next; 349 struct usb_page_cache *page_cache; 350 uint32_t len; 351 uint32_t remainder; 352 uint8_t ntrb; 353 uint8_t status; 354 } __aligned(XHCI_TRB_ALIGN); 355 356 struct xhci_command { 357 struct xhci_trb trb; 358 TAILQ_ENTRY(xhci_command) entry; 359 }; 360 361 struct xhci_event_ring_seg { 362 volatile uint64_t qwEvrsTablePtr; 363 volatile uint32_t dwEvrsTableSize; 364 volatile uint32_t dwEvrsReserved; 365 }; 366 367 struct xhci_hw_root { 368 struct xhci_event_ring_seg hwr_ring_seg[XHCI_MAX_RSEG]; 369 struct { 370 volatile uint64_t dummy; 371 } __aligned(64) padding; 372 struct xhci_trb hwr_events[XHCI_MAX_EVENTS]; 373 struct xhci_trb hwr_commands[XHCI_MAX_COMMANDS]; 374 }; 375 376 struct xhci_endpoint_ext { 377 struct xhci_trb *trb; 378 struct usb_xfer *xfer[XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS]; 379 struct usb_page_cache *page_cache; 380 uint64_t physaddr; 381 uint8_t trb_used[XHCI_MAX_STREAMS]; 382 uint8_t trb_index[XHCI_MAX_STREAMS]; 383 uint8_t trb_halted; 384 uint8_t trb_running; 385 uint8_t trb_ep_mode; 386 uint8_t trb_ep_maxp; 387 }; 388 389 enum { 390 XHCI_ST_DISABLED, 391 XHCI_ST_ENABLED, 392 XHCI_ST_DEFAULT, 393 XHCI_ST_ADDRESSED, 394 XHCI_ST_CONFIGURED, 395 XHCI_ST_MAX 396 }; 397 398 struct xhci_hw_dev { 399 struct usb_page_cache device_pc; 400 struct usb_page_cache input_pc; 401 struct usb_page_cache endpoint_pc[XHCI_MAX_ENDPOINTS]; 402 403 struct usb_page device_pg; 404 struct usb_page input_pg; 405 struct usb_page endpoint_pg[XHCI_MAX_ENDPOINTS]; 406 407 struct xhci_endpoint_ext endp[XHCI_MAX_ENDPOINTS]; 408 409 uint8_t state; 410 uint8_t nports; 411 uint8_t tt; 412 uint8_t context_num; 413 }; 414 415 struct xhci_hw_softc { 416 struct usb_page_cache root_pc; 417 struct usb_page_cache ctx_pc; 418 struct usb_page_cache scratch_pc[XHCI_MAX_SCRATCHPADS]; 419 420 struct usb_page root_pg; 421 struct usb_page ctx_pg; 422 struct usb_page scratch_pg[XHCI_MAX_SCRATCHPADS]; 423 424 struct xhci_hw_dev devs[XHCI_MAX_DEVICES + 1]; 425 }; 426 427 struct xhci_config_desc { 428 struct usb_config_descriptor confd; 429 struct usb_interface_descriptor ifcd; 430 struct usb_endpoint_descriptor endpd; 431 struct usb_endpoint_ss_comp_descriptor endpcd; 432 } __packed; 433 434 struct xhci_bos_desc { 435 struct usb_bos_descriptor bosd; 436 struct usb_devcap_usb2ext_descriptor usb2extd; 437 struct usb_devcap_ss_descriptor usbdcd; 438 struct usb_devcap_container_id_descriptor cidd; 439 } __packed; 440 441 union xhci_hub_desc { 442 struct usb_status stat; 443 struct usb_port_status ps; 444 struct usb_hub_ss_descriptor hubd; 445 uint8_t temp[128]; 446 }; 447 448 typedef int (xhci_port_route_t)(device_t, uint32_t, uint32_t); 449 450 struct xhci_softc { 451 struct xhci_hw_softc sc_hw; 452 /* base device */ 453 struct usb_bus sc_bus; 454 /* configure message */ 455 struct usb_bus_msg sc_config_msg[2]; 456 457 struct usb_callout sc_callout; 458 459 xhci_port_route_t *sc_port_route; 460 461 union xhci_hub_desc sc_hub_desc; 462 463 struct cv sc_cmd_cv; 464 struct lock sc_cmd_lock; 465 466 struct usb_device *sc_devices[XHCI_MAX_DEVICES]; 467 struct resource *sc_io_res; 468 int sc_irq_rid; 469 struct resource *sc_irq_res; 470 471 void *sc_intr_hdl; 472 bus_size_t sc_io_size; 473 bus_space_tag_t sc_io_tag; 474 bus_space_handle_t sc_io_hdl; 475 /* last pending command address */ 476 uint64_t sc_cmd_addr; 477 /* result of command */ 478 uint32_t sc_cmd_result[2]; 479 /* copy of cmd register */ 480 uint32_t sc_cmd; 481 /* worst case exit latency */ 482 uint32_t sc_exit_lat_max; 483 484 /* offset to operational registers */ 485 uint32_t sc_oper_off; 486 /* offset to capability registers */ 487 uint32_t sc_capa_off; 488 /* offset to runtime registers */ 489 uint32_t sc_runt_off; 490 /* offset to doorbell registers */ 491 uint32_t sc_door_off; 492 493 /* chip specific */ 494 uint16_t sc_erst_max; 495 uint16_t sc_event_idx; 496 uint16_t sc_command_idx; 497 uint16_t sc_imod_default; 498 499 uint8_t sc_event_ccs; 500 uint8_t sc_command_ccs; 501 /* number of XHCI device slots */ 502 uint8_t sc_noslot; 503 /* number of ports on root HUB */ 504 uint8_t sc_noport; 505 /* number of scratch pages */ 506 uint8_t sc_noscratch; 507 /* root HUB device configuration */ 508 uint8_t sc_conf; 509 /* root HUB port event bitmap, max 256 ports */ 510 uint8_t sc_hub_idata[32]; 511 512 /* size of context */ 513 uint8_t sc_ctx_is_64_byte; 514 515 /* vendor string for root HUB */ 516 char sc_vendor[16]; 517 }; 518 519 #define XHCI_CMD_LOCK(sc) lockmgr(&(sc)->sc_cmd_lock, LK_EXCLUSIVE) 520 #define XHCI_CMD_UNLOCK(sc) lockmgr(&(sc)->sc_cmd_lock, LK_RELEASE) 521 #define XHCI_CMD_ASSERT_LOCKED(sc) KKASSERT(lockstatus(&(sc)->sc_cmd_lock, curthread) == LK_EXCLUSIVE) 522 523 /* prototypes */ 524 525 uint8_t xhci_use_polling(void); 526 usb_error_t xhci_halt_controller(struct xhci_softc *); 527 usb_error_t xhci_init(struct xhci_softc *, device_t, uint8_t); 528 usb_error_t xhci_start_controller(struct xhci_softc *); 529 void xhci_interrupt(struct xhci_softc *); 530 void xhci_uninit(struct xhci_softc *); 531 532 #endif /* _XHCI_H_ */ 533