1 /*-
2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved.
3 * Copyright (c) 2022 NVIDIA corporation & affiliates.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #ifndef MLX5_DRIVER_H
28 #define MLX5_DRIVER_H
29
30 #include "opt_ratelimit.h"
31
32 #include <linux/kernel.h>
33 #include <linux/completion.h>
34 #include <linux/pci.h>
35 #include <linux/cache.h>
36 #include <linux/rbtree.h>
37 #include <linux/if_ether.h>
38 #include <linux/semaphore.h>
39 #include <linux/slab.h>
40 #include <linux/vmalloc.h>
41 #include <linux/radix-tree.h>
42 #include <linux/idr.h>
43 #include <linux/wait.h>
44
45 #include <dev/mlx5/device.h>
46 #include <dev/mlx5/doorbell.h>
47 #include <dev/mlx5/srq.h>
48
49 #define MLX5_QCOUNTER_SETS_NETDEV 64
50 #define MLX5_MAX_NUMBER_OF_VFS 128
51
52 #define MLX5_INVALID_QUEUE_HANDLE 0xffffffff
53
54 enum {
55 MLX5_BOARD_ID_LEN = 64,
56 MLX5_MAX_NAME_LEN = 16,
57 };
58
59 enum {
60 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
61 };
62
63 enum {
64 CMD_OWNER_SW = 0x0,
65 CMD_OWNER_HW = 0x1,
66 CMD_STATUS_SUCCESS = 0,
67 };
68
69 enum mlx5_sqp_t {
70 MLX5_SQP_SMI = 0,
71 MLX5_SQP_GSI = 1,
72 MLX5_SQP_IEEE_1588 = 2,
73 MLX5_SQP_SNIFFER = 3,
74 MLX5_SQP_SYNC_UMR = 4,
75 };
76
77 enum {
78 MLX5_MAX_PORTS = 2,
79 };
80
81 enum {
82 MLX5_EQ_VEC_PAGES = 0,
83 MLX5_EQ_VEC_CMD = 1,
84 MLX5_EQ_VEC_ASYNC = 2,
85 MLX5_EQ_VEC_COMP_BASE,
86 };
87
88 enum {
89 MLX5_ATOMIC_MODE_OFF = 16,
90 MLX5_ATOMIC_MODE_NONE = 0 << MLX5_ATOMIC_MODE_OFF,
91 MLX5_ATOMIC_MODE_IB_COMP = 1 << MLX5_ATOMIC_MODE_OFF,
92 MLX5_ATOMIC_MODE_CX = 2 << MLX5_ATOMIC_MODE_OFF,
93 MLX5_ATOMIC_MODE_8B = 3 << MLX5_ATOMIC_MODE_OFF,
94 MLX5_ATOMIC_MODE_16B = 4 << MLX5_ATOMIC_MODE_OFF,
95 MLX5_ATOMIC_MODE_32B = 5 << MLX5_ATOMIC_MODE_OFF,
96 MLX5_ATOMIC_MODE_64B = 6 << MLX5_ATOMIC_MODE_OFF,
97 MLX5_ATOMIC_MODE_128B = 7 << MLX5_ATOMIC_MODE_OFF,
98 MLX5_ATOMIC_MODE_256B = 8 << MLX5_ATOMIC_MODE_OFF,
99 };
100
101 enum {
102 MLX5_ATOMIC_MODE_DCT_OFF = 20,
103 MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF,
104 MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF,
105 MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF,
106 MLX5_ATOMIC_MODE_DCT_8B = 3 << MLX5_ATOMIC_MODE_DCT_OFF,
107 MLX5_ATOMIC_MODE_DCT_16B = 4 << MLX5_ATOMIC_MODE_DCT_OFF,
108 MLX5_ATOMIC_MODE_DCT_32B = 5 << MLX5_ATOMIC_MODE_DCT_OFF,
109 MLX5_ATOMIC_MODE_DCT_64B = 6 << MLX5_ATOMIC_MODE_DCT_OFF,
110 MLX5_ATOMIC_MODE_DCT_128B = 7 << MLX5_ATOMIC_MODE_DCT_OFF,
111 MLX5_ATOMIC_MODE_DCT_256B = 8 << MLX5_ATOMIC_MODE_DCT_OFF,
112 };
113
114 enum {
115 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
116 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
117 MLX5_ATOMIC_OPS_MASKED_CMP_SWAP = 1 << 2,
118 MLX5_ATOMIC_OPS_MASKED_FETCH_ADD = 1 << 3,
119 };
120
121 enum {
122 MLX5_REG_QPTS = 0x4002,
123 MLX5_REG_QETCR = 0x4005,
124 MLX5_REG_QPDP = 0x4007,
125 MLX5_REG_QTCT = 0x400A,
126 MLX5_REG_QPDPM = 0x4013,
127 MLX5_REG_QHLL = 0x4016,
128 MLX5_REG_QCAM = 0x4019,
129 MLX5_REG_DCBX_PARAM = 0x4020,
130 MLX5_REG_DCBX_APP = 0x4021,
131 MLX5_REG_FPGA_CAP = 0x4022,
132 MLX5_REG_FPGA_CTRL = 0x4023,
133 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
134 MLX5_REG_FPGA_SHELL_CNTR = 0x4025,
135 MLX5_REG_PCAP = 0x5001,
136 MLX5_REG_PMLP = 0x5002,
137 MLX5_REG_PMTU = 0x5003,
138 MLX5_REG_PTYS = 0x5004,
139 MLX5_REG_PAOS = 0x5006,
140 MLX5_REG_PFCC = 0x5007,
141 MLX5_REG_PPCNT = 0x5008,
142 MLX5_REG_PUDE = 0x5009,
143 MLX5_REG_PPTB = 0x500B,
144 MLX5_REG_PBMC = 0x500C,
145 MLX5_REG_PELC = 0x500E,
146 MLX5_REG_PVLC = 0x500F,
147 MLX5_REG_PMPE = 0x5010,
148 MLX5_REG_PMAOS = 0x5012,
149 MLX5_REG_PPLM = 0x5023,
150 MLX5_REG_PDDR = 0x5031,
151 MLX5_REG_PBSR = 0x5038,
152 MLX5_REG_PCAM = 0x507f,
153 MLX5_REG_NODE_DESC = 0x6001,
154 MLX5_REG_HOST_ENDIANNESS = 0x7004,
155 MLX5_REG_MTMP = 0x900a,
156 MLX5_REG_MCIA = 0x9014,
157 MLX5_REG_MFRL = 0x9028,
158 MLX5_REG_MPCNT = 0x9051,
159 MLX5_REG_MCQI = 0x9061,
160 MLX5_REG_MCC = 0x9062,
161 MLX5_REG_MCDA = 0x9063,
162 MLX5_REG_MCAM = 0x907f,
163 };
164
165 enum dbg_rsc_type {
166 MLX5_DBG_RSC_QP,
167 MLX5_DBG_RSC_EQ,
168 MLX5_DBG_RSC_CQ,
169 };
170
171 enum {
172 MLX5_INTERFACE_PROTOCOL_IB = 0,
173 MLX5_INTERFACE_PROTOCOL_ETH = 1,
174 MLX5_INTERFACE_NUMBER = 2,
175 };
176
177 struct mlx5_field_desc {
178 int i;
179 };
180
181 struct mlx5_rsc_debug {
182 struct mlx5_core_dev *dev;
183 void *object;
184 enum dbg_rsc_type type;
185 struct mlx5_field_desc fields[0];
186 };
187
188 enum mlx5_dev_event {
189 MLX5_DEV_EVENT_SYS_ERROR,
190 MLX5_DEV_EVENT_PORT_UP,
191 MLX5_DEV_EVENT_PORT_DOWN,
192 MLX5_DEV_EVENT_PORT_INITIALIZED,
193 MLX5_DEV_EVENT_LID_CHANGE,
194 MLX5_DEV_EVENT_PKEY_CHANGE,
195 MLX5_DEV_EVENT_GUID_CHANGE,
196 MLX5_DEV_EVENT_CLIENT_REREG,
197 MLX5_DEV_EVENT_VPORT_CHANGE,
198 MLX5_DEV_EVENT_ERROR_STATE_DCBX,
199 MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE,
200 MLX5_DEV_EVENT_LOCAL_OPER_CHANGE,
201 MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE,
202 };
203
204 enum mlx5_port_status {
205 MLX5_PORT_UP = 1 << 0,
206 MLX5_PORT_DOWN = 1 << 1,
207 };
208
209 enum {
210 MLX5_VSC_SPACE_SUPPORTED = 0x1,
211 MLX5_VSC_SPACE_OFFSET = 0x4,
212 MLX5_VSC_COUNTER_OFFSET = 0x8,
213 MLX5_VSC_SEMA_OFFSET = 0xC,
214 MLX5_VSC_ADDR_OFFSET = 0x10,
215 MLX5_VSC_DATA_OFFSET = 0x14,
216 MLX5_VSC_MAX_RETRIES = 0x1000,
217 };
218
219 #define MLX5_PROT_MASK(link_mode) (1 << link_mode)
220
221 struct mlx5_cmd_first {
222 __be32 data[4];
223 };
224
225 struct cache_ent;
226 struct mlx5_fw_page {
227 union {
228 struct rb_node rb_node;
229 struct list_head list;
230 };
231 struct mlx5_cmd_first first;
232 struct mlx5_core_dev *dev;
233 bus_dmamap_t dma_map;
234 bus_addr_t dma_addr;
235 void *virt_addr;
236 struct cache_ent *cache;
237 u32 numpages;
238 u16 load_done;
239 #define MLX5_LOAD_ST_NONE 0
240 #define MLX5_LOAD_ST_SUCCESS 1
241 #define MLX5_LOAD_ST_FAILURE 2
242 u16 func_id;
243 };
244 #define mlx5_cmd_msg mlx5_fw_page
245
246 struct mlx5_cmd_debug {
247 void *in_msg;
248 void *out_msg;
249 u8 status;
250 u16 inlen;
251 u16 outlen;
252 };
253
254 struct cache_ent {
255 /* protect block chain allocations
256 */
257 spinlock_t lock;
258 struct list_head head;
259 };
260
261 struct cmd_msg_cache {
262 struct cache_ent large;
263 struct cache_ent med;
264
265 };
266
267 struct mlx5_traffic_counter {
268 u64 packets;
269 u64 octets;
270 };
271
272 enum mlx5_cmd_mode {
273 MLX5_CMD_MODE_POLLING,
274 MLX5_CMD_MODE_EVENTS
275 };
276
277 struct mlx5_cmd_stats {
278 u64 sum;
279 u64 n;
280 /* protect command average calculations */
281 spinlock_t lock;
282 };
283
284 struct mlx5_cmd {
285 struct mlx5_fw_page *cmd_page;
286 bus_dma_tag_t dma_tag;
287 struct sx dma_sx;
288 struct mtx dma_mtx;
289 #define MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx)
290 #define MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx)
291 #define MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx)
292 struct cv dma_cv;
293 #define MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv)
294 #define MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx)
295 void *cmd_buf;
296 dma_addr_t dma;
297 u16 cmdif_rev;
298 u8 log_sz;
299 u8 log_stride;
300 int max_reg_cmds;
301 int events;
302 u32 __iomem *vector;
303
304 /* protect command queue allocations
305 */
306 spinlock_t alloc_lock;
307
308 /* protect token allocations
309 */
310 spinlock_t token_lock;
311 u8 token;
312 unsigned long bitmask;
313 struct semaphore sem;
314 struct semaphore pages_sem;
315 enum mlx5_cmd_mode mode;
316 struct mlx5_cmd_work_ent * volatile ent_arr[MLX5_MAX_COMMANDS];
317 volatile enum mlx5_cmd_mode ent_mode[MLX5_MAX_COMMANDS];
318 struct mlx5_cmd_debug dbg;
319 struct cmd_msg_cache cache;
320 int checksum_disabled;
321 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
322 };
323
324 struct mlx5_port_caps {
325 int gid_table_len;
326 int pkey_table_len;
327 u8 ext_port_cap;
328 };
329
330 struct mlx5_buf {
331 bus_dma_tag_t dma_tag;
332 bus_dmamap_t dma_map;
333 struct mlx5_core_dev *dev;
334 struct {
335 void *buf;
336 } direct;
337 u64 *page_list;
338 int npages;
339 int size;
340 u8 page_shift;
341 u8 load_done;
342 };
343
344 struct mlx5_frag_buf {
345 struct mlx5_buf_list *frags;
346 int npages;
347 int size;
348 u8 page_shift;
349 };
350
351 struct mlx5_eq {
352 struct mlx5_core_dev *dev;
353 __be32 __iomem *doorbell;
354 u32 cons_index;
355 struct mlx5_buf buf;
356 int size;
357 u8 irqn;
358 u8 eqn;
359 int nent;
360 u64 mask;
361 struct list_head list;
362 int index;
363 struct mlx5_rsc_debug *dbg;
364 };
365
366 struct mlx5_core_psv {
367 u32 psv_idx;
368 struct psv_layout {
369 u32 pd;
370 u16 syndrome;
371 u16 reserved;
372 u16 bg;
373 u16 app_tag;
374 u32 ref_tag;
375 } psv;
376 };
377
378 struct mlx5_core_sig_ctx {
379 struct mlx5_core_psv psv_memory;
380 struct mlx5_core_psv psv_wire;
381 struct ib_sig_err err_item;
382 bool sig_status_checked;
383 bool sig_err_exists;
384 u32 sigerr_count;
385 };
386
387 enum {
388 MLX5_MKEY_MR = 1,
389 MLX5_MKEY_MW,
390 MLX5_MKEY_MR_USER,
391 };
392
393 struct mlx5_core_mkey {
394 u64 iova;
395 u64 size;
396 u32 key;
397 u32 pd;
398 u32 type;
399 };
400
401 struct mlx5_core_mr {
402 u64 iova;
403 u64 size;
404 u32 key;
405 u32 pd;
406 };
407
408 enum mlx5_res_type {
409 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
410 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
411 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
412 MLX5_RES_SRQ = 3,
413 MLX5_RES_XSRQ = 4,
414 MLX5_RES_DCT = 5,
415 };
416
417 struct mlx5_core_rsc_common {
418 enum mlx5_res_type res;
419 atomic_t refcount;
420 struct completion free;
421 };
422
423 struct mlx5_uars_page {
424 void __iomem *map;
425 bool wc;
426 u32 index;
427 struct list_head list;
428 unsigned int bfregs;
429 unsigned long *reg_bitmap; /* for non fast path bf regs */
430 unsigned long *fp_bitmap;
431 unsigned int reg_avail;
432 unsigned int fp_avail;
433 struct kref ref_count;
434 struct mlx5_core_dev *mdev;
435 };
436
437 struct mlx5_bfreg_head {
438 /* protect blue flame registers allocations */
439 struct mutex lock;
440 struct list_head list;
441 };
442
443 struct mlx5_bfreg_data {
444 struct mlx5_bfreg_head reg_head;
445 struct mlx5_bfreg_head wc_head;
446 };
447
448 struct mlx5_sq_bfreg {
449 void __iomem *map;
450 struct mlx5_uars_page *up;
451 bool wc;
452 u32 index;
453 unsigned int offset;
454 };
455
456 struct mlx5_core_srq {
457 struct mlx5_core_rsc_common common; /* must be first */
458 u32 srqn;
459 int max;
460 size_t max_gs;
461 size_t max_avail_gather;
462 int wqe_shift;
463 void (*event)(struct mlx5_core_srq *, int);
464 atomic_t refcount;
465 struct completion free;
466 };
467
468 struct mlx5_eq_table {
469 void __iomem *update_ci;
470 void __iomem *update_arm_ci;
471 struct list_head comp_eqs_list;
472 struct mlx5_eq pages_eq;
473 struct mlx5_eq async_eq;
474 struct mlx5_eq cmd_eq;
475 int num_comp_vectors;
476 /* protect EQs list
477 */
478 spinlock_t lock;
479 };
480
481 struct mlx5_core_health {
482 struct mlx5_health_buffer __iomem *health;
483 __be32 __iomem *health_counter;
484 struct timer_list timer;
485 u32 prev;
486 int miss_counter;
487 u32 fatal_error;
488 struct workqueue_struct *wq_watchdog;
489 struct work_struct work_watchdog;
490 /* wq spinlock to synchronize draining */
491 spinlock_t wq_lock;
492 struct workqueue_struct *wq;
493 unsigned long flags;
494 struct work_struct work;
495 struct delayed_work recover_work;
496 unsigned int last_reset_req;
497 struct work_struct work_cmd_completion;
498 struct workqueue_struct *wq_cmd;
499 };
500
501 #define MLX5_CQ_LINEAR_ARRAY_SIZE 1024
502
503 struct mlx5_cq_linear_array_entry {
504 struct mlx5_core_cq * volatile cq;
505 };
506
507 struct mlx5_cq_table {
508 /* protect radix tree
509 */
510 spinlock_t writerlock;
511 atomic_t writercount;
512 struct radix_tree_root tree;
513 struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE];
514 };
515
516 struct mlx5_qp_table {
517 /* protect radix tree
518 */
519 spinlock_t lock;
520 struct radix_tree_root tree;
521 };
522
523 struct mlx5_srq_table {
524 /* protect radix tree
525 */
526 spinlock_t lock;
527 struct radix_tree_root tree;
528 };
529
530 struct mlx5_mr_table {
531 /* protect radix tree
532 */
533 spinlock_t lock;
534 struct radix_tree_root tree;
535 };
536
537 #ifdef RATELIMIT
538 struct mlx5_rl_entry {
539 u32 rate;
540 u16 burst;
541 u16 index;
542 u32 qos_handle; /* schedule queue handle */
543 u32 refcount;
544 };
545
546 struct mlx5_rl_table {
547 struct mutex rl_lock;
548 u16 max_size;
549 u32 max_rate;
550 u32 min_rate;
551 struct mlx5_rl_entry *rl_entry;
552 };
553 #endif
554
555 struct mlx5_pme_stats {
556 u64 status_counters[MLX5_MODULE_STATUS_NUM];
557 u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
558 };
559
560 struct mlx5_priv {
561 char name[MLX5_MAX_NAME_LEN];
562 struct mlx5_eq_table eq_table;
563 struct msix_entry *msix_arr;
564 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
565 int disable_irqs;
566
567 /* pages stuff */
568 struct workqueue_struct *pg_wq;
569 struct rb_root page_root;
570 s64 fw_pages;
571 atomic_t reg_pages;
572 s64 pages_per_func[MLX5_MAX_NUMBER_OF_VFS];
573 struct mlx5_core_health health;
574
575 struct mlx5_srq_table srq_table;
576
577 /* start: qp staff */
578 struct mlx5_qp_table qp_table;
579
580 /* end: qp staff */
581
582 /* start: cq staff */
583 struct mlx5_cq_table cq_table;
584 /* end: cq staff */
585
586 /* start: mr staff */
587 struct mlx5_mr_table mr_table;
588 /* end: mr staff */
589
590 /* start: alloc staff */
591 int numa_node;
592
593 struct mutex pgdir_mutex;
594 struct list_head pgdir_list;
595 /* end: alloc staff */
596
597 /* protect mkey key part */
598 spinlock_t mkey_lock;
599 u8 mkey_key;
600
601 struct list_head dev_list;
602 struct list_head ctx_list;
603 spinlock_t ctx_lock;
604 unsigned long pci_dev_data;
605 #ifdef RATELIMIT
606 struct mlx5_rl_table rl_table;
607 #endif
608 struct mlx5_pme_stats pme_stats;
609
610 struct mlx5_eswitch *eswitch;
611
612 struct mlx5_bfreg_data bfregs;
613 struct mlx5_uars_page *uar;
614 };
615
616 enum mlx5_device_state {
617 MLX5_DEVICE_STATE_UP,
618 MLX5_DEVICE_STATE_INTERNAL_ERROR,
619 };
620
621 enum mlx5_interface_state {
622 MLX5_INTERFACE_STATE_UP = 0x1,
623 MLX5_INTERFACE_STATE_TEARDOWN = 0x2,
624 };
625
626 enum mlx5_pci_status {
627 MLX5_PCI_STATUS_DISABLED,
628 MLX5_PCI_STATUS_ENABLED,
629 };
630
631 #define MLX5_MAX_RESERVED_GIDS 8
632
633 struct mlx5_rsvd_gids {
634 unsigned int start;
635 unsigned int count;
636 struct ida ida;
637 };
638
639 struct mlx5_special_contexts {
640 int resd_lkey;
641 };
642
643 struct mlx5_diag_cnt_id {
644 u16 id;
645 bool enabled;
646 };
647
648 struct mlx5_diag_cnt {
649 #define DIAG_LOCK(dc) mutex_lock(&(dc)->lock)
650 #define DIAG_UNLOCK(dc) mutex_unlock(&(dc)->lock)
651 struct mutex lock;
652 struct sysctl_ctx_list sysctl_ctx;
653 struct mlx5_diag_cnt_id *cnt_id;
654 u16 num_of_samples;
655 u16 sample_index;
656 u8 num_cnt_id;
657 u8 log_num_of_samples;
658 u8 log_sample_period;
659 u8 flag;
660 u8 ready;
661 };
662
663 struct mlx5_flow_root_namespace;
664 struct mlx5_core_dev {
665 struct pci_dev *pdev;
666 /* sync pci state */
667 struct mutex pci_status_mutex;
668 enum mlx5_pci_status pci_status;
669 char board_id[MLX5_BOARD_ID_LEN];
670 struct mlx5_cmd cmd;
671 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
672 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
673 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
674 struct {
675 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
676 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
677 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
678 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
679 } caps;
680 phys_addr_t iseg_base;
681 struct mlx5_init_seg __iomem *iseg;
682 enum mlx5_device_state state;
683 /* sync interface state */
684 struct mutex intf_state_mutex;
685 unsigned long intf_state;
686 void (*event) (struct mlx5_core_dev *dev,
687 enum mlx5_dev_event event,
688 unsigned long param);
689 struct mlx5_priv priv;
690 struct mlx5_profile *profile;
691 atomic_t num_qps;
692 struct mlx5_diag_cnt diag_cnt;
693 u32 vsc_addr;
694 u32 issi;
695 struct mlx5_special_contexts special_contexts;
696 unsigned int module_status[MLX5_MAX_PORTS];
697 struct mlx5_flow_root_namespace *root_ns;
698 struct mlx5_flow_root_namespace *fdb_root_ns;
699 struct mlx5_flow_root_namespace *esw_egress_root_ns;
700 struct mlx5_flow_root_namespace *esw_ingress_root_ns;
701 struct mlx5_flow_root_namespace *sniffer_rx_root_ns;
702 struct mlx5_flow_root_namespace *sniffer_tx_root_ns;
703 u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER];
704 struct mlx5_crspace_regmap *dump_rege;
705 uint32_t *dump_data;
706 unsigned dump_size;
707 bool dump_valid;
708 bool dump_copyout;
709 struct mtx dump_lock;
710
711 bool iov_pf;
712
713 struct sysctl_ctx_list sysctl_ctx;
714 int msix_eqvec;
715 int pwr_status;
716 int pwr_value;
717
718 struct {
719 struct mlx5_rsvd_gids reserved_gids;
720 atomic_t roce_en;
721 } roce;
722
723 struct {
724 spinlock_t spinlock;
725 #define MLX5_MPFS_TABLE_MAX 32
726 long bitmap[BITS_TO_LONGS(MLX5_MPFS_TABLE_MAX)];
727 } mpfs;
728 #ifdef CONFIG_MLX5_FPGA
729 struct mlx5_fpga_device *fpga;
730 #endif
731 };
732
733 enum {
734 MLX5_WOL_DISABLE = 0,
735 MLX5_WOL_SECURED_MAGIC = 1 << 1,
736 MLX5_WOL_MAGIC = 1 << 2,
737 MLX5_WOL_ARP = 1 << 3,
738 MLX5_WOL_BROADCAST = 1 << 4,
739 MLX5_WOL_MULTICAST = 1 << 5,
740 MLX5_WOL_UNICAST = 1 << 6,
741 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
742 };
743
744 struct mlx5_db {
745 __be32 *db;
746 union {
747 struct mlx5_db_pgdir *pgdir;
748 struct mlx5_ib_user_db_page *user_page;
749 } u;
750 dma_addr_t dma;
751 int index;
752 };
753
754 struct mlx5_net_counters {
755 u64 packets;
756 u64 octets;
757 };
758
759 struct mlx5_ptys_reg {
760 u8 an_dis_admin;
761 u8 an_dis_ap;
762 u8 local_port;
763 u8 proto_mask;
764 u32 eth_proto_cap;
765 u16 ib_link_width_cap;
766 u16 ib_proto_cap;
767 u32 eth_proto_admin;
768 u16 ib_link_width_admin;
769 u16 ib_proto_admin;
770 u32 eth_proto_oper;
771 u16 ib_link_width_oper;
772 u16 ib_proto_oper;
773 u32 eth_proto_lp_advertise;
774 };
775
776 struct mlx5_pvlc_reg {
777 u8 local_port;
778 u8 vl_hw_cap;
779 u8 vl_admin;
780 u8 vl_operational;
781 };
782
783 struct mlx5_pmtu_reg {
784 u8 local_port;
785 u16 max_mtu;
786 u16 admin_mtu;
787 u16 oper_mtu;
788 };
789
790 struct mlx5_vport_counters {
791 struct mlx5_net_counters received_errors;
792 struct mlx5_net_counters transmit_errors;
793 struct mlx5_net_counters received_ib_unicast;
794 struct mlx5_net_counters transmitted_ib_unicast;
795 struct mlx5_net_counters received_ib_multicast;
796 struct mlx5_net_counters transmitted_ib_multicast;
797 struct mlx5_net_counters received_eth_broadcast;
798 struct mlx5_net_counters transmitted_eth_broadcast;
799 struct mlx5_net_counters received_eth_unicast;
800 struct mlx5_net_counters transmitted_eth_unicast;
801 struct mlx5_net_counters received_eth_multicast;
802 struct mlx5_net_counters transmitted_eth_multicast;
803 };
804
805 enum {
806 MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES,
807 };
808
809 struct mlx5_core_dct {
810 struct mlx5_core_rsc_common common; /* must be first */
811 void (*event)(struct mlx5_core_dct *, int);
812 int dctn;
813 struct completion drained;
814 struct mlx5_rsc_debug *dbg;
815 int pid;
816 u16 uid;
817 };
818
819 enum {
820 MLX5_PTYS_IB = 1 << 0,
821 MLX5_PTYS_EN = 1 << 2,
822 };
823
824 struct mlx5_db_pgdir {
825 struct list_head list;
826 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
827 struct mlx5_fw_page *fw_page;
828 __be32 *db_page;
829 dma_addr_t db_dma;
830 };
831
832 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
833
834 struct mlx5_cmd_work_ent {
835 struct mlx5_cmd_msg *in;
836 struct mlx5_cmd_msg *out;
837 int uin_size;
838 void *uout;
839 int uout_size;
840 mlx5_cmd_cbk_t callback;
841 struct delayed_work cb_timeout_work;
842 void *context;
843 int idx;
844 struct completion done;
845 struct mlx5_cmd *cmd;
846 struct work_struct work;
847 struct mlx5_cmd_layout *lay;
848 int ret;
849 int page_queue;
850 u8 status;
851 u8 token;
852 u64 ts1;
853 u64 ts2;
854 u16 op;
855 u8 busy;
856 bool polling;
857 };
858
859 struct mlx5_pas {
860 u64 pa;
861 u8 log_sz;
862 };
863
864 enum port_state_policy {
865 MLX5_POLICY_DOWN = 0,
866 MLX5_POLICY_UP = 1,
867 MLX5_POLICY_FOLLOW = 2,
868 MLX5_POLICY_INVALID = 0xffffffff
869 };
870
871 static inline void *
mlx5_buf_offset(struct mlx5_buf * buf,int offset)872 mlx5_buf_offset(struct mlx5_buf *buf, int offset)
873 {
874 return ((char *)buf->direct.buf + offset);
875 }
876
877
878 extern struct workqueue_struct *mlx5_core_wq;
879
880 #define STRUCT_FIELD(header, field) \
881 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
882 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
883
pci2mlx5_core_dev(struct pci_dev * pdev)884 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
885 {
886 return pci_get_drvdata(pdev);
887 }
888
fw_rev_maj(struct mlx5_core_dev * dev)889 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
890 {
891 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
892 }
893
fw_rev_min(struct mlx5_core_dev * dev)894 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
895 {
896 return ioread32be(&dev->iseg->fw_rev) >> 16;
897 }
898
fw_rev_sub(struct mlx5_core_dev * dev)899 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
900 {
901 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
902 }
903
cmdif_rev_get(struct mlx5_core_dev * dev)904 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev)
905 {
906 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
907 }
908
mlx5_get_gid_table_len(u16 param)909 static inline int mlx5_get_gid_table_len(u16 param)
910 {
911 if (param > 4) {
912 printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n");
913 return 0;
914 }
915
916 return 8 * (1 << param);
917 }
918
mlx5_vzalloc(unsigned long size)919 static inline void *mlx5_vzalloc(unsigned long size)
920 {
921 void *rtn;
922
923 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
924 return rtn;
925 }
926
mlx5_vmalloc(unsigned long size)927 static inline void *mlx5_vmalloc(unsigned long size)
928 {
929 void *rtn;
930
931 rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN);
932 if (!rtn)
933 rtn = vmalloc(size);
934 return rtn;
935 }
936
mlx5_base_mkey(const u32 key)937 static inline u32 mlx5_base_mkey(const u32 key)
938 {
939 return key & 0xffffff00u;
940 }
941
942 int mlx5_cmd_init(struct mlx5_core_dev *dev);
943 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
944 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
945 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
946 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
947 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
948
949 struct mlx5_async_ctx {
950 struct mlx5_core_dev *dev;
951 atomic_t num_inflight;
952 struct wait_queue_head wait;
953 };
954
955 struct mlx5_async_work;
956
957 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
958
959 struct mlx5_async_work {
960 struct mlx5_async_ctx *ctx;
961 mlx5_async_cbk_t user_callback;
962 };
963
964 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
965 struct mlx5_async_ctx *ctx);
966 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
967 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
968 void *out, int out_size, mlx5_async_cbk_t callback,
969 struct mlx5_async_work *work);
970 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
971 int out_size);
972 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
973 void *out, int out_size);
974 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
975 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
976 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
977 bool map_wc, bool fast_path);
978 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
979 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
980 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
981 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
982 int mlx5_health_init(struct mlx5_core_dev *dev);
983 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
984 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
985 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
986 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
987 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
988 void mlx5_trigger_health_watchdog(struct mlx5_core_dev *dev);
989
990 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
991 struct mlx5_buf *buf);
992 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
993 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
994 struct mlx5_srq_attr *in);
995 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
996 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
997 struct mlx5_srq_attr *out);
998 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
999 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1000 u16 lwm, int is_srq);
1001 void mlx5_init_mr_table(struct mlx5_core_dev *dev);
1002 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
1003 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
1004 struct mlx5_core_mr *mkey,
1005 struct mlx5_async_ctx *async_ctx, u32 *in,
1006 int inlen, u32 *out, int outlen,
1007 mlx5_async_cbk_t callback,
1008 struct mlx5_async_work *context);
1009 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
1010 struct mlx5_core_mr *mr,
1011 u32 *in, int inlen);
1012 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey);
1013 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey,
1014 u32 *out, int outlen);
1015 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
1016 u32 *mkey);
1017 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1018 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1019 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
1020 u16 opmod, u8 port);
1021 void mlx5_fwp_flush(struct mlx5_fw_page *fwp);
1022 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp);
1023 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num);
1024 void mlx5_fwp_free(struct mlx5_fw_page *fwp);
1025 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset);
1026 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset);
1027 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1028 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1029 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1030 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1031 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1032 s32 npages);
1033 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1034 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1035 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev);
1036 void mlx5_register_debugfs(void);
1037 void mlx5_unregister_debugfs(void);
1038 int mlx5_eq_init(struct mlx5_core_dev *dev);
1039 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
1040 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
1041 void mlx5_cq_completion(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
1042 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1043 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1044 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1045 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector, enum mlx5_cmd_mode mode);
1046 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
1047 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
1048 int nent, u64 mask);
1049 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1050 int mlx5_start_eqs(struct mlx5_core_dev *dev);
1051 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
1052 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
1053 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1054 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1055 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
1056 u64 addr);
1057
1058 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1059 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1060 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1061 int size_in, void *data_out, int size_out,
1062 u16 reg_num, int arg, int write);
1063
1064 void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
1065
1066 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1067 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1068 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1069 u32 *out, int outlen);
1070 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1071 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1072 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1073 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1074 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1075 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1076
1077 static inline struct domainset *
mlx5_dev_domainset(struct mlx5_core_dev * mdev)1078 mlx5_dev_domainset(struct mlx5_core_dev *mdev)
1079 {
1080 return (linux_get_vm_domain_set(mdev->priv.numa_node));
1081 }
1082
1083 const char *mlx5_command_str(int command);
1084 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1085 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1086 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1087 int npsvs, u32 *sig_index);
1088 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1089 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1090 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev);
1091 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode);
1092 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout);
1093 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout);
1094 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode);
1095 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev,
1096 struct mlx5_pvlc_reg *pvlc, int write);
1097 int mlx5_core_access_ptys(struct mlx5_core_dev *dev,
1098 struct mlx5_ptys_reg *ptys, int write);
1099 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev,
1100 struct mlx5_pmtu_reg *pmtu, int write);
1101 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port);
1102 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port);
1103 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1104 int priority, int *is_enable);
1105 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1106 int priority, int enable);
1107 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol,
1108 void *out, int out_size);
1109 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev,
1110 void *in, int in_size);
1111 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear,
1112 void *out, int out_size);
1113 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in,
1114 int in_size);
1115 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev,
1116 u8 num_of_samples, u16 sample_index,
1117 void *out, int out_size);
1118 int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev);
1119 int mlx5_vsc_lock(struct mlx5_core_dev *mdev);
1120 void mlx5_vsc_unlock(struct mlx5_core_dev *mdev);
1121 int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space);
1122 int mlx5_vsc_wait_on_flag(struct mlx5_core_dev *mdev, u32 expected);
1123 int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data);
1124 int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data);
1125 int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1126 int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1127 int mlx5_pci_read_power_status(struct mlx5_core_dev *mdev,
1128 u16 *p_power, u8 *p_status);
1129
mlx5_mkey_to_idx(u32 mkey)1130 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1131 {
1132 return mkey >> 8;
1133 }
1134
mlx5_idx_to_mkey(u32 mkey_idx)1135 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1136 {
1137 return mkey_idx << 8;
1138 }
1139
mlx5_mkey_variant(u32 mkey)1140 static inline u8 mlx5_mkey_variant(u32 mkey)
1141 {
1142 return mkey & 0xff;
1143 }
1144
1145 enum {
1146 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
1147 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
1148 };
1149
1150 enum {
1151 MAX_MR_CACHE_ENTRIES = 15,
1152 };
1153
1154 struct mlx5_interface {
1155 void * (*add)(struct mlx5_core_dev *dev);
1156 void (*remove)(struct mlx5_core_dev *dev, void *context);
1157 void (*event)(struct mlx5_core_dev *dev, void *context,
1158 enum mlx5_dev_event event, unsigned long param);
1159 void * (*get_dev)(void *context);
1160 int protocol;
1161 struct list_head list;
1162 };
1163
1164 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1165 int mlx5_register_interface(struct mlx5_interface *intf);
1166 void mlx5_unregister_interface(struct mlx5_interface *intf);
1167
1168 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1169 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1170 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1171 const u8 *mac, bool vlan, u16 vlan_id);
1172
1173 struct mlx5_profile {
1174 u64 mask;
1175 u8 log_max_qp;
1176 struct {
1177 int size;
1178 int limit;
1179 } mr_cache[MAX_MR_CACHE_ENTRIES];
1180 };
1181
1182 enum {
1183 MLX5_PCI_DEV_IS_VF = 1 << 0,
1184 };
1185
1186 enum {
1187 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1188 };
1189
mlx5_core_is_pf(struct mlx5_core_dev * dev)1190 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1191 {
1192 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1193 }
1194 #ifdef RATELIMIT
1195 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1196 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1197 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst, u16 *index);
1198 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst);
1199 bool mlx5_rl_is_in_range(const struct mlx5_core_dev *dev, u32 rate, u32 burst);
1200 int mlx5e_query_rate_limit_cmd(struct mlx5_core_dev *dev, u16 index, u32 *scq_handle);
1201
mlx5_rl_get_scq_handle(struct mlx5_core_dev * dev,uint16_t index)1202 static inline u32 mlx5_rl_get_scq_handle(struct mlx5_core_dev *dev, uint16_t index)
1203 {
1204 KASSERT(index > 0,
1205 ("invalid rate index for sq remap, failed retrieving SCQ handle"));
1206
1207 return (dev->priv.rl_table.rl_entry[index - 1].qos_handle);
1208 }
1209
mlx5_rl_is_supported(struct mlx5_core_dev * dev)1210 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1211 {
1212 return !!(dev->priv.rl_table.max_size);
1213 }
1214 #endif
1215
1216 void mlx5_disable_interrupts(struct mlx5_core_dev *);
1217 void mlx5_poll_interrupts(struct mlx5_core_dev *);
1218
mlx5_get_qp_default_ts(struct mlx5_core_dev * dev)1219 static inline int mlx5_get_qp_default_ts(struct mlx5_core_dev *dev)
1220 {
1221 return !MLX5_CAP_ROCE(dev, qp_ts_format) ?
1222 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
1223 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
1224 }
1225
mlx5_get_rq_default_ts(struct mlx5_core_dev * dev)1226 static inline int mlx5_get_rq_default_ts(struct mlx5_core_dev *dev)
1227 {
1228 return !MLX5_CAP_GEN(dev, rq_ts_format) ?
1229 MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING :
1230 MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT;
1231 }
1232
mlx5_get_sq_default_ts(struct mlx5_core_dev * dev)1233 static inline int mlx5_get_sq_default_ts(struct mlx5_core_dev *dev)
1234 {
1235 return !MLX5_CAP_GEN(dev, sq_ts_format) ?
1236 MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING :
1237 MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT;
1238 }
1239
1240 #endif /* MLX5_DRIVER_H */
1241