1 /*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30
31 #include <linux/bitfield.h>
32 #include <linux/byteorder/generic.h>
33 #include <linux/cec.h>
34 #include <linux/hdmi.h>
35 #include <linux/i2c.h>
36 #include <linux/kernel.h>
37 #include <linux/module.h>
38 #include <linux/pci.h>
39 #include <linux/seq_buf.h>
40 #include <linux/slab.h>
41 #include <linux/vga_switcheroo.h>
42
43 #include <drm/drm_drv.h>
44 #include <drm/drm_edid.h>
45 #include <drm/drm_eld.h>
46 #include <drm/drm_encoder.h>
47 #include <drm/drm_print.h>
48
49 #include "drm_crtc_internal.h"
50 #include "drm_displayid_internal.h"
51 #include "drm_internal.h"
52
oui(u8 first,u8 second,u8 third)53 static int oui(u8 first, u8 second, u8 third)
54 {
55 return (first << 16) | (second << 8) | third;
56 }
57
58 #define EDID_EST_TIMINGS 16
59 #define EDID_STD_TIMINGS 8
60 #define EDID_DETAILED_TIMINGS 4
61
62 /*
63 * EDID blocks out in the wild have a variety of bugs, try to collect
64 * them here (note that userspace may work around broken monitors first,
65 * but fixes should make their way here so that the kernel "just works"
66 * on as many displays as possible).
67 */
68
69 /* First detailed mode wrong, use largest 60Hz mode */
70 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
71 /* Reported 135MHz pixel clock is too high, needs adjustment */
72 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
73 /* Prefer the largest mode at 75 Hz */
74 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
75 /* Detail timing is in cm not mm */
76 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
77 /* Detailed timing descriptors have bogus size values, so just take the
78 * maximum size and use that.
79 */
80 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
81 /* use +hsync +vsync for detailed mode */
82 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
83 /* Force reduced-blanking timings for detailed modes */
84 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
85 /* Force 8bpc */
86 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
87 /* Force 12bpc */
88 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
89 /* Force 6bpc */
90 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
91 /* Force 10bpc */
92 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
93 /* Non desktop display (i.e. HMD) */
94 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
95 /* Cap the DSC target bitrate to 15bpp */
96 #define EDID_QUIRK_CAP_DSC_15BPP (1 << 13)
97
98 #define MICROSOFT_IEEE_OUI 0xca125c
99
100 struct detailed_mode_closure {
101 struct drm_connector *connector;
102 const struct drm_edid *drm_edid;
103 bool preferred;
104 int modes;
105 };
106
107 struct drm_edid_match_closure {
108 const struct drm_edid_ident *ident;
109 bool matched;
110 };
111
112 #define LEVEL_DMT 0
113 #define LEVEL_GTF 1
114 #define LEVEL_GTF2 2
115 #define LEVEL_CVT 3
116
117 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
118 { \
119 .ident = { \
120 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, \
121 vend_chr_2, product_id), \
122 }, \
123 .quirks = _quirks \
124 }
125
126 static const struct edid_quirk {
127 const struct drm_edid_ident ident;
128 u32 quirks;
129 } edid_quirk_list[] = {
130 /* Acer AL1706 */
131 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
132 /* Acer F51 */
133 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
134
135 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
136 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
137
138 /* BenQ GW2765 */
139 EDID_QUIRK('B', 'N', 'Q', 0x78d6, EDID_QUIRK_FORCE_8BPC),
140
141 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
142 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
143
144 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
145 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
146
147 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
148 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
149
150 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
151 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
152
153 /* Belinea 10 15 55 */
154 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
155 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
156
157 /* Envision Peripherals, Inc. EN-7100e */
158 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
159 /* Envision EN2028 */
160 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
161
162 /* Funai Electronics PM36B */
163 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
164 EDID_QUIRK_DETAILED_IN_CM),
165
166 /* LG 27GP950 */
167 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP),
168
169 /* LG 27GN950 */
170 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP),
171
172 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
173 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
174
175 /* LG Philips LCD LP154W01-A5 */
176 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
177 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
178
179 /* Samsung SyncMaster 205BW. Note: irony */
180 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
181 /* Samsung SyncMaster 22[5-6]BW */
182 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
183 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
184
185 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
186 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
187
188 /* ViewSonic VA2026w */
189 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
190
191 /* Medion MD 30217 PG */
192 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
193
194 /* Lenovo G50 */
195 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
196
197 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
198 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
199
200 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
201 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
202
203 /* Valve Index Headset */
204 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
205 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
208 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
209 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
210 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
211 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
212 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
213 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
214 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
216 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
217 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
218 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
219 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
220 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
221
222 /* HTC Vive and Vive Pro VR Headsets */
223 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
224 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
225
226 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
227 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
228 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
229 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
230 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
231
232 /* Windows Mixed Reality Headsets */
233 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
234 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
235 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
236 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
237 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
238 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
239
240 /* Sony PlayStation VR Headset */
241 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
242
243 /* Sensics VR Headsets */
244 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
245
246 /* OSVR HDK and HDK2 VR Headsets */
247 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
248 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP),
249 };
250
251 /*
252 * Autogenerated from the DMT spec.
253 * This table is copied from xfree86/modes/xf86EdidModes.c.
254 */
255 static const struct drm_display_mode drm_dmt_modes[] = {
256 /* 0x01 - 640x350@85Hz */
257 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
258 736, 832, 0, 350, 382, 385, 445, 0,
259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
260 /* 0x02 - 640x400@85Hz */
261 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
262 736, 832, 0, 400, 401, 404, 445, 0,
263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
264 /* 0x03 - 720x400@85Hz */
265 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
266 828, 936, 0, 400, 401, 404, 446, 0,
267 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
268 /* 0x04 - 640x480@60Hz */
269 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
270 752, 800, 0, 480, 490, 492, 525, 0,
271 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
272 /* 0x05 - 640x480@72Hz */
273 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
274 704, 832, 0, 480, 489, 492, 520, 0,
275 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
276 /* 0x06 - 640x480@75Hz */
277 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
278 720, 840, 0, 480, 481, 484, 500, 0,
279 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
280 /* 0x07 - 640x480@85Hz */
281 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
282 752, 832, 0, 480, 481, 484, 509, 0,
283 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
284 /* 0x08 - 800x600@56Hz */
285 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
286 896, 1024, 0, 600, 601, 603, 625, 0,
287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
288 /* 0x09 - 800x600@60Hz */
289 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
290 968, 1056, 0, 600, 601, 605, 628, 0,
291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
292 /* 0x0a - 800x600@72Hz */
293 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
294 976, 1040, 0, 600, 637, 643, 666, 0,
295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
296 /* 0x0b - 800x600@75Hz */
297 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
298 896, 1056, 0, 600, 601, 604, 625, 0,
299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
300 /* 0x0c - 800x600@85Hz */
301 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
302 896, 1048, 0, 600, 601, 604, 631, 0,
303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
304 /* 0x0d - 800x600@120Hz RB */
305 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
306 880, 960, 0, 600, 603, 607, 636, 0,
307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
308 /* 0x0e - 848x480@60Hz */
309 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
310 976, 1088, 0, 480, 486, 494, 517, 0,
311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
312 /* 0x0f - 1024x768@43Hz, interlace */
313 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
314 1208, 1264, 0, 768, 768, 776, 817, 0,
315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
316 DRM_MODE_FLAG_INTERLACE) },
317 /* 0x10 - 1024x768@60Hz */
318 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
319 1184, 1344, 0, 768, 771, 777, 806, 0,
320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
321 /* 0x11 - 1024x768@70Hz */
322 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
323 1184, 1328, 0, 768, 771, 777, 806, 0,
324 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
325 /* 0x12 - 1024x768@75Hz */
326 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
327 1136, 1312, 0, 768, 769, 772, 800, 0,
328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
329 /* 0x13 - 1024x768@85Hz */
330 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
331 1168, 1376, 0, 768, 769, 772, 808, 0,
332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
333 /* 0x14 - 1024x768@120Hz RB */
334 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
335 1104, 1184, 0, 768, 771, 775, 813, 0,
336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
337 /* 0x15 - 1152x864@75Hz */
338 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
339 1344, 1600, 0, 864, 865, 868, 900, 0,
340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
341 /* 0x55 - 1280x720@60Hz */
342 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
343 1430, 1650, 0, 720, 725, 730, 750, 0,
344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
345 /* 0x16 - 1280x768@60Hz RB */
346 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
347 1360, 1440, 0, 768, 771, 778, 790, 0,
348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
349 /* 0x17 - 1280x768@60Hz */
350 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
351 1472, 1664, 0, 768, 771, 778, 798, 0,
352 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
353 /* 0x18 - 1280x768@75Hz */
354 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
355 1488, 1696, 0, 768, 771, 778, 805, 0,
356 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
357 /* 0x19 - 1280x768@85Hz */
358 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
359 1496, 1712, 0, 768, 771, 778, 809, 0,
360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
361 /* 0x1a - 1280x768@120Hz RB */
362 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
363 1360, 1440, 0, 768, 771, 778, 813, 0,
364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
365 /* 0x1b - 1280x800@60Hz RB */
366 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
367 1360, 1440, 0, 800, 803, 809, 823, 0,
368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
369 /* 0x1c - 1280x800@60Hz */
370 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
371 1480, 1680, 0, 800, 803, 809, 831, 0,
372 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
373 /* 0x1d - 1280x800@75Hz */
374 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
375 1488, 1696, 0, 800, 803, 809, 838, 0,
376 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
377 /* 0x1e - 1280x800@85Hz */
378 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
379 1496, 1712, 0, 800, 803, 809, 843, 0,
380 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
381 /* 0x1f - 1280x800@120Hz RB */
382 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
383 1360, 1440, 0, 800, 803, 809, 847, 0,
384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
385 /* 0x20 - 1280x960@60Hz */
386 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
387 1488, 1800, 0, 960, 961, 964, 1000, 0,
388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
389 /* 0x21 - 1280x960@85Hz */
390 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
391 1504, 1728, 0, 960, 961, 964, 1011, 0,
392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
393 /* 0x22 - 1280x960@120Hz RB */
394 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
395 1360, 1440, 0, 960, 963, 967, 1017, 0,
396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
397 /* 0x23 - 1280x1024@60Hz */
398 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
399 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
401 /* 0x24 - 1280x1024@75Hz */
402 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
403 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
405 /* 0x25 - 1280x1024@85Hz */
406 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
407 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
409 /* 0x26 - 1280x1024@120Hz RB */
410 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
411 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
413 /* 0x27 - 1360x768@60Hz */
414 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
415 1536, 1792, 0, 768, 771, 777, 795, 0,
416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
417 /* 0x28 - 1360x768@120Hz RB */
418 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
419 1440, 1520, 0, 768, 771, 776, 813, 0,
420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
421 /* 0x51 - 1366x768@60Hz */
422 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
423 1579, 1792, 0, 768, 771, 774, 798, 0,
424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
425 /* 0x56 - 1366x768@60Hz */
426 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
427 1436, 1500, 0, 768, 769, 772, 800, 0,
428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
429 /* 0x29 - 1400x1050@60Hz RB */
430 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
431 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
433 /* 0x2a - 1400x1050@60Hz */
434 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
435 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
436 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
437 /* 0x2b - 1400x1050@75Hz */
438 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
439 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
441 /* 0x2c - 1400x1050@85Hz */
442 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
443 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
444 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
445 /* 0x2d - 1400x1050@120Hz RB */
446 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
447 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
449 /* 0x2e - 1440x900@60Hz RB */
450 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
451 1520, 1600, 0, 900, 903, 909, 926, 0,
452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
453 /* 0x2f - 1440x900@60Hz */
454 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
455 1672, 1904, 0, 900, 903, 909, 934, 0,
456 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
457 /* 0x30 - 1440x900@75Hz */
458 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
459 1688, 1936, 0, 900, 903, 909, 942, 0,
460 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
461 /* 0x31 - 1440x900@85Hz */
462 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
463 1696, 1952, 0, 900, 903, 909, 948, 0,
464 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
465 /* 0x32 - 1440x900@120Hz RB */
466 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
467 1520, 1600, 0, 900, 903, 909, 953, 0,
468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
469 /* 0x53 - 1600x900@60Hz */
470 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
471 1704, 1800, 0, 900, 901, 904, 1000, 0,
472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
473 /* 0x33 - 1600x1200@60Hz */
474 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
475 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
477 /* 0x34 - 1600x1200@65Hz */
478 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
479 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
481 /* 0x35 - 1600x1200@70Hz */
482 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
483 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
485 /* 0x36 - 1600x1200@75Hz */
486 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
487 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
489 /* 0x37 - 1600x1200@85Hz */
490 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
491 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
493 /* 0x38 - 1600x1200@120Hz RB */
494 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
495 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
497 /* 0x39 - 1680x1050@60Hz RB */
498 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
499 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
501 /* 0x3a - 1680x1050@60Hz */
502 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
503 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
505 /* 0x3b - 1680x1050@75Hz */
506 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
507 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
509 /* 0x3c - 1680x1050@85Hz */
510 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
511 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
513 /* 0x3d - 1680x1050@120Hz RB */
514 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
515 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
517 /* 0x3e - 1792x1344@60Hz */
518 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
519 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
521 /* 0x3f - 1792x1344@75Hz */
522 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
523 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
525 /* 0x40 - 1792x1344@120Hz RB */
526 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
527 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
529 /* 0x41 - 1856x1392@60Hz */
530 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
531 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
532 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
533 /* 0x42 - 1856x1392@75Hz */
534 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
535 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
537 /* 0x43 - 1856x1392@120Hz RB */
538 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
539 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
541 /* 0x52 - 1920x1080@60Hz */
542 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
543 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
544 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
545 /* 0x44 - 1920x1200@60Hz RB */
546 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
547 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
549 /* 0x45 - 1920x1200@60Hz */
550 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
551 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
552 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
553 /* 0x46 - 1920x1200@75Hz */
554 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
555 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
557 /* 0x47 - 1920x1200@85Hz */
558 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
559 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
561 /* 0x48 - 1920x1200@120Hz RB */
562 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
563 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
565 /* 0x49 - 1920x1440@60Hz */
566 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
567 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
568 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
569 /* 0x4a - 1920x1440@75Hz */
570 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
571 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
572 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
573 /* 0x4b - 1920x1440@120Hz RB */
574 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
575 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
577 /* 0x54 - 2048x1152@60Hz */
578 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
579 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
580 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
581 /* 0x4c - 2560x1600@60Hz RB */
582 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
583 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
585 /* 0x4d - 2560x1600@60Hz */
586 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
587 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
588 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
589 /* 0x4e - 2560x1600@75Hz */
590 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
591 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
592 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
593 /* 0x4f - 2560x1600@85Hz */
594 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
595 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
596 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
597 /* 0x50 - 2560x1600@120Hz RB */
598 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
599 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
601 /* 0x57 - 4096x2160@60Hz RB */
602 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
603 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
604 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
605 /* 0x58 - 4096x2160@59.94Hz RB */
606 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
607 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
609 };
610
611 /*
612 * These more or less come from the DMT spec. The 720x400 modes are
613 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
614 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
615 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
616 * mode.
617 *
618 * The DMT modes have been fact-checked; the rest are mild guesses.
619 */
620 static const struct drm_display_mode edid_est_modes[] = {
621 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
622 968, 1056, 0, 600, 601, 605, 628, 0,
623 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
624 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
625 896, 1024, 0, 600, 601, 603, 625, 0,
626 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
627 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
628 720, 840, 0, 480, 481, 484, 500, 0,
629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
630 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
631 704, 832, 0, 480, 489, 492, 520, 0,
632 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
633 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
634 768, 864, 0, 480, 483, 486, 525, 0,
635 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
636 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
637 752, 800, 0, 480, 490, 492, 525, 0,
638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
639 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
640 846, 900, 0, 400, 421, 423, 449, 0,
641 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
642 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
643 846, 900, 0, 400, 412, 414, 449, 0,
644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
645 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
646 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
648 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
649 1136, 1312, 0, 768, 769, 772, 800, 0,
650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
651 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
652 1184, 1328, 0, 768, 771, 777, 806, 0,
653 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
654 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
655 1184, 1344, 0, 768, 771, 777, 806, 0,
656 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
657 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
658 1208, 1264, 0, 768, 768, 776, 817, 0,
659 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
660 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
661 928, 1152, 0, 624, 625, 628, 667, 0,
662 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
663 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
664 896, 1056, 0, 600, 601, 604, 625, 0,
665 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
666 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
667 976, 1040, 0, 600, 637, 643, 666, 0,
668 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
669 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
670 1344, 1600, 0, 864, 865, 868, 900, 0,
671 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
672 };
673
674 struct minimode {
675 short w;
676 short h;
677 short r;
678 short rb;
679 };
680
681 static const struct minimode est3_modes[] = {
682 /* byte 6 */
683 { 640, 350, 85, 0 },
684 { 640, 400, 85, 0 },
685 { 720, 400, 85, 0 },
686 { 640, 480, 85, 0 },
687 { 848, 480, 60, 0 },
688 { 800, 600, 85, 0 },
689 { 1024, 768, 85, 0 },
690 { 1152, 864, 75, 0 },
691 /* byte 7 */
692 { 1280, 768, 60, 1 },
693 { 1280, 768, 60, 0 },
694 { 1280, 768, 75, 0 },
695 { 1280, 768, 85, 0 },
696 { 1280, 960, 60, 0 },
697 { 1280, 960, 85, 0 },
698 { 1280, 1024, 60, 0 },
699 { 1280, 1024, 85, 0 },
700 /* byte 8 */
701 { 1360, 768, 60, 0 },
702 { 1440, 900, 60, 1 },
703 { 1440, 900, 60, 0 },
704 { 1440, 900, 75, 0 },
705 { 1440, 900, 85, 0 },
706 { 1400, 1050, 60, 1 },
707 { 1400, 1050, 60, 0 },
708 { 1400, 1050, 75, 0 },
709 /* byte 9 */
710 { 1400, 1050, 85, 0 },
711 { 1680, 1050, 60, 1 },
712 { 1680, 1050, 60, 0 },
713 { 1680, 1050, 75, 0 },
714 { 1680, 1050, 85, 0 },
715 { 1600, 1200, 60, 0 },
716 { 1600, 1200, 65, 0 },
717 { 1600, 1200, 70, 0 },
718 /* byte 10 */
719 { 1600, 1200, 75, 0 },
720 { 1600, 1200, 85, 0 },
721 { 1792, 1344, 60, 0 },
722 { 1792, 1344, 75, 0 },
723 { 1856, 1392, 60, 0 },
724 { 1856, 1392, 75, 0 },
725 { 1920, 1200, 60, 1 },
726 { 1920, 1200, 60, 0 },
727 /* byte 11 */
728 { 1920, 1200, 75, 0 },
729 { 1920, 1200, 85, 0 },
730 { 1920, 1440, 60, 0 },
731 { 1920, 1440, 75, 0 },
732 };
733
734 static const struct minimode extra_modes[] = {
735 { 1024, 576, 60, 0 },
736 { 1366, 768, 60, 0 },
737 { 1600, 900, 60, 0 },
738 { 1680, 945, 60, 0 },
739 { 1920, 1080, 60, 0 },
740 { 2048, 1152, 60, 0 },
741 { 2048, 1536, 60, 0 },
742 };
743
744 /*
745 * From CEA/CTA-861 spec.
746 *
747 * Do not access directly, instead always use cea_mode_for_vic().
748 */
749 static const struct drm_display_mode edid_cea_modes_1[] = {
750 /* 1 - 640x480@60Hz 4:3 */
751 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
752 752, 800, 0, 480, 490, 492, 525, 0,
753 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
754 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
755 /* 2 - 720x480@60Hz 4:3 */
756 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
757 798, 858, 0, 480, 489, 495, 525, 0,
758 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
759 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
760 /* 3 - 720x480@60Hz 16:9 */
761 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
762 798, 858, 0, 480, 489, 495, 525, 0,
763 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
764 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
765 /* 4 - 1280x720@60Hz 16:9 */
766 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
767 1430, 1650, 0, 720, 725, 730, 750, 0,
768 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
769 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
770 /* 5 - 1920x1080i@60Hz 16:9 */
771 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
772 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
773 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
774 DRM_MODE_FLAG_INTERLACE),
775 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
776 /* 6 - 720(1440)x480i@60Hz 4:3 */
777 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
778 801, 858, 0, 480, 488, 494, 525, 0,
779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
780 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
781 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
782 /* 7 - 720(1440)x480i@60Hz 16:9 */
783 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
784 801, 858, 0, 480, 488, 494, 525, 0,
785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
786 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
787 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
788 /* 8 - 720(1440)x240@60Hz 4:3 */
789 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
790 801, 858, 0, 240, 244, 247, 262, 0,
791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
792 DRM_MODE_FLAG_DBLCLK),
793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
794 /* 9 - 720(1440)x240@60Hz 16:9 */
795 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
796 801, 858, 0, 240, 244, 247, 262, 0,
797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
798 DRM_MODE_FLAG_DBLCLK),
799 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
800 /* 10 - 2880x480i@60Hz 4:3 */
801 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
802 3204, 3432, 0, 480, 488, 494, 525, 0,
803 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
804 DRM_MODE_FLAG_INTERLACE),
805 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
806 /* 11 - 2880x480i@60Hz 16:9 */
807 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
808 3204, 3432, 0, 480, 488, 494, 525, 0,
809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
810 DRM_MODE_FLAG_INTERLACE),
811 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
812 /* 12 - 2880x240@60Hz 4:3 */
813 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
814 3204, 3432, 0, 240, 244, 247, 262, 0,
815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
816 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
817 /* 13 - 2880x240@60Hz 16:9 */
818 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
819 3204, 3432, 0, 240, 244, 247, 262, 0,
820 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
821 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
822 /* 14 - 1440x480@60Hz 4:3 */
823 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
824 1596, 1716, 0, 480, 489, 495, 525, 0,
825 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
827 /* 15 - 1440x480@60Hz 16:9 */
828 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
829 1596, 1716, 0, 480, 489, 495, 525, 0,
830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
831 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
832 /* 16 - 1920x1080@60Hz 16:9 */
833 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
834 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
835 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
836 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
837 /* 17 - 720x576@50Hz 4:3 */
838 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
839 796, 864, 0, 576, 581, 586, 625, 0,
840 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
841 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
842 /* 18 - 720x576@50Hz 16:9 */
843 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
844 796, 864, 0, 576, 581, 586, 625, 0,
845 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
846 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
847 /* 19 - 1280x720@50Hz 16:9 */
848 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
849 1760, 1980, 0, 720, 725, 730, 750, 0,
850 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
851 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
852 /* 20 - 1920x1080i@50Hz 16:9 */
853 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
854 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
855 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
856 DRM_MODE_FLAG_INTERLACE),
857 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
858 /* 21 - 720(1440)x576i@50Hz 4:3 */
859 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
860 795, 864, 0, 576, 580, 586, 625, 0,
861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
862 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
863 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
864 /* 22 - 720(1440)x576i@50Hz 16:9 */
865 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
866 795, 864, 0, 576, 580, 586, 625, 0,
867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
868 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
869 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
870 /* 23 - 720(1440)x288@50Hz 4:3 */
871 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
872 795, 864, 0, 288, 290, 293, 312, 0,
873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
874 DRM_MODE_FLAG_DBLCLK),
875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
876 /* 24 - 720(1440)x288@50Hz 16:9 */
877 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
878 795, 864, 0, 288, 290, 293, 312, 0,
879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
880 DRM_MODE_FLAG_DBLCLK),
881 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
882 /* 25 - 2880x576i@50Hz 4:3 */
883 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
884 3180, 3456, 0, 576, 580, 586, 625, 0,
885 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
886 DRM_MODE_FLAG_INTERLACE),
887 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
888 /* 26 - 2880x576i@50Hz 16:9 */
889 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
890 3180, 3456, 0, 576, 580, 586, 625, 0,
891 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
892 DRM_MODE_FLAG_INTERLACE),
893 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
894 /* 27 - 2880x288@50Hz 4:3 */
895 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
896 3180, 3456, 0, 288, 290, 293, 312, 0,
897 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
898 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
899 /* 28 - 2880x288@50Hz 16:9 */
900 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
901 3180, 3456, 0, 288, 290, 293, 312, 0,
902 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
903 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
904 /* 29 - 1440x576@50Hz 4:3 */
905 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
906 1592, 1728, 0, 576, 581, 586, 625, 0,
907 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
908 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
909 /* 30 - 1440x576@50Hz 16:9 */
910 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
911 1592, 1728, 0, 576, 581, 586, 625, 0,
912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
913 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
914 /* 31 - 1920x1080@50Hz 16:9 */
915 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
916 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
917 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
918 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
919 /* 32 - 1920x1080@24Hz 16:9 */
920 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
921 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
922 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
923 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
924 /* 33 - 1920x1080@25Hz 16:9 */
925 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
926 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
927 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
929 /* 34 - 1920x1080@30Hz 16:9 */
930 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
931 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
933 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
934 /* 35 - 2880x480@60Hz 4:3 */
935 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
936 3192, 3432, 0, 480, 489, 495, 525, 0,
937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
938 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
939 /* 36 - 2880x480@60Hz 16:9 */
940 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
941 3192, 3432, 0, 480, 489, 495, 525, 0,
942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
943 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
944 /* 37 - 2880x576@50Hz 4:3 */
945 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
946 3184, 3456, 0, 576, 581, 586, 625, 0,
947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
948 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
949 /* 38 - 2880x576@50Hz 16:9 */
950 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
951 3184, 3456, 0, 576, 581, 586, 625, 0,
952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
953 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
954 /* 39 - 1920x1080i@50Hz 16:9 */
955 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
956 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
957 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
958 DRM_MODE_FLAG_INTERLACE),
959 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
960 /* 40 - 1920x1080i@100Hz 16:9 */
961 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
962 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
963 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
964 DRM_MODE_FLAG_INTERLACE),
965 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
966 /* 41 - 1280x720@100Hz 16:9 */
967 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
968 1760, 1980, 0, 720, 725, 730, 750, 0,
969 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
970 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
971 /* 42 - 720x576@100Hz 4:3 */
972 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
973 796, 864, 0, 576, 581, 586, 625, 0,
974 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
975 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
976 /* 43 - 720x576@100Hz 16:9 */
977 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
978 796, 864, 0, 576, 581, 586, 625, 0,
979 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
981 /* 44 - 720(1440)x576i@100Hz 4:3 */
982 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
983 795, 864, 0, 576, 580, 586, 625, 0,
984 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
985 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
986 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
987 /* 45 - 720(1440)x576i@100Hz 16:9 */
988 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
989 795, 864, 0, 576, 580, 586, 625, 0,
990 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
991 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
992 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
993 /* 46 - 1920x1080i@120Hz 16:9 */
994 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
995 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
996 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
997 DRM_MODE_FLAG_INTERLACE),
998 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
999 /* 47 - 1280x720@120Hz 16:9 */
1000 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1001 1430, 1650, 0, 720, 725, 730, 750, 0,
1002 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1003 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1004 /* 48 - 720x480@120Hz 4:3 */
1005 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
1006 798, 858, 0, 480, 489, 495, 525, 0,
1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1008 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1009 /* 49 - 720x480@120Hz 16:9 */
1010 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
1011 798, 858, 0, 480, 489, 495, 525, 0,
1012 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1013 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1014 /* 50 - 720(1440)x480i@120Hz 4:3 */
1015 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1016 801, 858, 0, 480, 488, 494, 525, 0,
1017 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1018 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1019 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1020 /* 51 - 720(1440)x480i@120Hz 16:9 */
1021 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1022 801, 858, 0, 480, 488, 494, 525, 0,
1023 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1024 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1025 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1026 /* 52 - 720x576@200Hz 4:3 */
1027 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1028 796, 864, 0, 576, 581, 586, 625, 0,
1029 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1030 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1031 /* 53 - 720x576@200Hz 16:9 */
1032 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1033 796, 864, 0, 576, 581, 586, 625, 0,
1034 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1035 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1036 /* 54 - 720(1440)x576i@200Hz 4:3 */
1037 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1038 795, 864, 0, 576, 580, 586, 625, 0,
1039 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1040 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1041 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1042 /* 55 - 720(1440)x576i@200Hz 16:9 */
1043 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1044 795, 864, 0, 576, 580, 586, 625, 0,
1045 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1046 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1047 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1048 /* 56 - 720x480@240Hz 4:3 */
1049 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1050 798, 858, 0, 480, 489, 495, 525, 0,
1051 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1052 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1053 /* 57 - 720x480@240Hz 16:9 */
1054 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1055 798, 858, 0, 480, 489, 495, 525, 0,
1056 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1057 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1058 /* 58 - 720(1440)x480i@240Hz 4:3 */
1059 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1060 801, 858, 0, 480, 488, 494, 525, 0,
1061 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1062 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1063 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1064 /* 59 - 720(1440)x480i@240Hz 16:9 */
1065 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1066 801, 858, 0, 480, 488, 494, 525, 0,
1067 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1068 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1069 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1070 /* 60 - 1280x720@24Hz 16:9 */
1071 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1072 3080, 3300, 0, 720, 725, 730, 750, 0,
1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1074 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1075 /* 61 - 1280x720@25Hz 16:9 */
1076 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1077 3740, 3960, 0, 720, 725, 730, 750, 0,
1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1079 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1080 /* 62 - 1280x720@30Hz 16:9 */
1081 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1082 3080, 3300, 0, 720, 725, 730, 750, 0,
1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1084 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1085 /* 63 - 1920x1080@120Hz 16:9 */
1086 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1087 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1089 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1090 /* 64 - 1920x1080@100Hz 16:9 */
1091 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1092 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1094 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1095 /* 65 - 1280x720@24Hz 64:27 */
1096 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1097 3080, 3300, 0, 720, 725, 730, 750, 0,
1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1099 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1100 /* 66 - 1280x720@25Hz 64:27 */
1101 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1102 3740, 3960, 0, 720, 725, 730, 750, 0,
1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1104 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1105 /* 67 - 1280x720@30Hz 64:27 */
1106 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1107 3080, 3300, 0, 720, 725, 730, 750, 0,
1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1109 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1110 /* 68 - 1280x720@50Hz 64:27 */
1111 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1112 1760, 1980, 0, 720, 725, 730, 750, 0,
1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1114 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1115 /* 69 - 1280x720@60Hz 64:27 */
1116 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1117 1430, 1650, 0, 720, 725, 730, 750, 0,
1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1119 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1120 /* 70 - 1280x720@100Hz 64:27 */
1121 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1122 1760, 1980, 0, 720, 725, 730, 750, 0,
1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1124 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1125 /* 71 - 1280x720@120Hz 64:27 */
1126 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1127 1430, 1650, 0, 720, 725, 730, 750, 0,
1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1129 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1130 /* 72 - 1920x1080@24Hz 64:27 */
1131 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1132 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1134 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1135 /* 73 - 1920x1080@25Hz 64:27 */
1136 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1137 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1139 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1140 /* 74 - 1920x1080@30Hz 64:27 */
1141 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1142 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1144 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1145 /* 75 - 1920x1080@50Hz 64:27 */
1146 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1147 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1149 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1150 /* 76 - 1920x1080@60Hz 64:27 */
1151 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1152 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1154 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1155 /* 77 - 1920x1080@100Hz 64:27 */
1156 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1157 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1159 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1160 /* 78 - 1920x1080@120Hz 64:27 */
1161 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1162 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1164 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1165 /* 79 - 1680x720@24Hz 64:27 */
1166 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1167 3080, 3300, 0, 720, 725, 730, 750, 0,
1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1169 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1170 /* 80 - 1680x720@25Hz 64:27 */
1171 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1172 2948, 3168, 0, 720, 725, 730, 750, 0,
1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1174 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1175 /* 81 - 1680x720@30Hz 64:27 */
1176 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1177 2420, 2640, 0, 720, 725, 730, 750, 0,
1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1179 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1180 /* 82 - 1680x720@50Hz 64:27 */
1181 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1182 1980, 2200, 0, 720, 725, 730, 750, 0,
1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1184 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1185 /* 83 - 1680x720@60Hz 64:27 */
1186 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1187 1980, 2200, 0, 720, 725, 730, 750, 0,
1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1189 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1190 /* 84 - 1680x720@100Hz 64:27 */
1191 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1192 1780, 2000, 0, 720, 725, 730, 825, 0,
1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1194 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1195 /* 85 - 1680x720@120Hz 64:27 */
1196 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1197 1780, 2000, 0, 720, 725, 730, 825, 0,
1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1199 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1200 /* 86 - 2560x1080@24Hz 64:27 */
1201 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1202 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1204 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1205 /* 87 - 2560x1080@25Hz 64:27 */
1206 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1207 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1209 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1210 /* 88 - 2560x1080@30Hz 64:27 */
1211 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1212 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1214 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1215 /* 89 - 2560x1080@50Hz 64:27 */
1216 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1217 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1219 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1220 /* 90 - 2560x1080@60Hz 64:27 */
1221 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1222 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1224 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1225 /* 91 - 2560x1080@100Hz 64:27 */
1226 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1227 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1229 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1230 /* 92 - 2560x1080@120Hz 64:27 */
1231 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1232 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1234 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1235 /* 93 - 3840x2160@24Hz 16:9 */
1236 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1237 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1239 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1240 /* 94 - 3840x2160@25Hz 16:9 */
1241 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1242 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1244 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1245 /* 95 - 3840x2160@30Hz 16:9 */
1246 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1247 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1249 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1250 /* 96 - 3840x2160@50Hz 16:9 */
1251 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1252 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1254 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1255 /* 97 - 3840x2160@60Hz 16:9 */
1256 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1257 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1259 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1260 /* 98 - 4096x2160@24Hz 256:135 */
1261 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1262 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1264 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1265 /* 99 - 4096x2160@25Hz 256:135 */
1266 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1267 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1269 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1270 /* 100 - 4096x2160@30Hz 256:135 */
1271 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1272 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1274 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1275 /* 101 - 4096x2160@50Hz 256:135 */
1276 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1277 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1279 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1280 /* 102 - 4096x2160@60Hz 256:135 */
1281 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1282 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1284 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1285 /* 103 - 3840x2160@24Hz 64:27 */
1286 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1287 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1289 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1290 /* 104 - 3840x2160@25Hz 64:27 */
1291 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1292 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1294 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1295 /* 105 - 3840x2160@30Hz 64:27 */
1296 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1297 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1299 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1300 /* 106 - 3840x2160@50Hz 64:27 */
1301 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1302 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1304 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1305 /* 107 - 3840x2160@60Hz 64:27 */
1306 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1307 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1309 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1310 /* 108 - 1280x720@48Hz 16:9 */
1311 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1312 2280, 2500, 0, 720, 725, 730, 750, 0,
1313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1314 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1315 /* 109 - 1280x720@48Hz 64:27 */
1316 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1317 2280, 2500, 0, 720, 725, 730, 750, 0,
1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1319 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1320 /* 110 - 1680x720@48Hz 64:27 */
1321 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1322 2530, 2750, 0, 720, 725, 730, 750, 0,
1323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1324 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1325 /* 111 - 1920x1080@48Hz 16:9 */
1326 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1327 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1329 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1330 /* 112 - 1920x1080@48Hz 64:27 */
1331 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1332 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1334 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1335 /* 113 - 2560x1080@48Hz 64:27 */
1336 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1337 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1339 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1340 /* 114 - 3840x2160@48Hz 16:9 */
1341 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1342 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1344 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1345 /* 115 - 4096x2160@48Hz 256:135 */
1346 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1347 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1349 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1350 /* 116 - 3840x2160@48Hz 64:27 */
1351 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1352 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1354 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1355 /* 117 - 3840x2160@100Hz 16:9 */
1356 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1357 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1359 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1360 /* 118 - 3840x2160@120Hz 16:9 */
1361 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1362 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1364 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1365 /* 119 - 3840x2160@100Hz 64:27 */
1366 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1367 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1369 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1370 /* 120 - 3840x2160@120Hz 64:27 */
1371 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1372 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1374 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1375 /* 121 - 5120x2160@24Hz 64:27 */
1376 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1377 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1379 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1380 /* 122 - 5120x2160@25Hz 64:27 */
1381 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1382 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1384 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1385 /* 123 - 5120x2160@30Hz 64:27 */
1386 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1387 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1389 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1390 /* 124 - 5120x2160@48Hz 64:27 */
1391 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1392 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1394 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1395 /* 125 - 5120x2160@50Hz 64:27 */
1396 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1397 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1399 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1400 /* 126 - 5120x2160@60Hz 64:27 */
1401 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1402 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1404 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1405 /* 127 - 5120x2160@100Hz 64:27 */
1406 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1407 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1410 };
1411
1412 /*
1413 * From CEA/CTA-861 spec.
1414 *
1415 * Do not access directly, instead always use cea_mode_for_vic().
1416 */
1417 static const struct drm_display_mode edid_cea_modes_193[] = {
1418 /* 193 - 5120x2160@120Hz 64:27 */
1419 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1420 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1422 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1423 /* 194 - 7680x4320@24Hz 16:9 */
1424 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1425 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1427 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1428 /* 195 - 7680x4320@25Hz 16:9 */
1429 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1430 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1432 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1433 /* 196 - 7680x4320@30Hz 16:9 */
1434 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1435 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1437 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1438 /* 197 - 7680x4320@48Hz 16:9 */
1439 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1440 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1442 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1443 /* 198 - 7680x4320@50Hz 16:9 */
1444 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1445 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1447 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1448 /* 199 - 7680x4320@60Hz 16:9 */
1449 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1450 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1452 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1453 /* 200 - 7680x4320@100Hz 16:9 */
1454 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1455 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1457 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1458 /* 201 - 7680x4320@120Hz 16:9 */
1459 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1460 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1462 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1463 /* 202 - 7680x4320@24Hz 64:27 */
1464 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1465 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1467 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1468 /* 203 - 7680x4320@25Hz 64:27 */
1469 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1470 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1472 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1473 /* 204 - 7680x4320@30Hz 64:27 */
1474 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1475 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1477 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1478 /* 205 - 7680x4320@48Hz 64:27 */
1479 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1480 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1482 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1483 /* 206 - 7680x4320@50Hz 64:27 */
1484 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1485 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1487 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1488 /* 207 - 7680x4320@60Hz 64:27 */
1489 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1490 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1492 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1493 /* 208 - 7680x4320@100Hz 64:27 */
1494 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1495 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1497 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1498 /* 209 - 7680x4320@120Hz 64:27 */
1499 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1500 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1502 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1503 /* 210 - 10240x4320@24Hz 64:27 */
1504 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1505 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1507 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1508 /* 211 - 10240x4320@25Hz 64:27 */
1509 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1510 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1512 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1513 /* 212 - 10240x4320@30Hz 64:27 */
1514 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1515 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1517 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1518 /* 213 - 10240x4320@48Hz 64:27 */
1519 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1520 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1522 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1523 /* 214 - 10240x4320@50Hz 64:27 */
1524 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1525 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1527 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1528 /* 215 - 10240x4320@60Hz 64:27 */
1529 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1530 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1532 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1533 /* 216 - 10240x4320@100Hz 64:27 */
1534 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1535 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1537 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1538 /* 217 - 10240x4320@120Hz 64:27 */
1539 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1540 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1542 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1543 /* 218 - 4096x2160@100Hz 256:135 */
1544 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1545 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1547 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1548 /* 219 - 4096x2160@120Hz 256:135 */
1549 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1550 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1552 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1553 };
1554
1555 /*
1556 * HDMI 1.4 4k modes. Index using the VIC.
1557 */
1558 static const struct drm_display_mode edid_4k_modes[] = {
1559 /* 0 - dummy, VICs start at 1 */
1560 { },
1561 /* 1 - 3840x2160@30Hz */
1562 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1563 3840, 4016, 4104, 4400, 0,
1564 2160, 2168, 2178, 2250, 0,
1565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1566 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1567 /* 2 - 3840x2160@25Hz */
1568 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1569 3840, 4896, 4984, 5280, 0,
1570 2160, 2168, 2178, 2250, 0,
1571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1572 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1573 /* 3 - 3840x2160@24Hz */
1574 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1575 3840, 5116, 5204, 5500, 0,
1576 2160, 2168, 2178, 2250, 0,
1577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1578 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1579 /* 4 - 4096x2160@24Hz (SMPTE) */
1580 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1581 4096, 5116, 5204, 5500, 0,
1582 2160, 2168, 2178, 2250, 0,
1583 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1584 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1585 };
1586
1587 /*** DDC fetch and block validation ***/
1588
1589 /*
1590 * The opaque EDID type, internal to drm_edid.c.
1591 */
1592 struct drm_edid {
1593 /* Size allocated for edid */
1594 size_t size;
1595 const struct edid *edid;
1596 };
1597
1598 static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1599
edid_hfeeodb_block_count(const struct edid * edid)1600 static int edid_hfeeodb_block_count(const struct edid *edid)
1601 {
1602 int eeodb = edid_hfeeodb_extension_block_count(edid);
1603
1604 return eeodb ? eeodb + 1 : 0;
1605 }
1606
edid_extension_block_count(const struct edid * edid)1607 static int edid_extension_block_count(const struct edid *edid)
1608 {
1609 return edid->extensions;
1610 }
1611
edid_block_count(const struct edid * edid)1612 static int edid_block_count(const struct edid *edid)
1613 {
1614 return edid_extension_block_count(edid) + 1;
1615 }
1616
edid_size_by_blocks(int num_blocks)1617 static int edid_size_by_blocks(int num_blocks)
1618 {
1619 return num_blocks * EDID_LENGTH;
1620 }
1621
edid_size(const struct edid * edid)1622 static int edid_size(const struct edid *edid)
1623 {
1624 return edid_size_by_blocks(edid_block_count(edid));
1625 }
1626
edid_block_data(const struct edid * edid,int index)1627 static const void *edid_block_data(const struct edid *edid, int index)
1628 {
1629 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1630
1631 return edid + index;
1632 }
1633
edid_extension_block_data(const struct edid * edid,int index)1634 static const void *edid_extension_block_data(const struct edid *edid, int index)
1635 {
1636 return edid_block_data(edid, index + 1);
1637 }
1638
1639 /* EDID block count indicated in EDID, may exceed allocated size */
__drm_edid_block_count(const struct drm_edid * drm_edid)1640 static int __drm_edid_block_count(const struct drm_edid *drm_edid)
1641 {
1642 int num_blocks;
1643
1644 /* Starting point */
1645 num_blocks = edid_block_count(drm_edid->edid);
1646
1647 /* HF-EEODB override */
1648 if (drm_edid->size >= edid_size_by_blocks(2)) {
1649 int eeodb;
1650
1651 /*
1652 * Note: HF-EEODB may specify a smaller extension count than the
1653 * regular one. Unlike in buffer allocation, here we can use it.
1654 */
1655 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1656 if (eeodb)
1657 num_blocks = eeodb;
1658 }
1659
1660 return num_blocks;
1661 }
1662
1663 /* EDID block count, limited by allocated size */
drm_edid_block_count(const struct drm_edid * drm_edid)1664 static int drm_edid_block_count(const struct drm_edid *drm_edid)
1665 {
1666 /* Limit by allocated size */
1667 return min(__drm_edid_block_count(drm_edid),
1668 (int)drm_edid->size / EDID_LENGTH);
1669 }
1670
1671 /* EDID extension block count, limited by allocated size */
drm_edid_extension_block_count(const struct drm_edid * drm_edid)1672 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1673 {
1674 return drm_edid_block_count(drm_edid) - 1;
1675 }
1676
drm_edid_block_data(const struct drm_edid * drm_edid,int index)1677 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1678 {
1679 return edid_block_data(drm_edid->edid, index);
1680 }
1681
drm_edid_extension_block_data(const struct drm_edid * drm_edid,int index)1682 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1683 int index)
1684 {
1685 return edid_extension_block_data(drm_edid->edid, index);
1686 }
1687
1688 /*
1689 * Initializer helper for legacy interfaces, where we have no choice but to
1690 * trust edid size. Not for general purpose use.
1691 */
drm_edid_legacy_init(struct drm_edid * drm_edid,const struct edid * edid)1692 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1693 const struct edid *edid)
1694 {
1695 if (!edid)
1696 return NULL;
1697
1698 memset(drm_edid, 0, sizeof(*drm_edid));
1699
1700 drm_edid->edid = edid;
1701 drm_edid->size = edid_size(edid);
1702
1703 return drm_edid;
1704 }
1705
1706 /*
1707 * EDID base and extension block iterator.
1708 *
1709 * struct drm_edid_iter iter;
1710 * const u8 *block;
1711 *
1712 * drm_edid_iter_begin(drm_edid, &iter);
1713 * drm_edid_iter_for_each(block, &iter) {
1714 * // do stuff with block
1715 * }
1716 * drm_edid_iter_end(&iter);
1717 */
1718 struct drm_edid_iter {
1719 const struct drm_edid *drm_edid;
1720
1721 /* Current block index. */
1722 int index;
1723 };
1724
drm_edid_iter_begin(const struct drm_edid * drm_edid,struct drm_edid_iter * iter)1725 static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
1726 struct drm_edid_iter *iter)
1727 {
1728 memset(iter, 0, sizeof(*iter));
1729
1730 iter->drm_edid = drm_edid;
1731 }
1732
__drm_edid_iter_next(struct drm_edid_iter * iter)1733 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1734 {
1735 const void *block = NULL;
1736
1737 if (!iter->drm_edid)
1738 return NULL;
1739
1740 if (iter->index < drm_edid_block_count(iter->drm_edid))
1741 block = drm_edid_block_data(iter->drm_edid, iter->index++);
1742
1743 return block;
1744 }
1745
1746 #define drm_edid_iter_for_each(__block, __iter) \
1747 while (((__block) = __drm_edid_iter_next(__iter)))
1748
drm_edid_iter_end(struct drm_edid_iter * iter)1749 static void drm_edid_iter_end(struct drm_edid_iter *iter)
1750 {
1751 memset(iter, 0, sizeof(*iter));
1752 }
1753
1754 static const u8 edid_header[] = {
1755 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1756 };
1757
edid_header_fix(void * edid)1758 static void edid_header_fix(void *edid)
1759 {
1760 memcpy(edid, edid_header, sizeof(edid_header));
1761 }
1762
1763 /**
1764 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1765 * @_edid: pointer to raw base EDID block
1766 *
1767 * Sanity check the header of the base EDID block.
1768 *
1769 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1770 */
drm_edid_header_is_valid(const void * _edid)1771 int drm_edid_header_is_valid(const void *_edid)
1772 {
1773 const struct edid *edid = _edid;
1774 int i, score = 0;
1775
1776 for (i = 0; i < sizeof(edid_header); i++) {
1777 if (edid->header[i] == edid_header[i])
1778 score++;
1779 }
1780
1781 return score;
1782 }
1783 EXPORT_SYMBOL(drm_edid_header_is_valid);
1784
1785 static int edid_fixup __read_mostly = 6;
1786 module_param_named(edid_fixup, edid_fixup, int, 0400);
1787 MODULE_PARM_DESC(edid_fixup,
1788 "Minimum number of valid EDID header bytes (0-8, default 6)");
1789
edid_block_compute_checksum(const void * _block)1790 static int edid_block_compute_checksum(const void *_block)
1791 {
1792 const u8 *block = _block;
1793 int i;
1794 u8 csum = 0, crc = 0;
1795
1796 for (i = 0; i < EDID_LENGTH - 1; i++)
1797 csum += block[i];
1798
1799 crc = 0x100 - csum;
1800
1801 return crc;
1802 }
1803
edid_block_get_checksum(const void * _block)1804 static int edid_block_get_checksum(const void *_block)
1805 {
1806 const struct edid *block = _block;
1807
1808 return block->checksum;
1809 }
1810
edid_block_tag(const void * _block)1811 static int edid_block_tag(const void *_block)
1812 {
1813 const u8 *block = _block;
1814
1815 return block[0];
1816 }
1817
edid_block_is_zero(const void * edid)1818 static bool edid_block_is_zero(const void *edid)
1819 {
1820 return mem_is_zero(edid, EDID_LENGTH);
1821 }
1822
drm_edid_eq(const struct drm_edid * drm_edid,const void * raw_edid,size_t raw_edid_size)1823 static bool drm_edid_eq(const struct drm_edid *drm_edid,
1824 const void *raw_edid, size_t raw_edid_size)
1825 {
1826 bool edid1_present = drm_edid && drm_edid->edid && drm_edid->size;
1827 bool edid2_present = raw_edid && raw_edid_size;
1828
1829 if (edid1_present != edid2_present)
1830 return false;
1831
1832 if (edid1_present) {
1833 if (drm_edid->size != raw_edid_size)
1834 return false;
1835
1836 if (memcmp(drm_edid->edid, raw_edid, drm_edid->size))
1837 return false;
1838 }
1839
1840 return true;
1841 }
1842
1843 enum edid_block_status {
1844 EDID_BLOCK_OK = 0,
1845 EDID_BLOCK_READ_FAIL,
1846 EDID_BLOCK_NULL,
1847 EDID_BLOCK_ZERO,
1848 EDID_BLOCK_HEADER_CORRUPT,
1849 EDID_BLOCK_HEADER_REPAIR,
1850 EDID_BLOCK_HEADER_FIXED,
1851 EDID_BLOCK_CHECKSUM,
1852 EDID_BLOCK_VERSION,
1853 };
1854
edid_block_check(const void * _block,bool is_base_block)1855 static enum edid_block_status edid_block_check(const void *_block,
1856 bool is_base_block)
1857 {
1858 const struct edid *block = _block;
1859
1860 if (!block)
1861 return EDID_BLOCK_NULL;
1862
1863 if (is_base_block) {
1864 int score = drm_edid_header_is_valid(block);
1865
1866 if (score < clamp(edid_fixup, 0, 8)) {
1867 if (edid_block_is_zero(block))
1868 return EDID_BLOCK_ZERO;
1869 else
1870 return EDID_BLOCK_HEADER_CORRUPT;
1871 }
1872
1873 if (score < 8)
1874 return EDID_BLOCK_HEADER_REPAIR;
1875 }
1876
1877 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1878 if (edid_block_is_zero(block))
1879 return EDID_BLOCK_ZERO;
1880 else
1881 return EDID_BLOCK_CHECKSUM;
1882 }
1883
1884 if (is_base_block) {
1885 if (block->version != 1)
1886 return EDID_BLOCK_VERSION;
1887 }
1888
1889 return EDID_BLOCK_OK;
1890 }
1891
edid_block_status_valid(enum edid_block_status status,int tag)1892 static bool edid_block_status_valid(enum edid_block_status status, int tag)
1893 {
1894 return status == EDID_BLOCK_OK ||
1895 status == EDID_BLOCK_HEADER_FIXED ||
1896 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1897 }
1898
edid_block_valid(const void * block,bool base)1899 static bool edid_block_valid(const void *block, bool base)
1900 {
1901 return edid_block_status_valid(edid_block_check(block, base),
1902 edid_block_tag(block));
1903 }
1904
edid_block_status_print(enum edid_block_status status,const struct edid * block,int block_num)1905 static void edid_block_status_print(enum edid_block_status status,
1906 const struct edid *block,
1907 int block_num)
1908 {
1909 switch (status) {
1910 case EDID_BLOCK_OK:
1911 break;
1912 case EDID_BLOCK_READ_FAIL:
1913 pr_debug("EDID block %d read failed\n", block_num);
1914 break;
1915 case EDID_BLOCK_NULL:
1916 pr_debug("EDID block %d pointer is NULL\n", block_num);
1917 break;
1918 case EDID_BLOCK_ZERO:
1919 pr_notice("EDID block %d is all zeroes\n", block_num);
1920 break;
1921 case EDID_BLOCK_HEADER_CORRUPT:
1922 pr_notice("EDID has corrupt header\n");
1923 break;
1924 case EDID_BLOCK_HEADER_REPAIR:
1925 pr_debug("EDID corrupt header needs repair\n");
1926 break;
1927 case EDID_BLOCK_HEADER_FIXED:
1928 pr_debug("EDID corrupt header fixed\n");
1929 break;
1930 case EDID_BLOCK_CHECKSUM:
1931 if (edid_block_status_valid(status, edid_block_tag(block))) {
1932 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1933 block_num, edid_block_tag(block),
1934 edid_block_compute_checksum(block));
1935 } else {
1936 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1937 block_num, edid_block_tag(block),
1938 edid_block_compute_checksum(block));
1939 }
1940 break;
1941 case EDID_BLOCK_VERSION:
1942 pr_notice("EDID has major version %d, instead of 1\n",
1943 block->version);
1944 break;
1945 default:
1946 WARN(1, "EDID block %d unknown edid block status code %d\n",
1947 block_num, status);
1948 break;
1949 }
1950 }
1951
edid_block_dump(const char * level,const void * block,int block_num)1952 static void edid_block_dump(const char *level, const void *block, int block_num)
1953 {
1954 enum edid_block_status status;
1955 char prefix[20];
1956
1957 status = edid_block_check(block, block_num == 0);
1958 if (status == EDID_BLOCK_ZERO)
1959 snprintf(prefix, sizeof(prefix), "\t[%02x] ZERO ", block_num);
1960 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1961 snprintf(prefix, sizeof(prefix), "\t[%02x] BAD ", block_num);
1962 else
1963 snprintf(prefix, sizeof(prefix), "\t[%02x] GOOD ", block_num);
1964
1965 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1966 block, EDID_LENGTH, false);
1967 }
1968
1969 /*
1970 * Validate a base or extension EDID block and optionally dump bad blocks to
1971 * the console.
1972 */
drm_edid_block_valid(void * _block,int block_num,bool print_bad_edid,bool * edid_corrupt)1973 static bool drm_edid_block_valid(void *_block, int block_num, bool print_bad_edid,
1974 bool *edid_corrupt)
1975 {
1976 struct edid *block = _block;
1977 enum edid_block_status status;
1978 bool is_base_block = block_num == 0;
1979 bool valid;
1980
1981 if (WARN_ON(!block))
1982 return false;
1983
1984 status = edid_block_check(block, is_base_block);
1985 if (status == EDID_BLOCK_HEADER_REPAIR) {
1986 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n");
1987 edid_header_fix(block);
1988
1989 /* Retry with fixed header, update status if that worked. */
1990 status = edid_block_check(block, is_base_block);
1991 if (status == EDID_BLOCK_OK)
1992 status = EDID_BLOCK_HEADER_FIXED;
1993 }
1994
1995 if (edid_corrupt) {
1996 /*
1997 * Unknown major version isn't corrupt but we can't use it. Only
1998 * the base block can reset edid_corrupt to false.
1999 */
2000 if (is_base_block &&
2001 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
2002 *edid_corrupt = false;
2003 else if (status != EDID_BLOCK_OK)
2004 *edid_corrupt = true;
2005 }
2006
2007 edid_block_status_print(status, block, block_num);
2008
2009 /* Determine whether we can use this block with this status. */
2010 valid = edid_block_status_valid(status, edid_block_tag(block));
2011
2012 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2013 pr_notice("Raw EDID:\n");
2014 edid_block_dump(KERN_NOTICE, block, block_num);
2015 }
2016
2017 return valid;
2018 }
2019
2020 /**
2021 * drm_edid_is_valid - sanity check EDID data
2022 * @edid: EDID data
2023 *
2024 * Sanity-check an entire EDID record (including extensions)
2025 *
2026 * Return: True if the EDID data is valid, false otherwise.
2027 */
drm_edid_is_valid(struct edid * edid)2028 bool drm_edid_is_valid(struct edid *edid)
2029 {
2030 int i;
2031
2032 if (!edid)
2033 return false;
2034
2035 for (i = 0; i < edid_block_count(edid); i++) {
2036 void *block = (void *)edid_block_data(edid, i);
2037
2038 if (!drm_edid_block_valid(block, i, true, NULL))
2039 return false;
2040 }
2041
2042 return true;
2043 }
2044 EXPORT_SYMBOL(drm_edid_is_valid);
2045
2046 /**
2047 * drm_edid_valid - sanity check EDID data
2048 * @drm_edid: EDID data
2049 *
2050 * Sanity check an EDID. Cross check block count against allocated size and
2051 * checksum the blocks.
2052 *
2053 * Return: True if the EDID data is valid, false otherwise.
2054 */
drm_edid_valid(const struct drm_edid * drm_edid)2055 bool drm_edid_valid(const struct drm_edid *drm_edid)
2056 {
2057 int i;
2058
2059 if (!drm_edid)
2060 return false;
2061
2062 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size)
2063 return false;
2064
2065 for (i = 0; i < drm_edid_block_count(drm_edid); i++) {
2066 const void *block = drm_edid_block_data(drm_edid, i);
2067
2068 if (!edid_block_valid(block, i == 0))
2069 return false;
2070 }
2071
2072 return true;
2073 }
2074 EXPORT_SYMBOL(drm_edid_valid);
2075
edid_filter_invalid_blocks(struct edid * edid,size_t * alloc_size)2076 static struct edid *edid_filter_invalid_blocks(struct edid *edid,
2077 size_t *alloc_size)
2078 {
2079 struct edid *new;
2080 int i, valid_blocks = 0;
2081
2082 /*
2083 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2084 * back to regular extension count here. We don't want to start
2085 * modifying the HF-EEODB extension too.
2086 */
2087 for (i = 0; i < edid_block_count(edid); i++) {
2088 const void *src_block = edid_block_data(edid, i);
2089
2090 if (edid_block_valid(src_block, i == 0)) {
2091 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
2092
2093 memmove(dst_block, src_block, EDID_LENGTH);
2094 valid_blocks++;
2095 }
2096 }
2097
2098 /* We already trusted the base block to be valid here... */
2099 if (WARN_ON(!valid_blocks)) {
2100 kfree(edid);
2101 return NULL;
2102 }
2103
2104 edid->extensions = valid_blocks - 1;
2105 edid->checksum = edid_block_compute_checksum(edid);
2106
2107 *alloc_size = edid_size_by_blocks(valid_blocks);
2108
2109 #ifdef __linux__
2110 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2111 if (!new)
2112 kfree(edid);
2113 #else
2114 new = kmalloc(*alloc_size, GFP_KERNEL);
2115 if (!new) {
2116 kfree(edid);
2117 return NULL;
2118 }
2119 memcpy(new, edid, EDID_LENGTH);
2120 kfree(edid);
2121 #endif
2122
2123 return new;
2124 }
2125
2126 #define DDC_SEGMENT_ADDR 0x30
2127 /**
2128 * drm_do_probe_ddc_edid() - get EDID information via I2C
2129 * @data: I2C device adapter
2130 * @buf: EDID data buffer to be filled
2131 * @block: 128 byte EDID block to start fetching from
2132 * @len: EDID data buffer length to fetch
2133 *
2134 * Try to fetch EDID information by calling I2C driver functions.
2135 *
2136 * Return: 0 on success or -1 on failure.
2137 */
2138 static int
drm_do_probe_ddc_edid(void * data,u8 * buf,unsigned int block,size_t len)2139 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
2140 {
2141 struct i2c_adapter *adapter = data;
2142 unsigned char start = block * EDID_LENGTH;
2143 unsigned char segment = block >> 1;
2144 unsigned char xfers = segment ? 3 : 2;
2145 int ret, retries = 5;
2146
2147 /*
2148 * The core I2C driver will automatically retry the transfer if the
2149 * adapter reports EAGAIN. However, we find that bit-banging transfers
2150 * are susceptible to errors under a heavily loaded machine and
2151 * generate spurious NAKs and timeouts. Retrying the transfer
2152 * of the individual block a few times seems to overcome this.
2153 */
2154 do {
2155 struct i2c_msg msgs[] = {
2156 {
2157 .addr = DDC_SEGMENT_ADDR,
2158 .flags = 0,
2159 .len = 1,
2160 .buf = &segment,
2161 }, {
2162 .addr = DDC_ADDR,
2163 .flags = 0,
2164 .len = 1,
2165 .buf = &start,
2166 }, {
2167 .addr = DDC_ADDR,
2168 .flags = I2C_M_RD,
2169 .len = len,
2170 .buf = buf,
2171 }
2172 };
2173
2174 /*
2175 * Avoid sending the segment addr to not upset non-compliant
2176 * DDC monitors.
2177 */
2178 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2179
2180 if (ret == -ENXIO) {
2181 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2182 adapter->name);
2183 break;
2184 }
2185 } while (ret != xfers && --retries);
2186
2187 return ret == xfers ? 0 : -1;
2188 }
2189
connector_bad_edid(struct drm_connector * connector,const struct edid * edid,int num_blocks)2190 static void connector_bad_edid(struct drm_connector *connector,
2191 const struct edid *edid, int num_blocks)
2192 {
2193 int i;
2194 u8 last_block;
2195
2196 /*
2197 * 0x7e in the EDID is the number of extension blocks. The EDID
2198 * is 1 (base block) + num_ext_blocks big. That means we can think
2199 * of 0x7e in the EDID of the _index_ of the last block in the
2200 * combined chunk of memory.
2201 */
2202 last_block = edid->extensions;
2203
2204 /* Calculate real checksum for the last edid extension block data */
2205 if (last_block < num_blocks)
2206 connector->real_edid_checksum =
2207 edid_block_compute_checksum(edid + last_block);
2208
2209 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
2210 return;
2211
2212 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n",
2213 connector->base.id, connector->name);
2214 for (i = 0; i < num_blocks; i++)
2215 edid_block_dump(KERN_DEBUG, edid + i, i);
2216 }
2217
2218 /* Get override or firmware EDID */
drm_edid_override_get(struct drm_connector * connector)2219 static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector)
2220 {
2221 const struct drm_edid *override = NULL;
2222
2223 mutex_lock(&connector->edid_override_mutex);
2224
2225 if (connector->edid_override)
2226 override = drm_edid_dup(connector->edid_override);
2227
2228 mutex_unlock(&connector->edid_override_mutex);
2229
2230 if (!override)
2231 override = drm_edid_load_firmware(connector);
2232
2233 return IS_ERR(override) ? NULL : override;
2234 }
2235
2236 /* For debugfs edid_override implementation */
drm_edid_override_show(struct drm_connector * connector,struct seq_file * m)2237 int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m)
2238 {
2239 const struct drm_edid *drm_edid;
2240
2241 mutex_lock(&connector->edid_override_mutex);
2242
2243 drm_edid = connector->edid_override;
2244 if (drm_edid)
2245 seq_write(m, drm_edid->edid, drm_edid->size);
2246
2247 mutex_unlock(&connector->edid_override_mutex);
2248
2249 return 0;
2250 }
2251
2252 /* For debugfs edid_override implementation */
drm_edid_override_set(struct drm_connector * connector,const void * edid,size_t size)2253 int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2254 size_t size)
2255 {
2256 const struct drm_edid *drm_edid;
2257
2258 drm_edid = drm_edid_alloc(edid, size);
2259 if (!drm_edid_valid(drm_edid)) {
2260 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n",
2261 connector->base.id, connector->name);
2262 drm_edid_free(drm_edid);
2263 return -EINVAL;
2264 }
2265
2266 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n",
2267 connector->base.id, connector->name);
2268
2269 mutex_lock(&connector->edid_override_mutex);
2270
2271 drm_edid_free(connector->edid_override);
2272 connector->edid_override = drm_edid;
2273
2274 mutex_unlock(&connector->edid_override_mutex);
2275
2276 return 0;
2277 }
2278
2279 /* For debugfs edid_override implementation */
drm_edid_override_reset(struct drm_connector * connector)2280 int drm_edid_override_reset(struct drm_connector *connector)
2281 {
2282 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n",
2283 connector->base.id, connector->name);
2284
2285 mutex_lock(&connector->edid_override_mutex);
2286
2287 drm_edid_free(connector->edid_override);
2288 connector->edid_override = NULL;
2289
2290 mutex_unlock(&connector->edid_override_mutex);
2291
2292 return 0;
2293 }
2294
2295 /**
2296 * drm_edid_override_connector_update - add modes from override/firmware EDID
2297 * @connector: connector we're probing
2298 *
2299 * Add modes from the override/firmware EDID, if available. Only to be used from
2300 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2301 * failed during drm_get_edid() and caused the override/firmware EDID to be
2302 * skipped.
2303 *
2304 * Return: The number of modes added or 0 if we couldn't find any.
2305 */
drm_edid_override_connector_update(struct drm_connector * connector)2306 int drm_edid_override_connector_update(struct drm_connector *connector)
2307 {
2308 const struct drm_edid *override;
2309 int num_modes = 0;
2310
2311 override = drm_edid_override_get(connector);
2312 if (override) {
2313 if (drm_edid_connector_update(connector, override) == 0)
2314 num_modes = drm_edid_connector_add_modes(connector);
2315
2316 drm_edid_free(override);
2317
2318 drm_dbg_kms(connector->dev,
2319 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2320 connector->base.id, connector->name, num_modes);
2321 }
2322
2323 return num_modes;
2324 }
2325 EXPORT_SYMBOL(drm_edid_override_connector_update);
2326
2327 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2328
edid_block_read(void * block,unsigned int block_num,read_block_fn read_block,void * context)2329 static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2330 read_block_fn read_block,
2331 void *context)
2332 {
2333 enum edid_block_status status;
2334 bool is_base_block = block_num == 0;
2335 int try;
2336
2337 for (try = 0; try < 4; try++) {
2338 if (read_block(context, block, block_num, EDID_LENGTH))
2339 return EDID_BLOCK_READ_FAIL;
2340
2341 status = edid_block_check(block, is_base_block);
2342 if (status == EDID_BLOCK_HEADER_REPAIR) {
2343 edid_header_fix(block);
2344
2345 /* Retry with fixed header, update status if that worked. */
2346 status = edid_block_check(block, is_base_block);
2347 if (status == EDID_BLOCK_OK)
2348 status = EDID_BLOCK_HEADER_FIXED;
2349 }
2350
2351 if (edid_block_status_valid(status, edid_block_tag(block)))
2352 break;
2353
2354 /* Fail early for unrepairable base block all zeros. */
2355 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2356 break;
2357 }
2358
2359 return status;
2360 }
2361
_drm_do_get_edid(struct drm_connector * connector,read_block_fn read_block,void * context,size_t * size)2362 static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2363 read_block_fn read_block, void *context,
2364 size_t *size)
2365 {
2366 enum edid_block_status status;
2367 int i, num_blocks, invalid_blocks = 0;
2368 const struct drm_edid *override;
2369 struct edid *edid, *new;
2370 size_t alloc_size = EDID_LENGTH;
2371
2372 override = drm_edid_override_get(connector);
2373 if (override) {
2374 alloc_size = override->size;
2375 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL);
2376 drm_edid_free(override);
2377 if (!edid)
2378 return NULL;
2379 goto ok;
2380 }
2381
2382 edid = kmalloc(alloc_size, GFP_KERNEL);
2383 if (!edid)
2384 return NULL;
2385
2386 status = edid_block_read(edid, 0, read_block, context);
2387
2388 edid_block_status_print(status, edid, 0);
2389
2390 if (status == EDID_BLOCK_READ_FAIL)
2391 goto fail;
2392
2393 /* FIXME: Clarify what a corrupt EDID actually means. */
2394 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2395 connector->edid_corrupt = false;
2396 else
2397 connector->edid_corrupt = true;
2398
2399 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2400 if (status == EDID_BLOCK_ZERO)
2401 connector->null_edid_counter++;
2402
2403 connector_bad_edid(connector, edid, 1);
2404 goto fail;
2405 }
2406
2407 if (!edid_extension_block_count(edid))
2408 goto ok;
2409
2410 alloc_size = edid_size(edid);
2411 #ifdef __linux__
2412 new = krealloc(edid, alloc_size, GFP_KERNEL);
2413 if (!new)
2414 goto fail;
2415 #else
2416 new = kmalloc(alloc_size, GFP_KERNEL);
2417 if (!new)
2418 goto fail;
2419 memcpy(new, edid, EDID_LENGTH);
2420 kfree(edid);
2421 #endif
2422 edid = new;
2423
2424 num_blocks = edid_block_count(edid);
2425 for (i = 1; i < num_blocks; i++) {
2426 void *block = (void *)edid_block_data(edid, i);
2427
2428 status = edid_block_read(block, i, read_block, context);
2429
2430 edid_block_status_print(status, block, i);
2431
2432 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2433 if (status == EDID_BLOCK_READ_FAIL)
2434 goto fail;
2435 invalid_blocks++;
2436 } else if (i == 1) {
2437 /*
2438 * If the first EDID extension is a CTA extension, and
2439 * the first Data Block is HF-EEODB, override the
2440 * extension block count.
2441 *
2442 * Note: HF-EEODB could specify a smaller extension
2443 * count too, but we can't risk allocating a smaller
2444 * amount.
2445 */
2446 int eeodb = edid_hfeeodb_block_count(edid);
2447
2448 if (eeodb > num_blocks) {
2449 num_blocks = eeodb;
2450 alloc_size = edid_size_by_blocks(num_blocks);
2451 #ifdef __linux__
2452 new = krealloc(edid, alloc_size, GFP_KERNEL);
2453 if (!new)
2454 goto fail;
2455 #else
2456 new = kmalloc(alloc_size, GFP_KERNEL);
2457 if (!new)
2458 goto fail;
2459 memcpy(new, edid, EDID_LENGTH);
2460 kfree(edid);
2461 #endif
2462 edid = new;
2463 }
2464 }
2465 }
2466
2467 if (invalid_blocks) {
2468 connector_bad_edid(connector, edid, num_blocks);
2469
2470 edid = edid_filter_invalid_blocks(edid, &alloc_size);
2471 }
2472
2473 ok:
2474 if (size)
2475 *size = alloc_size;
2476
2477 return edid;
2478
2479 fail:
2480 kfree(edid);
2481 return NULL;
2482 }
2483
2484 /**
2485 * drm_edid_raw - Get a pointer to the raw EDID data.
2486 * @drm_edid: drm_edid container
2487 *
2488 * Get a pointer to the raw EDID data.
2489 *
2490 * This is for transition only. Avoid using this like the plague.
2491 *
2492 * Return: Pointer to raw EDID data.
2493 */
drm_edid_raw(const struct drm_edid * drm_edid)2494 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2495 {
2496 if (!drm_edid || !drm_edid->size)
2497 return NULL;
2498
2499 /*
2500 * Do not return pointers where relying on EDID extension count would
2501 * lead to buffer overflow.
2502 */
2503 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2504 return NULL;
2505
2506 return drm_edid->edid;
2507 }
2508 EXPORT_SYMBOL(drm_edid_raw);
2509
2510 /* Allocate struct drm_edid container *without* duplicating the edid data */
_drm_edid_alloc(const void * edid,size_t size)2511 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2512 {
2513 struct drm_edid *drm_edid;
2514
2515 if (!edid || !size || size < EDID_LENGTH)
2516 return NULL;
2517
2518 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2519 if (drm_edid) {
2520 drm_edid->edid = edid;
2521 drm_edid->size = size;
2522 }
2523
2524 return drm_edid;
2525 }
2526
2527 /**
2528 * drm_edid_alloc - Allocate a new drm_edid container
2529 * @edid: Pointer to raw EDID data
2530 * @size: Size of memory allocated for EDID
2531 *
2532 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2533 * the actual size that has been allocated for the data. There is no validation
2534 * of the raw EDID data against the size, but at least the EDID base block must
2535 * fit in the buffer.
2536 *
2537 * The returned pointer must be freed using drm_edid_free().
2538 *
2539 * Return: drm_edid container, or NULL on errors
2540 */
drm_edid_alloc(const void * edid,size_t size)2541 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2542 {
2543 const struct drm_edid *drm_edid;
2544
2545 if (!edid || !size || size < EDID_LENGTH)
2546 return NULL;
2547
2548 edid = kmemdup(edid, size, GFP_KERNEL);
2549 if (!edid)
2550 return NULL;
2551
2552 drm_edid = _drm_edid_alloc(edid, size);
2553 if (!drm_edid)
2554 kfree(edid);
2555
2556 return drm_edid;
2557 }
2558 EXPORT_SYMBOL(drm_edid_alloc);
2559
2560 /**
2561 * drm_edid_dup - Duplicate a drm_edid container
2562 * @drm_edid: EDID to duplicate
2563 *
2564 * The returned pointer must be freed using drm_edid_free().
2565 *
2566 * Returns: drm_edid container copy, or NULL on errors
2567 */
drm_edid_dup(const struct drm_edid * drm_edid)2568 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2569 {
2570 if (!drm_edid)
2571 return NULL;
2572
2573 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2574 }
2575 EXPORT_SYMBOL(drm_edid_dup);
2576
2577 /**
2578 * drm_edid_free - Free the drm_edid container
2579 * @drm_edid: EDID to free
2580 */
drm_edid_free(const struct drm_edid * drm_edid)2581 void drm_edid_free(const struct drm_edid *drm_edid)
2582 {
2583 if (!drm_edid)
2584 return;
2585
2586 kfree(drm_edid->edid);
2587 kfree(drm_edid);
2588 }
2589 EXPORT_SYMBOL(drm_edid_free);
2590
2591 /**
2592 * drm_probe_ddc() - probe DDC presence
2593 * @adapter: I2C adapter to probe
2594 *
2595 * Return: True on success, false on failure.
2596 */
2597 bool
drm_probe_ddc(struct i2c_adapter * adapter)2598 drm_probe_ddc(struct i2c_adapter *adapter)
2599 {
2600 unsigned char out;
2601
2602 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2603 }
2604 EXPORT_SYMBOL(drm_probe_ddc);
2605
2606 /**
2607 * drm_get_edid - get EDID data, if available
2608 * @connector: connector we're probing
2609 * @adapter: I2C adapter to use for DDC
2610 *
2611 * Poke the given I2C channel to grab EDID data if possible. If found,
2612 * attach it to the connector.
2613 *
2614 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2615 */
drm_get_edid(struct drm_connector * connector,struct i2c_adapter * adapter)2616 struct edid *drm_get_edid(struct drm_connector *connector,
2617 struct i2c_adapter *adapter)
2618 {
2619 struct edid *edid;
2620
2621 if (connector->force == DRM_FORCE_OFF)
2622 return NULL;
2623
2624 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2625 return NULL;
2626
2627 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
2628 drm_connector_update_edid_property(connector, edid);
2629 return edid;
2630 }
2631 EXPORT_SYMBOL(drm_get_edid);
2632
2633 /**
2634 * drm_edid_read_custom - Read EDID data using given EDID block read function
2635 * @connector: Connector to use
2636 * @read_block: EDID block read function
2637 * @context: Private data passed to the block read function
2638 *
2639 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2640 * exposes a different interface to read EDID blocks this function can be used
2641 * to get EDID data using a custom block read function.
2642 *
2643 * As in the general case the DDC bus is accessible by the kernel at the I2C
2644 * level, drivers must make all reasonable efforts to expose it as an I2C
2645 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2646 * this function.
2647 *
2648 * The EDID may be overridden using debugfs override_edid or firmware EDID
2649 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2650 * order. Having either of them bypasses actual EDID reads.
2651 *
2652 * The returned pointer must be freed using drm_edid_free().
2653 *
2654 * Return: Pointer to EDID, or NULL if probe/read failed.
2655 */
drm_edid_read_custom(struct drm_connector * connector,read_block_fn read_block,void * context)2656 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2657 read_block_fn read_block,
2658 void *context)
2659 {
2660 const struct drm_edid *drm_edid;
2661 struct edid *edid;
2662 size_t size = 0;
2663
2664 edid = _drm_do_get_edid(connector, read_block, context, &size);
2665 if (!edid)
2666 return NULL;
2667
2668 /* Sanity check for now */
2669 drm_WARN_ON(connector->dev, !size);
2670
2671 drm_edid = _drm_edid_alloc(edid, size);
2672 if (!drm_edid)
2673 kfree(edid);
2674
2675 return drm_edid;
2676 }
2677 EXPORT_SYMBOL(drm_edid_read_custom);
2678
2679 /**
2680 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2681 * @connector: Connector to use
2682 * @adapter: I2C adapter to use for DDC
2683 *
2684 * Read EDID using the given I2C adapter.
2685 *
2686 * The EDID may be overridden using debugfs override_edid or firmware EDID
2687 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2688 * order. Having either of them bypasses actual EDID reads.
2689 *
2690 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2691 * using drm_edid_read() instead of this function.
2692 *
2693 * The returned pointer must be freed using drm_edid_free().
2694 *
2695 * Return: Pointer to EDID, or NULL if probe/read failed.
2696 */
drm_edid_read_ddc(struct drm_connector * connector,struct i2c_adapter * adapter)2697 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2698 struct i2c_adapter *adapter)
2699 {
2700 const struct drm_edid *drm_edid;
2701
2702 if (connector->force == DRM_FORCE_OFF)
2703 return NULL;
2704
2705 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2706 return NULL;
2707
2708 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2709
2710 /* Note: Do *not* call connector updates here. */
2711
2712 return drm_edid;
2713 }
2714 EXPORT_SYMBOL(drm_edid_read_ddc);
2715
2716 /**
2717 * drm_edid_read - Read EDID data using connector's I2C adapter
2718 * @connector: Connector to use
2719 *
2720 * Read EDID using the connector's I2C adapter.
2721 *
2722 * The EDID may be overridden using debugfs override_edid or firmware EDID
2723 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2724 * order. Having either of them bypasses actual EDID reads.
2725 *
2726 * The returned pointer must be freed using drm_edid_free().
2727 *
2728 * Return: Pointer to EDID, or NULL if probe/read failed.
2729 */
drm_edid_read(struct drm_connector * connector)2730 const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2731 {
2732 if (drm_WARN_ON(connector->dev, !connector->ddc))
2733 return NULL;
2734
2735 return drm_edid_read_ddc(connector, connector->ddc);
2736 }
2737 EXPORT_SYMBOL(drm_edid_read);
2738
2739 /**
2740 * drm_edid_get_product_id - Get the vendor and product identification
2741 * @drm_edid: EDID
2742 * @id: Where to place the product id
2743 */
drm_edid_get_product_id(const struct drm_edid * drm_edid,struct drm_edid_product_id * id)2744 void drm_edid_get_product_id(const struct drm_edid *drm_edid,
2745 struct drm_edid_product_id *id)
2746 {
2747 if (drm_edid && drm_edid->edid && drm_edid->size >= EDID_LENGTH)
2748 memcpy(id, &drm_edid->edid->product_id, sizeof(*id));
2749 else
2750 memset(id, 0, sizeof(*id));
2751 }
2752 EXPORT_SYMBOL(drm_edid_get_product_id);
2753
2754 #ifdef notyet
decode_date(struct seq_buf * s,const struct drm_edid_product_id * id)2755 static void decode_date(struct seq_buf *s, const struct drm_edid_product_id *id)
2756 {
2757 int week = id->week_of_manufacture;
2758 int year = id->year_of_manufacture + 1990;
2759
2760 if (week == 0xff)
2761 seq_buf_printf(s, "model year: %d", year);
2762 else if (!week)
2763 seq_buf_printf(s, "year of manufacture: %d", year);
2764 else
2765 seq_buf_printf(s, "week/year of manufacture: %d/%d", week, year);
2766 }
2767 #endif
2768
2769 /**
2770 * drm_edid_print_product_id - Print decoded product id to printer
2771 * @p: drm printer
2772 * @id: EDID product id
2773 * @raw: If true, also print the raw hex
2774 *
2775 * See VESA E-EDID 1.4 section 3.4.
2776 */
drm_edid_print_product_id(struct drm_printer * p,const struct drm_edid_product_id * id,bool raw)2777 void drm_edid_print_product_id(struct drm_printer *p,
2778 const struct drm_edid_product_id *id, bool raw)
2779 {
2780 #ifdef notyet
2781 DECLARE_SEQ_BUF(date, 40);
2782 #endif
2783 char vend[4];
2784
2785 drm_edid_decode_mfg_id(be16_to_cpu(id->manufacturer_name), vend);
2786
2787 #ifdef notyet
2788 decode_date(&date, id);
2789
2790 drm_printf(p, "manufacturer name: %s, product code: %u, serial number: %u, %s\n",
2791 vend, le16_to_cpu(id->product_code),
2792 le32_to_cpu(id->serial_number), seq_buf_str(&date));
2793 #else
2794 drm_printf(p, "manufacturer name: %s, product code: %u, serial number: %u\n",
2795 vend, le16_to_cpu(id->product_code),
2796 le32_to_cpu(id->serial_number));
2797 #endif
2798
2799 if (raw)
2800 drm_printf(p, "raw product id: %*ph\n", (int)sizeof(*id), id);
2801
2802 #ifdef notyet
2803 WARN_ON(seq_buf_has_overflowed(&date));
2804 #endif
2805 }
2806 EXPORT_SYMBOL(drm_edid_print_product_id);
2807
2808 /**
2809 * drm_edid_get_panel_id - Get a panel's ID from EDID
2810 * @drm_edid: EDID that contains panel ID.
2811 *
2812 * This function uses the first block of the EDID of a panel and (assuming
2813 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2814 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2815 * supposed to be different for each different modem of panel.
2816 *
2817 * Return: A 32-bit ID that should be different for each make/model of panel.
2818 * See the functions drm_edid_encode_panel_id() and
2819 * drm_edid_decode_panel_id() for some details on the structure of this
2820 * ID. Return 0 if the EDID size is less than a base block.
2821 */
drm_edid_get_panel_id(const struct drm_edid * drm_edid)2822 u32 drm_edid_get_panel_id(const struct drm_edid *drm_edid)
2823 {
2824 const struct edid *edid = drm_edid->edid;
2825
2826 if (drm_edid->size < EDID_LENGTH)
2827 return 0;
2828
2829 /*
2830 * We represent the ID as a 32-bit number so it can easily be compared
2831 * with "==".
2832 *
2833 * NOTE that we deal with endianness differently for the top half
2834 * of this ID than for the bottom half. The bottom half (the product
2835 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2836 * that's how everyone seems to interpret it. The top half (the mfg_id)
2837 * gets stored as big endian because that makes
2838 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2839 * to write (it's easier to extract the ASCII). It doesn't really
2840 * matter, though, as long as the number here is unique.
2841 */
2842 return (u32)edid->mfg_id[0] << 24 |
2843 (u32)edid->mfg_id[1] << 16 |
2844 (u32)EDID_PRODUCT_ID(edid);
2845 }
2846 EXPORT_SYMBOL(drm_edid_get_panel_id);
2847
2848 /**
2849 * drm_edid_read_base_block - Get a panel's EDID base block
2850 * @adapter: I2C adapter to use for DDC
2851 *
2852 * This function returns the drm_edid containing the first block of the EDID of
2853 * a panel.
2854 *
2855 * This function is intended to be used during early probing on devices where
2856 * more than one panel might be present. Because of its intended use it must
2857 * assume that the EDID of the panel is correct, at least as far as the base
2858 * block is concerned (in other words, we don't process any overrides here).
2859 *
2860 * Caller should call drm_edid_free() after use.
2861 *
2862 * NOTE: it's expected that this function and drm_do_get_edid() will both
2863 * be read the EDID, but there is no caching between them. Since we're only
2864 * reading the first block, hopefully this extra overhead won't be too big.
2865 *
2866 * WARNING: Only use this function when the connector is unknown. For example,
2867 * during the early probe of panel. The EDID read from the function is temporary
2868 * and should be replaced by the full EDID returned from other drm_edid_read.
2869 *
2870 * Return: Pointer to allocated EDID base block, or NULL on any failure.
2871 */
drm_edid_read_base_block(struct i2c_adapter * adapter)2872 const struct drm_edid *drm_edid_read_base_block(struct i2c_adapter *adapter)
2873 {
2874 enum edid_block_status status;
2875 void *base_block;
2876
2877 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL);
2878 if (!base_block)
2879 return NULL;
2880
2881 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2882
2883 edid_block_status_print(status, base_block, 0);
2884
2885 if (!edid_block_status_valid(status, edid_block_tag(base_block))) {
2886 edid_block_dump(KERN_NOTICE, base_block, 0);
2887 kfree(base_block);
2888 return NULL;
2889 }
2890
2891 return _drm_edid_alloc(base_block, EDID_LENGTH);
2892 }
2893 EXPORT_SYMBOL(drm_edid_read_base_block);
2894
2895 /**
2896 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2897 * @connector: connector we're probing
2898 * @adapter: I2C adapter to use for DDC
2899 *
2900 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2901 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2902 * switch DDC to the GPU which is retrieving EDID.
2903 *
2904 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2905 */
drm_get_edid_switcheroo(struct drm_connector * connector,struct i2c_adapter * adapter)2906 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2907 struct i2c_adapter *adapter)
2908 {
2909 STUB();
2910 return NULL;
2911 #ifdef notyet
2912 struct drm_device *dev = connector->dev;
2913 struct pci_dev *pdev = to_pci_dev(dev->dev);
2914 struct edid *edid;
2915
2916 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2917 return NULL;
2918
2919 vga_switcheroo_lock_ddc(pdev);
2920 edid = drm_get_edid(connector, adapter);
2921 vga_switcheroo_unlock_ddc(pdev);
2922
2923 return edid;
2924 #endif
2925 }
2926 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2927
2928 /**
2929 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output
2930 * @connector: connector we're probing
2931 * @adapter: I2C adapter to use for DDC
2932 *
2933 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set
2934 * of outputs. The wrapper adds the requisite vga_switcheroo calls to
2935 * temporarily switch DDC to the GPU which is retrieving EDID.
2936 *
2937 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2938 */
drm_edid_read_switcheroo(struct drm_connector * connector,struct i2c_adapter * adapter)2939 const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector,
2940 struct i2c_adapter *adapter)
2941 {
2942 STUB();
2943 return NULL;
2944 #ifdef notyet
2945 struct drm_device *dev = connector->dev;
2946 struct pci_dev *pdev = to_pci_dev(dev->dev);
2947 const struct drm_edid *drm_edid;
2948
2949 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2950 return NULL;
2951
2952 vga_switcheroo_lock_ddc(pdev);
2953 drm_edid = drm_edid_read_ddc(connector, adapter);
2954 vga_switcheroo_unlock_ddc(pdev);
2955
2956 return drm_edid;
2957 #endif
2958 }
2959 EXPORT_SYMBOL(drm_edid_read_switcheroo);
2960
2961 /**
2962 * drm_edid_duplicate - duplicate an EDID and the extensions
2963 * @edid: EDID to duplicate
2964 *
2965 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2966 */
drm_edid_duplicate(const struct edid * edid)2967 struct edid *drm_edid_duplicate(const struct edid *edid)
2968 {
2969 if (!edid)
2970 return NULL;
2971
2972 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
2973 }
2974 EXPORT_SYMBOL(drm_edid_duplicate);
2975
2976 /*** EDID parsing ***/
2977
2978 /**
2979 * edid_get_quirks - return quirk flags for a given EDID
2980 * @drm_edid: EDID to process
2981 *
2982 * This tells subsequent routines what fixes they need to apply.
2983 *
2984 * Return: A u32 represents the quirks to apply.
2985 */
edid_get_quirks(const struct drm_edid * drm_edid)2986 static u32 edid_get_quirks(const struct drm_edid *drm_edid)
2987 {
2988 const struct edid_quirk *quirk;
2989 int i;
2990
2991 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2992 quirk = &edid_quirk_list[i];
2993 if (drm_edid_match(drm_edid, &quirk->ident))
2994 return quirk->quirks;
2995 }
2996
2997 return 0;
2998 }
2999
3000 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
3001 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
3002
3003 /*
3004 * Walk the mode list for connector, clearing the preferred status on existing
3005 * modes and setting it anew for the right mode ala quirks.
3006 */
edid_fixup_preferred(struct drm_connector * connector)3007 static void edid_fixup_preferred(struct drm_connector *connector)
3008 {
3009 const struct drm_display_info *info = &connector->display_info;
3010 struct drm_display_mode *t, *cur_mode, *preferred_mode;
3011 int target_refresh = 0;
3012 int cur_vrefresh, preferred_vrefresh;
3013
3014 if (list_empty(&connector->probed_modes))
3015 return;
3016
3017 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60)
3018 target_refresh = 60;
3019 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75)
3020 target_refresh = 75;
3021
3022 preferred_mode = list_first_entry(&connector->probed_modes,
3023 struct drm_display_mode, head);
3024
3025 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
3026 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3027
3028 if (cur_mode == preferred_mode)
3029 continue;
3030
3031 /* Largest mode is preferred */
3032 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
3033 preferred_mode = cur_mode;
3034
3035 cur_vrefresh = drm_mode_vrefresh(cur_mode);
3036 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
3037 /* At a given size, try to get closest to target refresh */
3038 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
3039 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
3040 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
3041 preferred_mode = cur_mode;
3042 }
3043 }
3044
3045 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
3046 }
3047
3048 static bool
mode_is_rb(const struct drm_display_mode * mode)3049 mode_is_rb(const struct drm_display_mode *mode)
3050 {
3051 return (mode->htotal - mode->hdisplay == 160) &&
3052 (mode->hsync_end - mode->hdisplay == 80) &&
3053 (mode->hsync_end - mode->hsync_start == 32) &&
3054 (mode->vsync_start - mode->vdisplay == 3);
3055 }
3056
3057 /*
3058 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
3059 * @dev: Device to duplicate against
3060 * @hsize: Mode width
3061 * @vsize: Mode height
3062 * @fresh: Mode refresh rate
3063 * @rb: Mode reduced-blanking-ness
3064 *
3065 * Walk the DMT mode list looking for a match for the given parameters.
3066 *
3067 * Return: A newly allocated copy of the mode, or NULL if not found.
3068 */
drm_mode_find_dmt(struct drm_device * dev,int hsize,int vsize,int fresh,bool rb)3069 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
3070 int hsize, int vsize, int fresh,
3071 bool rb)
3072 {
3073 int i;
3074
3075 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3076 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
3077
3078 if (hsize != ptr->hdisplay)
3079 continue;
3080 if (vsize != ptr->vdisplay)
3081 continue;
3082 if (fresh != drm_mode_vrefresh(ptr))
3083 continue;
3084 if (rb != mode_is_rb(ptr))
3085 continue;
3086
3087 return drm_mode_duplicate(dev, ptr);
3088 }
3089
3090 return NULL;
3091 }
3092 EXPORT_SYMBOL(drm_mode_find_dmt);
3093
is_display_descriptor(const struct detailed_timing * descriptor,u8 type)3094 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
3095 {
3096 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3097 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
3098 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
3099
3100 return descriptor->pixel_clock == 0 &&
3101 descriptor->data.other_data.pad1 == 0 &&
3102 descriptor->data.other_data.type == type;
3103 }
3104
is_detailed_timing_descriptor(const struct detailed_timing * descriptor)3105 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
3106 {
3107 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3108
3109 return descriptor->pixel_clock != 0;
3110 }
3111
3112 typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
3113
3114 static void
cea_for_each_detailed_block(const u8 * ext,detailed_cb * cb,void * closure)3115 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3116 {
3117 int i, n;
3118 u8 d = ext[0x02];
3119 const u8 *det_base = ext + d;
3120
3121 if (d < 4 || d > 127)
3122 return;
3123
3124 n = (127 - d) / 18;
3125 for (i = 0; i < n; i++)
3126 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3127 }
3128
3129 static void
vtb_for_each_detailed_block(const u8 * ext,detailed_cb * cb,void * closure)3130 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3131 {
3132 unsigned int i, n = min((int)ext[0x02], 6);
3133 const u8 *det_base = ext + 5;
3134
3135 if (ext[0x01] != 1)
3136 return; /* unknown version */
3137
3138 for (i = 0; i < n; i++)
3139 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3140 }
3141
drm_for_each_detailed_block(const struct drm_edid * drm_edid,detailed_cb * cb,void * closure)3142 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
3143 detailed_cb *cb, void *closure)
3144 {
3145 struct drm_edid_iter edid_iter;
3146 const u8 *ext;
3147 int i;
3148
3149 if (!drm_edid)
3150 return;
3151
3152 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
3153 cb(&drm_edid->edid->detailed_timings[i], closure);
3154
3155 drm_edid_iter_begin(drm_edid, &edid_iter);
3156 drm_edid_iter_for_each(ext, &edid_iter) {
3157 switch (*ext) {
3158 case CEA_EXT:
3159 cea_for_each_detailed_block(ext, cb, closure);
3160 break;
3161 case VTB_EXT:
3162 vtb_for_each_detailed_block(ext, cb, closure);
3163 break;
3164 default:
3165 break;
3166 }
3167 }
3168 drm_edid_iter_end(&edid_iter);
3169 }
3170
3171 static void
is_rb(const struct detailed_timing * descriptor,void * data)3172 is_rb(const struct detailed_timing *descriptor, void *data)
3173 {
3174 bool *res = data;
3175
3176 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3177 return;
3178
3179 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3180 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
3181
3182 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
3183 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
3184 *res = true;
3185 }
3186
3187 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
3188 static bool
drm_monitor_supports_rb(const struct drm_edid * drm_edid)3189 drm_monitor_supports_rb(const struct drm_edid *drm_edid)
3190 {
3191 if (drm_edid->edid->revision >= 4) {
3192 bool ret = false;
3193
3194 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
3195 return ret;
3196 }
3197
3198 return drm_edid_is_digital(drm_edid);
3199 }
3200
3201 static void
find_gtf2(const struct detailed_timing * descriptor,void * data)3202 find_gtf2(const struct detailed_timing *descriptor, void *data)
3203 {
3204 const struct detailed_timing **res = data;
3205
3206 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3207 return;
3208
3209 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3210
3211 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
3212 *res = descriptor;
3213 }
3214
3215 /* Secondary GTF curve kicks in above some break frequency */
3216 static int
drm_gtf2_hbreak(const struct drm_edid * drm_edid)3217 drm_gtf2_hbreak(const struct drm_edid *drm_edid)
3218 {
3219 const struct detailed_timing *descriptor = NULL;
3220
3221 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3222
3223 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3224
3225 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
3226 }
3227
3228 static int
drm_gtf2_2c(const struct drm_edid * drm_edid)3229 drm_gtf2_2c(const struct drm_edid *drm_edid)
3230 {
3231 const struct detailed_timing *descriptor = NULL;
3232
3233 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3234
3235 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
3236
3237 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
3238 }
3239
3240 static int
drm_gtf2_m(const struct drm_edid * drm_edid)3241 drm_gtf2_m(const struct drm_edid *drm_edid)
3242 {
3243 const struct detailed_timing *descriptor = NULL;
3244
3245 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3246
3247 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3248
3249 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
3250 }
3251
3252 static int
drm_gtf2_k(const struct drm_edid * drm_edid)3253 drm_gtf2_k(const struct drm_edid *drm_edid)
3254 {
3255 const struct detailed_timing *descriptor = NULL;
3256
3257 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3258
3259 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3260
3261 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
3262 }
3263
3264 static int
drm_gtf2_2j(const struct drm_edid * drm_edid)3265 drm_gtf2_2j(const struct drm_edid *drm_edid)
3266 {
3267 const struct detailed_timing *descriptor = NULL;
3268
3269 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3270
3271 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
3272
3273 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
3274 }
3275
3276 static void
get_timing_level(const struct detailed_timing * descriptor,void * data)3277 get_timing_level(const struct detailed_timing *descriptor, void *data)
3278 {
3279 int *res = data;
3280
3281 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3282 return;
3283
3284 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3285
3286 switch (descriptor->data.other_data.data.range.flags) {
3287 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3288 *res = LEVEL_GTF;
3289 break;
3290 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3291 *res = LEVEL_GTF2;
3292 break;
3293 case DRM_EDID_CVT_SUPPORT_FLAG:
3294 *res = LEVEL_CVT;
3295 break;
3296 default:
3297 break;
3298 }
3299 }
3300
3301 /* Get standard timing level (CVT/GTF/DMT). */
standard_timing_level(const struct drm_edid * drm_edid)3302 static int standard_timing_level(const struct drm_edid *drm_edid)
3303 {
3304 const struct edid *edid = drm_edid->edid;
3305
3306 if (edid->revision >= 4) {
3307 /*
3308 * If the range descriptor doesn't
3309 * indicate otherwise default to CVT
3310 */
3311 int ret = LEVEL_CVT;
3312
3313 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
3314
3315 return ret;
3316 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
3317 return LEVEL_GTF2;
3318 } else if (edid->revision >= 2) {
3319 return LEVEL_GTF;
3320 } else {
3321 return LEVEL_DMT;
3322 }
3323 }
3324
3325 /*
3326 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3327 * monitors fill with ascii space (0x20) instead.
3328 */
3329 static int
bad_std_timing(u8 a,u8 b)3330 bad_std_timing(u8 a, u8 b)
3331 {
3332 return (a == 0x00 && b == 0x00) ||
3333 (a == 0x01 && b == 0x01) ||
3334 (a == 0x20 && b == 0x20);
3335 }
3336
drm_mode_hsync(const struct drm_display_mode * mode)3337 static int drm_mode_hsync(const struct drm_display_mode *mode)
3338 {
3339 if (mode->htotal <= 0)
3340 return 0;
3341
3342 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3343 }
3344
3345 static struct drm_display_mode *
drm_gtf2_mode(struct drm_device * dev,const struct drm_edid * drm_edid,int hsize,int vsize,int vrefresh_rate)3346 drm_gtf2_mode(struct drm_device *dev,
3347 const struct drm_edid *drm_edid,
3348 int hsize, int vsize, int vrefresh_rate)
3349 {
3350 struct drm_display_mode *mode;
3351
3352 /*
3353 * This is potentially wrong if there's ever a monitor with
3354 * more than one ranges section, each claiming a different
3355 * secondary GTF curve. Please don't do that.
3356 */
3357 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3358 if (!mode)
3359 return NULL;
3360
3361 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3362 drm_mode_destroy(dev, mode);
3363 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3364 vrefresh_rate, 0, 0,
3365 drm_gtf2_m(drm_edid),
3366 drm_gtf2_2c(drm_edid),
3367 drm_gtf2_k(drm_edid),
3368 drm_gtf2_2j(drm_edid));
3369 }
3370
3371 return mode;
3372 }
3373
3374 /*
3375 * Take the standard timing params (in this case width, aspect, and refresh)
3376 * and convert them into a real mode using CVT/GTF/DMT.
3377 */
drm_mode_std(struct drm_connector * connector,const struct drm_edid * drm_edid,const struct std_timing * t)3378 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3379 const struct drm_edid *drm_edid,
3380 const struct std_timing *t)
3381 {
3382 struct drm_device *dev = connector->dev;
3383 struct drm_display_mode *m, *mode = NULL;
3384 int hsize, vsize;
3385 int vrefresh_rate;
3386 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3387 >> EDID_TIMING_ASPECT_SHIFT;
3388 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3389 >> EDID_TIMING_VFREQ_SHIFT;
3390 int timing_level = standard_timing_level(drm_edid);
3391
3392 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3393 return NULL;
3394
3395 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3396 hsize = t->hsize * 8 + 248;
3397 /* vrefresh_rate = vfreq + 60 */
3398 vrefresh_rate = vfreq + 60;
3399 /* the vdisplay is calculated based on the aspect ratio */
3400 if (aspect_ratio == 0) {
3401 if (drm_edid->edid->revision < 3)
3402 vsize = hsize;
3403 else
3404 vsize = (hsize * 10) / 16;
3405 } else if (aspect_ratio == 1)
3406 vsize = (hsize * 3) / 4;
3407 else if (aspect_ratio == 2)
3408 vsize = (hsize * 4) / 5;
3409 else
3410 vsize = (hsize * 9) / 16;
3411
3412 /* HDTV hack, part 1 */
3413 if (vrefresh_rate == 60 &&
3414 ((hsize == 1360 && vsize == 765) ||
3415 (hsize == 1368 && vsize == 769))) {
3416 hsize = 1366;
3417 vsize = 768;
3418 }
3419
3420 /*
3421 * If this connector already has a mode for this size and refresh
3422 * rate (because it came from detailed or CVT info), use that
3423 * instead. This way we don't have to guess at interlace or
3424 * reduced blanking.
3425 */
3426 list_for_each_entry(m, &connector->probed_modes, head)
3427 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3428 drm_mode_vrefresh(m) == vrefresh_rate)
3429 return NULL;
3430
3431 /* HDTV hack, part 2 */
3432 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3433 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
3434 false);
3435 if (!mode)
3436 return NULL;
3437 mode->hdisplay = 1366;
3438 mode->hsync_start = mode->hsync_start - 1;
3439 mode->hsync_end = mode->hsync_end - 1;
3440 return mode;
3441 }
3442
3443 /* check whether it can be found in default mode table */
3444 if (drm_monitor_supports_rb(drm_edid)) {
3445 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3446 true);
3447 if (mode)
3448 return mode;
3449 }
3450 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
3451 if (mode)
3452 return mode;
3453
3454 /* okay, generate it */
3455 switch (timing_level) {
3456 case LEVEL_DMT:
3457 break;
3458 case LEVEL_GTF:
3459 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3460 break;
3461 case LEVEL_GTF2:
3462 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate);
3463 break;
3464 case LEVEL_CVT:
3465 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3466 false);
3467 break;
3468 }
3469 return mode;
3470 }
3471
3472 /*
3473 * EDID is delightfully ambiguous about how interlaced modes are to be
3474 * encoded. Our internal representation is of frame height, but some
3475 * HDTV detailed timings are encoded as field height.
3476 *
3477 * The format list here is from CEA, in frame size. Technically we
3478 * should be checking refresh rate too. Whatever.
3479 */
3480 static void
drm_mode_do_interlace_quirk(struct drm_display_mode * mode,const struct detailed_pixel_timing * pt)3481 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
3482 const struct detailed_pixel_timing *pt)
3483 {
3484 int i;
3485 static const struct {
3486 int w, h;
3487 } cea_interlaced[] = {
3488 { 1920, 1080 },
3489 { 720, 480 },
3490 { 1440, 480 },
3491 { 2880, 480 },
3492 { 720, 576 },
3493 { 1440, 576 },
3494 { 2880, 576 },
3495 };
3496
3497 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3498 return;
3499
3500 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
3501 if ((mode->hdisplay == cea_interlaced[i].w) &&
3502 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3503 mode->vdisplay *= 2;
3504 mode->vsync_start *= 2;
3505 mode->vsync_end *= 2;
3506 mode->vtotal *= 2;
3507 mode->vtotal |= 1;
3508 }
3509 }
3510
3511 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3512 }
3513
3514 /*
3515 * Create a new mode from an EDID detailed timing section. An EDID detailed
3516 * timing block contains enough info for us to create and return a new struct
3517 * drm_display_mode.
3518 */
drm_mode_detailed(struct drm_connector * connector,const struct drm_edid * drm_edid,const struct detailed_timing * timing)3519 static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector,
3520 const struct drm_edid *drm_edid,
3521 const struct detailed_timing *timing)
3522 {
3523 const struct drm_display_info *info = &connector->display_info;
3524 struct drm_device *dev = connector->dev;
3525 struct drm_display_mode *mode;
3526 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
3527 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3528 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3529 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3530 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
3531 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3532 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
3533 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
3534 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
3535
3536 /* ignore tiny modes */
3537 if (hactive < 64 || vactive < 64)
3538 return NULL;
3539
3540 if (pt->misc & DRM_EDID_PT_STEREO) {
3541 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n",
3542 connector->base.id, connector->name);
3543 return NULL;
3544 }
3545 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
3546 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n",
3547 connector->base.id, connector->name);
3548 }
3549
3550 /* it is incorrect if hsync/vsync width is zero */
3551 if (!hsync_pulse_width || !vsync_pulse_width) {
3552 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n",
3553 connector->base.id, connector->name);
3554 return NULL;
3555 }
3556
3557 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3558 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3559 if (!mode)
3560 return NULL;
3561
3562 goto set_size;
3563 }
3564
3565 mode = drm_mode_create(dev);
3566 if (!mode)
3567 return NULL;
3568
3569 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
3570 mode->clock = 1088 * 10;
3571 else
3572 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
3573
3574 mode->hdisplay = hactive;
3575 mode->hsync_start = mode->hdisplay + hsync_offset;
3576 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3577 mode->htotal = mode->hdisplay + hblank;
3578
3579 mode->vdisplay = vactive;
3580 mode->vsync_start = mode->vdisplay + vsync_offset;
3581 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3582 mode->vtotal = mode->vdisplay + vblank;
3583
3584 /* Some EDIDs have bogus h/vsync_end values */
3585 if (mode->hsync_end > mode->htotal) {
3586 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n",
3587 connector->base.id, connector->name,
3588 mode->hsync_end, mode->htotal);
3589 mode->hsync_end = mode->htotal;
3590 }
3591 if (mode->vsync_end > mode->vtotal) {
3592 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n",
3593 connector->base.id, connector->name,
3594 mode->vsync_end, mode->vtotal);
3595 mode->vsync_end = mode->vtotal;
3596 }
3597
3598 drm_mode_do_interlace_quirk(mode, pt);
3599
3600 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
3601 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3602 } else {
3603 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3604 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3605 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3606 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3607 }
3608
3609 set_size:
3610 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3611 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
3612
3613 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) {
3614 mode->width_mm *= 10;
3615 mode->height_mm *= 10;
3616 }
3617
3618 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
3619 mode->width_mm = drm_edid->edid->width_cm * 10;
3620 mode->height_mm = drm_edid->edid->height_cm * 10;
3621 }
3622
3623 mode->type = DRM_MODE_TYPE_DRIVER;
3624 drm_mode_set_name(mode);
3625
3626 return mode;
3627 }
3628
3629 static bool
mode_in_hsync_range(const struct drm_display_mode * mode,const struct edid * edid,const u8 * t)3630 mode_in_hsync_range(const struct drm_display_mode *mode,
3631 const struct edid *edid, const u8 *t)
3632 {
3633 int hsync, hmin, hmax;
3634
3635 hmin = t[7];
3636 if (edid->revision >= 4)
3637 hmin += ((t[4] & 0x04) ? 255 : 0);
3638 hmax = t[8];
3639 if (edid->revision >= 4)
3640 hmax += ((t[4] & 0x08) ? 255 : 0);
3641 hsync = drm_mode_hsync(mode);
3642
3643 return (hsync <= hmax && hsync >= hmin);
3644 }
3645
3646 static bool
mode_in_vsync_range(const struct drm_display_mode * mode,const struct edid * edid,const u8 * t)3647 mode_in_vsync_range(const struct drm_display_mode *mode,
3648 const struct edid *edid, const u8 *t)
3649 {
3650 int vsync, vmin, vmax;
3651
3652 vmin = t[5];
3653 if (edid->revision >= 4)
3654 vmin += ((t[4] & 0x01) ? 255 : 0);
3655 vmax = t[6];
3656 if (edid->revision >= 4)
3657 vmax += ((t[4] & 0x02) ? 255 : 0);
3658 vsync = drm_mode_vrefresh(mode);
3659
3660 return (vsync <= vmax && vsync >= vmin);
3661 }
3662
3663 static u32
range_pixel_clock(const struct edid * edid,const u8 * t)3664 range_pixel_clock(const struct edid *edid, const u8 *t)
3665 {
3666 /* unspecified */
3667 if (t[9] == 0 || t[9] == 255)
3668 return 0;
3669
3670 /* 1.4 with CVT support gives us real precision, yay */
3671 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3672 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3673
3674 /* 1.3 is pathetic, so fuzz up a bit */
3675 return t[9] * 10000 + 5001;
3676 }
3677
mode_in_range(const struct drm_display_mode * mode,const struct drm_edid * drm_edid,const struct detailed_timing * timing)3678 static bool mode_in_range(const struct drm_display_mode *mode,
3679 const struct drm_edid *drm_edid,
3680 const struct detailed_timing *timing)
3681 {
3682 const struct edid *edid = drm_edid->edid;
3683 u32 max_clock;
3684 const u8 *t = (const u8 *)timing;
3685
3686 if (!mode_in_hsync_range(mode, edid, t))
3687 return false;
3688
3689 if (!mode_in_vsync_range(mode, edid, t))
3690 return false;
3691
3692 max_clock = range_pixel_clock(edid, t);
3693 if (max_clock)
3694 if (mode->clock > max_clock)
3695 return false;
3696
3697 /* 1.4 max horizontal check */
3698 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3699 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3700 return false;
3701
3702 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
3703 return false;
3704
3705 return true;
3706 }
3707
valid_inferred_mode(const struct drm_connector * connector,const struct drm_display_mode * mode)3708 static bool valid_inferred_mode(const struct drm_connector *connector,
3709 const struct drm_display_mode *mode)
3710 {
3711 const struct drm_display_mode *m;
3712 bool ok = false;
3713
3714 list_for_each_entry(m, &connector->probed_modes, head) {
3715 if (mode->hdisplay == m->hdisplay &&
3716 mode->vdisplay == m->vdisplay &&
3717 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3718 return false; /* duplicated */
3719 if (mode->hdisplay <= m->hdisplay &&
3720 mode->vdisplay <= m->vdisplay)
3721 ok = true;
3722 }
3723 return ok;
3724 }
3725
drm_dmt_modes_for_range(struct drm_connector * connector,const struct drm_edid * drm_edid,const struct detailed_timing * timing)3726 static int drm_dmt_modes_for_range(struct drm_connector *connector,
3727 const struct drm_edid *drm_edid,
3728 const struct detailed_timing *timing)
3729 {
3730 int i, modes = 0;
3731 struct drm_display_mode *newmode;
3732 struct drm_device *dev = connector->dev;
3733
3734 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3735 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
3736 valid_inferred_mode(connector, drm_dmt_modes + i)) {
3737 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3738 if (newmode) {
3739 drm_mode_probed_add(connector, newmode);
3740 modes++;
3741 }
3742 }
3743 }
3744
3745 return modes;
3746 }
3747
3748 /* fix up 1366x768 mode from 1368x768;
3749 * GFT/CVT can't express 1366 width which isn't dividable by 8
3750 */
drm_mode_fixup_1366x768(struct drm_display_mode * mode)3751 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3752 {
3753 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3754 mode->hdisplay = 1366;
3755 mode->hsync_start--;
3756 mode->hsync_end--;
3757 drm_mode_set_name(mode);
3758 }
3759 }
3760
drm_gtf_modes_for_range(struct drm_connector * connector,const struct drm_edid * drm_edid,const struct detailed_timing * timing)3761 static int drm_gtf_modes_for_range(struct drm_connector *connector,
3762 const struct drm_edid *drm_edid,
3763 const struct detailed_timing *timing)
3764 {
3765 int i, modes = 0;
3766 struct drm_display_mode *newmode;
3767 struct drm_device *dev = connector->dev;
3768
3769 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3770 const struct minimode *m = &extra_modes[i];
3771
3772 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3773 if (!newmode)
3774 return modes;
3775
3776 drm_mode_fixup_1366x768(newmode);
3777 if (!mode_in_range(newmode, drm_edid, timing) ||
3778 !valid_inferred_mode(connector, newmode)) {
3779 drm_mode_destroy(dev, newmode);
3780 continue;
3781 }
3782
3783 drm_mode_probed_add(connector, newmode);
3784 modes++;
3785 }
3786
3787 return modes;
3788 }
3789
drm_gtf2_modes_for_range(struct drm_connector * connector,const struct drm_edid * drm_edid,const struct detailed_timing * timing)3790 static int drm_gtf2_modes_for_range(struct drm_connector *connector,
3791 const struct drm_edid *drm_edid,
3792 const struct detailed_timing *timing)
3793 {
3794 int i, modes = 0;
3795 struct drm_display_mode *newmode;
3796 struct drm_device *dev = connector->dev;
3797
3798 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3799 const struct minimode *m = &extra_modes[i];
3800
3801 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
3802 if (!newmode)
3803 return modes;
3804
3805 drm_mode_fixup_1366x768(newmode);
3806 if (!mode_in_range(newmode, drm_edid, timing) ||
3807 !valid_inferred_mode(connector, newmode)) {
3808 drm_mode_destroy(dev, newmode);
3809 continue;
3810 }
3811
3812 drm_mode_probed_add(connector, newmode);
3813 modes++;
3814 }
3815
3816 return modes;
3817 }
3818
drm_cvt_modes_for_range(struct drm_connector * connector,const struct drm_edid * drm_edid,const struct detailed_timing * timing)3819 static int drm_cvt_modes_for_range(struct drm_connector *connector,
3820 const struct drm_edid *drm_edid,
3821 const struct detailed_timing *timing)
3822 {
3823 int i, modes = 0;
3824 struct drm_display_mode *newmode;
3825 struct drm_device *dev = connector->dev;
3826 bool rb = drm_monitor_supports_rb(drm_edid);
3827
3828 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3829 const struct minimode *m = &extra_modes[i];
3830
3831 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3832 if (!newmode)
3833 return modes;
3834
3835 drm_mode_fixup_1366x768(newmode);
3836 if (!mode_in_range(newmode, drm_edid, timing) ||
3837 !valid_inferred_mode(connector, newmode)) {
3838 drm_mode_destroy(dev, newmode);
3839 continue;
3840 }
3841
3842 drm_mode_probed_add(connector, newmode);
3843 modes++;
3844 }
3845
3846 return modes;
3847 }
3848
3849 static void
do_inferred_modes(const struct detailed_timing * timing,void * c)3850 do_inferred_modes(const struct detailed_timing *timing, void *c)
3851 {
3852 struct detailed_mode_closure *closure = c;
3853 const struct detailed_non_pixel *data = &timing->data.other_data;
3854 const struct detailed_data_monitor_range *range = &data->data.range;
3855
3856 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3857 return;
3858
3859 closure->modes += drm_dmt_modes_for_range(closure->connector,
3860 closure->drm_edid,
3861 timing);
3862
3863 if (closure->drm_edid->edid->revision < 2)
3864 return; /* GTF not defined yet */
3865
3866 switch (range->flags) {
3867 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3868 closure->modes += drm_gtf2_modes_for_range(closure->connector,
3869 closure->drm_edid,
3870 timing);
3871 break;
3872 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3873 closure->modes += drm_gtf_modes_for_range(closure->connector,
3874 closure->drm_edid,
3875 timing);
3876 break;
3877 case DRM_EDID_CVT_SUPPORT_FLAG:
3878 if (closure->drm_edid->edid->revision < 4)
3879 break;
3880
3881 closure->modes += drm_cvt_modes_for_range(closure->connector,
3882 closure->drm_edid,
3883 timing);
3884 break;
3885 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
3886 default:
3887 break;
3888 }
3889 }
3890
add_inferred_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)3891 static int add_inferred_modes(struct drm_connector *connector,
3892 const struct drm_edid *drm_edid)
3893 {
3894 struct detailed_mode_closure closure = {
3895 .connector = connector,
3896 .drm_edid = drm_edid,
3897 };
3898
3899 if (drm_edid->edid->revision >= 1)
3900 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
3901
3902 return closure.modes;
3903 }
3904
3905 static int
drm_est3_modes(struct drm_connector * connector,const struct detailed_timing * timing)3906 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3907 {
3908 int i, j, m, modes = 0;
3909 struct drm_display_mode *mode;
3910 const u8 *est = ((const u8 *)timing) + 6;
3911
3912 for (i = 0; i < 6; i++) {
3913 for (j = 7; j >= 0; j--) {
3914 m = (i * 8) + (7 - j);
3915 if (m >= ARRAY_SIZE(est3_modes))
3916 break;
3917 if (est[i] & (1 << j)) {
3918 mode = drm_mode_find_dmt(connector->dev,
3919 est3_modes[m].w,
3920 est3_modes[m].h,
3921 est3_modes[m].r,
3922 est3_modes[m].rb);
3923 if (mode) {
3924 drm_mode_probed_add(connector, mode);
3925 modes++;
3926 }
3927 }
3928 }
3929 }
3930
3931 return modes;
3932 }
3933
3934 static void
do_established_modes(const struct detailed_timing * timing,void * c)3935 do_established_modes(const struct detailed_timing *timing, void *c)
3936 {
3937 struct detailed_mode_closure *closure = c;
3938
3939 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3940 return;
3941
3942 closure->modes += drm_est3_modes(closure->connector, timing);
3943 }
3944
3945 /*
3946 * Get established modes from EDID and add them. Each EDID block contains a
3947 * bitmap of the supported "established modes" list (defined above). Tease them
3948 * out and add them to the global modes list.
3949 */
add_established_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)3950 static int add_established_modes(struct drm_connector *connector,
3951 const struct drm_edid *drm_edid)
3952 {
3953 struct drm_device *dev = connector->dev;
3954 const struct edid *edid = drm_edid->edid;
3955 unsigned long est_bits = edid->established_timings.t1 |
3956 (edid->established_timings.t2 << 8) |
3957 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3958 int i, modes = 0;
3959 struct detailed_mode_closure closure = {
3960 .connector = connector,
3961 .drm_edid = drm_edid,
3962 };
3963
3964 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3965 if (est_bits & (1<<i)) {
3966 struct drm_display_mode *newmode;
3967
3968 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3969 if (newmode) {
3970 drm_mode_probed_add(connector, newmode);
3971 modes++;
3972 }
3973 }
3974 }
3975
3976 if (edid->revision >= 1)
3977 drm_for_each_detailed_block(drm_edid, do_established_modes,
3978 &closure);
3979
3980 return modes + closure.modes;
3981 }
3982
3983 static void
do_standard_modes(const struct detailed_timing * timing,void * c)3984 do_standard_modes(const struct detailed_timing *timing, void *c)
3985 {
3986 struct detailed_mode_closure *closure = c;
3987 const struct detailed_non_pixel *data = &timing->data.other_data;
3988 struct drm_connector *connector = closure->connector;
3989 int i;
3990
3991 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3992 return;
3993
3994 for (i = 0; i < 6; i++) {
3995 const struct std_timing *std = &data->data.timings[i];
3996 struct drm_display_mode *newmode;
3997
3998 newmode = drm_mode_std(connector, closure->drm_edid, std);
3999 if (newmode) {
4000 drm_mode_probed_add(connector, newmode);
4001 closure->modes++;
4002 }
4003 }
4004 }
4005
4006 /*
4007 * Get standard modes from EDID and add them. Standard modes can be calculated
4008 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
4009 * add them to the list.
4010 */
add_standard_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)4011 static int add_standard_modes(struct drm_connector *connector,
4012 const struct drm_edid *drm_edid)
4013 {
4014 int i, modes = 0;
4015 struct detailed_mode_closure closure = {
4016 .connector = connector,
4017 .drm_edid = drm_edid,
4018 };
4019
4020 for (i = 0; i < EDID_STD_TIMINGS; i++) {
4021 struct drm_display_mode *newmode;
4022
4023 newmode = drm_mode_std(connector, drm_edid,
4024 &drm_edid->edid->standard_timings[i]);
4025 if (newmode) {
4026 drm_mode_probed_add(connector, newmode);
4027 modes++;
4028 }
4029 }
4030
4031 if (drm_edid->edid->revision >= 1)
4032 drm_for_each_detailed_block(drm_edid, do_standard_modes,
4033 &closure);
4034
4035 /* XXX should also look for standard codes in VTB blocks */
4036
4037 return modes + closure.modes;
4038 }
4039
drm_cvt_modes(struct drm_connector * connector,const struct detailed_timing * timing)4040 static int drm_cvt_modes(struct drm_connector *connector,
4041 const struct detailed_timing *timing)
4042 {
4043 int i, j, modes = 0;
4044 struct drm_display_mode *newmode;
4045 struct drm_device *dev = connector->dev;
4046 const struct cvt_timing *cvt;
4047 static const int rates[] = { 60, 85, 75, 60, 50 };
4048 const u8 empty[3] = { 0, 0, 0 };
4049
4050 for (i = 0; i < 4; i++) {
4051 int width, height;
4052
4053 cvt = &(timing->data.other_data.data.cvt[i]);
4054
4055 if (!memcmp(cvt->code, empty, 3))
4056 continue;
4057
4058 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
4059 switch (cvt->code[1] & 0x0c) {
4060 /* default - because compiler doesn't see that we've enumerated all cases */
4061 default:
4062 case 0x00:
4063 width = height * 4 / 3;
4064 break;
4065 case 0x04:
4066 width = height * 16 / 9;
4067 break;
4068 case 0x08:
4069 width = height * 16 / 10;
4070 break;
4071 case 0x0c:
4072 width = height * 15 / 9;
4073 break;
4074 }
4075
4076 for (j = 1; j < 5; j++) {
4077 if (cvt->code[2] & (1 << j)) {
4078 newmode = drm_cvt_mode(dev, width, height,
4079 rates[j], j == 0,
4080 false, false);
4081 if (newmode) {
4082 drm_mode_probed_add(connector, newmode);
4083 modes++;
4084 }
4085 }
4086 }
4087 }
4088
4089 return modes;
4090 }
4091
4092 static void
do_cvt_mode(const struct detailed_timing * timing,void * c)4093 do_cvt_mode(const struct detailed_timing *timing, void *c)
4094 {
4095 struct detailed_mode_closure *closure = c;
4096
4097 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
4098 return;
4099
4100 closure->modes += drm_cvt_modes(closure->connector, timing);
4101 }
4102
4103 static int
add_cvt_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)4104 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
4105 {
4106 struct detailed_mode_closure closure = {
4107 .connector = connector,
4108 .drm_edid = drm_edid,
4109 };
4110
4111 if (drm_edid->edid->revision >= 3)
4112 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
4113
4114 /* XXX should also look for CVT codes in VTB blocks */
4115
4116 return closure.modes;
4117 }
4118
4119 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
4120 struct drm_display_mode *mode);
4121
4122 static void
do_detailed_mode(const struct detailed_timing * timing,void * c)4123 do_detailed_mode(const struct detailed_timing *timing, void *c)
4124 {
4125 struct detailed_mode_closure *closure = c;
4126 struct drm_display_mode *newmode;
4127
4128 if (!is_detailed_timing_descriptor(timing))
4129 return;
4130
4131 newmode = drm_mode_detailed(closure->connector,
4132 closure->drm_edid, timing);
4133 if (!newmode)
4134 return;
4135
4136 if (closure->preferred)
4137 newmode->type |= DRM_MODE_TYPE_PREFERRED;
4138
4139 /*
4140 * Detailed modes are limited to 10kHz pixel clock resolution,
4141 * so fix up anything that looks like CEA/HDMI mode, but the clock
4142 * is just slightly off.
4143 */
4144 fixup_detailed_cea_mode_clock(closure->connector, newmode);
4145
4146 drm_mode_probed_add(closure->connector, newmode);
4147 closure->modes++;
4148 closure->preferred = false;
4149 }
4150
4151 /*
4152 * add_detailed_modes - Add modes from detailed timings
4153 * @connector: attached connector
4154 * @drm_edid: EDID block to scan
4155 */
add_detailed_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)4156 static int add_detailed_modes(struct drm_connector *connector,
4157 const struct drm_edid *drm_edid)
4158 {
4159 struct detailed_mode_closure closure = {
4160 .connector = connector,
4161 .drm_edid = drm_edid,
4162 };
4163
4164 if (drm_edid->edid->revision >= 4)
4165 closure.preferred = true; /* first detailed timing is always preferred */
4166 else
4167 closure.preferred =
4168 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING;
4169
4170 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
4171
4172 return closure.modes;
4173 }
4174
4175 /* CTA-861-H Table 60 - CTA Tag Codes */
4176 #define CTA_DB_AUDIO 1
4177 #define CTA_DB_VIDEO 2
4178 #define CTA_DB_VENDOR 3
4179 #define CTA_DB_SPEAKER 4
4180 #define CTA_DB_EXTENDED_TAG 7
4181
4182 /* CTA-861-H Table 62 - CTA Extended Tag Codes */
4183 #define CTA_EXT_DB_VIDEO_CAP 0
4184 #define CTA_EXT_DB_VENDOR 1
4185 #define CTA_EXT_DB_HDR_STATIC_METADATA 6
4186 #define CTA_EXT_DB_420_VIDEO_DATA 14
4187 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
4188 #define CTA_EXT_DB_HF_EEODB 0x78
4189 #define CTA_EXT_DB_HF_SCDB 0x79
4190
4191 #define EDID_BASIC_AUDIO (1 << 6)
4192 #define EDID_CEA_YCRCB444 (1 << 5)
4193 #define EDID_CEA_YCRCB422 (1 << 4)
4194 #define EDID_CEA_VCDB_QS (1 << 6)
4195
4196 /*
4197 * Search EDID for CEA extension block.
4198 *
4199 * FIXME: Prefer not returning pointers to raw EDID data.
4200 */
drm_edid_find_extension(const struct drm_edid * drm_edid,int ext_id,int * ext_index)4201 const u8 *drm_edid_find_extension(const struct drm_edid *drm_edid,
4202 int ext_id, int *ext_index)
4203 {
4204 const u8 *edid_ext = NULL;
4205 int i;
4206
4207 /* No EDID or EDID extensions */
4208 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
4209 return NULL;
4210
4211 /* Find CEA extension */
4212 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
4213 edid_ext = drm_edid_extension_block_data(drm_edid, i);
4214 if (edid_block_tag(edid_ext) == ext_id)
4215 break;
4216 }
4217
4218 if (i >= drm_edid_extension_block_count(drm_edid))
4219 return NULL;
4220
4221 *ext_index = i + 1;
4222
4223 return edid_ext;
4224 }
4225
4226 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
drm_edid_has_cta_extension(const struct drm_edid * drm_edid)4227 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
4228 {
4229 const struct displayid_block *block;
4230 struct displayid_iter iter;
4231 struct drm_edid_iter edid_iter;
4232 const u8 *ext;
4233 bool found = false;
4234
4235 /* Look for a top level CEA extension block */
4236 drm_edid_iter_begin(drm_edid, &edid_iter);
4237 drm_edid_iter_for_each(ext, &edid_iter) {
4238 if (ext[0] == CEA_EXT) {
4239 found = true;
4240 break;
4241 }
4242 }
4243 drm_edid_iter_end(&edid_iter);
4244
4245 if (found)
4246 return true;
4247
4248 /* CEA blocks can also be found embedded in a DisplayID block */
4249 displayid_iter_edid_begin(drm_edid, &iter);
4250 displayid_iter_for_each(block, &iter) {
4251 if (block->tag == DATA_BLOCK_CTA) {
4252 found = true;
4253 break;
4254 }
4255 }
4256 displayid_iter_end(&iter);
4257
4258 return found;
4259 }
4260
cea_mode_for_vic(u8 vic)4261 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
4262 {
4263 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
4264 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
4265
4266 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
4267 return &edid_cea_modes_1[vic - 1];
4268 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
4269 return &edid_cea_modes_193[vic - 193];
4270 return NULL;
4271 }
4272
cea_num_vics(void)4273 static u8 cea_num_vics(void)
4274 {
4275 return 193 + ARRAY_SIZE(edid_cea_modes_193);
4276 }
4277
cea_next_vic(u8 vic)4278 static u8 cea_next_vic(u8 vic)
4279 {
4280 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
4281 vic = 193;
4282 return vic;
4283 }
4284
4285 /*
4286 * Calculate the alternate clock for the CEA mode
4287 * (60Hz vs. 59.94Hz etc.)
4288 */
4289 static unsigned int
cea_mode_alternate_clock(const struct drm_display_mode * cea_mode)4290 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4291 {
4292 unsigned int clock = cea_mode->clock;
4293
4294 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
4295 return clock;
4296
4297 /*
4298 * edid_cea_modes contains the 59.94Hz
4299 * variant for 240 and 480 line modes,
4300 * and the 60Hz variant otherwise.
4301 */
4302 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
4303 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
4304 else
4305 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
4306
4307 return clock;
4308 }
4309
4310 static bool
cea_mode_alternate_timings(u8 vic,struct drm_display_mode * mode)4311 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4312 {
4313 /*
4314 * For certain VICs the spec allows the vertical
4315 * front porch to vary by one or two lines.
4316 *
4317 * cea_modes[] stores the variant with the shortest
4318 * vertical front porch. We can adjust the mode to
4319 * get the other variants by simply increasing the
4320 * vertical front porch length.
4321 */
4322 #ifdef notyet
4323 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4324 cea_mode_for_vic(9)->vtotal != 262 ||
4325 cea_mode_for_vic(12)->vtotal != 262 ||
4326 cea_mode_for_vic(13)->vtotal != 262 ||
4327 cea_mode_for_vic(23)->vtotal != 312 ||
4328 cea_mode_for_vic(24)->vtotal != 312 ||
4329 cea_mode_for_vic(27)->vtotal != 312 ||
4330 cea_mode_for_vic(28)->vtotal != 312);
4331 #endif
4332
4333 if (((vic == 8 || vic == 9 ||
4334 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4335 ((vic == 23 || vic == 24 ||
4336 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4337 mode->vsync_start++;
4338 mode->vsync_end++;
4339 mode->vtotal++;
4340
4341 return true;
4342 }
4343
4344 return false;
4345 }
4346
drm_match_cea_mode_clock_tolerance(const struct drm_display_mode * to_match,unsigned int clock_tolerance)4347 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4348 unsigned int clock_tolerance)
4349 {
4350 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4351 u8 vic;
4352
4353 if (!to_match->clock)
4354 return 0;
4355
4356 if (to_match->picture_aspect_ratio)
4357 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4358
4359 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4360 struct drm_display_mode cea_mode;
4361 unsigned int clock1, clock2;
4362
4363 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4364
4365 /* Check both 60Hz and 59.94Hz */
4366 clock1 = cea_mode.clock;
4367 clock2 = cea_mode_alternate_clock(&cea_mode);
4368
4369 if (abs(to_match->clock - clock1) > clock_tolerance &&
4370 abs(to_match->clock - clock2) > clock_tolerance)
4371 continue;
4372
4373 do {
4374 if (drm_mode_match(to_match, &cea_mode, match_flags))
4375 return vic;
4376 } while (cea_mode_alternate_timings(vic, &cea_mode));
4377 }
4378
4379 return 0;
4380 }
4381
4382 /**
4383 * drm_match_cea_mode - look for a CEA mode matching given mode
4384 * @to_match: display mode
4385 *
4386 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
4387 * mode.
4388 */
drm_match_cea_mode(const struct drm_display_mode * to_match)4389 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
4390 {
4391 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4392 u8 vic;
4393
4394 if (!to_match->clock)
4395 return 0;
4396
4397 if (to_match->picture_aspect_ratio)
4398 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4399
4400 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4401 struct drm_display_mode cea_mode;
4402 unsigned int clock1, clock2;
4403
4404 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4405
4406 /* Check both 60Hz and 59.94Hz */
4407 clock1 = cea_mode.clock;
4408 clock2 = cea_mode_alternate_clock(&cea_mode);
4409
4410 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4411 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4412 continue;
4413
4414 do {
4415 if (drm_mode_match(to_match, &cea_mode, match_flags))
4416 return vic;
4417 } while (cea_mode_alternate_timings(vic, &cea_mode));
4418 }
4419
4420 return 0;
4421 }
4422 EXPORT_SYMBOL(drm_match_cea_mode);
4423
drm_valid_cea_vic(u8 vic)4424 static bool drm_valid_cea_vic(u8 vic)
4425 {
4426 return cea_mode_for_vic(vic) != NULL;
4427 }
4428
drm_get_cea_aspect_ratio(const u8 video_code)4429 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
4430 {
4431 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4432
4433 if (mode)
4434 return mode->picture_aspect_ratio;
4435
4436 return HDMI_PICTURE_ASPECT_NONE;
4437 }
4438
drm_get_hdmi_aspect_ratio(const u8 video_code)4439 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4440 {
4441 return edid_4k_modes[video_code].picture_aspect_ratio;
4442 }
4443
4444 /*
4445 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4446 * specific block).
4447 */
4448 static unsigned int
hdmi_mode_alternate_clock(const struct drm_display_mode * hdmi_mode)4449 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4450 {
4451 return cea_mode_alternate_clock(hdmi_mode);
4452 }
4453
drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode * to_match,unsigned int clock_tolerance)4454 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4455 unsigned int clock_tolerance)
4456 {
4457 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4458 u8 vic;
4459
4460 if (!to_match->clock)
4461 return 0;
4462
4463 if (to_match->picture_aspect_ratio)
4464 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4465
4466 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4467 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4468 unsigned int clock1, clock2;
4469
4470 /* Make sure to also match alternate clocks */
4471 clock1 = hdmi_mode->clock;
4472 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4473
4474 if (abs(to_match->clock - clock1) > clock_tolerance &&
4475 abs(to_match->clock - clock2) > clock_tolerance)
4476 continue;
4477
4478 if (drm_mode_match(to_match, hdmi_mode, match_flags))
4479 return vic;
4480 }
4481
4482 return 0;
4483 }
4484
4485 /*
4486 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4487 * @to_match: display mode
4488 *
4489 * An HDMI mode is one defined in the HDMI vendor specific block.
4490 *
4491 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4492 */
drm_match_hdmi_mode(const struct drm_display_mode * to_match)4493 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4494 {
4495 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4496 u8 vic;
4497
4498 if (!to_match->clock)
4499 return 0;
4500
4501 if (to_match->picture_aspect_ratio)
4502 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4503
4504 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4505 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4506 unsigned int clock1, clock2;
4507
4508 /* Make sure to also match alternate clocks */
4509 clock1 = hdmi_mode->clock;
4510 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4511
4512 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4513 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4514 drm_mode_match(to_match, hdmi_mode, match_flags))
4515 return vic;
4516 }
4517 return 0;
4518 }
4519
drm_valid_hdmi_vic(u8 vic)4520 static bool drm_valid_hdmi_vic(u8 vic)
4521 {
4522 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4523 }
4524
add_alternate_cea_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)4525 static int add_alternate_cea_modes(struct drm_connector *connector,
4526 const struct drm_edid *drm_edid)
4527 {
4528 struct drm_device *dev = connector->dev;
4529 struct drm_display_mode *mode, *tmp;
4530 DRM_LIST_HEAD(list);
4531 int modes = 0;
4532
4533 /* Don't add CTA modes if the CTA extension block is missing */
4534 if (!drm_edid_has_cta_extension(drm_edid))
4535 return 0;
4536
4537 /*
4538 * Go through all probed modes and create a new mode
4539 * with the alternate clock for certain CEA modes.
4540 */
4541 list_for_each_entry(mode, &connector->probed_modes, head) {
4542 const struct drm_display_mode *cea_mode = NULL;
4543 struct drm_display_mode *newmode;
4544 u8 vic = drm_match_cea_mode(mode);
4545 unsigned int clock1, clock2;
4546
4547 if (drm_valid_cea_vic(vic)) {
4548 cea_mode = cea_mode_for_vic(vic);
4549 clock2 = cea_mode_alternate_clock(cea_mode);
4550 } else {
4551 vic = drm_match_hdmi_mode(mode);
4552 if (drm_valid_hdmi_vic(vic)) {
4553 cea_mode = &edid_4k_modes[vic];
4554 clock2 = hdmi_mode_alternate_clock(cea_mode);
4555 }
4556 }
4557
4558 if (!cea_mode)
4559 continue;
4560
4561 clock1 = cea_mode->clock;
4562
4563 if (clock1 == clock2)
4564 continue;
4565
4566 if (mode->clock != clock1 && mode->clock != clock2)
4567 continue;
4568
4569 newmode = drm_mode_duplicate(dev, cea_mode);
4570 if (!newmode)
4571 continue;
4572
4573 /* Carry over the stereo flags */
4574 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4575
4576 /*
4577 * The current mode could be either variant. Make
4578 * sure to pick the "other" clock for the new mode.
4579 */
4580 if (mode->clock != clock1)
4581 newmode->clock = clock1;
4582 else
4583 newmode->clock = clock2;
4584
4585 list_add_tail(&newmode->head, &list);
4586 }
4587
4588 list_for_each_entry_safe(mode, tmp, &list, head) {
4589 list_del(&mode->head);
4590 drm_mode_probed_add(connector, mode);
4591 modes++;
4592 }
4593
4594 return modes;
4595 }
4596
svd_to_vic(u8 svd)4597 static u8 svd_to_vic(u8 svd)
4598 {
4599 /* 0-6 bit vic, 7th bit native mode indicator */
4600 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4601 return svd & 127;
4602
4603 return svd;
4604 }
4605
4606 /*
4607 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in
4608 * the EDID, or NULL on errors.
4609 */
4610 static struct drm_display_mode *
drm_display_mode_from_vic_index(struct drm_connector * connector,int vic_index)4611 drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index)
4612 {
4613 const struct drm_display_info *info = &connector->display_info;
4614 struct drm_device *dev = connector->dev;
4615
4616 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index])
4617 return NULL;
4618
4619 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]);
4620 }
4621
4622 /*
4623 * do_y420vdb_modes - Parse YCBCR 420 only modes
4624 * @connector: connector corresponding to the HDMI sink
4625 * @svds: start of the data block of CEA YCBCR 420 VDB
4626 * @len: length of the CEA YCBCR 420 VDB
4627 *
4628 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4629 * which contains modes which can be supported in YCBCR 420
4630 * output format only.
4631 */
do_y420vdb_modes(struct drm_connector * connector,const u8 * svds,u8 svds_len)4632 static int do_y420vdb_modes(struct drm_connector *connector,
4633 const u8 *svds, u8 svds_len)
4634 {
4635 struct drm_device *dev = connector->dev;
4636 int modes = 0, i;
4637
4638 for (i = 0; i < svds_len; i++) {
4639 u8 vic = svd_to_vic(svds[i]);
4640 struct drm_display_mode *newmode;
4641
4642 if (!drm_valid_cea_vic(vic))
4643 continue;
4644
4645 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4646 if (!newmode)
4647 break;
4648 drm_mode_probed_add(connector, newmode);
4649 modes++;
4650 }
4651
4652 return modes;
4653 }
4654
4655 /**
4656 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4657 * @dev: DRM device
4658 * @video_code: CEA VIC of the mode
4659 *
4660 * Creates a new mode matching the specified CEA VIC.
4661 *
4662 * Returns: A new drm_display_mode on success or NULL on failure
4663 */
4664 struct drm_display_mode *
drm_display_mode_from_cea_vic(struct drm_device * dev,u8 video_code)4665 drm_display_mode_from_cea_vic(struct drm_device *dev,
4666 u8 video_code)
4667 {
4668 const struct drm_display_mode *cea_mode;
4669 struct drm_display_mode *newmode;
4670
4671 cea_mode = cea_mode_for_vic(video_code);
4672 if (!cea_mode)
4673 return NULL;
4674
4675 newmode = drm_mode_duplicate(dev, cea_mode);
4676 if (!newmode)
4677 return NULL;
4678
4679 return newmode;
4680 }
4681 EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4682
4683 /* Add modes based on VICs parsed in parse_cta_vdb() */
add_cta_vdb_modes(struct drm_connector * connector)4684 static int add_cta_vdb_modes(struct drm_connector *connector)
4685 {
4686 const struct drm_display_info *info = &connector->display_info;
4687 int i, modes = 0;
4688
4689 if (!info->vics)
4690 return 0;
4691
4692 for (i = 0; i < info->vics_len; i++) {
4693 struct drm_display_mode *mode;
4694
4695 mode = drm_display_mode_from_vic_index(connector, i);
4696 if (mode) {
4697 drm_mode_probed_add(connector, mode);
4698 modes++;
4699 }
4700 }
4701
4702 return modes;
4703 }
4704
4705 struct stereo_mandatory_mode {
4706 int width, height, vrefresh;
4707 unsigned int flags;
4708 };
4709
4710 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4711 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4712 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4713 { 1920, 1080, 50,
4714 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4715 { 1920, 1080, 60,
4716 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4717 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4718 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4719 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4720 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4721 };
4722
4723 static bool
stereo_match_mandatory(const struct drm_display_mode * mode,const struct stereo_mandatory_mode * stereo_mode)4724 stereo_match_mandatory(const struct drm_display_mode *mode,
4725 const struct stereo_mandatory_mode *stereo_mode)
4726 {
4727 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4728
4729 return mode->hdisplay == stereo_mode->width &&
4730 mode->vdisplay == stereo_mode->height &&
4731 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4732 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4733 }
4734
add_hdmi_mandatory_stereo_modes(struct drm_connector * connector)4735 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4736 {
4737 struct drm_device *dev = connector->dev;
4738 const struct drm_display_mode *mode;
4739 struct list_head stereo_modes;
4740 int modes = 0, i;
4741
4742 INIT_LIST_HEAD(&stereo_modes);
4743
4744 list_for_each_entry(mode, &connector->probed_modes, head) {
4745 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4746 const struct stereo_mandatory_mode *mandatory;
4747 struct drm_display_mode *new_mode;
4748
4749 if (!stereo_match_mandatory(mode,
4750 &stereo_mandatory_modes[i]))
4751 continue;
4752
4753 mandatory = &stereo_mandatory_modes[i];
4754 new_mode = drm_mode_duplicate(dev, mode);
4755 if (!new_mode)
4756 continue;
4757
4758 new_mode->flags |= mandatory->flags;
4759 list_add_tail(&new_mode->head, &stereo_modes);
4760 modes++;
4761 }
4762 }
4763
4764 list_splice_tail(&stereo_modes, &connector->probed_modes);
4765
4766 return modes;
4767 }
4768
add_hdmi_mode(struct drm_connector * connector,u8 vic)4769 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4770 {
4771 struct drm_device *dev = connector->dev;
4772 struct drm_display_mode *newmode;
4773
4774 if (!drm_valid_hdmi_vic(vic)) {
4775 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n",
4776 connector->base.id, connector->name, vic);
4777 return 0;
4778 }
4779
4780 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4781 if (!newmode)
4782 return 0;
4783
4784 drm_mode_probed_add(connector, newmode);
4785
4786 return 1;
4787 }
4788
add_3d_struct_modes(struct drm_connector * connector,u16 structure,int vic_index)4789 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4790 int vic_index)
4791 {
4792 struct drm_display_mode *newmode;
4793 int modes = 0;
4794
4795 if (structure & (1 << 0)) {
4796 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4797 if (newmode) {
4798 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4799 drm_mode_probed_add(connector, newmode);
4800 modes++;
4801 }
4802 }
4803 if (structure & (1 << 6)) {
4804 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4805 if (newmode) {
4806 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4807 drm_mode_probed_add(connector, newmode);
4808 modes++;
4809 }
4810 }
4811 if (structure & (1 << 8)) {
4812 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4813 if (newmode) {
4814 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4815 drm_mode_probed_add(connector, newmode);
4816 modes++;
4817 }
4818 }
4819
4820 return modes;
4821 }
4822
hdmi_vsdb_latency_present(const u8 * db)4823 static bool hdmi_vsdb_latency_present(const u8 *db)
4824 {
4825 return db[8] & BIT(7);
4826 }
4827
hdmi_vsdb_i_latency_present(const u8 * db)4828 static bool hdmi_vsdb_i_latency_present(const u8 *db)
4829 {
4830 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6);
4831 }
4832
hdmi_vsdb_latency_length(const u8 * db)4833 static int hdmi_vsdb_latency_length(const u8 *db)
4834 {
4835 if (hdmi_vsdb_i_latency_present(db))
4836 return 4;
4837 else if (hdmi_vsdb_latency_present(db))
4838 return 2;
4839 else
4840 return 0;
4841 }
4842
4843 /*
4844 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4845 * @connector: connector corresponding to the HDMI sink
4846 * @db: start of the CEA vendor specific block
4847 * @len: length of the CEA block payload, ie. one can access up to db[len]
4848 *
4849 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4850 * also adds the stereo 3d modes when applicable.
4851 */
4852 static int
do_hdmi_vsdb_modes(struct drm_connector * connector,const u8 * db,u8 len)4853 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len)
4854 {
4855 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4856 u8 vic_len, hdmi_3d_len = 0;
4857 u16 mask;
4858 u16 structure_all;
4859
4860 if (len < 8)
4861 goto out;
4862
4863 /* no HDMI_Video_Present */
4864 if (!(db[8] & (1 << 5)))
4865 goto out;
4866
4867 offset += hdmi_vsdb_latency_length(db);
4868
4869 /* the declared length is not long enough for the 2 first bytes
4870 * of additional video format capabilities */
4871 if (len < (8 + offset + 2))
4872 goto out;
4873
4874 /* 3D_Present */
4875 offset++;
4876 if (db[8 + offset] & (1 << 7)) {
4877 modes += add_hdmi_mandatory_stereo_modes(connector);
4878
4879 /* 3D_Multi_present */
4880 multi_present = (db[8 + offset] & 0x60) >> 5;
4881 }
4882
4883 offset++;
4884 vic_len = db[8 + offset] >> 5;
4885 hdmi_3d_len = db[8 + offset] & 0x1f;
4886
4887 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4888 u8 vic;
4889
4890 vic = db[9 + offset + i];
4891 modes += add_hdmi_mode(connector, vic);
4892 }
4893 offset += 1 + vic_len;
4894
4895 if (multi_present == 1)
4896 multi_len = 2;
4897 else if (multi_present == 2)
4898 multi_len = 4;
4899 else
4900 multi_len = 0;
4901
4902 if (len < (8 + offset + hdmi_3d_len - 1))
4903 goto out;
4904
4905 if (hdmi_3d_len < multi_len)
4906 goto out;
4907
4908 if (multi_present == 1 || multi_present == 2) {
4909 /* 3D_Structure_ALL */
4910 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4911
4912 /* check if 3D_MASK is present */
4913 if (multi_present == 2)
4914 mask = (db[10 + offset] << 8) | db[11 + offset];
4915 else
4916 mask = 0xffff;
4917
4918 for (i = 0; i < 16; i++) {
4919 if (mask & (1 << i))
4920 modes += add_3d_struct_modes(connector,
4921 structure_all, i);
4922 }
4923 }
4924
4925 offset += multi_len;
4926
4927 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4928 int vic_index;
4929 struct drm_display_mode *newmode = NULL;
4930 unsigned int newflag = 0;
4931 bool detail_present;
4932
4933 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4934
4935 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4936 break;
4937
4938 /* 2D_VIC_order_X */
4939 vic_index = db[8 + offset + i] >> 4;
4940
4941 /* 3D_Structure_X */
4942 switch (db[8 + offset + i] & 0x0f) {
4943 case 0:
4944 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4945 break;
4946 case 6:
4947 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4948 break;
4949 case 8:
4950 /* 3D_Detail_X */
4951 if ((db[9 + offset + i] >> 4) == 1)
4952 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4953 break;
4954 }
4955
4956 if (newflag != 0) {
4957 newmode = drm_display_mode_from_vic_index(connector,
4958 vic_index);
4959
4960 if (newmode) {
4961 newmode->flags |= newflag;
4962 drm_mode_probed_add(connector, newmode);
4963 modes++;
4964 }
4965 }
4966
4967 if (detail_present)
4968 i++;
4969 }
4970
4971 out:
4972 return modes;
4973 }
4974
4975 static int
cea_revision(const u8 * cea)4976 cea_revision(const u8 *cea)
4977 {
4978 /*
4979 * FIXME is this correct for the DispID variant?
4980 * The DispID spec doesn't really specify whether
4981 * this is the revision of the CEA extension or
4982 * the DispID CEA data block. And the only value
4983 * given as an example is 0.
4984 */
4985 return cea[1];
4986 }
4987
4988 /*
4989 * CTA Data Block iterator.
4990 *
4991 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4992 * CTA Data Blocks.
4993 *
4994 * struct cea_db *db:
4995 * struct cea_db_iter iter;
4996 *
4997 * cea_db_iter_edid_begin(edid, &iter);
4998 * cea_db_iter_for_each(db, &iter) {
4999 * // do stuff with db
5000 * }
5001 * cea_db_iter_end(&iter);
5002 */
5003 struct cea_db_iter {
5004 struct drm_edid_iter edid_iter;
5005 struct displayid_iter displayid_iter;
5006
5007 /* Current Data Block Collection. */
5008 const u8 *collection;
5009
5010 /* Current Data Block index in current collection. */
5011 int index;
5012
5013 /* End index in current collection. */
5014 int end;
5015 };
5016
5017 /* CTA-861-H section 7.4 CTA Data BLock Collection */
5018 struct cea_db {
5019 u8 tag_length;
5020 u8 data[];
5021 } __packed;
5022
cea_db_tag(const struct cea_db * db)5023 static int cea_db_tag(const struct cea_db *db)
5024 {
5025 return db->tag_length >> 5;
5026 }
5027
cea_db_payload_len(const void * _db)5028 static int cea_db_payload_len(const void *_db)
5029 {
5030 /* FIXME: Transition to passing struct cea_db * everywhere. */
5031 const struct cea_db *db = _db;
5032
5033 return db->tag_length & 0x1f;
5034 }
5035
cea_db_data(const struct cea_db * db)5036 static const void *cea_db_data(const struct cea_db *db)
5037 {
5038 return db->data;
5039 }
5040
cea_db_is_extended_tag(const struct cea_db * db,int tag)5041 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
5042 {
5043 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
5044 cea_db_payload_len(db) >= 1 &&
5045 db->data[0] == tag;
5046 }
5047
cea_db_is_vendor(const struct cea_db * db,int vendor_oui)5048 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
5049 {
5050 const u8 *data = cea_db_data(db);
5051
5052 return cea_db_tag(db) == CTA_DB_VENDOR &&
5053 cea_db_payload_len(db) >= 3 &&
5054 oui(data[2], data[1], data[0]) == vendor_oui;
5055 }
5056
cea_db_iter_edid_begin(const struct drm_edid * drm_edid,struct cea_db_iter * iter)5057 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
5058 struct cea_db_iter *iter)
5059 {
5060 memset(iter, 0, sizeof(*iter));
5061
5062 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
5063 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
5064 }
5065
5066 static const struct cea_db *
__cea_db_iter_current_block(const struct cea_db_iter * iter)5067 __cea_db_iter_current_block(const struct cea_db_iter *iter)
5068 {
5069 const struct cea_db *db;
5070
5071 if (!iter->collection)
5072 return NULL;
5073
5074 db = (const struct cea_db *)&iter->collection[iter->index];
5075
5076 if (iter->index + sizeof(*db) <= iter->end &&
5077 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
5078 return db;
5079
5080 return NULL;
5081 }
5082
5083 /*
5084 * References:
5085 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5086 */
cea_db_collection_size(const u8 * cta)5087 static int cea_db_collection_size(const u8 *cta)
5088 {
5089 u8 d = cta[2];
5090
5091 if (d < 4 || d > 127)
5092 return 0;
5093
5094 return d - 4;
5095 }
5096
5097 /*
5098 * References:
5099 * - VESA E-EDID v1.4
5100 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5101 */
__cea_db_iter_edid_next(struct cea_db_iter * iter)5102 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
5103 {
5104 const u8 *ext;
5105
5106 drm_edid_iter_for_each(ext, &iter->edid_iter) {
5107 int size;
5108
5109 /* Only support CTA Extension revision 3+ */
5110 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
5111 continue;
5112
5113 size = cea_db_collection_size(ext);
5114 if (!size)
5115 continue;
5116
5117 iter->index = 4;
5118 iter->end = iter->index + size;
5119
5120 return ext;
5121 }
5122
5123 return NULL;
5124 }
5125
5126 /*
5127 * References:
5128 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
5129 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
5130 *
5131 * Note that the above do not specify any connection between DisplayID Data
5132 * Block revision and CTA Extension versions.
5133 */
__cea_db_iter_displayid_next(struct cea_db_iter * iter)5134 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
5135 {
5136 const struct displayid_block *block;
5137
5138 displayid_iter_for_each(block, &iter->displayid_iter) {
5139 if (block->tag != DATA_BLOCK_CTA)
5140 continue;
5141
5142 /*
5143 * The displayid iterator has already verified the block bounds
5144 * in displayid_iter_block().
5145 */
5146 iter->index = sizeof(*block);
5147 iter->end = iter->index + block->num_bytes;
5148
5149 return block;
5150 }
5151
5152 return NULL;
5153 }
5154
__cea_db_iter_next(struct cea_db_iter * iter)5155 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
5156 {
5157 const struct cea_db *db;
5158
5159 if (iter->collection) {
5160 /* Current collection should always be valid. */
5161 db = __cea_db_iter_current_block(iter);
5162 if (WARN_ON(!db)) {
5163 iter->collection = NULL;
5164 return NULL;
5165 }
5166
5167 /* Next block in CTA Data Block Collection */
5168 iter->index += sizeof(*db) + cea_db_payload_len(db);
5169
5170 db = __cea_db_iter_current_block(iter);
5171 if (db)
5172 return db;
5173 }
5174
5175 for (;;) {
5176 /*
5177 * Find the next CTA Data Block Collection. First iterate all
5178 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
5179 *
5180 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
5181 * Extension, it's recommended that DisplayID extensions are
5182 * exposed after all of the CTA Extensions.
5183 */
5184 iter->collection = __cea_db_iter_edid_next(iter);
5185 if (!iter->collection)
5186 iter->collection = __cea_db_iter_displayid_next(iter);
5187
5188 if (!iter->collection)
5189 return NULL;
5190
5191 db = __cea_db_iter_current_block(iter);
5192 if (db)
5193 return db;
5194 }
5195 }
5196
5197 #define cea_db_iter_for_each(__db, __iter) \
5198 while (((__db) = __cea_db_iter_next(__iter)))
5199
cea_db_iter_end(struct cea_db_iter * iter)5200 static void cea_db_iter_end(struct cea_db_iter *iter)
5201 {
5202 displayid_iter_end(&iter->displayid_iter);
5203 drm_edid_iter_end(&iter->edid_iter);
5204
5205 memset(iter, 0, sizeof(*iter));
5206 }
5207
cea_db_is_hdmi_vsdb(const struct cea_db * db)5208 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
5209 {
5210 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
5211 cea_db_payload_len(db) >= 5;
5212 }
5213
cea_db_is_hdmi_forum_vsdb(const struct cea_db * db)5214 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
5215 {
5216 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
5217 cea_db_payload_len(db) >= 7;
5218 }
5219
cea_db_is_hdmi_forum_eeodb(const void * db)5220 static bool cea_db_is_hdmi_forum_eeodb(const void *db)
5221 {
5222 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
5223 cea_db_payload_len(db) >= 2;
5224 }
5225
cea_db_is_microsoft_vsdb(const struct cea_db * db)5226 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
5227 {
5228 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
5229 cea_db_payload_len(db) == 21;
5230 }
5231
cea_db_is_vcdb(const struct cea_db * db)5232 static bool cea_db_is_vcdb(const struct cea_db *db)
5233 {
5234 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
5235 cea_db_payload_len(db) == 2;
5236 }
5237
cea_db_is_hdmi_forum_scdb(const struct cea_db * db)5238 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
5239 {
5240 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
5241 cea_db_payload_len(db) >= 7;
5242 }
5243
cea_db_is_y420cmdb(const struct cea_db * db)5244 static bool cea_db_is_y420cmdb(const struct cea_db *db)
5245 {
5246 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
5247 }
5248
cea_db_is_y420vdb(const struct cea_db * db)5249 static bool cea_db_is_y420vdb(const struct cea_db *db)
5250 {
5251 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5252 }
5253
cea_db_is_hdmi_hdr_metadata_block(const struct cea_db * db)5254 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
5255 {
5256 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5257 cea_db_payload_len(db) >= 3;
5258 }
5259
5260 /*
5261 * Get the HF-EEODB override extension block count from EDID.
5262 *
5263 * The passed in EDID may be partially read, as long as it has at least two
5264 * blocks (base block and one extension block) if EDID extension count is > 0.
5265 *
5266 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5267 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5268 * iterators instead.
5269 *
5270 * References:
5271 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5272 */
edid_hfeeodb_extension_block_count(const struct edid * edid)5273 static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5274 {
5275 const u8 *cta;
5276
5277 /* No extensions according to base block, no HF-EEODB. */
5278 if (!edid_extension_block_count(edid))
5279 return 0;
5280
5281 /* HF-EEODB is always in the first EDID extension block only */
5282 cta = edid_extension_block_data(edid, 0);
5283 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5284 return 0;
5285
5286 /* Need to have the data block collection, and at least 3 bytes. */
5287 if (cea_db_collection_size(cta) < 3)
5288 return 0;
5289
5290 /*
5291 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5292 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5293 * through 6 of Block 1 of the E-EDID.
5294 */
5295 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5296 return 0;
5297
5298 return cta[4 + 2];
5299 }
5300
5301 /*
5302 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB)
5303 *
5304 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB,
5305 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444
5306 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can
5307 * support YCBCR420 output too.
5308 */
parse_cta_y420cmdb(struct drm_connector * connector,const struct cea_db * db,u64 * y420cmdb_map)5309 static void parse_cta_y420cmdb(struct drm_connector *connector,
5310 const struct cea_db *db, u64 *y420cmdb_map)
5311 {
5312 struct drm_display_info *info = &connector->display_info;
5313 int i, map_len = cea_db_payload_len(db) - 1;
5314 const u8 *data = cea_db_data(db) + 1;
5315 u64 map = 0;
5316
5317 if (map_len == 0) {
5318 /* All CEA modes support ycbcr420 sampling also.*/
5319 map = U64_MAX;
5320 goto out;
5321 }
5322
5323 /*
5324 * This map indicates which of the existing CEA block modes
5325 * from VDB can support YCBCR420 output too. So if bit=0 is
5326 * set, first mode from VDB can support YCBCR420 output too.
5327 * We will parse and keep this map, before parsing VDB itself
5328 * to avoid going through the same block again and again.
5329 *
5330 * Spec is not clear about max possible size of this block.
5331 * Clamping max bitmap block size at 8 bytes. Every byte can
5332 * address 8 CEA modes, in this way this map can address
5333 * 8*8 = first 64 SVDs.
5334 */
5335 if (WARN_ON_ONCE(map_len > 8))
5336 map_len = 8;
5337
5338 for (i = 0; i < map_len; i++)
5339 map |= (u64)data[i] << (8 * i);
5340
5341 out:
5342 if (map)
5343 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5344
5345 *y420cmdb_map = map;
5346 }
5347
add_cea_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)5348 static int add_cea_modes(struct drm_connector *connector,
5349 const struct drm_edid *drm_edid)
5350 {
5351 const struct cea_db *db;
5352 struct cea_db_iter iter;
5353 int modes;
5354
5355 /* CTA VDB block VICs parsed earlier */
5356 modes = add_cta_vdb_modes(connector);
5357
5358 cea_db_iter_edid_begin(drm_edid, &iter);
5359 cea_db_iter_for_each(db, &iter) {
5360 if (cea_db_is_hdmi_vsdb(db)) {
5361 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db,
5362 cea_db_payload_len(db));
5363 } else if (cea_db_is_y420vdb(db)) {
5364 const u8 *vdb420 = cea_db_data(db) + 1;
5365
5366 /* Add 4:2:0(only) modes present in EDID */
5367 modes += do_y420vdb_modes(connector, vdb420,
5368 cea_db_payload_len(db) - 1);
5369 }
5370 }
5371 cea_db_iter_end(&iter);
5372
5373 return modes;
5374 }
5375
fixup_detailed_cea_mode_clock(struct drm_connector * connector,struct drm_display_mode * mode)5376 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
5377 struct drm_display_mode *mode)
5378 {
5379 const struct drm_display_mode *cea_mode;
5380 int clock1, clock2, clock;
5381 u8 vic;
5382 const char *type;
5383
5384 /*
5385 * allow 5kHz clock difference either way to account for
5386 * the 10kHz clock resolution limit of detailed timings.
5387 */
5388 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5389 if (drm_valid_cea_vic(vic)) {
5390 type = "CEA";
5391 cea_mode = cea_mode_for_vic(vic);
5392 clock1 = cea_mode->clock;
5393 clock2 = cea_mode_alternate_clock(cea_mode);
5394 } else {
5395 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5396 if (drm_valid_hdmi_vic(vic)) {
5397 type = "HDMI";
5398 cea_mode = &edid_4k_modes[vic];
5399 clock1 = cea_mode->clock;
5400 clock2 = hdmi_mode_alternate_clock(cea_mode);
5401 } else {
5402 return;
5403 }
5404 }
5405
5406 /* pick whichever is closest */
5407 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5408 clock = clock1;
5409 else
5410 clock = clock2;
5411
5412 if (mode->clock == clock)
5413 return;
5414
5415 drm_dbg_kms(connector->dev,
5416 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5417 connector->base.id, connector->name,
5418 type, vic, mode->clock, clock);
5419 mode->clock = clock;
5420 }
5421
drm_calculate_luminance_range(struct drm_connector * connector)5422 static void drm_calculate_luminance_range(struct drm_connector *connector)
5423 {
5424 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5425 struct drm_luminance_range_info *luminance_range =
5426 &connector->display_info.luminance_range;
5427 static const u8 pre_computed_values[] = {
5428 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5429 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5430 };
5431 u32 max_avg, min_cll, max, min, q, r;
5432
5433 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5434 return;
5435
5436 max_avg = hdr_metadata->max_fall;
5437 min_cll = hdr_metadata->min_cll;
5438
5439 /*
5440 * From the specification (CTA-861-G), for calculating the maximum
5441 * luminance we need to use:
5442 * Luminance = 50*2**(CV/32)
5443 * Where CV is a one-byte value.
5444 * For calculating this expression we may need float point precision;
5445 * to avoid this complexity level, we take advantage that CV is divided
5446 * by a constant. From the Euclids division algorithm, we know that CV
5447 * can be written as: CV = 32*q + r. Next, we replace CV in the
5448 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5449 * need to pre-compute the value of r/32. For pre-computing the values
5450 * We just used the following Ruby line:
5451 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5452 * The results of the above expressions can be verified at
5453 * pre_computed_values.
5454 */
5455 q = max_avg >> 5;
5456 r = max_avg % 32;
5457 max = (1 << q) * pre_computed_values[r];
5458
5459 /* min luminance: maxLum * (CV/255)^2 / 100 */
5460 q = DIV_ROUND_CLOSEST(min_cll, 255);
5461 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5462
5463 luminance_range->min_luminance = min;
5464 luminance_range->max_luminance = max;
5465 }
5466
eotf_supported(const u8 * edid_ext)5467 static uint8_t eotf_supported(const u8 *edid_ext)
5468 {
5469 return edid_ext[2] &
5470 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5471 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
5472 BIT(HDMI_EOTF_SMPTE_ST2084) |
5473 BIT(HDMI_EOTF_BT_2100_HLG));
5474 }
5475
hdr_metadata_type(const u8 * edid_ext)5476 static uint8_t hdr_metadata_type(const u8 *edid_ext)
5477 {
5478 return edid_ext[3] &
5479 BIT(HDMI_STATIC_METADATA_TYPE1);
5480 }
5481
5482 static void
drm_parse_hdr_metadata_block(struct drm_connector * connector,const u8 * db)5483 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5484 {
5485 u16 len;
5486
5487 len = cea_db_payload_len(db);
5488
5489 connector->hdr_sink_metadata.hdmi_type1.eotf =
5490 eotf_supported(db);
5491 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5492 hdr_metadata_type(db);
5493
5494 if (len >= 4)
5495 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5496 if (len >= 5)
5497 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
5498 if (len >= 6) {
5499 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
5500
5501 /* Calculate only when all values are available */
5502 drm_calculate_luminance_range(connector);
5503 }
5504 }
5505
5506 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
5507 static void
drm_parse_hdmi_vsdb_audio(struct drm_connector * connector,const u8 * db)5508 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
5509 {
5510 u8 len = cea_db_payload_len(db);
5511
5512 if (len >= 6 && (db[6] & (1 << 7)))
5513 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
5514
5515 if (len >= 10 && hdmi_vsdb_latency_present(db)) {
5516 connector->latency_present[0] = true;
5517 connector->video_latency[0] = db[9];
5518 connector->audio_latency[0] = db[10];
5519 }
5520
5521 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) {
5522 connector->latency_present[1] = true;
5523 connector->video_latency[1] = db[11];
5524 connector->audio_latency[1] = db[12];
5525 }
5526
5527 drm_dbg_kms(connector->dev,
5528 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n",
5529 connector->base.id, connector->name,
5530 connector->latency_present[0], connector->latency_present[1],
5531 connector->video_latency[0], connector->video_latency[1],
5532 connector->audio_latency[0], connector->audio_latency[1]);
5533 }
5534
5535 static void
match_identity(const struct detailed_timing * timing,void * data)5536 match_identity(const struct detailed_timing *timing, void *data)
5537 {
5538 struct drm_edid_match_closure *closure = data;
5539 unsigned int i;
5540 const char *name = closure->ident->name;
5541 unsigned int name_len = strlen(name);
5542 const char *desc = timing->data.other_data.data.str.str;
5543 unsigned int desc_len = ARRAY_SIZE(timing->data.other_data.data.str.str);
5544
5545 if (name_len > desc_len ||
5546 !(is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME) ||
5547 is_display_descriptor(timing, EDID_DETAIL_MONITOR_STRING)))
5548 return;
5549
5550 if (strncmp(name, desc, name_len))
5551 return;
5552
5553 for (i = name_len; i < desc_len; i++) {
5554 if (desc[i] == '\n')
5555 break;
5556 /* Allow white space before EDID string terminator. */
5557 if (!isspace(desc[i]))
5558 return;
5559 }
5560
5561 closure->matched = true;
5562 }
5563
5564 /**
5565 * drm_edid_match - match drm_edid with given identity
5566 * @drm_edid: EDID
5567 * @ident: the EDID identity to match with
5568 *
5569 * Check if the EDID matches with the given identity.
5570 *
5571 * Return: True if the given identity matched with EDID, false otherwise.
5572 */
drm_edid_match(const struct drm_edid * drm_edid,const struct drm_edid_ident * ident)5573 bool drm_edid_match(const struct drm_edid *drm_edid,
5574 const struct drm_edid_ident *ident)
5575 {
5576 if (!drm_edid || drm_edid_get_panel_id(drm_edid) != ident->panel_id)
5577 return false;
5578
5579 /* Match with name only if it's not NULL. */
5580 if (ident->name) {
5581 struct drm_edid_match_closure closure = {
5582 .ident = ident,
5583 .matched = false,
5584 };
5585
5586 drm_for_each_detailed_block(drm_edid, match_identity, &closure);
5587
5588 return closure.matched;
5589 }
5590
5591 return true;
5592 }
5593 EXPORT_SYMBOL(drm_edid_match);
5594
5595 static void
monitor_name(const struct detailed_timing * timing,void * data)5596 monitor_name(const struct detailed_timing *timing, void *data)
5597 {
5598 const char **res = data;
5599
5600 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
5601 return;
5602
5603 *res = timing->data.other_data.data.str.str;
5604 }
5605
get_monitor_name(const struct drm_edid * drm_edid,char name[13])5606 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
5607 {
5608 const char *edid_name = NULL;
5609 int mnl;
5610
5611 if (!drm_edid || !name)
5612 return 0;
5613
5614 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
5615 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5616 if (edid_name[mnl] == 0x0a)
5617 break;
5618
5619 name[mnl] = edid_name[mnl];
5620 }
5621
5622 return mnl;
5623 }
5624
5625 /**
5626 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5627 * @edid: monitor EDID information
5628 * @name: pointer to a character array to hold the name of the monitor
5629 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5630 *
5631 */
drm_edid_get_monitor_name(const struct edid * edid,char * name,int bufsize)5632 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
5633 {
5634 int name_length = 0;
5635
5636 if (bufsize <= 0)
5637 return;
5638
5639 if (edid) {
5640 char buf[13];
5641 struct drm_edid drm_edid = {
5642 .edid = edid,
5643 .size = edid_size(edid),
5644 };
5645
5646 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5647 memcpy(name, buf, name_length);
5648 }
5649
5650 name[name_length] = '\0';
5651 }
5652 EXPORT_SYMBOL(drm_edid_get_monitor_name);
5653
clear_eld(struct drm_connector * connector)5654 static void clear_eld(struct drm_connector *connector)
5655 {
5656 memset(connector->eld, 0, sizeof(connector->eld));
5657
5658 connector->latency_present[0] = false;
5659 connector->latency_present[1] = false;
5660 connector->video_latency[0] = 0;
5661 connector->audio_latency[0] = 0;
5662 connector->video_latency[1] = 0;
5663 connector->audio_latency[1] = 0;
5664 }
5665
5666 /*
5667 * Get 3-byte SAD buffer from struct cea_sad.
5668 */
drm_edid_cta_sad_get(const struct cea_sad * cta_sad,u8 * sad)5669 void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad)
5670 {
5671 sad[0] = cta_sad->format << 3 | cta_sad->channels;
5672 sad[1] = cta_sad->freq;
5673 sad[2] = cta_sad->byte2;
5674 }
5675
5676 /*
5677 * Set struct cea_sad from 3-byte SAD buffer.
5678 */
drm_edid_cta_sad_set(struct cea_sad * cta_sad,const u8 * sad)5679 void drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad)
5680 {
5681 cta_sad->format = (sad[0] & 0x78) >> 3;
5682 cta_sad->channels = sad[0] & 0x07;
5683 cta_sad->freq = sad[1] & 0x7f;
5684 cta_sad->byte2 = sad[2];
5685 }
5686
5687 /*
5688 * drm_edid_to_eld - build ELD from EDID
5689 * @connector: connector corresponding to the HDMI/DP sink
5690 * @drm_edid: EDID to parse
5691 *
5692 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
5693 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
5694 */
drm_edid_to_eld(struct drm_connector * connector,const struct drm_edid * drm_edid)5695 static void drm_edid_to_eld(struct drm_connector *connector,
5696 const struct drm_edid *drm_edid)
5697 {
5698 const struct drm_display_info *info = &connector->display_info;
5699 const struct cea_db *db;
5700 struct cea_db_iter iter;
5701 uint8_t *eld = connector->eld;
5702 int total_sad_count = 0;
5703 int mnl;
5704
5705 if (!drm_edid)
5706 return;
5707
5708 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
5709 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n",
5710 connector->base.id, connector->name,
5711 &eld[DRM_ELD_MONITOR_NAME_STRING]);
5712
5713 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
5714 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
5715
5716 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
5717
5718 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5719 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5720 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5721 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
5722
5723 cea_db_iter_edid_begin(drm_edid, &iter);
5724 cea_db_iter_for_each(db, &iter) {
5725 const u8 *data = cea_db_data(db);
5726 int len = cea_db_payload_len(db);
5727 int sad_count;
5728
5729 switch (cea_db_tag(db)) {
5730 case CTA_DB_AUDIO:
5731 /* Audio Data Block, contains SADs */
5732 sad_count = min(len / 3, 15 - total_sad_count);
5733 if (sad_count >= 1)
5734 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5735 data, sad_count * 3);
5736 total_sad_count += sad_count;
5737 break;
5738 case CTA_DB_SPEAKER:
5739 /* Speaker Allocation Data Block */
5740 if (len >= 1)
5741 eld[DRM_ELD_SPEAKER] = data[0];
5742 break;
5743 case CTA_DB_VENDOR:
5744 /* HDMI Vendor-Specific Data Block */
5745 if (cea_db_is_hdmi_vsdb(db))
5746 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5747 break;
5748 default:
5749 break;
5750 }
5751 }
5752 cea_db_iter_end(&iter);
5753
5754 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
5755
5756 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5757 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5758 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5759 else
5760 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
5761
5762 eld[DRM_ELD_BASELINE_ELD_LEN] =
5763 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5764
5765 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n",
5766 connector->base.id, connector->name,
5767 drm_eld_size(eld), total_sad_count);
5768 }
5769
_drm_edid_to_sad(const struct drm_edid * drm_edid,struct cea_sad ** psads)5770 static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5771 struct cea_sad **psads)
5772 {
5773 const struct cea_db *db;
5774 struct cea_db_iter iter;
5775 int count = 0;
5776
5777 cea_db_iter_edid_begin(drm_edid, &iter);
5778 cea_db_iter_for_each(db, &iter) {
5779 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5780 struct cea_sad *sads;
5781 int i;
5782
5783 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
5784 sads = kcalloc(count, sizeof(*sads), GFP_KERNEL);
5785 *psads = sads;
5786 if (!sads)
5787 return -ENOMEM;
5788 for (i = 0; i < count; i++)
5789 drm_edid_cta_sad_set(&sads[i], &db->data[i * 3]);
5790 break;
5791 }
5792 }
5793 cea_db_iter_end(&iter);
5794
5795 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
5796
5797 return count;
5798 }
5799
5800 /**
5801 * drm_edid_to_sad - extracts SADs from EDID
5802 * @edid: EDID to parse
5803 * @sads: pointer that will be set to the extracted SADs
5804 *
5805 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5806 *
5807 * Note: The returned pointer needs to be freed using kfree().
5808 *
5809 * Return: The number of found SADs or negative number on error.
5810 */
drm_edid_to_sad(const struct edid * edid,struct cea_sad ** sads)5811 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5812 {
5813 struct drm_edid drm_edid;
5814
5815 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5816 }
5817 EXPORT_SYMBOL(drm_edid_to_sad);
5818
_drm_edid_to_speaker_allocation(const struct drm_edid * drm_edid,u8 ** sadb)5819 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5820 u8 **sadb)
5821 {
5822 const struct cea_db *db;
5823 struct cea_db_iter iter;
5824 int count = 0;
5825
5826 cea_db_iter_edid_begin(drm_edid, &iter);
5827 cea_db_iter_for_each(db, &iter) {
5828 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5829 cea_db_payload_len(db) == 3) {
5830 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5831 GFP_KERNEL);
5832 if (!*sadb)
5833 return -ENOMEM;
5834 count = cea_db_payload_len(db);
5835 break;
5836 }
5837 }
5838 cea_db_iter_end(&iter);
5839
5840 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
5841
5842 return count;
5843 }
5844
5845 /**
5846 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5847 * @edid: EDID to parse
5848 * @sadb: pointer to the speaker block
5849 *
5850 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5851 *
5852 * Note: The returned pointer needs to be freed using kfree().
5853 *
5854 * Return: The number of found Speaker Allocation Blocks or negative number on
5855 * error.
5856 */
drm_edid_to_speaker_allocation(const struct edid * edid,u8 ** sadb)5857 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5858 {
5859 struct drm_edid drm_edid;
5860
5861 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5862 sadb);
5863 }
5864 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5865
5866 /**
5867 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
5868 * @connector: connector associated with the HDMI/DP sink
5869 * @mode: the display mode
5870 *
5871 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5872 * the sink doesn't support audio or video.
5873 */
drm_av_sync_delay(struct drm_connector * connector,const struct drm_display_mode * mode)5874 int drm_av_sync_delay(struct drm_connector *connector,
5875 const struct drm_display_mode *mode)
5876 {
5877 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5878 int a, v;
5879
5880 if (!connector->latency_present[0])
5881 return 0;
5882 if (!connector->latency_present[1])
5883 i = 0;
5884
5885 a = connector->audio_latency[i];
5886 v = connector->video_latency[i];
5887
5888 /*
5889 * HDMI/DP sink doesn't support audio or video?
5890 */
5891 if (a == 255 || v == 255)
5892 return 0;
5893
5894 /*
5895 * Convert raw EDID values to millisecond.
5896 * Treat unknown latency as 0ms.
5897 */
5898 if (a)
5899 a = min(2 * (a - 1), 500);
5900 if (v)
5901 v = min(2 * (v - 1), 500);
5902
5903 return max(v - a, 0);
5904 }
5905 EXPORT_SYMBOL(drm_av_sync_delay);
5906
_drm_detect_hdmi_monitor(const struct drm_edid * drm_edid)5907 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
5908 {
5909 const struct cea_db *db;
5910 struct cea_db_iter iter;
5911 bool hdmi = false;
5912
5913 /*
5914 * Because HDMI identifier is in Vendor Specific Block,
5915 * search it from all data blocks of CEA extension.
5916 */
5917 cea_db_iter_edid_begin(drm_edid, &iter);
5918 cea_db_iter_for_each(db, &iter) {
5919 if (cea_db_is_hdmi_vsdb(db)) {
5920 hdmi = true;
5921 break;
5922 }
5923 }
5924 cea_db_iter_end(&iter);
5925
5926 return hdmi;
5927 }
5928
5929 /**
5930 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5931 * @edid: monitor EDID information
5932 *
5933 * Parse the CEA extension according to CEA-861-B.
5934 *
5935 * Drivers that have added the modes parsed from EDID to drm_display_info
5936 * should use &drm_display_info.is_hdmi instead of calling this function.
5937 *
5938 * Return: True if the monitor is HDMI, false if not or unknown.
5939 */
drm_detect_hdmi_monitor(const struct edid * edid)5940 bool drm_detect_hdmi_monitor(const struct edid *edid)
5941 {
5942 struct drm_edid drm_edid;
5943
5944 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5945 }
5946 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5947
_drm_detect_monitor_audio(const struct drm_edid * drm_edid)5948 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
5949 {
5950 struct drm_edid_iter edid_iter;
5951 const struct cea_db *db;
5952 struct cea_db_iter iter;
5953 const u8 *edid_ext;
5954 bool has_audio = false;
5955
5956 drm_edid_iter_begin(drm_edid, &edid_iter);
5957 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5958 if (edid_ext[0] == CEA_EXT) {
5959 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5960 if (has_audio)
5961 break;
5962 }
5963 }
5964 drm_edid_iter_end(&edid_iter);
5965
5966 if (has_audio) {
5967 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5968 goto end;
5969 }
5970
5971 cea_db_iter_edid_begin(drm_edid, &iter);
5972 cea_db_iter_for_each(db, &iter) {
5973 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5974 const u8 *data = cea_db_data(db);
5975 int i;
5976
5977 for (i = 0; i < cea_db_payload_len(db); i += 3)
5978 DRM_DEBUG_KMS("CEA audio format %d\n",
5979 (data[i] >> 3) & 0xf);
5980 has_audio = true;
5981 break;
5982 }
5983 }
5984 cea_db_iter_end(&iter);
5985
5986 end:
5987 return has_audio;
5988 }
5989
5990 /**
5991 * drm_detect_monitor_audio - check monitor audio capability
5992 * @edid: EDID block to scan
5993 *
5994 * Monitor should have CEA extension block.
5995 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5996 * audio' only. If there is any audio extension block and supported
5997 * audio format, assume at least 'basic audio' support, even if 'basic
5998 * audio' is not defined in EDID.
5999 *
6000 * Return: True if the monitor supports audio, false otherwise.
6001 */
drm_detect_monitor_audio(const struct edid * edid)6002 bool drm_detect_monitor_audio(const struct edid *edid)
6003 {
6004 struct drm_edid drm_edid;
6005
6006 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
6007 }
6008 EXPORT_SYMBOL(drm_detect_monitor_audio);
6009
6010
6011 /**
6012 * drm_default_rgb_quant_range - default RGB quantization range
6013 * @mode: display mode
6014 *
6015 * Determine the default RGB quantization range for the mode,
6016 * as specified in CEA-861.
6017 *
6018 * Return: The default RGB quantization range for the mode
6019 */
6020 enum hdmi_quantization_range
drm_default_rgb_quant_range(const struct drm_display_mode * mode)6021 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
6022 {
6023 /* All CEA modes other than VIC 1 use limited quantization range. */
6024 return drm_match_cea_mode(mode) > 1 ?
6025 HDMI_QUANTIZATION_RANGE_LIMITED :
6026 HDMI_QUANTIZATION_RANGE_FULL;
6027 }
6028 EXPORT_SYMBOL(drm_default_rgb_quant_range);
6029
6030 /* CTA-861 Video Data Block (CTA VDB) */
parse_cta_vdb(struct drm_connector * connector,const struct cea_db * db)6031 static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db)
6032 {
6033 struct drm_display_info *info = &connector->display_info;
6034 int i, vic_index, len = cea_db_payload_len(db);
6035 const u8 *svds = cea_db_data(db);
6036 u8 *vics;
6037
6038 if (!len)
6039 return;
6040
6041 /* Gracefully handle multiple VDBs, however unlikely that is */
6042 #ifdef __linux__
6043 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL);
6044 if (!vics)
6045 return;
6046 #else
6047 vics = kmalloc(info->vics_len + len, GFP_KERNEL);
6048 if (!vics)
6049 return;
6050 memcpy(vics, info->vics, info->vics_len);
6051 kfree(info->vics);
6052 #endif
6053
6054 vic_index = info->vics_len;
6055 info->vics_len += len;
6056 info->vics = vics;
6057
6058 for (i = 0; i < len; i++) {
6059 u8 vic = svd_to_vic(svds[i]);
6060
6061 if (!drm_valid_cea_vic(vic))
6062 vic = 0;
6063
6064 info->vics[vic_index++] = vic;
6065 }
6066 }
6067
6068 /*
6069 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB.
6070 *
6071 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed
6072 * using the VICs themselves.
6073 */
update_cta_y420cmdb(struct drm_connector * connector,u64 y420cmdb_map)6074 static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map)
6075 {
6076 struct drm_display_info *info = &connector->display_info;
6077 struct drm_hdmi_info *hdmi = &info->hdmi;
6078 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map));
6079
6080 for (i = 0; i < len; i++) {
6081 u8 vic = info->vics[i];
6082
6083 if (vic && y420cmdb_map & BIT_ULL(i))
6084 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
6085 }
6086 }
6087
cta_vdb_has_vic(const struct drm_connector * connector,u8 vic)6088 static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic)
6089 {
6090 const struct drm_display_info *info = &connector->display_info;
6091 int i;
6092
6093 if (!vic || !info->vics)
6094 return false;
6095
6096 for (i = 0; i < info->vics_len; i++) {
6097 if (info->vics[i] == vic)
6098 return true;
6099 }
6100
6101 return false;
6102 }
6103
6104 /* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */
parse_cta_y420vdb(struct drm_connector * connector,const struct cea_db * db)6105 static void parse_cta_y420vdb(struct drm_connector *connector,
6106 const struct cea_db *db)
6107 {
6108 struct drm_display_info *info = &connector->display_info;
6109 struct drm_hdmi_info *hdmi = &info->hdmi;
6110 const u8 *svds = cea_db_data(db) + 1;
6111 int i;
6112
6113 for (i = 0; i < cea_db_payload_len(db) - 1; i++) {
6114 u8 vic = svd_to_vic(svds[i]);
6115
6116 if (!drm_valid_cea_vic(vic))
6117 continue;
6118
6119 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
6120 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
6121 }
6122 }
6123
drm_parse_vcdb(struct drm_connector * connector,const u8 * db)6124 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
6125 {
6126 struct drm_display_info *info = &connector->display_info;
6127
6128 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n",
6129 connector->base.id, connector->name, db[2]);
6130
6131 if (db[2] & EDID_CEA_VCDB_QS)
6132 info->rgb_quant_range_selectable = true;
6133 }
6134
6135 static
drm_get_max_frl_rate(int max_frl_rate,u8 * max_lanes,u8 * max_rate_per_lane)6136 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
6137 {
6138 switch (max_frl_rate) {
6139 case 1:
6140 *max_lanes = 3;
6141 *max_rate_per_lane = 3;
6142 break;
6143 case 2:
6144 *max_lanes = 3;
6145 *max_rate_per_lane = 6;
6146 break;
6147 case 3:
6148 *max_lanes = 4;
6149 *max_rate_per_lane = 6;
6150 break;
6151 case 4:
6152 *max_lanes = 4;
6153 *max_rate_per_lane = 8;
6154 break;
6155 case 5:
6156 *max_lanes = 4;
6157 *max_rate_per_lane = 10;
6158 break;
6159 case 6:
6160 *max_lanes = 4;
6161 *max_rate_per_lane = 12;
6162 break;
6163 case 0:
6164 default:
6165 *max_lanes = 0;
6166 *max_rate_per_lane = 0;
6167 }
6168 }
6169
drm_parse_ycbcr420_deep_color_info(struct drm_connector * connector,const u8 * db)6170 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
6171 const u8 *db)
6172 {
6173 u8 dc_mask;
6174 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
6175
6176 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
6177 hdmi->y420_dc_modes = dc_mask;
6178 }
6179
drm_parse_dsc_info(struct drm_hdmi_dsc_cap * hdmi_dsc,const u8 * hf_scds)6180 static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
6181 const u8 *hf_scds)
6182 {
6183 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
6184
6185 if (!hdmi_dsc->v_1p2)
6186 return;
6187
6188 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
6189 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
6190
6191 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
6192 hdmi_dsc->bpc_supported = 16;
6193 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
6194 hdmi_dsc->bpc_supported = 12;
6195 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
6196 hdmi_dsc->bpc_supported = 10;
6197 else
6198 /* Supports min 8 BPC if DSC 1.2 is supported*/
6199 hdmi_dsc->bpc_supported = 8;
6200
6201 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) {
6202 u8 dsc_max_slices;
6203 u8 dsc_max_frl_rate;
6204
6205 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
6206 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
6207 &hdmi_dsc->max_frl_rate_per_lane);
6208
6209 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
6210
6211 switch (dsc_max_slices) {
6212 case 1:
6213 hdmi_dsc->max_slices = 1;
6214 hdmi_dsc->clk_per_slice = 340;
6215 break;
6216 case 2:
6217 hdmi_dsc->max_slices = 2;
6218 hdmi_dsc->clk_per_slice = 340;
6219 break;
6220 case 3:
6221 hdmi_dsc->max_slices = 4;
6222 hdmi_dsc->clk_per_slice = 340;
6223 break;
6224 case 4:
6225 hdmi_dsc->max_slices = 8;
6226 hdmi_dsc->clk_per_slice = 340;
6227 break;
6228 case 5:
6229 hdmi_dsc->max_slices = 8;
6230 hdmi_dsc->clk_per_slice = 400;
6231 break;
6232 case 6:
6233 hdmi_dsc->max_slices = 12;
6234 hdmi_dsc->clk_per_slice = 400;
6235 break;
6236 case 7:
6237 hdmi_dsc->max_slices = 16;
6238 hdmi_dsc->clk_per_slice = 400;
6239 break;
6240 case 0:
6241 default:
6242 hdmi_dsc->max_slices = 0;
6243 hdmi_dsc->clk_per_slice = 0;
6244 }
6245 }
6246
6247 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13])
6248 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
6249 }
6250
6251 /* Sink Capability Data Structure */
drm_parse_hdmi_forum_scds(struct drm_connector * connector,const u8 * hf_scds)6252 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
6253 const u8 *hf_scds)
6254 {
6255 struct drm_display_info *info = &connector->display_info;
6256 struct drm_hdmi_info *hdmi = &info->hdmi;
6257 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
6258 int max_tmds_clock = 0;
6259 u8 max_frl_rate = 0;
6260 bool dsc_support = false;
6261
6262 info->has_hdmi_infoframe = true;
6263
6264 if (hf_scds[6] & 0x80) {
6265 hdmi->scdc.supported = true;
6266 if (hf_scds[6] & 0x40)
6267 hdmi->scdc.read_request = true;
6268 }
6269
6270 /*
6271 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
6272 * And as per the spec, three factors confirm this:
6273 * * Availability of a HF-VSDB block in EDID (check)
6274 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
6275 * * SCDC support available (let's check)
6276 * Lets check it out.
6277 */
6278
6279 if (hf_scds[5]) {
6280 struct drm_scdc *scdc = &hdmi->scdc;
6281
6282 /* max clock is 5000 KHz times block value */
6283 max_tmds_clock = hf_scds[5] * 5000;
6284
6285 if (max_tmds_clock > 340000) {
6286 info->max_tmds_clock = max_tmds_clock;
6287 }
6288
6289 if (scdc->supported) {
6290 scdc->scrambling.supported = true;
6291
6292 /* Few sinks support scrambling for clocks < 340M */
6293 if ((hf_scds[6] & 0x8))
6294 scdc->scrambling.low_rates = true;
6295 }
6296 }
6297
6298 if (hf_scds[7]) {
6299 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
6300 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
6301 &hdmi->max_frl_rate_per_lane);
6302 }
6303
6304 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
6305
6306 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
6307 drm_parse_dsc_info(hdmi_dsc, hf_scds);
6308 dsc_support = true;
6309 }
6310
6311 drm_dbg_kms(connector->dev,
6312 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
6313 connector->base.id, connector->name,
6314 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
6315 }
6316
drm_parse_hdmi_deep_color_info(struct drm_connector * connector,const u8 * hdmi)6317 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
6318 const u8 *hdmi)
6319 {
6320 struct drm_display_info *info = &connector->display_info;
6321 unsigned int dc_bpc = 0;
6322
6323 /* HDMI supports at least 8 bpc */
6324 info->bpc = 8;
6325
6326 if (cea_db_payload_len(hdmi) < 6)
6327 return;
6328
6329 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
6330 dc_bpc = 10;
6331 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
6332 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n",
6333 connector->base.id, connector->name);
6334 }
6335
6336 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
6337 dc_bpc = 12;
6338 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
6339 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n",
6340 connector->base.id, connector->name);
6341 }
6342
6343 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
6344 dc_bpc = 16;
6345 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
6346 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n",
6347 connector->base.id, connector->name);
6348 }
6349
6350 if (dc_bpc == 0) {
6351 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n",
6352 connector->base.id, connector->name);
6353 return;
6354 }
6355
6356 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n",
6357 connector->base.id, connector->name, dc_bpc);
6358 info->bpc = dc_bpc;
6359
6360 /* YCRCB444 is optional according to spec. */
6361 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
6362 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
6363 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n",
6364 connector->base.id, connector->name);
6365 }
6366
6367 /*
6368 * Spec says that if any deep color mode is supported at all,
6369 * then deep color 36 bit must be supported.
6370 */
6371 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
6372 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n",
6373 connector->base.id, connector->name);
6374 }
6375 }
6376
6377 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
6378 static void
drm_parse_hdmi_vsdb_video(struct drm_connector * connector,const u8 * db)6379 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
6380 {
6381 struct drm_display_info *info = &connector->display_info;
6382 u8 len = cea_db_payload_len(db);
6383
6384 info->is_hdmi = true;
6385
6386 info->source_physical_address = (db[4] << 8) | db[5];
6387
6388 if (len >= 6)
6389 info->dvi_dual = db[6] & 1;
6390 if (len >= 7)
6391 info->max_tmds_clock = db[7] * 5000;
6392
6393 /*
6394 * Try to infer whether the sink supports HDMI infoframes.
6395 *
6396 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink
6397 * supports infoframes if HDMI_Video_present is set.
6398 */
6399 if (len >= 8 && db[8] & BIT(5))
6400 info->has_hdmi_infoframe = true;
6401
6402 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n",
6403 connector->base.id, connector->name,
6404 info->dvi_dual, info->max_tmds_clock);
6405
6406 drm_parse_hdmi_deep_color_info(connector, db);
6407 }
6408
6409 /*
6410 * See EDID extension for head-mounted and specialized monitors, specified at:
6411 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
6412 */
drm_parse_microsoft_vsdb(struct drm_connector * connector,const u8 * db)6413 static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
6414 const u8 *db)
6415 {
6416 struct drm_display_info *info = &connector->display_info;
6417 u8 version = db[4];
6418 bool desktop_usage = db[5] & BIT(6);
6419
6420 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
6421 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
6422 info->non_desktop = true;
6423
6424 drm_dbg_kms(connector->dev,
6425 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n",
6426 connector->base.id, connector->name, version, db[5]);
6427 }
6428
drm_parse_cea_ext(struct drm_connector * connector,const struct drm_edid * drm_edid)6429 static void drm_parse_cea_ext(struct drm_connector *connector,
6430 const struct drm_edid *drm_edid)
6431 {
6432 struct drm_display_info *info = &connector->display_info;
6433 struct drm_edid_iter edid_iter;
6434 const struct cea_db *db;
6435 struct cea_db_iter iter;
6436 const u8 *edid_ext;
6437 u64 y420cmdb_map = 0;
6438
6439 drm_edid_iter_begin(drm_edid, &edid_iter);
6440 drm_edid_iter_for_each(edid_ext, &edid_iter) {
6441 if (edid_ext[0] != CEA_EXT)
6442 continue;
6443
6444 if (!info->cea_rev)
6445 info->cea_rev = edid_ext[1];
6446
6447 if (info->cea_rev != edid_ext[1])
6448 drm_dbg_kms(connector->dev,
6449 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n",
6450 connector->base.id, connector->name,
6451 info->cea_rev, edid_ext[1]);
6452
6453 /* The existence of a CTA extension should imply RGB support */
6454 info->color_formats = DRM_COLOR_FORMAT_RGB444;
6455 if (edid_ext[3] & EDID_CEA_YCRCB444)
6456 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6457 if (edid_ext[3] & EDID_CEA_YCRCB422)
6458 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6459 if (edid_ext[3] & EDID_BASIC_AUDIO)
6460 info->has_audio = true;
6461
6462 }
6463 drm_edid_iter_end(&edid_iter);
6464
6465 cea_db_iter_edid_begin(drm_edid, &iter);
6466 cea_db_iter_for_each(db, &iter) {
6467 /* FIXME: convert parsers to use struct cea_db */
6468 const u8 *data = (const u8 *)db;
6469
6470 if (cea_db_is_hdmi_vsdb(db))
6471 drm_parse_hdmi_vsdb_video(connector, data);
6472 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6473 cea_db_is_hdmi_forum_scdb(db))
6474 drm_parse_hdmi_forum_scds(connector, data);
6475 else if (cea_db_is_microsoft_vsdb(db))
6476 drm_parse_microsoft_vsdb(connector, data);
6477 else if (cea_db_is_y420cmdb(db))
6478 parse_cta_y420cmdb(connector, db, &y420cmdb_map);
6479 else if (cea_db_is_y420vdb(db))
6480 parse_cta_y420vdb(connector, db);
6481 else if (cea_db_is_vcdb(db))
6482 drm_parse_vcdb(connector, data);
6483 else if (cea_db_is_hdmi_hdr_metadata_block(db))
6484 drm_parse_hdr_metadata_block(connector, data);
6485 else if (cea_db_tag(db) == CTA_DB_VIDEO)
6486 parse_cta_vdb(connector, db);
6487 else if (cea_db_tag(db) == CTA_DB_AUDIO)
6488 info->has_audio = true;
6489 }
6490 cea_db_iter_end(&iter);
6491
6492 if (y420cmdb_map)
6493 update_cta_y420cmdb(connector, y420cmdb_map);
6494 }
6495
6496 static
get_monitor_range(const struct detailed_timing * timing,void * c)6497 void get_monitor_range(const struct detailed_timing *timing, void *c)
6498 {
6499 struct detailed_mode_closure *closure = c;
6500 struct drm_display_info *info = &closure->connector->display_info;
6501 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
6502 const struct detailed_non_pixel *data = &timing->data.other_data;
6503 const struct detailed_data_monitor_range *range = &data->data.range;
6504 const struct edid *edid = closure->drm_edid->edid;
6505
6506 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
6507 return;
6508
6509 /*
6510 * These limits are used to determine the VRR refresh
6511 * rate range. Only the "range limits only" variant
6512 * of the range descriptor seems to guarantee that
6513 * any and all timings are accepted by the sink, as
6514 * opposed to just timings conforming to the indicated
6515 * formula (GTF/GTF2/CVT). Thus other variants of the
6516 * range descriptor are not accepted here.
6517 */
6518 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6519 return;
6520
6521 monitor_range->min_vfreq = range->min_vfreq;
6522 monitor_range->max_vfreq = range->max_vfreq;
6523
6524 if (edid->revision >= 4) {
6525 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6526 monitor_range->min_vfreq += 255;
6527 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6528 monitor_range->max_vfreq += 255;
6529 }
6530 }
6531
drm_get_monitor_range(struct drm_connector * connector,const struct drm_edid * drm_edid)6532 static void drm_get_monitor_range(struct drm_connector *connector,
6533 const struct drm_edid *drm_edid)
6534 {
6535 const struct drm_display_info *info = &connector->display_info;
6536 struct detailed_mode_closure closure = {
6537 .connector = connector,
6538 .drm_edid = drm_edid,
6539 };
6540
6541 if (drm_edid->edid->revision < 4)
6542 return;
6543
6544 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
6545 return;
6546
6547 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
6548
6549 drm_dbg_kms(connector->dev,
6550 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6551 connector->base.id, connector->name,
6552 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq);
6553 }
6554
drm_parse_vesa_mso_data(struct drm_connector * connector,const struct displayid_block * block)6555 static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6556 const struct displayid_block *block)
6557 {
6558 struct displayid_vesa_vendor_specific_block *vesa =
6559 (struct displayid_vesa_vendor_specific_block *)block;
6560 struct drm_display_info *info = &connector->display_info;
6561
6562 if (block->num_bytes < 3) {
6563 drm_dbg_kms(connector->dev,
6564 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n",
6565 connector->base.id, connector->name, block->num_bytes);
6566 return;
6567 }
6568
6569 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6570 return;
6571
6572 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
6573 drm_dbg_kms(connector->dev,
6574 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
6575 connector->base.id, connector->name);
6576 return;
6577 }
6578
6579 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6580 default:
6581 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
6582 connector->base.id, connector->name);
6583 fallthrough;
6584 case 0:
6585 info->mso_stream_count = 0;
6586 break;
6587 case 1:
6588 info->mso_stream_count = 2; /* 2 or 4 links */
6589 break;
6590 case 2:
6591 info->mso_stream_count = 4; /* 4 links */
6592 break;
6593 }
6594
6595 if (!info->mso_stream_count) {
6596 info->mso_pixel_overlap = 0;
6597 return;
6598 }
6599
6600 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6601 if (info->mso_pixel_overlap > 8) {
6602 drm_dbg_kms(connector->dev,
6603 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
6604 connector->base.id, connector->name,
6605 info->mso_pixel_overlap);
6606 info->mso_pixel_overlap = 8;
6607 }
6608
6609 drm_dbg_kms(connector->dev,
6610 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
6611 connector->base.id, connector->name,
6612 info->mso_stream_count, info->mso_pixel_overlap);
6613 }
6614
drm_update_mso(struct drm_connector * connector,const struct drm_edid * drm_edid)6615 static void drm_update_mso(struct drm_connector *connector,
6616 const struct drm_edid *drm_edid)
6617 {
6618 const struct displayid_block *block;
6619 struct displayid_iter iter;
6620
6621 displayid_iter_edid_begin(drm_edid, &iter);
6622 displayid_iter_for_each(block, &iter) {
6623 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6624 drm_parse_vesa_mso_data(connector, block);
6625 }
6626 displayid_iter_end(&iter);
6627 }
6628
6629 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6630 * all of the values which would have been set from EDID
6631 */
drm_reset_display_info(struct drm_connector * connector)6632 static void drm_reset_display_info(struct drm_connector *connector)
6633 {
6634 struct drm_display_info *info = &connector->display_info;
6635
6636 info->width_mm = 0;
6637 info->height_mm = 0;
6638
6639 info->bpc = 0;
6640 info->color_formats = 0;
6641 info->cea_rev = 0;
6642 info->max_tmds_clock = 0;
6643 info->dvi_dual = false;
6644 info->is_hdmi = false;
6645 info->has_audio = false;
6646 info->has_hdmi_infoframe = false;
6647 info->rgb_quant_range_selectable = false;
6648 memset(&info->hdmi, 0, sizeof(info->hdmi));
6649
6650 info->edid_hdmi_rgb444_dc_modes = 0;
6651 info->edid_hdmi_ycbcr444_dc_modes = 0;
6652
6653 info->non_desktop = 0;
6654 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
6655 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
6656
6657 info->mso_stream_count = 0;
6658 info->mso_pixel_overlap = 0;
6659 info->max_dsc_bpp = 0;
6660
6661 kfree(info->vics);
6662 info->vics = NULL;
6663 info->vics_len = 0;
6664
6665 info->quirks = 0;
6666
6667 info->source_physical_address = CEC_PHYS_ADDR_INVALID;
6668 }
6669
update_displayid_info(struct drm_connector * connector,const struct drm_edid * drm_edid)6670 static void update_displayid_info(struct drm_connector *connector,
6671 const struct drm_edid *drm_edid)
6672 {
6673 struct drm_display_info *info = &connector->display_info;
6674 const struct displayid_block *block;
6675 struct displayid_iter iter;
6676
6677 displayid_iter_edid_begin(drm_edid, &iter);
6678 displayid_iter_for_each(block, &iter) {
6679 drm_dbg_kms(connector->dev,
6680 "[CONNECTOR:%d:%s] DisplayID extension version 0x%02x, primary use 0x%02x\n",
6681 connector->base.id, connector->name,
6682 displayid_version(&iter),
6683 displayid_primary_use(&iter));
6684 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
6685 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR ||
6686 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR))
6687 info->non_desktop = true;
6688
6689 /*
6690 * We're only interested in the base section here, no need to
6691 * iterate further.
6692 */
6693 break;
6694 }
6695 displayid_iter_end(&iter);
6696 }
6697
update_display_info(struct drm_connector * connector,const struct drm_edid * drm_edid)6698 static void update_display_info(struct drm_connector *connector,
6699 const struct drm_edid *drm_edid)
6700 {
6701 struct drm_display_info *info = &connector->display_info;
6702 const struct edid *edid;
6703
6704 drm_reset_display_info(connector);
6705 clear_eld(connector);
6706
6707 if (!drm_edid)
6708 return;
6709
6710 edid = drm_edid->edid;
6711
6712 info->quirks = edid_get_quirks(drm_edid);
6713
6714 info->width_mm = edid->width_cm * 10;
6715 info->height_mm = edid->height_cm * 10;
6716
6717 drm_get_monitor_range(connector, drm_edid);
6718
6719 if (edid->revision < 3)
6720 goto out;
6721
6722 if (!drm_edid_is_digital(drm_edid))
6723 goto out;
6724
6725 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
6726 drm_parse_cea_ext(connector, drm_edid);
6727
6728 update_displayid_info(connector, drm_edid);
6729
6730 /*
6731 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6732 *
6733 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6734 * tells us to assume 8 bpc color depth if the EDID doesn't have
6735 * extensions which tell otherwise.
6736 */
6737 if (info->bpc == 0 && edid->revision == 3 &&
6738 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
6739 info->bpc = 8;
6740 drm_dbg_kms(connector->dev,
6741 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n",
6742 connector->base.id, connector->name, info->bpc);
6743 }
6744
6745 /* Only defined for 1.4 with digital displays */
6746 if (edid->revision < 4)
6747 goto out;
6748
6749 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6750 case DRM_EDID_DIGITAL_DEPTH_6:
6751 info->bpc = 6;
6752 break;
6753 case DRM_EDID_DIGITAL_DEPTH_8:
6754 info->bpc = 8;
6755 break;
6756 case DRM_EDID_DIGITAL_DEPTH_10:
6757 info->bpc = 10;
6758 break;
6759 case DRM_EDID_DIGITAL_DEPTH_12:
6760 info->bpc = 12;
6761 break;
6762 case DRM_EDID_DIGITAL_DEPTH_14:
6763 info->bpc = 14;
6764 break;
6765 case DRM_EDID_DIGITAL_DEPTH_16:
6766 info->bpc = 16;
6767 break;
6768 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6769 default:
6770 info->bpc = 0;
6771 break;
6772 }
6773
6774 drm_dbg_kms(connector->dev,
6775 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6776 connector->base.id, connector->name, info->bpc);
6777
6778 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
6779 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6780 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
6781 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6782
6783 drm_update_mso(connector, drm_edid);
6784
6785 out:
6786 if (info->quirks & EDID_QUIRK_NON_DESKTOP) {
6787 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n",
6788 connector->base.id, connector->name,
6789 info->non_desktop ? " (redundant quirk)" : "");
6790 info->non_desktop = true;
6791 }
6792
6793 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP)
6794 info->max_dsc_bpp = 15;
6795
6796 if (info->quirks & EDID_QUIRK_FORCE_6BPC)
6797 info->bpc = 6;
6798
6799 if (info->quirks & EDID_QUIRK_FORCE_8BPC)
6800 info->bpc = 8;
6801
6802 if (info->quirks & EDID_QUIRK_FORCE_10BPC)
6803 info->bpc = 10;
6804
6805 if (info->quirks & EDID_QUIRK_FORCE_12BPC)
6806 info->bpc = 12;
6807
6808 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */
6809 drm_edid_to_eld(connector, drm_edid);
6810 }
6811
drm_mode_displayid_detailed(struct drm_device * dev,struct displayid_detailed_timings_1 * timings,bool type_7)6812 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
6813 struct displayid_detailed_timings_1 *timings,
6814 bool type_7)
6815 {
6816 struct drm_display_mode *mode;
6817 unsigned pixel_clock = (timings->pixel_clock[0] |
6818 (timings->pixel_clock[1] << 8) |
6819 (timings->pixel_clock[2] << 16)) + 1;
6820 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6821 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6822 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6823 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6824 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6825 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6826 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6827 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6828 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6829 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
6830
6831 mode = drm_mode_create(dev);
6832 if (!mode)
6833 return NULL;
6834
6835 /* resolution is kHz for type VII, and 10 kHz for type I */
6836 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
6837 mode->hdisplay = hactive;
6838 mode->hsync_start = mode->hdisplay + hsync;
6839 mode->hsync_end = mode->hsync_start + hsync_width;
6840 mode->htotal = mode->hdisplay + hblank;
6841
6842 mode->vdisplay = vactive;
6843 mode->vsync_start = mode->vdisplay + vsync;
6844 mode->vsync_end = mode->vsync_start + vsync_width;
6845 mode->vtotal = mode->vdisplay + vblank;
6846
6847 mode->flags = 0;
6848 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6849 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6850 mode->type = DRM_MODE_TYPE_DRIVER;
6851
6852 if (timings->flags & 0x80)
6853 mode->type |= DRM_MODE_TYPE_PREFERRED;
6854 drm_mode_set_name(mode);
6855
6856 return mode;
6857 }
6858
add_displayid_detailed_1_modes(struct drm_connector * connector,const struct displayid_block * block)6859 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
6860 const struct displayid_block *block)
6861 {
6862 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6863 int i;
6864 int num_timings;
6865 struct drm_display_mode *newmode;
6866 int num_modes = 0;
6867 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
6868 /* blocks must be multiple of 20 bytes length */
6869 if (block->num_bytes % 20)
6870 return 0;
6871
6872 num_timings = block->num_bytes / 20;
6873 for (i = 0; i < num_timings; i++) {
6874 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6875
6876 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
6877 if (!newmode)
6878 continue;
6879
6880 drm_mode_probed_add(connector, newmode);
6881 num_modes++;
6882 }
6883 return num_modes;
6884 }
6885
add_displayid_detailed_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)6886 static int add_displayid_detailed_modes(struct drm_connector *connector,
6887 const struct drm_edid *drm_edid)
6888 {
6889 const struct displayid_block *block;
6890 struct displayid_iter iter;
6891 int num_modes = 0;
6892
6893 displayid_iter_edid_begin(drm_edid, &iter);
6894 displayid_iter_for_each(block, &iter) {
6895 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6896 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
6897 num_modes += add_displayid_detailed_1_modes(connector, block);
6898 }
6899 displayid_iter_end(&iter);
6900
6901 return num_modes;
6902 }
6903
_drm_edid_connector_add_modes(struct drm_connector * connector,const struct drm_edid * drm_edid)6904 static int _drm_edid_connector_add_modes(struct drm_connector *connector,
6905 const struct drm_edid *drm_edid)
6906 {
6907 const struct drm_display_info *info = &connector->display_info;
6908 int num_modes = 0;
6909
6910 if (!drm_edid)
6911 return 0;
6912
6913 /*
6914 * EDID spec says modes should be preferred in this order:
6915 * - preferred detailed mode
6916 * - other detailed modes from base block
6917 * - detailed modes from extension blocks
6918 * - CVT 3-byte code modes
6919 * - standard timing codes
6920 * - established timing codes
6921 * - modes inferred from GTF or CVT range information
6922 *
6923 * We get this pretty much right.
6924 *
6925 * XXX order for additional mode types in extension blocks?
6926 */
6927 num_modes += add_detailed_modes(connector, drm_edid);
6928 num_modes += add_cvt_modes(connector, drm_edid);
6929 num_modes += add_standard_modes(connector, drm_edid);
6930 num_modes += add_established_modes(connector, drm_edid);
6931 num_modes += add_cea_modes(connector, drm_edid);
6932 num_modes += add_alternate_cea_modes(connector, drm_edid);
6933 num_modes += add_displayid_detailed_modes(connector, drm_edid);
6934 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
6935 num_modes += add_inferred_modes(connector, drm_edid);
6936
6937 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6938 edid_fixup_preferred(connector);
6939
6940 return num_modes;
6941 }
6942
6943 static void _drm_update_tile_info(struct drm_connector *connector,
6944 const struct drm_edid *drm_edid);
6945
_drm_edid_connector_property_update(struct drm_connector * connector,const struct drm_edid * drm_edid)6946 static int _drm_edid_connector_property_update(struct drm_connector *connector,
6947 const struct drm_edid *drm_edid)
6948 {
6949 struct drm_device *dev = connector->dev;
6950 int ret;
6951
6952 if (connector->edid_blob_ptr) {
6953 const void *old_edid = connector->edid_blob_ptr->data;
6954 size_t old_edid_size = connector->edid_blob_ptr->length;
6955
6956 if (old_edid && !drm_edid_eq(drm_edid, old_edid, old_edid_size)) {
6957 connector->epoch_counter++;
6958 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6959 connector->base.id, connector->name,
6960 connector->epoch_counter);
6961 }
6962 }
6963
6964 ret = drm_property_replace_global_blob(dev,
6965 &connector->edid_blob_ptr,
6966 drm_edid ? drm_edid->size : 0,
6967 drm_edid ? drm_edid->edid : NULL,
6968 &connector->base,
6969 dev->mode_config.edid_property);
6970 if (ret) {
6971 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6972 connector->base.id, connector->name, ret);
6973 goto out;
6974 }
6975
6976 ret = drm_object_property_set_value(&connector->base,
6977 dev->mode_config.non_desktop_property,
6978 connector->display_info.non_desktop);
6979 if (ret) {
6980 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6981 connector->base.id, connector->name, ret);
6982 goto out;
6983 }
6984
6985 ret = drm_connector_set_tile_property(connector);
6986 if (ret) {
6987 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6988 connector->base.id, connector->name, ret);
6989 goto out;
6990 }
6991
6992 out:
6993 return ret;
6994 }
6995
6996 /* For sysfs edid show implementation */
drm_edid_connector_property_show(struct drm_connector * connector,char * buf,loff_t off,size_t count)6997 ssize_t drm_edid_connector_property_show(struct drm_connector *connector,
6998 char *buf, loff_t off, size_t count)
6999 {
7000 const void *edid;
7001 size_t size;
7002 ssize_t ret = 0;
7003
7004 mutex_lock(&connector->dev->mode_config.mutex);
7005
7006 if (!connector->edid_blob_ptr)
7007 goto unlock;
7008
7009 edid = connector->edid_blob_ptr->data;
7010 size = connector->edid_blob_ptr->length;
7011 if (!edid)
7012 goto unlock;
7013
7014 if (off >= size)
7015 goto unlock;
7016
7017 if (off + count > size)
7018 count = size - off;
7019
7020 memcpy(buf, edid + off, count);
7021
7022 ret = count;
7023 unlock:
7024 mutex_unlock(&connector->dev->mode_config.mutex);
7025
7026 return ret;
7027 }
7028
7029 /**
7030 * drm_edid_connector_update - Update connector information from EDID
7031 * @connector: Connector
7032 * @drm_edid: EDID
7033 *
7034 * Update the connector display info, ELD, HDR metadata, relevant properties,
7035 * etc. from the passed in EDID.
7036 *
7037 * If EDID is NULL, reset the information.
7038 *
7039 * Must be called before calling drm_edid_connector_add_modes().
7040 *
7041 * Return: 0 on success, negative error on errors.
7042 */
drm_edid_connector_update(struct drm_connector * connector,const struct drm_edid * drm_edid)7043 int drm_edid_connector_update(struct drm_connector *connector,
7044 const struct drm_edid *drm_edid)
7045 {
7046 update_display_info(connector, drm_edid);
7047
7048 _drm_update_tile_info(connector, drm_edid);
7049
7050 return _drm_edid_connector_property_update(connector, drm_edid);
7051 }
7052 EXPORT_SYMBOL(drm_edid_connector_update);
7053
7054 /**
7055 * drm_edid_connector_add_modes - Update probed modes from the EDID property
7056 * @connector: Connector
7057 *
7058 * Add the modes from the previously updated EDID property to the connector
7059 * probed modes list.
7060 *
7061 * drm_edid_connector_update() must have been called before this to update the
7062 * EDID property.
7063 *
7064 * Return: The number of modes added, or 0 if we couldn't find any.
7065 */
drm_edid_connector_add_modes(struct drm_connector * connector)7066 int drm_edid_connector_add_modes(struct drm_connector *connector)
7067 {
7068 const struct drm_edid *drm_edid = NULL;
7069 int count;
7070
7071 if (connector->edid_blob_ptr)
7072 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data,
7073 connector->edid_blob_ptr->length);
7074
7075 count = _drm_edid_connector_add_modes(connector, drm_edid);
7076
7077 drm_edid_free(drm_edid);
7078
7079 return count;
7080 }
7081 EXPORT_SYMBOL(drm_edid_connector_add_modes);
7082
7083 /**
7084 * drm_connector_update_edid_property - update the edid property of a connector
7085 * @connector: drm connector
7086 * @edid: new value of the edid property
7087 *
7088 * This function creates a new blob modeset object and assigns its id to the
7089 * connector's edid property.
7090 * Since we also parse tile information from EDID's displayID block, we also
7091 * set the connector's tile property here. See drm_connector_set_tile_property()
7092 * for more details.
7093 *
7094 * This function is deprecated. Use drm_edid_connector_update() instead.
7095 *
7096 * Returns:
7097 * Zero on success, negative errno on failure.
7098 */
drm_connector_update_edid_property(struct drm_connector * connector,const struct edid * edid)7099 int drm_connector_update_edid_property(struct drm_connector *connector,
7100 const struct edid *edid)
7101 {
7102 struct drm_edid drm_edid;
7103
7104 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid));
7105 }
7106 EXPORT_SYMBOL(drm_connector_update_edid_property);
7107
7108 /**
7109 * drm_add_edid_modes - add modes from EDID data, if available
7110 * @connector: connector we're probing
7111 * @edid: EDID data
7112 *
7113 * Add the specified modes to the connector's mode list. Also fills out the
7114 * &drm_display_info structure and ELD in @connector with any information which
7115 * can be derived from the edid.
7116 *
7117 * This function is deprecated. Use drm_edid_connector_add_modes() instead.
7118 *
7119 * Return: The number of modes added or 0 if we couldn't find any.
7120 */
drm_add_edid_modes(struct drm_connector * connector,struct edid * edid)7121 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
7122 {
7123 struct drm_edid _drm_edid;
7124 const struct drm_edid *drm_edid;
7125
7126 if (edid && !drm_edid_is_valid(edid)) {
7127 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n",
7128 connector->base.id, connector->name);
7129 edid = NULL;
7130 }
7131
7132 drm_edid = drm_edid_legacy_init(&_drm_edid, edid);
7133
7134 update_display_info(connector, drm_edid);
7135
7136 return _drm_edid_connector_add_modes(connector, drm_edid);
7137 }
7138 EXPORT_SYMBOL(drm_add_edid_modes);
7139
7140 /**
7141 * drm_add_modes_noedid - add modes for the connectors without EDID
7142 * @connector: connector we're probing
7143 * @hdisplay: the horizontal display limit
7144 * @vdisplay: the vertical display limit
7145 *
7146 * Add the specified modes to the connector's mode list. Only when the
7147 * hdisplay/vdisplay is not beyond the given limit, it will be added.
7148 *
7149 * Return: The number of modes added or 0 if we couldn't find any.
7150 */
drm_add_modes_noedid(struct drm_connector * connector,int hdisplay,int vdisplay)7151 int drm_add_modes_noedid(struct drm_connector *connector,
7152 int hdisplay, int vdisplay)
7153 {
7154 int i, count, num_modes = 0;
7155 struct drm_display_mode *mode;
7156 struct drm_device *dev = connector->dev;
7157
7158 count = ARRAY_SIZE(drm_dmt_modes);
7159 if (hdisplay < 0)
7160 hdisplay = 0;
7161 if (vdisplay < 0)
7162 vdisplay = 0;
7163
7164 for (i = 0; i < count; i++) {
7165 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
7166
7167 if (hdisplay && vdisplay) {
7168 /*
7169 * Only when two are valid, they will be used to check
7170 * whether the mode should be added to the mode list of
7171 * the connector.
7172 */
7173 if (ptr->hdisplay > hdisplay ||
7174 ptr->vdisplay > vdisplay)
7175 continue;
7176 }
7177 if (drm_mode_vrefresh(ptr) > 61)
7178 continue;
7179 mode = drm_mode_duplicate(dev, ptr);
7180 if (mode) {
7181 drm_mode_probed_add(connector, mode);
7182 num_modes++;
7183 }
7184 }
7185 return num_modes;
7186 }
7187 EXPORT_SYMBOL(drm_add_modes_noedid);
7188
is_hdmi2_sink(const struct drm_connector * connector)7189 static bool is_hdmi2_sink(const struct drm_connector *connector)
7190 {
7191 /*
7192 * FIXME: sil-sii8620 doesn't have a connector around when
7193 * we need one, so we have to be prepared for a NULL connector.
7194 */
7195 if (!connector)
7196 return true;
7197
7198 return connector->display_info.hdmi.scdc.supported ||
7199 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
7200 }
7201
drm_mode_hdmi_vic(const struct drm_connector * connector,const struct drm_display_mode * mode)7202 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
7203 const struct drm_display_mode *mode)
7204 {
7205 bool has_hdmi_infoframe = connector ?
7206 connector->display_info.has_hdmi_infoframe : false;
7207
7208 if (!has_hdmi_infoframe)
7209 return 0;
7210
7211 /* No HDMI VIC when signalling 3D video format */
7212 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
7213 return 0;
7214
7215 return drm_match_hdmi_mode(mode);
7216 }
7217
drm_mode_cea_vic(const struct drm_connector * connector,const struct drm_display_mode * mode)7218 static u8 drm_mode_cea_vic(const struct drm_connector *connector,
7219 const struct drm_display_mode *mode)
7220 {
7221 /*
7222 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
7223 * we should send its VIC in vendor infoframes, else send the
7224 * VIC in AVI infoframes. Lets check if this mode is present in
7225 * HDMI 1.4b 4K modes
7226 */
7227 if (drm_mode_hdmi_vic(connector, mode))
7228 return 0;
7229
7230 return drm_match_cea_mode(mode);
7231 }
7232
7233 /*
7234 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that
7235 * conform to HDMI 1.4.
7236 *
7237 * HDMI 1.4 (CTA-861-D) VIC range: [1..64]
7238 * HDMI 2.0 (CTA-861-F) VIC range: [1..107]
7239 *
7240 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI
7241 * version.
7242 */
vic_for_avi_infoframe(const struct drm_connector * connector,u8 vic)7243 static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic)
7244 {
7245 if (!is_hdmi2_sink(connector) && vic > 64 &&
7246 !cta_vdb_has_vic(connector, vic))
7247 return 0;
7248
7249 return vic;
7250 }
7251
7252 /**
7253 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
7254 * data from a DRM display mode
7255 * @frame: HDMI AVI infoframe
7256 * @connector: the connector
7257 * @mode: DRM display mode
7258 *
7259 * Return: 0 on success or a negative error code on failure.
7260 */
7261 int
drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode)7262 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
7263 const struct drm_connector *connector,
7264 const struct drm_display_mode *mode)
7265 {
7266 enum hdmi_picture_aspect picture_aspect;
7267 u8 vic, hdmi_vic;
7268
7269 if (!frame || !mode)
7270 return -EINVAL;
7271
7272 hdmi_avi_infoframe_init(frame);
7273
7274 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
7275 frame->pixel_repeat = 1;
7276
7277 vic = drm_mode_cea_vic(connector, mode);
7278 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
7279
7280 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7281
7282 /*
7283 * As some drivers don't support atomic, we can't use connector state.
7284 * So just initialize the frame with default values, just the same way
7285 * as it's done with other properties here.
7286 */
7287 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
7288 frame->itc = 0;
7289
7290 /*
7291 * Populate picture aspect ratio from either
7292 * user input (if specified) or from the CEA/HDMI mode lists.
7293 */
7294 picture_aspect = mode->picture_aspect_ratio;
7295 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
7296 if (vic)
7297 picture_aspect = drm_get_cea_aspect_ratio(vic);
7298 else if (hdmi_vic)
7299 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
7300 }
7301
7302 /*
7303 * The infoframe can't convey anything but none, 4:3
7304 * and 16:9, so if the user has asked for anything else
7305 * we can only satisfy it by specifying the right VIC.
7306 */
7307 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
7308 if (vic) {
7309 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
7310 return -EINVAL;
7311 } else if (hdmi_vic) {
7312 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
7313 return -EINVAL;
7314 } else {
7315 return -EINVAL;
7316 }
7317
7318 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7319 }
7320
7321 frame->video_code = vic_for_avi_infoframe(connector, vic);
7322 frame->picture_aspect = picture_aspect;
7323 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
7324 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
7325
7326 return 0;
7327 }
7328 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
7329
7330 /**
7331 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
7332 * quantization range information
7333 * @frame: HDMI AVI infoframe
7334 * @connector: the connector
7335 * @mode: DRM display mode
7336 * @rgb_quant_range: RGB quantization range (Q)
7337 */
7338 void
drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode,enum hdmi_quantization_range rgb_quant_range)7339 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
7340 const struct drm_connector *connector,
7341 const struct drm_display_mode *mode,
7342 enum hdmi_quantization_range rgb_quant_range)
7343 {
7344 const struct drm_display_info *info = &connector->display_info;
7345
7346 /*
7347 * CEA-861:
7348 * "A Source shall not send a non-zero Q value that does not correspond
7349 * to the default RGB Quantization Range for the transmitted Picture
7350 * unless the Sink indicates support for the Q bit in a Video
7351 * Capabilities Data Block."
7352 *
7353 * HDMI 2.0 recommends sending non-zero Q when it does match the
7354 * default RGB quantization range for the mode, even when QS=0.
7355 */
7356 if (info->rgb_quant_range_selectable ||
7357 rgb_quant_range == drm_default_rgb_quant_range(mode))
7358 frame->quantization_range = rgb_quant_range;
7359 else
7360 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
7361
7362 /*
7363 * CEA-861-F:
7364 * "When transmitting any RGB colorimetry, the Source should set the
7365 * YQ-field to match the RGB Quantization Range being transmitted
7366 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
7367 * set YQ=1) and the Sink shall ignore the YQ-field."
7368 *
7369 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
7370 * by non-zero YQ when receiving RGB. There doesn't seem to be any
7371 * good way to tell which version of CEA-861 the sink supports, so
7372 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
7373 * on CEA-861-F.
7374 */
7375 if (!is_hdmi2_sink(connector) ||
7376 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
7377 frame->ycc_quantization_range =
7378 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
7379 else
7380 frame->ycc_quantization_range =
7381 HDMI_YCC_QUANTIZATION_RANGE_FULL;
7382 }
7383 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
7384
7385 static enum hdmi_3d_structure
s3d_structure_from_display_mode(const struct drm_display_mode * mode)7386 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
7387 {
7388 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
7389
7390 switch (layout) {
7391 case DRM_MODE_FLAG_3D_FRAME_PACKING:
7392 return HDMI_3D_STRUCTURE_FRAME_PACKING;
7393 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
7394 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
7395 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
7396 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
7397 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
7398 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
7399 case DRM_MODE_FLAG_3D_L_DEPTH:
7400 return HDMI_3D_STRUCTURE_L_DEPTH;
7401 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
7402 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
7403 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
7404 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
7405 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
7406 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
7407 default:
7408 return HDMI_3D_STRUCTURE_INVALID;
7409 }
7410 }
7411
7412 /**
7413 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
7414 * data from a DRM display mode
7415 * @frame: HDMI vendor infoframe
7416 * @connector: the connector
7417 * @mode: DRM display mode
7418 *
7419 * Note that there's is a need to send HDMI vendor infoframes only when using a
7420 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
7421 * function will return -EINVAL, error that can be safely ignored.
7422 *
7423 * Return: 0 on success or a negative error code on failure.
7424 */
7425 int
drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe * frame,const struct drm_connector * connector,const struct drm_display_mode * mode)7426 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
7427 const struct drm_connector *connector,
7428 const struct drm_display_mode *mode)
7429 {
7430 /*
7431 * FIXME: sil-sii8620 doesn't have a connector around when
7432 * we need one, so we have to be prepared for a NULL connector.
7433 */
7434 bool has_hdmi_infoframe = connector ?
7435 connector->display_info.has_hdmi_infoframe : false;
7436 int err;
7437
7438 if (!frame || !mode)
7439 return -EINVAL;
7440
7441 if (!has_hdmi_infoframe)
7442 return -EINVAL;
7443
7444 err = hdmi_vendor_infoframe_init(frame);
7445 if (err < 0)
7446 return err;
7447
7448 /*
7449 * Even if it's not absolutely necessary to send the infoframe
7450 * (ie.vic==0 and s3d_struct==0) we will still send it if we
7451 * know that the sink can handle it. This is based on a
7452 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
7453 * have trouble realizing that they should switch from 3D to 2D
7454 * mode if the source simply stops sending the infoframe when
7455 * it wants to switch from 3D to 2D.
7456 */
7457 frame->vic = drm_mode_hdmi_vic(connector, mode);
7458 frame->s3d_struct = s3d_structure_from_display_mode(mode);
7459
7460 return 0;
7461 }
7462 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
7463
drm_parse_tiled_block(struct drm_connector * connector,const struct displayid_block * block)7464 static void drm_parse_tiled_block(struct drm_connector *connector,
7465 const struct displayid_block *block)
7466 {
7467 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
7468 u16 w, h;
7469 u8 tile_v_loc, tile_h_loc;
7470 u8 num_v_tile, num_h_tile;
7471 struct drm_tile_group *tg;
7472
7473 w = tile->tile_size[0] | tile->tile_size[1] << 8;
7474 h = tile->tile_size[2] | tile->tile_size[3] << 8;
7475
7476 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7477 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
7478 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
7479 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
7480
7481 connector->has_tile = true;
7482 if (tile->tile_cap & 0x80)
7483 connector->tile_is_single_monitor = true;
7484
7485 connector->num_h_tile = num_h_tile + 1;
7486 connector->num_v_tile = num_v_tile + 1;
7487 connector->tile_h_loc = tile_h_loc;
7488 connector->tile_v_loc = tile_v_loc;
7489 connector->tile_h_size = w + 1;
7490 connector->tile_v_size = h + 1;
7491
7492 drm_dbg_kms(connector->dev,
7493 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c",
7494 connector->base.id, connector->name,
7495 tile->tile_cap,
7496 connector->tile_h_size, connector->tile_v_size,
7497 connector->num_h_tile, connector->num_v_tile,
7498 connector->tile_h_loc, connector->tile_v_loc,
7499 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
7500
7501 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
7502 if (!tg)
7503 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
7504 if (!tg)
7505 return;
7506
7507 if (connector->tile_group != tg) {
7508 /* if we haven't got a pointer,
7509 take the reference, drop ref to old tile group */
7510 if (connector->tile_group)
7511 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7512 connector->tile_group = tg;
7513 } else {
7514 /* if same tile group, then release the ref we just took. */
7515 drm_mode_put_tile_group(connector->dev, tg);
7516 }
7517 }
7518
displayid_is_tiled_block(const struct displayid_iter * iter,const struct displayid_block * block)7519 static bool displayid_is_tiled_block(const struct displayid_iter *iter,
7520 const struct displayid_block *block)
7521 {
7522 return (displayid_version(iter) < DISPLAY_ID_STRUCTURE_VER_20 &&
7523 block->tag == DATA_BLOCK_TILED_DISPLAY) ||
7524 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
7525 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY);
7526 }
7527
_drm_update_tile_info(struct drm_connector * connector,const struct drm_edid * drm_edid)7528 static void _drm_update_tile_info(struct drm_connector *connector,
7529 const struct drm_edid *drm_edid)
7530 {
7531 const struct displayid_block *block;
7532 struct displayid_iter iter;
7533
7534 connector->has_tile = false;
7535
7536 displayid_iter_edid_begin(drm_edid, &iter);
7537 displayid_iter_for_each(block, &iter) {
7538 if (displayid_is_tiled_block(&iter, block))
7539 drm_parse_tiled_block(connector, block);
7540 }
7541 displayid_iter_end(&iter);
7542
7543 if (!connector->has_tile && connector->tile_group) {
7544 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7545 connector->tile_group = NULL;
7546 }
7547 }
7548
7549 /**
7550 * drm_edid_is_digital - is digital?
7551 * @drm_edid: The EDID
7552 *
7553 * Return true if input is digital.
7554 */
drm_edid_is_digital(const struct drm_edid * drm_edid)7555 bool drm_edid_is_digital(const struct drm_edid *drm_edid)
7556 {
7557 return drm_edid && drm_edid->edid &&
7558 drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL;
7559 }
7560 EXPORT_SYMBOL(drm_edid_is_digital);
7561