1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #ifndef __AMDGPU_MES_H__
25 #define __AMDGPU_MES_H__
26
27 #include "amdgpu_irq.h"
28 #include "kgd_kfd_interface.h"
29 #include "amdgpu_gfx.h"
30 #include "amdgpu_doorbell.h"
31 #include <linux/sched/mm.h>
32
33 #define AMDGPU_MES_MAX_COMPUTE_PIPES 8
34 #define AMDGPU_MES_MAX_GFX_PIPES 2
35 #define AMDGPU_MES_MAX_SDMA_PIPES 2
36
37 #define AMDGPU_MES_API_VERSION_SHIFT 12
38 #define AMDGPU_MES_FEAT_VERSION_SHIFT 24
39
40 #define AMDGPU_MES_VERSION_MASK 0x00000fff
41 #define AMDGPU_MES_API_VERSION_MASK 0x00fff000
42 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000
43
44 enum amdgpu_mes_priority_level {
45 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0,
46 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1,
47 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2,
48 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3,
49 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4,
50 AMDGPU_MES_PRIORITY_NUM_LEVELS
51 };
52
53 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */
54 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */
55
56 struct amdgpu_mes_funcs;
57
58 enum admgpu_mes_pipe {
59 AMDGPU_MES_SCHED_PIPE = 0,
60 AMDGPU_MES_KIQ_PIPE,
61 AMDGPU_MAX_MES_PIPES = 2,
62 };
63
64 struct amdgpu_mes {
65 struct amdgpu_device *adev;
66
67 struct rwlock mutex_hidden;
68
69 struct idr pasid_idr;
70 struct idr gang_id_idr;
71 struct idr queue_id_idr;
72 struct ida doorbell_ida;
73
74 spinlock_t queue_id_lock;
75
76 uint32_t sched_version;
77 uint32_t kiq_version;
78 bool enable_legacy_queue_map;
79
80 uint32_t total_max_queue;
81 uint32_t max_doorbell_slices;
82
83 uint64_t default_process_quantum;
84 uint64_t default_gang_quantum;
85
86 struct amdgpu_ring ring[AMDGPU_MAX_MES_PIPES];
87 spinlock_t ring_lock[AMDGPU_MAX_MES_PIPES];
88
89 const struct firmware *fw[AMDGPU_MAX_MES_PIPES];
90
91 /* mes ucode */
92 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES];
93 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
94 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES];
95 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES];
96
97 /* mes ucode data */
98 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES];
99 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
100 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES];
101 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES];
102
103 /* eop gpu obj */
104 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES];
105 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES];
106
107 void *mqd_backup[AMDGPU_MAX_MES_PIPES];
108 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES];
109
110 uint32_t vmid_mask_gfxhub;
111 uint32_t vmid_mask_mmhub;
112 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];
113 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];
114 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];
115 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];
116 uint32_t sch_ctx_offs[AMDGPU_MAX_MES_PIPES];
117 uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_PIPES];
118 uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_PIPES];
119 uint32_t query_status_fence_offs[AMDGPU_MAX_MES_PIPES];
120 uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_PIPES];
121 uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_PIPES];
122 uint32_t read_val_offs;
123 uint64_t read_val_gpu_addr;
124 uint32_t *read_val_ptr;
125
126 #ifdef notyet
127 uint32_t saved_flags;
128 #endif
129
130 /* initialize kiq pipe */
131 int (*kiq_hw_init)(struct amdgpu_device *adev);
132 int (*kiq_hw_fini)(struct amdgpu_device *adev);
133
134 /* MES doorbells */
135 uint32_t db_start_dw_offset;
136 uint32_t num_mes_dbs;
137 unsigned long *doorbell_bitmap;
138
139 /* MES event log buffer */
140 uint32_t event_log_size;
141 struct amdgpu_bo *event_log_gpu_obj;
142 uint64_t event_log_gpu_addr;
143 void *event_log_cpu_addr;
144
145 /* ip specific functions */
146 const struct amdgpu_mes_funcs *funcs;
147
148 /* mes resource_1 bo*/
149 struct amdgpu_bo *resource_1;
150 uint64_t resource_1_gpu_addr;
151 void *resource_1_addr;
152
153 };
154
155 struct amdgpu_mes_process {
156 int pasid;
157 struct amdgpu_vm *vm;
158 uint64_t pd_gpu_addr;
159 struct amdgpu_bo *proc_ctx_bo;
160 uint64_t proc_ctx_gpu_addr;
161 void *proc_ctx_cpu_ptr;
162 uint64_t process_quantum;
163 struct list_head gang_list;
164 uint32_t doorbell_index;
165 struct mutex doorbell_lock;
166 };
167
168 struct amdgpu_mes_gang {
169 int gang_id;
170 int priority;
171 int inprocess_gang_priority;
172 int global_priority_level;
173 struct list_head list;
174 struct amdgpu_mes_process *process;
175 struct amdgpu_bo *gang_ctx_bo;
176 uint64_t gang_ctx_gpu_addr;
177 void *gang_ctx_cpu_ptr;
178 uint64_t gang_quantum;
179 struct list_head queue_list;
180 };
181
182 struct amdgpu_mes_queue {
183 struct list_head list;
184 struct amdgpu_mes_gang *gang;
185 int queue_id;
186 uint64_t doorbell_off;
187 struct amdgpu_bo *mqd_obj;
188 void *mqd_cpu_ptr;
189 uint64_t mqd_gpu_addr;
190 uint64_t wptr_gpu_addr;
191 int queue_type;
192 int paging;
193 struct amdgpu_ring *ring;
194 };
195
196 struct amdgpu_mes_queue_properties {
197 int queue_type;
198 uint64_t hqd_base_gpu_addr;
199 uint64_t rptr_gpu_addr;
200 uint64_t wptr_gpu_addr;
201 uint64_t wptr_mc_addr;
202 uint32_t queue_size;
203 uint64_t eop_gpu_addr;
204 uint32_t hqd_pipe_priority;
205 uint32_t hqd_queue_priority;
206 bool paging;
207 struct amdgpu_ring *ring;
208 /* out */
209 uint64_t doorbell_off;
210 };
211
212 struct amdgpu_mes_gang_properties {
213 uint32_t priority;
214 uint32_t gang_quantum;
215 uint32_t inprocess_gang_priority;
216 uint32_t priority_level;
217 int global_priority_level;
218 };
219
220 struct mes_add_queue_input {
221 uint32_t process_id;
222 uint64_t page_table_base_addr;
223 uint64_t process_va_start;
224 uint64_t process_va_end;
225 uint64_t process_quantum;
226 uint64_t process_context_addr;
227 uint64_t gang_quantum;
228 uint64_t gang_context_addr;
229 uint32_t inprocess_gang_priority;
230 uint32_t gang_global_priority_level;
231 uint32_t doorbell_offset;
232 uint64_t mqd_addr;
233 uint64_t wptr_addr;
234 uint64_t wptr_mc_addr;
235 uint32_t queue_type;
236 uint32_t paging;
237 uint32_t gws_base;
238 uint32_t gws_size;
239 uint64_t tba_addr;
240 uint64_t tma_addr;
241 uint32_t trap_en;
242 uint32_t skip_process_ctx_clear;
243 uint32_t is_kfd_process;
244 uint32_t is_aql_queue;
245 uint32_t queue_size;
246 uint32_t exclusively_scheduled;
247 };
248
249 struct mes_remove_queue_input {
250 uint32_t doorbell_offset;
251 uint64_t gang_context_addr;
252 };
253
254 struct mes_reset_queue_input {
255 uint32_t doorbell_offset;
256 uint64_t gang_context_addr;
257 bool use_mmio;
258 uint32_t queue_type;
259 uint32_t me_id;
260 uint32_t pipe_id;
261 uint32_t queue_id;
262 uint32_t xcc_id;
263 uint32_t vmid;
264 };
265
266 struct mes_map_legacy_queue_input {
267 uint32_t queue_type;
268 uint32_t doorbell_offset;
269 uint32_t pipe_id;
270 uint32_t queue_id;
271 uint64_t mqd_addr;
272 uint64_t wptr_addr;
273 };
274
275 struct mes_unmap_legacy_queue_input {
276 enum amdgpu_unmap_queues_action action;
277 uint32_t queue_type;
278 uint32_t doorbell_offset;
279 uint32_t pipe_id;
280 uint32_t queue_id;
281 uint64_t trail_fence_addr;
282 uint64_t trail_fence_data;
283 };
284
285 struct mes_suspend_gang_input {
286 bool suspend_all_gangs;
287 uint64_t gang_context_addr;
288 uint64_t suspend_fence_addr;
289 uint32_t suspend_fence_value;
290 };
291
292 struct mes_resume_gang_input {
293 bool resume_all_gangs;
294 uint64_t gang_context_addr;
295 };
296
297 struct mes_reset_legacy_queue_input {
298 uint32_t queue_type;
299 uint32_t doorbell_offset;
300 bool use_mmio;
301 uint32_t me_id;
302 uint32_t pipe_id;
303 uint32_t queue_id;
304 uint64_t mqd_addr;
305 uint64_t wptr_addr;
306 uint32_t vmid;
307 };
308
309 enum mes_misc_opcode {
310 MES_MISC_OP_WRITE_REG,
311 MES_MISC_OP_READ_REG,
312 MES_MISC_OP_WRM_REG_WAIT,
313 MES_MISC_OP_WRM_REG_WR_WAIT,
314 MES_MISC_OP_SET_SHADER_DEBUGGER,
315 };
316
317 struct mes_misc_op_input {
318 enum mes_misc_opcode op;
319
320 union {
321 struct {
322 uint32_t reg_offset;
323 uint64_t buffer_addr;
324 } read_reg;
325
326 struct {
327 uint32_t reg_offset;
328 uint32_t reg_value;
329 } write_reg;
330
331 struct {
332 uint32_t ref;
333 uint32_t mask;
334 uint32_t reg0;
335 uint32_t reg1;
336 } wrm_reg;
337
338 struct {
339 uint64_t process_context_addr;
340 union {
341 struct {
342 uint32_t single_memop : 1;
343 uint32_t single_alu_op : 1;
344 uint32_t reserved: 29;
345 uint32_t process_ctx_flush: 1;
346 };
347 uint32_t u32all;
348 } flags;
349 uint32_t spi_gdbg_per_vmid_cntl;
350 uint32_t tcp_watch_cntl[4];
351 uint32_t trap_en;
352 } set_shader_debugger;
353 };
354 };
355
356 struct amdgpu_mes_funcs {
357 int (*add_hw_queue)(struct amdgpu_mes *mes,
358 struct mes_add_queue_input *input);
359
360 int (*remove_hw_queue)(struct amdgpu_mes *mes,
361 struct mes_remove_queue_input *input);
362
363 int (*map_legacy_queue)(struct amdgpu_mes *mes,
364 struct mes_map_legacy_queue_input *input);
365
366 int (*unmap_legacy_queue)(struct amdgpu_mes *mes,
367 struct mes_unmap_legacy_queue_input *input);
368
369 int (*suspend_gang)(struct amdgpu_mes *mes,
370 struct mes_suspend_gang_input *input);
371
372 int (*resume_gang)(struct amdgpu_mes *mes,
373 struct mes_resume_gang_input *input);
374
375 int (*misc_op)(struct amdgpu_mes *mes,
376 struct mes_misc_op_input *input);
377
378 int (*reset_legacy_queue)(struct amdgpu_mes *mes,
379 struct mes_reset_legacy_queue_input *input);
380
381 int (*reset_hw_queue)(struct amdgpu_mes *mes,
382 struct mes_reset_queue_input *input);
383 };
384
385 #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev))
386 #define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev))
387
388 int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs);
389
390 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe);
391 int amdgpu_mes_init(struct amdgpu_device *adev);
392 void amdgpu_mes_fini(struct amdgpu_device *adev);
393
394 int amdgpu_mes_create_process(struct amdgpu_device *adev, int pasid,
395 struct amdgpu_vm *vm);
396 void amdgpu_mes_destroy_process(struct amdgpu_device *adev, int pasid);
397
398 int amdgpu_mes_add_gang(struct amdgpu_device *adev, int pasid,
399 struct amdgpu_mes_gang_properties *gprops,
400 int *gang_id);
401 int amdgpu_mes_remove_gang(struct amdgpu_device *adev, int gang_id);
402
403 int amdgpu_mes_suspend(struct amdgpu_device *adev);
404 int amdgpu_mes_resume(struct amdgpu_device *adev);
405
406 int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id,
407 struct amdgpu_mes_queue_properties *qprops,
408 int *queue_id);
409 int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id);
410 int amdgpu_mes_reset_hw_queue(struct amdgpu_device *adev, int queue_id);
411 int amdgpu_mes_reset_hw_queue_mmio(struct amdgpu_device *adev, int queue_type,
412 int me_id, int pipe_id, int queue_id, int vmid);
413
414 int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev,
415 struct amdgpu_ring *ring);
416 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,
417 struct amdgpu_ring *ring,
418 enum amdgpu_unmap_queues_action action,
419 u64 gpu_addr, u64 seq);
420 int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev,
421 struct amdgpu_ring *ring,
422 unsigned int vmid,
423 bool use_mmio);
424
425 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg);
426 int amdgpu_mes_wreg(struct amdgpu_device *adev,
427 uint32_t reg, uint32_t val);
428 int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg,
429 uint32_t val, uint32_t mask);
430 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev,
431 uint32_t reg0, uint32_t reg1,
432 uint32_t ref, uint32_t mask);
433 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev,
434 uint64_t process_context_addr,
435 uint32_t spi_gdbg_per_vmid_cntl,
436 const uint32_t *tcp_watch_cntl,
437 uint32_t flags,
438 bool trap_en);
439 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev,
440 uint64_t process_context_addr);
441 int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,
442 int queue_type, int idx,
443 struct amdgpu_mes_ctx_data *ctx_data,
444 struct amdgpu_ring **out);
445 void amdgpu_mes_remove_ring(struct amdgpu_device *adev,
446 struct amdgpu_ring *ring);
447
448 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev,
449 enum amdgpu_mes_priority_level prio);
450
451 int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev,
452 struct amdgpu_mes_ctx_data *ctx_data);
453 void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data);
454 int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev,
455 struct amdgpu_vm *vm,
456 struct amdgpu_mes_ctx_data *ctx_data);
457 int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev,
458 struct amdgpu_mes_ctx_data *ctx_data);
459
460 int amdgpu_mes_self_test(struct amdgpu_device *adev);
461
462 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev);
463
464 /*
465 * MES lock can be taken in MMU notifiers.
466 *
467 * A bit more detail about why to set no-FS reclaim with MES lock:
468 *
469 * The purpose of the MMU notifier is to stop GPU access to memory so
470 * that the Linux VM subsystem can move pages around safely. This is
471 * done by preempting user mode queues for the affected process. When
472 * MES is used, MES lock needs to be taken to preempt the queues.
473 *
474 * The MMU notifier callback entry point in the driver is
475 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from
476 * there is:
477 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm ->
478 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues
479 *
480 * The last part of the chain is a function pointer where we take the
481 * MES lock.
482 *
483 * The problem with taking locks in the MMU notifier is, that MMU
484 * notifiers can be called in reclaim-FS context. That's where the
485 * kernel frees up pages to make room for new page allocations under
486 * memory pressure. While we are running in reclaim-FS context, we must
487 * not trigger another memory reclaim operation because that would
488 * recursively reenter the reclaim code and cause a deadlock. The
489 * memalloc_nofs_save/restore calls guarantee that.
490 *
491 * In addition we also need to avoid lock dependencies on other locks taken
492 * under the MES lock, for example reservation locks. Here is a possible
493 * scenario of a deadlock:
494 * Thread A: takes and holds reservation lock | triggers reclaim-FS |
495 * MMU notifier | blocks trying to take MES lock
496 * Thread B: takes and holds MES lock | blocks trying to take reservation lock
497 *
498 * In this scenario Thread B gets involved in a deadlock even without
499 * triggering a reclaim-FS operation itself.
500 * To fix this and break the lock dependency chain you'd need to either:
501 * 1. protect reservation locks with memalloc_nofs_save/restore, or
502 * 2. avoid taking reservation locks under the MES lock.
503 *
504 * Reservation locks are taken all over the kernel in different subsystems, we
505 * have no control over them and their lock dependencies.So the only workable
506 * solution is to avoid taking other locks under the MES lock.
507 * As a result, make sure no reclaim-FS happens while holding this lock anywhere
508 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context.
509 */
amdgpu_mes_lock(struct amdgpu_mes * mes)510 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes)
511 {
512 mutex_lock(&mes->mutex_hidden);
513 #ifdef notyet
514 mes->saved_flags = memalloc_noreclaim_save();
515 #endif
516 }
517
amdgpu_mes_unlock(struct amdgpu_mes * mes)518 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes)
519 {
520 #ifdef notyet
521 memalloc_noreclaim_restore(mes->saved_flags);
522 #endif
523 mutex_unlock(&mes->mutex_hidden);
524 }
525
526 bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev);
527 #endif /* __AMDGPU_MES_H__ */
528