1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: stable/9/sys/dev/drm2/radeon/radeon_atombios.c 254885 2013-08-25 19:37:15Z dumbbell $");
29
30 #include <dev/drm2/drmP.h>
31 #include <dev/drm2/radeon/radeon_drm.h>
32 #include "radeon.h"
33 #include "radeon_asic.h" /* Declares several prototypes; clang is pleased. */
34
35 #include "atom.h"
36 #include "atom-bits.h"
37
38 /* local */
39 static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
40 u16 voltage_id, u16 *voltage);
41
42 union atom_supported_devices {
43 struct _ATOM_SUPPORTED_DEVICES_INFO info;
44 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
45 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
46 };
47
radeon_lookup_i2c_gpio_quirks(struct radeon_device * rdev,ATOM_GPIO_I2C_ASSIGMENT * gpio,u8 index)48 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
49 ATOM_GPIO_I2C_ASSIGMENT *gpio,
50 u8 index)
51 {
52 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
53 if ((rdev->family == CHIP_R420) ||
54 (rdev->family == CHIP_R423) ||
55 (rdev->family == CHIP_RV410)) {
56 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
57 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
58 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
59 gpio->ucClkMaskShift = 0x19;
60 gpio->ucDataMaskShift = 0x18;
61 }
62 }
63
64 /* some evergreen boards have bad data for this entry */
65 if (ASIC_IS_DCE4(rdev)) {
66 if ((index == 7) &&
67 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
68 (gpio->sucI2cId.ucAccess == 0)) {
69 gpio->sucI2cId.ucAccess = 0x97;
70 gpio->ucDataMaskShift = 8;
71 gpio->ucDataEnShift = 8;
72 gpio->ucDataY_Shift = 8;
73 gpio->ucDataA_Shift = 8;
74 }
75 }
76
77 /* some DCE3 boards have bad data for this entry */
78 if (ASIC_IS_DCE3(rdev)) {
79 if ((index == 4) &&
80 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
81 (gpio->sucI2cId.ucAccess == 0x94))
82 gpio->sucI2cId.ucAccess = 0x14;
83 }
84 }
85
radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT * gpio)86 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
87 {
88 struct radeon_i2c_bus_rec i2c;
89
90 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
91
92 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
93 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
94 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
95 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
96 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
97 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
98 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
99 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
100 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
101 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
102 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
103 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
104 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
105 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
106 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
107 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
108
109 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
110 i2c.hw_capable = true;
111 else
112 i2c.hw_capable = false;
113
114 if (gpio->sucI2cId.ucAccess == 0xa0)
115 i2c.mm_i2c = true;
116 else
117 i2c.mm_i2c = false;
118
119 i2c.i2c_id = gpio->sucI2cId.ucAccess;
120
121 if (i2c.mask_clk_reg)
122 i2c.valid = true;
123 else
124 i2c.valid = false;
125
126 return i2c;
127 }
128
radeon_lookup_i2c_gpio(struct radeon_device * rdev,uint8_t id)129 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
130 uint8_t id)
131 {
132 struct atom_context *ctx = rdev->mode_info.atom_context;
133 ATOM_GPIO_I2C_ASSIGMENT *gpio;
134 struct radeon_i2c_bus_rec i2c;
135 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
136 struct _ATOM_GPIO_I2C_INFO *i2c_info;
137 uint16_t data_offset, size;
138 int i, num_indices;
139
140 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
141 i2c.valid = false;
142
143 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
144 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)((char *)ctx->bios + data_offset);
145
146 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
147 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
148
149 for (i = 0; i < num_indices; i++) {
150 gpio = &i2c_info->asGPIO_Info[i];
151
152 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
153
154 if (gpio->sucI2cId.ucAccess == id) {
155 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
156 break;
157 }
158 }
159 }
160
161 return i2c;
162 }
163
radeon_atombios_i2c_init(struct radeon_device * rdev)164 void radeon_atombios_i2c_init(struct radeon_device *rdev)
165 {
166 struct atom_context *ctx = rdev->mode_info.atom_context;
167 ATOM_GPIO_I2C_ASSIGMENT *gpio;
168 struct radeon_i2c_bus_rec i2c;
169 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
170 struct _ATOM_GPIO_I2C_INFO *i2c_info;
171 uint16_t data_offset, size;
172 int i, num_indices;
173 char stmp[32];
174
175 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
176 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)((char *)ctx->bios + data_offset);
177
178 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
179 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
180
181 for (i = 0; i < num_indices; i++) {
182 gpio = &i2c_info->asGPIO_Info[i];
183
184 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
185
186 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
187
188 if (i2c.valid) {
189 sprintf(stmp, "0x%x", i2c.i2c_id);
190 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
191 }
192 }
193 }
194 }
195
radeon_lookup_gpio(struct radeon_device * rdev,u8 id)196 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
197 u8 id)
198 {
199 struct atom_context *ctx = rdev->mode_info.atom_context;
200 struct radeon_gpio_rec gpio;
201 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
202 struct _ATOM_GPIO_PIN_LUT *gpio_info;
203 ATOM_GPIO_PIN_ASSIGNMENT *pin;
204 u16 data_offset, size;
205 int i, num_indices;
206
207 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
208 gpio.valid = false;
209
210 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
211 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)((char *)ctx->bios + data_offset);
212
213 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
214 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
215
216 for (i = 0; i < num_indices; i++) {
217 pin = &gpio_info->asGPIO_Pin[i];
218 if (id == pin->ucGPIO_ID) {
219 gpio.id = pin->ucGPIO_ID;
220 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
221 gpio.mask = (1 << pin->ucGpioPinBitShift);
222 gpio.valid = true;
223 break;
224 }
225 }
226 }
227
228 return gpio;
229 }
230
radeon_atom_get_hpd_info_from_gpio(struct radeon_device * rdev,struct radeon_gpio_rec * gpio)231 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
232 struct radeon_gpio_rec *gpio)
233 {
234 struct radeon_hpd hpd;
235 u32 reg;
236
237 memset(&hpd, 0, sizeof(struct radeon_hpd));
238
239 if (ASIC_IS_DCE6(rdev))
240 reg = SI_DC_GPIO_HPD_A;
241 else if (ASIC_IS_DCE4(rdev))
242 reg = EVERGREEN_DC_GPIO_HPD_A;
243 else
244 reg = AVIVO_DC_GPIO_HPD_A;
245
246 hpd.gpio = *gpio;
247 if (gpio->reg == reg) {
248 switch(gpio->mask) {
249 case (1 << 0):
250 hpd.hpd = RADEON_HPD_1;
251 break;
252 case (1 << 8):
253 hpd.hpd = RADEON_HPD_2;
254 break;
255 case (1 << 16):
256 hpd.hpd = RADEON_HPD_3;
257 break;
258 case (1 << 24):
259 hpd.hpd = RADEON_HPD_4;
260 break;
261 case (1 << 26):
262 hpd.hpd = RADEON_HPD_5;
263 break;
264 case (1 << 28):
265 hpd.hpd = RADEON_HPD_6;
266 break;
267 default:
268 hpd.hpd = RADEON_HPD_NONE;
269 break;
270 }
271 } else
272 hpd.hpd = RADEON_HPD_NONE;
273 return hpd;
274 }
275
radeon_atom_apply_quirks(struct drm_device * dev,uint32_t supported_device,int * connector_type,struct radeon_i2c_bus_rec * i2c_bus,uint16_t * line_mux,struct radeon_hpd * hpd)276 static bool radeon_atom_apply_quirks(struct drm_device *dev,
277 uint32_t supported_device,
278 int *connector_type,
279 struct radeon_i2c_bus_rec *i2c_bus,
280 uint16_t *line_mux,
281 struct radeon_hpd *hpd)
282 {
283
284 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
285 if ((dev->pci_device == 0x791e) &&
286 (dev->pci_subvendor == 0x1043) &&
287 (dev->pci_subdevice == 0x826d)) {
288 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
289 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
290 *connector_type = DRM_MODE_CONNECTOR_DVID;
291 }
292
293 /* Asrock RS600 board lists the DVI port as HDMI */
294 if ((dev->pci_device == 0x7941) &&
295 (dev->pci_subvendor == 0x1849) &&
296 (dev->pci_subdevice == 0x7941)) {
297 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
298 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
299 *connector_type = DRM_MODE_CONNECTOR_DVID;
300 }
301
302 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
303 if ((dev->pci_device == 0x796e) &&
304 (dev->pci_subvendor == 0x1462) &&
305 (dev->pci_subdevice == 0x7302)) {
306 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
307 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
308 return false;
309 }
310
311 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
312 if ((dev->pci_device == 0x7941) &&
313 (dev->pci_subvendor == 0x147b) &&
314 (dev->pci_subdevice == 0x2412)) {
315 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
316 return false;
317 }
318
319 /* Falcon NW laptop lists vga ddc line for LVDS */
320 if ((dev->pci_device == 0x5653) &&
321 (dev->pci_subvendor == 0x1462) &&
322 (dev->pci_subdevice == 0x0291)) {
323 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
324 i2c_bus->valid = false;
325 *line_mux = 53;
326 }
327 }
328
329 /* HIS X1300 is DVI+VGA, not DVI+DVI */
330 if ((dev->pci_device == 0x7146) &&
331 (dev->pci_subvendor == 0x17af) &&
332 (dev->pci_subdevice == 0x2058)) {
333 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
334 return false;
335 }
336
337 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
338 if ((dev->pci_device == 0x7142) &&
339 (dev->pci_subvendor == 0x1458) &&
340 (dev->pci_subdevice == 0x2134)) {
341 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
342 return false;
343 }
344
345
346 /* Funky macbooks */
347 if ((dev->pci_device == 0x71C5) &&
348 (dev->pci_subvendor == 0x106b) &&
349 (dev->pci_subdevice == 0x0080)) {
350 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
351 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
352 return false;
353 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
354 *line_mux = 0x90;
355 }
356
357 /* mac rv630, rv730, others */
358 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
359 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
360 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
361 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
362 }
363
364 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
365 if ((dev->pci_device == 0x9598) &&
366 (dev->pci_subvendor == 0x1043) &&
367 (dev->pci_subdevice == 0x01da)) {
368 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
369 *connector_type = DRM_MODE_CONNECTOR_DVII;
370 }
371 }
372
373 /* ASUS HD 3600 board lists the DVI port as HDMI */
374 if ((dev->pci_device == 0x9598) &&
375 (dev->pci_subvendor == 0x1043) &&
376 (dev->pci_subdevice == 0x01e4)) {
377 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
378 *connector_type = DRM_MODE_CONNECTOR_DVII;
379 }
380 }
381
382 /* ASUS HD 3450 board lists the DVI port as HDMI */
383 if ((dev->pci_device == 0x95C5) &&
384 (dev->pci_subvendor == 0x1043) &&
385 (dev->pci_subdevice == 0x01e2)) {
386 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
387 *connector_type = DRM_MODE_CONNECTOR_DVII;
388 }
389 }
390
391 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
392 * HDMI + VGA reporting as HDMI
393 */
394 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
395 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
396 *connector_type = DRM_MODE_CONNECTOR_VGA;
397 *line_mux = 0;
398 }
399 }
400
401 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
402 * on the laptop and a DVI port on the docking station and
403 * both share the same encoder, hpd pin, and ddc line.
404 * So while the bios table is technically correct,
405 * we drop the DVI port here since xrandr has no concept of
406 * encoders and will try and drive both connectors
407 * with different crtcs which isn't possible on the hardware
408 * side and leaves no crtcs for LVDS or VGA.
409 */
410 if (((dev->pci_device == 0x95c4) || (dev->pci_device == 0x9591)) &&
411 (dev->pci_subvendor == 0x1025) &&
412 (dev->pci_subdevice == 0x013c)) {
413 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
414 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
415 /* actually it's a DVI-D port not DVI-I */
416 *connector_type = DRM_MODE_CONNECTOR_DVID;
417 return false;
418 }
419 }
420
421 /* XFX Pine Group device rv730 reports no VGA DDC lines
422 * even though they are wired up to record 0x93
423 */
424 if ((dev->pci_device == 0x9498) &&
425 (dev->pci_subvendor == 0x1682) &&
426 (dev->pci_subdevice == 0x2452) &&
427 (i2c_bus->valid == false) &&
428 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
429 struct radeon_device *rdev = dev->dev_private;
430 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
431 }
432
433 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
434 if (((dev->pci_device == 0x9802) || (dev->pci_device == 0x9806)) &&
435 (dev->pci_subvendor == 0x1734) &&
436 (dev->pci_subdevice == 0x11bd)) {
437 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
438 *connector_type = DRM_MODE_CONNECTOR_DVII;
439 *line_mux = 0x3103;
440 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
441 *connector_type = DRM_MODE_CONNECTOR_DVII;
442 }
443 }
444
445
446 return true;
447 }
448
449 const int supported_devices_connector_convert[] = {
450 DRM_MODE_CONNECTOR_Unknown,
451 DRM_MODE_CONNECTOR_VGA,
452 DRM_MODE_CONNECTOR_DVII,
453 DRM_MODE_CONNECTOR_DVID,
454 DRM_MODE_CONNECTOR_DVIA,
455 DRM_MODE_CONNECTOR_SVIDEO,
456 DRM_MODE_CONNECTOR_Composite,
457 DRM_MODE_CONNECTOR_LVDS,
458 DRM_MODE_CONNECTOR_Unknown,
459 DRM_MODE_CONNECTOR_Unknown,
460 DRM_MODE_CONNECTOR_HDMIA,
461 DRM_MODE_CONNECTOR_HDMIB,
462 DRM_MODE_CONNECTOR_Unknown,
463 DRM_MODE_CONNECTOR_Unknown,
464 DRM_MODE_CONNECTOR_9PinDIN,
465 DRM_MODE_CONNECTOR_DisplayPort
466 };
467
468 const uint16_t supported_devices_connector_object_id_convert[] = {
469 CONNECTOR_OBJECT_ID_NONE,
470 CONNECTOR_OBJECT_ID_VGA,
471 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
472 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
473 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
474 CONNECTOR_OBJECT_ID_COMPOSITE,
475 CONNECTOR_OBJECT_ID_SVIDEO,
476 CONNECTOR_OBJECT_ID_LVDS,
477 CONNECTOR_OBJECT_ID_9PIN_DIN,
478 CONNECTOR_OBJECT_ID_9PIN_DIN,
479 CONNECTOR_OBJECT_ID_DISPLAYPORT,
480 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
481 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
482 CONNECTOR_OBJECT_ID_SVIDEO
483 };
484
485 const int object_connector_convert[] = {
486 DRM_MODE_CONNECTOR_Unknown,
487 DRM_MODE_CONNECTOR_DVII,
488 DRM_MODE_CONNECTOR_DVII,
489 DRM_MODE_CONNECTOR_DVID,
490 DRM_MODE_CONNECTOR_DVID,
491 DRM_MODE_CONNECTOR_VGA,
492 DRM_MODE_CONNECTOR_Composite,
493 DRM_MODE_CONNECTOR_SVIDEO,
494 DRM_MODE_CONNECTOR_Unknown,
495 DRM_MODE_CONNECTOR_Unknown,
496 DRM_MODE_CONNECTOR_9PinDIN,
497 DRM_MODE_CONNECTOR_Unknown,
498 DRM_MODE_CONNECTOR_HDMIA,
499 DRM_MODE_CONNECTOR_HDMIB,
500 DRM_MODE_CONNECTOR_LVDS,
501 DRM_MODE_CONNECTOR_9PinDIN,
502 DRM_MODE_CONNECTOR_Unknown,
503 DRM_MODE_CONNECTOR_Unknown,
504 DRM_MODE_CONNECTOR_Unknown,
505 DRM_MODE_CONNECTOR_DisplayPort,
506 DRM_MODE_CONNECTOR_eDP,
507 DRM_MODE_CONNECTOR_Unknown
508 };
509
radeon_get_atom_connector_info_from_object_table(struct drm_device * dev)510 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
511 {
512 struct radeon_device *rdev = dev->dev_private;
513 struct radeon_mode_info *mode_info = &rdev->mode_info;
514 struct atom_context *ctx = mode_info->atom_context;
515 int index = GetIndexIntoMasterTable(DATA, Object_Header);
516 u16 size, data_offset;
517 u8 frev, crev;
518 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
519 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
520 ATOM_OBJECT_TABLE *router_obj;
521 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
522 ATOM_OBJECT_HEADER *obj_header;
523 int i, j, k, path_size, device_support;
524 int connector_type;
525 u16 igp_lane_info, conn_id, connector_object_id;
526 struct radeon_i2c_bus_rec ddc_bus;
527 struct radeon_router router;
528 struct radeon_gpio_rec gpio;
529 struct radeon_hpd hpd;
530
531 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
532 return false;
533
534 if (crev < 2)
535 return false;
536
537 obj_header = (ATOM_OBJECT_HEADER *) ((char *)ctx->bios + data_offset);
538 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
539 ((char *)ctx->bios + data_offset +
540 le16_to_cpu(obj_header->usDisplayPathTableOffset));
541 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
542 ((char *)ctx->bios + data_offset +
543 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
544 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
545 ((char *)ctx->bios + data_offset +
546 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
547 router_obj = (ATOM_OBJECT_TABLE *)
548 ((char *)ctx->bios + data_offset +
549 le16_to_cpu(obj_header->usRouterObjectTableOffset));
550 device_support = le16_to_cpu(obj_header->usDeviceSupport);
551
552 path_size = 0;
553 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
554 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
555 ATOM_DISPLAY_OBJECT_PATH *path;
556 addr += path_size;
557 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
558 path_size += le16_to_cpu(path->usSize);
559
560 if (device_support & le16_to_cpu(path->usDeviceTag)) {
561 uint8_t con_obj_id, con_obj_num, con_obj_type;
562
563 con_obj_id =
564 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
565 >> OBJECT_ID_SHIFT;
566 con_obj_num =
567 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
568 >> ENUM_ID_SHIFT;
569 con_obj_type =
570 (le16_to_cpu(path->usConnObjectId) &
571 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
572
573 /* TODO CV support */
574 if (le16_to_cpu(path->usDeviceTag) ==
575 ATOM_DEVICE_CV_SUPPORT)
576 continue;
577
578 /* IGP chips */
579 if ((rdev->flags & RADEON_IS_IGP) &&
580 (con_obj_id ==
581 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
582 uint16_t igp_offset = 0;
583 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
584
585 index =
586 GetIndexIntoMasterTable(DATA,
587 IntegratedSystemInfo);
588
589 if (atom_parse_data_header(ctx, index, &size, &frev,
590 &crev, &igp_offset)) {
591
592 if (crev >= 2) {
593 igp_obj =
594 (ATOM_INTEGRATED_SYSTEM_INFO_V2
595 *) ((char *)ctx->bios + igp_offset);
596
597 if (igp_obj) {
598 uint32_t slot_config, ct;
599
600 if (con_obj_num == 1)
601 slot_config =
602 igp_obj->
603 ulDDISlot1Config;
604 else
605 slot_config =
606 igp_obj->
607 ulDDISlot2Config;
608
609 ct = (slot_config >> 16) & 0xff;
610 connector_type =
611 object_connector_convert
612 [ct];
613 connector_object_id = ct;
614 igp_lane_info =
615 slot_config & 0xffff;
616 } else
617 continue;
618 } else
619 continue;
620 } else {
621 igp_lane_info = 0;
622 connector_type =
623 object_connector_convert[con_obj_id];
624 connector_object_id = con_obj_id;
625 }
626 } else {
627 igp_lane_info = 0;
628 connector_type =
629 object_connector_convert[con_obj_id];
630 connector_object_id = con_obj_id;
631 }
632
633 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
634 continue;
635
636 router.ddc_valid = false;
637 router.cd_valid = false;
638 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
639 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
640
641 grph_obj_id =
642 (le16_to_cpu(path->usGraphicObjIds[j]) &
643 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
644 grph_obj_num =
645 (le16_to_cpu(path->usGraphicObjIds[j]) &
646 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
647 grph_obj_type =
648 (le16_to_cpu(path->usGraphicObjIds[j]) &
649 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
650
651 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
652 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
653 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
654 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
655 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
656 ((char *)ctx->bios + data_offset +
657 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
658 ATOM_ENCODER_CAP_RECORD *cap_record;
659 u16 caps = 0;
660
661 while (record->ucRecordSize > 0 &&
662 record->ucRecordType > 0 &&
663 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
664 switch (record->ucRecordType) {
665 case ATOM_ENCODER_CAP_RECORD_TYPE:
666 cap_record =(ATOM_ENCODER_CAP_RECORD *)
667 record;
668 caps = le16_to_cpu(cap_record->usEncoderCap);
669 break;
670 }
671 record = (ATOM_COMMON_RECORD_HEADER *)
672 ((char *)record + record->ucRecordSize);
673 }
674 radeon_add_atom_encoder(dev,
675 encoder_obj,
676 le16_to_cpu
677 (path->
678 usDeviceTag),
679 caps);
680 }
681 }
682 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
683 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
684 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
685 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
686 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
687 ((char *)ctx->bios + data_offset +
688 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
689 ATOM_I2C_RECORD *i2c_record;
690 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
691 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
692 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
693 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
694 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
695 ((char *)ctx->bios + data_offset +
696 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
697 int enum_id;
698
699 router.router_id = router_obj_id;
700 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
701 enum_id++) {
702 if (le16_to_cpu(path->usConnObjectId) ==
703 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
704 break;
705 }
706
707 while (record->ucRecordSize > 0 &&
708 record->ucRecordType > 0 &&
709 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
710 switch (record->ucRecordType) {
711 case ATOM_I2C_RECORD_TYPE:
712 i2c_record =
713 (ATOM_I2C_RECORD *)
714 record;
715 i2c_config =
716 (ATOM_I2C_ID_CONFIG_ACCESS *)
717 &i2c_record->sucI2cId;
718 router.i2c_info =
719 radeon_lookup_i2c_gpio(rdev,
720 i2c_config->
721 ucAccess);
722 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
723 break;
724 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
725 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
726 record;
727 router.ddc_valid = true;
728 router.ddc_mux_type = ddc_path->ucMuxType;
729 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
730 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
731 break;
732 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
733 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
734 record;
735 router.cd_valid = true;
736 router.cd_mux_type = cd_path->ucMuxType;
737 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
738 router.cd_mux_state = cd_path->ucMuxState[enum_id];
739 break;
740 }
741 record = (ATOM_COMMON_RECORD_HEADER *)
742 ((char *)record + record->ucRecordSize);
743 }
744 }
745 }
746 }
747 }
748
749 /* look up gpio for ddc, hpd */
750 ddc_bus.valid = false;
751 hpd.hpd = RADEON_HPD_NONE;
752 if ((le16_to_cpu(path->usDeviceTag) &
753 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
754 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
755 if (le16_to_cpu(path->usConnObjectId) ==
756 le16_to_cpu(con_obj->asObjects[j].
757 usObjectID)) {
758 ATOM_COMMON_RECORD_HEADER
759 *record =
760 (ATOM_COMMON_RECORD_HEADER
761 *)
762 ((char *)ctx->bios + data_offset +
763 le16_to_cpu(con_obj->
764 asObjects[j].
765 usRecordOffset));
766 ATOM_I2C_RECORD *i2c_record;
767 ATOM_HPD_INT_RECORD *hpd_record;
768 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
769
770 while (record->ucRecordSize > 0 &&
771 record->ucRecordType > 0 &&
772 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
773 switch (record->ucRecordType) {
774 case ATOM_I2C_RECORD_TYPE:
775 i2c_record =
776 (ATOM_I2C_RECORD *)
777 record;
778 i2c_config =
779 (ATOM_I2C_ID_CONFIG_ACCESS *)
780 &i2c_record->sucI2cId;
781 ddc_bus = radeon_lookup_i2c_gpio(rdev,
782 i2c_config->
783 ucAccess);
784 break;
785 case ATOM_HPD_INT_RECORD_TYPE:
786 hpd_record =
787 (ATOM_HPD_INT_RECORD *)
788 record;
789 gpio = radeon_lookup_gpio(rdev,
790 hpd_record->ucHPDIntGPIOID);
791 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
792 hpd.plugged_state = hpd_record->ucPlugged_PinState;
793 break;
794 }
795 record =
796 (ATOM_COMMON_RECORD_HEADER
797 *) ((char *)record
798 +
799 record->
800 ucRecordSize);
801 }
802 break;
803 }
804 }
805 }
806
807 /* needed for aux chan transactions */
808 ddc_bus.hpd = hpd.hpd;
809
810 conn_id = le16_to_cpu(path->usConnObjectId);
811
812 if (!radeon_atom_apply_quirks
813 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
814 &ddc_bus, &conn_id, &hpd))
815 continue;
816
817 radeon_add_atom_connector(dev,
818 conn_id,
819 le16_to_cpu(path->
820 usDeviceTag),
821 connector_type, &ddc_bus,
822 igp_lane_info,
823 connector_object_id,
824 &hpd,
825 &router);
826
827 }
828 }
829
830 radeon_link_encoder_connector(dev);
831
832 return true;
833 }
834
atombios_get_connector_object_id(struct drm_device * dev,int connector_type,uint16_t devices)835 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
836 int connector_type,
837 uint16_t devices)
838 {
839 struct radeon_device *rdev = dev->dev_private;
840
841 if (rdev->flags & RADEON_IS_IGP) {
842 return supported_devices_connector_object_id_convert
843 [connector_type];
844 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
845 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
846 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
847 struct radeon_mode_info *mode_info = &rdev->mode_info;
848 struct atom_context *ctx = mode_info->atom_context;
849 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
850 uint16_t size, data_offset;
851 uint8_t frev, crev;
852 ATOM_XTMDS_INFO *xtmds;
853
854 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
855 xtmds = (ATOM_XTMDS_INFO *)((char *)ctx->bios + data_offset);
856
857 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
858 if (connector_type == DRM_MODE_CONNECTOR_DVII)
859 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
860 else
861 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
862 } else {
863 if (connector_type == DRM_MODE_CONNECTOR_DVII)
864 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
865 else
866 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
867 }
868 } else
869 return supported_devices_connector_object_id_convert
870 [connector_type];
871 } else {
872 return supported_devices_connector_object_id_convert
873 [connector_type];
874 }
875 }
876
877 struct bios_connector {
878 bool valid;
879 uint16_t line_mux;
880 uint16_t devices;
881 int connector_type;
882 struct radeon_i2c_bus_rec ddc_bus;
883 struct radeon_hpd hpd;
884 };
885
radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device * dev)886 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
887 drm_device
888 *dev)
889 {
890 struct radeon_device *rdev = dev->dev_private;
891 struct radeon_mode_info *mode_info = &rdev->mode_info;
892 struct atom_context *ctx = mode_info->atom_context;
893 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
894 uint16_t size, data_offset;
895 uint8_t frev, crev;
896 uint16_t device_support;
897 uint8_t dac;
898 union atom_supported_devices *supported_devices;
899 int i, j, max_device;
900 struct bios_connector *bios_connectors;
901 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
902 struct radeon_router router;
903
904 router.ddc_valid = false;
905 router.cd_valid = false;
906
907 bios_connectors = malloc(bc_size, DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
908 if (!bios_connectors)
909 return false;
910
911 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
912 &data_offset)) {
913 free(bios_connectors, DRM_MEM_DRIVER);
914 return false;
915 }
916
917 supported_devices =
918 (union atom_supported_devices *)((char *)ctx->bios + data_offset);
919
920 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
921
922 if (frev > 1)
923 max_device = ATOM_MAX_SUPPORTED_DEVICE;
924 else
925 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
926
927 for (i = 0; i < max_device; i++) {
928 ATOM_CONNECTOR_INFO_I2C ci =
929 supported_devices->info.asConnInfo[i];
930
931 bios_connectors[i].valid = false;
932
933 if (!(device_support & (1 << i))) {
934 continue;
935 }
936
937 if (i == ATOM_DEVICE_CV_INDEX) {
938 DRM_DEBUG_KMS("Skipping Component Video\n");
939 continue;
940 }
941
942 bios_connectors[i].connector_type =
943 supported_devices_connector_convert[ci.sucConnectorInfo.
944 sbfAccess.
945 bfConnectorType];
946
947 if (bios_connectors[i].connector_type ==
948 DRM_MODE_CONNECTOR_Unknown)
949 continue;
950
951 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
952
953 bios_connectors[i].line_mux =
954 ci.sucI2cId.ucAccess;
955
956 /* give tv unique connector ids */
957 if (i == ATOM_DEVICE_TV1_INDEX) {
958 bios_connectors[i].ddc_bus.valid = false;
959 bios_connectors[i].line_mux = 50;
960 } else if (i == ATOM_DEVICE_TV2_INDEX) {
961 bios_connectors[i].ddc_bus.valid = false;
962 bios_connectors[i].line_mux = 51;
963 } else if (i == ATOM_DEVICE_CV_INDEX) {
964 bios_connectors[i].ddc_bus.valid = false;
965 bios_connectors[i].line_mux = 52;
966 } else
967 bios_connectors[i].ddc_bus =
968 radeon_lookup_i2c_gpio(rdev,
969 bios_connectors[i].line_mux);
970
971 if ((crev > 1) && (frev > 1)) {
972 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
973 switch (isb) {
974 case 0x4:
975 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
976 break;
977 case 0xa:
978 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
979 break;
980 default:
981 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
982 break;
983 }
984 } else {
985 if (i == ATOM_DEVICE_DFP1_INDEX)
986 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
987 else if (i == ATOM_DEVICE_DFP2_INDEX)
988 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
989 else
990 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
991 }
992
993 /* Always set the connector type to VGA for CRT1/CRT2. if they are
994 * shared with a DVI port, we'll pick up the DVI connector when we
995 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
996 */
997 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
998 bios_connectors[i].connector_type =
999 DRM_MODE_CONNECTOR_VGA;
1000
1001 if (!radeon_atom_apply_quirks
1002 (dev, (1 << i), &bios_connectors[i].connector_type,
1003 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1004 &bios_connectors[i].hpd))
1005 continue;
1006
1007 bios_connectors[i].valid = true;
1008 bios_connectors[i].devices = (1 << i);
1009
1010 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1011 radeon_add_atom_encoder(dev,
1012 radeon_get_encoder_enum(dev,
1013 (1 << i),
1014 dac),
1015 (1 << i),
1016 0);
1017 else
1018 radeon_add_legacy_encoder(dev,
1019 radeon_get_encoder_enum(dev,
1020 (1 << i),
1021 dac),
1022 (1 << i));
1023 }
1024
1025 /* combine shared connectors */
1026 for (i = 0; i < max_device; i++) {
1027 if (bios_connectors[i].valid) {
1028 for (j = 0; j < max_device; j++) {
1029 if (bios_connectors[j].valid && (i != j)) {
1030 if (bios_connectors[i].line_mux ==
1031 bios_connectors[j].line_mux) {
1032 /* make sure not to combine LVDS */
1033 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1034 bios_connectors[i].line_mux = 53;
1035 bios_connectors[i].ddc_bus.valid = false;
1036 continue;
1037 }
1038 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1039 bios_connectors[j].line_mux = 53;
1040 bios_connectors[j].ddc_bus.valid = false;
1041 continue;
1042 }
1043 /* combine analog and digital for DVI-I */
1044 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1045 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1046 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1047 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1048 bios_connectors[i].devices |=
1049 bios_connectors[j].devices;
1050 bios_connectors[i].connector_type =
1051 DRM_MODE_CONNECTOR_DVII;
1052 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1053 bios_connectors[i].hpd =
1054 bios_connectors[j].hpd;
1055 bios_connectors[j].valid = false;
1056 }
1057 }
1058 }
1059 }
1060 }
1061 }
1062
1063 /* add the connectors */
1064 for (i = 0; i < max_device; i++) {
1065 if (bios_connectors[i].valid) {
1066 uint16_t connector_object_id =
1067 atombios_get_connector_object_id(dev,
1068 bios_connectors[i].connector_type,
1069 bios_connectors[i].devices);
1070 radeon_add_atom_connector(dev,
1071 bios_connectors[i].line_mux,
1072 bios_connectors[i].devices,
1073 bios_connectors[i].
1074 connector_type,
1075 &bios_connectors[i].ddc_bus,
1076 0,
1077 connector_object_id,
1078 &bios_connectors[i].hpd,
1079 &router);
1080 }
1081 }
1082
1083 radeon_link_encoder_connector(dev);
1084
1085 free(bios_connectors, DRM_MEM_DRIVER);
1086 return true;
1087 }
1088
1089 union firmware_info {
1090 ATOM_FIRMWARE_INFO info;
1091 ATOM_FIRMWARE_INFO_V1_2 info_12;
1092 ATOM_FIRMWARE_INFO_V1_3 info_13;
1093 ATOM_FIRMWARE_INFO_V1_4 info_14;
1094 ATOM_FIRMWARE_INFO_V2_1 info_21;
1095 ATOM_FIRMWARE_INFO_V2_2 info_22;
1096 };
1097
radeon_atom_get_clock_info(struct drm_device * dev)1098 bool radeon_atom_get_clock_info(struct drm_device *dev)
1099 {
1100 struct radeon_device *rdev = dev->dev_private;
1101 struct radeon_mode_info *mode_info = &rdev->mode_info;
1102 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1103 union firmware_info *firmware_info;
1104 uint8_t frev, crev;
1105 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1106 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1107 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1108 struct radeon_pll *spll = &rdev->clock.spll;
1109 struct radeon_pll *mpll = &rdev->clock.mpll;
1110 uint16_t data_offset;
1111
1112 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1113 &frev, &crev, &data_offset)) {
1114 firmware_info =
1115 (union firmware_info *)((char *)mode_info->atom_context->bios +
1116 data_offset);
1117 /* pixel clocks */
1118 p1pll->reference_freq =
1119 le16_to_cpu(firmware_info->info.usReferenceClock);
1120 p1pll->reference_div = 0;
1121
1122 if (crev < 2)
1123 p1pll->pll_out_min =
1124 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1125 else
1126 p1pll->pll_out_min =
1127 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1128 p1pll->pll_out_max =
1129 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1130
1131 if (crev >= 4) {
1132 p1pll->lcd_pll_out_min =
1133 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1134 if (p1pll->lcd_pll_out_min == 0)
1135 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1136 p1pll->lcd_pll_out_max =
1137 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1138 if (p1pll->lcd_pll_out_max == 0)
1139 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1140 } else {
1141 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1142 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1143 }
1144
1145 if (p1pll->pll_out_min == 0) {
1146 if (ASIC_IS_AVIVO(rdev))
1147 p1pll->pll_out_min = 64800;
1148 else
1149 p1pll->pll_out_min = 20000;
1150 }
1151
1152 p1pll->pll_in_min =
1153 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1154 p1pll->pll_in_max =
1155 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1156
1157 *p2pll = *p1pll;
1158
1159 /* system clock */
1160 if (ASIC_IS_DCE4(rdev))
1161 spll->reference_freq =
1162 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1163 else
1164 spll->reference_freq =
1165 le16_to_cpu(firmware_info->info.usReferenceClock);
1166 spll->reference_div = 0;
1167
1168 spll->pll_out_min =
1169 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1170 spll->pll_out_max =
1171 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1172
1173 /* ??? */
1174 if (spll->pll_out_min == 0) {
1175 if (ASIC_IS_AVIVO(rdev))
1176 spll->pll_out_min = 64800;
1177 else
1178 spll->pll_out_min = 20000;
1179 }
1180
1181 spll->pll_in_min =
1182 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1183 spll->pll_in_max =
1184 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1185
1186 /* memory clock */
1187 if (ASIC_IS_DCE4(rdev))
1188 mpll->reference_freq =
1189 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1190 else
1191 mpll->reference_freq =
1192 le16_to_cpu(firmware_info->info.usReferenceClock);
1193 mpll->reference_div = 0;
1194
1195 mpll->pll_out_min =
1196 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1197 mpll->pll_out_max =
1198 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1199
1200 /* ??? */
1201 if (mpll->pll_out_min == 0) {
1202 if (ASIC_IS_AVIVO(rdev))
1203 mpll->pll_out_min = 64800;
1204 else
1205 mpll->pll_out_min = 20000;
1206 }
1207
1208 mpll->pll_in_min =
1209 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1210 mpll->pll_in_max =
1211 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1212
1213 rdev->clock.default_sclk =
1214 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1215 rdev->clock.default_mclk =
1216 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1217
1218 if (ASIC_IS_DCE4(rdev)) {
1219 rdev->clock.default_dispclk =
1220 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1221 if (rdev->clock.default_dispclk == 0) {
1222 if (ASIC_IS_DCE5(rdev))
1223 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1224 else
1225 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1226 }
1227 rdev->clock.dp_extclk =
1228 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1229 }
1230 *dcpll = *p1pll;
1231
1232 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1233 if (rdev->clock.max_pixel_clock == 0)
1234 rdev->clock.max_pixel_clock = 40000;
1235
1236 /* not technically a clock, but... */
1237 rdev->mode_info.firmware_flags =
1238 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1239
1240 return true;
1241 }
1242
1243 return false;
1244 }
1245
1246 union igp_info {
1247 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1248 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1249 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1250 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1251 };
1252
radeon_atombios_sideport_present(struct radeon_device * rdev)1253 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1254 {
1255 struct radeon_mode_info *mode_info = &rdev->mode_info;
1256 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1257 union igp_info *igp_info;
1258 u8 frev, crev;
1259 u16 data_offset;
1260
1261 /* sideport is AMD only */
1262 if (rdev->family == CHIP_RS600)
1263 return false;
1264
1265 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1266 &frev, &crev, &data_offset)) {
1267 igp_info = (union igp_info *)((char *)mode_info->atom_context->bios +
1268 data_offset);
1269 switch (crev) {
1270 case 1:
1271 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1272 return true;
1273 break;
1274 case 2:
1275 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1276 return true;
1277 break;
1278 default:
1279 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1280 break;
1281 }
1282 }
1283 return false;
1284 }
1285
radeon_atombios_get_tmds_info(struct radeon_encoder * encoder,struct radeon_encoder_int_tmds * tmds)1286 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1287 struct radeon_encoder_int_tmds *tmds)
1288 {
1289 struct drm_device *dev = encoder->base.dev;
1290 struct radeon_device *rdev = dev->dev_private;
1291 struct radeon_mode_info *mode_info = &rdev->mode_info;
1292 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1293 uint16_t data_offset;
1294 struct _ATOM_TMDS_INFO *tmds_info;
1295 uint8_t frev, crev;
1296 uint16_t maxfreq;
1297 int i;
1298
1299 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1300 &frev, &crev, &data_offset)) {
1301 tmds_info =
1302 (struct _ATOM_TMDS_INFO *)((char *)mode_info->atom_context->bios +
1303 data_offset);
1304
1305 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1306 for (i = 0; i < 4; i++) {
1307 tmds->tmds_pll[i].freq =
1308 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1309 tmds->tmds_pll[i].value =
1310 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1311 tmds->tmds_pll[i].value |=
1312 (tmds_info->asMiscInfo[i].
1313 ucPLL_VCO_Gain & 0x3f) << 6;
1314 tmds->tmds_pll[i].value |=
1315 (tmds_info->asMiscInfo[i].
1316 ucPLL_DutyCycle & 0xf) << 12;
1317 tmds->tmds_pll[i].value |=
1318 (tmds_info->asMiscInfo[i].
1319 ucPLL_VoltageSwing & 0xf) << 16;
1320
1321 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1322 tmds->tmds_pll[i].freq,
1323 tmds->tmds_pll[i].value);
1324
1325 if (maxfreq == tmds->tmds_pll[i].freq) {
1326 tmds->tmds_pll[i].freq = 0xffffffff;
1327 break;
1328 }
1329 }
1330 return true;
1331 }
1332 return false;
1333 }
1334
radeon_atombios_get_ppll_ss_info(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id)1335 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1336 struct radeon_atom_ss *ss,
1337 int id)
1338 {
1339 struct radeon_mode_info *mode_info = &rdev->mode_info;
1340 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1341 uint16_t data_offset, size;
1342 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1343 uint8_t frev, crev;
1344 int i, num_indices;
1345
1346 memset(ss, 0, sizeof(struct radeon_atom_ss));
1347 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1348 &frev, &crev, &data_offset)) {
1349 ss_info =
1350 (struct _ATOM_SPREAD_SPECTRUM_INFO *)((char *)mode_info->atom_context->bios + data_offset);
1351
1352 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1353 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1354
1355 for (i = 0; i < num_indices; i++) {
1356 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1357 ss->percentage =
1358 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1359 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1360 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1361 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1362 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1363 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1364 return true;
1365 }
1366 }
1367 }
1368 return false;
1369 }
1370
radeon_atombios_get_igp_ss_overrides(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id)1371 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1372 struct radeon_atom_ss *ss,
1373 int id)
1374 {
1375 struct radeon_mode_info *mode_info = &rdev->mode_info;
1376 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1377 u16 data_offset, size;
1378 union igp_info *igp_info;
1379 u8 frev, crev;
1380 u16 percentage = 0, rate = 0;
1381
1382 /* get any igp specific overrides */
1383 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1384 &frev, &crev, &data_offset)) {
1385 igp_info = (union igp_info *)
1386 ((char *)mode_info->atom_context->bios + data_offset);
1387 switch (crev) {
1388 case 6:
1389 switch (id) {
1390 case ASIC_INTERNAL_SS_ON_TMDS:
1391 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1392 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1393 break;
1394 case ASIC_INTERNAL_SS_ON_HDMI:
1395 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1396 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1397 break;
1398 case ASIC_INTERNAL_SS_ON_LVDS:
1399 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1400 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1401 break;
1402 }
1403 break;
1404 case 7:
1405 switch (id) {
1406 case ASIC_INTERNAL_SS_ON_TMDS:
1407 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1408 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1409 break;
1410 case ASIC_INTERNAL_SS_ON_HDMI:
1411 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1412 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1413 break;
1414 case ASIC_INTERNAL_SS_ON_LVDS:
1415 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1416 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1417 break;
1418 }
1419 break;
1420 default:
1421 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1422 break;
1423 }
1424 if (percentage)
1425 ss->percentage = percentage;
1426 if (rate)
1427 ss->rate = rate;
1428 }
1429 }
1430
1431 union asic_ss_info {
1432 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1433 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1434 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1435 };
1436
radeon_atombios_get_asic_ss_info(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id,u32 clock)1437 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1438 struct radeon_atom_ss *ss,
1439 int id, u32 clock)
1440 {
1441 struct radeon_mode_info *mode_info = &rdev->mode_info;
1442 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1443 uint16_t data_offset, size;
1444 union asic_ss_info *ss_info;
1445 uint8_t frev, crev;
1446 int i, num_indices;
1447
1448 memset(ss, 0, sizeof(struct radeon_atom_ss));
1449 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1450 &frev, &crev, &data_offset)) {
1451
1452 ss_info =
1453 (union asic_ss_info *)((char *)mode_info->atom_context->bios + data_offset);
1454
1455 switch (frev) {
1456 case 1:
1457 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1458 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1459
1460 for (i = 0; i < num_indices; i++) {
1461 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1462 (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1463 ss->percentage =
1464 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1465 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1466 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1467 return true;
1468 }
1469 }
1470 break;
1471 case 2:
1472 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1473 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1474 for (i = 0; i < num_indices; i++) {
1475 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1476 (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1477 ss->percentage =
1478 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1479 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1480 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1481 return true;
1482 }
1483 }
1484 break;
1485 case 3:
1486 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1487 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1488 for (i = 0; i < num_indices; i++) {
1489 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1490 (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1491 ss->percentage =
1492 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1493 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1494 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1495 if (rdev->flags & RADEON_IS_IGP)
1496 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1497 return true;
1498 }
1499 }
1500 break;
1501 default:
1502 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1503 break;
1504 }
1505
1506 }
1507 return false;
1508 }
1509
1510 union lvds_info {
1511 struct _ATOM_LVDS_INFO info;
1512 struct _ATOM_LVDS_INFO_V12 info_12;
1513 };
1514
radeon_atombios_get_lvds_info(struct radeon_encoder * encoder)1515 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1516 radeon_encoder
1517 *encoder)
1518 {
1519 struct drm_device *dev = encoder->base.dev;
1520 struct radeon_device *rdev = dev->dev_private;
1521 struct radeon_mode_info *mode_info = &rdev->mode_info;
1522 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1523 uint16_t data_offset, misc;
1524 union lvds_info *lvds_info;
1525 uint8_t frev, crev;
1526 struct radeon_encoder_atom_dig *lvds = NULL;
1527 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1528
1529 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1530 &frev, &crev, &data_offset)) {
1531 lvds_info =
1532 (union lvds_info *)((char *)mode_info->atom_context->bios + data_offset);
1533 lvds =
1534 malloc(sizeof(struct radeon_encoder_atom_dig),
1535 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
1536
1537 if (!lvds)
1538 return NULL;
1539
1540 lvds->native_mode.clock =
1541 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1542 lvds->native_mode.hdisplay =
1543 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1544 lvds->native_mode.vdisplay =
1545 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1546 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1547 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1548 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1549 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1550 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1551 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1552 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1553 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1554 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1555 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1556 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1557 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1558 lvds->panel_pwr_delay =
1559 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1560 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1561
1562 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1563 if (misc & ATOM_VSYNC_POLARITY)
1564 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1565 if (misc & ATOM_HSYNC_POLARITY)
1566 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1567 if (misc & ATOM_COMPOSITESYNC)
1568 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1569 if (misc & ATOM_INTERLACE)
1570 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1571 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1572 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1573
1574 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1575 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1576
1577 /* set crtc values */
1578 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1579
1580 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1581
1582 encoder->native_mode = lvds->native_mode;
1583
1584 if (encoder_enum == 2)
1585 lvds->linkb = true;
1586 else
1587 lvds->linkb = false;
1588
1589 /* parse the lcd record table */
1590 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1591 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1592 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1593 bool bad_record = false;
1594 u8 *record;
1595
1596 if ((frev == 1) && (crev < 2))
1597 /* absolute */
1598 record = (u8 *)((char *)mode_info->atom_context->bios +
1599 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1600 else
1601 /* relative */
1602 record = (u8 *)((char *)mode_info->atom_context->bios +
1603 data_offset +
1604 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1605 while (*record != ATOM_RECORD_END_TYPE) {
1606 switch (*record) {
1607 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1608 record += sizeof(ATOM_PATCH_RECORD_MODE);
1609 break;
1610 case LCD_RTS_RECORD_TYPE:
1611 record += sizeof(ATOM_LCD_RTS_RECORD);
1612 break;
1613 case LCD_CAP_RECORD_TYPE:
1614 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1615 break;
1616 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1617 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1618 if (fake_edid_record->ucFakeEDIDLength) {
1619 struct edid *edid;
1620 int edid_size =
1621 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1622 edid = malloc(edid_size, DRM_MEM_KMS, M_WAITOK);
1623 if (edid) {
1624 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1625 fake_edid_record->ucFakeEDIDLength);
1626
1627 if (drm_edid_is_valid(edid)) {
1628 rdev->mode_info.bios_hardcoded_edid = edid;
1629 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1630 } else
1631 free(edid, DRM_MEM_KMS);
1632 }
1633 }
1634 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1635 break;
1636 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1637 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1638 lvds->native_mode.width_mm = panel_res_record->usHSize;
1639 lvds->native_mode.height_mm = panel_res_record->usVSize;
1640 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1641 break;
1642 default:
1643 DRM_ERROR("Bad LCD record %d\n", *record);
1644 bad_record = true;
1645 break;
1646 }
1647 if (bad_record)
1648 break;
1649 }
1650 }
1651 }
1652 return lvds;
1653 }
1654
1655 struct radeon_encoder_primary_dac *
radeon_atombios_get_primary_dac_info(struct radeon_encoder * encoder)1656 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1657 {
1658 struct drm_device *dev = encoder->base.dev;
1659 struct radeon_device *rdev = dev->dev_private;
1660 struct radeon_mode_info *mode_info = &rdev->mode_info;
1661 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1662 uint16_t data_offset;
1663 struct _COMPASSIONATE_DATA *dac_info;
1664 uint8_t frev, crev;
1665 uint8_t bg, dac;
1666 struct radeon_encoder_primary_dac *p_dac = NULL;
1667
1668 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1669 &frev, &crev, &data_offset)) {
1670 dac_info = (struct _COMPASSIONATE_DATA *)
1671 ((char *)mode_info->atom_context->bios + data_offset);
1672
1673 p_dac = malloc(sizeof(struct radeon_encoder_primary_dac),
1674 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
1675
1676 if (!p_dac)
1677 return NULL;
1678
1679 bg = dac_info->ucDAC1_BG_Adjustment;
1680 dac = dac_info->ucDAC1_DAC_Adjustment;
1681 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1682
1683 }
1684 return p_dac;
1685 }
1686
radeon_atom_get_tv_timings(struct radeon_device * rdev,int index,struct drm_display_mode * mode)1687 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1688 struct drm_display_mode *mode)
1689 {
1690 struct radeon_mode_info *mode_info = &rdev->mode_info;
1691 ATOM_ANALOG_TV_INFO *tv_info;
1692 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1693 ATOM_DTD_FORMAT *dtd_timings;
1694 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1695 u8 frev, crev;
1696 u16 data_offset, misc;
1697
1698 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1699 &frev, &crev, &data_offset))
1700 return false;
1701
1702 switch (crev) {
1703 case 1:
1704 tv_info = (ATOM_ANALOG_TV_INFO *)((char *)mode_info->atom_context->bios + data_offset);
1705 if (index >= MAX_SUPPORTED_TV_TIMING)
1706 return false;
1707
1708 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1709 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1710 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1711 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1712 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1713
1714 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1715 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1716 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1717 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1718 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1719
1720 mode->flags = 0;
1721 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1722 if (misc & ATOM_VSYNC_POLARITY)
1723 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1724 if (misc & ATOM_HSYNC_POLARITY)
1725 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1726 if (misc & ATOM_COMPOSITESYNC)
1727 mode->flags |= DRM_MODE_FLAG_CSYNC;
1728 if (misc & ATOM_INTERLACE)
1729 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1730 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1731 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1732
1733 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1734
1735 if (index == 1) {
1736 /* PAL timings appear to have wrong values for totals */
1737 mode->crtc_htotal -= 1;
1738 mode->crtc_vtotal -= 1;
1739 }
1740 break;
1741 case 2:
1742 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)((char *)mode_info->atom_context->bios + data_offset);
1743 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1744 return false;
1745
1746 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1747 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1748 le16_to_cpu(dtd_timings->usHBlanking_Time);
1749 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1750 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1751 le16_to_cpu(dtd_timings->usHSyncOffset);
1752 mode->crtc_hsync_end = mode->crtc_hsync_start +
1753 le16_to_cpu(dtd_timings->usHSyncWidth);
1754
1755 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1756 le16_to_cpu(dtd_timings->usVBlanking_Time);
1757 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1758 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1759 le16_to_cpu(dtd_timings->usVSyncOffset);
1760 mode->crtc_vsync_end = mode->crtc_vsync_start +
1761 le16_to_cpu(dtd_timings->usVSyncWidth);
1762
1763 mode->flags = 0;
1764 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1765 if (misc & ATOM_VSYNC_POLARITY)
1766 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1767 if (misc & ATOM_HSYNC_POLARITY)
1768 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1769 if (misc & ATOM_COMPOSITESYNC)
1770 mode->flags |= DRM_MODE_FLAG_CSYNC;
1771 if (misc & ATOM_INTERLACE)
1772 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1773 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1774 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1775
1776 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1777 break;
1778 }
1779 return true;
1780 }
1781
1782 enum radeon_tv_std
radeon_atombios_get_tv_info(struct radeon_device * rdev)1783 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1784 {
1785 struct radeon_mode_info *mode_info = &rdev->mode_info;
1786 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1787 uint16_t data_offset;
1788 uint8_t frev, crev;
1789 struct _ATOM_ANALOG_TV_INFO *tv_info;
1790 enum radeon_tv_std tv_std = TV_STD_NTSC;
1791
1792 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1793 &frev, &crev, &data_offset)) {
1794
1795 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1796 ((char *)mode_info->atom_context->bios + data_offset);
1797
1798 switch (tv_info->ucTV_BootUpDefaultStandard) {
1799 case ATOM_TV_NTSC:
1800 tv_std = TV_STD_NTSC;
1801 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1802 break;
1803 case ATOM_TV_NTSCJ:
1804 tv_std = TV_STD_NTSC_J;
1805 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1806 break;
1807 case ATOM_TV_PAL:
1808 tv_std = TV_STD_PAL;
1809 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1810 break;
1811 case ATOM_TV_PALM:
1812 tv_std = TV_STD_PAL_M;
1813 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1814 break;
1815 case ATOM_TV_PALN:
1816 tv_std = TV_STD_PAL_N;
1817 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1818 break;
1819 case ATOM_TV_PALCN:
1820 tv_std = TV_STD_PAL_CN;
1821 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1822 break;
1823 case ATOM_TV_PAL60:
1824 tv_std = TV_STD_PAL_60;
1825 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1826 break;
1827 case ATOM_TV_SECAM:
1828 tv_std = TV_STD_SECAM;
1829 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1830 break;
1831 default:
1832 tv_std = TV_STD_NTSC;
1833 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1834 break;
1835 }
1836 }
1837 return tv_std;
1838 }
1839
1840 struct radeon_encoder_tv_dac *
radeon_atombios_get_tv_dac_info(struct radeon_encoder * encoder)1841 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1842 {
1843 struct drm_device *dev = encoder->base.dev;
1844 struct radeon_device *rdev = dev->dev_private;
1845 struct radeon_mode_info *mode_info = &rdev->mode_info;
1846 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1847 uint16_t data_offset;
1848 struct _COMPASSIONATE_DATA *dac_info;
1849 uint8_t frev, crev;
1850 uint8_t bg, dac;
1851 struct radeon_encoder_tv_dac *tv_dac = NULL;
1852
1853 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1854 &frev, &crev, &data_offset)) {
1855
1856 dac_info = (struct _COMPASSIONATE_DATA *)
1857 ((char *)mode_info->atom_context->bios + data_offset);
1858
1859 tv_dac = malloc(sizeof(struct radeon_encoder_tv_dac),
1860 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
1861
1862 if (!tv_dac)
1863 return NULL;
1864
1865 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1866 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1867 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1868
1869 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1870 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1871 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1872
1873 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1874 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1875 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1876
1877 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1878 }
1879 return tv_dac;
1880 }
1881
1882 static const char *thermal_controller_names[] = {
1883 "NONE",
1884 "lm63",
1885 "adm1032",
1886 "adm1030",
1887 "max6649",
1888 "lm64",
1889 "f75375",
1890 "asc7xxx",
1891 };
1892
1893 static const char *pp_lib_thermal_controller_names[] = {
1894 "NONE",
1895 "lm63",
1896 "adm1032",
1897 "adm1030",
1898 "max6649",
1899 "lm64",
1900 "f75375",
1901 "RV6xx",
1902 "RV770",
1903 "adt7473",
1904 "NONE",
1905 "External GPIO",
1906 "Evergreen",
1907 "emc2103",
1908 "Sumo",
1909 "Northern Islands",
1910 "Southern Islands",
1911 "lm96163",
1912 };
1913
1914 union power_info {
1915 struct _ATOM_POWERPLAY_INFO info;
1916 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1917 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1918 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1919 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1920 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1921 };
1922
1923 union pplib_clock_info {
1924 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1925 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1926 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1927 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1928 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
1929 };
1930
1931 union pplib_power_state {
1932 struct _ATOM_PPLIB_STATE v1;
1933 struct _ATOM_PPLIB_STATE_V2 v2;
1934 };
1935
radeon_atombios_parse_misc_flags_1_3(struct radeon_device * rdev,int state_index,u32 misc,u32 misc2)1936 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1937 int state_index,
1938 u32 misc, u32 misc2)
1939 {
1940 rdev->pm.power_state[state_index].misc = misc;
1941 rdev->pm.power_state[state_index].misc2 = misc2;
1942 /* order matters! */
1943 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1944 rdev->pm.power_state[state_index].type =
1945 POWER_STATE_TYPE_POWERSAVE;
1946 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1947 rdev->pm.power_state[state_index].type =
1948 POWER_STATE_TYPE_BATTERY;
1949 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1950 rdev->pm.power_state[state_index].type =
1951 POWER_STATE_TYPE_BATTERY;
1952 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1953 rdev->pm.power_state[state_index].type =
1954 POWER_STATE_TYPE_BALANCED;
1955 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1956 rdev->pm.power_state[state_index].type =
1957 POWER_STATE_TYPE_PERFORMANCE;
1958 rdev->pm.power_state[state_index].flags &=
1959 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1960 }
1961 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1962 rdev->pm.power_state[state_index].type =
1963 POWER_STATE_TYPE_BALANCED;
1964 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1965 rdev->pm.power_state[state_index].type =
1966 POWER_STATE_TYPE_DEFAULT;
1967 rdev->pm.default_power_state_index = state_index;
1968 rdev->pm.power_state[state_index].default_clock_mode =
1969 &rdev->pm.power_state[state_index].clock_info[0];
1970 } else if (state_index == 0) {
1971 rdev->pm.power_state[state_index].clock_info[0].flags |=
1972 RADEON_PM_MODE_NO_DISPLAY;
1973 }
1974 }
1975
radeon_atombios_parse_power_table_1_3(struct radeon_device * rdev)1976 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1977 {
1978 struct radeon_mode_info *mode_info = &rdev->mode_info;
1979 u32 misc, misc2 = 0;
1980 int num_modes = 0, i;
1981 int state_index = 0;
1982 struct radeon_i2c_bus_rec i2c_bus;
1983 union power_info *power_info;
1984 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1985 u16 data_offset;
1986 u8 frev, crev;
1987
1988 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1989 &frev, &crev, &data_offset))
1990 return state_index;
1991 power_info = (union power_info *)((char *)mode_info->atom_context->bios + data_offset);
1992
1993 /* add the i2c bus for thermal/fan chip */
1994 if ((power_info->info.ucOverdriveThermalController > 0) &&
1995 (power_info->info.ucOverdriveThermalController < DRM_ARRAY_SIZE(thermal_controller_names))) {
1996 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1997 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1998 power_info->info.ucOverdriveControllerAddress >> 1);
1999 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2000 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2001 #ifdef DUMBBELL_WIP
2002 if (rdev->pm.i2c_bus) {
2003 struct i2c_board_info info = { };
2004 const char *name = thermal_controller_names[power_info->info.
2005 ucOverdriveThermalController];
2006 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2007 strlcpy(info.type, name, sizeof(info.type));
2008 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2009 }
2010 #endif /* DUMBBELL_WIP */
2011 }
2012 num_modes = power_info->info.ucNumOfPowerModeEntries;
2013 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2014 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2015 rdev->pm.power_state = malloc(sizeof(struct radeon_power_state) * num_modes,
2016 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
2017 if (!rdev->pm.power_state)
2018 return state_index;
2019 /* last mode is usually default, array is low to high */
2020 for (i = 0; i < num_modes; i++) {
2021 rdev->pm.power_state[state_index].clock_info =
2022 malloc(sizeof(struct radeon_pm_clock_info) * 1,
2023 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
2024 if (!rdev->pm.power_state[state_index].clock_info)
2025 return state_index;
2026 rdev->pm.power_state[state_index].num_clock_modes = 1;
2027 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2028 switch (frev) {
2029 case 1:
2030 rdev->pm.power_state[state_index].clock_info[0].mclk =
2031 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2032 rdev->pm.power_state[state_index].clock_info[0].sclk =
2033 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2034 /* skip invalid modes */
2035 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2036 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2037 continue;
2038 rdev->pm.power_state[state_index].pcie_lanes =
2039 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2040 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2041 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2042 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2043 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2044 VOLTAGE_GPIO;
2045 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2046 radeon_lookup_gpio(rdev,
2047 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2048 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2049 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2050 true;
2051 else
2052 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2053 false;
2054 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2055 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2056 VOLTAGE_VDDC;
2057 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2058 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2059 }
2060 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2061 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2062 state_index++;
2063 break;
2064 case 2:
2065 rdev->pm.power_state[state_index].clock_info[0].mclk =
2066 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2067 rdev->pm.power_state[state_index].clock_info[0].sclk =
2068 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2069 /* skip invalid modes */
2070 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2071 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2072 continue;
2073 rdev->pm.power_state[state_index].pcie_lanes =
2074 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2075 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2076 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2077 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2078 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2079 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2080 VOLTAGE_GPIO;
2081 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2082 radeon_lookup_gpio(rdev,
2083 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2084 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2085 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2086 true;
2087 else
2088 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2089 false;
2090 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2091 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2092 VOLTAGE_VDDC;
2093 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2094 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2095 }
2096 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2097 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2098 state_index++;
2099 break;
2100 case 3:
2101 rdev->pm.power_state[state_index].clock_info[0].mclk =
2102 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2103 rdev->pm.power_state[state_index].clock_info[0].sclk =
2104 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2105 /* skip invalid modes */
2106 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2107 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2108 continue;
2109 rdev->pm.power_state[state_index].pcie_lanes =
2110 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2111 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2112 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2113 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2114 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2115 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2116 VOLTAGE_GPIO;
2117 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2118 radeon_lookup_gpio(rdev,
2119 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2120 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2121 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2122 true;
2123 else
2124 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2125 false;
2126 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2127 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2128 VOLTAGE_VDDC;
2129 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2130 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2131 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2132 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2133 true;
2134 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2135 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2136 }
2137 }
2138 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2139 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2140 state_index++;
2141 break;
2142 }
2143 }
2144 /* last mode is usually default */
2145 if (rdev->pm.default_power_state_index == -1) {
2146 rdev->pm.power_state[state_index - 1].type =
2147 POWER_STATE_TYPE_DEFAULT;
2148 rdev->pm.default_power_state_index = state_index - 1;
2149 rdev->pm.power_state[state_index - 1].default_clock_mode =
2150 &rdev->pm.power_state[state_index - 1].clock_info[0];
2151 rdev->pm.power_state[state_index].flags &=
2152 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2153 rdev->pm.power_state[state_index].misc = 0;
2154 rdev->pm.power_state[state_index].misc2 = 0;
2155 }
2156 return state_index;
2157 }
2158
radeon_atombios_add_pplib_thermal_controller(struct radeon_device * rdev,ATOM_PPLIB_THERMALCONTROLLER * controller)2159 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2160 ATOM_PPLIB_THERMALCONTROLLER *controller)
2161 {
2162 struct radeon_i2c_bus_rec i2c_bus;
2163
2164 /* add the i2c bus for thermal/fan chip */
2165 if (controller->ucType > 0) {
2166 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2167 DRM_INFO("Internal thermal controller %s fan control\n",
2168 (controller->ucFanParameters &
2169 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2170 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2171 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2172 DRM_INFO("Internal thermal controller %s fan control\n",
2173 (controller->ucFanParameters &
2174 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2175 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2176 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2177 DRM_INFO("Internal thermal controller %s fan control\n",
2178 (controller->ucFanParameters &
2179 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2180 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2181 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2182 DRM_INFO("Internal thermal controller %s fan control\n",
2183 (controller->ucFanParameters &
2184 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2185 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2186 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2187 DRM_INFO("Internal thermal controller %s fan control\n",
2188 (controller->ucFanParameters &
2189 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2190 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2191 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2192 DRM_INFO("Internal thermal controller %s fan control\n",
2193 (controller->ucFanParameters &
2194 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2195 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2196 } else if ((controller->ucType ==
2197 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2198 (controller->ucType ==
2199 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2200 (controller->ucType ==
2201 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2202 DRM_INFO("Special thermal controller config\n");
2203 } else if (controller->ucType < DRM_ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2204 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2205 pp_lib_thermal_controller_names[controller->ucType],
2206 controller->ucI2cAddress >> 1,
2207 (controller->ucFanParameters &
2208 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2209 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2210 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2211 #ifdef DUMBBELL_WIP
2212 if (rdev->pm.i2c_bus) {
2213 struct i2c_board_info info = { };
2214 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2215 info.addr = controller->ucI2cAddress >> 1;
2216 strlcpy(info.type, name, sizeof(info.type));
2217 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2218 }
2219 #endif /* DUMBBELL_WIP */
2220 } else {
2221 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2222 controller->ucType,
2223 controller->ucI2cAddress >> 1,
2224 (controller->ucFanParameters &
2225 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2226 }
2227 }
2228 }
2229
radeon_atombios_get_default_voltages(struct radeon_device * rdev,u16 * vddc,u16 * vddci)2230 static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2231 u16 *vddc, u16 *vddci)
2232 {
2233 struct radeon_mode_info *mode_info = &rdev->mode_info;
2234 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2235 u8 frev, crev;
2236 u16 data_offset;
2237 union firmware_info *firmware_info;
2238
2239 *vddc = 0;
2240 *vddci = 0;
2241
2242 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2243 &frev, &crev, &data_offset)) {
2244 firmware_info =
2245 (union firmware_info *)((char *)mode_info->atom_context->bios +
2246 data_offset);
2247 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2248 if ((frev == 2) && (crev >= 2))
2249 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2250 }
2251 }
2252
radeon_atombios_parse_pplib_non_clock_info(struct radeon_device * rdev,int state_index,int mode_index,struct _ATOM_PPLIB_NONCLOCK_INFO * non_clock_info)2253 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2254 int state_index, int mode_index,
2255 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2256 {
2257 int j;
2258 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2259 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2260 u16 vddc, vddci;
2261
2262 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
2263
2264 rdev->pm.power_state[state_index].misc = misc;
2265 rdev->pm.power_state[state_index].misc2 = misc2;
2266 rdev->pm.power_state[state_index].pcie_lanes =
2267 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2268 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2269 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2270 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2271 rdev->pm.power_state[state_index].type =
2272 POWER_STATE_TYPE_BATTERY;
2273 break;
2274 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2275 rdev->pm.power_state[state_index].type =
2276 POWER_STATE_TYPE_BALANCED;
2277 break;
2278 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2279 rdev->pm.power_state[state_index].type =
2280 POWER_STATE_TYPE_PERFORMANCE;
2281 break;
2282 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2283 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2284 rdev->pm.power_state[state_index].type =
2285 POWER_STATE_TYPE_PERFORMANCE;
2286 break;
2287 }
2288 rdev->pm.power_state[state_index].flags = 0;
2289 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2290 rdev->pm.power_state[state_index].flags |=
2291 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2292 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2293 rdev->pm.power_state[state_index].type =
2294 POWER_STATE_TYPE_DEFAULT;
2295 rdev->pm.default_power_state_index = state_index;
2296 rdev->pm.power_state[state_index].default_clock_mode =
2297 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2298 if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2299 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2300 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2301 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2302 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2303 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2304 } else {
2305 /* patch the table values with the default slck/mclk from firmware info */
2306 for (j = 0; j < mode_index; j++) {
2307 rdev->pm.power_state[state_index].clock_info[j].mclk =
2308 rdev->clock.default_mclk;
2309 rdev->pm.power_state[state_index].clock_info[j].sclk =
2310 rdev->clock.default_sclk;
2311 if (vddc)
2312 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2313 vddc;
2314 }
2315 }
2316 }
2317 }
2318
radeon_atombios_parse_pplib_clock_info(struct radeon_device * rdev,int state_index,int mode_index,union pplib_clock_info * clock_info)2319 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2320 int state_index, int mode_index,
2321 union pplib_clock_info *clock_info)
2322 {
2323 u32 sclk, mclk;
2324 u16 vddc;
2325
2326 if (rdev->flags & RADEON_IS_IGP) {
2327 if (rdev->family >= CHIP_PALM) {
2328 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2329 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2330 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2331 } else {
2332 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2333 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2334 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2335 }
2336 } else if (ASIC_IS_DCE6(rdev)) {
2337 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2338 sclk |= clock_info->si.ucEngineClockHigh << 16;
2339 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2340 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2341 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2342 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2343 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2344 VOLTAGE_SW;
2345 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2346 le16_to_cpu(clock_info->si.usVDDC);
2347 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2348 le16_to_cpu(clock_info->si.usVDDCI);
2349 } else if (ASIC_IS_DCE4(rdev)) {
2350 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2351 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2352 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2353 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2354 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2355 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2356 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2357 VOLTAGE_SW;
2358 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2359 le16_to_cpu(clock_info->evergreen.usVDDC);
2360 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2361 le16_to_cpu(clock_info->evergreen.usVDDCI);
2362 } else {
2363 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2364 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2365 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2366 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2367 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2368 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2369 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2370 VOLTAGE_SW;
2371 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2372 le16_to_cpu(clock_info->r600.usVDDC);
2373 }
2374
2375 /* patch up vddc if necessary */
2376 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2377 case ATOM_VIRTUAL_VOLTAGE_ID0:
2378 case ATOM_VIRTUAL_VOLTAGE_ID1:
2379 case ATOM_VIRTUAL_VOLTAGE_ID2:
2380 case ATOM_VIRTUAL_VOLTAGE_ID3:
2381 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2382 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2383 &vddc) == 0)
2384 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2385 break;
2386 default:
2387 break;
2388 }
2389
2390 if (rdev->flags & RADEON_IS_IGP) {
2391 /* skip invalid modes */
2392 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2393 return false;
2394 } else {
2395 /* skip invalid modes */
2396 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2397 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2398 return false;
2399 }
2400 return true;
2401 }
2402
radeon_atombios_parse_power_table_4_5(struct radeon_device * rdev)2403 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2404 {
2405 struct radeon_mode_info *mode_info = &rdev->mode_info;
2406 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2407 union pplib_power_state *power_state;
2408 int i, j;
2409 int state_index = 0, mode_index = 0;
2410 union pplib_clock_info *clock_info;
2411 bool valid;
2412 union power_info *power_info;
2413 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2414 u16 data_offset;
2415 u8 frev, crev;
2416
2417 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2418 &frev, &crev, &data_offset))
2419 return state_index;
2420 power_info = (union power_info *)((char *)mode_info->atom_context->bios + data_offset);
2421
2422 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2423 rdev->pm.power_state = malloc(sizeof(struct radeon_power_state) *
2424 power_info->pplib.ucNumStates,
2425 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
2426 if (!rdev->pm.power_state)
2427 return state_index;
2428 /* first mode is usually default, followed by low to high */
2429 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2430 mode_index = 0;
2431 power_state = (union pplib_power_state *)
2432 ((char *)mode_info->atom_context->bios + data_offset +
2433 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2434 i * power_info->pplib.ucStateEntrySize);
2435 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2436 ((char *)mode_info->atom_context->bios + data_offset +
2437 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2438 (power_state->v1.ucNonClockStateIndex *
2439 power_info->pplib.ucNonClockSize));
2440 rdev->pm.power_state[i].clock_info = malloc(sizeof(struct radeon_pm_clock_info) *
2441 ((power_info->pplib.ucStateEntrySize - 1) ?
2442 (power_info->pplib.ucStateEntrySize - 1) : 1),
2443 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
2444 if (!rdev->pm.power_state[i].clock_info)
2445 return state_index;
2446 if (power_info->pplib.ucStateEntrySize - 1) {
2447 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2448 clock_info = (union pplib_clock_info *)
2449 ((char *)mode_info->atom_context->bios + data_offset +
2450 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2451 (power_state->v1.ucClockStateIndices[j] *
2452 power_info->pplib.ucClockInfoSize));
2453 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2454 state_index, mode_index,
2455 clock_info);
2456 if (valid)
2457 mode_index++;
2458 }
2459 } else {
2460 rdev->pm.power_state[state_index].clock_info[0].mclk =
2461 rdev->clock.default_mclk;
2462 rdev->pm.power_state[state_index].clock_info[0].sclk =
2463 rdev->clock.default_sclk;
2464 mode_index++;
2465 }
2466 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2467 if (mode_index) {
2468 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2469 non_clock_info);
2470 state_index++;
2471 }
2472 }
2473 /* if multiple clock modes, mark the lowest as no display */
2474 for (i = 0; i < state_index; i++) {
2475 if (rdev->pm.power_state[i].num_clock_modes > 1)
2476 rdev->pm.power_state[i].clock_info[0].flags |=
2477 RADEON_PM_MODE_NO_DISPLAY;
2478 }
2479 /* first mode is usually default */
2480 if (rdev->pm.default_power_state_index == -1) {
2481 rdev->pm.power_state[0].type =
2482 POWER_STATE_TYPE_DEFAULT;
2483 rdev->pm.default_power_state_index = 0;
2484 rdev->pm.power_state[0].default_clock_mode =
2485 &rdev->pm.power_state[0].clock_info[0];
2486 }
2487 return state_index;
2488 }
2489
radeon_atombios_parse_power_table_6(struct radeon_device * rdev)2490 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2491 {
2492 struct radeon_mode_info *mode_info = &rdev->mode_info;
2493 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2494 union pplib_power_state *power_state;
2495 int i, j, non_clock_array_index, clock_array_index;
2496 int state_index = 0, mode_index = 0;
2497 union pplib_clock_info *clock_info;
2498 struct _StateArray *state_array;
2499 struct _ClockInfoArray *clock_info_array;
2500 struct _NonClockInfoArray *non_clock_info_array;
2501 bool valid;
2502 union power_info *power_info;
2503 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2504 u16 data_offset;
2505 u8 frev, crev;
2506
2507 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2508 &frev, &crev, &data_offset))
2509 return state_index;
2510 power_info = (union power_info *)((char *)mode_info->atom_context->bios + data_offset);
2511
2512 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2513 state_array = (struct _StateArray *)
2514 ((char *)mode_info->atom_context->bios + data_offset +
2515 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2516 clock_info_array = (struct _ClockInfoArray *)
2517 ((char *)mode_info->atom_context->bios + data_offset +
2518 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2519 non_clock_info_array = (struct _NonClockInfoArray *)
2520 ((char *)mode_info->atom_context->bios + data_offset +
2521 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2522 rdev->pm.power_state = malloc(sizeof(struct radeon_power_state) *
2523 state_array->ucNumEntries,
2524 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
2525 if (!rdev->pm.power_state)
2526 return state_index;
2527 for (i = 0; i < state_array->ucNumEntries; i++) {
2528 mode_index = 0;
2529 power_state = (union pplib_power_state *)&state_array->states[i];
2530 /* XXX this might be an inagua bug... */
2531 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2532 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2533 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2534 rdev->pm.power_state[i].clock_info = malloc(sizeof(struct radeon_pm_clock_info) *
2535 (power_state->v2.ucNumDPMLevels ?
2536 power_state->v2.ucNumDPMLevels : 1),
2537 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
2538 if (!rdev->pm.power_state[i].clock_info)
2539 return state_index;
2540 if (power_state->v2.ucNumDPMLevels) {
2541 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2542 clock_array_index = power_state->v2.clockInfoIndex[j];
2543 /* XXX this might be an inagua bug... */
2544 if (clock_array_index >= clock_info_array->ucNumEntries)
2545 continue;
2546 clock_info = (union pplib_clock_info *)
2547 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2548 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2549 state_index, mode_index,
2550 clock_info);
2551 if (valid)
2552 mode_index++;
2553 }
2554 } else {
2555 rdev->pm.power_state[state_index].clock_info[0].mclk =
2556 rdev->clock.default_mclk;
2557 rdev->pm.power_state[state_index].clock_info[0].sclk =
2558 rdev->clock.default_sclk;
2559 mode_index++;
2560 }
2561 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2562 if (mode_index) {
2563 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2564 non_clock_info);
2565 state_index++;
2566 }
2567 }
2568 /* if multiple clock modes, mark the lowest as no display */
2569 for (i = 0; i < state_index; i++) {
2570 if (rdev->pm.power_state[i].num_clock_modes > 1)
2571 rdev->pm.power_state[i].clock_info[0].flags |=
2572 RADEON_PM_MODE_NO_DISPLAY;
2573 }
2574 /* first mode is usually default */
2575 if (rdev->pm.default_power_state_index == -1) {
2576 rdev->pm.power_state[0].type =
2577 POWER_STATE_TYPE_DEFAULT;
2578 rdev->pm.default_power_state_index = 0;
2579 rdev->pm.power_state[0].default_clock_mode =
2580 &rdev->pm.power_state[0].clock_info[0];
2581 }
2582 return state_index;
2583 }
2584
radeon_atombios_get_power_modes(struct radeon_device * rdev)2585 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2586 {
2587 struct radeon_mode_info *mode_info = &rdev->mode_info;
2588 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2589 u16 data_offset;
2590 u8 frev, crev;
2591 int state_index = 0;
2592
2593 rdev->pm.default_power_state_index = -1;
2594
2595 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2596 &frev, &crev, &data_offset)) {
2597 switch (frev) {
2598 case 1:
2599 case 2:
2600 case 3:
2601 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2602 break;
2603 case 4:
2604 case 5:
2605 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2606 break;
2607 case 6:
2608 state_index = radeon_atombios_parse_power_table_6(rdev);
2609 break;
2610 default:
2611 break;
2612 }
2613 } else {
2614 rdev->pm.power_state = malloc(sizeof(struct radeon_power_state),
2615 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
2616 if (rdev->pm.power_state) {
2617 rdev->pm.power_state[0].clock_info =
2618 malloc(sizeof(struct radeon_pm_clock_info) * 1,
2619 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
2620 if (rdev->pm.power_state[0].clock_info) {
2621 /* add the default mode */
2622 rdev->pm.power_state[state_index].type =
2623 POWER_STATE_TYPE_DEFAULT;
2624 rdev->pm.power_state[state_index].num_clock_modes = 1;
2625 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2626 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2627 rdev->pm.power_state[state_index].default_clock_mode =
2628 &rdev->pm.power_state[state_index].clock_info[0];
2629 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2630 rdev->pm.power_state[state_index].pcie_lanes = 16;
2631 rdev->pm.default_power_state_index = state_index;
2632 rdev->pm.power_state[state_index].flags = 0;
2633 state_index++;
2634 }
2635 }
2636 }
2637
2638 rdev->pm.num_power_states = state_index;
2639
2640 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2641 rdev->pm.current_clock_mode_index = 0;
2642 if (rdev->pm.default_power_state_index >= 0)
2643 rdev->pm.current_vddc =
2644 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2645 else
2646 rdev->pm.current_vddc = 0;
2647 }
2648
radeon_atom_set_clock_gating(struct radeon_device * rdev,int enable)2649 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2650 {
2651 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2652 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2653
2654 args.ucEnable = enable;
2655
2656 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2657 }
2658
radeon_atom_get_engine_clock(struct radeon_device * rdev)2659 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2660 {
2661 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2662 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2663
2664 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2665 return le32_to_cpu(args.ulReturnEngineClock);
2666 }
2667
radeon_atom_get_memory_clock(struct radeon_device * rdev)2668 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2669 {
2670 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2671 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2672
2673 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2674 return le32_to_cpu(args.ulReturnMemoryClock);
2675 }
2676
radeon_atom_set_engine_clock(struct radeon_device * rdev,uint32_t eng_clock)2677 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2678 uint32_t eng_clock)
2679 {
2680 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2681 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2682
2683 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
2684
2685 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2686 }
2687
radeon_atom_set_memory_clock(struct radeon_device * rdev,uint32_t mem_clock)2688 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2689 uint32_t mem_clock)
2690 {
2691 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2692 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2693
2694 if (rdev->flags & RADEON_IS_IGP)
2695 return;
2696
2697 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
2698
2699 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2700 }
2701
2702 union set_voltage {
2703 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2704 struct _SET_VOLTAGE_PARAMETERS v1;
2705 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2706 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
2707 };
2708
radeon_atom_set_voltage(struct radeon_device * rdev,u16 voltage_level,u8 voltage_type)2709 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
2710 {
2711 union set_voltage args;
2712 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2713 u8 frev, crev, volt_index = voltage_level;
2714
2715 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2716 return;
2717
2718 /* 0xff01 is a flag rather then an actual voltage */
2719 if (voltage_level == 0xff01)
2720 return;
2721
2722 switch (crev) {
2723 case 1:
2724 args.v1.ucVoltageType = voltage_type;
2725 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2726 args.v1.ucVoltageIndex = volt_index;
2727 break;
2728 case 2:
2729 args.v2.ucVoltageType = voltage_type;
2730 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2731 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
2732 break;
2733 case 3:
2734 args.v3.ucVoltageType = voltage_type;
2735 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
2736 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
2737 break;
2738 default:
2739 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2740 return;
2741 }
2742
2743 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2744 }
2745
radeon_atom_get_max_vddc(struct radeon_device * rdev,u8 voltage_type,u16 voltage_id,u16 * voltage)2746 static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
2747 u16 voltage_id, u16 *voltage)
2748 {
2749 union set_voltage args;
2750 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2751 u8 frev, crev;
2752
2753 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2754 return -EINVAL;
2755
2756 switch (crev) {
2757 case 1:
2758 return -EINVAL;
2759 case 2:
2760 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2761 args.v2.ucVoltageMode = 0;
2762 args.v2.usVoltageLevel = 0;
2763
2764 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2765
2766 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2767 break;
2768 case 3:
2769 args.v3.ucVoltageType = voltage_type;
2770 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
2771 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
2772
2773 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2774
2775 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
2776 break;
2777 default:
2778 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2779 return -EINVAL;
2780 }
2781
2782 return 0;
2783 }
2784
radeon_atom_initialize_bios_scratch_regs(struct drm_device * dev)2785 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2786 {
2787 struct radeon_device *rdev = dev->dev_private;
2788 uint32_t bios_2_scratch, bios_6_scratch;
2789
2790 if (rdev->family >= CHIP_R600) {
2791 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2792 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2793 } else {
2794 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2795 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2796 }
2797
2798 /* let the bios control the backlight */
2799 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2800
2801 /* tell the bios not to handle mode switching */
2802 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
2803
2804 if (rdev->family >= CHIP_R600) {
2805 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2806 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2807 } else {
2808 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2809 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2810 }
2811
2812 }
2813
radeon_save_bios_scratch_regs(struct radeon_device * rdev)2814 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2815 {
2816 uint32_t scratch_reg;
2817 int i;
2818
2819 if (rdev->family >= CHIP_R600)
2820 scratch_reg = R600_BIOS_0_SCRATCH;
2821 else
2822 scratch_reg = RADEON_BIOS_0_SCRATCH;
2823
2824 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2825 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2826 }
2827
radeon_restore_bios_scratch_regs(struct radeon_device * rdev)2828 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2829 {
2830 uint32_t scratch_reg;
2831 int i;
2832
2833 if (rdev->family >= CHIP_R600)
2834 scratch_reg = R600_BIOS_0_SCRATCH;
2835 else
2836 scratch_reg = RADEON_BIOS_0_SCRATCH;
2837
2838 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2839 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2840 }
2841
radeon_atom_output_lock(struct drm_encoder * encoder,bool lock)2842 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2843 {
2844 struct drm_device *dev = encoder->dev;
2845 struct radeon_device *rdev = dev->dev_private;
2846 uint32_t bios_6_scratch;
2847
2848 if (rdev->family >= CHIP_R600)
2849 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2850 else
2851 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2852
2853 if (lock) {
2854 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2855 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2856 } else {
2857 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2858 bios_6_scratch |= ATOM_S6_ACC_MODE;
2859 }
2860
2861 if (rdev->family >= CHIP_R600)
2862 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2863 else
2864 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2865 }
2866
2867 /* at some point we may want to break this out into individual functions */
2868 void
radeon_atombios_connected_scratch_regs(struct drm_connector * connector,struct drm_encoder * encoder,bool connected)2869 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2870 struct drm_encoder *encoder,
2871 bool connected)
2872 {
2873 struct drm_device *dev = connector->dev;
2874 struct radeon_device *rdev = dev->dev_private;
2875 struct radeon_connector *radeon_connector =
2876 to_radeon_connector(connector);
2877 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2878 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2879
2880 if (rdev->family >= CHIP_R600) {
2881 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2882 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2883 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2884 } else {
2885 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2886 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2887 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2888 }
2889
2890 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2891 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2892 if (connected) {
2893 DRM_DEBUG_KMS("TV1 connected\n");
2894 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2895 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2896 } else {
2897 DRM_DEBUG_KMS("TV1 disconnected\n");
2898 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2899 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2900 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2901 }
2902 }
2903 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2904 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2905 if (connected) {
2906 DRM_DEBUG_KMS("CV connected\n");
2907 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2908 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2909 } else {
2910 DRM_DEBUG_KMS("CV disconnected\n");
2911 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2912 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2913 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2914 }
2915 }
2916 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2917 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2918 if (connected) {
2919 DRM_DEBUG_KMS("LCD1 connected\n");
2920 bios_0_scratch |= ATOM_S0_LCD1;
2921 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2922 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2923 } else {
2924 DRM_DEBUG_KMS("LCD1 disconnected\n");
2925 bios_0_scratch &= ~ATOM_S0_LCD1;
2926 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2927 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2928 }
2929 }
2930 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2931 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2932 if (connected) {
2933 DRM_DEBUG_KMS("CRT1 connected\n");
2934 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2935 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2936 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2937 } else {
2938 DRM_DEBUG_KMS("CRT1 disconnected\n");
2939 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2940 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2941 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2942 }
2943 }
2944 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2945 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2946 if (connected) {
2947 DRM_DEBUG_KMS("CRT2 connected\n");
2948 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2949 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2950 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2951 } else {
2952 DRM_DEBUG_KMS("CRT2 disconnected\n");
2953 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2954 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2955 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2956 }
2957 }
2958 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2959 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2960 if (connected) {
2961 DRM_DEBUG_KMS("DFP1 connected\n");
2962 bios_0_scratch |= ATOM_S0_DFP1;
2963 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2964 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2965 } else {
2966 DRM_DEBUG_KMS("DFP1 disconnected\n");
2967 bios_0_scratch &= ~ATOM_S0_DFP1;
2968 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2969 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2970 }
2971 }
2972 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2973 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2974 if (connected) {
2975 DRM_DEBUG_KMS("DFP2 connected\n");
2976 bios_0_scratch |= ATOM_S0_DFP2;
2977 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2978 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2979 } else {
2980 DRM_DEBUG_KMS("DFP2 disconnected\n");
2981 bios_0_scratch &= ~ATOM_S0_DFP2;
2982 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2983 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2984 }
2985 }
2986 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2987 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2988 if (connected) {
2989 DRM_DEBUG_KMS("DFP3 connected\n");
2990 bios_0_scratch |= ATOM_S0_DFP3;
2991 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2992 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2993 } else {
2994 DRM_DEBUG_KMS("DFP3 disconnected\n");
2995 bios_0_scratch &= ~ATOM_S0_DFP3;
2996 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2997 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2998 }
2999 }
3000 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
3001 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
3002 if (connected) {
3003 DRM_DEBUG_KMS("DFP4 connected\n");
3004 bios_0_scratch |= ATOM_S0_DFP4;
3005 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
3006 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
3007 } else {
3008 DRM_DEBUG_KMS("DFP4 disconnected\n");
3009 bios_0_scratch &= ~ATOM_S0_DFP4;
3010 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
3011 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
3012 }
3013 }
3014 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
3015 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
3016 if (connected) {
3017 DRM_DEBUG_KMS("DFP5 connected\n");
3018 bios_0_scratch |= ATOM_S0_DFP5;
3019 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
3020 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
3021 } else {
3022 DRM_DEBUG_KMS("DFP5 disconnected\n");
3023 bios_0_scratch &= ~ATOM_S0_DFP5;
3024 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
3025 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
3026 }
3027 }
3028 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
3029 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
3030 if (connected) {
3031 DRM_DEBUG_KMS("DFP6 connected\n");
3032 bios_0_scratch |= ATOM_S0_DFP6;
3033 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
3034 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
3035 } else {
3036 DRM_DEBUG_KMS("DFP6 disconnected\n");
3037 bios_0_scratch &= ~ATOM_S0_DFP6;
3038 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
3039 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
3040 }
3041 }
3042
3043 if (rdev->family >= CHIP_R600) {
3044 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
3045 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3046 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
3047 } else {
3048 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3049 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3050 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3051 }
3052 }
3053
3054 void
radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder * encoder,int crtc)3055 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3056 {
3057 struct drm_device *dev = encoder->dev;
3058 struct radeon_device *rdev = dev->dev_private;
3059 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3060 uint32_t bios_3_scratch;
3061
3062 if (ASIC_IS_DCE4(rdev))
3063 return;
3064
3065 if (rdev->family >= CHIP_R600)
3066 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
3067 else
3068 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
3069
3070 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3071 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
3072 bios_3_scratch |= (crtc << 18);
3073 }
3074 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3075 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
3076 bios_3_scratch |= (crtc << 24);
3077 }
3078 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3079 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
3080 bios_3_scratch |= (crtc << 16);
3081 }
3082 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3083 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
3084 bios_3_scratch |= (crtc << 20);
3085 }
3086 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3087 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
3088 bios_3_scratch |= (crtc << 17);
3089 }
3090 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3091 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
3092 bios_3_scratch |= (crtc << 19);
3093 }
3094 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3095 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
3096 bios_3_scratch |= (crtc << 23);
3097 }
3098 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3099 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
3100 bios_3_scratch |= (crtc << 25);
3101 }
3102
3103 if (rdev->family >= CHIP_R600)
3104 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3105 else
3106 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3107 }
3108
3109 void
radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder * encoder,bool on)3110 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3111 {
3112 struct drm_device *dev = encoder->dev;
3113 struct radeon_device *rdev = dev->dev_private;
3114 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3115 uint32_t bios_2_scratch;
3116
3117 if (ASIC_IS_DCE4(rdev))
3118 return;
3119
3120 if (rdev->family >= CHIP_R600)
3121 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
3122 else
3123 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
3124
3125 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3126 if (on)
3127 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
3128 else
3129 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
3130 }
3131 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3132 if (on)
3133 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
3134 else
3135 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
3136 }
3137 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3138 if (on)
3139 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
3140 else
3141 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
3142 }
3143 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3144 if (on)
3145 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
3146 else
3147 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
3148 }
3149 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3150 if (on)
3151 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
3152 else
3153 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
3154 }
3155 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3156 if (on)
3157 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
3158 else
3159 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
3160 }
3161 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3162 if (on)
3163 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
3164 else
3165 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
3166 }
3167 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3168 if (on)
3169 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
3170 else
3171 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
3172 }
3173 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
3174 if (on)
3175 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
3176 else
3177 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
3178 }
3179 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
3180 if (on)
3181 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
3182 else
3183 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
3184 }
3185
3186 if (rdev->family >= CHIP_R600)
3187 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3188 else
3189 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
3190 }
3191