1 /*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
22 */
23
24 #include <linux/debugfs.h>
25 #include <linux/hwmon-sysfs.h>
26 #include <linux/hwmon.h>
27 #include <linux/pci.h>
28 #include <linux/power_supply.h>
29
30 #include <drm/drm_vblank.h>
31
32 #include "atom.h"
33 #include "avivod.h"
34 #include "r600_dpm.h"
35 #include "radeon.h"
36 #include "radeon_pm.h"
37
38 #define RADEON_IDLE_LOOP_MS 100
39 #define RADEON_RECLOCK_DELAY_MS 200
40 #define RADEON_WAIT_VBLANK_TIMEOUT 200
41
42 static const char *radeon_pm_state_type_name[5] = {
43 "",
44 "Powersave",
45 "Battery",
46 "Balanced",
47 "Performance",
48 };
49
50 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
51 static void radeon_debugfs_pm_init(struct radeon_device *rdev);
52 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
53 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
54 static void radeon_pm_update_profile(struct radeon_device *rdev);
55 static void radeon_pm_set_clocks(struct radeon_device *rdev);
56
radeon_pm_get_type_index(struct radeon_device * rdev,enum radeon_pm_state_type ps_type,int instance)57 int radeon_pm_get_type_index(struct radeon_device *rdev,
58 enum radeon_pm_state_type ps_type,
59 int instance)
60 {
61 int i;
62 int found_instance = -1;
63
64 for (i = 0; i < rdev->pm.num_power_states; i++) {
65 if (rdev->pm.power_state[i].type == ps_type) {
66 found_instance++;
67 if (found_instance == instance)
68 return i;
69 }
70 }
71 /* return default if no match */
72 return rdev->pm.default_power_state_index;
73 }
74
radeon_pm_acpi_event_handler(struct radeon_device * rdev)75 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
76 {
77 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
78 mutex_lock(&rdev->pm.mutex);
79 if (power_supply_is_system_supplied() > 0)
80 rdev->pm.dpm.ac_power = true;
81 else
82 rdev->pm.dpm.ac_power = false;
83 if (rdev->family == CHIP_ARUBA) {
84 if (rdev->asic->dpm.enable_bapm)
85 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
86 }
87 mutex_unlock(&rdev->pm.mutex);
88 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
89 if (rdev->pm.profile == PM_PROFILE_AUTO) {
90 mutex_lock(&rdev->pm.mutex);
91 radeon_pm_update_profile(rdev);
92 radeon_pm_set_clocks(rdev);
93 mutex_unlock(&rdev->pm.mutex);
94 }
95 }
96 }
97
radeon_pm_update_profile(struct radeon_device * rdev)98 static void radeon_pm_update_profile(struct radeon_device *rdev)
99 {
100 switch (rdev->pm.profile) {
101 case PM_PROFILE_DEFAULT:
102 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
103 break;
104 case PM_PROFILE_AUTO:
105 if (power_supply_is_system_supplied() > 0) {
106 if (rdev->pm.active_crtc_count > 1)
107 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
108 else
109 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
110 } else {
111 if (rdev->pm.active_crtc_count > 1)
112 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
113 else
114 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
115 }
116 break;
117 case PM_PROFILE_LOW:
118 if (rdev->pm.active_crtc_count > 1)
119 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
120 else
121 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
122 break;
123 case PM_PROFILE_MID:
124 if (rdev->pm.active_crtc_count > 1)
125 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
126 else
127 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
128 break;
129 case PM_PROFILE_HIGH:
130 if (rdev->pm.active_crtc_count > 1)
131 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
132 else
133 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
134 break;
135 }
136
137 if (rdev->pm.active_crtc_count == 0) {
138 rdev->pm.requested_power_state_index =
139 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
140 rdev->pm.requested_clock_mode_index =
141 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
142 } else {
143 rdev->pm.requested_power_state_index =
144 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
145 rdev->pm.requested_clock_mode_index =
146 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
147 }
148 }
149
radeon_unmap_vram_bos(struct radeon_device * rdev)150 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
151 {
152 struct radeon_bo *bo, *n;
153
154 if (list_empty(&rdev->gem.objects))
155 return;
156
157 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
158 if (bo->tbo.resource->mem_type == TTM_PL_VRAM)
159 ttm_bo_unmap_virtual(&bo->tbo);
160 }
161 }
162
radeon_sync_with_vblank(struct radeon_device * rdev)163 static void radeon_sync_with_vblank(struct radeon_device *rdev)
164 {
165 if (rdev->pm.active_crtcs) {
166 rdev->pm.vblank_sync = false;
167 wait_event_timeout(
168 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
169 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
170 }
171 }
172
radeon_set_power_state(struct radeon_device * rdev)173 static void radeon_set_power_state(struct radeon_device *rdev)
174 {
175 u32 sclk, mclk;
176 bool misc_after = false;
177
178 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
179 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
180 return;
181
182 if (radeon_gui_idle(rdev)) {
183 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
184 clock_info[rdev->pm.requested_clock_mode_index].sclk;
185 if (sclk > rdev->pm.default_sclk)
186 sclk = rdev->pm.default_sclk;
187
188 /* starting with BTC, there is one state that is used for both
189 * MH and SH. Difference is that we always use the high clock index for
190 * mclk and vddci.
191 */
192 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
193 (rdev->family >= CHIP_BARTS) &&
194 rdev->pm.active_crtc_count &&
195 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
196 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
197 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
198 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
199 else
200 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
201 clock_info[rdev->pm.requested_clock_mode_index].mclk;
202
203 if (mclk > rdev->pm.default_mclk)
204 mclk = rdev->pm.default_mclk;
205
206 /* upvolt before raising clocks, downvolt after lowering clocks */
207 if (sclk < rdev->pm.current_sclk)
208 misc_after = true;
209
210 radeon_sync_with_vblank(rdev);
211
212 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
213 if (!radeon_pm_in_vbl(rdev))
214 return;
215 }
216
217 radeon_pm_prepare(rdev);
218
219 if (!misc_after)
220 /* voltage, pcie lanes, etc.*/
221 radeon_pm_misc(rdev);
222
223 /* set engine clock */
224 if (sclk != rdev->pm.current_sclk) {
225 radeon_pm_debug_check_in_vbl(rdev, false);
226 radeon_set_engine_clock(rdev, sclk);
227 radeon_pm_debug_check_in_vbl(rdev, true);
228 rdev->pm.current_sclk = sclk;
229 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
230 }
231
232 /* set memory clock */
233 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
234 radeon_pm_debug_check_in_vbl(rdev, false);
235 radeon_set_memory_clock(rdev, mclk);
236 radeon_pm_debug_check_in_vbl(rdev, true);
237 rdev->pm.current_mclk = mclk;
238 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
239 }
240
241 if (misc_after)
242 /* voltage, pcie lanes, etc.*/
243 radeon_pm_misc(rdev);
244
245 radeon_pm_finish(rdev);
246
247 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
248 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
249 } else
250 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
251 }
252
radeon_pm_set_clocks(struct radeon_device * rdev)253 static void radeon_pm_set_clocks(struct radeon_device *rdev)
254 {
255 struct drm_crtc *crtc;
256 int i, r;
257
258 /* no need to take locks, etc. if nothing's going to change */
259 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
260 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
261 return;
262
263 down_write(&rdev->pm.mclk_lock);
264 mutex_lock(&rdev->ring_lock);
265
266 /* wait for the rings to drain */
267 for (i = 0; i < RADEON_NUM_RINGS; i++) {
268 struct radeon_ring *ring = &rdev->ring[i];
269 if (!ring->ready) {
270 continue;
271 }
272 r = radeon_fence_wait_empty(rdev, i);
273 if (r) {
274 /* needs a GPU reset dont reset here */
275 mutex_unlock(&rdev->ring_lock);
276 up_write(&rdev->pm.mclk_lock);
277 return;
278 }
279 }
280
281 radeon_unmap_vram_bos(rdev);
282
283 if (rdev->irq.installed) {
284 i = 0;
285 drm_for_each_crtc(crtc, rdev_to_drm(rdev)) {
286 if (rdev->pm.active_crtcs & (1 << i)) {
287 /* This can fail if a modeset is in progress */
288 if (drm_crtc_vblank_get(crtc) == 0)
289 rdev->pm.req_vblank |= (1 << i);
290 else
291 DRM_DEBUG_DRIVER("crtc %d no vblank, can glitch\n",
292 i);
293 }
294 i++;
295 }
296 }
297
298 radeon_set_power_state(rdev);
299
300 if (rdev->irq.installed) {
301 i = 0;
302 drm_for_each_crtc(crtc, rdev_to_drm(rdev)) {
303 if (rdev->pm.req_vblank & (1 << i)) {
304 rdev->pm.req_vblank &= ~(1 << i);
305 drm_crtc_vblank_put(crtc);
306 }
307 i++;
308 }
309 }
310
311 /* update display watermarks based on new power state */
312 radeon_update_bandwidth_info(rdev);
313 if (rdev->pm.active_crtc_count)
314 radeon_bandwidth_update(rdev);
315
316 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
317
318 mutex_unlock(&rdev->ring_lock);
319 up_write(&rdev->pm.mclk_lock);
320 }
321
radeon_pm_print_states(struct radeon_device * rdev)322 static void radeon_pm_print_states(struct radeon_device *rdev)
323 {
324 int i, j;
325 struct radeon_power_state *power_state;
326 struct radeon_pm_clock_info *clock_info;
327
328 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
329 for (i = 0; i < rdev->pm.num_power_states; i++) {
330 power_state = &rdev->pm.power_state[i];
331 DRM_DEBUG_DRIVER("State %d: %s\n", i,
332 radeon_pm_state_type_name[power_state->type]);
333 if (i == rdev->pm.default_power_state_index)
334 DRM_DEBUG_DRIVER("\tDefault");
335 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
336 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
337 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
338 DRM_DEBUG_DRIVER("\tSingle display only\n");
339 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
340 for (j = 0; j < power_state->num_clock_modes; j++) {
341 clock_info = &(power_state->clock_info[j]);
342 if (rdev->flags & RADEON_IS_IGP)
343 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
344 j,
345 clock_info->sclk * 10);
346 else
347 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
348 j,
349 clock_info->sclk * 10,
350 clock_info->mclk * 10,
351 clock_info->voltage.voltage);
352 }
353 }
354 }
355
356 #ifdef notyet
radeon_get_pm_profile(struct device * dev,struct device_attribute * attr,char * buf)357 static ssize_t radeon_get_pm_profile(struct device *dev,
358 struct device_attribute *attr,
359 char *buf)
360 {
361 struct drm_device *ddev = dev_get_drvdata(dev);
362 struct radeon_device *rdev = ddev->dev_private;
363 int cp = rdev->pm.profile;
364
365 return sysfs_emit(buf, "%s\n", (cp == PM_PROFILE_AUTO) ? "auto" :
366 (cp == PM_PROFILE_LOW) ? "low" :
367 (cp == PM_PROFILE_MID) ? "mid" :
368 (cp == PM_PROFILE_HIGH) ? "high" : "default");
369 }
370
radeon_set_pm_profile(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)371 static ssize_t radeon_set_pm_profile(struct device *dev,
372 struct device_attribute *attr,
373 const char *buf,
374 size_t count)
375 {
376 struct drm_device *ddev = dev_get_drvdata(dev);
377 struct radeon_device *rdev = ddev->dev_private;
378
379 /* Can't set profile when the card is off */
380 #ifdef notyet
381 if ((rdev->flags & RADEON_IS_PX) &&
382 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
383 return -EINVAL;
384 #endif
385
386 mutex_lock(&rdev->pm.mutex);
387 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
388 if (strncmp("default", buf, strlen("default")) == 0)
389 rdev->pm.profile = PM_PROFILE_DEFAULT;
390 else if (strncmp("auto", buf, strlen("auto")) == 0)
391 rdev->pm.profile = PM_PROFILE_AUTO;
392 else if (strncmp("low", buf, strlen("low")) == 0)
393 rdev->pm.profile = PM_PROFILE_LOW;
394 else if (strncmp("mid", buf, strlen("mid")) == 0)
395 rdev->pm.profile = PM_PROFILE_MID;
396 else if (strncmp("high", buf, strlen("high")) == 0)
397 rdev->pm.profile = PM_PROFILE_HIGH;
398 else {
399 count = -EINVAL;
400 goto fail;
401 }
402 radeon_pm_update_profile(rdev);
403 radeon_pm_set_clocks(rdev);
404 } else
405 count = -EINVAL;
406
407 fail:
408 mutex_unlock(&rdev->pm.mutex);
409
410 return count;
411 }
412
radeon_get_pm_method(struct device * dev,struct device_attribute * attr,char * buf)413 static ssize_t radeon_get_pm_method(struct device *dev,
414 struct device_attribute *attr,
415 char *buf)
416 {
417 struct drm_device *ddev = dev_get_drvdata(dev);
418 struct radeon_device *rdev = ddev->dev_private;
419 int pm = rdev->pm.pm_method;
420
421 return sysfs_emit(buf, "%s\n", (pm == PM_METHOD_DYNPM) ? "dynpm" :
422 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
423 }
424
radeon_set_pm_method(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)425 static ssize_t radeon_set_pm_method(struct device *dev,
426 struct device_attribute *attr,
427 const char *buf,
428 size_t count)
429 {
430 struct drm_device *ddev = dev_get_drvdata(dev);
431 struct radeon_device *rdev = ddev->dev_private;
432
433 #ifdef notyet
434 /* Can't set method when the card is off */
435 if ((rdev->flags & RADEON_IS_PX) &&
436 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
437 count = -EINVAL;
438 goto fail;
439 }
440 #endif
441
442 /* we don't support the legacy modes with dpm */
443 if (rdev->pm.pm_method == PM_METHOD_DPM) {
444 count = -EINVAL;
445 goto fail;
446 }
447
448 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
449 mutex_lock(&rdev->pm.mutex);
450 rdev->pm.pm_method = PM_METHOD_DYNPM;
451 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
452 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
453 mutex_unlock(&rdev->pm.mutex);
454 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
455 mutex_lock(&rdev->pm.mutex);
456 /* disable dynpm */
457 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
458 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
459 rdev->pm.pm_method = PM_METHOD_PROFILE;
460 mutex_unlock(&rdev->pm.mutex);
461 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
462 } else {
463 count = -EINVAL;
464 goto fail;
465 }
466 radeon_pm_compute_clocks(rdev);
467 fail:
468 return count;
469 }
470
radeon_get_dpm_state(struct device * dev,struct device_attribute * attr,char * buf)471 static ssize_t radeon_get_dpm_state(struct device *dev,
472 struct device_attribute *attr,
473 char *buf)
474 {
475 struct drm_device *ddev = dev_get_drvdata(dev);
476 struct radeon_device *rdev = ddev->dev_private;
477 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
478
479 return sysfs_emit(buf, "%s\n",
480 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
481 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
482 }
483
radeon_set_dpm_state(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)484 static ssize_t radeon_set_dpm_state(struct device *dev,
485 struct device_attribute *attr,
486 const char *buf,
487 size_t count)
488 {
489 struct drm_device *ddev = dev_get_drvdata(dev);
490 struct radeon_device *rdev = ddev->dev_private;
491
492 mutex_lock(&rdev->pm.mutex);
493 if (strncmp("battery", buf, strlen("battery")) == 0)
494 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
495 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
496 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
497 else if (strncmp("performance", buf, strlen("performance")) == 0)
498 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
499 else {
500 mutex_unlock(&rdev->pm.mutex);
501 count = -EINVAL;
502 goto fail;
503 }
504 mutex_unlock(&rdev->pm.mutex);
505
506 /* Can't set dpm state when the card is off */
507 #ifdef notyet
508 if (!(rdev->flags & RADEON_IS_PX) ||
509 (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
510 #endif
511 radeon_pm_compute_clocks(rdev);
512
513 fail:
514 return count;
515 }
516
radeon_get_dpm_forced_performance_level(struct device * dev,struct device_attribute * attr,char * buf)517 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
518 struct device_attribute *attr,
519 char *buf)
520 {
521 struct drm_device *ddev = dev_get_drvdata(dev);
522 struct radeon_device *rdev = ddev->dev_private;
523 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
524
525 #ifdef notyet
526 if ((rdev->flags & RADEON_IS_PX) &&
527 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
528 return sysfs_emit(buf, "off\n");
529 #endif
530
531 return sysfs_emit(buf, "%s\n",
532 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
533 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
534 }
535
radeon_set_dpm_forced_performance_level(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)536 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
537 struct device_attribute *attr,
538 const char *buf,
539 size_t count)
540 {
541 struct drm_device *ddev = dev_get_drvdata(dev);
542 struct radeon_device *rdev = ddev->dev_private;
543 enum radeon_dpm_forced_level level;
544 int ret = 0;
545
546 /* Can't force performance level when the card is off */
547 #ifdef notyet
548 if ((rdev->flags & RADEON_IS_PX) &&
549 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
550 return -EINVAL;
551 #endif
552
553 mutex_lock(&rdev->pm.mutex);
554 if (strncmp("low", buf, strlen("low")) == 0) {
555 level = RADEON_DPM_FORCED_LEVEL_LOW;
556 } else if (strncmp("high", buf, strlen("high")) == 0) {
557 level = RADEON_DPM_FORCED_LEVEL_HIGH;
558 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
559 level = RADEON_DPM_FORCED_LEVEL_AUTO;
560 } else {
561 count = -EINVAL;
562 goto fail;
563 }
564 if (rdev->asic->dpm.force_performance_level) {
565 if (rdev->pm.dpm.thermal_active) {
566 count = -EINVAL;
567 goto fail;
568 }
569 ret = radeon_dpm_force_performance_level(rdev, level);
570 if (ret)
571 count = -EINVAL;
572 }
573 fail:
574 mutex_unlock(&rdev->pm.mutex);
575
576 return count;
577 }
578 #endif
579
580 #ifdef notyet
radeon_hwmon_get_pwm1_enable(struct device * dev,struct device_attribute * attr,char * buf)581 static ssize_t radeon_hwmon_get_pwm1_enable(struct device *dev,
582 struct device_attribute *attr,
583 char *buf)
584 {
585 struct radeon_device *rdev = dev_get_drvdata(dev);
586 u32 pwm_mode = 0;
587
588 if (rdev->asic->dpm.fan_ctrl_get_mode)
589 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev);
590
591 /* never 0 (full-speed), fuse or smc-controlled always */
592 return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2);
593 }
594
radeon_hwmon_set_pwm1_enable(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)595 static ssize_t radeon_hwmon_set_pwm1_enable(struct device *dev,
596 struct device_attribute *attr,
597 const char *buf,
598 size_t count)
599 {
600 struct radeon_device *rdev = dev_get_drvdata(dev);
601 int err;
602 int value;
603
604 if (!rdev->asic->dpm.fan_ctrl_set_mode)
605 return -EINVAL;
606
607 err = kstrtoint(buf, 10, &value);
608 if (err)
609 return err;
610
611 switch (value) {
612 case 1: /* manual, percent-based */
613 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC);
614 break;
615 default: /* disable */
616 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0);
617 break;
618 }
619
620 return count;
621 }
622
radeon_hwmon_get_pwm1_min(struct device * dev,struct device_attribute * attr,char * buf)623 static ssize_t radeon_hwmon_get_pwm1_min(struct device *dev,
624 struct device_attribute *attr,
625 char *buf)
626 {
627 return sprintf(buf, "%i\n", 0);
628 }
629
radeon_hwmon_get_pwm1_max(struct device * dev,struct device_attribute * attr,char * buf)630 static ssize_t radeon_hwmon_get_pwm1_max(struct device *dev,
631 struct device_attribute *attr,
632 char *buf)
633 {
634 return sprintf(buf, "%i\n", 255);
635 }
636
radeon_hwmon_set_pwm1(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)637 static ssize_t radeon_hwmon_set_pwm1(struct device *dev,
638 struct device_attribute *attr,
639 const char *buf, size_t count)
640 {
641 struct radeon_device *rdev = dev_get_drvdata(dev);
642 int err;
643 u32 value;
644
645 err = kstrtou32(buf, 10, &value);
646 if (err)
647 return err;
648
649 value = (value * 100) / 255;
650
651 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value);
652 if (err)
653 return err;
654
655 return count;
656 }
657
radeon_hwmon_get_pwm1(struct device * dev,struct device_attribute * attr,char * buf)658 static ssize_t radeon_hwmon_get_pwm1(struct device *dev,
659 struct device_attribute *attr,
660 char *buf)
661 {
662 struct radeon_device *rdev = dev_get_drvdata(dev);
663 int err;
664 u32 speed;
665
666 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed);
667 if (err)
668 return err;
669
670 speed = (speed * 255) / 100;
671
672 return sprintf(buf, "%i\n", speed);
673 }
674
675 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
676 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
677 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
678 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
679 radeon_get_dpm_forced_performance_level,
680 radeon_set_dpm_forced_performance_level);
681
radeon_hwmon_show_temp(struct device * dev,struct device_attribute * attr,char * buf)682 static ssize_t radeon_hwmon_show_temp(struct device *dev,
683 struct device_attribute *attr,
684 char *buf)
685 {
686 struct radeon_device *rdev = dev_get_drvdata(dev);
687 struct drm_device *ddev = rdev_to_drm(rdev);
688 int temp;
689
690 /* Can't get temperature when the card is off */
691 if ((rdev->flags & RADEON_IS_PX) &&
692 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
693 return -EINVAL;
694
695 if (rdev->asic->pm.get_temperature)
696 temp = radeon_get_temperature(rdev);
697 else
698 temp = 0;
699
700 return sysfs_emit(buf, "%d\n", temp);
701 }
702
radeon_hwmon_show_temp_thresh(struct device * dev,struct device_attribute * attr,char * buf)703 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
704 struct device_attribute *attr,
705 char *buf)
706 {
707 struct radeon_device *rdev = dev_get_drvdata(dev);
708 int hyst = to_sensor_dev_attr(attr)->index;
709 int temp;
710
711 if (hyst)
712 temp = rdev->pm.dpm.thermal.min_temp;
713 else
714 temp = rdev->pm.dpm.thermal.max_temp;
715
716 return sysfs_emit(buf, "%d\n", temp);
717 }
718
719 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
720 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
721 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
722 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1, radeon_hwmon_set_pwm1, 0);
723 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1_enable, radeon_hwmon_set_pwm1_enable, 0);
724 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, radeon_hwmon_get_pwm1_min, NULL, 0);
725 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, radeon_hwmon_get_pwm1_max, NULL, 0);
726
radeon_hwmon_show_sclk(struct device * dev,struct device_attribute * attr,char * buf)727 static ssize_t radeon_hwmon_show_sclk(struct device *dev,
728 struct device_attribute *attr, char *buf)
729 {
730 struct radeon_device *rdev = dev_get_drvdata(dev);
731 struct drm_device *ddev = rdev_to_drm(rdev);
732 u32 sclk = 0;
733
734 /* Can't get clock frequency when the card is off */
735 if ((rdev->flags & RADEON_IS_PX) &&
736 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
737 return -EINVAL;
738
739 if (rdev->asic->dpm.get_current_sclk)
740 sclk = radeon_dpm_get_current_sclk(rdev);
741
742 /* Value returned by dpm is in 10 KHz units, need to convert it into Hz
743 for hwmon */
744 sclk *= 10000;
745
746 return sysfs_emit(buf, "%u\n", sclk);
747 }
748
749 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, radeon_hwmon_show_sclk, NULL,
750 0);
751
radeon_hwmon_show_vddc(struct device * dev,struct device_attribute * attr,char * buf)752 static ssize_t radeon_hwmon_show_vddc(struct device *dev,
753 struct device_attribute *attr, char *buf)
754 {
755 struct radeon_device *rdev = dev_get_drvdata(dev);
756 struct drm_device *ddev = rdev_to_drm(rdev);
757 u16 vddc = 0;
758
759 /* Can't get vddc when the card is off */
760 if ((rdev->flags & RADEON_IS_PX) &&
761 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
762 return -EINVAL;
763
764 if (rdev->asic->dpm.get_current_vddc)
765 vddc = rdev->asic->dpm.get_current_vddc(rdev);
766
767 return sysfs_emit(buf, "%u\n", vddc);
768 }
769
770 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, radeon_hwmon_show_vddc, NULL,
771 0);
772
773 static struct attribute *hwmon_attributes[] = {
774 &sensor_dev_attr_temp1_input.dev_attr.attr,
775 &sensor_dev_attr_temp1_crit.dev_attr.attr,
776 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
777 &sensor_dev_attr_pwm1.dev_attr.attr,
778 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
779 &sensor_dev_attr_pwm1_min.dev_attr.attr,
780 &sensor_dev_attr_pwm1_max.dev_attr.attr,
781 &sensor_dev_attr_freq1_input.dev_attr.attr,
782 &sensor_dev_attr_in0_input.dev_attr.attr,
783 NULL
784 };
785
hwmon_attributes_visible(struct kobject * kobj,struct attribute * attr,int index)786 static umode_t hwmon_attributes_visible(struct kobject *kobj,
787 struct attribute *attr, int index)
788 {
789 struct device *dev = kobj_to_dev(kobj);
790 struct radeon_device *rdev = dev_get_drvdata(dev);
791 umode_t effective_mode = attr->mode;
792
793 /* Skip attributes if DPM is not enabled */
794 if (rdev->pm.pm_method != PM_METHOD_DPM &&
795 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
796 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
797 attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
798 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
799 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
800 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
801 attr == &sensor_dev_attr_freq1_input.dev_attr.attr ||
802 attr == &sensor_dev_attr_in0_input.dev_attr.attr))
803 return 0;
804
805 /* Skip vddc attribute if get_current_vddc is not implemented */
806 if (attr == &sensor_dev_attr_in0_input.dev_attr.attr &&
807 !rdev->asic->dpm.get_current_vddc)
808 return 0;
809
810 /* Skip fan attributes if fan is not present */
811 if (rdev->pm.no_fan &&
812 (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
813 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
814 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
815 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
816 return 0;
817
818 /* mask fan attributes if we have no bindings for this asic to expose */
819 if ((!rdev->asic->dpm.get_fan_speed_percent &&
820 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
821 (!rdev->asic->dpm.fan_ctrl_get_mode &&
822 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
823 effective_mode &= ~S_IRUGO;
824
825 if ((!rdev->asic->dpm.set_fan_speed_percent &&
826 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
827 (!rdev->asic->dpm.fan_ctrl_set_mode &&
828 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
829 effective_mode &= ~S_IWUSR;
830
831 /* hide max/min values if we can't both query and manage the fan */
832 if ((!rdev->asic->dpm.set_fan_speed_percent &&
833 !rdev->asic->dpm.get_fan_speed_percent) &&
834 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
835 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
836 return 0;
837
838 return effective_mode;
839 }
840
841 static const struct attribute_group hwmon_attrgroup = {
842 .attrs = hwmon_attributes,
843 .is_visible = hwmon_attributes_visible,
844 };
845
846 static const struct attribute_group *hwmon_groups[] = {
847 &hwmon_attrgroup,
848 NULL
849 };
850 #endif
851
radeon_hwmon_init(struct radeon_device * rdev)852 static int radeon_hwmon_init(struct radeon_device *rdev)
853 {
854 int err = 0;
855
856 switch (rdev->pm.int_thermal_type) {
857 case THERMAL_TYPE_RV6XX:
858 case THERMAL_TYPE_RV770:
859 case THERMAL_TYPE_EVERGREEN:
860 case THERMAL_TYPE_NI:
861 case THERMAL_TYPE_SUMO:
862 case THERMAL_TYPE_SI:
863 case THERMAL_TYPE_CI:
864 case THERMAL_TYPE_KV:
865 if (rdev->asic->pm.get_temperature == NULL)
866 return err;
867 #ifdef notyet
868 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
869 "radeon", rdev,
870 hwmon_groups);
871 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
872 err = PTR_ERR(rdev->pm.int_hwmon_dev);
873 dev_err(rdev->dev,
874 "Unable to register hwmon device: %d\n", err);
875 }
876 #endif
877 break;
878 default:
879 break;
880 }
881
882 return err;
883 }
884
radeon_hwmon_fini(struct radeon_device * rdev)885 static void radeon_hwmon_fini(struct radeon_device *rdev)
886 {
887 #ifdef notyet
888 if (rdev->pm.int_hwmon_dev)
889 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
890 #endif
891 }
892
radeon_dpm_thermal_work_handler(struct work_struct * work)893 static void radeon_dpm_thermal_work_handler(struct work_struct *work)
894 {
895 struct radeon_device *rdev =
896 container_of(work, struct radeon_device,
897 pm.dpm.thermal.work);
898 /* switch to the thermal state */
899 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
900
901 if (!rdev->pm.dpm_enabled)
902 return;
903
904 if (rdev->asic->pm.get_temperature) {
905 int temp = radeon_get_temperature(rdev);
906
907 if (temp < rdev->pm.dpm.thermal.min_temp)
908 /* switch back the user state */
909 dpm_state = rdev->pm.dpm.user_state;
910 } else {
911 if (rdev->pm.dpm.thermal.high_to_low)
912 /* switch back the user state */
913 dpm_state = rdev->pm.dpm.user_state;
914 }
915 mutex_lock(&rdev->pm.mutex);
916 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
917 rdev->pm.dpm.thermal_active = true;
918 else
919 rdev->pm.dpm.thermal_active = false;
920 rdev->pm.dpm.state = dpm_state;
921 mutex_unlock(&rdev->pm.mutex);
922
923 radeon_pm_compute_clocks(rdev);
924 }
925
radeon_dpm_single_display(struct radeon_device * rdev)926 static bool radeon_dpm_single_display(struct radeon_device *rdev)
927 {
928 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
929 true : false;
930
931 /* check if the vblank period is too short to adjust the mclk */
932 if (single_display && rdev->asic->dpm.vblank_too_short) {
933 if (radeon_dpm_vblank_too_short(rdev))
934 single_display = false;
935 }
936
937 /* 120hz tends to be problematic even if they are under the
938 * vblank limit.
939 */
940 if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120))
941 single_display = false;
942
943 return single_display;
944 }
945
radeon_dpm_pick_power_state(struct radeon_device * rdev,enum radeon_pm_state_type dpm_state)946 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
947 enum radeon_pm_state_type dpm_state)
948 {
949 int i;
950 struct radeon_ps *ps;
951 u32 ui_class;
952 bool single_display = radeon_dpm_single_display(rdev);
953
954 /* certain older asics have a separare 3D performance state,
955 * so try that first if the user selected performance
956 */
957 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
958 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
959 /* balanced states don't exist at the moment */
960 if (dpm_state == POWER_STATE_TYPE_BALANCED)
961 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
962
963 restart_search:
964 /* Pick the best power state based on current conditions */
965 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
966 ps = &rdev->pm.dpm.ps[i];
967 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
968 switch (dpm_state) {
969 /* user states */
970 case POWER_STATE_TYPE_BATTERY:
971 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
972 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
973 if (single_display)
974 return ps;
975 } else
976 return ps;
977 }
978 break;
979 case POWER_STATE_TYPE_BALANCED:
980 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
981 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
982 if (single_display)
983 return ps;
984 } else
985 return ps;
986 }
987 break;
988 case POWER_STATE_TYPE_PERFORMANCE:
989 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
990 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
991 if (single_display)
992 return ps;
993 } else
994 return ps;
995 }
996 break;
997 /* internal states */
998 case POWER_STATE_TYPE_INTERNAL_UVD:
999 if (rdev->pm.dpm.uvd_ps)
1000 return rdev->pm.dpm.uvd_ps;
1001 else
1002 break;
1003 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1004 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
1005 return ps;
1006 break;
1007 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1008 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
1009 return ps;
1010 break;
1011 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1012 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
1013 return ps;
1014 break;
1015 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1016 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
1017 return ps;
1018 break;
1019 case POWER_STATE_TYPE_INTERNAL_BOOT:
1020 return rdev->pm.dpm.boot_ps;
1021 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1022 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1023 return ps;
1024 break;
1025 case POWER_STATE_TYPE_INTERNAL_ACPI:
1026 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
1027 return ps;
1028 break;
1029 case POWER_STATE_TYPE_INTERNAL_ULV:
1030 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
1031 return ps;
1032 break;
1033 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1034 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
1035 return ps;
1036 break;
1037 default:
1038 break;
1039 }
1040 }
1041 /* use a fallback state if we didn't match */
1042 switch (dpm_state) {
1043 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1044 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1045 goto restart_search;
1046 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1047 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1048 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1049 if (rdev->pm.dpm.uvd_ps) {
1050 return rdev->pm.dpm.uvd_ps;
1051 } else {
1052 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1053 goto restart_search;
1054 }
1055 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1056 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
1057 goto restart_search;
1058 case POWER_STATE_TYPE_INTERNAL_ACPI:
1059 dpm_state = POWER_STATE_TYPE_BATTERY;
1060 goto restart_search;
1061 case POWER_STATE_TYPE_BATTERY:
1062 case POWER_STATE_TYPE_BALANCED:
1063 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1064 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1065 goto restart_search;
1066 default:
1067 break;
1068 }
1069
1070 return NULL;
1071 }
1072
radeon_dpm_change_power_state_locked(struct radeon_device * rdev)1073 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
1074 {
1075 int i;
1076 struct radeon_ps *ps;
1077 enum radeon_pm_state_type dpm_state;
1078 int ret;
1079 bool single_display = radeon_dpm_single_display(rdev);
1080
1081 /* if dpm init failed */
1082 if (!rdev->pm.dpm_enabled)
1083 return;
1084
1085 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
1086 /* add other state override checks here */
1087 if ((!rdev->pm.dpm.thermal_active) &&
1088 (!rdev->pm.dpm.uvd_active))
1089 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
1090 }
1091 dpm_state = rdev->pm.dpm.state;
1092
1093 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
1094 if (ps)
1095 rdev->pm.dpm.requested_ps = ps;
1096 else
1097 return;
1098
1099 /* no need to reprogram if nothing changed unless we are on BTC+ */
1100 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
1101 /* vce just modifies an existing state so force a change */
1102 if (ps->vce_active != rdev->pm.dpm.vce_active)
1103 goto force;
1104 /* user has made a display change (such as timing) */
1105 if (rdev->pm.dpm.single_display != single_display)
1106 goto force;
1107 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
1108 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
1109 * all we need to do is update the display configuration.
1110 */
1111 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
1112 /* update display watermarks based on new power state */
1113 radeon_bandwidth_update(rdev);
1114 /* update displays */
1115 radeon_dpm_display_configuration_changed(rdev);
1116 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1117 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1118 }
1119 return;
1120 } else {
1121 /* for BTC+ if the num crtcs hasn't changed and state is the same,
1122 * nothing to do, if the num crtcs is > 1 and state is the same,
1123 * update display configuration.
1124 */
1125 if (rdev->pm.dpm.new_active_crtcs ==
1126 rdev->pm.dpm.current_active_crtcs) {
1127 return;
1128 } else {
1129 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
1130 (rdev->pm.dpm.new_active_crtc_count > 1)) {
1131 /* update display watermarks based on new power state */
1132 radeon_bandwidth_update(rdev);
1133 /* update displays */
1134 radeon_dpm_display_configuration_changed(rdev);
1135 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1136 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1137 return;
1138 }
1139 }
1140 }
1141 }
1142
1143 force:
1144 if (radeon_dpm == 1) {
1145 printk("switching from power state:\n");
1146 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
1147 printk("switching to power state:\n");
1148 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
1149 }
1150
1151 down_write(&rdev->pm.mclk_lock);
1152 mutex_lock(&rdev->ring_lock);
1153
1154 /* update whether vce is active */
1155 ps->vce_active = rdev->pm.dpm.vce_active;
1156
1157 ret = radeon_dpm_pre_set_power_state(rdev);
1158 if (ret)
1159 goto done;
1160
1161 /* update display watermarks based on new power state */
1162 radeon_bandwidth_update(rdev);
1163 /* update displays */
1164 radeon_dpm_display_configuration_changed(rdev);
1165
1166 /* wait for the rings to drain */
1167 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1168 struct radeon_ring *ring = &rdev->ring[i];
1169 if (ring->ready)
1170 radeon_fence_wait_empty(rdev, i);
1171 }
1172
1173 /* program the new power state */
1174 radeon_dpm_set_power_state(rdev);
1175
1176 /* update current power state */
1177 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
1178
1179 radeon_dpm_post_set_power_state(rdev);
1180
1181 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1182 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1183 rdev->pm.dpm.single_display = single_display;
1184
1185 if (rdev->asic->dpm.force_performance_level) {
1186 if (rdev->pm.dpm.thermal_active) {
1187 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
1188 /* force low perf level for thermal */
1189 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
1190 /* save the user's level */
1191 rdev->pm.dpm.forced_level = level;
1192 } else {
1193 /* otherwise, user selected level */
1194 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
1195 }
1196 }
1197
1198 done:
1199 mutex_unlock(&rdev->ring_lock);
1200 up_write(&rdev->pm.mclk_lock);
1201 }
1202
radeon_dpm_enable_uvd(struct radeon_device * rdev,bool enable)1203 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
1204 {
1205 enum radeon_pm_state_type dpm_state;
1206
1207 if (rdev->asic->dpm.powergate_uvd) {
1208 mutex_lock(&rdev->pm.mutex);
1209 /* don't powergate anything if we
1210 have active but pause streams */
1211 enable |= rdev->pm.dpm.sd > 0;
1212 enable |= rdev->pm.dpm.hd > 0;
1213 /* enable/disable UVD */
1214 radeon_dpm_powergate_uvd(rdev, !enable);
1215 mutex_unlock(&rdev->pm.mutex);
1216 } else {
1217 if (enable) {
1218 mutex_lock(&rdev->pm.mutex);
1219 rdev->pm.dpm.uvd_active = true;
1220 /* disable this for now */
1221 #if 0
1222 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
1223 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
1224 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
1225 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1226 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
1227 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1228 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
1229 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
1230 else
1231 #endif
1232 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
1233 rdev->pm.dpm.state = dpm_state;
1234 mutex_unlock(&rdev->pm.mutex);
1235 } else {
1236 mutex_lock(&rdev->pm.mutex);
1237 rdev->pm.dpm.uvd_active = false;
1238 mutex_unlock(&rdev->pm.mutex);
1239 }
1240
1241 radeon_pm_compute_clocks(rdev);
1242 }
1243 }
1244
radeon_dpm_enable_vce(struct radeon_device * rdev,bool enable)1245 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
1246 {
1247 if (enable) {
1248 mutex_lock(&rdev->pm.mutex);
1249 rdev->pm.dpm.vce_active = true;
1250 /* XXX select vce level based on ring/task */
1251 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
1252 mutex_unlock(&rdev->pm.mutex);
1253 } else {
1254 mutex_lock(&rdev->pm.mutex);
1255 rdev->pm.dpm.vce_active = false;
1256 mutex_unlock(&rdev->pm.mutex);
1257 }
1258
1259 radeon_pm_compute_clocks(rdev);
1260 }
1261
radeon_pm_suspend_old(struct radeon_device * rdev)1262 static void radeon_pm_suspend_old(struct radeon_device *rdev)
1263 {
1264 mutex_lock(&rdev->pm.mutex);
1265 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1266 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
1267 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
1268 }
1269 mutex_unlock(&rdev->pm.mutex);
1270
1271 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1272 }
1273
radeon_pm_suspend_dpm(struct radeon_device * rdev)1274 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
1275 {
1276 mutex_lock(&rdev->pm.mutex);
1277 /* disable dpm */
1278 radeon_dpm_disable(rdev);
1279 /* reset the power state */
1280 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1281 rdev->pm.dpm_enabled = false;
1282 mutex_unlock(&rdev->pm.mutex);
1283 }
1284
radeon_pm_suspend(struct radeon_device * rdev)1285 void radeon_pm_suspend(struct radeon_device *rdev)
1286 {
1287 if (rdev->pm.pm_method == PM_METHOD_DPM)
1288 radeon_pm_suspend_dpm(rdev);
1289 else
1290 radeon_pm_suspend_old(rdev);
1291 }
1292
radeon_pm_resume_old(struct radeon_device * rdev)1293 static void radeon_pm_resume_old(struct radeon_device *rdev)
1294 {
1295 /* set up the default clocks if the MC ucode is loaded */
1296 if ((rdev->family >= CHIP_BARTS) &&
1297 (rdev->family <= CHIP_CAYMAN) &&
1298 rdev->mc_fw) {
1299 if (rdev->pm.default_vddc)
1300 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1301 SET_VOLTAGE_TYPE_ASIC_VDDC);
1302 if (rdev->pm.default_vddci)
1303 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1304 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1305 if (rdev->pm.default_sclk)
1306 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1307 if (rdev->pm.default_mclk)
1308 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1309 }
1310 /* asic init will reset the default power state */
1311 mutex_lock(&rdev->pm.mutex);
1312 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1313 rdev->pm.current_clock_mode_index = 0;
1314 rdev->pm.current_sclk = rdev->pm.default_sclk;
1315 rdev->pm.current_mclk = rdev->pm.default_mclk;
1316 if (rdev->pm.power_state) {
1317 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1318 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1319 }
1320 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1321 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1322 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1323 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1324 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1325 }
1326 mutex_unlock(&rdev->pm.mutex);
1327 radeon_pm_compute_clocks(rdev);
1328 }
1329
radeon_pm_resume_dpm(struct radeon_device * rdev)1330 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1331 {
1332 int ret;
1333
1334 /* asic init will reset to the boot state */
1335 mutex_lock(&rdev->pm.mutex);
1336 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1337 radeon_dpm_setup_asic(rdev);
1338 ret = radeon_dpm_enable(rdev);
1339 mutex_unlock(&rdev->pm.mutex);
1340 if (ret)
1341 goto dpm_resume_fail;
1342 rdev->pm.dpm_enabled = true;
1343 return;
1344
1345 dpm_resume_fail:
1346 DRM_ERROR("radeon: dpm resume failed\n");
1347 if ((rdev->family >= CHIP_BARTS) &&
1348 (rdev->family <= CHIP_CAYMAN) &&
1349 rdev->mc_fw) {
1350 if (rdev->pm.default_vddc)
1351 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1352 SET_VOLTAGE_TYPE_ASIC_VDDC);
1353 if (rdev->pm.default_vddci)
1354 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1355 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1356 if (rdev->pm.default_sclk)
1357 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1358 if (rdev->pm.default_mclk)
1359 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1360 }
1361 }
1362
radeon_pm_resume(struct radeon_device * rdev)1363 void radeon_pm_resume(struct radeon_device *rdev)
1364 {
1365 if (rdev->pm.pm_method == PM_METHOD_DPM)
1366 radeon_pm_resume_dpm(rdev);
1367 else
1368 radeon_pm_resume_old(rdev);
1369 }
1370
radeon_pm_init_old(struct radeon_device * rdev)1371 static int radeon_pm_init_old(struct radeon_device *rdev)
1372 {
1373 int ret;
1374
1375 rdev->pm.profile = PM_PROFILE_DEFAULT;
1376 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1377 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1378 rdev->pm.dynpm_can_upclock = true;
1379 rdev->pm.dynpm_can_downclock = true;
1380 rdev->pm.default_sclk = rdev->clock.default_sclk;
1381 rdev->pm.default_mclk = rdev->clock.default_mclk;
1382 rdev->pm.current_sclk = rdev->clock.default_sclk;
1383 rdev->pm.current_mclk = rdev->clock.default_mclk;
1384 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1385
1386 if (rdev->bios) {
1387 if (rdev->is_atom_bios)
1388 radeon_atombios_get_power_modes(rdev);
1389 else
1390 radeon_combios_get_power_modes(rdev);
1391 radeon_pm_print_states(rdev);
1392 radeon_pm_init_profile(rdev);
1393 /* set up the default clocks if the MC ucode is loaded */
1394 if ((rdev->family >= CHIP_BARTS) &&
1395 (rdev->family <= CHIP_CAYMAN) &&
1396 rdev->mc_fw) {
1397 if (rdev->pm.default_vddc)
1398 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1399 SET_VOLTAGE_TYPE_ASIC_VDDC);
1400 if (rdev->pm.default_vddci)
1401 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1402 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1403 if (rdev->pm.default_sclk)
1404 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1405 if (rdev->pm.default_mclk)
1406 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1407 }
1408 }
1409
1410 /* set up the internal thermal sensor if applicable */
1411 ret = radeon_hwmon_init(rdev);
1412 if (ret)
1413 return ret;
1414
1415 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1416
1417 if (rdev->pm.num_power_states > 1) {
1418 radeon_debugfs_pm_init(rdev);
1419 DRM_INFO("radeon: power management initialized\n");
1420 }
1421
1422 return 0;
1423 }
1424
radeon_dpm_print_power_states(struct radeon_device * rdev)1425 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1426 {
1427 int i;
1428
1429 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1430 printk("== power state %d ==\n", i);
1431 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1432 }
1433 }
1434
radeon_pm_init_dpm(struct radeon_device * rdev)1435 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1436 {
1437 int ret;
1438
1439 /* default to balanced state */
1440 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1441 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1442 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1443 rdev->pm.default_sclk = rdev->clock.default_sclk;
1444 rdev->pm.default_mclk = rdev->clock.default_mclk;
1445 rdev->pm.current_sclk = rdev->clock.default_sclk;
1446 rdev->pm.current_mclk = rdev->clock.default_mclk;
1447 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1448
1449 if (rdev->bios && rdev->is_atom_bios)
1450 radeon_atombios_get_power_modes(rdev);
1451 else
1452 return -EINVAL;
1453
1454 /* set up the internal thermal sensor if applicable */
1455 ret = radeon_hwmon_init(rdev);
1456 if (ret)
1457 return ret;
1458
1459 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1460 mutex_lock(&rdev->pm.mutex);
1461 radeon_dpm_init(rdev);
1462 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1463 if (radeon_dpm == 1)
1464 radeon_dpm_print_power_states(rdev);
1465 radeon_dpm_setup_asic(rdev);
1466 ret = radeon_dpm_enable(rdev);
1467 mutex_unlock(&rdev->pm.mutex);
1468 if (ret)
1469 goto dpm_failed;
1470 rdev->pm.dpm_enabled = true;
1471
1472 radeon_debugfs_pm_init(rdev);
1473
1474 DRM_INFO("radeon: dpm initialized\n");
1475
1476 return 0;
1477
1478 dpm_failed:
1479 rdev->pm.dpm_enabled = false;
1480 if ((rdev->family >= CHIP_BARTS) &&
1481 (rdev->family <= CHIP_CAYMAN) &&
1482 rdev->mc_fw) {
1483 if (rdev->pm.default_vddc)
1484 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1485 SET_VOLTAGE_TYPE_ASIC_VDDC);
1486 if (rdev->pm.default_vddci)
1487 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1488 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1489 if (rdev->pm.default_sclk)
1490 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1491 if (rdev->pm.default_mclk)
1492 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1493 }
1494 DRM_ERROR("radeon: dpm initialization failed\n");
1495 return ret;
1496 }
1497
1498 struct radeon_dpm_quirk {
1499 u32 chip_vendor;
1500 u32 chip_device;
1501 u32 subsys_vendor;
1502 u32 subsys_device;
1503 };
1504
1505 /* cards with dpm stability problems */
1506 static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = {
1507 /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */
1508 { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 },
1509 /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */
1510 { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 },
1511 { 0, 0, 0, 0 },
1512 };
1513
radeon_pm_init(struct radeon_device * rdev)1514 int radeon_pm_init(struct radeon_device *rdev)
1515 {
1516 struct radeon_dpm_quirk *p = radeon_dpm_quirk_list;
1517 bool disable_dpm = false;
1518
1519 /* Apply dpm quirks */
1520 while (p && p->chip_device != 0) {
1521 if (rdev->pdev->vendor == p->chip_vendor &&
1522 rdev->pdev->device == p->chip_device &&
1523 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
1524 rdev->pdev->subsystem_device == p->subsys_device) {
1525 disable_dpm = true;
1526 break;
1527 }
1528 ++p;
1529 }
1530
1531 /* enable dpm on rv6xx+ */
1532 switch (rdev->family) {
1533 case CHIP_RV610:
1534 case CHIP_RV630:
1535 case CHIP_RV620:
1536 case CHIP_RV635:
1537 case CHIP_RV670:
1538 case CHIP_RS780:
1539 case CHIP_RS880:
1540 case CHIP_RV770:
1541 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1542 if (!rdev->rlc_fw)
1543 rdev->pm.pm_method = PM_METHOD_PROFILE;
1544 else if ((rdev->family >= CHIP_RV770) &&
1545 (!(rdev->flags & RADEON_IS_IGP)) &&
1546 (!rdev->smc_fw))
1547 rdev->pm.pm_method = PM_METHOD_PROFILE;
1548 else if (radeon_dpm == 1)
1549 rdev->pm.pm_method = PM_METHOD_DPM;
1550 else
1551 rdev->pm.pm_method = PM_METHOD_PROFILE;
1552 break;
1553 case CHIP_RV730:
1554 case CHIP_RV710:
1555 case CHIP_RV740:
1556 case CHIP_CEDAR:
1557 case CHIP_REDWOOD:
1558 case CHIP_JUNIPER:
1559 case CHIP_CYPRESS:
1560 case CHIP_HEMLOCK:
1561 case CHIP_PALM:
1562 case CHIP_SUMO:
1563 case CHIP_SUMO2:
1564 case CHIP_BARTS:
1565 case CHIP_TURKS:
1566 case CHIP_CAICOS:
1567 case CHIP_CAYMAN:
1568 case CHIP_ARUBA:
1569 case CHIP_TAHITI:
1570 case CHIP_PITCAIRN:
1571 case CHIP_VERDE:
1572 case CHIP_OLAND:
1573 case CHIP_HAINAN:
1574 case CHIP_BONAIRE:
1575 case CHIP_KABINI:
1576 case CHIP_KAVERI:
1577 case CHIP_HAWAII:
1578 case CHIP_MULLINS:
1579 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1580 if (!rdev->rlc_fw)
1581 rdev->pm.pm_method = PM_METHOD_PROFILE;
1582 else if ((rdev->family >= CHIP_RV770) &&
1583 (!(rdev->flags & RADEON_IS_IGP)) &&
1584 (!rdev->smc_fw))
1585 rdev->pm.pm_method = PM_METHOD_PROFILE;
1586 else if (disable_dpm && (radeon_dpm == -1))
1587 rdev->pm.pm_method = PM_METHOD_PROFILE;
1588 else if (radeon_dpm == 0)
1589 rdev->pm.pm_method = PM_METHOD_PROFILE;
1590 else
1591 rdev->pm.pm_method = PM_METHOD_DPM;
1592 break;
1593 default:
1594 /* default to profile method */
1595 rdev->pm.pm_method = PM_METHOD_PROFILE;
1596 break;
1597 }
1598
1599 if (rdev->pm.pm_method == PM_METHOD_DPM)
1600 return radeon_pm_init_dpm(rdev);
1601 else
1602 return radeon_pm_init_old(rdev);
1603 }
1604
radeon_pm_late_init(struct radeon_device * rdev)1605 int radeon_pm_late_init(struct radeon_device *rdev)
1606 {
1607 int ret = 0;
1608
1609 if (rdev->pm.pm_method == PM_METHOD_DPM) {
1610 if (rdev->pm.dpm_enabled) {
1611 #ifdef __linux__
1612 if (!rdev->pm.sysfs_initialized) {
1613 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1614 if (ret)
1615 DRM_ERROR("failed to create device file for dpm state\n");
1616 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1617 if (ret)
1618 DRM_ERROR("failed to create device file for dpm state\n");
1619 /* XXX: these are noops for dpm but are here for backwards compat */
1620 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1621 if (ret)
1622 DRM_ERROR("failed to create device file for power profile\n");
1623 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1624 if (ret)
1625 DRM_ERROR("failed to create device file for power method\n");
1626 rdev->pm.sysfs_initialized = true;
1627 }
1628 #endif
1629
1630 mutex_lock(&rdev->pm.mutex);
1631 ret = radeon_dpm_late_enable(rdev);
1632 mutex_unlock(&rdev->pm.mutex);
1633 if (ret) {
1634 rdev->pm.dpm_enabled = false;
1635 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1636 } else {
1637 /* set the dpm state for PX since there won't be
1638 * a modeset to call this.
1639 */
1640 radeon_pm_compute_clocks(rdev);
1641 }
1642 }
1643 } else {
1644 #ifdef __linux__
1645 if ((rdev->pm.num_power_states > 1) &&
1646 (!rdev->pm.sysfs_initialized)) {
1647 /* where's the best place to put these? */
1648 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1649 if (ret)
1650 DRM_ERROR("failed to create device file for power profile\n");
1651 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1652 if (ret)
1653 DRM_ERROR("failed to create device file for power method\n");
1654 else
1655 rdev->pm.sysfs_initialized = true;
1656 }
1657 #endif
1658 }
1659 return ret;
1660 }
1661
radeon_pm_fini_old(struct radeon_device * rdev)1662 static void radeon_pm_fini_old(struct radeon_device *rdev)
1663 {
1664 if (rdev->pm.num_power_states > 1) {
1665 mutex_lock(&rdev->pm.mutex);
1666 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1667 rdev->pm.profile = PM_PROFILE_DEFAULT;
1668 radeon_pm_update_profile(rdev);
1669 radeon_pm_set_clocks(rdev);
1670 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1671 /* reset default clocks */
1672 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1673 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1674 radeon_pm_set_clocks(rdev);
1675 }
1676 mutex_unlock(&rdev->pm.mutex);
1677
1678 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1679
1680 device_remove_file(rdev->dev, &dev_attr_power_profile);
1681 device_remove_file(rdev->dev, &dev_attr_power_method);
1682 }
1683
1684 radeon_hwmon_fini(rdev);
1685 kfree(rdev->pm.power_state);
1686 }
1687
radeon_pm_fini_dpm(struct radeon_device * rdev)1688 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1689 {
1690 if (rdev->pm.num_power_states > 1) {
1691 mutex_lock(&rdev->pm.mutex);
1692 radeon_dpm_disable(rdev);
1693 mutex_unlock(&rdev->pm.mutex);
1694
1695 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1696 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1697 /* XXX backwards compat */
1698 device_remove_file(rdev->dev, &dev_attr_power_profile);
1699 device_remove_file(rdev->dev, &dev_attr_power_method);
1700 }
1701 radeon_dpm_fini(rdev);
1702
1703 radeon_hwmon_fini(rdev);
1704 kfree(rdev->pm.power_state);
1705 }
1706
radeon_pm_fini(struct radeon_device * rdev)1707 void radeon_pm_fini(struct radeon_device *rdev)
1708 {
1709 if (rdev->pm.pm_method == PM_METHOD_DPM)
1710 radeon_pm_fini_dpm(rdev);
1711 else
1712 radeon_pm_fini_old(rdev);
1713 }
1714
radeon_pm_compute_clocks_old(struct radeon_device * rdev)1715 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1716 {
1717 struct drm_device *ddev = rdev_to_drm(rdev);
1718 struct drm_crtc *crtc;
1719 struct radeon_crtc *radeon_crtc;
1720
1721 if (rdev->pm.num_power_states < 2)
1722 return;
1723
1724 mutex_lock(&rdev->pm.mutex);
1725
1726 rdev->pm.active_crtcs = 0;
1727 rdev->pm.active_crtc_count = 0;
1728 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1729 list_for_each_entry(crtc,
1730 &ddev->mode_config.crtc_list, head) {
1731 radeon_crtc = to_radeon_crtc(crtc);
1732 if (radeon_crtc->enabled) {
1733 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1734 rdev->pm.active_crtc_count++;
1735 }
1736 }
1737 }
1738
1739 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1740 radeon_pm_update_profile(rdev);
1741 radeon_pm_set_clocks(rdev);
1742 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1743 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1744 if (rdev->pm.active_crtc_count > 1) {
1745 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1746 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1747
1748 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1749 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1750 radeon_pm_get_dynpm_state(rdev);
1751 radeon_pm_set_clocks(rdev);
1752
1753 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1754 }
1755 } else if (rdev->pm.active_crtc_count == 1) {
1756 /* TODO: Increase clocks if needed for current mode */
1757
1758 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1759 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1760 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1761 radeon_pm_get_dynpm_state(rdev);
1762 radeon_pm_set_clocks(rdev);
1763
1764 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1765 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1766 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1767 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1768 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1769 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1770 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1771 }
1772 } else { /* count == 0 */
1773 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1774 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1775
1776 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1777 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1778 radeon_pm_get_dynpm_state(rdev);
1779 radeon_pm_set_clocks(rdev);
1780 }
1781 }
1782 }
1783 }
1784
1785 mutex_unlock(&rdev->pm.mutex);
1786 }
1787
radeon_pm_compute_clocks_dpm(struct radeon_device * rdev)1788 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1789 {
1790 struct drm_device *ddev = rdev_to_drm(rdev);
1791 struct drm_crtc *crtc;
1792 struct radeon_crtc *radeon_crtc;
1793 struct radeon_connector *radeon_connector;
1794
1795 if (!rdev->pm.dpm_enabled)
1796 return;
1797
1798 mutex_lock(&rdev->pm.mutex);
1799
1800 /* update active crtc counts */
1801 rdev->pm.dpm.new_active_crtcs = 0;
1802 rdev->pm.dpm.new_active_crtc_count = 0;
1803 rdev->pm.dpm.high_pixelclock_count = 0;
1804 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1805 list_for_each_entry(crtc,
1806 &ddev->mode_config.crtc_list, head) {
1807 radeon_crtc = to_radeon_crtc(crtc);
1808 if (crtc->enabled) {
1809 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1810 rdev->pm.dpm.new_active_crtc_count++;
1811 if (!radeon_crtc->connector)
1812 continue;
1813
1814 radeon_connector = to_radeon_connector(radeon_crtc->connector);
1815 if (radeon_connector->pixelclock_for_modeset > 297000)
1816 rdev->pm.dpm.high_pixelclock_count++;
1817 }
1818 }
1819 }
1820
1821 /* update battery/ac status */
1822 if (power_supply_is_system_supplied() > 0)
1823 rdev->pm.dpm.ac_power = true;
1824 else
1825 rdev->pm.dpm.ac_power = false;
1826
1827 radeon_dpm_change_power_state_locked(rdev);
1828
1829 mutex_unlock(&rdev->pm.mutex);
1830
1831 }
1832
radeon_pm_compute_clocks(struct radeon_device * rdev)1833 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1834 {
1835 if (rdev->pm.pm_method == PM_METHOD_DPM)
1836 radeon_pm_compute_clocks_dpm(rdev);
1837 else
1838 radeon_pm_compute_clocks_old(rdev);
1839 }
1840
radeon_pm_in_vbl(struct radeon_device * rdev)1841 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1842 {
1843 int crtc, vpos, hpos, vbl_status;
1844 bool in_vbl = true;
1845
1846 /* Iterate over all active crtc's. All crtc's must be in vblank,
1847 * otherwise return in_vbl == false.
1848 */
1849 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1850 if (rdev->pm.active_crtcs & (1 << crtc)) {
1851 vbl_status = radeon_get_crtc_scanoutpos(rdev_to_drm(rdev),
1852 crtc,
1853 USE_REAL_VBLANKSTART,
1854 &vpos, &hpos, NULL, NULL,
1855 &rdev->mode_info.crtcs[crtc]->base.hwmode);
1856 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1857 !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK))
1858 in_vbl = false;
1859 }
1860 }
1861
1862 return in_vbl;
1863 }
1864
radeon_pm_debug_check_in_vbl(struct radeon_device * rdev,bool finish)1865 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1866 {
1867 u32 stat_crtc = 0;
1868 bool in_vbl = radeon_pm_in_vbl(rdev);
1869
1870 if (!in_vbl)
1871 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1872 finish ? "exit" : "entry");
1873 return in_vbl;
1874 }
1875
radeon_dynpm_idle_work_handler(struct work_struct * work)1876 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1877 {
1878 struct radeon_device *rdev;
1879
1880 rdev = container_of(work, struct radeon_device,
1881 pm.dynpm_idle_work.work);
1882
1883 mutex_lock(&rdev->pm.mutex);
1884 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1885 int not_processed = 0;
1886 int i;
1887
1888 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1889 struct radeon_ring *ring = &rdev->ring[i];
1890
1891 if (ring->ready) {
1892 not_processed += radeon_fence_count_emitted(rdev, i);
1893 if (not_processed >= 3)
1894 break;
1895 }
1896 }
1897
1898 if (not_processed >= 3) { /* should upclock */
1899 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1900 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1901 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1902 rdev->pm.dynpm_can_upclock) {
1903 rdev->pm.dynpm_planned_action =
1904 DYNPM_ACTION_UPCLOCK;
1905 rdev->pm.dynpm_action_timeout = jiffies +
1906 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1907 }
1908 } else if (not_processed == 0) { /* should downclock */
1909 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1910 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1911 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1912 rdev->pm.dynpm_can_downclock) {
1913 rdev->pm.dynpm_planned_action =
1914 DYNPM_ACTION_DOWNCLOCK;
1915 rdev->pm.dynpm_action_timeout = jiffies +
1916 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1917 }
1918 }
1919
1920 /* Note, radeon_pm_set_clocks is called with static_switch set
1921 * to false since we want to wait for vbl to avoid flicker.
1922 */
1923 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1924 time_after(jiffies, rdev->pm.dynpm_action_timeout)) {
1925 radeon_pm_get_dynpm_state(rdev);
1926 radeon_pm_set_clocks(rdev);
1927 }
1928
1929 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1930 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1931 }
1932 mutex_unlock(&rdev->pm.mutex);
1933 }
1934
1935 /*
1936 * Debugfs info
1937 */
1938 #if defined(CONFIG_DEBUG_FS)
1939
radeon_debugfs_pm_info_show(struct seq_file * m,void * unused)1940 static int radeon_debugfs_pm_info_show(struct seq_file *m, void *unused)
1941 {
1942 struct radeon_device *rdev = m->private;
1943 struct drm_device *ddev = rdev_to_drm(rdev);
1944
1945 if ((rdev->flags & RADEON_IS_PX) &&
1946 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1947 seq_printf(m, "PX asic powered off\n");
1948 } else if (rdev->pm.dpm_enabled) {
1949 mutex_lock(&rdev->pm.mutex);
1950 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1951 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1952 else
1953 seq_printf(m, "Debugfs support not implemented for this asic\n");
1954 mutex_unlock(&rdev->pm.mutex);
1955 } else {
1956 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1957 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1958 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1959 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1960 else
1961 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1962 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1963 if (rdev->asic->pm.get_memory_clock)
1964 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1965 if (rdev->pm.current_vddc)
1966 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1967 if (rdev->asic->pm.get_pcie_lanes)
1968 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1969 }
1970
1971 return 0;
1972 }
1973
1974 DEFINE_SHOW_ATTRIBUTE(radeon_debugfs_pm_info);
1975 #endif
1976
radeon_debugfs_pm_init(struct radeon_device * rdev)1977 static void radeon_debugfs_pm_init(struct radeon_device *rdev)
1978 {
1979 #if defined(CONFIG_DEBUG_FS)
1980 struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root;
1981
1982 debugfs_create_file("radeon_pm_info", 0444, root, rdev,
1983 &radeon_debugfs_pm_info_fops);
1984
1985 #endif
1986 }
1987