1 /*
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8 /*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32
33 #include <linux/compat.h>
34 #include <linux/module.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/vga_switcheroo.h>
37 #include <linux/mmu_notifier.h>
38 #include <linux/pci.h>
39
40 #include <drm/drm_aperture.h>
41 #include <drm/drm_drv.h>
42 #include <drm/drm_file.h>
43 #include <drm/drm_gem.h>
44 #include <drm/drm_ioctl.h>
45 #include <drm/drm_pciids.h>
46 #include <drm/drm_probe_helper.h>
47 #include <drm/drm_vblank.h>
48 #include <drm/radeon_drm.h>
49
50 #include "radeon_drv.h"
51 #include "radeon.h"
52 #include "radeon_kms.h"
53 #include "radeon_ttm.h"
54 #include "radeon_device.h"
55 #include "radeon_prime.h"
56
57 /*
58 * KMS wrapper.
59 * - 2.0.0 - initial interface
60 * - 2.1.0 - add square tiling interface
61 * - 2.2.0 - add r6xx/r7xx const buffer support
62 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
63 * - 2.4.0 - add crtc id query
64 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
65 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
66 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
67 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
68 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
69 * 2.10.0 - fusion 2D tiling
70 * 2.11.0 - backend map, initial compute support for the CS checker
71 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
72 * 2.13.0 - virtual memory support, streamout
73 * 2.14.0 - add evergreen tiling informations
74 * 2.15.0 - add max_pipes query
75 * 2.16.0 - fix evergreen 2D tiled surface calculation
76 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
77 * 2.18.0 - r600-eg: allow "invalid" DB formats
78 * 2.19.0 - r600-eg: MSAA textures
79 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
80 * 2.21.0 - r600-r700: FMASK and CMASK
81 * 2.22.0 - r600 only: RESOLVE_BOX allowed
82 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
83 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
84 * 2.25.0 - eg+: new info request for num SE and num SH
85 * 2.26.0 - r600-eg: fix htile size computation
86 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
87 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
88 * 2.29.0 - R500 FP16 color clear registers
89 * 2.30.0 - fix for FMASK texturing
90 * 2.31.0 - Add fastfb support for rs690
91 * 2.32.0 - new info request for rings working
92 * 2.33.0 - Add SI tiling mode array query
93 * 2.34.0 - Add CIK tiling mode array query
94 * 2.35.0 - Add CIK macrotile mode array query
95 * 2.36.0 - Fix CIK DCE tiling setup
96 * 2.37.0 - allow GS ring setup on r6xx/r7xx
97 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
98 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
99 * 2.39.0 - Add INFO query for number of active CUs
100 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
101 * CS to GPU on >= r600
102 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
103 * 2.42.0 - Add VCE/VUI (Video Usability Information) support
104 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
105 * 2.44.0 - SET_APPEND_CNT packet3 support
106 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
107 * 2.46.0 - Add PFP_SYNC_ME support on evergreen
108 * 2.47.0 - Add UVD_NO_OP register support
109 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
110 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values
111 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL)
112 */
113 #define KMS_DRIVER_MAJOR 2
114 #define KMS_DRIVER_MINOR 50
115 #define KMS_DRIVER_PATCHLEVEL 0
116
117 int radeon_no_wb;
118 int radeon_modeset = -1;
119 int radeon_dynclks = -1;
120 int radeon_r4xx_atom;
121 int radeon_agpmode = -1;
122 int radeon_vram_limit;
123 int radeon_gart_size = -1; /* auto */
124 int radeon_benchmarking;
125 int radeon_testing;
126 int radeon_connector_table;
127 int radeon_tv = 1;
128 int radeon_audio = -1;
129 int radeon_disp_priority;
130 int radeon_hw_i2c;
131 int radeon_pcie_gen2 = -1;
132 int radeon_msi = -1;
133 int radeon_lockup_timeout = 10000;
134 int radeon_fastfb;
135 int radeon_dpm = -1;
136 int radeon_aspm = -1;
137 int radeon_runtime_pm = -1;
138 int radeon_hard_reset;
139 int radeon_vm_size = 8;
140 int radeon_vm_block_size = -1;
141 int radeon_deep_color;
142 int radeon_use_pflipirq = 2;
143 int radeon_bapm = -1;
144 int radeon_backlight = -1;
145 int radeon_auxch = -1;
146 int radeon_uvd = 1;
147 int radeon_vce = 1;
148
149 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
150 module_param_named(no_wb, radeon_no_wb, int, 0444);
151
152 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
153 module_param_named(modeset, radeon_modeset, int, 0400);
154
155 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
156 module_param_named(dynclks, radeon_dynclks, int, 0444);
157
158 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
159 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
160
161 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
162 module_param_named(vramlimit, radeon_vram_limit, int, 0600);
163
164 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
165 module_param_named(agpmode, radeon_agpmode, int, 0444);
166
167 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
168 module_param_named(gartsize, radeon_gart_size, int, 0600);
169
170 MODULE_PARM_DESC(benchmark, "Run benchmark");
171 module_param_named(benchmark, radeon_benchmarking, int, 0444);
172
173 MODULE_PARM_DESC(test, "Run tests");
174 module_param_named(test, radeon_testing, int, 0444);
175
176 MODULE_PARM_DESC(connector_table, "Force connector table");
177 module_param_named(connector_table, radeon_connector_table, int, 0444);
178
179 MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
180 module_param_named(tv, radeon_tv, int, 0444);
181
182 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
183 module_param_named(audio, radeon_audio, int, 0444);
184
185 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
186 module_param_named(disp_priority, radeon_disp_priority, int, 0444);
187
188 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
189 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
190
191 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
192 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
193
194 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
195 module_param_named(msi, radeon_msi, int, 0444);
196
197 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
198 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
199
200 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
201 module_param_named(fastfb, radeon_fastfb, int, 0444);
202
203 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
204 module_param_named(dpm, radeon_dpm, int, 0444);
205
206 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
207 module_param_named(aspm, radeon_aspm, int, 0444);
208
209 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
210 module_param_named(runpm, radeon_runtime_pm, int, 0444);
211
212 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
213 module_param_named(hard_reset, radeon_hard_reset, int, 0444);
214
215 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
216 module_param_named(vm_size, radeon_vm_size, int, 0444);
217
218 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
219 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
220
221 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
222 module_param_named(deep_color, radeon_deep_color, int, 0444);
223
224 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
225 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
226
227 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
228 module_param_named(bapm, radeon_bapm, int, 0444);
229
230 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
231 module_param_named(backlight, radeon_backlight, int, 0444);
232
233 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
234 module_param_named(auxch, radeon_auxch, int, 0444);
235
236 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
237 module_param_named(uvd, radeon_uvd, int, 0444);
238
239 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
240 module_param_named(vce, radeon_vce, int, 0444);
241
242 int radeon_si_support = 1;
243 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
244 module_param_named(si_support, radeon_si_support, int, 0444);
245
246 int radeon_cik_support = 1;
247 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
248 module_param_named(cik_support, radeon_cik_support, int, 0444);
249
250 static const struct pci_device_id pciidlist[] = {
251 radeon_PCI_IDS
252 };
253
254 MODULE_DEVICE_TABLE(pci, pciidlist);
255
256 static const struct drm_driver kms_driver;
257
258 #ifdef __linux__
radeon_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)259 static int radeon_pci_probe(struct pci_dev *pdev,
260 const struct pci_device_id *ent)
261 {
262 unsigned long flags = 0;
263 struct drm_device *ddev;
264 struct radeon_device *rdev;
265 int ret;
266
267 if (!ent)
268 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */
269
270 flags = ent->driver_data;
271
272 if (!radeon_si_support) {
273 switch (flags & RADEON_FAMILY_MASK) {
274 case CHIP_TAHITI:
275 case CHIP_PITCAIRN:
276 case CHIP_VERDE:
277 case CHIP_OLAND:
278 case CHIP_HAINAN:
279 dev_info(&pdev->dev,
280 "SI support disabled by module param\n");
281 return -ENODEV;
282 }
283 }
284 if (!radeon_cik_support) {
285 switch (flags & RADEON_FAMILY_MASK) {
286 case CHIP_KAVERI:
287 case CHIP_BONAIRE:
288 case CHIP_HAWAII:
289 case CHIP_KABINI:
290 case CHIP_MULLINS:
291 dev_info(&pdev->dev,
292 "CIK support disabled by module param\n");
293 return -ENODEV;
294 }
295 }
296
297 if (vga_switcheroo_client_probe_defer(pdev))
298 return -EPROBE_DEFER;
299
300 /* Get rid of things like offb */
301 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &kms_driver);
302 if (ret)
303 return ret;
304
305 rdev = devm_drm_dev_alloc(&pdev->dev, &kms_driver, typeof(*rdev), ddev);
306 if (IS_ERR(rdev))
307 return PTR_ERR(rdev);
308
309 rdev->dev = &pdev->dev;
310 rdev->pdev = pdev;
311 ddev = rdev_to_drm(rdev);
312 ddev->dev_private = rdev;
313
314 ret = pci_enable_device(pdev);
315 if (ret)
316 goto err_free;
317
318 pci_set_drvdata(pdev, ddev);
319
320 ret = radeon_driver_load_kms(ddev, flags);
321 if (ret)
322 goto err_agp;
323
324 ret = drm_dev_register(ddev, flags);
325 if (ret)
326 goto err_agp;
327
328 radeon_fbdev_setup(ddev->dev_private);
329
330 return 0;
331
332 err_agp:
333 pci_disable_device(pdev);
334 err_free:
335 drm_dev_put(ddev);
336 return ret;
337 }
338
339 static void
radeon_pci_remove(struct pci_dev * pdev)340 radeon_pci_remove(struct pci_dev *pdev)
341 {
342 struct drm_device *dev = pci_get_drvdata(pdev);
343
344 drm_put_dev(dev);
345 }
346
347 static void
radeon_pci_shutdown(struct pci_dev * pdev)348 radeon_pci_shutdown(struct pci_dev *pdev)
349 {
350 /* if we are running in a VM, make sure the device
351 * torn down properly on reboot/shutdown
352 */
353 if (radeon_device_is_virtual())
354 radeon_pci_remove(pdev);
355
356 #if defined(CONFIG_PPC64) || defined(CONFIG_MACH_LOONGSON64)
357 /*
358 * Some adapters need to be suspended before a
359 * shutdown occurs in order to prevent an error
360 * during kexec, shutdown or reboot.
361 * Make this power and Loongson specific because
362 * it breaks some other boards.
363 */
364 radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false);
365 #endif
366 }
367
radeon_pmops_suspend(struct device * dev)368 static int radeon_pmops_suspend(struct device *dev)
369 {
370 struct drm_device *drm_dev = dev_get_drvdata(dev);
371
372 return radeon_suspend_kms(drm_dev, true, true, false);
373 }
374
radeon_pmops_resume(struct device * dev)375 static int radeon_pmops_resume(struct device *dev)
376 {
377 struct drm_device *drm_dev = dev_get_drvdata(dev);
378
379 /* GPU comes up enabled by the bios on resume */
380 if (radeon_is_px(drm_dev)) {
381 pm_runtime_disable(dev);
382 pm_runtime_set_active(dev);
383 pm_runtime_enable(dev);
384 }
385
386 return radeon_resume_kms(drm_dev, true, true);
387 }
388
radeon_pmops_freeze(struct device * dev)389 static int radeon_pmops_freeze(struct device *dev)
390 {
391 struct drm_device *drm_dev = dev_get_drvdata(dev);
392
393 return radeon_suspend_kms(drm_dev, false, true, true);
394 }
395
radeon_pmops_thaw(struct device * dev)396 static int radeon_pmops_thaw(struct device *dev)
397 {
398 struct drm_device *drm_dev = dev_get_drvdata(dev);
399
400 return radeon_resume_kms(drm_dev, false, true);
401 }
402
radeon_pmops_runtime_suspend(struct device * dev)403 static int radeon_pmops_runtime_suspend(struct device *dev)
404 {
405 struct pci_dev *pdev = to_pci_dev(dev);
406 struct drm_device *drm_dev = pci_get_drvdata(pdev);
407
408 if (!radeon_is_px(drm_dev)) {
409 pm_runtime_forbid(dev);
410 return -EBUSY;
411 }
412
413 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
414 drm_kms_helper_poll_disable(drm_dev);
415
416 radeon_suspend_kms(drm_dev, false, false, false);
417 pci_save_state(pdev);
418 pci_disable_device(pdev);
419 pci_ignore_hotplug(pdev);
420 if (radeon_is_atpx_hybrid())
421 pci_set_power_state(pdev, PCI_D3cold);
422 else if (!radeon_has_atpx_dgpu_power_cntl())
423 pci_set_power_state(pdev, PCI_D3hot);
424 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
425
426 return 0;
427 }
428
radeon_pmops_runtime_resume(struct device * dev)429 static int radeon_pmops_runtime_resume(struct device *dev)
430 {
431 struct pci_dev *pdev = to_pci_dev(dev);
432 struct drm_device *drm_dev = pci_get_drvdata(pdev);
433 int ret;
434
435 if (!radeon_is_px(drm_dev))
436 return -EINVAL;
437
438 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
439
440 if (radeon_is_atpx_hybrid() ||
441 !radeon_has_atpx_dgpu_power_cntl())
442 pci_set_power_state(pdev, PCI_D0);
443 pci_restore_state(pdev);
444 ret = pci_enable_device(pdev);
445 if (ret)
446 return ret;
447 pci_set_master(pdev);
448
449 ret = radeon_resume_kms(drm_dev, false, false);
450 drm_kms_helper_poll_enable(drm_dev);
451 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
452 return 0;
453 }
454
radeon_pmops_runtime_idle(struct device * dev)455 static int radeon_pmops_runtime_idle(struct device *dev)
456 {
457 struct drm_device *drm_dev = dev_get_drvdata(dev);
458 struct drm_crtc *crtc;
459
460 if (!radeon_is_px(drm_dev)) {
461 pm_runtime_forbid(dev);
462 return -EBUSY;
463 }
464
465 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
466 if (crtc->enabled) {
467 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
468 return -EBUSY;
469 }
470 }
471
472 pm_runtime_mark_last_busy(dev);
473 pm_runtime_autosuspend(dev);
474 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
475 return 1;
476 }
477
radeon_drm_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)478 long radeon_drm_ioctl(struct file *filp,
479 unsigned int cmd, unsigned long arg)
480 {
481 struct drm_file *file_priv = filp->private_data;
482 struct drm_device *dev;
483 long ret;
484
485 dev = file_priv->minor->dev;
486 ret = pm_runtime_get_sync(dev->dev);
487 if (ret < 0) {
488 pm_runtime_put_autosuspend(dev->dev);
489 return ret;
490 }
491
492 ret = drm_ioctl(filp, cmd, arg);
493
494 pm_runtime_mark_last_busy(dev->dev);
495 pm_runtime_put_autosuspend(dev->dev);
496 return ret;
497 }
498
499 #ifdef CONFIG_COMPAT
radeon_kms_compat_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)500 static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
501 {
502 unsigned int nr = DRM_IOCTL_NR(cmd);
503
504 if (nr < DRM_COMMAND_BASE)
505 return drm_compat_ioctl(filp, cmd, arg);
506
507 return radeon_drm_ioctl(filp, cmd, arg);
508 }
509 #endif
510
511 static const struct dev_pm_ops radeon_pm_ops = {
512 .suspend = radeon_pmops_suspend,
513 .resume = radeon_pmops_resume,
514 .freeze = radeon_pmops_freeze,
515 .thaw = radeon_pmops_thaw,
516 .poweroff = radeon_pmops_freeze,
517 .restore = radeon_pmops_resume,
518 .runtime_suspend = radeon_pmops_runtime_suspend,
519 .runtime_resume = radeon_pmops_runtime_resume,
520 .runtime_idle = radeon_pmops_runtime_idle,
521 };
522
523 static const struct file_operations radeon_driver_kms_fops = {
524 .owner = THIS_MODULE,
525 .open = drm_open,
526 .release = drm_release,
527 .unlocked_ioctl = radeon_drm_ioctl,
528 .mmap = drm_gem_mmap,
529 .poll = drm_poll,
530 .read = drm_read,
531 #ifdef CONFIG_COMPAT
532 .compat_ioctl = radeon_kms_compat_ioctl,
533 #endif
534 .fop_flags = FOP_UNSIGNED_OFFSET,
535 };
536
537 #endif /* __linux__ */
538
539 static const struct drm_ioctl_desc radeon_ioctls_kms[] = {
540 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
541 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
542 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
543 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
544 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
545 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
546 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
547 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
548 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
549 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
550 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
551 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
552 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
553 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
554 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
555 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
556 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
557 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
558 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
559 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
560 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
561 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
562 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
563 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
564 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
565 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
566 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
567 /* KMS */
568 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
569 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
570 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
571 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
572 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
573 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
574 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
575 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
576 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
577 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
578 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
579 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
580 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
581 };
582
583 static const struct drm_driver kms_driver = {
584 .driver_features =
585 DRIVER_GEM | DRIVER_RENDER | DRIVER_MODESET,
586 .open = radeon_driver_open_kms,
587 #ifdef __OpenBSD__
588 .mmap = drm_gem_mmap,
589 .gem_size = sizeof(struct radeon_bo),
590 #endif
591 .postclose = radeon_driver_postclose_kms,
592 #ifdef notyet
593 .unload = radeon_driver_unload_kms,
594 #endif
595 .ioctls = radeon_ioctls_kms,
596 .num_ioctls = ARRAY_SIZE(radeon_ioctls_kms),
597 .dumb_create = radeon_mode_dumb_create,
598 .dumb_map_offset = radeon_mode_dumb_mmap,
599 #ifdef __linux__
600 .fops = &radeon_driver_kms_fops,
601
602 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
603 #endif
604
605 .name = DRIVER_NAME,
606 .desc = DRIVER_DESC,
607 .date = DRIVER_DATE,
608 .major = KMS_DRIVER_MAJOR,
609 .minor = KMS_DRIVER_MINOR,
610 .patchlevel = KMS_DRIVER_PATCHLEVEL,
611 };
612
613 #ifdef __linux__
614 static struct pci_driver radeon_kms_pci_driver = {
615 .name = DRIVER_NAME,
616 .id_table = pciidlist,
617 .probe = radeon_pci_probe,
618 .remove = radeon_pci_remove,
619 .shutdown = radeon_pci_shutdown,
620 .driver.pm = &radeon_pm_ops,
621 };
622 #endif
623
624 #ifdef notyet
radeon_module_init(void)625 static int __init radeon_module_init(void)
626 {
627 if (drm_firmware_drivers_only() && radeon_modeset == -1)
628 radeon_modeset = 0;
629
630 if (radeon_modeset == 0)
631 return -EINVAL;
632
633 DRM_INFO("radeon kernel modesetting enabled.\n");
634 radeon_register_atpx_handler();
635
636 return pci_register_driver(&radeon_kms_pci_driver);
637 }
638
radeon_module_exit(void)639 static void __exit radeon_module_exit(void)
640 {
641 pci_unregister_driver(&radeon_kms_pci_driver);
642 radeon_unregister_atpx_handler();
643 mmu_notifier_synchronize();
644 }
645 #endif /* notyet */
646
647 module_init(radeon_module_init);
648 module_exit(radeon_module_exit);
649
650 MODULE_AUTHOR(DRIVER_AUTHOR);
651 MODULE_DESCRIPTION(DRIVER_DESC);
652 MODULE_LICENSE("GPL and additional rights");
653
654 #if defined(CONFIG_VGA_SWITCHEROO)
655 bool radeon_has_atpx(void);
656 #else
radeon_has_atpx(void)657 static inline bool radeon_has_atpx(void) { return false; }
658 #endif
659
660 #include <drm/drm_drv.h>
661 #include <drm/drm_fb_helper.h>
662 #include "vga.h"
663
664 #if NVGA > 0
665 #include <dev/ic/mc6845reg.h>
666 #include <dev/ic/pcdisplayvar.h>
667 #include <dev/ic/vgareg.h>
668 #include <dev/ic/vgavar.h>
669
670 extern int vga_console_attached;
671 #endif
672
673 #ifdef __amd64__
674 #include "efifb.h"
675 #include <machine/biosvar.h>
676 #endif
677
678 #if NEFIFB > 0
679 #include <machine/efifbvar.h>
680 #endif
681
682 int radeondrm_probe(struct device *, void *, void *);
683 void radeondrm_attach_kms(struct device *, struct device *, void *);
684 int radeondrm_detach_kms(struct device *, int);
685 int radeondrm_activate_kms(struct device *, int);
686 void radeondrm_attachhook(struct device *);
687 int radeondrm_forcedetach(struct radeon_device *);
688
689 bool radeon_msi_ok(struct radeon_device *);
690 irqreturn_t radeon_driver_irq_handler_kms(void *);
691
692 /*
693 * set if the mountroot hook has a fatal error
694 * such as not being able to find the firmware on newer cards
695 */
696 int radeon_fatal_error;
697
698 const struct cfattach radeondrm_ca = {
699 sizeof (struct radeon_device), radeondrm_probe, radeondrm_attach_kms,
700 radeondrm_detach_kms, radeondrm_activate_kms
701 };
702
703 struct cfdriver radeondrm_cd = {
704 NULL, "radeondrm", DV_DULL
705 };
706
707 int
radeondrm_probe(struct device * parent,void * match,void * aux)708 radeondrm_probe(struct device *parent, void *match, void *aux)
709 {
710 if (radeon_fatal_error)
711 return 0;
712 if (drm_pciprobe(aux, pciidlist))
713 return 20;
714 return 0;
715 }
716
717 int
radeondrm_detach_kms(struct device * self,int flags)718 radeondrm_detach_kms(struct device *self, int flags)
719 {
720 struct radeon_device *rdev = (struct radeon_device *)self;
721
722 if (rdev == NULL)
723 return 0;
724
725 pci_intr_disestablish(rdev->pc, rdev->irqh);
726
727 #ifdef notyet
728 pm_runtime_get_sync(dev->dev);
729
730 radeon_kfd_device_fini(rdev);
731 #endif
732
733 radeon_acpi_fini(rdev);
734
735 radeon_modeset_fini(rdev);
736 radeon_device_fini(rdev);
737
738 config_detach(rdev_to_drm(rdev)->dev, flags);
739
740 return 0;
741 }
742
743 void radeondrm_burner(void *, u_int, u_int);
744 int radeondrm_wsioctl(void *, u_long, caddr_t, int, struct proc *);
745 paddr_t radeondrm_wsmmap(void *, off_t, int);
746 int radeondrm_alloc_screen(void *, const struct wsscreen_descr *,
747 void **, int *, int *, uint32_t *);
748 void radeondrm_free_screen(void *, void *);
749 int radeondrm_show_screen(void *, void *, int,
750 void (*)(void *, int, int), void *);
751 void radeondrm_doswitch(void *);
752 void radeondrm_enter_ddb(void *, void *);
753 #ifdef __sparc64__
754 void radeondrm_setcolor(void *, u_int, u_int8_t, u_int8_t, u_int8_t);
755 #endif
756 void radeondrm_setpal(struct radeon_device *, struct rasops_info *);
757
758 struct wsscreen_descr radeondrm_stdscreen = {
759 "std",
760 0, 0,
761 0,
762 0, 0,
763 WSSCREEN_UNDERLINE | WSSCREEN_HILIT |
764 WSSCREEN_REVERSE | WSSCREEN_WSCOLORS
765 };
766
767 const struct wsscreen_descr *radeondrm_scrlist[] = {
768 &radeondrm_stdscreen,
769 };
770
771 struct wsscreen_list radeondrm_screenlist = {
772 nitems(radeondrm_scrlist), radeondrm_scrlist
773 };
774
775 struct wsdisplay_accessops radeondrm_accessops = {
776 .ioctl = radeondrm_wsioctl,
777 .mmap = radeondrm_wsmmap,
778 .alloc_screen = radeondrm_alloc_screen,
779 .free_screen = radeondrm_free_screen,
780 .show_screen = radeondrm_show_screen,
781 .enter_ddb = radeondrm_enter_ddb,
782 .getchar = rasops_getchar,
783 .load_font = rasops_load_font,
784 .list_font = rasops_list_font,
785 .scrollback = rasops_scrollback,
786 .burn_screen = radeondrm_burner
787 };
788
789 int
radeondrm_wsioctl(void * v,u_long cmd,caddr_t data,int flag,struct proc * p)790 radeondrm_wsioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p)
791 {
792 struct rasops_info *ri = v;
793 struct wsdisplay_fbinfo *wdf;
794 struct wsdisplay_param *dp = (struct wsdisplay_param *)data;
795
796 switch (cmd) {
797 case WSDISPLAYIO_GTYPE:
798 *(u_int *)data = WSDISPLAY_TYPE_RADEONDRM;
799 return 0;
800 case WSDISPLAYIO_GINFO:
801 wdf = (struct wsdisplay_fbinfo *)data;
802 wdf->width = ri->ri_width;
803 wdf->height = ri->ri_height;
804 wdf->depth = ri->ri_depth;
805 wdf->stride = ri->ri_stride;
806 wdf->offset = 0;
807 wdf->cmsize = 0;
808 return 0;
809 case WSDISPLAYIO_GETPARAM:
810 if (ws_get_param == NULL)
811 return 0;
812 return ws_get_param(dp);
813 case WSDISPLAYIO_SETPARAM:
814 if (ws_set_param == NULL)
815 return 0;
816 return ws_set_param(dp);
817 case WSDISPLAYIO_SVIDEO:
818 case WSDISPLAYIO_GVIDEO:
819 return 0;
820 default:
821 return -1;
822 }
823 }
824
825 paddr_t
radeondrm_wsmmap(void * v,off_t off,int prot)826 radeondrm_wsmmap(void *v, off_t off, int prot)
827 {
828 return (-1);
829 }
830
831 int
radeondrm_alloc_screen(void * v,const struct wsscreen_descr * type,void ** cookiep,int * curxp,int * curyp,uint32_t * attrp)832 radeondrm_alloc_screen(void *v, const struct wsscreen_descr *type,
833 void **cookiep, int *curxp, int *curyp, uint32_t *attrp)
834 {
835 return rasops_alloc_screen(v, cookiep, curxp, curyp, attrp);
836 }
837
838 void
radeondrm_free_screen(void * v,void * cookie)839 radeondrm_free_screen(void *v, void *cookie)
840 {
841 return rasops_free_screen(v, cookie);
842 }
843
844 int
radeondrm_show_screen(void * v,void * cookie,int waitok,void (* cb)(void *,int,int),void * cbarg)845 radeondrm_show_screen(void *v, void *cookie, int waitok,
846 void (*cb)(void *, int, int), void *cbarg)
847 {
848 struct rasops_info *ri = v;
849 struct radeon_device *rdev = ri->ri_hw;
850
851 if (cookie == ri->ri_active)
852 return (0);
853
854 rdev->switchcb = cb;
855 rdev->switchcbarg = cbarg;
856 rdev->switchcookie = cookie;
857 if (cb) {
858 task_add(systq, &rdev->switchtask);
859 return (EAGAIN);
860 }
861
862 radeondrm_doswitch(v);
863
864 return (0);
865 }
866
867 void
radeondrm_doswitch(void * v)868 radeondrm_doswitch(void *v)
869 {
870 struct rasops_info *ri = v;
871 struct radeon_device *rdev = ri->ri_hw;
872
873 rasops_show_screen(ri, rdev->switchcookie, 0, NULL, NULL);
874 #ifdef __sparc64__
875 fbwscons_setcolormap(&rdev->sf, radeondrm_setcolor);
876 #else
877 radeondrm_setpal(rdev, ri);
878 #endif
879 drm_fb_helper_restore_fbdev_mode_unlocked(rdev_to_drm(rdev)->fb_helper);
880
881 if (rdev->switchcb)
882 (rdev->switchcb)(rdev->switchcbarg, 0, 0);
883 }
884
885 void
radeondrm_enter_ddb(void * v,void * cookie)886 radeondrm_enter_ddb(void *v, void *cookie)
887 {
888 struct rasops_info *ri = v;
889 struct radeon_device *rdev = ri->ri_hw;
890 struct drm_fb_helper *fb_helper = rdev_to_drm(rdev)->fb_helper;
891
892 if (cookie == ri->ri_active)
893 return;
894
895 rasops_show_screen(ri, cookie, 0, NULL, NULL);
896 drm_fb_helper_debug_enter(fb_helper->info);
897 }
898
899 #ifdef __sparc64__
900 void
radeondrm_setcolor(void * v,u_int index,u_int8_t r,u_int8_t g,u_int8_t b)901 radeondrm_setcolor(void *v, u_int index, u_int8_t r, u_int8_t g, u_int8_t b)
902 {
903 struct sunfb *sf = v;
904 struct radeon_device *rdev = sf->sf_ro.ri_hw;
905
906 /* see legacy_crtc_load_lut() */
907 if (rdev->family < CHIP_RS600) {
908 WREG8(RADEON_PALETTE_INDEX, index);
909 WREG32(RADEON_PALETTE_30_DATA,
910 (r << 22) | (g << 12) | (b << 2));
911 } else {
912 printf("%s: setcolor family %d not handled\n",
913 rdev->self.dv_xname, rdev->family);
914 }
915 }
916 #endif
917
918 void
radeondrm_setpal(struct radeon_device * rdev,struct rasops_info * ri)919 radeondrm_setpal(struct radeon_device *rdev, struct rasops_info *ri)
920 {
921 struct drm_device *dev = rdev_to_drm(rdev);
922 struct drm_crtc *crtc;
923 uint16_t *r_base, *g_base, *b_base;
924 int i, index, ret = 0;
925 const u_char *p;
926
927 if (ri->ri_depth != 8)
928 return;
929
930 for (i = 0; i < rdev->num_crtc; i++) {
931 struct drm_modeset_acquire_ctx ctx;
932 crtc = &rdev->mode_info.crtcs[i]->base;
933
934 r_base = crtc->gamma_store;
935 g_base = r_base + crtc->gamma_size;
936 b_base = g_base + crtc->gamma_size;
937
938 DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret);
939
940 p = rasops_cmap;
941 for (index = 0; index < 256; index++) {
942 r_base[index] = *p++ << 8;
943 g_base[index] = *p++ << 8;
944 b_base[index] = *p++ << 8;
945 }
946
947 crtc->funcs->gamma_set(crtc, NULL, NULL, NULL, 0, NULL);
948
949 DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
950 }
951 }
952
953 void
radeondrm_attach_kms(struct device * parent,struct device * self,void * aux)954 radeondrm_attach_kms(struct device *parent, struct device *self, void *aux)
955 {
956 struct radeon_device *rdev = (struct radeon_device *)self;
957 struct drm_device *dev;
958 struct pci_attach_args *pa = aux;
959 const struct pci_device_id *id_entry;
960 int is_agp;
961 pcireg_t type;
962 int i;
963 uint8_t rmmio_bar;
964 paddr_t fb_aper;
965 pcireg_t addr, mask;
966 int s;
967
968 #if defined(__sparc64__) || defined(__macppc__)
969 extern int fbnode;
970 #endif
971
972 id_entry = drm_find_description(PCI_VENDOR(pa->pa_id),
973 PCI_PRODUCT(pa->pa_id), pciidlist);
974 rdev->flags = id_entry->driver_data;
975 rdev->family = rdev->flags & RADEON_FAMILY_MASK;
976 rdev->pc = pa->pa_pc;
977 rdev->pa_tag = pa->pa_tag;
978 rdev->iot = pa->pa_iot;
979 rdev->memt = pa->pa_memt;
980 rdev->dmat = pa->pa_dmat;
981
982 #if defined(__sparc64__) || defined(__macppc__)
983 if (fbnode == PCITAG_NODE(rdev->pa_tag))
984 rdev->console = rdev->primary = 1;
985 #else
986 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY &&
987 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_DISPLAY_VGA &&
988 (pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG)
989 & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE))
990 == (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) {
991 rdev->primary = 1;
992 #if NVGA > 0
993 rdev->console = vga_is_console(pa->pa_iot, -1);
994 vga_console_attached = 1;
995 #endif
996 }
997
998 #if NEFIFB > 0
999 if (efifb_is_primary(pa)) {
1000 rdev->primary = 1;
1001 rdev->console = efifb_is_console(pa);
1002 efifb_detach();
1003 }
1004 #endif
1005 #endif
1006
1007 #define RADEON_PCI_MEM 0x10
1008
1009 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RADEON_PCI_MEM);
1010 if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM ||
1011 pci_mapreg_info(pa->pa_pc, pa->pa_tag, RADEON_PCI_MEM,
1012 type, &rdev->fb_aper_offset, &rdev->fb_aper_size, NULL)) {
1013 printf(": can't get framebuffer info\n");
1014 return;
1015 }
1016 if (rdev->fb_aper_offset == 0) {
1017 bus_size_t start, end;
1018 bus_addr_t base;
1019
1020 KASSERT(pa->pa_memex != NULL);
1021
1022 start = max(PCI_MEM_START, pa->pa_memex->ex_start);
1023 end = min(PCI_MEM_END, pa->pa_memex->ex_end);
1024 if (extent_alloc_subregion(pa->pa_memex, start, end,
1025 rdev->fb_aper_size, rdev->fb_aper_size, 0, 0, 0, &base)) {
1026 printf(": can't reserve framebuffer space\n");
1027 return;
1028 }
1029 pci_conf_write(pa->pa_pc, pa->pa_tag, RADEON_PCI_MEM, base);
1030 if (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT)
1031 pci_conf_write(pa->pa_pc, pa->pa_tag,
1032 RADEON_PCI_MEM + 4, (uint64_t)base >> 32);
1033 rdev->fb_aper_offset = base;
1034 }
1035
1036 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) {
1037 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, i);
1038 if (type == PCI_MAPREG_TYPE_IO) {
1039 pci_mapreg_map(pa, i, type, 0, NULL,
1040 &rdev->rio_mem, NULL, &rdev->rio_mem_size, 0);
1041 break;
1042 }
1043 if (type == PCI_MAPREG_MEM_TYPE_64BIT)
1044 i += 4;
1045 }
1046
1047 if (rdev->family >= CHIP_BONAIRE) {
1048 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x18);
1049 if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM ||
1050 pci_mapreg_map(pa, 0x18, type, BUS_SPACE_MAP_LINEAR, NULL,
1051 &rdev->doorbell.bsh, &rdev->doorbell.base,
1052 &rdev->doorbell.size, 0)) {
1053 printf(": can't map doorbell space\n");
1054 return;
1055 }
1056 rdev->doorbell.ptr = bus_space_vaddr(rdev->memt,
1057 rdev->doorbell.bsh);
1058 }
1059
1060 if (rdev->family >= CHIP_BONAIRE)
1061 rmmio_bar = 0x24;
1062 else
1063 rmmio_bar = 0x18;
1064
1065 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, rmmio_bar);
1066 if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM ||
1067 pci_mapreg_map(pa, rmmio_bar, type, BUS_SPACE_MAP_LINEAR, NULL,
1068 &rdev->rmmio_bsh, &rdev->rmmio_base, &rdev->rmmio_size, 0)) {
1069 printf(": can't map rmmio space\n");
1070 return;
1071 }
1072 rdev->rmmio = bus_space_vaddr(rdev->memt, rdev->rmmio_bsh);
1073
1074 /*
1075 * Make sure we have a base address for the ROM such that we
1076 * can map it later.
1077 */
1078 s = splhigh();
1079 addr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG);
1080 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, ~PCI_ROM_ENABLE);
1081 mask = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG);
1082 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, addr);
1083 splx(s);
1084
1085 if (addr == 0 && PCI_ROM_SIZE(mask) != 0 && pa->pa_memex) {
1086 bus_size_t size, start, end;
1087 bus_addr_t base;
1088
1089 size = PCI_ROM_SIZE(mask);
1090 start = max(PCI_MEM_START, pa->pa_memex->ex_start);
1091 end = min(PCI_MEM_END, pa->pa_memex->ex_end);
1092 if (extent_alloc_subregion(pa->pa_memex, start, end, size,
1093 size, 0, 0, 0, &base) == 0)
1094 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, base);
1095 }
1096
1097 /* update BUS flag */
1098 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, NULL, NULL)) {
1099 rdev->flags |= RADEON_IS_AGP;
1100 } else if (pci_get_capability(pa->pa_pc, pa->pa_tag,
1101 PCI_CAP_PCIEXPRESS, NULL, NULL)) {
1102 rdev->flags |= RADEON_IS_PCIE;
1103 } else {
1104 rdev->flags |= RADEON_IS_PCI;
1105 }
1106
1107 if ((radeon_runtime_pm != 0) &&
1108 radeon_has_atpx() &&
1109 ((rdev->flags & RADEON_IS_IGP) == 0))
1110 rdev->flags |= RADEON_IS_PX;
1111
1112 DRM_DEBUG("%s card detected\n",
1113 ((rdev->flags & RADEON_IS_AGP) ? "AGP" :
1114 (((rdev->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1115
1116 is_agp = pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP,
1117 NULL, NULL);
1118
1119 printf("\n");
1120
1121 dev = drm_attach_pci(&kms_driver, pa, is_agp, rdev->primary,
1122 self, &rdev->ddev);
1123 if (dev == NULL) {
1124 printf("%s: drm attach failed\n", rdev->self.dv_xname);
1125 return;
1126 }
1127 rdev->pdev = dev->pdev;
1128
1129 if (!radeon_msi_ok(rdev))
1130 pa->pa_flags &= ~PCI_FLAGS_MSI_ENABLED;
1131
1132 rdev->msi_enabled = 0;
1133 if (pci_intr_map_msi(pa, &rdev->intrh) == 0)
1134 rdev->msi_enabled = 1;
1135 else if (pci_intr_map(pa, &rdev->intrh) != 0) {
1136 printf("%s: couldn't map interrupt\n", rdev->self.dv_xname);
1137 return;
1138 }
1139 printf("%s: %s\n", rdev->self.dv_xname,
1140 pci_intr_string(pa->pa_pc, rdev->intrh));
1141
1142 rdev->irqh = pci_intr_establish(pa->pa_pc, rdev->intrh, IPL_TTY,
1143 radeon_driver_irq_handler_kms, rdev_to_drm(rdev), rdev->self.dv_xname);
1144 if (rdev->irqh == NULL) {
1145 printf("%s: couldn't establish interrupt\n",
1146 rdev->self.dv_xname);
1147 return;
1148 }
1149 rdev->pdev->irq = -1;
1150
1151 #ifdef __sparc64__
1152 {
1153 struct rasops_info *ri;
1154 int node, console;
1155
1156 node = PCITAG_NODE(pa->pa_tag);
1157 console = (fbnode == node);
1158
1159 fb_setsize(&rdev->sf, 8, 1152, 900, node, 0);
1160
1161 /*
1162 * The firmware sets up the framebuffer such that it starts at
1163 * an offset from the start of video memory.
1164 */
1165 rdev->fb_offset =
1166 bus_space_read_4(rdev->memt, rdev->rmmio_bsh, RADEON_CRTC_OFFSET);
1167 if (bus_space_map(rdev->memt, rdev->fb_aper_offset + rdev->fb_offset,
1168 rdev->sf.sf_fbsize, BUS_SPACE_MAP_LINEAR, &rdev->memh)) {
1169 printf("%s: can't map video memory\n", rdev->self.dv_xname);
1170 return;
1171 }
1172
1173 ri = &rdev->sf.sf_ro;
1174 ri->ri_bits = bus_space_vaddr(rdev->memt, rdev->memh);
1175 ri->ri_hw = rdev;
1176 ri->ri_updatecursor = NULL;
1177
1178 fbwscons_init(&rdev->sf, RI_VCONS | RI_WRONLY | RI_BSWAP, console);
1179 if (console)
1180 fbwscons_console_init(&rdev->sf, -1);
1181 }
1182 #endif
1183
1184 fb_aper = bus_space_mmap(rdev->memt, rdev->fb_aper_offset, 0, 0, 0);
1185 if (fb_aper != -1)
1186 rasops_claim_framebuffer(fb_aper, rdev->fb_aper_size, self);
1187
1188 rdev->shutdown = true;
1189 config_mountroot(self, radeondrm_attachhook);
1190 }
1191
1192 int
radeondrm_forcedetach(struct radeon_device * rdev)1193 radeondrm_forcedetach(struct radeon_device *rdev)
1194 {
1195 struct pci_softc *sc = (struct pci_softc *)rdev->self.dv_parent;
1196 pcitag_t tag = rdev->pa_tag;
1197
1198 #if NVGA > 0
1199 if (rdev->primary)
1200 vga_console_attached = 0;
1201 #endif
1202
1203 /* reprobe pci device for non efi systems */
1204 #if NEFIFB > 0
1205 if (bios_efiinfo == NULL && !efifb_cb_found()) {
1206 #endif
1207 config_detach(&rdev->self, 0);
1208 return pci_probe_device(sc, tag, NULL, NULL);
1209 #if NEFIFB > 0
1210 } else if (rdev->primary) {
1211 efifb_reattach();
1212 }
1213 #endif
1214
1215 return 0;
1216 }
1217
1218 void
radeondrm_attachhook(struct device * self)1219 radeondrm_attachhook(struct device *self)
1220 {
1221 struct radeon_device *rdev = (struct radeon_device *)self;
1222 struct drm_device *dev = rdev_to_drm(rdev);
1223 int r, acpi_status;
1224
1225 /* radeon_device_init should report only fatal error
1226 * like memory allocation failure or iomapping failure,
1227 * or memory manager initialization failure, it must
1228 * properly initialize the GPU MC controller and permit
1229 * VRAM allocation
1230 */
1231 r = radeon_device_init(rdev, dev, dev->pdev, rdev->flags);
1232 if (r) {
1233 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
1234 radeon_fatal_error = 1;
1235 radeondrm_forcedetach(rdev);
1236 return;
1237 }
1238
1239 /* Again modeset_init should fail only on fatal error
1240 * otherwise it should provide enough functionalities
1241 * for shadowfb to run
1242 */
1243 r = radeon_modeset_init(rdev);
1244 if (r)
1245 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
1246
1247 /* Call ACPI methods: require modeset init
1248 * but failure is not fatal
1249 */
1250 if (!r) {
1251 acpi_status = radeon_acpi_init(rdev);
1252 if (acpi_status)
1253 DRM_DEBUG("Error during ACPI methods call\n");
1254 }
1255
1256 #ifdef notyet
1257 radeon_kfd_device_probe(rdev);
1258 radeon_kfd_device_init(rdev);
1259 #endif
1260
1261 if (radeon_is_px(rdev_to_drm(rdev))) {
1262 pm_runtime_use_autosuspend(dev->dev);
1263 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
1264 pm_runtime_set_active(dev->dev);
1265 pm_runtime_allow(dev->dev);
1266 pm_runtime_mark_last_busy(dev->dev);
1267 pm_runtime_put_autosuspend(dev->dev);
1268 }
1269
1270 {
1271 struct wsemuldisplaydev_attach_args aa;
1272 struct rasops_info *ri = &rdev->ro;
1273
1274 task_set(&rdev->switchtask, radeondrm_doswitch, ri);
1275
1276 /* from linux radeon_pci_probe() */
1277
1278 pci_set_drvdata(dev->pdev, dev);
1279
1280 drm_dev_register(dev, rdev->flags);
1281
1282 radeon_fbdev_setup(rdev);
1283
1284 if (ri->ri_bits == NULL)
1285 return;
1286
1287 #ifdef __sparc64__
1288 fbwscons_setcolormap(&rdev->sf, radeondrm_setcolor);
1289 ri = &rdev->sf.sf_ro;
1290 #else
1291 radeondrm_setpal(rdev, ri);
1292 ri->ri_flg = RI_CENTER | RI_VCONS | RI_WRONLY;
1293 rasops_init(ri, 160, 160);
1294
1295 ri->ri_hw = rdev;
1296 #endif
1297
1298 radeondrm_stdscreen.capabilities = ri->ri_caps;
1299 radeondrm_stdscreen.nrows = ri->ri_rows;
1300 radeondrm_stdscreen.ncols = ri->ri_cols;
1301 radeondrm_stdscreen.textops = &ri->ri_ops;
1302 radeondrm_stdscreen.fontwidth = ri->ri_font->fontwidth;
1303 radeondrm_stdscreen.fontheight = ri->ri_font->fontheight;
1304
1305 aa.console = rdev->console;
1306 aa.primary = rdev->primary;
1307 aa.scrdata = &radeondrm_screenlist;
1308 aa.accessops = &radeondrm_accessops;
1309 aa.accesscookie = ri;
1310 aa.defaultscreens = 0;
1311
1312 if (rdev->console) {
1313 uint32_t defattr;
1314
1315 ri->ri_ops.pack_attr(ri->ri_active, 0, 0, 0, &defattr);
1316 wsdisplay_cnattach(&radeondrm_stdscreen, ri->ri_active,
1317 ri->ri_ccol, ri->ri_crow, defattr);
1318 }
1319
1320 /*
1321 * Now that we've taken over the console, disable decoding of
1322 * VGA legacy addresses, and opt out of arbitration.
1323 */
1324 radeon_vga_set_state(rdev, false);
1325 pci_disable_legacy_vga(&rdev->self);
1326
1327 printf("%s: %dx%d, %dbpp\n", rdev->self.dv_xname,
1328 ri->ri_width, ri->ri_height, ri->ri_depth);
1329
1330 config_found_sm(&rdev->self, &aa, wsemuldisplaydevprint,
1331 wsemuldisplaydevsubmatch);
1332 }
1333 }
1334
1335 int
radeondrm_activate_kms(struct device * self,int act)1336 radeondrm_activate_kms(struct device *self, int act)
1337 {
1338 struct radeon_device *rdev = (struct radeon_device *)self;
1339 struct drm_device *ddev = rdev_to_drm(rdev);
1340 int rv = 0;
1341
1342 if (ddev == NULL || radeon_fatal_error)
1343 return (0);
1344
1345 switch (act) {
1346 case DVACT_QUIESCE:
1347 rv = config_activate_children(self, act);
1348 radeon_suspend_kms(ddev, true, true, false);
1349 break;
1350 case DVACT_SUSPEND:
1351 break;
1352 case DVACT_RESUME:
1353 break;
1354 case DVACT_WAKEUP:
1355 radeon_resume_kms(ddev, true, true);
1356 rv = config_activate_children(self, act);
1357 break;
1358 }
1359
1360 return (rv);
1361 }
1362