1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include <dev/drm2/drmP.h>
31 #include <dev/drm2/radeon/radeon_drm.h>
32 #include "radeon.h"
33
34 #define CURSOR_WIDTH 64
35 #define CURSOR_HEIGHT 64
36
radeon_lock_cursor(struct drm_crtc * crtc,bool lock)37 static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock)
38 {
39 struct radeon_device *rdev = crtc->dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 uint32_t cur_lock;
42
43 if (ASIC_IS_DCE4(rdev)) {
44 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
45 if (lock)
46 cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK;
47 else
48 cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK;
49 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
50 } else if (ASIC_IS_AVIVO(rdev)) {
51 cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
52 if (lock)
53 cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK;
54 else
55 cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
56 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
57 } else {
58 cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);
59 if (lock)
60 cur_lock |= RADEON_CUR_LOCK;
61 else
62 cur_lock &= ~RADEON_CUR_LOCK;
63 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
64 }
65 }
66
radeon_hide_cursor(struct drm_crtc * crtc)67 static void radeon_hide_cursor(struct drm_crtc *crtc)
68 {
69 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
70 struct radeon_device *rdev = crtc->dev->dev_private;
71
72 if (ASIC_IS_DCE4(rdev)) {
73 WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset,
74 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
75 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
76 } else if (ASIC_IS_AVIVO(rdev)) {
77 WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
78 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
79 } else {
80 u32 reg;
81 switch (radeon_crtc->crtc_id) {
82 case 0:
83 reg = RADEON_CRTC_GEN_CNTL;
84 break;
85 case 1:
86 reg = RADEON_CRTC2_GEN_CNTL;
87 break;
88 default:
89 return;
90 }
91 WREG32_IDX(reg, RREG32_IDX(reg) & ~RADEON_CRTC_CUR_EN);
92 }
93 }
94
radeon_show_cursor(struct drm_crtc * crtc)95 static void radeon_show_cursor(struct drm_crtc *crtc)
96 {
97 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
98 struct radeon_device *rdev = crtc->dev->dev_private;
99
100 if (ASIC_IS_DCE4(rdev)) {
101 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
102 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |
103 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
104 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
105 } else if (ASIC_IS_AVIVO(rdev)) {
106 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
107 WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
108 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
109 } else {
110 switch (radeon_crtc->crtc_id) {
111 case 0:
112 WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
113 break;
114 case 1:
115 WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
116 break;
117 default:
118 return;
119 }
120
121 WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN |
122 (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)),
123 ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
124 }
125 }
126
radeon_set_cursor(struct drm_crtc * crtc,struct drm_gem_object * obj,uint64_t gpu_addr)127 static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
128 uint64_t gpu_addr)
129 {
130 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
131 struct radeon_device *rdev = crtc->dev->dev_private;
132
133 if (ASIC_IS_DCE4(rdev)) {
134 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
135 upper_32_bits(gpu_addr));
136 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
137 gpu_addr & 0xffffffff);
138 } else if (ASIC_IS_AVIVO(rdev)) {
139 if (rdev->family >= CHIP_RV770) {
140 if (radeon_crtc->crtc_id)
141 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
142 else
143 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
144 }
145 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
146 gpu_addr & 0xffffffff);
147 } else {
148 radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr;
149 /* offset is from DISP(2)_BASE_ADDRESS */
150 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);
151 }
152 }
153
radeon_crtc_cursor_set(struct drm_crtc * crtc,struct drm_file * file_priv,uint32_t handle,uint32_t width,uint32_t height)154 int radeon_crtc_cursor_set(struct drm_crtc *crtc,
155 struct drm_file *file_priv,
156 uint32_t handle,
157 uint32_t width,
158 uint32_t height)
159 {
160 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
161 struct radeon_device *rdev = crtc->dev->dev_private;
162 struct drm_gem_object *obj;
163 struct radeon_bo *robj;
164 uint64_t gpu_addr;
165 int ret;
166
167 if (!handle) {
168 /* turn off cursor */
169 radeon_hide_cursor(crtc);
170 obj = NULL;
171 goto unpin;
172 }
173
174 if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
175 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
176 return -EINVAL;
177 }
178
179 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
180 if (!obj) {
181 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);
182 return -ENOENT;
183 }
184
185 robj = gem_to_radeon_bo(obj);
186 ret = radeon_bo_reserve(robj, false);
187 if (unlikely(ret != 0))
188 goto fail;
189 /* Only 27 bit offset for legacy cursor */
190 ret = radeon_bo_pin_restricted(robj, RADEON_GEM_DOMAIN_VRAM,
191 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
192 &gpu_addr);
193 radeon_bo_unreserve(robj);
194 if (ret)
195 goto fail;
196
197 radeon_crtc->cursor_width = width;
198 radeon_crtc->cursor_height = height;
199
200 radeon_lock_cursor(crtc, true);
201 radeon_set_cursor(crtc, obj, gpu_addr);
202 radeon_show_cursor(crtc);
203 radeon_lock_cursor(crtc, false);
204
205 unpin:
206 if (radeon_crtc->cursor_bo) {
207 robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
208 ret = radeon_bo_reserve(robj, false);
209 if (likely(ret == 0)) {
210 radeon_bo_unpin(robj);
211 radeon_bo_unreserve(robj);
212 }
213 drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo);
214 }
215
216 radeon_crtc->cursor_bo = obj;
217 return 0;
218 fail:
219 drm_gem_object_unreference_unlocked(obj);
220
221 return ret;
222 }
223
radeon_crtc_cursor_move(struct drm_crtc * crtc,int x,int y)224 int radeon_crtc_cursor_move(struct drm_crtc *crtc,
225 int x, int y)
226 {
227 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
228 struct radeon_device *rdev = crtc->dev->dev_private;
229 int xorigin = 0, yorigin = 0;
230 int w = radeon_crtc->cursor_width;
231
232 if (ASIC_IS_AVIVO(rdev)) {
233 /* avivo cursor are offset into the total surface */
234 x += crtc->x;
235 y += crtc->y;
236 }
237 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
238
239 if (x < 0) {
240 xorigin = min(-x, CURSOR_WIDTH - 1);
241 x = 0;
242 }
243 if (y < 0) {
244 yorigin = min(-y, CURSOR_HEIGHT - 1);
245 y = 0;
246 }
247
248 /* fixed on DCE6 and newer */
249 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE6(rdev)) {
250 int i = 0;
251 struct drm_crtc *crtc_p;
252
253 /* avivo cursor image can't end on 128 pixel boundary or
254 * go past the end of the frame if both crtcs are enabled
255 */
256 list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) {
257 if (crtc_p->enabled)
258 i++;
259 }
260 if (i > 1) {
261 int cursor_end, frame_end;
262
263 cursor_end = x - xorigin + w;
264 frame_end = crtc->x + crtc->mode.crtc_hdisplay;
265 if (cursor_end >= frame_end) {
266 w = w - (cursor_end - frame_end);
267 if (!(frame_end & 0x7f))
268 w--;
269 } else {
270 if (!(cursor_end & 0x7f))
271 w--;
272 }
273 if (w <= 0) {
274 w = 1;
275 cursor_end = x - xorigin + w;
276 if (!(cursor_end & 0x7f)) {
277 x--;
278 if (x < 0) {
279 DRM_ERROR("%s: x(%d) < 0", __func__, x);
280 }
281 }
282 }
283 }
284 }
285
286 radeon_lock_cursor(crtc, true);
287 if (ASIC_IS_DCE4(rdev)) {
288 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
289 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
290 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
291 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
292 } else if (ASIC_IS_AVIVO(rdev)) {
293 WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
294 WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
295 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
296 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
297 } else {
298 if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
299 y *= 2;
300
301 WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,
302 (RADEON_CUR_LOCK
303 | (xorigin << 16)
304 | yorigin));
305 WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
306 (RADEON_CUR_LOCK
307 | (x << 16)
308 | y));
309 /* offset is from DISP(2)_BASE_ADDRESS */
310 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +
311 (yorigin * 256)));
312 }
313 radeon_lock_cursor(crtc, false);
314
315 return 0;
316 }
317