1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include <dev/drm2/drmP.h>
31 #include <dev/drm2/radeon/radeon_drm.h>
32 #include "radeon.h"
33
34 #include "atom.h"
35
36 #include <dev/drm2/drm_crtc_helper.h>
37 #include <dev/drm2/drm_edid.h>
38
avivo_crtc_load_lut(struct drm_crtc * crtc)39 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
40 {
41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
42 struct drm_device *dev = crtc->dev;
43 struct radeon_device *rdev = dev->dev_private;
44 int i;
45
46 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
47 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
48
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
52
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
56
57 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
58 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
59 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
60
61 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
62 for (i = 0; i < 256; i++) {
63 WREG32(AVIVO_DC_LUT_30_COLOR,
64 (radeon_crtc->lut_r[i] << 20) |
65 (radeon_crtc->lut_g[i] << 10) |
66 (radeon_crtc->lut_b[i] << 0));
67 }
68
69 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
70 }
71
dce4_crtc_load_lut(struct drm_crtc * crtc)72 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
73 {
74 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
75 struct drm_device *dev = crtc->dev;
76 struct radeon_device *rdev = dev->dev_private;
77 int i;
78
79 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
80 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
81
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
85
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
89
90 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
91 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
92
93 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
94 for (i = 0; i < 256; i++) {
95 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
96 (radeon_crtc->lut_r[i] << 20) |
97 (radeon_crtc->lut_g[i] << 10) |
98 (radeon_crtc->lut_b[i] << 0));
99 }
100 }
101
dce5_crtc_load_lut(struct drm_crtc * crtc)102 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
103 {
104 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
105 struct drm_device *dev = crtc->dev;
106 struct radeon_device *rdev = dev->dev_private;
107 int i;
108
109 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
110
111 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
112 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
113 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
114 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
115 NI_GRPH_PRESCALE_BYPASS);
116 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
117 NI_OVL_PRESCALE_BYPASS);
118 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
119 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
120 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
121
122 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
123
124 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
125 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
127
128 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
129 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
131
132 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
133 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
134
135 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
136 for (i = 0; i < 256; i++) {
137 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
138 (radeon_crtc->lut_r[i] << 20) |
139 (radeon_crtc->lut_g[i] << 10) |
140 (radeon_crtc->lut_b[i] << 0));
141 }
142
143 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
144 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
145 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
146 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
147 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
148 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
149 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
150 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
151 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
152 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
153 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
154 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
155 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
156 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
157 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
158 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
159
160 }
161
legacy_crtc_load_lut(struct drm_crtc * crtc)162 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
163 {
164 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
165 struct drm_device *dev = crtc->dev;
166 struct radeon_device *rdev = dev->dev_private;
167 int i;
168 uint32_t dac2_cntl;
169
170 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
171 if (radeon_crtc->crtc_id == 0)
172 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
173 else
174 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
175 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
176
177 WREG8(RADEON_PALETTE_INDEX, 0);
178 for (i = 0; i < 256; i++) {
179 WREG32(RADEON_PALETTE_30_DATA,
180 (radeon_crtc->lut_r[i] << 20) |
181 (radeon_crtc->lut_g[i] << 10) |
182 (radeon_crtc->lut_b[i] << 0));
183 }
184 }
185
radeon_crtc_load_lut(struct drm_crtc * crtc)186 void radeon_crtc_load_lut(struct drm_crtc *crtc)
187 {
188 struct drm_device *dev = crtc->dev;
189 struct radeon_device *rdev = dev->dev_private;
190
191 if (!crtc->enabled)
192 return;
193
194 if (ASIC_IS_DCE5(rdev))
195 dce5_crtc_load_lut(crtc);
196 else if (ASIC_IS_DCE4(rdev))
197 dce4_crtc_load_lut(crtc);
198 else if (ASIC_IS_AVIVO(rdev))
199 avivo_crtc_load_lut(crtc);
200 else
201 legacy_crtc_load_lut(crtc);
202 }
203
204 /** Sets the color ramps on behalf of fbcon */
radeon_crtc_fb_gamma_set(struct drm_crtc * crtc,u16 red,u16 green,u16 blue,int regno)205 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
206 u16 blue, int regno)
207 {
208 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
209
210 radeon_crtc->lut_r[regno] = red >> 6;
211 radeon_crtc->lut_g[regno] = green >> 6;
212 radeon_crtc->lut_b[regno] = blue >> 6;
213 }
214
215 /** Gets the color ramps on behalf of fbcon */
radeon_crtc_fb_gamma_get(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,int regno)216 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
217 u16 *blue, int regno)
218 {
219 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
220
221 *red = radeon_crtc->lut_r[regno] << 6;
222 *green = radeon_crtc->lut_g[regno] << 6;
223 *blue = radeon_crtc->lut_b[regno] << 6;
224 }
225
radeon_crtc_gamma_set(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,uint32_t start,uint32_t size)226 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
227 u16 *blue, uint32_t start, uint32_t size)
228 {
229 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
230 int end = (start + size > 256) ? 256 : start + size, i;
231
232 /* userspace palettes are always correct as is */
233 for (i = start; i < end; i++) {
234 radeon_crtc->lut_r[i] = red[i] >> 6;
235 radeon_crtc->lut_g[i] = green[i] >> 6;
236 radeon_crtc->lut_b[i] = blue[i] >> 6;
237 }
238 radeon_crtc_load_lut(crtc);
239 }
240
radeon_crtc_destroy(struct drm_crtc * crtc)241 static void radeon_crtc_destroy(struct drm_crtc *crtc)
242 {
243 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
244
245 drm_crtc_cleanup(crtc);
246 free(radeon_crtc, DRM_MEM_DRIVER);
247 }
248
249 /*
250 * Handle unpin events outside the interrupt handler proper.
251 */
radeon_unpin_work_func(void * arg,int pending)252 static void radeon_unpin_work_func(void *arg, int pending)
253 {
254 struct radeon_unpin_work *work = arg;
255 int r;
256
257 /* unpin of the old buffer */
258 r = radeon_bo_reserve(work->old_rbo, false);
259 if (likely(r == 0)) {
260 r = radeon_bo_unpin(work->old_rbo);
261 if (unlikely(r != 0)) {
262 DRM_ERROR("failed to unpin buffer after flip\n");
263 }
264 radeon_bo_unreserve(work->old_rbo);
265 } else
266 DRM_ERROR("failed to reserve buffer after flip\n");
267
268 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
269 free(work, DRM_MEM_DRIVER);
270 }
271
radeon_crtc_handle_flip(struct radeon_device * rdev,int crtc_id)272 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
273 {
274 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
275 struct radeon_unpin_work *work;
276 struct drm_pending_vblank_event *e;
277 struct timeval now;
278 unsigned long flags;
279 u32 update_pending;
280 int vpos, hpos;
281
282 DRM_SPINLOCK_IRQSAVE(&rdev->ddev->event_lock, flags);
283 work = radeon_crtc->unpin_work;
284 if (work == NULL ||
285 (work->fence && !radeon_fence_signaled(work->fence))) {
286 DRM_SPINUNLOCK_IRQRESTORE(&rdev->ddev->event_lock, flags);
287 return;
288 }
289 /* New pageflip, or just completion of a previous one? */
290 if (!radeon_crtc->deferred_flip_completion) {
291 /* do the flip (mmio) */
292 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
293 } else {
294 /* This is just a completion of a flip queued in crtc
295 * at last invocation. Make sure we go directly to
296 * completion routine.
297 */
298 update_pending = 0;
299 radeon_crtc->deferred_flip_completion = 0;
300 }
301
302 /* Has the pageflip already completed in crtc, or is it certain
303 * to complete in this vblank?
304 */
305 if (update_pending &&
306 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
307 &vpos, &hpos)) &&
308 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
309 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
310 /* crtc didn't flip in this target vblank interval,
311 * but flip is pending in crtc. Based on the current
312 * scanout position we know that the current frame is
313 * (nearly) complete and the flip will (likely)
314 * complete before the start of the next frame.
315 */
316 update_pending = 0;
317 }
318 if (update_pending) {
319 /* crtc didn't flip in this target vblank interval,
320 * but flip is pending in crtc. It will complete it
321 * in next vblank interval, so complete the flip at
322 * next vblank irq.
323 */
324 radeon_crtc->deferred_flip_completion = 1;
325 DRM_SPINUNLOCK_IRQRESTORE(&rdev->ddev->event_lock, flags);
326 return;
327 }
328
329 /* Pageflip (will be) certainly completed in this vblank. Clean up. */
330 radeon_crtc->unpin_work = NULL;
331
332 /* wakeup userspace */
333 if (work->event) {
334 e = work->event;
335 e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now);
336 e->event.tv_sec = now.tv_sec;
337 e->event.tv_usec = now.tv_usec;
338 list_add_tail(&e->base.link, &e->base.file_priv->event_list);
339 drm_event_wakeup(&e->base);
340 }
341 DRM_SPINUNLOCK_IRQRESTORE(&rdev->ddev->event_lock, flags);
342
343 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
344 radeon_fence_unref(&work->fence);
345 radeon_post_page_flip(work->rdev, work->crtc_id);
346 taskqueue_enqueue(rdev->tq, &work->work);
347 }
348
radeon_crtc_page_flip(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_pending_vblank_event * event)349 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
350 struct drm_framebuffer *fb,
351 struct drm_pending_vblank_event *event)
352 {
353 struct drm_device *dev = crtc->dev;
354 struct radeon_device *rdev = dev->dev_private;
355 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
356 struct radeon_framebuffer *old_radeon_fb;
357 struct radeon_framebuffer *new_radeon_fb;
358 struct drm_gem_object *obj;
359 struct radeon_bo *rbo;
360 struct radeon_unpin_work *work;
361 unsigned long flags;
362 u32 tiling_flags, pitch_pixels;
363 u64 base;
364 int r;
365
366 work = malloc(sizeof *work, DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
367 if (work == NULL)
368 return -ENOMEM;
369
370 work->event = event;
371 work->rdev = rdev;
372 work->crtc_id = radeon_crtc->crtc_id;
373 old_radeon_fb = to_radeon_framebuffer(crtc->fb);
374 new_radeon_fb = to_radeon_framebuffer(fb);
375 /* schedule unpin of the old buffer */
376 obj = old_radeon_fb->obj;
377 /* take a reference to the old object */
378 drm_gem_object_reference(obj);
379 rbo = gem_to_radeon_bo(obj);
380 work->old_rbo = rbo;
381 obj = new_radeon_fb->obj;
382 rbo = gem_to_radeon_bo(obj);
383
384 mtx_lock(&rbo->tbo.bdev->fence_lock);
385 if (rbo->tbo.sync_obj)
386 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
387 mtx_unlock(&rbo->tbo.bdev->fence_lock);
388
389 TASK_INIT(&work->work, 0, radeon_unpin_work_func, work);
390
391 /* We borrow the event spin lock for protecting unpin_work */
392 DRM_SPINLOCK_IRQSAVE(&dev->event_lock, flags);
393 if (radeon_crtc->unpin_work) {
394 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
395 r = -EBUSY;
396 goto unlock_free;
397 }
398 radeon_crtc->unpin_work = work;
399 radeon_crtc->deferred_flip_completion = 0;
400 DRM_SPINUNLOCK_IRQRESTORE(&dev->event_lock, flags);
401
402 /* pin the new buffer */
403 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
404 work->old_rbo, rbo);
405
406 r = radeon_bo_reserve(rbo, false);
407 if (unlikely(r != 0)) {
408 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
409 goto pflip_cleanup;
410 }
411 /* Only 27 bit offset for legacy CRTC */
412 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
413 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
414 if (unlikely(r != 0)) {
415 radeon_bo_unreserve(rbo);
416 r = -EINVAL;
417 DRM_ERROR("failed to pin new rbo buffer before flip\n");
418 goto pflip_cleanup;
419 }
420 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
421 radeon_bo_unreserve(rbo);
422
423 if (!ASIC_IS_AVIVO(rdev)) {
424 /* crtc offset is from display base addr not FB location */
425 base -= radeon_crtc->legacy_display_base_addr;
426 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
427
428 if (tiling_flags & RADEON_TILING_MACRO) {
429 if (ASIC_IS_R300(rdev)) {
430 base &= ~0x7ff;
431 } else {
432 int byteshift = fb->bits_per_pixel >> 4;
433 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
434 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
435 }
436 } else {
437 int offset = crtc->y * pitch_pixels + crtc->x;
438 switch (fb->bits_per_pixel) {
439 case 8:
440 default:
441 offset *= 1;
442 break;
443 case 15:
444 case 16:
445 offset *= 2;
446 break;
447 case 24:
448 offset *= 3;
449 break;
450 case 32:
451 offset *= 4;
452 break;
453 }
454 base += offset;
455 }
456 base &= ~7;
457 }
458
459 DRM_SPINLOCK_IRQSAVE(&dev->event_lock, flags);
460 work->new_crtc_base = base;
461 DRM_SPINUNLOCK_IRQRESTORE(&dev->event_lock, flags);
462
463 /* update crtc fb */
464 crtc->fb = fb;
465
466 r = drm_vblank_get(dev, radeon_crtc->crtc_id);
467 if (r) {
468 DRM_ERROR("failed to get vblank before flip\n");
469 goto pflip_cleanup1;
470 }
471
472 /* set the proper interrupt */
473 radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
474
475 return 0;
476
477 pflip_cleanup1:
478 if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
479 DRM_ERROR("failed to reserve new rbo in error path\n");
480 goto pflip_cleanup;
481 }
482 if (unlikely(radeon_bo_unpin(rbo) != 0)) {
483 DRM_ERROR("failed to unpin new rbo in error path\n");
484 }
485 radeon_bo_unreserve(rbo);
486
487 pflip_cleanup:
488 DRM_SPINLOCK_IRQSAVE(&dev->event_lock, flags);
489 radeon_crtc->unpin_work = NULL;
490 unlock_free:
491 DRM_SPINUNLOCK_IRQRESTORE(&dev->event_lock, flags);
492 drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
493 radeon_fence_unref(&work->fence);
494 free(work, DRM_MEM_DRIVER);
495
496 return r;
497 }
498
499 static const struct drm_crtc_funcs radeon_crtc_funcs = {
500 .cursor_set = radeon_crtc_cursor_set,
501 .cursor_move = radeon_crtc_cursor_move,
502 .gamma_set = radeon_crtc_gamma_set,
503 .set_config = drm_crtc_helper_set_config,
504 .destroy = radeon_crtc_destroy,
505 .page_flip = radeon_crtc_page_flip,
506 };
507
radeon_crtc_init(struct drm_device * dev,int index)508 static void radeon_crtc_init(struct drm_device *dev, int index)
509 {
510 struct radeon_device *rdev = dev->dev_private;
511 struct radeon_crtc *radeon_crtc;
512 int i;
513
514 radeon_crtc = malloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
515 if (radeon_crtc == NULL)
516 return;
517
518 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
519
520 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
521 radeon_crtc->crtc_id = index;
522 rdev->mode_info.crtcs[index] = radeon_crtc;
523
524 #if 0
525 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
526 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
527 radeon_crtc->mode_set.num_connectors = 0;
528 #endif
529
530 for (i = 0; i < 256; i++) {
531 radeon_crtc->lut_r[i] = i << 2;
532 radeon_crtc->lut_g[i] = i << 2;
533 radeon_crtc->lut_b[i] = i << 2;
534 }
535
536 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
537 radeon_atombios_init_crtc(dev, radeon_crtc);
538 else
539 radeon_legacy_init_crtc(dev, radeon_crtc);
540 }
541
542 static const char *encoder_names[37] = {
543 "NONE",
544 "INTERNAL_LVDS",
545 "INTERNAL_TMDS1",
546 "INTERNAL_TMDS2",
547 "INTERNAL_DAC1",
548 "INTERNAL_DAC2",
549 "INTERNAL_SDVOA",
550 "INTERNAL_SDVOB",
551 "SI170B",
552 "CH7303",
553 "CH7301",
554 "INTERNAL_DVO1",
555 "EXTERNAL_SDVOA",
556 "EXTERNAL_SDVOB",
557 "TITFP513",
558 "INTERNAL_LVTM1",
559 "VT1623",
560 "HDMI_SI1930",
561 "HDMI_INTERNAL",
562 "INTERNAL_KLDSCP_TMDS1",
563 "INTERNAL_KLDSCP_DVO1",
564 "INTERNAL_KLDSCP_DAC1",
565 "INTERNAL_KLDSCP_DAC2",
566 "SI178",
567 "MVPU_FPGA",
568 "INTERNAL_DDI",
569 "VT1625",
570 "HDMI_SI1932",
571 "DP_AN9801",
572 "DP_DP501",
573 "INTERNAL_UNIPHY",
574 "INTERNAL_KLDSCP_LVTMA",
575 "INTERNAL_UNIPHY1",
576 "INTERNAL_UNIPHY2",
577 "NUTMEG",
578 "TRAVIS",
579 "INTERNAL_VCE"
580 };
581
582 static const char *hpd_names[6] = {
583 "HPD1",
584 "HPD2",
585 "HPD3",
586 "HPD4",
587 "HPD5",
588 "HPD6",
589 };
590
radeon_print_display_setup(struct drm_device * dev)591 static void radeon_print_display_setup(struct drm_device *dev)
592 {
593 struct drm_connector *connector;
594 struct radeon_connector *radeon_connector;
595 struct drm_encoder *encoder;
596 struct radeon_encoder *radeon_encoder;
597 uint32_t devices;
598 int i = 0;
599
600 DRM_INFO("Radeon Display Connectors\n");
601 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
602 radeon_connector = to_radeon_connector(connector);
603 DRM_INFO("Connector %d:\n", i);
604 DRM_INFO(" %s\n", drm_get_connector_name(connector));
605 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
606 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
607 if (radeon_connector->ddc_bus) {
608 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
609 radeon_connector->ddc_bus->rec.mask_clk_reg,
610 radeon_connector->ddc_bus->rec.mask_data_reg,
611 radeon_connector->ddc_bus->rec.a_clk_reg,
612 radeon_connector->ddc_bus->rec.a_data_reg,
613 radeon_connector->ddc_bus->rec.en_clk_reg,
614 radeon_connector->ddc_bus->rec.en_data_reg,
615 radeon_connector->ddc_bus->rec.y_clk_reg,
616 radeon_connector->ddc_bus->rec.y_data_reg);
617 if (radeon_connector->router.ddc_valid)
618 DRM_INFO(" DDC Router 0x%x/0x%x\n",
619 radeon_connector->router.ddc_mux_control_pin,
620 radeon_connector->router.ddc_mux_state);
621 if (radeon_connector->router.cd_valid)
622 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
623 radeon_connector->router.cd_mux_control_pin,
624 radeon_connector->router.cd_mux_state);
625 } else {
626 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
627 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
628 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
629 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
630 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
631 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
632 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
633 }
634 DRM_INFO(" Encoders:\n");
635 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
636 radeon_encoder = to_radeon_encoder(encoder);
637 devices = radeon_encoder->devices & radeon_connector->devices;
638 if (devices) {
639 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
640 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
641 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
642 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
643 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
644 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
645 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
646 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
647 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
648 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
649 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
650 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
651 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
652 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
653 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
654 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
655 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
656 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
657 if (devices & ATOM_DEVICE_TV1_SUPPORT)
658 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
659 if (devices & ATOM_DEVICE_CV_SUPPORT)
660 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
661 }
662 }
663 i++;
664 }
665 }
666
radeon_setup_enc_conn(struct drm_device * dev)667 static bool radeon_setup_enc_conn(struct drm_device *dev)
668 {
669 struct radeon_device *rdev = dev->dev_private;
670 bool ret = false;
671
672 if (rdev->bios) {
673 if (rdev->is_atom_bios) {
674 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
675 if (ret == false)
676 ret = radeon_get_atom_connector_info_from_object_table(dev);
677 } else {
678 ret = radeon_get_legacy_connector_info_from_bios(dev);
679 if (ret == false)
680 ret = radeon_get_legacy_connector_info_from_table(dev);
681 }
682 } else {
683 if (!ASIC_IS_AVIVO(rdev))
684 ret = radeon_get_legacy_connector_info_from_table(dev);
685 }
686 if (ret) {
687 radeon_setup_encoder_clones(dev);
688 radeon_print_display_setup(dev);
689 }
690
691 return ret;
692 }
693
radeon_ddc_get_modes(struct radeon_connector * radeon_connector)694 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
695 {
696 struct drm_device *dev = radeon_connector->base.dev;
697 struct radeon_device *rdev = dev->dev_private;
698 int ret = 0;
699
700 /* on hw with routers, select right port */
701 if (radeon_connector->router.ddc_valid)
702 radeon_router_select_ddc_port(radeon_connector);
703
704 if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
705 ENCODER_OBJECT_ID_NONE) {
706 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
707
708 if (dig->dp_i2c_bus)
709 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
710 dig->dp_i2c_bus->adapter);
711 } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
712 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
713 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
714
715 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
716 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
717 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
718 dig->dp_i2c_bus->adapter);
719 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
720 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
721 radeon_connector->ddc_bus->adapter);
722 } else {
723 if (radeon_connector->ddc_bus && !radeon_connector->edid)
724 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
725 radeon_connector->ddc_bus->adapter);
726 }
727
728 if (!radeon_connector->edid) {
729 if (rdev->is_atom_bios) {
730 /* some laptops provide a hardcoded edid in rom for LCDs */
731 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
732 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
733 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
734 } else
735 /* some servers provide a hardcoded edid in rom for KVMs */
736 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
737 }
738 if (radeon_connector->edid) {
739 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
740 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
741 return ret;
742 }
743 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
744 return 0;
745 }
746
747 /* avivo */
avivo_get_fb_div(struct radeon_pll * pll,u32 target_clock,u32 post_div,u32 ref_div,u32 * fb_div,u32 * frac_fb_div)748 static void avivo_get_fb_div(struct radeon_pll *pll,
749 u32 target_clock,
750 u32 post_div,
751 u32 ref_div,
752 u32 *fb_div,
753 u32 *frac_fb_div)
754 {
755 u32 tmp = post_div * ref_div;
756
757 tmp *= target_clock;
758 *fb_div = tmp / pll->reference_freq;
759 *frac_fb_div = tmp % pll->reference_freq;
760
761 if (*fb_div > pll->max_feedback_div)
762 *fb_div = pll->max_feedback_div;
763 else if (*fb_div < pll->min_feedback_div)
764 *fb_div = pll->min_feedback_div;
765 }
766
avivo_get_post_div(struct radeon_pll * pll,u32 target_clock)767 static u32 avivo_get_post_div(struct radeon_pll *pll,
768 u32 target_clock)
769 {
770 u32 vco, post_div, tmp;
771
772 if (pll->flags & RADEON_PLL_USE_POST_DIV)
773 return pll->post_div;
774
775 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
776 if (pll->flags & RADEON_PLL_IS_LCD)
777 vco = pll->lcd_pll_out_min;
778 else
779 vco = pll->pll_out_min;
780 } else {
781 if (pll->flags & RADEON_PLL_IS_LCD)
782 vco = pll->lcd_pll_out_max;
783 else
784 vco = pll->pll_out_max;
785 }
786
787 post_div = vco / target_clock;
788 tmp = vco % target_clock;
789
790 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
791 if (tmp)
792 post_div++;
793 } else {
794 if (!tmp)
795 post_div--;
796 }
797
798 if (post_div > pll->max_post_div)
799 post_div = pll->max_post_div;
800 else if (post_div < pll->min_post_div)
801 post_div = pll->min_post_div;
802
803 return post_div;
804 }
805
806 #define MAX_TOLERANCE 10
807
radeon_compute_pll_avivo(struct radeon_pll * pll,u32 freq,u32 * dot_clock_p,u32 * fb_div_p,u32 * frac_fb_div_p,u32 * ref_div_p,u32 * post_div_p)808 void radeon_compute_pll_avivo(struct radeon_pll *pll,
809 u32 freq,
810 u32 *dot_clock_p,
811 u32 *fb_div_p,
812 u32 *frac_fb_div_p,
813 u32 *ref_div_p,
814 u32 *post_div_p)
815 {
816 u32 target_clock = freq / 10;
817 u32 post_div = avivo_get_post_div(pll, target_clock);
818 u32 ref_div = pll->min_ref_div;
819 u32 fb_div = 0, frac_fb_div = 0, tmp;
820
821 if (pll->flags & RADEON_PLL_USE_REF_DIV)
822 ref_div = pll->reference_div;
823
824 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
825 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
826 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
827 if (frac_fb_div >= 5) {
828 frac_fb_div -= 5;
829 frac_fb_div = frac_fb_div / 10;
830 frac_fb_div++;
831 }
832 if (frac_fb_div >= 10) {
833 fb_div++;
834 frac_fb_div = 0;
835 }
836 } else {
837 while (ref_div <= pll->max_ref_div) {
838 avivo_get_fb_div(pll, target_clock, post_div, ref_div,
839 &fb_div, &frac_fb_div);
840 if (frac_fb_div >= (pll->reference_freq / 2))
841 fb_div++;
842 frac_fb_div = 0;
843 tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
844 tmp = (tmp * 10000) / target_clock;
845
846 if (tmp > (10000 + MAX_TOLERANCE))
847 ref_div++;
848 else if (tmp >= (10000 - MAX_TOLERANCE))
849 break;
850 else
851 ref_div++;
852 }
853 }
854
855 *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
856 (ref_div * post_div * 10);
857 *fb_div_p = fb_div;
858 *frac_fb_div_p = frac_fb_div;
859 *ref_div_p = ref_div;
860 *post_div_p = post_div;
861 DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
862 *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
863 }
864
865 /* pre-avivo */
radeon_div(uint64_t n,uint32_t d)866 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
867 {
868 uint64_t mod;
869
870 n += d / 2;
871
872 mod = do_div(n, d);
873 return n;
874 }
875
radeon_compute_pll_legacy(struct radeon_pll * pll,uint64_t freq,uint32_t * dot_clock_p,uint32_t * fb_div_p,uint32_t * frac_fb_div_p,uint32_t * ref_div_p,uint32_t * post_div_p)876 void radeon_compute_pll_legacy(struct radeon_pll *pll,
877 uint64_t freq,
878 uint32_t *dot_clock_p,
879 uint32_t *fb_div_p,
880 uint32_t *frac_fb_div_p,
881 uint32_t *ref_div_p,
882 uint32_t *post_div_p)
883 {
884 uint32_t min_ref_div = pll->min_ref_div;
885 uint32_t max_ref_div = pll->max_ref_div;
886 uint32_t min_post_div = pll->min_post_div;
887 uint32_t max_post_div = pll->max_post_div;
888 uint32_t min_fractional_feed_div = 0;
889 uint32_t max_fractional_feed_div = 0;
890 uint32_t best_vco = pll->best_vco;
891 uint32_t best_post_div = 1;
892 uint32_t best_ref_div = 1;
893 uint32_t best_feedback_div = 1;
894 uint32_t best_frac_feedback_div = 0;
895 uint32_t best_freq = -1;
896 uint32_t best_error = 0xffffffff;
897 uint32_t best_vco_diff = 1;
898 uint32_t post_div;
899 u32 pll_out_min, pll_out_max;
900
901 DRM_DEBUG_KMS("PLL freq %ju %u %u\n", (uintmax_t)freq, pll->min_ref_div, pll->max_ref_div);
902 freq = freq * 1000;
903
904 if (pll->flags & RADEON_PLL_IS_LCD) {
905 pll_out_min = pll->lcd_pll_out_min;
906 pll_out_max = pll->lcd_pll_out_max;
907 } else {
908 pll_out_min = pll->pll_out_min;
909 pll_out_max = pll->pll_out_max;
910 }
911
912 if (pll_out_min > 64800)
913 pll_out_min = 64800;
914
915 if (pll->flags & RADEON_PLL_USE_REF_DIV)
916 min_ref_div = max_ref_div = pll->reference_div;
917 else {
918 while (min_ref_div < max_ref_div-1) {
919 uint32_t mid = (min_ref_div + max_ref_div) / 2;
920 uint32_t pll_in = pll->reference_freq / mid;
921 if (pll_in < pll->pll_in_min)
922 max_ref_div = mid;
923 else if (pll_in > pll->pll_in_max)
924 min_ref_div = mid;
925 else
926 break;
927 }
928 }
929
930 if (pll->flags & RADEON_PLL_USE_POST_DIV)
931 min_post_div = max_post_div = pll->post_div;
932
933 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
934 min_fractional_feed_div = pll->min_frac_feedback_div;
935 max_fractional_feed_div = pll->max_frac_feedback_div;
936 }
937
938 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
939 uint32_t ref_div;
940
941 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
942 continue;
943
944 /* legacy radeons only have a few post_divs */
945 if (pll->flags & RADEON_PLL_LEGACY) {
946 if ((post_div == 5) ||
947 (post_div == 7) ||
948 (post_div == 9) ||
949 (post_div == 10) ||
950 (post_div == 11) ||
951 (post_div == 13) ||
952 (post_div == 14) ||
953 (post_div == 15))
954 continue;
955 }
956
957 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
958 uint32_t feedback_div, current_freq = 0, error, vco_diff;
959 uint32_t pll_in = pll->reference_freq / ref_div;
960 uint32_t min_feed_div = pll->min_feedback_div;
961 uint32_t max_feed_div = pll->max_feedback_div + 1;
962
963 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
964 continue;
965
966 while (min_feed_div < max_feed_div) {
967 uint32_t vco;
968 uint32_t min_frac_feed_div = min_fractional_feed_div;
969 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
970 uint32_t frac_feedback_div;
971 uint64_t tmp;
972
973 feedback_div = (min_feed_div + max_feed_div) / 2;
974
975 tmp = (uint64_t)pll->reference_freq * feedback_div;
976 vco = radeon_div(tmp, ref_div);
977
978 if (vco < pll_out_min) {
979 min_feed_div = feedback_div + 1;
980 continue;
981 } else if (vco > pll_out_max) {
982 max_feed_div = feedback_div;
983 continue;
984 }
985
986 while (min_frac_feed_div < max_frac_feed_div) {
987 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
988 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
989 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
990 current_freq = radeon_div(tmp, ref_div * post_div);
991
992 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
993 if (freq < current_freq)
994 error = 0xffffffff;
995 else
996 error = freq - current_freq;
997 } else
998 error = abs(current_freq - freq);
999 vco_diff = abs(vco - best_vco);
1000
1001 if ((best_vco == 0 && error < best_error) ||
1002 (best_vco != 0 &&
1003 ((best_error > 100 && error < best_error - 100) ||
1004 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1005 best_post_div = post_div;
1006 best_ref_div = ref_div;
1007 best_feedback_div = feedback_div;
1008 best_frac_feedback_div = frac_feedback_div;
1009 best_freq = current_freq;
1010 best_error = error;
1011 best_vco_diff = vco_diff;
1012 } else if (current_freq == freq) {
1013 if (best_freq == -1) {
1014 best_post_div = post_div;
1015 best_ref_div = ref_div;
1016 best_feedback_div = feedback_div;
1017 best_frac_feedback_div = frac_feedback_div;
1018 best_freq = current_freq;
1019 best_error = error;
1020 best_vco_diff = vco_diff;
1021 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1022 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1023 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1024 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1025 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1026 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1027 best_post_div = post_div;
1028 best_ref_div = ref_div;
1029 best_feedback_div = feedback_div;
1030 best_frac_feedback_div = frac_feedback_div;
1031 best_freq = current_freq;
1032 best_error = error;
1033 best_vco_diff = vco_diff;
1034 }
1035 }
1036 if (current_freq < freq)
1037 min_frac_feed_div = frac_feedback_div + 1;
1038 else
1039 max_frac_feed_div = frac_feedback_div;
1040 }
1041 if (current_freq < freq)
1042 min_feed_div = feedback_div + 1;
1043 else
1044 max_feed_div = feedback_div;
1045 }
1046 }
1047 }
1048
1049 *dot_clock_p = best_freq / 10000;
1050 *fb_div_p = best_feedback_div;
1051 *frac_fb_div_p = best_frac_feedback_div;
1052 *ref_div_p = best_ref_div;
1053 *post_div_p = best_post_div;
1054 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1055 (long long)freq,
1056 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1057 best_ref_div, best_post_div);
1058
1059 }
1060
radeon_user_framebuffer_destroy(struct drm_framebuffer * fb)1061 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1062 {
1063 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1064
1065 if (radeon_fb->obj) {
1066 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1067 }
1068 drm_framebuffer_cleanup(fb);
1069 free(radeon_fb, DRM_MEM_DRIVER);
1070 }
1071
radeon_user_framebuffer_create_handle(struct drm_framebuffer * fb,struct drm_file * file_priv,unsigned int * handle)1072 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1073 struct drm_file *file_priv,
1074 unsigned int *handle)
1075 {
1076 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1077
1078 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1079 }
1080
1081 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1082 .destroy = radeon_user_framebuffer_destroy,
1083 .create_handle = radeon_user_framebuffer_create_handle,
1084 };
1085
1086 int
radeon_framebuffer_init(struct drm_device * dev,struct radeon_framebuffer * rfb,struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object * obj)1087 radeon_framebuffer_init(struct drm_device *dev,
1088 struct radeon_framebuffer *rfb,
1089 struct drm_mode_fb_cmd2 *mode_cmd,
1090 struct drm_gem_object *obj)
1091 {
1092 int ret;
1093 rfb->obj = obj;
1094 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1095 if (ret) {
1096 rfb->obj = NULL;
1097 return ret;
1098 }
1099 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1100 return 0;
1101 }
1102
1103 static int
radeon_user_framebuffer_create(struct drm_device * dev,struct drm_file * file_priv,struct drm_mode_fb_cmd2 * mode_cmd,struct drm_framebuffer ** res)1104 radeon_user_framebuffer_create(struct drm_device *dev,
1105 struct drm_file *file_priv,
1106 struct drm_mode_fb_cmd2 *mode_cmd,
1107 struct drm_framebuffer **res)
1108 {
1109 struct drm_gem_object *obj;
1110 struct radeon_framebuffer *radeon_fb;
1111 int ret;
1112
1113 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1114 if (obj == NULL) {
1115 dev_err(dev->dev, "No GEM object associated to handle 0x%08X, "
1116 "can't create framebuffer\n", mode_cmd->handles[0]);
1117 return -ENOENT;
1118 }
1119
1120 radeon_fb = malloc(sizeof(*radeon_fb), DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
1121 if (radeon_fb == NULL) {
1122 drm_gem_object_unreference_unlocked(obj);
1123 return (-ENOMEM);
1124 }
1125
1126 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1127 if (ret) {
1128 free(radeon_fb, DRM_MEM_DRIVER);
1129 drm_gem_object_unreference_unlocked(obj);
1130 return ret;
1131 }
1132
1133 *res = &radeon_fb->base;
1134 return 0;
1135 }
1136
radeon_output_poll_changed(struct drm_device * dev)1137 static void radeon_output_poll_changed(struct drm_device *dev)
1138 {
1139 struct radeon_device *rdev = dev->dev_private;
1140 radeon_fb_output_poll_changed(rdev);
1141 }
1142
1143 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1144 .fb_create = radeon_user_framebuffer_create,
1145 .output_poll_changed = radeon_output_poll_changed
1146 };
1147
1148 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1149 { { 0, "driver" },
1150 { 1, "bios" },
1151 };
1152
1153 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1154 { { TV_STD_NTSC, "ntsc" },
1155 { TV_STD_PAL, "pal" },
1156 { TV_STD_PAL_M, "pal-m" },
1157 { TV_STD_PAL_60, "pal-60" },
1158 { TV_STD_NTSC_J, "ntsc-j" },
1159 { TV_STD_SCART_PAL, "scart-pal" },
1160 { TV_STD_PAL_CN, "pal-cn" },
1161 { TV_STD_SECAM, "secam" },
1162 };
1163
1164 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1165 { { UNDERSCAN_OFF, "off" },
1166 { UNDERSCAN_ON, "on" },
1167 { UNDERSCAN_AUTO, "auto" },
1168 };
1169
radeon_modeset_create_props(struct radeon_device * rdev)1170 static int radeon_modeset_create_props(struct radeon_device *rdev)
1171 {
1172 int sz;
1173
1174 if (rdev->is_atom_bios) {
1175 rdev->mode_info.coherent_mode_property =
1176 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1177 if (!rdev->mode_info.coherent_mode_property)
1178 return -ENOMEM;
1179 }
1180
1181 if (!ASIC_IS_AVIVO(rdev)) {
1182 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1183 rdev->mode_info.tmds_pll_property =
1184 drm_property_create_enum(rdev->ddev, 0,
1185 "tmds_pll",
1186 radeon_tmds_pll_enum_list, sz);
1187 }
1188
1189 rdev->mode_info.load_detect_property =
1190 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1191 if (!rdev->mode_info.load_detect_property)
1192 return -ENOMEM;
1193
1194 drm_mode_create_scaling_mode_property(rdev->ddev);
1195
1196 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1197 rdev->mode_info.tv_std_property =
1198 drm_property_create_enum(rdev->ddev, 0,
1199 "tv standard",
1200 radeon_tv_std_enum_list, sz);
1201
1202 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1203 rdev->mode_info.underscan_property =
1204 drm_property_create_enum(rdev->ddev, 0,
1205 "underscan",
1206 radeon_underscan_enum_list, sz);
1207
1208 rdev->mode_info.underscan_hborder_property =
1209 drm_property_create_range(rdev->ddev, 0,
1210 "underscan hborder", 0, 128);
1211 if (!rdev->mode_info.underscan_hborder_property)
1212 return -ENOMEM;
1213
1214 rdev->mode_info.underscan_vborder_property =
1215 drm_property_create_range(rdev->ddev, 0,
1216 "underscan vborder", 0, 128);
1217 if (!rdev->mode_info.underscan_vborder_property)
1218 return -ENOMEM;
1219
1220 return 0;
1221 }
1222
radeon_update_display_priority(struct radeon_device * rdev)1223 void radeon_update_display_priority(struct radeon_device *rdev)
1224 {
1225 /* adjustment options for the display watermarks */
1226 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1227 /* set display priority to high for r3xx, rv515 chips
1228 * this avoids flickering due to underflow to the
1229 * display controllers during heavy acceleration.
1230 * Don't force high on rs4xx igp chips as it seems to
1231 * affect the sound card. See kernel bug 15982.
1232 */
1233 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1234 !(rdev->flags & RADEON_IS_IGP))
1235 rdev->disp_priority = 2;
1236 else
1237 rdev->disp_priority = 0;
1238 } else
1239 rdev->disp_priority = radeon_disp_priority;
1240
1241 }
1242
1243 /*
1244 * Allocate hdmi structs and determine register offsets
1245 */
radeon_afmt_init(struct radeon_device * rdev)1246 static void radeon_afmt_init(struct radeon_device *rdev)
1247 {
1248 int i;
1249
1250 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1251 rdev->mode_info.afmt[i] = NULL;
1252
1253 if (ASIC_IS_DCE6(rdev)) {
1254 /* todo */
1255 } else if (ASIC_IS_DCE4(rdev)) {
1256 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1257 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1258 rdev->mode_info.afmt[0] = malloc(sizeof(struct radeon_afmt),
1259 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
1260 if (rdev->mode_info.afmt[0]) {
1261 rdev->mode_info.afmt[0]->offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1262 rdev->mode_info.afmt[0]->id = 0;
1263 }
1264 rdev->mode_info.afmt[1] = malloc(sizeof(struct radeon_afmt),
1265 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
1266 if (rdev->mode_info.afmt[1]) {
1267 rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1268 rdev->mode_info.afmt[1]->id = 1;
1269 }
1270 if (!ASIC_IS_DCE41(rdev)) {
1271 rdev->mode_info.afmt[2] = malloc(sizeof(struct radeon_afmt),
1272 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
1273 if (rdev->mode_info.afmt[2]) {
1274 rdev->mode_info.afmt[2]->offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1275 rdev->mode_info.afmt[2]->id = 2;
1276 }
1277 rdev->mode_info.afmt[3] = malloc(sizeof(struct radeon_afmt),
1278 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
1279 if (rdev->mode_info.afmt[3]) {
1280 rdev->mode_info.afmt[3]->offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1281 rdev->mode_info.afmt[3]->id = 3;
1282 }
1283 rdev->mode_info.afmt[4] = malloc(sizeof(struct radeon_afmt),
1284 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
1285 if (rdev->mode_info.afmt[4]) {
1286 rdev->mode_info.afmt[4]->offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1287 rdev->mode_info.afmt[4]->id = 4;
1288 }
1289 rdev->mode_info.afmt[5] = malloc(sizeof(struct radeon_afmt),
1290 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
1291 if (rdev->mode_info.afmt[5]) {
1292 rdev->mode_info.afmt[5]->offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1293 rdev->mode_info.afmt[5]->id = 5;
1294 }
1295 }
1296 } else if (ASIC_IS_DCE3(rdev)) {
1297 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1298 rdev->mode_info.afmt[0] = malloc(sizeof(struct radeon_afmt),
1299 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
1300 if (rdev->mode_info.afmt[0]) {
1301 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1302 rdev->mode_info.afmt[0]->id = 0;
1303 }
1304 rdev->mode_info.afmt[1] = malloc(sizeof(struct radeon_afmt),
1305 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
1306 if (rdev->mode_info.afmt[1]) {
1307 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1308 rdev->mode_info.afmt[1]->id = 1;
1309 }
1310 } else if (ASIC_IS_DCE2(rdev)) {
1311 /* DCE2 has at least 1 routable audio block */
1312 rdev->mode_info.afmt[0] = malloc(sizeof(struct radeon_afmt),
1313 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
1314 if (rdev->mode_info.afmt[0]) {
1315 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1316 rdev->mode_info.afmt[0]->id = 0;
1317 }
1318 /* r6xx has 2 routable audio blocks */
1319 if (rdev->family >= CHIP_R600) {
1320 rdev->mode_info.afmt[1] = malloc(sizeof(struct radeon_afmt),
1321 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
1322 if (rdev->mode_info.afmt[1]) {
1323 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1324 rdev->mode_info.afmt[1]->id = 1;
1325 }
1326 }
1327 }
1328 }
1329
radeon_afmt_fini(struct radeon_device * rdev)1330 static void radeon_afmt_fini(struct radeon_device *rdev)
1331 {
1332 int i;
1333
1334 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1335 free(rdev->mode_info.afmt[i], DRM_MEM_DRIVER);
1336 rdev->mode_info.afmt[i] = NULL;
1337 }
1338 }
1339
radeon_modeset_init(struct radeon_device * rdev)1340 int radeon_modeset_init(struct radeon_device *rdev)
1341 {
1342 int i;
1343 int ret;
1344
1345 drm_mode_config_init(rdev->ddev);
1346 rdev->mode_info.mode_config_initialized = true;
1347
1348 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1349
1350 if (ASIC_IS_DCE5(rdev)) {
1351 rdev->ddev->mode_config.max_width = 16384;
1352 rdev->ddev->mode_config.max_height = 16384;
1353 } else if (ASIC_IS_AVIVO(rdev)) {
1354 rdev->ddev->mode_config.max_width = 8192;
1355 rdev->ddev->mode_config.max_height = 8192;
1356 } else {
1357 rdev->ddev->mode_config.max_width = 4096;
1358 rdev->ddev->mode_config.max_height = 4096;
1359 }
1360
1361 rdev->ddev->mode_config.preferred_depth = 24;
1362 rdev->ddev->mode_config.prefer_shadow = 1;
1363
1364 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1365
1366 ret = radeon_modeset_create_props(rdev);
1367 if (ret) {
1368 return ret;
1369 }
1370
1371 /* init i2c buses */
1372 radeon_i2c_init(rdev);
1373
1374 /* check combios for a valid hardcoded EDID - Sun servers */
1375 if (!rdev->is_atom_bios) {
1376 /* check for hardcoded EDID in BIOS */
1377 radeon_combios_check_hardcoded_edid(rdev);
1378 }
1379
1380 /* allocate crtcs */
1381 for (i = 0; i < rdev->num_crtc; i++) {
1382 radeon_crtc_init(rdev->ddev, i);
1383 }
1384
1385 /* okay we should have all the bios connectors */
1386 ret = radeon_setup_enc_conn(rdev->ddev);
1387 if (!ret) {
1388 return ret;
1389 }
1390
1391 /* init dig PHYs, disp eng pll */
1392 if (rdev->is_atom_bios) {
1393 radeon_atom_encoder_init(rdev);
1394 radeon_atom_disp_eng_pll_init(rdev);
1395 }
1396
1397 /* initialize hpd */
1398 radeon_hpd_init(rdev);
1399
1400 /* setup afmt */
1401 radeon_afmt_init(rdev);
1402
1403 /* Initialize power management */
1404 radeon_pm_init(rdev);
1405
1406 radeon_fbdev_init(rdev);
1407 drm_kms_helper_poll_init(rdev->ddev);
1408
1409 return 0;
1410 }
1411
radeon_modeset_fini(struct radeon_device * rdev)1412 void radeon_modeset_fini(struct radeon_device *rdev)
1413 {
1414 radeon_fbdev_fini(rdev);
1415 free(rdev->mode_info.bios_hardcoded_edid, DRM_MEM_KMS);
1416 radeon_pm_fini(rdev);
1417
1418 if (rdev->mode_info.mode_config_initialized) {
1419 radeon_afmt_fini(rdev);
1420 drm_kms_helper_poll_fini(rdev->ddev);
1421 radeon_hpd_fini(rdev);
1422 drm_mode_config_cleanup(rdev->ddev);
1423 rdev->mode_info.mode_config_initialized = false;
1424 }
1425 /* free i2c buses */
1426 radeon_i2c_fini(rdev);
1427 }
1428
is_hdtv_mode(const struct drm_display_mode * mode)1429 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1430 {
1431 /* try and guess if this is a tv or a monitor */
1432 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1433 (mode->vdisplay == 576) || /* 576p */
1434 (mode->vdisplay == 720) || /* 720p */
1435 (mode->vdisplay == 1080)) /* 1080p */
1436 return true;
1437 else
1438 return false;
1439 }
1440
radeon_crtc_scaling_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1441 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1442 const struct drm_display_mode *mode,
1443 struct drm_display_mode *adjusted_mode)
1444 {
1445 struct drm_device *dev = crtc->dev;
1446 struct radeon_device *rdev = dev->dev_private;
1447 struct drm_encoder *encoder;
1448 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1449 struct radeon_encoder *radeon_encoder;
1450 struct drm_connector *connector;
1451 struct radeon_connector *radeon_connector;
1452 bool first = true;
1453 u32 src_v = 1, dst_v = 1;
1454 u32 src_h = 1, dst_h = 1;
1455
1456 radeon_crtc->h_border = 0;
1457 radeon_crtc->v_border = 0;
1458
1459 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1460 if (encoder->crtc != crtc)
1461 continue;
1462 radeon_encoder = to_radeon_encoder(encoder);
1463 connector = radeon_get_connector_for_encoder(encoder);
1464 radeon_connector = to_radeon_connector(connector);
1465
1466 if (first) {
1467 /* set scaling */
1468 if (radeon_encoder->rmx_type == RMX_OFF)
1469 radeon_crtc->rmx_type = RMX_OFF;
1470 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1471 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1472 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1473 else
1474 radeon_crtc->rmx_type = RMX_OFF;
1475 /* copy native mode */
1476 memcpy(&radeon_crtc->native_mode,
1477 &radeon_encoder->native_mode,
1478 sizeof(struct drm_display_mode));
1479 src_v = crtc->mode.vdisplay;
1480 dst_v = radeon_crtc->native_mode.vdisplay;
1481 src_h = crtc->mode.hdisplay;
1482 dst_h = radeon_crtc->native_mode.hdisplay;
1483
1484 /* fix up for overscan on hdmi */
1485 if (ASIC_IS_AVIVO(rdev) &&
1486 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1487 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1488 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1489 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1490 is_hdtv_mode(mode)))) {
1491 if (radeon_encoder->underscan_hborder != 0)
1492 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1493 else
1494 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1495 if (radeon_encoder->underscan_vborder != 0)
1496 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1497 else
1498 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1499 radeon_crtc->rmx_type = RMX_FULL;
1500 src_v = crtc->mode.vdisplay;
1501 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1502 src_h = crtc->mode.hdisplay;
1503 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1504 }
1505 first = false;
1506 } else {
1507 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1508 /* WARNING: Right now this can't happen but
1509 * in the future we need to check that scaling
1510 * are consistent across different encoder
1511 * (ie all encoder can work with the same
1512 * scaling).
1513 */
1514 DRM_ERROR("Scaling not consistent across encoder.\n");
1515 return false;
1516 }
1517 }
1518 }
1519 if (radeon_crtc->rmx_type != RMX_OFF) {
1520 fixed20_12 a, b;
1521 a.full = dfixed_const(src_v);
1522 b.full = dfixed_const(dst_v);
1523 radeon_crtc->vsc.full = dfixed_div(a, b);
1524 a.full = dfixed_const(src_h);
1525 b.full = dfixed_const(dst_h);
1526 radeon_crtc->hsc.full = dfixed_div(a, b);
1527 } else {
1528 radeon_crtc->vsc.full = dfixed_const(1);
1529 radeon_crtc->hsc.full = dfixed_const(1);
1530 }
1531 return true;
1532 }
1533
1534 /*
1535 * Retrieve current video scanout position of crtc on a given gpu.
1536 *
1537 * \param dev Device to query.
1538 * \param crtc Crtc to query.
1539 * \param *vpos Location where vertical scanout position should be stored.
1540 * \param *hpos Location where horizontal scanout position should go.
1541 *
1542 * Returns vpos as a positive number while in active scanout area.
1543 * Returns vpos as a negative number inside vblank, counting the number
1544 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1545 * until start of active scanout / end of vblank."
1546 *
1547 * \return Flags, or'ed together as follows:
1548 *
1549 * DRM_SCANOUTPOS_VALID = Query successful.
1550 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1551 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1552 * this flag means that returned position may be offset by a constant but
1553 * unknown small number of scanlines wrt. real scanout position.
1554 *
1555 */
radeon_get_crtc_scanoutpos(struct drm_device * dev,int crtc,int * vpos,int * hpos)1556 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)
1557 {
1558 u32 stat_crtc = 0, vbl = 0, position = 0;
1559 int vbl_start, vbl_end, vtotal, ret = 0;
1560 bool in_vbl = true;
1561
1562 struct radeon_device *rdev = dev->dev_private;
1563
1564 if (ASIC_IS_DCE4(rdev)) {
1565 if (crtc == 0) {
1566 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1567 EVERGREEN_CRTC0_REGISTER_OFFSET);
1568 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1569 EVERGREEN_CRTC0_REGISTER_OFFSET);
1570 ret |= DRM_SCANOUTPOS_VALID;
1571 }
1572 if (crtc == 1) {
1573 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1574 EVERGREEN_CRTC1_REGISTER_OFFSET);
1575 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1576 EVERGREEN_CRTC1_REGISTER_OFFSET);
1577 ret |= DRM_SCANOUTPOS_VALID;
1578 }
1579 if (crtc == 2) {
1580 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1581 EVERGREEN_CRTC2_REGISTER_OFFSET);
1582 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1583 EVERGREEN_CRTC2_REGISTER_OFFSET);
1584 ret |= DRM_SCANOUTPOS_VALID;
1585 }
1586 if (crtc == 3) {
1587 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1588 EVERGREEN_CRTC3_REGISTER_OFFSET);
1589 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1590 EVERGREEN_CRTC3_REGISTER_OFFSET);
1591 ret |= DRM_SCANOUTPOS_VALID;
1592 }
1593 if (crtc == 4) {
1594 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1595 EVERGREEN_CRTC4_REGISTER_OFFSET);
1596 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1597 EVERGREEN_CRTC4_REGISTER_OFFSET);
1598 ret |= DRM_SCANOUTPOS_VALID;
1599 }
1600 if (crtc == 5) {
1601 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1602 EVERGREEN_CRTC5_REGISTER_OFFSET);
1603 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1604 EVERGREEN_CRTC5_REGISTER_OFFSET);
1605 ret |= DRM_SCANOUTPOS_VALID;
1606 }
1607 } else if (ASIC_IS_AVIVO(rdev)) {
1608 if (crtc == 0) {
1609 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1610 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1611 ret |= DRM_SCANOUTPOS_VALID;
1612 }
1613 if (crtc == 1) {
1614 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1615 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1616 ret |= DRM_SCANOUTPOS_VALID;
1617 }
1618 } else {
1619 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1620 if (crtc == 0) {
1621 /* Assume vbl_end == 0, get vbl_start from
1622 * upper 16 bits.
1623 */
1624 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1625 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1626 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1627 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1628 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1629 if (!(stat_crtc & 1))
1630 in_vbl = false;
1631
1632 ret |= DRM_SCANOUTPOS_VALID;
1633 }
1634 if (crtc == 1) {
1635 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1636 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1637 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1638 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1639 if (!(stat_crtc & 1))
1640 in_vbl = false;
1641
1642 ret |= DRM_SCANOUTPOS_VALID;
1643 }
1644 }
1645
1646 /* Decode into vertical and horizontal scanout position. */
1647 *vpos = position & 0x1fff;
1648 *hpos = (position >> 16) & 0x1fff;
1649
1650 /* Valid vblank area boundaries from gpu retrieved? */
1651 if (vbl > 0) {
1652 /* Yes: Decode. */
1653 ret |= DRM_SCANOUTPOS_ACCURATE;
1654 vbl_start = vbl & 0x1fff;
1655 vbl_end = (vbl >> 16) & 0x1fff;
1656 }
1657 else {
1658 /* No: Fake something reasonable which gives at least ok results. */
1659 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1660 vbl_end = 0;
1661 }
1662
1663 /* Test scanout position against vblank region. */
1664 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1665 in_vbl = false;
1666
1667 /* Check if inside vblank area and apply corrective offsets:
1668 * vpos will then be >=0 in video scanout area, but negative
1669 * within vblank area, counting down the number of lines until
1670 * start of scanout.
1671 */
1672
1673 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1674 if (in_vbl && (*vpos >= vbl_start)) {
1675 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1676 *vpos = *vpos - vtotal;
1677 }
1678
1679 /* Correct for shifted end of vbl at vbl_end. */
1680 *vpos = *vpos - vbl_end;
1681
1682 /* In vblank? */
1683 if (in_vbl)
1684 ret |= DRM_SCANOUTPOS_INVBL;
1685
1686 return ret;
1687 }
1688