1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <linux/pci.h>
28
29 #include <drm/drm_device.h>
30 #include <drm/drm_edid.h>
31 #include <drm/radeon_drm.h>
32
33 #include "radeon.h"
34
35 #include "atom.h"
36 #include "atom-bits.h"
37 #include "radeon_asic.h"
38 #include "radeon_atombios.h"
39 #include "radeon_legacy_encoders.h"
40
41 union atom_supported_devices {
42 struct _ATOM_SUPPORTED_DEVICES_INFO info;
43 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
44 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
45 };
46
radeon_lookup_i2c_gpio_quirks(struct radeon_device * rdev,ATOM_GPIO_I2C_ASSIGMENT * gpio,u8 index)47 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
48 ATOM_GPIO_I2C_ASSIGMENT *gpio,
49 u8 index)
50 {
51 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
52 if ((rdev->family == CHIP_R420) ||
53 (rdev->family == CHIP_R423) ||
54 (rdev->family == CHIP_RV410)) {
55 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
56 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
57 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
58 gpio->ucClkMaskShift = 0x19;
59 gpio->ucDataMaskShift = 0x18;
60 }
61 }
62
63 /* some evergreen boards have bad data for this entry */
64 if (ASIC_IS_DCE4(rdev)) {
65 if ((index == 7) &&
66 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
67 (gpio->sucI2cId.ucAccess == 0)) {
68 gpio->sucI2cId.ucAccess = 0x97;
69 gpio->ucDataMaskShift = 8;
70 gpio->ucDataEnShift = 8;
71 gpio->ucDataY_Shift = 8;
72 gpio->ucDataA_Shift = 8;
73 }
74 }
75
76 /* some DCE3 boards have bad data for this entry */
77 if (ASIC_IS_DCE3(rdev)) {
78 if ((index == 4) &&
79 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
80 (gpio->sucI2cId.ucAccess == 0x94))
81 gpio->sucI2cId.ucAccess = 0x14;
82 }
83 }
84
radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT * gpio)85 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
86 {
87 struct radeon_i2c_bus_rec i2c;
88
89 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
90
91 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
92 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
93 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
94 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
95 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
96 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
97 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
98 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
99 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
100 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
101 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
102 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
103 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
104 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
105 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
106 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
107
108 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
109 i2c.hw_capable = true;
110 else
111 i2c.hw_capable = false;
112
113 if (gpio->sucI2cId.ucAccess == 0xa0)
114 i2c.mm_i2c = true;
115 else
116 i2c.mm_i2c = false;
117
118 i2c.i2c_id = gpio->sucI2cId.ucAccess;
119
120 if (i2c.mask_clk_reg)
121 i2c.valid = true;
122 else
123 i2c.valid = false;
124
125 return i2c;
126 }
127
radeon_lookup_i2c_gpio(struct radeon_device * rdev,uint8_t id)128 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
129 uint8_t id)
130 {
131 struct atom_context *ctx = rdev->mode_info.atom_context;
132 ATOM_GPIO_I2C_ASSIGMENT *gpio;
133 struct radeon_i2c_bus_rec i2c;
134 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
135 struct _ATOM_GPIO_I2C_INFO *i2c_info;
136 uint16_t data_offset, size;
137 int i, num_indices;
138
139 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
140 i2c.valid = false;
141
142 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
143 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
144
145 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
146 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
147
148 gpio = &i2c_info->asGPIO_Info[0];
149 for (i = 0; i < num_indices; i++) {
150
151 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
152
153 if (gpio->sucI2cId.ucAccess == id) {
154 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
155 break;
156 }
157 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
158 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
159 }
160 }
161
162 return i2c;
163 }
164
radeon_atombios_i2c_init(struct radeon_device * rdev)165 void radeon_atombios_i2c_init(struct radeon_device *rdev)
166 {
167 struct atom_context *ctx = rdev->mode_info.atom_context;
168 ATOM_GPIO_I2C_ASSIGMENT *gpio;
169 struct radeon_i2c_bus_rec i2c;
170 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
171 struct _ATOM_GPIO_I2C_INFO *i2c_info;
172 uint16_t data_offset, size;
173 int i, num_indices;
174 char stmp[32];
175
176 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
177 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
178
179 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
180 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
181
182 gpio = &i2c_info->asGPIO_Info[0];
183 for (i = 0; i < num_indices; i++) {
184 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
185
186 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
187
188 if (i2c.valid) {
189 snprintf(stmp, sizeof(stmp), "0x%x", i2c.i2c_id);
190 rdev->i2c_bus[i] = radeon_i2c_create(rdev_to_drm(rdev), &i2c, stmp);
191 }
192 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
193 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
194 }
195 }
196 }
197
radeon_atombios_lookup_gpio(struct radeon_device * rdev,u8 id)198 struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
199 u8 id)
200 {
201 struct atom_context *ctx = rdev->mode_info.atom_context;
202 struct radeon_gpio_rec gpio;
203 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
204 struct _ATOM_GPIO_PIN_LUT *gpio_info;
205 ATOM_GPIO_PIN_ASSIGNMENT *pin;
206 u16 data_offset, size;
207 int i, num_indices;
208
209 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
210 gpio.valid = false;
211
212 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
213 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
214
215 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
216 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
217
218 pin = gpio_info->asGPIO_Pin;
219 for (i = 0; i < num_indices; i++) {
220 if (id == pin->ucGPIO_ID) {
221 gpio.id = pin->ucGPIO_ID;
222 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
223 gpio.shift = pin->ucGpioPinBitShift;
224 gpio.mask = (1 << pin->ucGpioPinBitShift);
225 gpio.valid = true;
226 break;
227 }
228 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
229 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
230 }
231 }
232
233 return gpio;
234 }
235
radeon_atom_get_hpd_info_from_gpio(struct radeon_device * rdev,struct radeon_gpio_rec * gpio)236 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
237 struct radeon_gpio_rec *gpio)
238 {
239 struct radeon_hpd hpd;
240 u32 reg;
241
242 memset(&hpd, 0, sizeof(struct radeon_hpd));
243
244 if (ASIC_IS_DCE6(rdev))
245 reg = SI_DC_GPIO_HPD_A;
246 else if (ASIC_IS_DCE4(rdev))
247 reg = EVERGREEN_DC_GPIO_HPD_A;
248 else
249 reg = AVIVO_DC_GPIO_HPD_A;
250
251 hpd.gpio = *gpio;
252 if (gpio->reg == reg) {
253 switch(gpio->mask) {
254 case (1 << 0):
255 hpd.hpd = RADEON_HPD_1;
256 break;
257 case (1 << 8):
258 hpd.hpd = RADEON_HPD_2;
259 break;
260 case (1 << 16):
261 hpd.hpd = RADEON_HPD_3;
262 break;
263 case (1 << 24):
264 hpd.hpd = RADEON_HPD_4;
265 break;
266 case (1 << 26):
267 hpd.hpd = RADEON_HPD_5;
268 break;
269 case (1 << 28):
270 hpd.hpd = RADEON_HPD_6;
271 break;
272 default:
273 hpd.hpd = RADEON_HPD_NONE;
274 break;
275 }
276 } else
277 hpd.hpd = RADEON_HPD_NONE;
278 return hpd;
279 }
280
radeon_atom_apply_quirks(struct drm_device * dev,uint32_t supported_device,int * connector_type,struct radeon_i2c_bus_rec * i2c_bus,uint16_t * line_mux,struct radeon_hpd * hpd)281 static bool radeon_atom_apply_quirks(struct drm_device *dev,
282 uint32_t supported_device,
283 int *connector_type,
284 struct radeon_i2c_bus_rec *i2c_bus,
285 uint16_t *line_mux,
286 struct radeon_hpd *hpd)
287 {
288 #ifdef __linux__
289 struct pci_dev *pdev = to_pci_dev(dev->dev);
290 #else
291 struct pci_dev *pdev = dev->pdev;
292 #endif
293
294 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
295 if ((pdev->device == 0x791e) &&
296 (pdev->subsystem_vendor == 0x1043) &&
297 (pdev->subsystem_device == 0x826d)) {
298 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
299 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
300 *connector_type = DRM_MODE_CONNECTOR_DVID;
301 }
302
303 /* Asrock RS600 board lists the DVI port as HDMI */
304 if ((pdev->device == 0x7941) &&
305 (pdev->subsystem_vendor == 0x1849) &&
306 (pdev->subsystem_device == 0x7941)) {
307 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
308 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
309 *connector_type = DRM_MODE_CONNECTOR_DVID;
310 }
311
312 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
313 if ((pdev->device == 0x796e) &&
314 (pdev->subsystem_vendor == 0x1462) &&
315 (pdev->subsystem_device == 0x7302)) {
316 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
317 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
318 return false;
319 }
320
321 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
322 if ((pdev->device == 0x7941) &&
323 (pdev->subsystem_vendor == 0x147b) &&
324 (pdev->subsystem_device == 0x2412)) {
325 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
326 return false;
327 }
328
329 /* Falcon NW laptop lists vga ddc line for LVDS */
330 if ((pdev->device == 0x5653) &&
331 (pdev->subsystem_vendor == 0x1462) &&
332 (pdev->subsystem_device == 0x0291)) {
333 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
334 i2c_bus->valid = false;
335 *line_mux = 53;
336 }
337 }
338
339 /* HIS X1300 is DVI+VGA, not DVI+DVI */
340 if ((pdev->device == 0x7146) &&
341 (pdev->subsystem_vendor == 0x17af) &&
342 (pdev->subsystem_device == 0x2058)) {
343 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
344 return false;
345 }
346
347 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
348 if ((pdev->device == 0x7142) &&
349 (pdev->subsystem_vendor == 0x1458) &&
350 (pdev->subsystem_device == 0x2134)) {
351 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
352 return false;
353 }
354
355
356 /* Funky macbooks */
357 if ((pdev->device == 0x71C5) &&
358 (pdev->subsystem_vendor == 0x106b) &&
359 (pdev->subsystem_device == 0x0080)) {
360 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
361 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
362 return false;
363 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
364 *line_mux = 0x90;
365 }
366
367 /* mac rv630, rv730, others */
368 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
369 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
370 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
371 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
372 }
373
374 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
375 if ((pdev->device == 0x9598) &&
376 (pdev->subsystem_vendor == 0x1043) &&
377 (pdev->subsystem_device == 0x01da)) {
378 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
379 *connector_type = DRM_MODE_CONNECTOR_DVII;
380 }
381 }
382
383 /* ASUS HD 3600 board lists the DVI port as HDMI */
384 if ((pdev->device == 0x9598) &&
385 (pdev->subsystem_vendor == 0x1043) &&
386 (pdev->subsystem_device == 0x01e4)) {
387 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
388 *connector_type = DRM_MODE_CONNECTOR_DVII;
389 }
390 }
391
392 /* ASUS HD 3450 board lists the DVI port as HDMI */
393 if ((pdev->device == 0x95C5) &&
394 (pdev->subsystem_vendor == 0x1043) &&
395 (pdev->subsystem_device == 0x01e2)) {
396 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
397 *connector_type = DRM_MODE_CONNECTOR_DVII;
398 }
399 }
400
401 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
402 * HDMI + VGA reporting as HDMI
403 */
404 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
405 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
406 *connector_type = DRM_MODE_CONNECTOR_VGA;
407 *line_mux = 0;
408 }
409 }
410
411 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
412 * on the laptop and a DVI port on the docking station and
413 * both share the same encoder, hpd pin, and ddc line.
414 * So while the bios table is technically correct,
415 * we drop the DVI port here since xrandr has no concept of
416 * encoders and will try and drive both connectors
417 * with different crtcs which isn't possible on the hardware
418 * side and leaves no crtcs for LVDS or VGA.
419 */
420 if (((pdev->device == 0x95c4) || (pdev->device == 0x9591)) &&
421 (pdev->subsystem_vendor == 0x1025) &&
422 (pdev->subsystem_device == 0x013c)) {
423 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
424 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
425 /* actually it's a DVI-D port not DVI-I */
426 *connector_type = DRM_MODE_CONNECTOR_DVID;
427 return false;
428 }
429 }
430
431 /* XFX Pine Group device rv730 reports no VGA DDC lines
432 * even though they are wired up to record 0x93
433 */
434 if ((pdev->device == 0x9498) &&
435 (pdev->subsystem_vendor == 0x1682) &&
436 (pdev->subsystem_device == 0x2452) &&
437 (i2c_bus->valid == false) &&
438 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
439 struct radeon_device *rdev = dev->dev_private;
440 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
441 }
442
443 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
444 if (((pdev->device == 0x9802) ||
445 (pdev->device == 0x9805) ||
446 (pdev->device == 0x9806)) &&
447 (pdev->subsystem_vendor == 0x1734) &&
448 (pdev->subsystem_device == 0x11bd)) {
449 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
450 *connector_type = DRM_MODE_CONNECTOR_DVII;
451 *line_mux = 0x3103;
452 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
453 *connector_type = DRM_MODE_CONNECTOR_DVII;
454 }
455 }
456
457 return true;
458 }
459
460 static const int supported_devices_connector_convert[] = {
461 DRM_MODE_CONNECTOR_Unknown,
462 DRM_MODE_CONNECTOR_VGA,
463 DRM_MODE_CONNECTOR_DVII,
464 DRM_MODE_CONNECTOR_DVID,
465 DRM_MODE_CONNECTOR_DVIA,
466 DRM_MODE_CONNECTOR_SVIDEO,
467 DRM_MODE_CONNECTOR_Composite,
468 DRM_MODE_CONNECTOR_LVDS,
469 DRM_MODE_CONNECTOR_Unknown,
470 DRM_MODE_CONNECTOR_Unknown,
471 DRM_MODE_CONNECTOR_HDMIA,
472 DRM_MODE_CONNECTOR_HDMIB,
473 DRM_MODE_CONNECTOR_Unknown,
474 DRM_MODE_CONNECTOR_Unknown,
475 DRM_MODE_CONNECTOR_9PinDIN,
476 DRM_MODE_CONNECTOR_DisplayPort
477 };
478
479 static const uint16_t supported_devices_connector_object_id_convert[] = {
480 CONNECTOR_OBJECT_ID_NONE,
481 CONNECTOR_OBJECT_ID_VGA,
482 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
483 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
484 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
485 CONNECTOR_OBJECT_ID_COMPOSITE,
486 CONNECTOR_OBJECT_ID_SVIDEO,
487 CONNECTOR_OBJECT_ID_LVDS,
488 CONNECTOR_OBJECT_ID_9PIN_DIN,
489 CONNECTOR_OBJECT_ID_9PIN_DIN,
490 CONNECTOR_OBJECT_ID_DISPLAYPORT,
491 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
492 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
493 CONNECTOR_OBJECT_ID_SVIDEO
494 };
495
496 static const int object_connector_convert[] = {
497 DRM_MODE_CONNECTOR_Unknown,
498 DRM_MODE_CONNECTOR_DVII,
499 DRM_MODE_CONNECTOR_DVII,
500 DRM_MODE_CONNECTOR_DVID,
501 DRM_MODE_CONNECTOR_DVID,
502 DRM_MODE_CONNECTOR_VGA,
503 DRM_MODE_CONNECTOR_Composite,
504 DRM_MODE_CONNECTOR_SVIDEO,
505 DRM_MODE_CONNECTOR_Unknown,
506 DRM_MODE_CONNECTOR_Unknown,
507 DRM_MODE_CONNECTOR_9PinDIN,
508 DRM_MODE_CONNECTOR_Unknown,
509 DRM_MODE_CONNECTOR_HDMIA,
510 DRM_MODE_CONNECTOR_HDMIB,
511 DRM_MODE_CONNECTOR_LVDS,
512 DRM_MODE_CONNECTOR_9PinDIN,
513 DRM_MODE_CONNECTOR_Unknown,
514 DRM_MODE_CONNECTOR_Unknown,
515 DRM_MODE_CONNECTOR_Unknown,
516 DRM_MODE_CONNECTOR_DisplayPort,
517 DRM_MODE_CONNECTOR_eDP,
518 DRM_MODE_CONNECTOR_Unknown
519 };
520
radeon_get_atom_connector_info_from_object_table(struct drm_device * dev)521 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
522 {
523 struct radeon_device *rdev = dev->dev_private;
524 struct radeon_mode_info *mode_info = &rdev->mode_info;
525 struct atom_context *ctx = mode_info->atom_context;
526 int index = GetIndexIntoMasterTable(DATA, Object_Header);
527 u16 size, data_offset;
528 u8 frev, crev;
529 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
530 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
531 ATOM_OBJECT_TABLE *router_obj;
532 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
533 ATOM_OBJECT_HEADER *obj_header;
534 int i, j, k, path_size, device_support;
535 int connector_type;
536 u16 igp_lane_info, conn_id, connector_object_id;
537 struct radeon_i2c_bus_rec ddc_bus;
538 struct radeon_router router;
539 struct radeon_gpio_rec gpio;
540 struct radeon_hpd hpd;
541
542 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
543 return false;
544
545 if (crev < 2)
546 return false;
547
548 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
549 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
550 (ctx->bios + data_offset +
551 le16_to_cpu(obj_header->usDisplayPathTableOffset));
552 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
553 (ctx->bios + data_offset +
554 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
555 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
556 (ctx->bios + data_offset +
557 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
558 router_obj = (ATOM_OBJECT_TABLE *)
559 (ctx->bios + data_offset +
560 le16_to_cpu(obj_header->usRouterObjectTableOffset));
561 device_support = le16_to_cpu(obj_header->usDeviceSupport);
562
563 path_size = 0;
564 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
565 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
566 ATOM_DISPLAY_OBJECT_PATH *path;
567 addr += path_size;
568 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
569 path_size += le16_to_cpu(path->usSize);
570
571 if (device_support & le16_to_cpu(path->usDeviceTag)) {
572 uint8_t con_obj_id, con_obj_num;
573
574 con_obj_id =
575 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
576 >> OBJECT_ID_SHIFT;
577 con_obj_num =
578 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
579 >> ENUM_ID_SHIFT;
580
581 /* TODO CV support */
582 if (le16_to_cpu(path->usDeviceTag) ==
583 ATOM_DEVICE_CV_SUPPORT)
584 continue;
585
586 /* IGP chips */
587 if ((rdev->flags & RADEON_IS_IGP) &&
588 (con_obj_id ==
589 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
590 uint16_t igp_offset = 0;
591 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
592
593 index =
594 GetIndexIntoMasterTable(DATA,
595 IntegratedSystemInfo);
596
597 if (atom_parse_data_header(ctx, index, &size, &frev,
598 &crev, &igp_offset)) {
599
600 if (crev >= 2) {
601 igp_obj =
602 (ATOM_INTEGRATED_SYSTEM_INFO_V2
603 *) (ctx->bios + igp_offset);
604
605 if (igp_obj) {
606 uint32_t slot_config, ct;
607
608 if (con_obj_num == 1)
609 slot_config =
610 igp_obj->
611 ulDDISlot1Config;
612 else
613 slot_config =
614 igp_obj->
615 ulDDISlot2Config;
616
617 ct = (slot_config >> 16) & 0xff;
618 connector_type =
619 object_connector_convert
620 [ct];
621 connector_object_id = ct;
622 igp_lane_info =
623 slot_config & 0xffff;
624 } else
625 continue;
626 } else
627 continue;
628 } else {
629 igp_lane_info = 0;
630 connector_type =
631 object_connector_convert[con_obj_id];
632 connector_object_id = con_obj_id;
633 }
634 } else {
635 igp_lane_info = 0;
636 connector_type =
637 object_connector_convert[con_obj_id];
638 connector_object_id = con_obj_id;
639 }
640
641 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
642 continue;
643
644 router.ddc_valid = false;
645 router.cd_valid = false;
646 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
647 uint8_t grph_obj_type =
648 (le16_to_cpu(path->usGraphicObjIds[j]) &
649 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
650
651 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
652 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
653 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
654 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
655 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
656 (ctx->bios + data_offset +
657 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
658 ATOM_ENCODER_CAP_RECORD *cap_record;
659 u16 caps = 0;
660
661 while (record->ucRecordSize > 0 &&
662 record->ucRecordType > 0 &&
663 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
664 switch (record->ucRecordType) {
665 case ATOM_ENCODER_CAP_RECORD_TYPE:
666 cap_record =(ATOM_ENCODER_CAP_RECORD *)
667 record;
668 caps = le16_to_cpu(cap_record->usEncoderCap);
669 break;
670 }
671 record = (ATOM_COMMON_RECORD_HEADER *)
672 ((char *)record + record->ucRecordSize);
673 }
674 radeon_add_atom_encoder(dev,
675 encoder_obj,
676 le16_to_cpu
677 (path->
678 usDeviceTag),
679 caps);
680 }
681 }
682 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
683 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
684 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
685 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
686 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
687 (ctx->bios + data_offset +
688 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
689 ATOM_I2C_RECORD *i2c_record;
690 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
691 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
692 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
693 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
694 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
695 (ctx->bios + data_offset +
696 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
697 u8 *num_dst_objs = (u8 *)
698 ((u8 *)router_src_dst_table + 1 +
699 (router_src_dst_table->ucNumberOfSrc * 2));
700 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
701 int enum_id;
702
703 router.router_id = router_obj_id;
704 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
705 if (le16_to_cpu(path->usConnObjectId) ==
706 le16_to_cpu(dst_objs[enum_id]))
707 break;
708 }
709
710 while (record->ucRecordSize > 0 &&
711 record->ucRecordType > 0 &&
712 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
713 switch (record->ucRecordType) {
714 case ATOM_I2C_RECORD_TYPE:
715 i2c_record =
716 (ATOM_I2C_RECORD *)
717 record;
718 i2c_config =
719 (ATOM_I2C_ID_CONFIG_ACCESS *)
720 &i2c_record->sucI2cId;
721 router.i2c_info =
722 radeon_lookup_i2c_gpio(rdev,
723 i2c_config->
724 ucAccess);
725 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
726 break;
727 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
728 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
729 record;
730 router.ddc_valid = true;
731 router.ddc_mux_type = ddc_path->ucMuxType;
732 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
733 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
734 break;
735 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
736 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
737 record;
738 router.cd_valid = true;
739 router.cd_mux_type = cd_path->ucMuxType;
740 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
741 router.cd_mux_state = cd_path->ucMuxState[enum_id];
742 break;
743 }
744 record = (ATOM_COMMON_RECORD_HEADER *)
745 ((char *)record + record->ucRecordSize);
746 }
747 }
748 }
749 }
750 }
751
752 /* look up gpio for ddc, hpd */
753 ddc_bus.valid = false;
754 hpd.hpd = RADEON_HPD_NONE;
755 if ((le16_to_cpu(path->usDeviceTag) &
756 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
757 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
758 if (le16_to_cpu(path->usConnObjectId) ==
759 le16_to_cpu(con_obj->asObjects[j].
760 usObjectID)) {
761 ATOM_COMMON_RECORD_HEADER
762 *record =
763 (ATOM_COMMON_RECORD_HEADER
764 *)
765 (ctx->bios + data_offset +
766 le16_to_cpu(con_obj->
767 asObjects[j].
768 usRecordOffset));
769 ATOM_I2C_RECORD *i2c_record;
770 ATOM_HPD_INT_RECORD *hpd_record;
771 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
772
773 while (record->ucRecordSize > 0 &&
774 record->ucRecordType > 0 &&
775 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
776 switch (record->ucRecordType) {
777 case ATOM_I2C_RECORD_TYPE:
778 i2c_record =
779 (ATOM_I2C_RECORD *)
780 record;
781 i2c_config =
782 (ATOM_I2C_ID_CONFIG_ACCESS *)
783 &i2c_record->sucI2cId;
784 ddc_bus = radeon_lookup_i2c_gpio(rdev,
785 i2c_config->
786 ucAccess);
787 break;
788 case ATOM_HPD_INT_RECORD_TYPE:
789 hpd_record =
790 (ATOM_HPD_INT_RECORD *)
791 record;
792 gpio = radeon_atombios_lookup_gpio(rdev,
793 hpd_record->ucHPDIntGPIOID);
794 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
795 hpd.plugged_state = hpd_record->ucPlugged_PinState;
796 break;
797 }
798 record =
799 (ATOM_COMMON_RECORD_HEADER
800 *) ((char *)record
801 +
802 record->
803 ucRecordSize);
804 }
805 break;
806 }
807 }
808 }
809
810 /* needed for aux chan transactions */
811 ddc_bus.hpd = hpd.hpd;
812
813 conn_id = le16_to_cpu(path->usConnObjectId);
814
815 if (!radeon_atom_apply_quirks
816 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
817 &ddc_bus, &conn_id, &hpd))
818 continue;
819
820 radeon_add_atom_connector(dev,
821 conn_id,
822 le16_to_cpu(path->
823 usDeviceTag),
824 connector_type, &ddc_bus,
825 igp_lane_info,
826 connector_object_id,
827 &hpd,
828 &router);
829
830 }
831 }
832
833 radeon_link_encoder_connector(dev);
834 return true;
835 }
836
atombios_get_connector_object_id(struct drm_device * dev,int connector_type,uint16_t devices)837 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
838 int connector_type,
839 uint16_t devices)
840 {
841 struct radeon_device *rdev = dev->dev_private;
842
843 if (rdev->flags & RADEON_IS_IGP) {
844 return supported_devices_connector_object_id_convert
845 [connector_type];
846 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
847 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
848 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
849 struct radeon_mode_info *mode_info = &rdev->mode_info;
850 struct atom_context *ctx = mode_info->atom_context;
851 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
852 uint16_t size, data_offset;
853 uint8_t frev, crev;
854 ATOM_XTMDS_INFO *xtmds;
855
856 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
857 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
858
859 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
860 if (connector_type == DRM_MODE_CONNECTOR_DVII)
861 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
862 else
863 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
864 } else {
865 if (connector_type == DRM_MODE_CONNECTOR_DVII)
866 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
867 else
868 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
869 }
870 } else
871 return supported_devices_connector_object_id_convert
872 [connector_type];
873 } else {
874 return supported_devices_connector_object_id_convert
875 [connector_type];
876 }
877 }
878
879 struct bios_connector {
880 bool valid;
881 uint16_t line_mux;
882 uint16_t devices;
883 int connector_type;
884 struct radeon_i2c_bus_rec ddc_bus;
885 struct radeon_hpd hpd;
886 };
887
radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device * dev)888 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
889 drm_device
890 *dev)
891 {
892 struct radeon_device *rdev = dev->dev_private;
893 struct radeon_mode_info *mode_info = &rdev->mode_info;
894 struct atom_context *ctx = mode_info->atom_context;
895 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
896 uint16_t size, data_offset;
897 uint8_t frev, crev;
898 uint16_t device_support;
899 uint8_t dac;
900 union atom_supported_devices *supported_devices;
901 int i, j, max_device;
902 struct bios_connector *bios_connectors;
903 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
904 struct radeon_router router;
905
906 router.ddc_valid = false;
907 router.cd_valid = false;
908
909 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
910 if (!bios_connectors)
911 return false;
912
913 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
914 &data_offset)) {
915 kfree(bios_connectors);
916 return false;
917 }
918
919 supported_devices =
920 (union atom_supported_devices *)(ctx->bios + data_offset);
921
922 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
923
924 if (frev > 1)
925 max_device = ATOM_MAX_SUPPORTED_DEVICE;
926 else
927 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
928
929 for (i = 0; i < max_device; i++) {
930 ATOM_CONNECTOR_INFO_I2C ci;
931
932 if (frev > 1)
933 ci = supported_devices->info_2d1.asConnInfo[i];
934 else
935 ci = supported_devices->info.asConnInfo[i];
936
937 bios_connectors[i].valid = false;
938
939 if (!(device_support & (1 << i))) {
940 continue;
941 }
942
943 if (i == ATOM_DEVICE_CV_INDEX) {
944 DRM_DEBUG_KMS("Skipping Component Video\n");
945 continue;
946 }
947
948 bios_connectors[i].connector_type =
949 supported_devices_connector_convert[ci.sucConnectorInfo.
950 sbfAccess.
951 bfConnectorType];
952
953 if (bios_connectors[i].connector_type ==
954 DRM_MODE_CONNECTOR_Unknown)
955 continue;
956
957 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
958
959 bios_connectors[i].line_mux =
960 ci.sucI2cId.ucAccess;
961
962 /* give tv unique connector ids */
963 if (i == ATOM_DEVICE_TV1_INDEX) {
964 bios_connectors[i].ddc_bus.valid = false;
965 bios_connectors[i].line_mux = 50;
966 } else if (i == ATOM_DEVICE_TV2_INDEX) {
967 bios_connectors[i].ddc_bus.valid = false;
968 bios_connectors[i].line_mux = 51;
969 } else if (i == ATOM_DEVICE_CV_INDEX) {
970 bios_connectors[i].ddc_bus.valid = false;
971 bios_connectors[i].line_mux = 52;
972 } else
973 bios_connectors[i].ddc_bus =
974 radeon_lookup_i2c_gpio(rdev,
975 bios_connectors[i].line_mux);
976
977 if ((crev > 1) && (frev > 1)) {
978 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
979 switch (isb) {
980 case 0x4:
981 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
982 break;
983 case 0xa:
984 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
985 break;
986 default:
987 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
988 break;
989 }
990 } else {
991 if (i == ATOM_DEVICE_DFP1_INDEX)
992 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
993 else if (i == ATOM_DEVICE_DFP2_INDEX)
994 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
995 else
996 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
997 }
998
999 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1000 * shared with a DVI port, we'll pick up the DVI connector when we
1001 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1002 */
1003 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1004 bios_connectors[i].connector_type =
1005 DRM_MODE_CONNECTOR_VGA;
1006
1007 if (!radeon_atom_apply_quirks
1008 (dev, (1 << i), &bios_connectors[i].connector_type,
1009 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1010 &bios_connectors[i].hpd))
1011 continue;
1012
1013 bios_connectors[i].valid = true;
1014 bios_connectors[i].devices = (1 << i);
1015
1016 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1017 radeon_add_atom_encoder(dev,
1018 radeon_get_encoder_enum(dev,
1019 (1 << i),
1020 dac),
1021 (1 << i),
1022 0);
1023 else
1024 radeon_add_legacy_encoder(dev,
1025 radeon_get_encoder_enum(dev,
1026 (1 << i),
1027 dac),
1028 (1 << i));
1029 }
1030
1031 /* combine shared connectors */
1032 for (i = 0; i < max_device; i++) {
1033 if (bios_connectors[i].valid) {
1034 for (j = 0; j < max_device; j++) {
1035 if (bios_connectors[j].valid && (i != j)) {
1036 if (bios_connectors[i].line_mux ==
1037 bios_connectors[j].line_mux) {
1038 /* make sure not to combine LVDS */
1039 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1040 bios_connectors[i].line_mux = 53;
1041 bios_connectors[i].ddc_bus.valid = false;
1042 continue;
1043 }
1044 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1045 bios_connectors[j].line_mux = 53;
1046 bios_connectors[j].ddc_bus.valid = false;
1047 continue;
1048 }
1049 /* combine analog and digital for DVI-I */
1050 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1051 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1052 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1053 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1054 bios_connectors[i].devices |=
1055 bios_connectors[j].devices;
1056 bios_connectors[i].connector_type =
1057 DRM_MODE_CONNECTOR_DVII;
1058 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1059 bios_connectors[i].hpd =
1060 bios_connectors[j].hpd;
1061 bios_connectors[j].valid = false;
1062 }
1063 }
1064 }
1065 }
1066 }
1067 }
1068
1069 /* add the connectors */
1070 for (i = 0; i < max_device; i++) {
1071 if (bios_connectors[i].valid) {
1072 uint16_t connector_object_id =
1073 atombios_get_connector_object_id(dev,
1074 bios_connectors[i].connector_type,
1075 bios_connectors[i].devices);
1076 radeon_add_atom_connector(dev,
1077 bios_connectors[i].line_mux,
1078 bios_connectors[i].devices,
1079 bios_connectors[i].
1080 connector_type,
1081 &bios_connectors[i].ddc_bus,
1082 0,
1083 connector_object_id,
1084 &bios_connectors[i].hpd,
1085 &router);
1086 }
1087 }
1088
1089 radeon_link_encoder_connector(dev);
1090
1091 kfree(bios_connectors);
1092 return true;
1093 }
1094
1095 union firmware_info {
1096 ATOM_FIRMWARE_INFO info;
1097 ATOM_FIRMWARE_INFO_V1_2 info_12;
1098 ATOM_FIRMWARE_INFO_V1_3 info_13;
1099 ATOM_FIRMWARE_INFO_V1_4 info_14;
1100 ATOM_FIRMWARE_INFO_V2_1 info_21;
1101 ATOM_FIRMWARE_INFO_V2_2 info_22;
1102 };
1103
1104 union igp_info {
1105 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1106 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1107 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1108 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1109 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1110 };
1111
radeon_atombios_get_dentist_vco_freq(struct radeon_device * rdev)1112 static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev)
1113 {
1114 struct radeon_mode_info *mode_info = &rdev->mode_info;
1115 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1116 union igp_info *igp_info;
1117 u8 frev, crev;
1118 u16 data_offset;
1119
1120 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1121 &frev, &crev, &data_offset)) {
1122 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1123 data_offset);
1124 rdev->clock.vco_freq =
1125 le32_to_cpu(igp_info->info_6.ulDentistVCOFreq);
1126 }
1127 }
1128
radeon_atom_get_clock_info(struct drm_device * dev)1129 bool radeon_atom_get_clock_info(struct drm_device *dev)
1130 {
1131 struct radeon_device *rdev = dev->dev_private;
1132 struct radeon_mode_info *mode_info = &rdev->mode_info;
1133 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1134 union firmware_info *firmware_info;
1135 uint8_t frev, crev;
1136 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1137 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1138 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1139 struct radeon_pll *spll = &rdev->clock.spll;
1140 struct radeon_pll *mpll = &rdev->clock.mpll;
1141 uint16_t data_offset;
1142
1143 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1144 &frev, &crev, &data_offset)) {
1145 firmware_info =
1146 (union firmware_info *)(mode_info->atom_context->bios +
1147 data_offset);
1148 /* pixel clocks */
1149 p1pll->reference_freq =
1150 le16_to_cpu(firmware_info->info.usReferenceClock);
1151 p1pll->reference_div = 0;
1152
1153 if ((frev < 2) && (crev < 2))
1154 p1pll->pll_out_min =
1155 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1156 else
1157 p1pll->pll_out_min =
1158 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1159 p1pll->pll_out_max =
1160 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1161
1162 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) {
1163 p1pll->lcd_pll_out_min =
1164 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1165 if (p1pll->lcd_pll_out_min == 0)
1166 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1167 p1pll->lcd_pll_out_max =
1168 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1169 if (p1pll->lcd_pll_out_max == 0)
1170 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1171 } else {
1172 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1173 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1174 }
1175
1176 if (p1pll->pll_out_min == 0) {
1177 if (ASIC_IS_AVIVO(rdev))
1178 p1pll->pll_out_min = 64800;
1179 else
1180 p1pll->pll_out_min = 20000;
1181 }
1182
1183 p1pll->pll_in_min =
1184 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1185 p1pll->pll_in_max =
1186 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1187
1188 *p2pll = *p1pll;
1189
1190 /* system clock */
1191 if (ASIC_IS_DCE4(rdev))
1192 spll->reference_freq =
1193 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1194 else
1195 spll->reference_freq =
1196 le16_to_cpu(firmware_info->info.usReferenceClock);
1197 spll->reference_div = 0;
1198
1199 spll->pll_out_min =
1200 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1201 spll->pll_out_max =
1202 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1203
1204 /* ??? */
1205 if (spll->pll_out_min == 0) {
1206 if (ASIC_IS_AVIVO(rdev))
1207 spll->pll_out_min = 64800;
1208 else
1209 spll->pll_out_min = 20000;
1210 }
1211
1212 spll->pll_in_min =
1213 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1214 spll->pll_in_max =
1215 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1216
1217 /* memory clock */
1218 if (ASIC_IS_DCE4(rdev))
1219 mpll->reference_freq =
1220 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1221 else
1222 mpll->reference_freq =
1223 le16_to_cpu(firmware_info->info.usReferenceClock);
1224 mpll->reference_div = 0;
1225
1226 mpll->pll_out_min =
1227 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1228 mpll->pll_out_max =
1229 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1230
1231 /* ??? */
1232 if (mpll->pll_out_min == 0) {
1233 if (ASIC_IS_AVIVO(rdev))
1234 mpll->pll_out_min = 64800;
1235 else
1236 mpll->pll_out_min = 20000;
1237 }
1238
1239 mpll->pll_in_min =
1240 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1241 mpll->pll_in_max =
1242 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1243
1244 rdev->clock.default_sclk =
1245 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1246 rdev->clock.default_mclk =
1247 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1248
1249 if (ASIC_IS_DCE4(rdev)) {
1250 rdev->clock.default_dispclk =
1251 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1252 if (rdev->clock.default_dispclk == 0) {
1253 if (ASIC_IS_DCE6(rdev))
1254 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1255 else if (ASIC_IS_DCE5(rdev))
1256 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1257 else
1258 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1259 }
1260 /* set a reasonable default for DP */
1261 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1262 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1263 rdev->clock.default_dispclk / 100);
1264 rdev->clock.default_dispclk = 60000;
1265 }
1266 rdev->clock.dp_extclk =
1267 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1268 rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1269 }
1270 *dcpll = *p1pll;
1271
1272 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1273 if (rdev->clock.max_pixel_clock == 0)
1274 rdev->clock.max_pixel_clock = 40000;
1275
1276 /* not technically a clock, but... */
1277 rdev->mode_info.firmware_flags =
1278 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1279
1280 if (ASIC_IS_DCE8(rdev))
1281 rdev->clock.vco_freq =
1282 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq);
1283 else if (ASIC_IS_DCE5(rdev))
1284 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1285 else if (ASIC_IS_DCE41(rdev))
1286 radeon_atombios_get_dentist_vco_freq(rdev);
1287 else
1288 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1289
1290 if (rdev->clock.vco_freq == 0)
1291 rdev->clock.vco_freq = 360000; /* 3.6 GHz */
1292
1293 return true;
1294 }
1295
1296 return false;
1297 }
1298
radeon_atombios_sideport_present(struct radeon_device * rdev)1299 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1300 {
1301 struct radeon_mode_info *mode_info = &rdev->mode_info;
1302 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1303 union igp_info *igp_info;
1304 u8 frev, crev;
1305 u16 data_offset;
1306
1307 /* sideport is AMD only */
1308 if (rdev->family == CHIP_RS600)
1309 return false;
1310
1311 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1312 &frev, &crev, &data_offset)) {
1313 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1314 data_offset);
1315 switch (crev) {
1316 case 1:
1317 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1318 return true;
1319 break;
1320 case 2:
1321 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1322 return true;
1323 break;
1324 default:
1325 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1326 break;
1327 }
1328 }
1329 return false;
1330 }
1331
radeon_atombios_get_tmds_info(struct radeon_encoder * encoder,struct radeon_encoder_int_tmds * tmds)1332 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1333 struct radeon_encoder_int_tmds *tmds)
1334 {
1335 struct drm_device *dev = encoder->base.dev;
1336 struct radeon_device *rdev = dev->dev_private;
1337 struct radeon_mode_info *mode_info = &rdev->mode_info;
1338 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1339 uint16_t data_offset;
1340 struct _ATOM_TMDS_INFO *tmds_info;
1341 uint8_t frev, crev;
1342 uint16_t maxfreq;
1343 int i;
1344
1345 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1346 &frev, &crev, &data_offset)) {
1347 tmds_info =
1348 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1349 data_offset);
1350
1351 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1352 for (i = 0; i < 4; i++) {
1353 tmds->tmds_pll[i].freq =
1354 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1355 tmds->tmds_pll[i].value =
1356 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1357 tmds->tmds_pll[i].value |=
1358 (tmds_info->asMiscInfo[i].
1359 ucPLL_VCO_Gain & 0x3f) << 6;
1360 tmds->tmds_pll[i].value |=
1361 (tmds_info->asMiscInfo[i].
1362 ucPLL_DutyCycle & 0xf) << 12;
1363 tmds->tmds_pll[i].value |=
1364 (tmds_info->asMiscInfo[i].
1365 ucPLL_VoltageSwing & 0xf) << 16;
1366
1367 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1368 tmds->tmds_pll[i].freq,
1369 tmds->tmds_pll[i].value);
1370
1371 if (maxfreq == tmds->tmds_pll[i].freq) {
1372 tmds->tmds_pll[i].freq = 0xffffffff;
1373 break;
1374 }
1375 }
1376 return true;
1377 }
1378 return false;
1379 }
1380
radeon_atombios_get_ppll_ss_info(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id)1381 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1382 struct radeon_atom_ss *ss,
1383 int id)
1384 {
1385 struct radeon_mode_info *mode_info = &rdev->mode_info;
1386 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1387 uint16_t data_offset, size;
1388 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1389 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1390 uint8_t frev, crev;
1391 int i, num_indices;
1392
1393 memset(ss, 0, sizeof(struct radeon_atom_ss));
1394 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1395 &frev, &crev, &data_offset)) {
1396 ss_info =
1397 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1398
1399 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1400 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1401 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *)
1402 ((u8 *)&ss_info->asSS_Info[0]);
1403 for (i = 0; i < num_indices; i++) {
1404 if (ss_assign->ucSS_Id == id) {
1405 ss->percentage =
1406 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
1407 ss->type = ss_assign->ucSpreadSpectrumType;
1408 ss->step = ss_assign->ucSS_Step;
1409 ss->delay = ss_assign->ucSS_Delay;
1410 ss->range = ss_assign->ucSS_Range;
1411 ss->refdiv = ss_assign->ucRecommendedRef_Div;
1412 return true;
1413 }
1414 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *)
1415 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1416 }
1417 }
1418 return false;
1419 }
1420
radeon_atombios_get_igp_ss_overrides(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id)1421 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1422 struct radeon_atom_ss *ss,
1423 int id)
1424 {
1425 struct radeon_mode_info *mode_info = &rdev->mode_info;
1426 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1427 u16 data_offset, size;
1428 union igp_info *igp_info;
1429 u8 frev, crev;
1430 u16 percentage = 0, rate = 0;
1431
1432 /* get any igp specific overrides */
1433 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1434 &frev, &crev, &data_offset)) {
1435 igp_info = (union igp_info *)
1436 (mode_info->atom_context->bios + data_offset);
1437 switch (crev) {
1438 case 6:
1439 switch (id) {
1440 case ASIC_INTERNAL_SS_ON_TMDS:
1441 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1442 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1443 break;
1444 case ASIC_INTERNAL_SS_ON_HDMI:
1445 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1446 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1447 break;
1448 case ASIC_INTERNAL_SS_ON_LVDS:
1449 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1450 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1451 break;
1452 }
1453 break;
1454 case 7:
1455 switch (id) {
1456 case ASIC_INTERNAL_SS_ON_TMDS:
1457 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1458 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1459 break;
1460 case ASIC_INTERNAL_SS_ON_HDMI:
1461 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1462 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1463 break;
1464 case ASIC_INTERNAL_SS_ON_LVDS:
1465 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1466 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1467 break;
1468 }
1469 break;
1470 case 8:
1471 switch (id) {
1472 case ASIC_INTERNAL_SS_ON_TMDS:
1473 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1474 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1475 break;
1476 case ASIC_INTERNAL_SS_ON_HDMI:
1477 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1478 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1479 break;
1480 case ASIC_INTERNAL_SS_ON_LVDS:
1481 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1482 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1483 break;
1484 }
1485 break;
1486 default:
1487 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1488 break;
1489 }
1490 if (percentage)
1491 ss->percentage = percentage;
1492 if (rate)
1493 ss->rate = rate;
1494 }
1495 }
1496
1497 union asic_ss_info {
1498 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1499 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1500 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1501 };
1502
1503 union asic_ss_assignment {
1504 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
1505 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
1506 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
1507 };
1508
radeon_atombios_get_asic_ss_info(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id,u32 clock)1509 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1510 struct radeon_atom_ss *ss,
1511 int id, u32 clock)
1512 {
1513 struct radeon_mode_info *mode_info = &rdev->mode_info;
1514 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1515 uint16_t data_offset, size;
1516 union asic_ss_info *ss_info;
1517 union asic_ss_assignment *ss_assign;
1518 uint8_t frev, crev;
1519 int i, num_indices;
1520
1521 if (id == ASIC_INTERNAL_MEMORY_SS) {
1522 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1523 return false;
1524 }
1525 if (id == ASIC_INTERNAL_ENGINE_SS) {
1526 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1527 return false;
1528 }
1529
1530 memset(ss, 0, sizeof(struct radeon_atom_ss));
1531 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1532 &frev, &crev, &data_offset)) {
1533
1534 ss_info =
1535 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1536
1537 switch (frev) {
1538 case 1:
1539 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1540 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1541
1542 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
1543 for (i = 0; i < num_indices; i++) {
1544 if ((ss_assign->v1.ucClockIndication == id) &&
1545 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1546 ss->percentage =
1547 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1548 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1549 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1550 ss->percentage_divider = 100;
1551 return true;
1552 }
1553 ss_assign = (union asic_ss_assignment *)
1554 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1555 }
1556 break;
1557 case 2:
1558 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1559 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1560 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
1561 for (i = 0; i < num_indices; i++) {
1562 if ((ss_assign->v2.ucClockIndication == id) &&
1563 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1564 ss->percentage =
1565 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1566 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1567 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1568 ss->percentage_divider = 100;
1569 if ((crev == 2) &&
1570 ((id == ASIC_INTERNAL_ENGINE_SS) ||
1571 (id == ASIC_INTERNAL_MEMORY_SS)))
1572 ss->rate /= 100;
1573 return true;
1574 }
1575 ss_assign = (union asic_ss_assignment *)
1576 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1577 }
1578 break;
1579 case 3:
1580 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1581 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1582 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
1583 for (i = 0; i < num_indices; i++) {
1584 if ((ss_assign->v3.ucClockIndication == id) &&
1585 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1586 ss->percentage =
1587 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1588 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1589 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1590 if (ss_assign->v3.ucSpreadSpectrumMode &
1591 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
1592 ss->percentage_divider = 1000;
1593 else
1594 ss->percentage_divider = 100;
1595 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1596 (id == ASIC_INTERNAL_MEMORY_SS))
1597 ss->rate /= 100;
1598 if (rdev->flags & RADEON_IS_IGP)
1599 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1600 return true;
1601 }
1602 ss_assign = (union asic_ss_assignment *)
1603 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1604 }
1605 break;
1606 default:
1607 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1608 break;
1609 }
1610
1611 }
1612 return false;
1613 }
1614
1615 union lvds_info {
1616 struct _ATOM_LVDS_INFO info;
1617 struct _ATOM_LVDS_INFO_V12 info_12;
1618 };
1619
radeon_atombios_get_lvds_info(struct radeon_encoder * encoder)1620 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1621 radeon_encoder
1622 *encoder)
1623 {
1624 struct drm_device *dev = encoder->base.dev;
1625 struct radeon_device *rdev = dev->dev_private;
1626 struct radeon_mode_info *mode_info = &rdev->mode_info;
1627 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1628 uint16_t data_offset, misc;
1629 union lvds_info *lvds_info;
1630 uint8_t frev, crev;
1631 struct radeon_encoder_atom_dig *lvds = NULL;
1632 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1633
1634 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1635 &frev, &crev, &data_offset)) {
1636 lvds_info =
1637 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1638 lvds =
1639 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1640
1641 if (!lvds)
1642 return NULL;
1643
1644 lvds->native_mode.clock =
1645 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1646 lvds->native_mode.hdisplay =
1647 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1648 lvds->native_mode.vdisplay =
1649 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1650 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1651 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1652 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1653 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1654 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1655 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1656 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1657 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1658 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1659 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1660 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1661 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1662 lvds->panel_pwr_delay =
1663 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1664 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1665
1666 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1667 if (misc & ATOM_VSYNC_POLARITY)
1668 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1669 if (misc & ATOM_HSYNC_POLARITY)
1670 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1671 if (misc & ATOM_COMPOSITESYNC)
1672 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1673 if (misc & ATOM_INTERLACE)
1674 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1675 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1676 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1677
1678 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1679 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1680
1681 /* set crtc values */
1682 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1683
1684 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1685
1686 encoder->native_mode = lvds->native_mode;
1687
1688 if (encoder_enum == 2)
1689 lvds->linkb = true;
1690 else
1691 lvds->linkb = false;
1692
1693 /* parse the lcd record table */
1694 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1695 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1696 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1697 bool bad_record = false;
1698 u8 *record;
1699
1700 if ((frev == 1) && (crev < 2))
1701 /* absolute */
1702 record = (u8 *)(mode_info->atom_context->bios +
1703 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1704 else
1705 /* relative */
1706 record = (u8 *)(mode_info->atom_context->bios +
1707 data_offset +
1708 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1709 while (*record != ATOM_RECORD_END_TYPE) {
1710 switch (*record) {
1711 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1712 record += sizeof(ATOM_PATCH_RECORD_MODE);
1713 break;
1714 case LCD_RTS_RECORD_TYPE:
1715 record += sizeof(ATOM_LCD_RTS_RECORD);
1716 break;
1717 case LCD_CAP_RECORD_TYPE:
1718 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1719 break;
1720 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1721 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1722 if (fake_edid_record->ucFakeEDIDLength) {
1723 const struct drm_edid *edid;
1724 int edid_size;
1725
1726 if (fake_edid_record->ucFakeEDIDLength == 128)
1727 edid_size = fake_edid_record->ucFakeEDIDLength;
1728 else
1729 edid_size = fake_edid_record->ucFakeEDIDLength * 128;
1730 edid = drm_edid_alloc(fake_edid_record->ucFakeEDIDString, edid_size);
1731 if (drm_edid_valid(edid))
1732 rdev->mode_info.bios_hardcoded_edid = edid;
1733 else
1734 drm_edid_free(edid);
1735 record += struct_size(fake_edid_record,
1736 ucFakeEDIDString,
1737 edid_size);
1738 } else {
1739 /* empty fake edid record must be 3 bytes long */
1740 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1;
1741 }
1742 break;
1743 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1744 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1745 lvds->native_mode.width_mm = panel_res_record->usHSize;
1746 lvds->native_mode.height_mm = panel_res_record->usVSize;
1747 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1748 break;
1749 default:
1750 DRM_ERROR("Bad LCD record %d\n", *record);
1751 bad_record = true;
1752 break;
1753 }
1754 if (bad_record)
1755 break;
1756 }
1757 }
1758 }
1759 return lvds;
1760 }
1761
1762 struct radeon_encoder_primary_dac *
radeon_atombios_get_primary_dac_info(struct radeon_encoder * encoder)1763 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1764 {
1765 struct drm_device *dev = encoder->base.dev;
1766 struct radeon_device *rdev = dev->dev_private;
1767 struct radeon_mode_info *mode_info = &rdev->mode_info;
1768 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1769 uint16_t data_offset;
1770 struct _COMPASSIONATE_DATA *dac_info;
1771 uint8_t frev, crev;
1772 uint8_t bg, dac;
1773 struct radeon_encoder_primary_dac *p_dac = NULL;
1774
1775 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1776 &frev, &crev, &data_offset)) {
1777 dac_info = (struct _COMPASSIONATE_DATA *)
1778 (mode_info->atom_context->bios + data_offset);
1779
1780 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1781
1782 if (!p_dac)
1783 return NULL;
1784
1785 bg = dac_info->ucDAC1_BG_Adjustment;
1786 dac = dac_info->ucDAC1_DAC_Adjustment;
1787 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1788
1789 }
1790 return p_dac;
1791 }
1792
radeon_atom_get_tv_timings(struct radeon_device * rdev,int index,struct drm_display_mode * mode)1793 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1794 struct drm_display_mode *mode)
1795 {
1796 struct radeon_mode_info *mode_info = &rdev->mode_info;
1797 ATOM_ANALOG_TV_INFO *tv_info;
1798 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1799 ATOM_DTD_FORMAT *dtd_timings;
1800 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1801 u8 frev, crev;
1802 u16 data_offset, misc;
1803
1804 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1805 &frev, &crev, &data_offset))
1806 return false;
1807
1808 switch (crev) {
1809 case 1:
1810 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1811 if (index >= MAX_SUPPORTED_TV_TIMING)
1812 return false;
1813
1814 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1815 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1816 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1817 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1818 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1819
1820 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1821 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1822 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1823 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1824 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1825
1826 mode->flags = 0;
1827 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1828 if (misc & ATOM_VSYNC_POLARITY)
1829 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1830 if (misc & ATOM_HSYNC_POLARITY)
1831 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1832 if (misc & ATOM_COMPOSITESYNC)
1833 mode->flags |= DRM_MODE_FLAG_CSYNC;
1834 if (misc & ATOM_INTERLACE)
1835 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1836 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1837 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1838
1839 mode->crtc_clock = mode->clock =
1840 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1841
1842 if (index == 1) {
1843 /* PAL timings appear to have wrong values for totals */
1844 mode->crtc_htotal -= 1;
1845 mode->crtc_vtotal -= 1;
1846 }
1847 break;
1848 case 2:
1849 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1850 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1851 return false;
1852
1853 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1854 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1855 le16_to_cpu(dtd_timings->usHBlanking_Time);
1856 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1857 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1858 le16_to_cpu(dtd_timings->usHSyncOffset);
1859 mode->crtc_hsync_end = mode->crtc_hsync_start +
1860 le16_to_cpu(dtd_timings->usHSyncWidth);
1861
1862 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1863 le16_to_cpu(dtd_timings->usVBlanking_Time);
1864 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1865 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1866 le16_to_cpu(dtd_timings->usVSyncOffset);
1867 mode->crtc_vsync_end = mode->crtc_vsync_start +
1868 le16_to_cpu(dtd_timings->usVSyncWidth);
1869
1870 mode->flags = 0;
1871 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1872 if (misc & ATOM_VSYNC_POLARITY)
1873 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1874 if (misc & ATOM_HSYNC_POLARITY)
1875 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1876 if (misc & ATOM_COMPOSITESYNC)
1877 mode->flags |= DRM_MODE_FLAG_CSYNC;
1878 if (misc & ATOM_INTERLACE)
1879 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1880 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1881 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1882
1883 mode->crtc_clock = mode->clock =
1884 le16_to_cpu(dtd_timings->usPixClk) * 10;
1885 break;
1886 }
1887 return true;
1888 }
1889
1890 enum radeon_tv_std
radeon_atombios_get_tv_info(struct radeon_device * rdev)1891 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1892 {
1893 struct radeon_mode_info *mode_info = &rdev->mode_info;
1894 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1895 uint16_t data_offset;
1896 uint8_t frev, crev;
1897 struct _ATOM_ANALOG_TV_INFO *tv_info;
1898 enum radeon_tv_std tv_std = TV_STD_NTSC;
1899
1900 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1901 &frev, &crev, &data_offset)) {
1902
1903 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1904 (mode_info->atom_context->bios + data_offset);
1905
1906 switch (tv_info->ucTV_BootUpDefaultStandard) {
1907 case ATOM_TV_NTSC:
1908 tv_std = TV_STD_NTSC;
1909 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1910 break;
1911 case ATOM_TV_NTSCJ:
1912 tv_std = TV_STD_NTSC_J;
1913 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1914 break;
1915 case ATOM_TV_PAL:
1916 tv_std = TV_STD_PAL;
1917 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1918 break;
1919 case ATOM_TV_PALM:
1920 tv_std = TV_STD_PAL_M;
1921 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1922 break;
1923 case ATOM_TV_PALN:
1924 tv_std = TV_STD_PAL_N;
1925 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1926 break;
1927 case ATOM_TV_PALCN:
1928 tv_std = TV_STD_PAL_CN;
1929 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1930 break;
1931 case ATOM_TV_PAL60:
1932 tv_std = TV_STD_PAL_60;
1933 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1934 break;
1935 case ATOM_TV_SECAM:
1936 tv_std = TV_STD_SECAM;
1937 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1938 break;
1939 default:
1940 tv_std = TV_STD_NTSC;
1941 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1942 break;
1943 }
1944 }
1945 return tv_std;
1946 }
1947
1948 struct radeon_encoder_tv_dac *
radeon_atombios_get_tv_dac_info(struct radeon_encoder * encoder)1949 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1950 {
1951 struct drm_device *dev = encoder->base.dev;
1952 struct radeon_device *rdev = dev->dev_private;
1953 struct radeon_mode_info *mode_info = &rdev->mode_info;
1954 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1955 uint16_t data_offset;
1956 struct _COMPASSIONATE_DATA *dac_info;
1957 uint8_t frev, crev;
1958 uint8_t bg, dac;
1959 struct radeon_encoder_tv_dac *tv_dac = NULL;
1960
1961 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1962 &frev, &crev, &data_offset)) {
1963
1964 dac_info = (struct _COMPASSIONATE_DATA *)
1965 (mode_info->atom_context->bios + data_offset);
1966
1967 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1968
1969 if (!tv_dac)
1970 return NULL;
1971
1972 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1973 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1974 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1975
1976 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1977 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1978 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1979
1980 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1981 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1982 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1983
1984 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1985 }
1986 return tv_dac;
1987 }
1988
1989 static const char *thermal_controller_names[] = {
1990 "NONE",
1991 "lm63",
1992 "adm1032",
1993 "adm1030",
1994 "max6649",
1995 "lm63", /* lm64 */
1996 "f75375",
1997 "asc7xxx",
1998 };
1999
2000 static const char *pp_lib_thermal_controller_names[] = {
2001 "NONE",
2002 "lm63",
2003 "adm1032",
2004 "adm1030",
2005 "max6649",
2006 "lm63", /* lm64 */
2007 "f75375",
2008 "RV6xx",
2009 "RV770",
2010 "adt7473",
2011 "NONE",
2012 "External GPIO",
2013 "Evergreen",
2014 "emc2103",
2015 "Sumo",
2016 "Northern Islands",
2017 "Southern Islands",
2018 "lm96163",
2019 "Sea Islands",
2020 };
2021
2022 union power_info {
2023 struct _ATOM_POWERPLAY_INFO info;
2024 struct _ATOM_POWERPLAY_INFO_V2 info_2;
2025 struct _ATOM_POWERPLAY_INFO_V3 info_3;
2026 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2027 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2028 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2029 };
2030
2031 union pplib_clock_info {
2032 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2033 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2034 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2035 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2036 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
2037 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
2038 };
2039
2040 union pplib_power_state {
2041 struct _ATOM_PPLIB_STATE v1;
2042 struct _ATOM_PPLIB_STATE_V2 v2;
2043 };
2044
radeon_atombios_parse_misc_flags_1_3(struct radeon_device * rdev,int state_index,u32 misc,u32 misc2)2045 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2046 int state_index,
2047 u32 misc, u32 misc2)
2048 {
2049 rdev->pm.power_state[state_index].misc = misc;
2050 rdev->pm.power_state[state_index].misc2 = misc2;
2051 /* order matters! */
2052 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2053 rdev->pm.power_state[state_index].type =
2054 POWER_STATE_TYPE_POWERSAVE;
2055 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2056 rdev->pm.power_state[state_index].type =
2057 POWER_STATE_TYPE_BATTERY;
2058 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2059 rdev->pm.power_state[state_index].type =
2060 POWER_STATE_TYPE_BATTERY;
2061 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2062 rdev->pm.power_state[state_index].type =
2063 POWER_STATE_TYPE_BALANCED;
2064 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2065 rdev->pm.power_state[state_index].type =
2066 POWER_STATE_TYPE_PERFORMANCE;
2067 rdev->pm.power_state[state_index].flags &=
2068 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2069 }
2070 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2071 rdev->pm.power_state[state_index].type =
2072 POWER_STATE_TYPE_BALANCED;
2073 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2074 rdev->pm.power_state[state_index].type =
2075 POWER_STATE_TYPE_DEFAULT;
2076 rdev->pm.default_power_state_index = state_index;
2077 rdev->pm.power_state[state_index].default_clock_mode =
2078 &rdev->pm.power_state[state_index].clock_info[0];
2079 } else if (state_index == 0) {
2080 rdev->pm.power_state[state_index].clock_info[0].flags |=
2081 RADEON_PM_MODE_NO_DISPLAY;
2082 }
2083 }
2084
radeon_atombios_parse_power_table_1_3(struct radeon_device * rdev)2085 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2086 {
2087 struct radeon_mode_info *mode_info = &rdev->mode_info;
2088 u32 misc, misc2 = 0;
2089 int num_modes = 0, i;
2090 int state_index = 0;
2091 struct radeon_i2c_bus_rec i2c_bus;
2092 union power_info *power_info;
2093 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2094 u16 data_offset;
2095 u8 frev, crev;
2096
2097 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2098 &frev, &crev, &data_offset))
2099 return state_index;
2100 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2101
2102 /* add the i2c bus for thermal/fan chip */
2103 if ((power_info->info.ucOverdriveThermalController > 0) &&
2104 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2105 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2106 thermal_controller_names[power_info->info.ucOverdriveThermalController],
2107 power_info->info.ucOverdriveControllerAddress >> 1);
2108 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2109 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2110 #ifdef notyet
2111 if (rdev->pm.i2c_bus) {
2112 struct i2c_board_info info = { };
2113 const char *name = thermal_controller_names[power_info->info.
2114 ucOverdriveThermalController];
2115 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2116 strscpy(info.type, name, sizeof(info.type));
2117 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2118 }
2119 #endif
2120 }
2121 num_modes = power_info->info.ucNumOfPowerModeEntries;
2122 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2123 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2124 if (num_modes == 0)
2125 return state_index;
2126 rdev->pm.power_state = kcalloc(num_modes,
2127 sizeof(struct radeon_power_state),
2128 GFP_KERNEL);
2129 if (!rdev->pm.power_state)
2130 return state_index;
2131 /* last mode is usually default, array is low to high */
2132 for (i = 0; i < num_modes; i++) {
2133 /* avoid memory leaks from invalid modes or unknown frev. */
2134 if (!rdev->pm.power_state[state_index].clock_info) {
2135 rdev->pm.power_state[state_index].clock_info =
2136 kzalloc(sizeof(struct radeon_pm_clock_info),
2137 GFP_KERNEL);
2138 }
2139 if (!rdev->pm.power_state[state_index].clock_info)
2140 goto out;
2141 rdev->pm.power_state[state_index].num_clock_modes = 1;
2142 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2143 switch (frev) {
2144 case 1:
2145 rdev->pm.power_state[state_index].clock_info[0].mclk =
2146 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2147 rdev->pm.power_state[state_index].clock_info[0].sclk =
2148 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2149 /* skip invalid modes */
2150 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2151 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2152 continue;
2153 rdev->pm.power_state[state_index].pcie_lanes =
2154 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2155 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2156 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2157 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2158 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2159 VOLTAGE_GPIO;
2160 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2161 radeon_atombios_lookup_gpio(rdev,
2162 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2163 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2164 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2165 true;
2166 else
2167 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2168 false;
2169 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2170 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2171 VOLTAGE_VDDC;
2172 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2173 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2174 }
2175 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2176 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2177 state_index++;
2178 break;
2179 case 2:
2180 rdev->pm.power_state[state_index].clock_info[0].mclk =
2181 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2182 rdev->pm.power_state[state_index].clock_info[0].sclk =
2183 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2184 /* skip invalid modes */
2185 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2186 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2187 continue;
2188 rdev->pm.power_state[state_index].pcie_lanes =
2189 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2190 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2191 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2192 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2193 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2194 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2195 VOLTAGE_GPIO;
2196 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2197 radeon_atombios_lookup_gpio(rdev,
2198 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2199 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2200 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2201 true;
2202 else
2203 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2204 false;
2205 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2206 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2207 VOLTAGE_VDDC;
2208 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2209 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2210 }
2211 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2212 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2213 state_index++;
2214 break;
2215 case 3:
2216 rdev->pm.power_state[state_index].clock_info[0].mclk =
2217 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2218 rdev->pm.power_state[state_index].clock_info[0].sclk =
2219 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2220 /* skip invalid modes */
2221 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2222 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2223 continue;
2224 rdev->pm.power_state[state_index].pcie_lanes =
2225 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2226 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2227 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2228 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2229 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2230 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2231 VOLTAGE_GPIO;
2232 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2233 radeon_atombios_lookup_gpio(rdev,
2234 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2235 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2236 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2237 true;
2238 else
2239 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2240 false;
2241 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2242 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2243 VOLTAGE_VDDC;
2244 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2245 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2246 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2247 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2248 true;
2249 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2250 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2251 }
2252 }
2253 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2254 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2255 state_index++;
2256 break;
2257 }
2258 }
2259 out:
2260 /* free any unused clock_info allocation. */
2261 if (state_index && state_index < num_modes) {
2262 kfree(rdev->pm.power_state[state_index].clock_info);
2263 rdev->pm.power_state[state_index].clock_info = NULL;
2264 }
2265
2266 /* last mode is usually default */
2267 if (state_index && rdev->pm.default_power_state_index == -1) {
2268 rdev->pm.power_state[state_index - 1].type =
2269 POWER_STATE_TYPE_DEFAULT;
2270 rdev->pm.default_power_state_index = state_index - 1;
2271 rdev->pm.power_state[state_index - 1].default_clock_mode =
2272 &rdev->pm.power_state[state_index - 1].clock_info[0];
2273 rdev->pm.power_state[state_index - 1].flags &=
2274 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2275 rdev->pm.power_state[state_index - 1].misc = 0;
2276 rdev->pm.power_state[state_index - 1].misc2 = 0;
2277 }
2278 return state_index;
2279 }
2280
radeon_atombios_add_pplib_thermal_controller(struct radeon_device * rdev,ATOM_PPLIB_THERMALCONTROLLER * controller)2281 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2282 ATOM_PPLIB_THERMALCONTROLLER *controller)
2283 {
2284 struct radeon_i2c_bus_rec i2c_bus;
2285
2286 /* add the i2c bus for thermal/fan chip */
2287 if (controller->ucType > 0) {
2288 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN)
2289 rdev->pm.no_fan = true;
2290 rdev->pm.fan_pulses_per_revolution =
2291 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
2292 if (rdev->pm.fan_pulses_per_revolution) {
2293 rdev->pm.fan_min_rpm = controller->ucFanMinRPM;
2294 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM;
2295 }
2296 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2297 DRM_INFO("Internal thermal controller %s fan control\n",
2298 (controller->ucFanParameters &
2299 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2300 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2301 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2302 DRM_INFO("Internal thermal controller %s fan control\n",
2303 (controller->ucFanParameters &
2304 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2305 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2306 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2307 DRM_INFO("Internal thermal controller %s fan control\n",
2308 (controller->ucFanParameters &
2309 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2310 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2311 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2312 DRM_INFO("Internal thermal controller %s fan control\n",
2313 (controller->ucFanParameters &
2314 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2315 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2316 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2317 DRM_INFO("Internal thermal controller %s fan control\n",
2318 (controller->ucFanParameters &
2319 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2320 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2321 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2322 DRM_INFO("Internal thermal controller %s fan control\n",
2323 (controller->ucFanParameters &
2324 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2325 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2326 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2327 DRM_INFO("Internal thermal controller %s fan control\n",
2328 (controller->ucFanParameters &
2329 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2330 rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2331 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
2332 DRM_INFO("Internal thermal controller %s fan control\n",
2333 (controller->ucFanParameters &
2334 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2335 rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2336 } else if (controller->ucType ==
2337 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
2338 DRM_INFO("External GPIO thermal controller %s fan control\n",
2339 (controller->ucFanParameters &
2340 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2341 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
2342 } else if (controller->ucType ==
2343 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
2344 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
2345 (controller->ucFanParameters &
2346 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2347 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
2348 } else if (controller->ucType ==
2349 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
2350 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
2351 (controller->ucFanParameters &
2352 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2353 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2354 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2355 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2356 pp_lib_thermal_controller_names[controller->ucType],
2357 controller->ucI2cAddress >> 1,
2358 (controller->ucFanParameters &
2359 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2360 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
2361 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2362 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2363 #ifdef notyet
2364 if (rdev->pm.i2c_bus) {
2365 struct i2c_board_info info = { };
2366 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2367 info.addr = controller->ucI2cAddress >> 1;
2368 strscpy(info.type, name, sizeof(info.type));
2369 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2370 }
2371 #endif
2372 } else {
2373 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2374 controller->ucType,
2375 controller->ucI2cAddress >> 1,
2376 (controller->ucFanParameters &
2377 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2378 }
2379 }
2380 }
2381
radeon_atombios_get_default_voltages(struct radeon_device * rdev,u16 * vddc,u16 * vddci,u16 * mvdd)2382 void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2383 u16 *vddc, u16 *vddci, u16 *mvdd)
2384 {
2385 struct radeon_mode_info *mode_info = &rdev->mode_info;
2386 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2387 u8 frev, crev;
2388 u16 data_offset;
2389 union firmware_info *firmware_info;
2390
2391 *vddc = 0;
2392 *vddci = 0;
2393 *mvdd = 0;
2394
2395 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2396 &frev, &crev, &data_offset)) {
2397 firmware_info =
2398 (union firmware_info *)(mode_info->atom_context->bios +
2399 data_offset);
2400 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2401 if ((frev == 2) && (crev >= 2)) {
2402 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2403 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2404 }
2405 }
2406 }
2407
radeon_atombios_parse_pplib_non_clock_info(struct radeon_device * rdev,int state_index,int mode_index,struct _ATOM_PPLIB_NONCLOCK_INFO * non_clock_info)2408 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2409 int state_index, int mode_index,
2410 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2411 {
2412 int j;
2413 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2414 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2415 u16 vddc, vddci, mvdd;
2416
2417 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2418
2419 rdev->pm.power_state[state_index].misc = misc;
2420 rdev->pm.power_state[state_index].misc2 = misc2;
2421 rdev->pm.power_state[state_index].pcie_lanes =
2422 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2423 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2424 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2425 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2426 rdev->pm.power_state[state_index].type =
2427 POWER_STATE_TYPE_BATTERY;
2428 break;
2429 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2430 rdev->pm.power_state[state_index].type =
2431 POWER_STATE_TYPE_BALANCED;
2432 break;
2433 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2434 rdev->pm.power_state[state_index].type =
2435 POWER_STATE_TYPE_PERFORMANCE;
2436 break;
2437 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2438 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2439 rdev->pm.power_state[state_index].type =
2440 POWER_STATE_TYPE_PERFORMANCE;
2441 break;
2442 }
2443 rdev->pm.power_state[state_index].flags = 0;
2444 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2445 rdev->pm.power_state[state_index].flags |=
2446 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2447 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2448 rdev->pm.power_state[state_index].type =
2449 POWER_STATE_TYPE_DEFAULT;
2450 rdev->pm.default_power_state_index = state_index;
2451 rdev->pm.power_state[state_index].default_clock_mode =
2452 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2453 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2454 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2455 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2456 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2457 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2458 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2459 } else {
2460 u16 max_vddci = 0;
2461
2462 if (ASIC_IS_DCE4(rdev))
2463 radeon_atom_get_max_voltage(rdev,
2464 SET_VOLTAGE_TYPE_ASIC_VDDCI,
2465 &max_vddci);
2466 /* patch the table values with the default sclk/mclk from firmware info */
2467 for (j = 0; j < mode_index; j++) {
2468 rdev->pm.power_state[state_index].clock_info[j].mclk =
2469 rdev->clock.default_mclk;
2470 rdev->pm.power_state[state_index].clock_info[j].sclk =
2471 rdev->clock.default_sclk;
2472 if (vddc)
2473 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2474 vddc;
2475 if (max_vddci)
2476 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2477 max_vddci;
2478 }
2479 }
2480 }
2481 }
2482
radeon_atombios_parse_pplib_clock_info(struct radeon_device * rdev,int state_index,int mode_index,union pplib_clock_info * clock_info)2483 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2484 int state_index, int mode_index,
2485 union pplib_clock_info *clock_info)
2486 {
2487 u32 sclk, mclk;
2488 u16 vddc;
2489
2490 if (rdev->flags & RADEON_IS_IGP) {
2491 if (rdev->family >= CHIP_PALM) {
2492 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2493 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2494 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2495 } else {
2496 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2497 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2498 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2499 }
2500 } else if (rdev->family >= CHIP_BONAIRE) {
2501 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2502 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2503 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2504 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2505 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2506 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2507 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2508 VOLTAGE_NONE;
2509 } else if (rdev->family >= CHIP_TAHITI) {
2510 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2511 sclk |= clock_info->si.ucEngineClockHigh << 16;
2512 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2513 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2514 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2515 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2516 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2517 VOLTAGE_SW;
2518 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2519 le16_to_cpu(clock_info->si.usVDDC);
2520 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2521 le16_to_cpu(clock_info->si.usVDDCI);
2522 } else if (rdev->family >= CHIP_CEDAR) {
2523 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2524 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2525 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2526 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2527 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2528 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2529 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2530 VOLTAGE_SW;
2531 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2532 le16_to_cpu(clock_info->evergreen.usVDDC);
2533 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2534 le16_to_cpu(clock_info->evergreen.usVDDCI);
2535 } else {
2536 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2537 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2538 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2539 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2540 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2541 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2542 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2543 VOLTAGE_SW;
2544 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2545 le16_to_cpu(clock_info->r600.usVDDC);
2546 }
2547
2548 /* patch up vddc if necessary */
2549 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2550 case ATOM_VIRTUAL_VOLTAGE_ID0:
2551 case ATOM_VIRTUAL_VOLTAGE_ID1:
2552 case ATOM_VIRTUAL_VOLTAGE_ID2:
2553 case ATOM_VIRTUAL_VOLTAGE_ID3:
2554 case ATOM_VIRTUAL_VOLTAGE_ID4:
2555 case ATOM_VIRTUAL_VOLTAGE_ID5:
2556 case ATOM_VIRTUAL_VOLTAGE_ID6:
2557 case ATOM_VIRTUAL_VOLTAGE_ID7:
2558 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2559 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2560 &vddc) == 0)
2561 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2562 break;
2563 default:
2564 break;
2565 }
2566
2567 if (rdev->flags & RADEON_IS_IGP) {
2568 /* skip invalid modes */
2569 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2570 return false;
2571 } else {
2572 /* skip invalid modes */
2573 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2574 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2575 return false;
2576 }
2577 return true;
2578 }
2579
radeon_atombios_parse_power_table_4_5(struct radeon_device * rdev)2580 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2581 {
2582 struct radeon_mode_info *mode_info = &rdev->mode_info;
2583 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2584 union pplib_power_state *power_state;
2585 int i, j;
2586 int state_index = 0, mode_index = 0;
2587 union pplib_clock_info *clock_info;
2588 bool valid;
2589 union power_info *power_info;
2590 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2591 u16 data_offset;
2592 u8 frev, crev;
2593
2594 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2595 &frev, &crev, &data_offset))
2596 return state_index;
2597 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2598
2599 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2600 if (power_info->pplib.ucNumStates == 0)
2601 return state_index;
2602 rdev->pm.power_state = kcalloc(power_info->pplib.ucNumStates,
2603 sizeof(struct radeon_power_state),
2604 GFP_KERNEL);
2605 if (!rdev->pm.power_state)
2606 return state_index;
2607 /* first mode is usually default, followed by low to high */
2608 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2609 mode_index = 0;
2610 power_state = (union pplib_power_state *)
2611 (mode_info->atom_context->bios + data_offset +
2612 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2613 i * power_info->pplib.ucStateEntrySize);
2614 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2615 (mode_info->atom_context->bios + data_offset +
2616 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2617 (power_state->v1.ucNonClockStateIndex *
2618 power_info->pplib.ucNonClockSize));
2619 rdev->pm.power_state[i].clock_info =
2620 kcalloc((power_info->pplib.ucStateEntrySize - 1) ?
2621 (power_info->pplib.ucStateEntrySize - 1) : 1,
2622 sizeof(struct radeon_pm_clock_info),
2623 GFP_KERNEL);
2624 if (!rdev->pm.power_state[i].clock_info)
2625 return state_index;
2626 if (power_info->pplib.ucStateEntrySize - 1) {
2627 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2628 clock_info = (union pplib_clock_info *)
2629 (mode_info->atom_context->bios + data_offset +
2630 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2631 (power_state->v1.ucClockStateIndices[j] *
2632 power_info->pplib.ucClockInfoSize));
2633 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2634 state_index, mode_index,
2635 clock_info);
2636 if (valid)
2637 mode_index++;
2638 }
2639 } else {
2640 rdev->pm.power_state[state_index].clock_info[0].mclk =
2641 rdev->clock.default_mclk;
2642 rdev->pm.power_state[state_index].clock_info[0].sclk =
2643 rdev->clock.default_sclk;
2644 mode_index++;
2645 }
2646 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2647 if (mode_index) {
2648 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2649 non_clock_info);
2650 state_index++;
2651 }
2652 }
2653 /* if multiple clock modes, mark the lowest as no display */
2654 for (i = 0; i < state_index; i++) {
2655 if (rdev->pm.power_state[i].num_clock_modes > 1)
2656 rdev->pm.power_state[i].clock_info[0].flags |=
2657 RADEON_PM_MODE_NO_DISPLAY;
2658 }
2659 /* first mode is usually default */
2660 if (rdev->pm.default_power_state_index == -1) {
2661 rdev->pm.power_state[0].type =
2662 POWER_STATE_TYPE_DEFAULT;
2663 rdev->pm.default_power_state_index = 0;
2664 rdev->pm.power_state[0].default_clock_mode =
2665 &rdev->pm.power_state[0].clock_info[0];
2666 }
2667 return state_index;
2668 }
2669
radeon_atombios_parse_power_table_6(struct radeon_device * rdev)2670 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2671 {
2672 struct radeon_mode_info *mode_info = &rdev->mode_info;
2673 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2674 union pplib_power_state *power_state;
2675 int i, j, non_clock_array_index, clock_array_index;
2676 int state_index = 0, mode_index = 0;
2677 union pplib_clock_info *clock_info;
2678 struct _StateArray *state_array;
2679 struct _ClockInfoArray *clock_info_array;
2680 struct _NonClockInfoArray *non_clock_info_array;
2681 bool valid;
2682 union power_info *power_info;
2683 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2684 u16 data_offset;
2685 u8 frev, crev;
2686 u8 *power_state_offset;
2687
2688 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2689 &frev, &crev, &data_offset))
2690 return state_index;
2691 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2692
2693 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2694 state_array = (struct _StateArray *)
2695 (mode_info->atom_context->bios + data_offset +
2696 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2697 clock_info_array = (struct _ClockInfoArray *)
2698 (mode_info->atom_context->bios + data_offset +
2699 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2700 non_clock_info_array = (struct _NonClockInfoArray *)
2701 (mode_info->atom_context->bios + data_offset +
2702 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2703 if (state_array->ucNumEntries == 0)
2704 return state_index;
2705 rdev->pm.power_state = kcalloc(state_array->ucNumEntries,
2706 sizeof(struct radeon_power_state),
2707 GFP_KERNEL);
2708 if (!rdev->pm.power_state)
2709 return state_index;
2710 power_state_offset = (u8 *)state_array->states;
2711 for (i = 0; i < state_array->ucNumEntries; i++) {
2712 mode_index = 0;
2713 power_state = (union pplib_power_state *)power_state_offset;
2714 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2715 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2716 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2717 rdev->pm.power_state[i].clock_info =
2718 kcalloc(power_state->v2.ucNumDPMLevels ?
2719 power_state->v2.ucNumDPMLevels : 1,
2720 sizeof(struct radeon_pm_clock_info),
2721 GFP_KERNEL);
2722 if (!rdev->pm.power_state[i].clock_info)
2723 return state_index;
2724 if (power_state->v2.ucNumDPMLevels) {
2725 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2726 clock_array_index = power_state->v2.clockInfoIndex[j];
2727 clock_info = (union pplib_clock_info *)
2728 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2729 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2730 state_index, mode_index,
2731 clock_info);
2732 if (valid)
2733 mode_index++;
2734 }
2735 } else {
2736 rdev->pm.power_state[state_index].clock_info[0].mclk =
2737 rdev->clock.default_mclk;
2738 rdev->pm.power_state[state_index].clock_info[0].sclk =
2739 rdev->clock.default_sclk;
2740 mode_index++;
2741 }
2742 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2743 if (mode_index) {
2744 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2745 non_clock_info);
2746 state_index++;
2747 }
2748 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2749 }
2750 /* if multiple clock modes, mark the lowest as no display */
2751 for (i = 0; i < state_index; i++) {
2752 if (rdev->pm.power_state[i].num_clock_modes > 1)
2753 rdev->pm.power_state[i].clock_info[0].flags |=
2754 RADEON_PM_MODE_NO_DISPLAY;
2755 }
2756 /* first mode is usually default */
2757 if (rdev->pm.default_power_state_index == -1) {
2758 rdev->pm.power_state[0].type =
2759 POWER_STATE_TYPE_DEFAULT;
2760 rdev->pm.default_power_state_index = 0;
2761 rdev->pm.power_state[0].default_clock_mode =
2762 &rdev->pm.power_state[0].clock_info[0];
2763 }
2764 return state_index;
2765 }
2766
radeon_atombios_get_power_modes(struct radeon_device * rdev)2767 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2768 {
2769 struct radeon_mode_info *mode_info = &rdev->mode_info;
2770 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2771 u16 data_offset;
2772 u8 frev, crev;
2773 int state_index = 0;
2774
2775 rdev->pm.default_power_state_index = -1;
2776
2777 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2778 &frev, &crev, &data_offset)) {
2779 switch (frev) {
2780 case 1:
2781 case 2:
2782 case 3:
2783 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2784 break;
2785 case 4:
2786 case 5:
2787 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2788 break;
2789 case 6:
2790 state_index = radeon_atombios_parse_power_table_6(rdev);
2791 break;
2792 default:
2793 break;
2794 }
2795 }
2796
2797 if (state_index == 0) {
2798 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2799 if (rdev->pm.power_state) {
2800 rdev->pm.power_state[0].clock_info =
2801 kcalloc(1,
2802 sizeof(struct radeon_pm_clock_info),
2803 GFP_KERNEL);
2804 if (rdev->pm.power_state[0].clock_info) {
2805 /* add the default mode */
2806 rdev->pm.power_state[state_index].type =
2807 POWER_STATE_TYPE_DEFAULT;
2808 rdev->pm.power_state[state_index].num_clock_modes = 1;
2809 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2810 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2811 rdev->pm.power_state[state_index].default_clock_mode =
2812 &rdev->pm.power_state[state_index].clock_info[0];
2813 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2814 rdev->pm.power_state[state_index].pcie_lanes = 16;
2815 rdev->pm.default_power_state_index = state_index;
2816 rdev->pm.power_state[state_index].flags = 0;
2817 state_index++;
2818 }
2819 }
2820 }
2821
2822 rdev->pm.num_power_states = state_index;
2823
2824 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2825 rdev->pm.current_clock_mode_index = 0;
2826 if (rdev->pm.default_power_state_index >= 0)
2827 rdev->pm.current_vddc =
2828 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2829 else
2830 rdev->pm.current_vddc = 0;
2831 }
2832
2833 union get_clock_dividers {
2834 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2835 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2836 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2837 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2838 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2839 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2840 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2841 };
2842
radeon_atom_get_clock_dividers(struct radeon_device * rdev,u8 clock_type,u32 clock,bool strobe_mode,struct atom_clock_dividers * dividers)2843 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2844 u8 clock_type,
2845 u32 clock,
2846 bool strobe_mode,
2847 struct atom_clock_dividers *dividers)
2848 {
2849 union get_clock_dividers args;
2850 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2851 u8 frev, crev;
2852
2853 memset(&args, 0, sizeof(args));
2854 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2855
2856 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2857 return -EINVAL;
2858
2859 switch (crev) {
2860 case 1:
2861 /* r4xx, r5xx */
2862 args.v1.ucAction = clock_type;
2863 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
2864
2865 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2866
2867 dividers->post_div = args.v1.ucPostDiv;
2868 dividers->fb_div = args.v1.ucFbDiv;
2869 dividers->enable_post_div = true;
2870 break;
2871 case 2:
2872 case 3:
2873 case 5:
2874 /* r6xx, r7xx, evergreen, ni, si */
2875 if (rdev->family <= CHIP_RV770) {
2876 args.v2.ucAction = clock_type;
2877 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
2878
2879 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2880
2881 dividers->post_div = args.v2.ucPostDiv;
2882 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2883 dividers->ref_div = args.v2.ucAction;
2884 if (rdev->family == CHIP_RV770) {
2885 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2886 true : false;
2887 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2888 } else
2889 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2890 } else {
2891 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2892 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2893
2894 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2895
2896 dividers->post_div = args.v3.ucPostDiv;
2897 dividers->enable_post_div = (args.v3.ucCntlFlag &
2898 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2899 dividers->enable_dithen = (args.v3.ucCntlFlag &
2900 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2901 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2902 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2903 dividers->ref_div = args.v3.ucRefDiv;
2904 dividers->vco_mode = (args.v3.ucCntlFlag &
2905 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2906 } else {
2907 /* for SI we use ComputeMemoryClockParam for memory plls */
2908 if (rdev->family >= CHIP_TAHITI)
2909 return -EINVAL;
2910 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2911 if (strobe_mode)
2912 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2913
2914 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2915
2916 dividers->post_div = args.v5.ucPostDiv;
2917 dividers->enable_post_div = (args.v5.ucCntlFlag &
2918 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2919 dividers->enable_dithen = (args.v5.ucCntlFlag &
2920 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2921 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2922 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2923 dividers->ref_div = args.v5.ucRefDiv;
2924 dividers->vco_mode = (args.v5.ucCntlFlag &
2925 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2926 }
2927 }
2928 break;
2929 case 4:
2930 /* fusion */
2931 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
2932
2933 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2934
2935 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2936 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2937 break;
2938 case 6:
2939 /* CI */
2940 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2941 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2942 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2943
2944 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2945
2946 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2947 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2948 dividers->ref_div = args.v6_out.ucPllRefDiv;
2949 dividers->post_div = args.v6_out.ucPllPostDiv;
2950 dividers->flags = args.v6_out.ucPllCntlFlag;
2951 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2952 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2953 break;
2954 default:
2955 return -EINVAL;
2956 }
2957 return 0;
2958 }
2959
radeon_atom_get_memory_pll_dividers(struct radeon_device * rdev,u32 clock,bool strobe_mode,struct atom_mpll_param * mpll_param)2960 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2961 u32 clock,
2962 bool strobe_mode,
2963 struct atom_mpll_param *mpll_param)
2964 {
2965 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2966 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2967 u8 frev, crev;
2968
2969 memset(&args, 0, sizeof(args));
2970 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2971
2972 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2973 return -EINVAL;
2974
2975 switch (frev) {
2976 case 2:
2977 switch (crev) {
2978 case 1:
2979 /* SI */
2980 args.ulClock = cpu_to_le32(clock); /* 10 khz */
2981 args.ucInputFlag = 0;
2982 if (strobe_mode)
2983 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2984
2985 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2986
2987 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2988 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2989 mpll_param->post_div = args.ucPostDiv;
2990 mpll_param->dll_speed = args.ucDllSpeed;
2991 mpll_param->bwcntl = args.ucBWCntl;
2992 mpll_param->vco_mode =
2993 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
2994 mpll_param->yclk_sel =
2995 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2996 mpll_param->qdr =
2997 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2998 mpll_param->half_rate =
2999 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
3000 break;
3001 default:
3002 return -EINVAL;
3003 }
3004 break;
3005 default:
3006 return -EINVAL;
3007 }
3008 return 0;
3009 }
3010
radeon_atom_set_clock_gating(struct radeon_device * rdev,int enable)3011 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
3012 {
3013 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
3014 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
3015
3016 args.ucEnable = enable;
3017
3018 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3019 }
3020
radeon_atom_get_engine_clock(struct radeon_device * rdev)3021 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
3022 {
3023 GET_ENGINE_CLOCK_PS_ALLOCATION args;
3024 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
3025
3026 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3027 return le32_to_cpu(args.ulReturnEngineClock);
3028 }
3029
radeon_atom_get_memory_clock(struct radeon_device * rdev)3030 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
3031 {
3032 GET_MEMORY_CLOCK_PS_ALLOCATION args;
3033 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
3034
3035 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3036 return le32_to_cpu(args.ulReturnMemoryClock);
3037 }
3038
radeon_atom_set_engine_clock(struct radeon_device * rdev,uint32_t eng_clock)3039 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
3040 uint32_t eng_clock)
3041 {
3042 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3043 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
3044
3045 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
3046
3047 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3048 }
3049
radeon_atom_set_memory_clock(struct radeon_device * rdev,uint32_t mem_clock)3050 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
3051 uint32_t mem_clock)
3052 {
3053 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3054 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
3055
3056 if (rdev->flags & RADEON_IS_IGP)
3057 return;
3058
3059 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
3060
3061 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3062 }
3063
radeon_atom_set_engine_dram_timings(struct radeon_device * rdev,u32 eng_clock,u32 mem_clock)3064 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
3065 u32 eng_clock, u32 mem_clock)
3066 {
3067 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3068 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3069 u32 tmp;
3070
3071 memset(&args, 0, sizeof(args));
3072
3073 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
3074 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
3075
3076 args.ulTargetEngineClock = cpu_to_le32(tmp);
3077 if (mem_clock)
3078 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
3079
3080 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3081 }
3082
radeon_atom_update_memory_dll(struct radeon_device * rdev,u32 mem_clock)3083 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3084 u32 mem_clock)
3085 {
3086 u32 args;
3087 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3088
3089 args = cpu_to_le32(mem_clock); /* 10 khz */
3090
3091 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3092 }
3093
radeon_atom_set_ac_timing(struct radeon_device * rdev,u32 mem_clock)3094 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3095 u32 mem_clock)
3096 {
3097 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3098 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3099 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
3100
3101 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */
3102
3103 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3104 }
3105
3106 union set_voltage {
3107 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
3108 struct _SET_VOLTAGE_PARAMETERS v1;
3109 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
3110 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
3111 };
3112
radeon_atom_set_voltage(struct radeon_device * rdev,u16 voltage_level,u8 voltage_type)3113 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3114 {
3115 union set_voltage args;
3116 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3117 u8 frev, crev, volt_index = voltage_level;
3118
3119 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3120 return;
3121
3122 /* 0xff01 is a flag rather then an actual voltage */
3123 if (voltage_level == 0xff01)
3124 return;
3125
3126 switch (crev) {
3127 case 1:
3128 args.v1.ucVoltageType = voltage_type;
3129 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3130 args.v1.ucVoltageIndex = volt_index;
3131 break;
3132 case 2:
3133 args.v2.ucVoltageType = voltage_type;
3134 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3135 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3136 break;
3137 case 3:
3138 args.v3.ucVoltageType = voltage_type;
3139 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3140 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3141 break;
3142 default:
3143 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3144 return;
3145 }
3146
3147 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3148 }
3149
radeon_atom_get_max_vddc(struct radeon_device * rdev,u8 voltage_type,u16 voltage_id,u16 * voltage)3150 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3151 u16 voltage_id, u16 *voltage)
3152 {
3153 union set_voltage args;
3154 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3155 u8 frev, crev;
3156
3157 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3158 return -EINVAL;
3159
3160 switch (crev) {
3161 case 1:
3162 return -EINVAL;
3163 case 2:
3164 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3165 args.v2.ucVoltageMode = 0;
3166 args.v2.usVoltageLevel = 0;
3167
3168 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3169
3170 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3171 break;
3172 case 3:
3173 args.v3.ucVoltageType = voltage_type;
3174 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3175 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3176
3177 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3178
3179 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3180 break;
3181 default:
3182 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3183 return -EINVAL;
3184 }
3185
3186 return 0;
3187 }
3188
radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device * rdev,u16 * voltage,u16 leakage_idx)3189 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3190 u16 *voltage,
3191 u16 leakage_idx)
3192 {
3193 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3194 }
3195
radeon_atom_get_leakage_id_from_vbios(struct radeon_device * rdev,u16 * leakage_id)3196 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3197 u16 *leakage_id)
3198 {
3199 union set_voltage args;
3200 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3201 u8 frev, crev;
3202
3203 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3204 return -EINVAL;
3205
3206 switch (crev) {
3207 case 3:
3208 case 4:
3209 args.v3.ucVoltageType = 0;
3210 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
3211 args.v3.usVoltageLevel = 0;
3212
3213 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3214
3215 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
3216 break;
3217 default:
3218 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3219 return -EINVAL;
3220 }
3221
3222 return 0;
3223 }
3224
radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device * rdev,u16 * vddc,u16 * vddci,u16 virtual_voltage_id,u16 vbios_voltage_id)3225 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3226 u16 *vddc, u16 *vddci,
3227 u16 virtual_voltage_id,
3228 u16 vbios_voltage_id)
3229 {
3230 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
3231 u8 frev, crev;
3232 u16 data_offset, size;
3233 int i, j;
3234 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
3235 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
3236
3237 *vddc = 0;
3238 *vddci = 0;
3239
3240 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3241 &frev, &crev, &data_offset))
3242 return -EINVAL;
3243
3244 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
3245 (rdev->mode_info.atom_context->bios + data_offset);
3246
3247 switch (frev) {
3248 case 1:
3249 return -EINVAL;
3250 case 2:
3251 switch (crev) {
3252 case 1:
3253 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
3254 return -EINVAL;
3255 leakage_bin = (u16 *)
3256 (rdev->mode_info.atom_context->bios + data_offset +
3257 le16_to_cpu(profile->usLeakageBinArrayOffset));
3258 vddc_id_buf = (u16 *)
3259 (rdev->mode_info.atom_context->bios + data_offset +
3260 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
3261 vddc_buf = (u16 *)
3262 (rdev->mode_info.atom_context->bios + data_offset +
3263 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
3264 vddci_id_buf = (u16 *)
3265 (rdev->mode_info.atom_context->bios + data_offset +
3266 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
3267 vddci_buf = (u16 *)
3268 (rdev->mode_info.atom_context->bios + data_offset +
3269 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
3270
3271 if (profile->ucElbVDDC_Num > 0) {
3272 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
3273 if (vddc_id_buf[i] == virtual_voltage_id) {
3274 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3275 if (vbios_voltage_id <= leakage_bin[j]) {
3276 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
3277 break;
3278 }
3279 }
3280 break;
3281 }
3282 }
3283 }
3284 if (profile->ucElbVDDCI_Num > 0) {
3285 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
3286 if (vddci_id_buf[i] == virtual_voltage_id) {
3287 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3288 if (vbios_voltage_id <= leakage_bin[j]) {
3289 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
3290 break;
3291 }
3292 }
3293 break;
3294 }
3295 }
3296 }
3297 break;
3298 default:
3299 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3300 return -EINVAL;
3301 }
3302 break;
3303 default:
3304 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3305 return -EINVAL;
3306 }
3307
3308 return 0;
3309 }
3310
3311 union get_voltage_info {
3312 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
3313 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
3314 };
3315
radeon_atom_get_voltage_evv(struct radeon_device * rdev,u16 virtual_voltage_id,u16 * voltage)3316 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
3317 u16 virtual_voltage_id,
3318 u16 *voltage)
3319 {
3320 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
3321 u32 entry_id;
3322 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
3323 union get_voltage_info args;
3324
3325 for (entry_id = 0; entry_id < count; entry_id++) {
3326 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
3327 virtual_voltage_id)
3328 break;
3329 }
3330
3331 if (entry_id >= count)
3332 return -EINVAL;
3333
3334 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
3335 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
3336 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
3337 args.in.ulSCLKFreq =
3338 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
3339
3340 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3341
3342 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
3343
3344 return 0;
3345 }
3346
radeon_atom_get_voltage_gpio_settings(struct radeon_device * rdev,u16 voltage_level,u8 voltage_type,u32 * gpio_value,u32 * gpio_mask)3347 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3348 u16 voltage_level, u8 voltage_type,
3349 u32 *gpio_value, u32 *gpio_mask)
3350 {
3351 union set_voltage args;
3352 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3353 u8 frev, crev;
3354
3355 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3356 return -EINVAL;
3357
3358 switch (crev) {
3359 case 1:
3360 return -EINVAL;
3361 case 2:
3362 args.v2.ucVoltageType = voltage_type;
3363 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3364 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3365
3366 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3367
3368 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3369
3370 args.v2.ucVoltageType = voltage_type;
3371 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3372 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3373
3374 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3375
3376 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3377 break;
3378 default:
3379 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3380 return -EINVAL;
3381 }
3382
3383 return 0;
3384 }
3385
3386 union voltage_object_info {
3387 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3388 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3389 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3390 };
3391
3392 union voltage_object {
3393 struct _ATOM_VOLTAGE_OBJECT v1;
3394 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3395 union _ATOM_VOLTAGE_OBJECT_V3 v3;
3396 };
3397
atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO * v1,u8 voltage_type)3398 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3399 u8 voltage_type)
3400 {
3401 u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3402 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3403 u8 *start = (u8 *)v1;
3404
3405 while (offset < size) {
3406 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3407 if (vo->ucVoltageType == voltage_type)
3408 return vo;
3409 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3410 vo->asFormula.ucNumOfVoltageEntries;
3411 }
3412 return NULL;
3413 }
3414
atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 * v2,u8 voltage_type)3415 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3416 u8 voltage_type)
3417 {
3418 u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3419 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3420 u8 *start = (u8 *)v2;
3421
3422 while (offset < size) {
3423 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3424 if (vo->ucVoltageType == voltage_type)
3425 return vo;
3426 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3427 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3428 }
3429 return NULL;
3430 }
3431
atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 * v3,u8 voltage_type,u8 voltage_mode)3432 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3433 u8 voltage_type, u8 voltage_mode)
3434 {
3435 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3436 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3437 u8 *start = (u8 *)v3;
3438
3439 while (offset < size) {
3440 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3441 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3442 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3443 return vo;
3444 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3445 }
3446 return NULL;
3447 }
3448
3449 bool
radeon_atom_is_voltage_gpio(struct radeon_device * rdev,u8 voltage_type,u8 voltage_mode)3450 radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3451 u8 voltage_type, u8 voltage_mode)
3452 {
3453 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3454 u8 frev, crev;
3455 u16 data_offset, size;
3456 union voltage_object_info *voltage_info;
3457 union voltage_object *voltage_object = NULL;
3458
3459 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3460 &frev, &crev, &data_offset)) {
3461 voltage_info = (union voltage_object_info *)
3462 (rdev->mode_info.atom_context->bios + data_offset);
3463
3464 switch (frev) {
3465 case 1:
3466 case 2:
3467 switch (crev) {
3468 case 1:
3469 voltage_object = (union voltage_object *)
3470 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3471 if (voltage_object &&
3472 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3473 return true;
3474 break;
3475 case 2:
3476 voltage_object = (union voltage_object *)
3477 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3478 if (voltage_object &&
3479 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3480 return true;
3481 break;
3482 default:
3483 DRM_ERROR("unknown voltage object table\n");
3484 return false;
3485 }
3486 break;
3487 case 3:
3488 switch (crev) {
3489 case 1:
3490 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3491 voltage_type, voltage_mode))
3492 return true;
3493 break;
3494 default:
3495 DRM_ERROR("unknown voltage object table\n");
3496 return false;
3497 }
3498 break;
3499 default:
3500 DRM_ERROR("unknown voltage object table\n");
3501 return false;
3502 }
3503
3504 }
3505 return false;
3506 }
3507
radeon_atom_get_svi2_info(struct radeon_device * rdev,u8 voltage_type,u8 * svd_gpio_id,u8 * svc_gpio_id)3508 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
3509 u8 voltage_type,
3510 u8 *svd_gpio_id, u8 *svc_gpio_id)
3511 {
3512 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3513 u8 frev, crev;
3514 u16 data_offset, size;
3515 union voltage_object_info *voltage_info;
3516 union voltage_object *voltage_object = NULL;
3517
3518 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3519 &frev, &crev, &data_offset)) {
3520 voltage_info = (union voltage_object_info *)
3521 (rdev->mode_info.atom_context->bios + data_offset);
3522
3523 switch (frev) {
3524 case 3:
3525 switch (crev) {
3526 case 1:
3527 voltage_object = (union voltage_object *)
3528 atom_lookup_voltage_object_v3(&voltage_info->v3,
3529 voltage_type,
3530 VOLTAGE_OBJ_SVID2);
3531 if (voltage_object) {
3532 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
3533 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
3534 } else {
3535 return -EINVAL;
3536 }
3537 break;
3538 default:
3539 DRM_ERROR("unknown voltage object table\n");
3540 return -EINVAL;
3541 }
3542 break;
3543 default:
3544 DRM_ERROR("unknown voltage object table\n");
3545 return -EINVAL;
3546 }
3547
3548 }
3549 return 0;
3550 }
3551
radeon_atom_get_max_voltage(struct radeon_device * rdev,u8 voltage_type,u16 * max_voltage)3552 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3553 u8 voltage_type, u16 *max_voltage)
3554 {
3555 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3556 u8 frev, crev;
3557 u16 data_offset, size;
3558 union voltage_object_info *voltage_info;
3559 union voltage_object *voltage_object = NULL;
3560
3561 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3562 &frev, &crev, &data_offset)) {
3563 voltage_info = (union voltage_object_info *)
3564 (rdev->mode_info.atom_context->bios + data_offset);
3565
3566 switch (crev) {
3567 case 1:
3568 voltage_object = (union voltage_object *)
3569 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3570 if (voltage_object) {
3571 ATOM_VOLTAGE_FORMULA *formula =
3572 &voltage_object->v1.asFormula;
3573 if (formula->ucFlag & 1)
3574 *max_voltage =
3575 le16_to_cpu(formula->usVoltageBaseLevel) +
3576 formula->ucNumOfVoltageEntries / 2 *
3577 le16_to_cpu(formula->usVoltageStep);
3578 else
3579 *max_voltage =
3580 le16_to_cpu(formula->usVoltageBaseLevel) +
3581 (formula->ucNumOfVoltageEntries - 1) *
3582 le16_to_cpu(formula->usVoltageStep);
3583 return 0;
3584 }
3585 break;
3586 case 2:
3587 voltage_object = (union voltage_object *)
3588 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3589 if (voltage_object) {
3590 ATOM_VOLTAGE_FORMULA_V2 *formula =
3591 &voltage_object->v2.asFormula;
3592 if (formula->ucNumOfVoltageEntries) {
3593 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *)
3594 ((u8 *)&formula->asVIDAdjustEntries[0] +
3595 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
3596 *max_voltage =
3597 le16_to_cpu(lut->usVoltageValue);
3598 return 0;
3599 }
3600 }
3601 break;
3602 default:
3603 DRM_ERROR("unknown voltage object table\n");
3604 return -EINVAL;
3605 }
3606
3607 }
3608 return -EINVAL;
3609 }
3610
radeon_atom_get_min_voltage(struct radeon_device * rdev,u8 voltage_type,u16 * min_voltage)3611 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3612 u8 voltage_type, u16 *min_voltage)
3613 {
3614 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3615 u8 frev, crev;
3616 u16 data_offset, size;
3617 union voltage_object_info *voltage_info;
3618 union voltage_object *voltage_object = NULL;
3619
3620 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3621 &frev, &crev, &data_offset)) {
3622 voltage_info = (union voltage_object_info *)
3623 (rdev->mode_info.atom_context->bios + data_offset);
3624
3625 switch (crev) {
3626 case 1:
3627 voltage_object = (union voltage_object *)
3628 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3629 if (voltage_object) {
3630 ATOM_VOLTAGE_FORMULA *formula =
3631 &voltage_object->v1.asFormula;
3632 *min_voltage =
3633 le16_to_cpu(formula->usVoltageBaseLevel);
3634 return 0;
3635 }
3636 break;
3637 case 2:
3638 voltage_object = (union voltage_object *)
3639 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3640 if (voltage_object) {
3641 ATOM_VOLTAGE_FORMULA_V2 *formula =
3642 &voltage_object->v2.asFormula;
3643 if (formula->ucNumOfVoltageEntries) {
3644 *min_voltage =
3645 le16_to_cpu(formula->asVIDAdjustEntries[
3646 0
3647 ].usVoltageValue);
3648 return 0;
3649 }
3650 }
3651 break;
3652 default:
3653 DRM_ERROR("unknown voltage object table\n");
3654 return -EINVAL;
3655 }
3656
3657 }
3658 return -EINVAL;
3659 }
3660
radeon_atom_get_voltage_step(struct radeon_device * rdev,u8 voltage_type,u16 * voltage_step)3661 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3662 u8 voltage_type, u16 *voltage_step)
3663 {
3664 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3665 u8 frev, crev;
3666 u16 data_offset, size;
3667 union voltage_object_info *voltage_info;
3668 union voltage_object *voltage_object = NULL;
3669
3670 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3671 &frev, &crev, &data_offset)) {
3672 voltage_info = (union voltage_object_info *)
3673 (rdev->mode_info.atom_context->bios + data_offset);
3674
3675 switch (crev) {
3676 case 1:
3677 voltage_object = (union voltage_object *)
3678 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3679 if (voltage_object) {
3680 ATOM_VOLTAGE_FORMULA *formula =
3681 &voltage_object->v1.asFormula;
3682 if (formula->ucFlag & 1)
3683 *voltage_step =
3684 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3685 else
3686 *voltage_step =
3687 le16_to_cpu(formula->usVoltageStep);
3688 return 0;
3689 }
3690 break;
3691 case 2:
3692 return -EINVAL;
3693 default:
3694 DRM_ERROR("unknown voltage object table\n");
3695 return -EINVAL;
3696 }
3697
3698 }
3699 return -EINVAL;
3700 }
3701
radeon_atom_round_to_true_voltage(struct radeon_device * rdev,u8 voltage_type,u16 nominal_voltage,u16 * true_voltage)3702 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3703 u8 voltage_type,
3704 u16 nominal_voltage,
3705 u16 *true_voltage)
3706 {
3707 u16 min_voltage, max_voltage, voltage_step;
3708
3709 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3710 return -EINVAL;
3711 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3712 return -EINVAL;
3713 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3714 return -EINVAL;
3715
3716 if (nominal_voltage <= min_voltage)
3717 *true_voltage = min_voltage;
3718 else if (nominal_voltage >= max_voltage)
3719 *true_voltage = max_voltage;
3720 else
3721 *true_voltage = min_voltage +
3722 ((nominal_voltage - min_voltage) / voltage_step) *
3723 voltage_step;
3724
3725 return 0;
3726 }
3727
radeon_atom_get_voltage_table(struct radeon_device * rdev,u8 voltage_type,u8 voltage_mode,struct atom_voltage_table * voltage_table)3728 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3729 u8 voltage_type, u8 voltage_mode,
3730 struct atom_voltage_table *voltage_table)
3731 {
3732 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3733 u8 frev, crev;
3734 u16 data_offset, size;
3735 int i, ret;
3736 union voltage_object_info *voltage_info;
3737 union voltage_object *voltage_object = NULL;
3738
3739 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3740 &frev, &crev, &data_offset)) {
3741 voltage_info = (union voltage_object_info *)
3742 (rdev->mode_info.atom_context->bios + data_offset);
3743
3744 switch (frev) {
3745 case 1:
3746 case 2:
3747 switch (crev) {
3748 case 1:
3749 DRM_ERROR("old table version %d, %d\n", frev, crev);
3750 return -EINVAL;
3751 case 2:
3752 voltage_object = (union voltage_object *)
3753 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3754 if (voltage_object) {
3755 ATOM_VOLTAGE_FORMULA_V2 *formula =
3756 &voltage_object->v2.asFormula;
3757 VOLTAGE_LUT_ENTRY *lut;
3758 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3759 return -EINVAL;
3760 lut = &formula->asVIDAdjustEntries[0];
3761 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3762 voltage_table->entries[i].value =
3763 le16_to_cpu(lut->usVoltageValue);
3764 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3765 voltage_table->entries[i].value,
3766 voltage_type,
3767 &voltage_table->entries[i].smio_low,
3768 &voltage_table->mask_low);
3769 if (ret)
3770 return ret;
3771 lut = (VOLTAGE_LUT_ENTRY *)
3772 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
3773 }
3774 voltage_table->count = formula->ucNumOfVoltageEntries;
3775 return 0;
3776 }
3777 break;
3778 default:
3779 DRM_ERROR("unknown voltage object table\n");
3780 return -EINVAL;
3781 }
3782 break;
3783 case 3:
3784 switch (crev) {
3785 case 1:
3786 voltage_object = (union voltage_object *)
3787 atom_lookup_voltage_object_v3(&voltage_info->v3,
3788 voltage_type, voltage_mode);
3789 if (voltage_object) {
3790 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3791 &voltage_object->v3.asGpioVoltageObj;
3792 VOLTAGE_LUT_ENTRY_V2 *lut;
3793 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3794 return -EINVAL;
3795 lut = &gpio->asVolGpioLut[0];
3796 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3797 voltage_table->entries[i].value =
3798 le16_to_cpu(lut->usVoltageValue);
3799 voltage_table->entries[i].smio_low =
3800 le32_to_cpu(lut->ulVoltageId);
3801 lut = (VOLTAGE_LUT_ENTRY_V2 *)
3802 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
3803 }
3804 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3805 voltage_table->count = gpio->ucGpioEntryNum;
3806 voltage_table->phase_delay = gpio->ucPhaseDelay;
3807 return 0;
3808 }
3809 break;
3810 default:
3811 DRM_ERROR("unknown voltage object table\n");
3812 return -EINVAL;
3813 }
3814 break;
3815 default:
3816 DRM_ERROR("unknown voltage object table\n");
3817 return -EINVAL;
3818 }
3819 }
3820 return -EINVAL;
3821 }
3822
3823 union vram_info {
3824 struct _ATOM_VRAM_INFO_V3 v1_3;
3825 struct _ATOM_VRAM_INFO_V4 v1_4;
3826 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3827 };
3828
radeon_atom_get_memory_info(struct radeon_device * rdev,u8 module_index,struct atom_memory_info * mem_info)3829 int radeon_atom_get_memory_info(struct radeon_device *rdev,
3830 u8 module_index, struct atom_memory_info *mem_info)
3831 {
3832 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3833 u8 frev, crev, i;
3834 u16 data_offset, size;
3835 union vram_info *vram_info;
3836
3837 memset(mem_info, 0, sizeof(struct atom_memory_info));
3838
3839 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3840 &frev, &crev, &data_offset)) {
3841 vram_info = (union vram_info *)
3842 (rdev->mode_info.atom_context->bios + data_offset);
3843 switch (frev) {
3844 case 1:
3845 switch (crev) {
3846 case 3:
3847 /* r6xx */
3848 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3849 ATOM_VRAM_MODULE_V3 *vram_module =
3850 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3851
3852 for (i = 0; i < module_index; i++) {
3853 if (le16_to_cpu(vram_module->usSize) == 0)
3854 return -EINVAL;
3855 vram_module = (ATOM_VRAM_MODULE_V3 *)
3856 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3857 }
3858 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3859 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3860 } else
3861 return -EINVAL;
3862 break;
3863 case 4:
3864 /* r7xx, evergreen */
3865 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3866 ATOM_VRAM_MODULE_V4 *vram_module =
3867 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3868
3869 for (i = 0; i < module_index; i++) {
3870 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3871 return -EINVAL;
3872 vram_module = (ATOM_VRAM_MODULE_V4 *)
3873 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3874 }
3875 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3876 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3877 } else
3878 return -EINVAL;
3879 break;
3880 default:
3881 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3882 return -EINVAL;
3883 }
3884 break;
3885 case 2:
3886 switch (crev) {
3887 case 1:
3888 /* ni */
3889 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3890 ATOM_VRAM_MODULE_V7 *vram_module =
3891 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3892
3893 for (i = 0; i < module_index; i++) {
3894 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3895 return -EINVAL;
3896 vram_module = (ATOM_VRAM_MODULE_V7 *)
3897 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3898 }
3899 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3900 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3901 } else
3902 return -EINVAL;
3903 break;
3904 default:
3905 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3906 return -EINVAL;
3907 }
3908 break;
3909 default:
3910 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3911 return -EINVAL;
3912 }
3913 return 0;
3914 }
3915 return -EINVAL;
3916 }
3917
radeon_atom_get_mclk_range_table(struct radeon_device * rdev,bool gddr5,u8 module_index,struct atom_memory_clock_range_table * mclk_range_table)3918 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3919 bool gddr5, u8 module_index,
3920 struct atom_memory_clock_range_table *mclk_range_table)
3921 {
3922 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3923 u8 frev, crev, i;
3924 u16 data_offset, size;
3925 union vram_info *vram_info;
3926 u32 mem_timing_size = gddr5 ?
3927 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3928
3929 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3930
3931 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3932 &frev, &crev, &data_offset)) {
3933 vram_info = (union vram_info *)
3934 (rdev->mode_info.atom_context->bios + data_offset);
3935 switch (frev) {
3936 case 1:
3937 switch (crev) {
3938 case 3:
3939 DRM_ERROR("old table version %d, %d\n", frev, crev);
3940 return -EINVAL;
3941 case 4:
3942 /* r7xx, evergreen */
3943 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3944 ATOM_VRAM_MODULE_V4 *vram_module =
3945 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3946 ATOM_MEMORY_TIMING_FORMAT *format;
3947
3948 for (i = 0; i < module_index; i++) {
3949 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3950 return -EINVAL;
3951 vram_module = (ATOM_VRAM_MODULE_V4 *)
3952 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3953 }
3954 mclk_range_table->num_entries = (u8)
3955 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3956 mem_timing_size);
3957 format = &vram_module->asMemTiming[0];
3958 for (i = 0; i < mclk_range_table->num_entries; i++) {
3959 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3960 format = (ATOM_MEMORY_TIMING_FORMAT *)
3961 ((u8 *)format + mem_timing_size);
3962 }
3963 } else
3964 return -EINVAL;
3965 break;
3966 default:
3967 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3968 return -EINVAL;
3969 }
3970 break;
3971 case 2:
3972 DRM_ERROR("new table version %d, %d\n", frev, crev);
3973 return -EINVAL;
3974 default:
3975 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3976 return -EINVAL;
3977 }
3978 return 0;
3979 }
3980 return -EINVAL;
3981 }
3982
3983 #define MEM_ID_MASK 0xff000000
3984 #define MEM_ID_SHIFT 24
3985 #define CLOCK_RANGE_MASK 0x00ffffff
3986 #define CLOCK_RANGE_SHIFT 0
3987 #define LOW_NIBBLE_MASK 0xf
3988 #define DATA_EQU_PREV 0
3989 #define DATA_FROM_TABLE 4
3990
radeon_atom_init_mc_reg_table(struct radeon_device * rdev,u8 module_index,struct atom_mc_reg_table * reg_table)3991 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3992 u8 module_index,
3993 struct atom_mc_reg_table *reg_table)
3994 {
3995 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3996 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3997 u32 i = 0, j;
3998 u16 data_offset, size;
3999 union vram_info *vram_info;
4000
4001 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
4002
4003 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
4004 &frev, &crev, &data_offset)) {
4005 vram_info = (union vram_info *)
4006 (rdev->mode_info.atom_context->bios + data_offset);
4007 switch (frev) {
4008 case 1:
4009 DRM_ERROR("old table version %d, %d\n", frev, crev);
4010 return -EINVAL;
4011 case 2:
4012 switch (crev) {
4013 case 1:
4014 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
4015 ATOM_INIT_REG_BLOCK *reg_block =
4016 (ATOM_INIT_REG_BLOCK *)
4017 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
4018 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
4019 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4020 ((u8 *)reg_block + (2 * sizeof(u16)) +
4021 le16_to_cpu(reg_block->usRegIndexTblSize));
4022 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
4023 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
4024 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
4025 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
4026 return -EINVAL;
4027 while (i < num_entries) {
4028 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
4029 break;
4030 reg_table->mc_reg_address[i].s1 =
4031 (u16)(le16_to_cpu(format->usRegIndex));
4032 reg_table->mc_reg_address[i].pre_reg_data =
4033 (u8)(format->ucPreRegDataLength);
4034 i++;
4035 format = (ATOM_INIT_REG_INDEX_FORMAT *)
4036 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
4037 }
4038 reg_table->last = i;
4039 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
4040 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
4041 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
4042 >> MEM_ID_SHIFT);
4043 if (module_index == t_mem_id) {
4044 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
4045 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
4046 >> CLOCK_RANGE_SHIFT);
4047 for (i = 0, j = 1; i < reg_table->last; i++) {
4048 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
4049 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4050 (u32)le32_to_cpu(*((u32 *)reg_data + j));
4051 j++;
4052 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
4053 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4054 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
4055 }
4056 }
4057 num_ranges++;
4058 }
4059 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4060 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
4061 }
4062 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
4063 return -EINVAL;
4064 reg_table->num_entries = num_ranges;
4065 } else
4066 return -EINVAL;
4067 break;
4068 default:
4069 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4070 return -EINVAL;
4071 }
4072 break;
4073 default:
4074 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4075 return -EINVAL;
4076 }
4077 return 0;
4078 }
4079 return -EINVAL;
4080 }
4081
radeon_atom_initialize_bios_scratch_regs(struct drm_device * dev)4082 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
4083 {
4084 struct radeon_device *rdev = dev->dev_private;
4085 uint32_t bios_2_scratch, bios_6_scratch;
4086
4087 if (rdev->family >= CHIP_R600) {
4088 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4089 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4090 } else {
4091 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4092 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4093 }
4094
4095 /* let the bios control the backlight */
4096 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
4097
4098 /* tell the bios not to handle mode switching */
4099 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
4100
4101 /* clear the vbios dpms state */
4102 if (ASIC_IS_DCE4(rdev))
4103 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
4104
4105 if (rdev->family >= CHIP_R600) {
4106 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4107 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4108 } else {
4109 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4110 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4111 }
4112
4113 }
4114
radeon_save_bios_scratch_regs(struct radeon_device * rdev)4115 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
4116 {
4117 uint32_t scratch_reg;
4118 int i;
4119
4120 if (rdev->family >= CHIP_R600)
4121 scratch_reg = R600_BIOS_0_SCRATCH;
4122 else
4123 scratch_reg = RADEON_BIOS_0_SCRATCH;
4124
4125 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4126 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
4127 }
4128
radeon_restore_bios_scratch_regs(struct radeon_device * rdev)4129 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
4130 {
4131 uint32_t scratch_reg;
4132 int i;
4133
4134 if (rdev->family >= CHIP_R600)
4135 scratch_reg = R600_BIOS_0_SCRATCH;
4136 else
4137 scratch_reg = RADEON_BIOS_0_SCRATCH;
4138
4139 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4140 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
4141 }
4142
radeon_atom_output_lock(struct drm_encoder * encoder,bool lock)4143 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
4144 {
4145 struct drm_device *dev = encoder->dev;
4146 struct radeon_device *rdev = dev->dev_private;
4147 uint32_t bios_6_scratch;
4148
4149 if (rdev->family >= CHIP_R600)
4150 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4151 else
4152 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4153
4154 if (lock) {
4155 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
4156 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
4157 } else {
4158 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
4159 bios_6_scratch |= ATOM_S6_ACC_MODE;
4160 }
4161
4162 if (rdev->family >= CHIP_R600)
4163 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4164 else
4165 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4166 }
4167
4168 /* at some point we may want to break this out into individual functions */
4169 void
radeon_atombios_connected_scratch_regs(struct drm_connector * connector,struct drm_encoder * encoder,bool connected)4170 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
4171 struct drm_encoder *encoder,
4172 bool connected)
4173 {
4174 struct drm_device *dev = connector->dev;
4175 struct radeon_device *rdev = dev->dev_private;
4176 struct radeon_connector *radeon_connector =
4177 to_radeon_connector(connector);
4178 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4179 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
4180
4181 if (rdev->family >= CHIP_R600) {
4182 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
4183 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4184 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4185 } else {
4186 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
4187 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4188 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4189 }
4190
4191 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
4192 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
4193 if (connected) {
4194 DRM_DEBUG_KMS("TV1 connected\n");
4195 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
4196 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
4197 } else {
4198 DRM_DEBUG_KMS("TV1 disconnected\n");
4199 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
4200 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
4201 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
4202 }
4203 }
4204 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
4205 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
4206 if (connected) {
4207 DRM_DEBUG_KMS("CV connected\n");
4208 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
4209 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
4210 } else {
4211 DRM_DEBUG_KMS("CV disconnected\n");
4212 bios_0_scratch &= ~ATOM_S0_CV_MASK;
4213 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
4214 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
4215 }
4216 }
4217 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
4218 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
4219 if (connected) {
4220 DRM_DEBUG_KMS("LCD1 connected\n");
4221 bios_0_scratch |= ATOM_S0_LCD1;
4222 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
4223 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
4224 } else {
4225 DRM_DEBUG_KMS("LCD1 disconnected\n");
4226 bios_0_scratch &= ~ATOM_S0_LCD1;
4227 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
4228 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
4229 }
4230 }
4231 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
4232 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
4233 if (connected) {
4234 DRM_DEBUG_KMS("CRT1 connected\n");
4235 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
4236 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
4237 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
4238 } else {
4239 DRM_DEBUG_KMS("CRT1 disconnected\n");
4240 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
4241 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
4242 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
4243 }
4244 }
4245 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
4246 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
4247 if (connected) {
4248 DRM_DEBUG_KMS("CRT2 connected\n");
4249 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
4250 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
4251 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
4252 } else {
4253 DRM_DEBUG_KMS("CRT2 disconnected\n");
4254 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
4255 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
4256 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
4257 }
4258 }
4259 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
4260 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
4261 if (connected) {
4262 DRM_DEBUG_KMS("DFP1 connected\n");
4263 bios_0_scratch |= ATOM_S0_DFP1;
4264 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
4265 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
4266 } else {
4267 DRM_DEBUG_KMS("DFP1 disconnected\n");
4268 bios_0_scratch &= ~ATOM_S0_DFP1;
4269 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
4270 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
4271 }
4272 }
4273 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
4274 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
4275 if (connected) {
4276 DRM_DEBUG_KMS("DFP2 connected\n");
4277 bios_0_scratch |= ATOM_S0_DFP2;
4278 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
4279 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
4280 } else {
4281 DRM_DEBUG_KMS("DFP2 disconnected\n");
4282 bios_0_scratch &= ~ATOM_S0_DFP2;
4283 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
4284 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
4285 }
4286 }
4287 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
4288 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
4289 if (connected) {
4290 DRM_DEBUG_KMS("DFP3 connected\n");
4291 bios_0_scratch |= ATOM_S0_DFP3;
4292 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
4293 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
4294 } else {
4295 DRM_DEBUG_KMS("DFP3 disconnected\n");
4296 bios_0_scratch &= ~ATOM_S0_DFP3;
4297 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
4298 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
4299 }
4300 }
4301 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
4302 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
4303 if (connected) {
4304 DRM_DEBUG_KMS("DFP4 connected\n");
4305 bios_0_scratch |= ATOM_S0_DFP4;
4306 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
4307 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
4308 } else {
4309 DRM_DEBUG_KMS("DFP4 disconnected\n");
4310 bios_0_scratch &= ~ATOM_S0_DFP4;
4311 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
4312 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
4313 }
4314 }
4315 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
4316 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
4317 if (connected) {
4318 DRM_DEBUG_KMS("DFP5 connected\n");
4319 bios_0_scratch |= ATOM_S0_DFP5;
4320 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
4321 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
4322 } else {
4323 DRM_DEBUG_KMS("DFP5 disconnected\n");
4324 bios_0_scratch &= ~ATOM_S0_DFP5;
4325 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
4326 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
4327 }
4328 }
4329 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4330 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4331 if (connected) {
4332 DRM_DEBUG_KMS("DFP6 connected\n");
4333 bios_0_scratch |= ATOM_S0_DFP6;
4334 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4335 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4336 } else {
4337 DRM_DEBUG_KMS("DFP6 disconnected\n");
4338 bios_0_scratch &= ~ATOM_S0_DFP6;
4339 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4340 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4341 }
4342 }
4343
4344 if (rdev->family >= CHIP_R600) {
4345 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4346 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4347 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4348 } else {
4349 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4350 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4351 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4352 }
4353 }
4354
4355 void
radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder * encoder,int crtc)4356 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4357 {
4358 struct drm_device *dev = encoder->dev;
4359 struct radeon_device *rdev = dev->dev_private;
4360 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4361 uint32_t bios_3_scratch;
4362
4363 if (ASIC_IS_DCE4(rdev))
4364 return;
4365
4366 if (rdev->family >= CHIP_R600)
4367 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4368 else
4369 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4370
4371 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4372 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4373 bios_3_scratch |= (crtc << 18);
4374 }
4375 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4376 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4377 bios_3_scratch |= (crtc << 24);
4378 }
4379 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4380 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4381 bios_3_scratch |= (crtc << 16);
4382 }
4383 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4384 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4385 bios_3_scratch |= (crtc << 20);
4386 }
4387 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4388 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4389 bios_3_scratch |= (crtc << 17);
4390 }
4391 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4392 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4393 bios_3_scratch |= (crtc << 19);
4394 }
4395 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4396 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4397 bios_3_scratch |= (crtc << 23);
4398 }
4399 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4400 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4401 bios_3_scratch |= (crtc << 25);
4402 }
4403
4404 if (rdev->family >= CHIP_R600)
4405 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4406 else
4407 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4408 }
4409
4410 void
radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder * encoder,bool on)4411 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4412 {
4413 struct drm_device *dev = encoder->dev;
4414 struct radeon_device *rdev = dev->dev_private;
4415 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4416 uint32_t bios_2_scratch;
4417
4418 if (ASIC_IS_DCE4(rdev))
4419 return;
4420
4421 if (rdev->family >= CHIP_R600)
4422 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4423 else
4424 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4425
4426 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4427 if (on)
4428 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4429 else
4430 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4431 }
4432 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4433 if (on)
4434 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4435 else
4436 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4437 }
4438 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4439 if (on)
4440 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4441 else
4442 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4443 }
4444 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4445 if (on)
4446 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4447 else
4448 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4449 }
4450 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4451 if (on)
4452 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4453 else
4454 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4455 }
4456 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4457 if (on)
4458 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4459 else
4460 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4461 }
4462 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4463 if (on)
4464 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4465 else
4466 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4467 }
4468 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4469 if (on)
4470 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4471 else
4472 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4473 }
4474 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4475 if (on)
4476 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4477 else
4478 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4479 }
4480 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4481 if (on)
4482 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4483 else
4484 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4485 }
4486
4487 if (rdev->family >= CHIP_R600)
4488 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4489 else
4490 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4491 }
4492