1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/slab.h>
29 #include <linux/seq_file.h>
30 #include <linux/firmware.h>
31 #include <linux/module.h>
32 #include <drm/drmP.h>
33 #include <drm/radeon_drm.h>
34 #include "radeon.h"
35 #include "radeon_asic.h"
36 #include "radeon_audio.h"
37 #include "radeon_mode.h"
38 #include "r600d.h"
39 #include "atom.h"
40 #include "avivod.h"
41 #include "radeon_ucode.h"
42
43 /* Firmware Names */
44 MODULE_FIRMWARE("radeon/R600_pfp.bin");
45 MODULE_FIRMWARE("radeon/R600_me.bin");
46 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
47 MODULE_FIRMWARE("radeon/RV610_me.bin");
48 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
49 MODULE_FIRMWARE("radeon/RV630_me.bin");
50 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
51 MODULE_FIRMWARE("radeon/RV620_me.bin");
52 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
53 MODULE_FIRMWARE("radeon/RV635_me.bin");
54 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
55 MODULE_FIRMWARE("radeon/RV670_me.bin");
56 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
57 MODULE_FIRMWARE("radeon/RS780_me.bin");
58 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
59 MODULE_FIRMWARE("radeon/RV770_me.bin");
60 MODULE_FIRMWARE("radeon/RV770_smc.bin");
61 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
62 MODULE_FIRMWARE("radeon/RV730_me.bin");
63 MODULE_FIRMWARE("radeon/RV730_smc.bin");
64 MODULE_FIRMWARE("radeon/RV740_smc.bin");
65 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
66 MODULE_FIRMWARE("radeon/RV710_me.bin");
67 MODULE_FIRMWARE("radeon/RV710_smc.bin");
68 MODULE_FIRMWARE("radeon/R600_rlc.bin");
69 MODULE_FIRMWARE("radeon/R700_rlc.bin");
70 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
71 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
72 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
73 MODULE_FIRMWARE("radeon/CEDAR_smc.bin");
74 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
75 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
76 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
77 MODULE_FIRMWARE("radeon/REDWOOD_smc.bin");
78 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
79 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
80 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
81 MODULE_FIRMWARE("radeon/JUNIPER_smc.bin");
82 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
83 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
84 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
85 MODULE_FIRMWARE("radeon/CYPRESS_smc.bin");
86 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
87 MODULE_FIRMWARE("radeon/PALM_me.bin");
88 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
89 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
90 MODULE_FIRMWARE("radeon/SUMO_me.bin");
91 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
92 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
93
94 static const u32 crtc_offsets[2] =
95 {
96 0,
97 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
98 };
99
100 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
101
102 /* r600,rv610,rv630,rv620,rv635,rv670 */
103 static void r600_gpu_init(struct radeon_device *rdev);
104 void r600_irq_disable(struct radeon_device *rdev);
105 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
106
107 /*
108 * Indirect registers accessor
109 */
r600_rcu_rreg(struct radeon_device * rdev,u32 reg)110 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
111 {
112 unsigned long flags;
113 u32 r;
114
115 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
116 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
117 r = RREG32(R600_RCU_DATA);
118 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
119 return r;
120 }
121
r600_rcu_wreg(struct radeon_device * rdev,u32 reg,u32 v)122 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
123 {
124 unsigned long flags;
125
126 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
127 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
128 WREG32(R600_RCU_DATA, (v));
129 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
130 }
131
r600_uvd_ctx_rreg(struct radeon_device * rdev,u32 reg)132 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
133 {
134 unsigned long flags;
135 u32 r;
136
137 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
138 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
139 r = RREG32(R600_UVD_CTX_DATA);
140 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
141 return r;
142 }
143
r600_uvd_ctx_wreg(struct radeon_device * rdev,u32 reg,u32 v)144 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
145 {
146 unsigned long flags;
147
148 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
149 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
150 WREG32(R600_UVD_CTX_DATA, (v));
151 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
152 }
153
154 /**
155 * r600_get_allowed_info_register - fetch the register for the info ioctl
156 *
157 * @rdev: radeon_device pointer
158 * @reg: register offset in bytes
159 * @val: register value
160 *
161 * Returns 0 for success or -EINVAL for an invalid register
162 *
163 */
r600_get_allowed_info_register(struct radeon_device * rdev,u32 reg,u32 * val)164 int r600_get_allowed_info_register(struct radeon_device *rdev,
165 u32 reg, u32 *val)
166 {
167 switch (reg) {
168 case GRBM_STATUS:
169 case GRBM_STATUS2:
170 case R_000E50_SRBM_STATUS:
171 case DMA_STATUS_REG:
172 case UVD_STATUS:
173 *val = RREG32(reg);
174 return 0;
175 default:
176 return -EINVAL;
177 }
178 }
179
180 /**
181 * r600_get_xclk - get the xclk
182 *
183 * @rdev: radeon_device pointer
184 *
185 * Returns the reference clock used by the gfx engine
186 * (r6xx, IGPs, APUs).
187 */
r600_get_xclk(struct radeon_device * rdev)188 u32 r600_get_xclk(struct radeon_device *rdev)
189 {
190 return rdev->clock.spll.reference_freq;
191 }
192
r600_set_uvd_clocks(struct radeon_device * rdev,u32 vclk,u32 dclk)193 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
194 {
195 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0;
196 int r;
197
198 /* bypass vclk and dclk with bclk */
199 WREG32_P(CG_UPLL_FUNC_CNTL_2,
200 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
201 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
202
203 /* assert BYPASS_EN, deassert UPLL_RESET, UPLL_SLEEP and UPLL_CTLREQ */
204 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~(
205 UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK));
206
207 if (rdev->family >= CHIP_RS780)
208 WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL,
209 ~UPLL_BYPASS_CNTL);
210
211 if (!vclk || !dclk) {
212 /* keep the Bypass mode, put PLL to sleep */
213 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
214 return 0;
215 }
216
217 if (rdev->clock.spll.reference_freq == 10000)
218 ref_div = 34;
219 else
220 ref_div = 4;
221
222 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
223 ref_div + 1, 0xFFF, 2, 30, ~0,
224 &fb_div, &vclk_div, &dclk_div);
225 if (r)
226 return r;
227
228 if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780)
229 fb_div >>= 1;
230 else
231 fb_div |= 1;
232
233 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
234 if (r)
235 return r;
236
237 /* assert PLL_RESET */
238 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
239
240 /* For RS780 we have to choose ref clk */
241 if (rdev->family >= CHIP_RS780)
242 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK,
243 ~UPLL_REFCLK_SRC_SEL_MASK);
244
245 /* set the required fb, ref and post divder values */
246 WREG32_P(CG_UPLL_FUNC_CNTL,
247 UPLL_FB_DIV(fb_div) |
248 UPLL_REF_DIV(ref_div),
249 ~(UPLL_FB_DIV_MASK | UPLL_REF_DIV_MASK));
250 WREG32_P(CG_UPLL_FUNC_CNTL_2,
251 UPLL_SW_HILEN(vclk_div >> 1) |
252 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
253 UPLL_SW_HILEN2(dclk_div >> 1) |
254 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) |
255 UPLL_DIVEN_MASK | UPLL_DIVEN2_MASK,
256 ~UPLL_SW_MASK);
257
258 /* give the PLL some time to settle */
259 mdelay(15);
260
261 /* deassert PLL_RESET */
262 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
263
264 mdelay(15);
265
266 /* deassert BYPASS EN */
267 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
268
269 if (rdev->family >= CHIP_RS780)
270 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL);
271
272 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
273 if (r)
274 return r;
275
276 /* switch VCLK and DCLK selection */
277 WREG32_P(CG_UPLL_FUNC_CNTL_2,
278 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
279 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
280
281 mdelay(100);
282
283 return 0;
284 }
285
dce3_program_fmt(struct drm_encoder * encoder)286 void dce3_program_fmt(struct drm_encoder *encoder)
287 {
288 struct drm_device *dev = encoder->dev;
289 struct radeon_device *rdev = dev->dev_private;
290 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
291 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
292 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
293 int bpc = 0;
294 u32 tmp = 0;
295 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
296
297 if (connector) {
298 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
299 bpc = radeon_get_monitor_bpc(connector);
300 dither = radeon_connector->dither;
301 }
302
303 /* LVDS FMT is set up by atom */
304 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
305 return;
306
307 /* not needed for analog */
308 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
309 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
310 return;
311
312 if (bpc == 0)
313 return;
314
315 switch (bpc) {
316 case 6:
317 if (dither == RADEON_FMT_DITHER_ENABLE)
318 /* XXX sort out optimal dither settings */
319 tmp |= FMT_SPATIAL_DITHER_EN;
320 else
321 tmp |= FMT_TRUNCATE_EN;
322 break;
323 case 8:
324 if (dither == RADEON_FMT_DITHER_ENABLE)
325 /* XXX sort out optimal dither settings */
326 tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH);
327 else
328 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
329 break;
330 case 10:
331 default:
332 /* not needed */
333 break;
334 }
335
336 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
337 }
338
339 /* get temperature in millidegrees */
rv6xx_get_temp(struct radeon_device * rdev)340 int rv6xx_get_temp(struct radeon_device *rdev)
341 {
342 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
343 ASIC_T_SHIFT;
344 int actual_temp = temp & 0xff;
345
346 if (temp & 0x100)
347 actual_temp -= 256;
348
349 return actual_temp * 1000;
350 }
351
r600_pm_get_dynpm_state(struct radeon_device * rdev)352 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
353 {
354 int i;
355
356 rdev->pm.dynpm_can_upclock = true;
357 rdev->pm.dynpm_can_downclock = true;
358
359 /* power state array is low to high, default is first */
360 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
361 int min_power_state_index = 0;
362
363 if (rdev->pm.num_power_states > 2)
364 min_power_state_index = 1;
365
366 switch (rdev->pm.dynpm_planned_action) {
367 case DYNPM_ACTION_MINIMUM:
368 rdev->pm.requested_power_state_index = min_power_state_index;
369 rdev->pm.requested_clock_mode_index = 0;
370 rdev->pm.dynpm_can_downclock = false;
371 break;
372 case DYNPM_ACTION_DOWNCLOCK:
373 if (rdev->pm.current_power_state_index == min_power_state_index) {
374 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
375 rdev->pm.dynpm_can_downclock = false;
376 } else {
377 if (rdev->pm.active_crtc_count > 1) {
378 for (i = 0; i < rdev->pm.num_power_states; i++) {
379 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
380 continue;
381 else if (i >= rdev->pm.current_power_state_index) {
382 rdev->pm.requested_power_state_index =
383 rdev->pm.current_power_state_index;
384 break;
385 } else {
386 rdev->pm.requested_power_state_index = i;
387 break;
388 }
389 }
390 } else {
391 if (rdev->pm.current_power_state_index == 0)
392 rdev->pm.requested_power_state_index =
393 rdev->pm.num_power_states - 1;
394 else
395 rdev->pm.requested_power_state_index =
396 rdev->pm.current_power_state_index - 1;
397 }
398 }
399 rdev->pm.requested_clock_mode_index = 0;
400 /* don't use the power state if crtcs are active and no display flag is set */
401 if ((rdev->pm.active_crtc_count > 0) &&
402 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
403 clock_info[rdev->pm.requested_clock_mode_index].flags &
404 RADEON_PM_MODE_NO_DISPLAY)) {
405 rdev->pm.requested_power_state_index++;
406 }
407 break;
408 case DYNPM_ACTION_UPCLOCK:
409 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
410 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
411 rdev->pm.dynpm_can_upclock = false;
412 } else {
413 if (rdev->pm.active_crtc_count > 1) {
414 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
415 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
416 continue;
417 else if (i <= rdev->pm.current_power_state_index) {
418 rdev->pm.requested_power_state_index =
419 rdev->pm.current_power_state_index;
420 break;
421 } else {
422 rdev->pm.requested_power_state_index = i;
423 break;
424 }
425 }
426 } else
427 rdev->pm.requested_power_state_index =
428 rdev->pm.current_power_state_index + 1;
429 }
430 rdev->pm.requested_clock_mode_index = 0;
431 break;
432 case DYNPM_ACTION_DEFAULT:
433 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
434 rdev->pm.requested_clock_mode_index = 0;
435 rdev->pm.dynpm_can_upclock = false;
436 break;
437 case DYNPM_ACTION_NONE:
438 default:
439 DRM_ERROR("Requested mode for not defined action\n");
440 return;
441 }
442 } else {
443 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
444 /* for now just select the first power state and switch between clock modes */
445 /* power state array is low to high, default is first (0) */
446 if (rdev->pm.active_crtc_count > 1) {
447 rdev->pm.requested_power_state_index = -1;
448 /* start at 1 as we don't want the default mode */
449 for (i = 1; i < rdev->pm.num_power_states; i++) {
450 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
451 continue;
452 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
453 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
454 rdev->pm.requested_power_state_index = i;
455 break;
456 }
457 }
458 /* if nothing selected, grab the default state. */
459 if (rdev->pm.requested_power_state_index == -1)
460 rdev->pm.requested_power_state_index = 0;
461 } else
462 rdev->pm.requested_power_state_index = 1;
463
464 switch (rdev->pm.dynpm_planned_action) {
465 case DYNPM_ACTION_MINIMUM:
466 rdev->pm.requested_clock_mode_index = 0;
467 rdev->pm.dynpm_can_downclock = false;
468 break;
469 case DYNPM_ACTION_DOWNCLOCK:
470 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
471 if (rdev->pm.current_clock_mode_index == 0) {
472 rdev->pm.requested_clock_mode_index = 0;
473 rdev->pm.dynpm_can_downclock = false;
474 } else
475 rdev->pm.requested_clock_mode_index =
476 rdev->pm.current_clock_mode_index - 1;
477 } else {
478 rdev->pm.requested_clock_mode_index = 0;
479 rdev->pm.dynpm_can_downclock = false;
480 }
481 /* don't use the power state if crtcs are active and no display flag is set */
482 if ((rdev->pm.active_crtc_count > 0) &&
483 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
484 clock_info[rdev->pm.requested_clock_mode_index].flags &
485 RADEON_PM_MODE_NO_DISPLAY)) {
486 rdev->pm.requested_clock_mode_index++;
487 }
488 break;
489 case DYNPM_ACTION_UPCLOCK:
490 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
491 if (rdev->pm.current_clock_mode_index ==
492 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
493 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
494 rdev->pm.dynpm_can_upclock = false;
495 } else
496 rdev->pm.requested_clock_mode_index =
497 rdev->pm.current_clock_mode_index + 1;
498 } else {
499 rdev->pm.requested_clock_mode_index =
500 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
501 rdev->pm.dynpm_can_upclock = false;
502 }
503 break;
504 case DYNPM_ACTION_DEFAULT:
505 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
506 rdev->pm.requested_clock_mode_index = 0;
507 rdev->pm.dynpm_can_upclock = false;
508 break;
509 case DYNPM_ACTION_NONE:
510 default:
511 DRM_ERROR("Requested mode for not defined action\n");
512 return;
513 }
514 }
515
516 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
517 rdev->pm.power_state[rdev->pm.requested_power_state_index].
518 clock_info[rdev->pm.requested_clock_mode_index].sclk,
519 rdev->pm.power_state[rdev->pm.requested_power_state_index].
520 clock_info[rdev->pm.requested_clock_mode_index].mclk,
521 rdev->pm.power_state[rdev->pm.requested_power_state_index].
522 pcie_lanes);
523 }
524
rs780_pm_init_profile(struct radeon_device * rdev)525 void rs780_pm_init_profile(struct radeon_device *rdev)
526 {
527 if (rdev->pm.num_power_states == 2) {
528 /* default */
529 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
530 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
531 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
532 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
533 /* low sh */
534 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
535 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
536 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
537 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
538 /* mid sh */
539 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
540 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
541 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
542 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
543 /* high sh */
544 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
545 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
546 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
547 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
548 /* low mh */
549 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
550 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
551 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
552 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
553 /* mid mh */
554 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
555 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
556 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
557 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
558 /* high mh */
559 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
560 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
561 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
562 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
563 } else if (rdev->pm.num_power_states == 3) {
564 /* default */
565 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
566 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
567 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
568 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
569 /* low sh */
570 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
571 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
572 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
573 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
574 /* mid sh */
575 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
576 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
577 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
578 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
579 /* high sh */
580 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
581 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
582 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
583 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
584 /* low mh */
585 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
586 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
587 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
588 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
589 /* mid mh */
590 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
591 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
592 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
593 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
594 /* high mh */
595 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
596 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
597 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
598 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
599 } else {
600 /* default */
601 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
602 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
603 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
604 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
605 /* low sh */
606 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
607 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
608 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
609 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
610 /* mid sh */
611 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
612 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
613 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
614 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
615 /* high sh */
616 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
617 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
618 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
619 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
620 /* low mh */
621 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
622 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
623 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
624 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
625 /* mid mh */
626 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
627 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
628 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
629 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
630 /* high mh */
631 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
632 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
633 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
634 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
635 }
636 }
637
r600_pm_init_profile(struct radeon_device * rdev)638 void r600_pm_init_profile(struct radeon_device *rdev)
639 {
640 int idx;
641
642 if (rdev->family == CHIP_R600) {
643 /* XXX */
644 /* default */
645 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
646 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
647 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
648 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
649 /* low sh */
650 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
651 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
652 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
653 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
654 /* mid sh */
655 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
656 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
657 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
658 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
659 /* high sh */
660 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
661 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
662 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
663 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
664 /* low mh */
665 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
666 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
667 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
668 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
669 /* mid mh */
670 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
671 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
672 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
673 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
674 /* high mh */
675 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
676 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
677 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
678 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
679 } else {
680 if (rdev->pm.num_power_states < 4) {
681 /* default */
682 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
683 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
684 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
685 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
686 /* low sh */
687 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
688 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
689 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
690 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
691 /* mid sh */
692 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
693 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
694 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
695 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
696 /* high sh */
697 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
698 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
699 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
700 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
701 /* low mh */
702 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
703 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
704 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
705 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
706 /* low mh */
707 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
708 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
709 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
710 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
711 /* high mh */
712 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
713 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
714 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
715 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
716 } else {
717 /* default */
718 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
719 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
720 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
721 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
722 /* low sh */
723 if (rdev->flags & RADEON_IS_MOBILITY)
724 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
725 else
726 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
727 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
728 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
729 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
730 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
731 /* mid sh */
732 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
733 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
734 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
735 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
736 /* high sh */
737 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
738 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
739 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
740 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
741 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
742 /* low mh */
743 if (rdev->flags & RADEON_IS_MOBILITY)
744 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
745 else
746 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
747 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
748 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
749 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
750 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
751 /* mid mh */
752 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
753 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
754 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
755 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
756 /* high mh */
757 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
758 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
759 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
760 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
761 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
762 }
763 }
764 }
765
r600_pm_misc(struct radeon_device * rdev)766 void r600_pm_misc(struct radeon_device *rdev)
767 {
768 int req_ps_idx = rdev->pm.requested_power_state_index;
769 int req_cm_idx = rdev->pm.requested_clock_mode_index;
770 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
771 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
772
773 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
774 /* 0xff01 is a flag rather then an actual voltage */
775 if (voltage->voltage == 0xff01)
776 return;
777 if (voltage->voltage != rdev->pm.current_vddc) {
778 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
779 rdev->pm.current_vddc = voltage->voltage;
780 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
781 }
782 }
783 }
784
r600_gui_idle(struct radeon_device * rdev)785 bool r600_gui_idle(struct radeon_device *rdev)
786 {
787 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
788 return false;
789 else
790 return true;
791 }
792
793 /* hpd for digital panel detect/disconnect */
r600_hpd_sense(struct radeon_device * rdev,enum radeon_hpd_id hpd)794 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
795 {
796 bool connected = false;
797
798 if (ASIC_IS_DCE3(rdev)) {
799 switch (hpd) {
800 case RADEON_HPD_1:
801 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
802 connected = true;
803 break;
804 case RADEON_HPD_2:
805 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
806 connected = true;
807 break;
808 case RADEON_HPD_3:
809 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
810 connected = true;
811 break;
812 case RADEON_HPD_4:
813 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
814 connected = true;
815 break;
816 /* DCE 3.2 */
817 case RADEON_HPD_5:
818 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
819 connected = true;
820 break;
821 case RADEON_HPD_6:
822 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
823 connected = true;
824 break;
825 default:
826 break;
827 }
828 } else {
829 switch (hpd) {
830 case RADEON_HPD_1:
831 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
832 connected = true;
833 break;
834 case RADEON_HPD_2:
835 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
836 connected = true;
837 break;
838 case RADEON_HPD_3:
839 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
840 connected = true;
841 break;
842 default:
843 break;
844 }
845 }
846 return connected;
847 }
848
r600_hpd_set_polarity(struct radeon_device * rdev,enum radeon_hpd_id hpd)849 void r600_hpd_set_polarity(struct radeon_device *rdev,
850 enum radeon_hpd_id hpd)
851 {
852 u32 tmp;
853 bool connected = r600_hpd_sense(rdev, hpd);
854
855 if (ASIC_IS_DCE3(rdev)) {
856 switch (hpd) {
857 case RADEON_HPD_1:
858 tmp = RREG32(DC_HPD1_INT_CONTROL);
859 if (connected)
860 tmp &= ~DC_HPDx_INT_POLARITY;
861 else
862 tmp |= DC_HPDx_INT_POLARITY;
863 WREG32(DC_HPD1_INT_CONTROL, tmp);
864 break;
865 case RADEON_HPD_2:
866 tmp = RREG32(DC_HPD2_INT_CONTROL);
867 if (connected)
868 tmp &= ~DC_HPDx_INT_POLARITY;
869 else
870 tmp |= DC_HPDx_INT_POLARITY;
871 WREG32(DC_HPD2_INT_CONTROL, tmp);
872 break;
873 case RADEON_HPD_3:
874 tmp = RREG32(DC_HPD3_INT_CONTROL);
875 if (connected)
876 tmp &= ~DC_HPDx_INT_POLARITY;
877 else
878 tmp |= DC_HPDx_INT_POLARITY;
879 WREG32(DC_HPD3_INT_CONTROL, tmp);
880 break;
881 case RADEON_HPD_4:
882 tmp = RREG32(DC_HPD4_INT_CONTROL);
883 if (connected)
884 tmp &= ~DC_HPDx_INT_POLARITY;
885 else
886 tmp |= DC_HPDx_INT_POLARITY;
887 WREG32(DC_HPD4_INT_CONTROL, tmp);
888 break;
889 case RADEON_HPD_5:
890 tmp = RREG32(DC_HPD5_INT_CONTROL);
891 if (connected)
892 tmp &= ~DC_HPDx_INT_POLARITY;
893 else
894 tmp |= DC_HPDx_INT_POLARITY;
895 WREG32(DC_HPD5_INT_CONTROL, tmp);
896 break;
897 /* DCE 3.2 */
898 case RADEON_HPD_6:
899 tmp = RREG32(DC_HPD6_INT_CONTROL);
900 if (connected)
901 tmp &= ~DC_HPDx_INT_POLARITY;
902 else
903 tmp |= DC_HPDx_INT_POLARITY;
904 WREG32(DC_HPD6_INT_CONTROL, tmp);
905 break;
906 default:
907 break;
908 }
909 } else {
910 switch (hpd) {
911 case RADEON_HPD_1:
912 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
913 if (connected)
914 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
915 else
916 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
917 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
918 break;
919 case RADEON_HPD_2:
920 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
921 if (connected)
922 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
923 else
924 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
925 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
926 break;
927 case RADEON_HPD_3:
928 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
929 if (connected)
930 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
931 else
932 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
933 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
934 break;
935 default:
936 break;
937 }
938 }
939 }
940
r600_hpd_init(struct radeon_device * rdev)941 void r600_hpd_init(struct radeon_device *rdev)
942 {
943 struct drm_device *dev = rdev->ddev;
944 struct drm_connector *connector;
945 unsigned enable = 0;
946
947 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
948 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
949
950 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
951 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
952 /* don't try to enable hpd on eDP or LVDS avoid breaking the
953 * aux dp channel on imac and help (but not completely fix)
954 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
955 */
956 continue;
957 }
958 if (ASIC_IS_DCE3(rdev)) {
959 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
960 if (ASIC_IS_DCE32(rdev))
961 tmp |= DC_HPDx_EN;
962
963 switch (radeon_connector->hpd.hpd) {
964 case RADEON_HPD_1:
965 WREG32(DC_HPD1_CONTROL, tmp);
966 break;
967 case RADEON_HPD_2:
968 WREG32(DC_HPD2_CONTROL, tmp);
969 break;
970 case RADEON_HPD_3:
971 WREG32(DC_HPD3_CONTROL, tmp);
972 break;
973 case RADEON_HPD_4:
974 WREG32(DC_HPD4_CONTROL, tmp);
975 break;
976 /* DCE 3.2 */
977 case RADEON_HPD_5:
978 WREG32(DC_HPD5_CONTROL, tmp);
979 break;
980 case RADEON_HPD_6:
981 WREG32(DC_HPD6_CONTROL, tmp);
982 break;
983 default:
984 break;
985 }
986 } else {
987 switch (radeon_connector->hpd.hpd) {
988 case RADEON_HPD_1:
989 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
990 break;
991 case RADEON_HPD_2:
992 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
993 break;
994 case RADEON_HPD_3:
995 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
996 break;
997 default:
998 break;
999 }
1000 }
1001 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
1002 enable |= 1 << radeon_connector->hpd.hpd;
1003 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
1004 }
1005 radeon_irq_kms_enable_hpd(rdev, enable);
1006 }
1007
r600_hpd_fini(struct radeon_device * rdev)1008 void r600_hpd_fini(struct radeon_device *rdev)
1009 {
1010 struct drm_device *dev = rdev->ddev;
1011 struct drm_connector *connector;
1012 unsigned disable = 0;
1013
1014 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1015 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1016 if (ASIC_IS_DCE3(rdev)) {
1017 switch (radeon_connector->hpd.hpd) {
1018 case RADEON_HPD_1:
1019 WREG32(DC_HPD1_CONTROL, 0);
1020 break;
1021 case RADEON_HPD_2:
1022 WREG32(DC_HPD2_CONTROL, 0);
1023 break;
1024 case RADEON_HPD_3:
1025 WREG32(DC_HPD3_CONTROL, 0);
1026 break;
1027 case RADEON_HPD_4:
1028 WREG32(DC_HPD4_CONTROL, 0);
1029 break;
1030 /* DCE 3.2 */
1031 case RADEON_HPD_5:
1032 WREG32(DC_HPD5_CONTROL, 0);
1033 break;
1034 case RADEON_HPD_6:
1035 WREG32(DC_HPD6_CONTROL, 0);
1036 break;
1037 default:
1038 break;
1039 }
1040 } else {
1041 switch (radeon_connector->hpd.hpd) {
1042 case RADEON_HPD_1:
1043 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
1044 break;
1045 case RADEON_HPD_2:
1046 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
1047 break;
1048 case RADEON_HPD_3:
1049 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
1050 break;
1051 default:
1052 break;
1053 }
1054 }
1055 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
1056 disable |= 1 << radeon_connector->hpd.hpd;
1057 }
1058 radeon_irq_kms_disable_hpd(rdev, disable);
1059 }
1060
1061 /*
1062 * R600 PCIE GART
1063 */
r600_pcie_gart_tlb_flush(struct radeon_device * rdev)1064 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
1065 {
1066 unsigned i;
1067 u32 tmp;
1068
1069 /* flush hdp cache so updates hit vram */
1070 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
1071 !(rdev->flags & RADEON_IS_AGP)) {
1072 void __iomem *ptr = (void *)rdev->gart.ptr;
1073 u32 tmp;
1074
1075 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
1076 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
1077 * This seems to cause problems on some AGP cards. Just use the old
1078 * method for them.
1079 */
1080 WREG32(HDP_DEBUG1, 0);
1081 tmp = readl((void __iomem *)ptr);
1082 } else
1083 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1084
1085 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
1086 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
1087 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1088 for (i = 0; i < rdev->usec_timeout; i++) {
1089 /* read MC_STATUS */
1090 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1091 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1092 if (tmp == 2) {
1093 pr_warn("[drm] r600 flush TLB failed\n");
1094 return;
1095 }
1096 if (tmp) {
1097 return;
1098 }
1099 udelay(1);
1100 }
1101 }
1102
r600_pcie_gart_init(struct radeon_device * rdev)1103 int r600_pcie_gart_init(struct radeon_device *rdev)
1104 {
1105 int r;
1106
1107 if (rdev->gart.robj) {
1108 WARN(1, "R600 PCIE GART already initialized\n");
1109 return 0;
1110 }
1111 /* Initialize common gart structure */
1112 r = radeon_gart_init(rdev);
1113 if (r)
1114 return r;
1115 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
1116 return radeon_gart_table_vram_alloc(rdev);
1117 }
1118
r600_pcie_gart_enable(struct radeon_device * rdev)1119 static int r600_pcie_gart_enable(struct radeon_device *rdev)
1120 {
1121 u32 tmp;
1122 int r, i;
1123
1124 if (rdev->gart.robj == NULL) {
1125 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1126 return -EINVAL;
1127 }
1128 r = radeon_gart_table_vram_pin(rdev);
1129 if (r)
1130 return r;
1131
1132 /* Setup L2 cache */
1133 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1134 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1135 EFFECTIVE_L2_QUEUE_SIZE(7));
1136 WREG32(VM_L2_CNTL2, 0);
1137 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1138 /* Setup TLB control */
1139 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1140 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1141 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1142 ENABLE_WAIT_L2_QUERY;
1143 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1144 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1145 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1146 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1147 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1148 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1149 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1150 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1151 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1152 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1153 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1154 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1155 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
1156 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
1157 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1158 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1159 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1160 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1161 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1162 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1163 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1164 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1165 (u32)(rdev->dummy_page.addr >> 12));
1166 for (i = 1; i < 7; i++)
1167 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1168
1169 r600_pcie_gart_tlb_flush(rdev);
1170 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1171 (unsigned)(rdev->mc.gtt_size >> 20),
1172 (unsigned long long)rdev->gart.table_addr);
1173 rdev->gart.ready = true;
1174 return 0;
1175 }
1176
r600_pcie_gart_disable(struct radeon_device * rdev)1177 static void r600_pcie_gart_disable(struct radeon_device *rdev)
1178 {
1179 u32 tmp;
1180 int i;
1181
1182 /* Disable all tables */
1183 for (i = 0; i < 7; i++)
1184 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1185
1186 /* Disable L2 cache */
1187 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1188 EFFECTIVE_L2_QUEUE_SIZE(7));
1189 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1190 /* Setup L1 TLB control */
1191 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1192 ENABLE_WAIT_L2_QUERY;
1193 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1194 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1195 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1196 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1197 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1198 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1199 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1200 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1201 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1202 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1203 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1204 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1205 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1206 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1207 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
1208 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
1209 radeon_gart_table_vram_unpin(rdev);
1210 }
1211
r600_pcie_gart_fini(struct radeon_device * rdev)1212 static void r600_pcie_gart_fini(struct radeon_device *rdev)
1213 {
1214 radeon_gart_fini(rdev);
1215 r600_pcie_gart_disable(rdev);
1216 radeon_gart_table_vram_free(rdev);
1217 }
1218
r600_agp_enable(struct radeon_device * rdev)1219 static void r600_agp_enable(struct radeon_device *rdev)
1220 {
1221 u32 tmp;
1222 int i;
1223
1224 /* Setup L2 cache */
1225 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1226 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1227 EFFECTIVE_L2_QUEUE_SIZE(7));
1228 WREG32(VM_L2_CNTL2, 0);
1229 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1230 /* Setup TLB control */
1231 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1232 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1233 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1234 ENABLE_WAIT_L2_QUERY;
1235 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1236 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1237 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1238 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1239 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1240 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1241 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1242 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1243 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1244 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1245 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1246 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1247 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1248 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1249 for (i = 0; i < 7; i++)
1250 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1251 }
1252
r600_mc_wait_for_idle(struct radeon_device * rdev)1253 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1254 {
1255 unsigned i;
1256 u32 tmp;
1257
1258 for (i = 0; i < rdev->usec_timeout; i++) {
1259 /* read MC_STATUS */
1260 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1261 if (!tmp)
1262 return 0;
1263 udelay(1);
1264 }
1265 return -1;
1266 }
1267
rs780_mc_rreg(struct radeon_device * rdev,uint32_t reg)1268 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1269 {
1270 unsigned long flags;
1271 uint32_t r;
1272
1273 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1274 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
1275 r = RREG32(R_0028FC_MC_DATA);
1276 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
1277 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1278 return r;
1279 }
1280
rs780_mc_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v)1281 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1282 {
1283 unsigned long flags;
1284
1285 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1286 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
1287 S_0028F8_MC_IND_WR_EN(1));
1288 WREG32(R_0028FC_MC_DATA, v);
1289 WREG32(R_0028F8_MC_INDEX, 0x7F);
1290 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1291 }
1292
r600_mc_program(struct radeon_device * rdev)1293 static void r600_mc_program(struct radeon_device *rdev)
1294 {
1295 struct rv515_mc_save save;
1296 u32 tmp;
1297 int i, j;
1298
1299 /* Initialize HDP */
1300 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1301 WREG32((0x2c14 + j), 0x00000000);
1302 WREG32((0x2c18 + j), 0x00000000);
1303 WREG32((0x2c1c + j), 0x00000000);
1304 WREG32((0x2c20 + j), 0x00000000);
1305 WREG32((0x2c24 + j), 0x00000000);
1306 }
1307 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1308
1309 rv515_mc_stop(rdev, &save);
1310 if (r600_mc_wait_for_idle(rdev)) {
1311 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1312 }
1313 /* Lockout access through VGA aperture (doesn't exist before R600) */
1314 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1315 /* Update configuration */
1316 if (rdev->flags & RADEON_IS_AGP) {
1317 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1318 /* VRAM before AGP */
1319 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1320 rdev->mc.vram_start >> 12);
1321 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1322 rdev->mc.gtt_end >> 12);
1323 } else {
1324 /* VRAM after AGP */
1325 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1326 rdev->mc.gtt_start >> 12);
1327 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1328 rdev->mc.vram_end >> 12);
1329 }
1330 } else {
1331 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1332 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1333 }
1334 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1335 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1336 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1337 WREG32(MC_VM_FB_LOCATION, tmp);
1338 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1339 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1340 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1341 if (rdev->flags & RADEON_IS_AGP) {
1342 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1343 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1344 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1345 } else {
1346 WREG32(MC_VM_AGP_BASE, 0);
1347 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1348 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1349 }
1350 if (r600_mc_wait_for_idle(rdev)) {
1351 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1352 }
1353 rv515_mc_resume(rdev, &save);
1354 /* we need to own VRAM, so turn off the VGA renderer here
1355 * to stop it overwriting our objects */
1356 rv515_vga_render_disable(rdev);
1357 }
1358
1359 /**
1360 * r600_vram_gtt_location - try to find VRAM & GTT location
1361 * @rdev: radeon device structure holding all necessary informations
1362 * @mc: memory controller structure holding memory informations
1363 *
1364 * Function will place try to place VRAM at same place as in CPU (PCI)
1365 * address space as some GPU seems to have issue when we reprogram at
1366 * different address space.
1367 *
1368 * If there is not enough space to fit the unvisible VRAM after the
1369 * aperture then we limit the VRAM size to the aperture.
1370 *
1371 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1372 * them to be in one from GPU point of view so that we can program GPU to
1373 * catch access outside them (weird GPU policy see ??).
1374 *
1375 * This function will never fails, worst case are limiting VRAM or GTT.
1376 *
1377 * Note: GTT start, end, size should be initialized before calling this
1378 * function on AGP platform.
1379 */
r600_vram_gtt_location(struct radeon_device * rdev,struct radeon_mc * mc)1380 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1381 {
1382 u64 size_bf, size_af;
1383
1384 if (mc->mc_vram_size > 0xE0000000) {
1385 /* leave room for at least 512M GTT */
1386 dev_warn(rdev->dev, "limiting VRAM\n");
1387 mc->real_vram_size = 0xE0000000;
1388 mc->mc_vram_size = 0xE0000000;
1389 }
1390 if (rdev->flags & RADEON_IS_AGP) {
1391 size_bf = mc->gtt_start;
1392 size_af = mc->mc_mask - mc->gtt_end;
1393 if (size_bf > size_af) {
1394 if (mc->mc_vram_size > size_bf) {
1395 dev_warn(rdev->dev, "limiting VRAM\n");
1396 mc->real_vram_size = size_bf;
1397 mc->mc_vram_size = size_bf;
1398 }
1399 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1400 } else {
1401 if (mc->mc_vram_size > size_af) {
1402 dev_warn(rdev->dev, "limiting VRAM\n");
1403 mc->real_vram_size = size_af;
1404 mc->mc_vram_size = size_af;
1405 }
1406 mc->vram_start = mc->gtt_end + 1;
1407 }
1408 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1409 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1410 mc->mc_vram_size >> 20, mc->vram_start,
1411 mc->vram_end, mc->real_vram_size >> 20);
1412 } else {
1413 u64 base = 0;
1414 if (rdev->flags & RADEON_IS_IGP) {
1415 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1416 base <<= 24;
1417 }
1418 radeon_vram_location(rdev, &rdev->mc, base);
1419 rdev->mc.gtt_base_align = 0;
1420 radeon_gtt_location(rdev, mc);
1421 }
1422 }
1423
r600_mc_init(struct radeon_device * rdev)1424 static int r600_mc_init(struct radeon_device *rdev)
1425 {
1426 u32 tmp;
1427 int chansize, numchan;
1428 uint32_t h_addr, l_addr;
1429 unsigned long long k8_addr;
1430
1431 /* Get VRAM informations */
1432 rdev->mc.vram_is_ddr = true;
1433 tmp = RREG32(RAMCFG);
1434 if (tmp & CHANSIZE_OVERRIDE) {
1435 chansize = 16;
1436 } else if (tmp & CHANSIZE_MASK) {
1437 chansize = 64;
1438 } else {
1439 chansize = 32;
1440 }
1441 tmp = RREG32(CHMAP);
1442 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1443 case 0:
1444 default:
1445 numchan = 1;
1446 break;
1447 case 1:
1448 numchan = 2;
1449 break;
1450 case 2:
1451 numchan = 4;
1452 break;
1453 case 3:
1454 numchan = 8;
1455 break;
1456 }
1457 rdev->mc.vram_width = numchan * chansize;
1458 /* Could aper size report 0 ? */
1459 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1460 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1461 /* Setup GPU memory space */
1462 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1463 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1464 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1465 r600_vram_gtt_location(rdev, &rdev->mc);
1466
1467 if (rdev->flags & RADEON_IS_IGP) {
1468 rs690_pm_info(rdev);
1469 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1470
1471 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
1472 /* Use K8 direct mapping for fast fb access. */
1473 rdev->fastfb_working = false;
1474 h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
1475 l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
1476 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
1477 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
1478 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
1479 #endif
1480 {
1481 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
1482 * memory is present.
1483 */
1484 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
1485 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
1486 (unsigned long long)rdev->mc.aper_base, k8_addr);
1487 rdev->mc.aper_base = (resource_size_t)k8_addr;
1488 rdev->fastfb_working = true;
1489 }
1490 }
1491 }
1492 }
1493
1494 radeon_update_bandwidth_info(rdev);
1495 return 0;
1496 }
1497
r600_vram_scratch_init(struct radeon_device * rdev)1498 int r600_vram_scratch_init(struct radeon_device *rdev)
1499 {
1500 int r;
1501
1502 if (rdev->vram_scratch.robj == NULL) {
1503 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1504 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1505 0, NULL, NULL, &rdev->vram_scratch.robj);
1506 if (r) {
1507 return r;
1508 }
1509 }
1510
1511 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1512 if (unlikely(r != 0))
1513 return r;
1514 r = radeon_bo_pin(rdev->vram_scratch.robj,
1515 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1516 if (r) {
1517 radeon_bo_unreserve(rdev->vram_scratch.robj);
1518 return r;
1519 }
1520 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1521 (void **)&rdev->vram_scratch.ptr);
1522 if (r)
1523 radeon_bo_unpin(rdev->vram_scratch.robj);
1524 radeon_bo_unreserve(rdev->vram_scratch.robj);
1525
1526 return r;
1527 }
1528
r600_vram_scratch_fini(struct radeon_device * rdev)1529 void r600_vram_scratch_fini(struct radeon_device *rdev)
1530 {
1531 int r;
1532
1533 if (rdev->vram_scratch.robj == NULL) {
1534 return;
1535 }
1536 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1537 if (likely(r == 0)) {
1538 radeon_bo_kunmap(rdev->vram_scratch.robj);
1539 radeon_bo_unpin(rdev->vram_scratch.robj);
1540 radeon_bo_unreserve(rdev->vram_scratch.robj);
1541 }
1542 radeon_bo_unref(&rdev->vram_scratch.robj);
1543 }
1544
r600_set_bios_scratch_engine_hung(struct radeon_device * rdev,bool hung)1545 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
1546 {
1547 u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
1548
1549 if (hung)
1550 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1551 else
1552 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1553
1554 WREG32(R600_BIOS_3_SCRATCH, tmp);
1555 }
1556
r600_print_gpu_status_regs(struct radeon_device * rdev)1557 static void r600_print_gpu_status_regs(struct radeon_device *rdev)
1558 {
1559 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
1560 RREG32(R_008010_GRBM_STATUS));
1561 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
1562 RREG32(R_008014_GRBM_STATUS2));
1563 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
1564 RREG32(R_000E50_SRBM_STATUS));
1565 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1566 RREG32(CP_STALLED_STAT1));
1567 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1568 RREG32(CP_STALLED_STAT2));
1569 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
1570 RREG32(CP_BUSY_STAT));
1571 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1572 RREG32(CP_STAT));
1573 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1574 RREG32(DMA_STATUS_REG));
1575 }
1576
r600_is_display_hung(struct radeon_device * rdev)1577 static bool r600_is_display_hung(struct radeon_device *rdev)
1578 {
1579 u32 crtc_hung = 0;
1580 u32 crtc_status[2];
1581 u32 i, j, tmp;
1582
1583 for (i = 0; i < rdev->num_crtc; i++) {
1584 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
1585 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1586 crtc_hung |= (1 << i);
1587 }
1588 }
1589
1590 for (j = 0; j < 10; j++) {
1591 for (i = 0; i < rdev->num_crtc; i++) {
1592 if (crtc_hung & (1 << i)) {
1593 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1594 if (tmp != crtc_status[i])
1595 crtc_hung &= ~(1 << i);
1596 }
1597 }
1598 if (crtc_hung == 0)
1599 return false;
1600 udelay(100);
1601 }
1602
1603 return true;
1604 }
1605
r600_gpu_check_soft_reset(struct radeon_device * rdev)1606 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
1607 {
1608 u32 reset_mask = 0;
1609 u32 tmp;
1610
1611 /* GRBM_STATUS */
1612 tmp = RREG32(R_008010_GRBM_STATUS);
1613 if (rdev->family >= CHIP_RV770) {
1614 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1615 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1616 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1617 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1618 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1619 reset_mask |= RADEON_RESET_GFX;
1620 } else {
1621 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1622 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1623 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1624 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1625 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1626 reset_mask |= RADEON_RESET_GFX;
1627 }
1628
1629 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) |
1630 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp))
1631 reset_mask |= RADEON_RESET_CP;
1632
1633 if (G_008010_GRBM_EE_BUSY(tmp))
1634 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1635
1636 /* DMA_STATUS_REG */
1637 tmp = RREG32(DMA_STATUS_REG);
1638 if (!(tmp & DMA_IDLE))
1639 reset_mask |= RADEON_RESET_DMA;
1640
1641 /* SRBM_STATUS */
1642 tmp = RREG32(R_000E50_SRBM_STATUS);
1643 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp))
1644 reset_mask |= RADEON_RESET_RLC;
1645
1646 if (G_000E50_IH_BUSY(tmp))
1647 reset_mask |= RADEON_RESET_IH;
1648
1649 if (G_000E50_SEM_BUSY(tmp))
1650 reset_mask |= RADEON_RESET_SEM;
1651
1652 if (G_000E50_GRBM_RQ_PENDING(tmp))
1653 reset_mask |= RADEON_RESET_GRBM;
1654
1655 if (G_000E50_VMC_BUSY(tmp))
1656 reset_mask |= RADEON_RESET_VMC;
1657
1658 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) |
1659 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) |
1660 G_000E50_MCDW_BUSY(tmp))
1661 reset_mask |= RADEON_RESET_MC;
1662
1663 if (r600_is_display_hung(rdev))
1664 reset_mask |= RADEON_RESET_DISPLAY;
1665
1666 /* Skip MC reset as it's mostly likely not hung, just busy */
1667 if (reset_mask & RADEON_RESET_MC) {
1668 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1669 reset_mask &= ~RADEON_RESET_MC;
1670 }
1671
1672 return reset_mask;
1673 }
1674
r600_gpu_soft_reset(struct radeon_device * rdev,u32 reset_mask)1675 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1676 {
1677 struct rv515_mc_save save;
1678 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1679 u32 tmp;
1680
1681 if (reset_mask == 0)
1682 return;
1683
1684 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1685
1686 r600_print_gpu_status_regs(rdev);
1687
1688 /* Disable CP parsing/prefetching */
1689 if (rdev->family >= CHIP_RV770)
1690 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1691 else
1692 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1693
1694 /* disable the RLC */
1695 WREG32(RLC_CNTL, 0);
1696
1697 if (reset_mask & RADEON_RESET_DMA) {
1698 /* Disable DMA */
1699 tmp = RREG32(DMA_RB_CNTL);
1700 tmp &= ~DMA_RB_ENABLE;
1701 WREG32(DMA_RB_CNTL, tmp);
1702 }
1703
1704 mdelay(50);
1705
1706 rv515_mc_stop(rdev, &save);
1707 if (r600_mc_wait_for_idle(rdev)) {
1708 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1709 }
1710
1711 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1712 if (rdev->family >= CHIP_RV770)
1713 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |
1714 S_008020_SOFT_RESET_CB(1) |
1715 S_008020_SOFT_RESET_PA(1) |
1716 S_008020_SOFT_RESET_SC(1) |
1717 S_008020_SOFT_RESET_SPI(1) |
1718 S_008020_SOFT_RESET_SX(1) |
1719 S_008020_SOFT_RESET_SH(1) |
1720 S_008020_SOFT_RESET_TC(1) |
1721 S_008020_SOFT_RESET_TA(1) |
1722 S_008020_SOFT_RESET_VC(1) |
1723 S_008020_SOFT_RESET_VGT(1);
1724 else
1725 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |
1726 S_008020_SOFT_RESET_DB(1) |
1727 S_008020_SOFT_RESET_CB(1) |
1728 S_008020_SOFT_RESET_PA(1) |
1729 S_008020_SOFT_RESET_SC(1) |
1730 S_008020_SOFT_RESET_SMX(1) |
1731 S_008020_SOFT_RESET_SPI(1) |
1732 S_008020_SOFT_RESET_SX(1) |
1733 S_008020_SOFT_RESET_SH(1) |
1734 S_008020_SOFT_RESET_TC(1) |
1735 S_008020_SOFT_RESET_TA(1) |
1736 S_008020_SOFT_RESET_VC(1) |
1737 S_008020_SOFT_RESET_VGT(1);
1738 }
1739
1740 if (reset_mask & RADEON_RESET_CP) {
1741 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |
1742 S_008020_SOFT_RESET_VGT(1);
1743
1744 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1745 }
1746
1747 if (reset_mask & RADEON_RESET_DMA) {
1748 if (rdev->family >= CHIP_RV770)
1749 srbm_soft_reset |= RV770_SOFT_RESET_DMA;
1750 else
1751 srbm_soft_reset |= SOFT_RESET_DMA;
1752 }
1753
1754 if (reset_mask & RADEON_RESET_RLC)
1755 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1);
1756
1757 if (reset_mask & RADEON_RESET_SEM)
1758 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1);
1759
1760 if (reset_mask & RADEON_RESET_IH)
1761 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1);
1762
1763 if (reset_mask & RADEON_RESET_GRBM)
1764 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1765
1766 if (!(rdev->flags & RADEON_IS_IGP)) {
1767 if (reset_mask & RADEON_RESET_MC)
1768 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1);
1769 }
1770
1771 if (reset_mask & RADEON_RESET_VMC)
1772 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1);
1773
1774 if (grbm_soft_reset) {
1775 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1776 tmp |= grbm_soft_reset;
1777 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1778 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1779 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1780
1781 udelay(50);
1782
1783 tmp &= ~grbm_soft_reset;
1784 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1785 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1786 }
1787
1788 if (srbm_soft_reset) {
1789 tmp = RREG32(SRBM_SOFT_RESET);
1790 tmp |= srbm_soft_reset;
1791 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1792 WREG32(SRBM_SOFT_RESET, tmp);
1793 tmp = RREG32(SRBM_SOFT_RESET);
1794
1795 udelay(50);
1796
1797 tmp &= ~srbm_soft_reset;
1798 WREG32(SRBM_SOFT_RESET, tmp);
1799 tmp = RREG32(SRBM_SOFT_RESET);
1800 }
1801
1802 /* Wait a little for things to settle down */
1803 mdelay(1);
1804
1805 rv515_mc_resume(rdev, &save);
1806 udelay(50);
1807
1808 r600_print_gpu_status_regs(rdev);
1809 }
1810
r600_gpu_pci_config_reset(struct radeon_device * rdev)1811 static void r600_gpu_pci_config_reset(struct radeon_device *rdev)
1812 {
1813 struct rv515_mc_save save;
1814 u32 tmp, i;
1815
1816 dev_info(rdev->dev, "GPU pci config reset\n");
1817
1818 /* disable dpm? */
1819
1820 /* Disable CP parsing/prefetching */
1821 if (rdev->family >= CHIP_RV770)
1822 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1823 else
1824 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1825
1826 /* disable the RLC */
1827 WREG32(RLC_CNTL, 0);
1828
1829 /* Disable DMA */
1830 tmp = RREG32(DMA_RB_CNTL);
1831 tmp &= ~DMA_RB_ENABLE;
1832 WREG32(DMA_RB_CNTL, tmp);
1833
1834 mdelay(50);
1835
1836 /* set mclk/sclk to bypass */
1837 if (rdev->family >= CHIP_RV770)
1838 rv770_set_clk_bypass_mode(rdev);
1839 /* disable BM */
1840 pci_clear_master(rdev->pdev);
1841 /* disable mem access */
1842 rv515_mc_stop(rdev, &save);
1843 if (r600_mc_wait_for_idle(rdev)) {
1844 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1845 }
1846
1847 /* BIF reset workaround. Not sure if this is needed on 6xx */
1848 tmp = RREG32(BUS_CNTL);
1849 tmp |= VGA_COHE_SPEC_TIMER_DIS;
1850 WREG32(BUS_CNTL, tmp);
1851
1852 tmp = RREG32(BIF_SCRATCH0);
1853
1854 /* reset */
1855 radeon_pci_config_reset(rdev);
1856 mdelay(1);
1857
1858 /* BIF reset workaround. Not sure if this is needed on 6xx */
1859 tmp = SOFT_RESET_BIF;
1860 WREG32(SRBM_SOFT_RESET, tmp);
1861 mdelay(1);
1862 WREG32(SRBM_SOFT_RESET, 0);
1863
1864 /* wait for asic to come out of reset */
1865 for (i = 0; i < rdev->usec_timeout; i++) {
1866 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
1867 break;
1868 udelay(1);
1869 }
1870 }
1871
r600_asic_reset(struct radeon_device * rdev,bool hard)1872 int r600_asic_reset(struct radeon_device *rdev, bool hard)
1873 {
1874 u32 reset_mask;
1875
1876 if (hard) {
1877 r600_gpu_pci_config_reset(rdev);
1878 return 0;
1879 }
1880
1881 reset_mask = r600_gpu_check_soft_reset(rdev);
1882
1883 if (reset_mask)
1884 r600_set_bios_scratch_engine_hung(rdev, true);
1885
1886 /* try soft reset */
1887 r600_gpu_soft_reset(rdev, reset_mask);
1888
1889 reset_mask = r600_gpu_check_soft_reset(rdev);
1890
1891 /* try pci config reset */
1892 if (reset_mask && radeon_hard_reset)
1893 r600_gpu_pci_config_reset(rdev);
1894
1895 reset_mask = r600_gpu_check_soft_reset(rdev);
1896
1897 if (!reset_mask)
1898 r600_set_bios_scratch_engine_hung(rdev, false);
1899
1900 return 0;
1901 }
1902
1903 /**
1904 * r600_gfx_is_lockup - Check if the GFX engine is locked up
1905 *
1906 * @rdev: radeon_device pointer
1907 * @ring: radeon_ring structure holding ring information
1908 *
1909 * Check if the GFX engine is locked up.
1910 * Returns true if the engine appears to be locked up, false if not.
1911 */
r600_gfx_is_lockup(struct radeon_device * rdev,struct radeon_ring * ring)1912 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1913 {
1914 u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1915
1916 if (!(reset_mask & (RADEON_RESET_GFX |
1917 RADEON_RESET_COMPUTE |
1918 RADEON_RESET_CP))) {
1919 radeon_ring_lockup_update(rdev, ring);
1920 return false;
1921 }
1922 return radeon_ring_test_lockup(rdev, ring);
1923 }
1924
r6xx_remap_render_backend(struct radeon_device * rdev,u32 tiling_pipe_num,u32 max_rb_num,u32 total_max_rb_num,u32 disabled_rb_mask)1925 u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1926 u32 tiling_pipe_num,
1927 u32 max_rb_num,
1928 u32 total_max_rb_num,
1929 u32 disabled_rb_mask)
1930 {
1931 u32 rendering_pipe_num, rb_num_width, req_rb_num;
1932 u32 pipe_rb_ratio, pipe_rb_remain, tmp;
1933 u32 data = 0, mask = 1 << (max_rb_num - 1);
1934 unsigned i, j;
1935
1936 /* mask out the RBs that don't exist on that asic */
1937 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1938 /* make sure at least one RB is available */
1939 if ((tmp & 0xff) != 0xff)
1940 disabled_rb_mask = tmp;
1941
1942 rendering_pipe_num = 1 << tiling_pipe_num;
1943 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1944 BUG_ON(rendering_pipe_num < req_rb_num);
1945
1946 pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1947 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1948
1949 if (rdev->family <= CHIP_RV740) {
1950 /* r6xx/r7xx */
1951 rb_num_width = 2;
1952 } else {
1953 /* eg+ */
1954 rb_num_width = 4;
1955 }
1956
1957 for (i = 0; i < max_rb_num; i++) {
1958 if (!(mask & disabled_rb_mask)) {
1959 for (j = 0; j < pipe_rb_ratio; j++) {
1960 data <<= rb_num_width;
1961 data |= max_rb_num - i - 1;
1962 }
1963 if (pipe_rb_remain) {
1964 data <<= rb_num_width;
1965 data |= max_rb_num - i - 1;
1966 pipe_rb_remain--;
1967 }
1968 }
1969 mask >>= 1;
1970 }
1971
1972 return data;
1973 }
1974
r600_count_pipe_bits(uint32_t val)1975 int r600_count_pipe_bits(uint32_t val)
1976 {
1977 return hweight32(val);
1978 }
1979
r600_gpu_init(struct radeon_device * rdev)1980 static void r600_gpu_init(struct radeon_device *rdev)
1981 {
1982 u32 tiling_config;
1983 u32 ramcfg;
1984 u32 cc_gc_shader_pipe_config;
1985 u32 tmp;
1986 int i, j;
1987 u32 sq_config;
1988 u32 sq_gpr_resource_mgmt_1 = 0;
1989 u32 sq_gpr_resource_mgmt_2 = 0;
1990 u32 sq_thread_resource_mgmt = 0;
1991 u32 sq_stack_resource_mgmt_1 = 0;
1992 u32 sq_stack_resource_mgmt_2 = 0;
1993 u32 disabled_rb_mask;
1994
1995 rdev->config.r600.tiling_group_size = 256;
1996 switch (rdev->family) {
1997 case CHIP_R600:
1998 rdev->config.r600.max_pipes = 4;
1999 rdev->config.r600.max_tile_pipes = 8;
2000 rdev->config.r600.max_simds = 4;
2001 rdev->config.r600.max_backends = 4;
2002 rdev->config.r600.max_gprs = 256;
2003 rdev->config.r600.max_threads = 192;
2004 rdev->config.r600.max_stack_entries = 256;
2005 rdev->config.r600.max_hw_contexts = 8;
2006 rdev->config.r600.max_gs_threads = 16;
2007 rdev->config.r600.sx_max_export_size = 128;
2008 rdev->config.r600.sx_max_export_pos_size = 16;
2009 rdev->config.r600.sx_max_export_smx_size = 128;
2010 rdev->config.r600.sq_num_cf_insts = 2;
2011 break;
2012 case CHIP_RV630:
2013 case CHIP_RV635:
2014 rdev->config.r600.max_pipes = 2;
2015 rdev->config.r600.max_tile_pipes = 2;
2016 rdev->config.r600.max_simds = 3;
2017 rdev->config.r600.max_backends = 1;
2018 rdev->config.r600.max_gprs = 128;
2019 rdev->config.r600.max_threads = 192;
2020 rdev->config.r600.max_stack_entries = 128;
2021 rdev->config.r600.max_hw_contexts = 8;
2022 rdev->config.r600.max_gs_threads = 4;
2023 rdev->config.r600.sx_max_export_size = 128;
2024 rdev->config.r600.sx_max_export_pos_size = 16;
2025 rdev->config.r600.sx_max_export_smx_size = 128;
2026 rdev->config.r600.sq_num_cf_insts = 2;
2027 break;
2028 case CHIP_RV610:
2029 case CHIP_RV620:
2030 case CHIP_RS780:
2031 case CHIP_RS880:
2032 rdev->config.r600.max_pipes = 1;
2033 rdev->config.r600.max_tile_pipes = 1;
2034 rdev->config.r600.max_simds = 2;
2035 rdev->config.r600.max_backends = 1;
2036 rdev->config.r600.max_gprs = 128;
2037 rdev->config.r600.max_threads = 192;
2038 rdev->config.r600.max_stack_entries = 128;
2039 rdev->config.r600.max_hw_contexts = 4;
2040 rdev->config.r600.max_gs_threads = 4;
2041 rdev->config.r600.sx_max_export_size = 128;
2042 rdev->config.r600.sx_max_export_pos_size = 16;
2043 rdev->config.r600.sx_max_export_smx_size = 128;
2044 rdev->config.r600.sq_num_cf_insts = 1;
2045 break;
2046 case CHIP_RV670:
2047 rdev->config.r600.max_pipes = 4;
2048 rdev->config.r600.max_tile_pipes = 4;
2049 rdev->config.r600.max_simds = 4;
2050 rdev->config.r600.max_backends = 4;
2051 rdev->config.r600.max_gprs = 192;
2052 rdev->config.r600.max_threads = 192;
2053 rdev->config.r600.max_stack_entries = 256;
2054 rdev->config.r600.max_hw_contexts = 8;
2055 rdev->config.r600.max_gs_threads = 16;
2056 rdev->config.r600.sx_max_export_size = 128;
2057 rdev->config.r600.sx_max_export_pos_size = 16;
2058 rdev->config.r600.sx_max_export_smx_size = 128;
2059 rdev->config.r600.sq_num_cf_insts = 2;
2060 break;
2061 default:
2062 break;
2063 }
2064
2065 /* Initialize HDP */
2066 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2067 WREG32((0x2c14 + j), 0x00000000);
2068 WREG32((0x2c18 + j), 0x00000000);
2069 WREG32((0x2c1c + j), 0x00000000);
2070 WREG32((0x2c20 + j), 0x00000000);
2071 WREG32((0x2c24 + j), 0x00000000);
2072 }
2073
2074 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
2075
2076 /* Setup tiling */
2077 tiling_config = 0;
2078 ramcfg = RREG32(RAMCFG);
2079 switch (rdev->config.r600.max_tile_pipes) {
2080 case 1:
2081 tiling_config |= PIPE_TILING(0);
2082 break;
2083 case 2:
2084 tiling_config |= PIPE_TILING(1);
2085 break;
2086 case 4:
2087 tiling_config |= PIPE_TILING(2);
2088 break;
2089 case 8:
2090 tiling_config |= PIPE_TILING(3);
2091 break;
2092 default:
2093 break;
2094 }
2095 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
2096 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
2097 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
2098 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
2099
2100 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
2101 if (tmp > 3) {
2102 tiling_config |= ROW_TILING(3);
2103 tiling_config |= SAMPLE_SPLIT(3);
2104 } else {
2105 tiling_config |= ROW_TILING(tmp);
2106 tiling_config |= SAMPLE_SPLIT(tmp);
2107 }
2108 tiling_config |= BANK_SWAPS(1);
2109
2110 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
2111 tmp = rdev->config.r600.max_simds -
2112 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
2113 rdev->config.r600.active_simds = tmp;
2114
2115 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
2116 tmp = 0;
2117 for (i = 0; i < rdev->config.r600.max_backends; i++)
2118 tmp |= (1 << i);
2119 /* if all the backends are disabled, fix it up here */
2120 if ((disabled_rb_mask & tmp) == tmp) {
2121 for (i = 0; i < rdev->config.r600.max_backends; i++)
2122 disabled_rb_mask &= ~(1 << i);
2123 }
2124 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
2125 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
2126 R6XX_MAX_BACKENDS, disabled_rb_mask);
2127 tiling_config |= tmp << 16;
2128 rdev->config.r600.backend_map = tmp;
2129
2130 rdev->config.r600.tile_config = tiling_config;
2131 WREG32(GB_TILING_CONFIG, tiling_config);
2132 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
2133 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
2134 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
2135
2136 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
2137 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
2138 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
2139
2140 /* Setup some CP states */
2141 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
2142 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
2143
2144 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
2145 SYNC_WALKER | SYNC_ALIGNER));
2146 /* Setup various GPU states */
2147 if (rdev->family == CHIP_RV670)
2148 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
2149
2150 tmp = RREG32(SX_DEBUG_1);
2151 tmp |= SMX_EVENT_RELEASE;
2152 if ((rdev->family > CHIP_R600))
2153 tmp |= ENABLE_NEW_SMX_ADDRESS;
2154 WREG32(SX_DEBUG_1, tmp);
2155
2156 if (((rdev->family) == CHIP_R600) ||
2157 ((rdev->family) == CHIP_RV630) ||
2158 ((rdev->family) == CHIP_RV610) ||
2159 ((rdev->family) == CHIP_RV620) ||
2160 ((rdev->family) == CHIP_RS780) ||
2161 ((rdev->family) == CHIP_RS880)) {
2162 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
2163 } else {
2164 WREG32(DB_DEBUG, 0);
2165 }
2166 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
2167 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
2168
2169 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2170 WREG32(VGT_NUM_INSTANCES, 0);
2171
2172 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
2173 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
2174
2175 tmp = RREG32(SQ_MS_FIFO_SIZES);
2176 if (((rdev->family) == CHIP_RV610) ||
2177 ((rdev->family) == CHIP_RV620) ||
2178 ((rdev->family) == CHIP_RS780) ||
2179 ((rdev->family) == CHIP_RS880)) {
2180 tmp = (CACHE_FIFO_SIZE(0xa) |
2181 FETCH_FIFO_HIWATER(0xa) |
2182 DONE_FIFO_HIWATER(0xe0) |
2183 ALU_UPDATE_FIFO_HIWATER(0x8));
2184 } else if (((rdev->family) == CHIP_R600) ||
2185 ((rdev->family) == CHIP_RV630)) {
2186 tmp &= ~DONE_FIFO_HIWATER(0xff);
2187 tmp |= DONE_FIFO_HIWATER(0x4);
2188 }
2189 WREG32(SQ_MS_FIFO_SIZES, tmp);
2190
2191 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
2192 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
2193 */
2194 sq_config = RREG32(SQ_CONFIG);
2195 sq_config &= ~(PS_PRIO(3) |
2196 VS_PRIO(3) |
2197 GS_PRIO(3) |
2198 ES_PRIO(3));
2199 sq_config |= (DX9_CONSTS |
2200 VC_ENABLE |
2201 PS_PRIO(0) |
2202 VS_PRIO(1) |
2203 GS_PRIO(2) |
2204 ES_PRIO(3));
2205
2206 if ((rdev->family) == CHIP_R600) {
2207 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
2208 NUM_VS_GPRS(124) |
2209 NUM_CLAUSE_TEMP_GPRS(4));
2210 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
2211 NUM_ES_GPRS(0));
2212 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
2213 NUM_VS_THREADS(48) |
2214 NUM_GS_THREADS(4) |
2215 NUM_ES_THREADS(4));
2216 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
2217 NUM_VS_STACK_ENTRIES(128));
2218 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
2219 NUM_ES_STACK_ENTRIES(0));
2220 } else if (((rdev->family) == CHIP_RV610) ||
2221 ((rdev->family) == CHIP_RV620) ||
2222 ((rdev->family) == CHIP_RS780) ||
2223 ((rdev->family) == CHIP_RS880)) {
2224 /* no vertex cache */
2225 sq_config &= ~VC_ENABLE;
2226
2227 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2228 NUM_VS_GPRS(44) |
2229 NUM_CLAUSE_TEMP_GPRS(2));
2230 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2231 NUM_ES_GPRS(17));
2232 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2233 NUM_VS_THREADS(78) |
2234 NUM_GS_THREADS(4) |
2235 NUM_ES_THREADS(31));
2236 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2237 NUM_VS_STACK_ENTRIES(40));
2238 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2239 NUM_ES_STACK_ENTRIES(16));
2240 } else if (((rdev->family) == CHIP_RV630) ||
2241 ((rdev->family) == CHIP_RV635)) {
2242 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2243 NUM_VS_GPRS(44) |
2244 NUM_CLAUSE_TEMP_GPRS(2));
2245 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
2246 NUM_ES_GPRS(18));
2247 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2248 NUM_VS_THREADS(78) |
2249 NUM_GS_THREADS(4) |
2250 NUM_ES_THREADS(31));
2251 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2252 NUM_VS_STACK_ENTRIES(40));
2253 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2254 NUM_ES_STACK_ENTRIES(16));
2255 } else if ((rdev->family) == CHIP_RV670) {
2256 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2257 NUM_VS_GPRS(44) |
2258 NUM_CLAUSE_TEMP_GPRS(2));
2259 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2260 NUM_ES_GPRS(17));
2261 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2262 NUM_VS_THREADS(78) |
2263 NUM_GS_THREADS(4) |
2264 NUM_ES_THREADS(31));
2265 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
2266 NUM_VS_STACK_ENTRIES(64));
2267 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
2268 NUM_ES_STACK_ENTRIES(64));
2269 }
2270
2271 WREG32(SQ_CONFIG, sq_config);
2272 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2273 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2274 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2275 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2276 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2277
2278 if (((rdev->family) == CHIP_RV610) ||
2279 ((rdev->family) == CHIP_RV620) ||
2280 ((rdev->family) == CHIP_RS780) ||
2281 ((rdev->family) == CHIP_RS880)) {
2282 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
2283 } else {
2284 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
2285 }
2286
2287 /* More default values. 2D/3D driver should adjust as needed */
2288 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
2289 S1_X(0x4) | S1_Y(0xc)));
2290 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
2291 S1_X(0x2) | S1_Y(0x2) |
2292 S2_X(0xa) | S2_Y(0x6) |
2293 S3_X(0x6) | S3_Y(0xa)));
2294 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
2295 S1_X(0x4) | S1_Y(0xc) |
2296 S2_X(0x1) | S2_Y(0x6) |
2297 S3_X(0xa) | S3_Y(0xe)));
2298 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
2299 S5_X(0x0) | S5_Y(0x0) |
2300 S6_X(0xb) | S6_Y(0x4) |
2301 S7_X(0x7) | S7_Y(0x8)));
2302
2303 WREG32(VGT_STRMOUT_EN, 0);
2304 tmp = rdev->config.r600.max_pipes * 16;
2305 switch (rdev->family) {
2306 case CHIP_RV610:
2307 case CHIP_RV620:
2308 case CHIP_RS780:
2309 case CHIP_RS880:
2310 tmp += 32;
2311 break;
2312 case CHIP_RV670:
2313 tmp += 128;
2314 break;
2315 default:
2316 break;
2317 }
2318 if (tmp > 256) {
2319 tmp = 256;
2320 }
2321 WREG32(VGT_ES_PER_GS, 128);
2322 WREG32(VGT_GS_PER_ES, tmp);
2323 WREG32(VGT_GS_PER_VS, 2);
2324 WREG32(VGT_GS_VERTEX_REUSE, 16);
2325
2326 /* more default values. 2D/3D driver should adjust as needed */
2327 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2328 WREG32(VGT_STRMOUT_EN, 0);
2329 WREG32(SX_MISC, 0);
2330 WREG32(PA_SC_MODE_CNTL, 0);
2331 WREG32(PA_SC_AA_CONFIG, 0);
2332 WREG32(PA_SC_LINE_STIPPLE, 0);
2333 WREG32(SPI_INPUT_Z, 0);
2334 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
2335 WREG32(CB_COLOR7_FRAG, 0);
2336
2337 /* Clear render buffer base addresses */
2338 WREG32(CB_COLOR0_BASE, 0);
2339 WREG32(CB_COLOR1_BASE, 0);
2340 WREG32(CB_COLOR2_BASE, 0);
2341 WREG32(CB_COLOR3_BASE, 0);
2342 WREG32(CB_COLOR4_BASE, 0);
2343 WREG32(CB_COLOR5_BASE, 0);
2344 WREG32(CB_COLOR6_BASE, 0);
2345 WREG32(CB_COLOR7_BASE, 0);
2346 WREG32(CB_COLOR7_FRAG, 0);
2347
2348 switch (rdev->family) {
2349 case CHIP_RV610:
2350 case CHIP_RV620:
2351 case CHIP_RS780:
2352 case CHIP_RS880:
2353 tmp = TC_L2_SIZE(8);
2354 break;
2355 case CHIP_RV630:
2356 case CHIP_RV635:
2357 tmp = TC_L2_SIZE(4);
2358 break;
2359 case CHIP_R600:
2360 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
2361 break;
2362 default:
2363 tmp = TC_L2_SIZE(0);
2364 break;
2365 }
2366 WREG32(TC_CNTL, tmp);
2367
2368 tmp = RREG32(HDP_HOST_PATH_CNTL);
2369 WREG32(HDP_HOST_PATH_CNTL, tmp);
2370
2371 tmp = RREG32(ARB_POP);
2372 tmp |= ENABLE_TC128;
2373 WREG32(ARB_POP, tmp);
2374
2375 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2376 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
2377 NUM_CLIP_SEQ(3)));
2378 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
2379 WREG32(VC_ENHANCE, 0);
2380 }
2381
2382
2383 /*
2384 * Indirect registers accessor
2385 */
r600_pciep_rreg(struct radeon_device * rdev,u32 reg)2386 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2387 {
2388 unsigned long flags;
2389 u32 r;
2390
2391 spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2392 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2393 (void)RREG32(PCIE_PORT_INDEX);
2394 r = RREG32(PCIE_PORT_DATA);
2395 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2396 return r;
2397 }
2398
r600_pciep_wreg(struct radeon_device * rdev,u32 reg,u32 v)2399 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2400 {
2401 unsigned long flags;
2402
2403 spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2404 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2405 (void)RREG32(PCIE_PORT_INDEX);
2406 WREG32(PCIE_PORT_DATA, (v));
2407 (void)RREG32(PCIE_PORT_DATA);
2408 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2409 }
2410
2411 /*
2412 * CP & Ring
2413 */
r600_cp_stop(struct radeon_device * rdev)2414 void r600_cp_stop(struct radeon_device *rdev)
2415 {
2416 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2417 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2418 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
2419 WREG32(SCRATCH_UMSK, 0);
2420 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2421 }
2422
r600_init_microcode(struct radeon_device * rdev)2423 int r600_init_microcode(struct radeon_device *rdev)
2424 {
2425 const char *chip_name;
2426 const char *rlc_chip_name;
2427 const char *smc_chip_name = "RV770";
2428 size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0;
2429 char fw_name[30];
2430 int err;
2431
2432 DRM_DEBUG("\n");
2433
2434 switch (rdev->family) {
2435 case CHIP_R600:
2436 chip_name = "R600";
2437 rlc_chip_name = "R600";
2438 break;
2439 case CHIP_RV610:
2440 chip_name = "RV610";
2441 rlc_chip_name = "R600";
2442 break;
2443 case CHIP_RV630:
2444 chip_name = "RV630";
2445 rlc_chip_name = "R600";
2446 break;
2447 case CHIP_RV620:
2448 chip_name = "RV620";
2449 rlc_chip_name = "R600";
2450 break;
2451 case CHIP_RV635:
2452 chip_name = "RV635";
2453 rlc_chip_name = "R600";
2454 break;
2455 case CHIP_RV670:
2456 chip_name = "RV670";
2457 rlc_chip_name = "R600";
2458 break;
2459 case CHIP_RS780:
2460 case CHIP_RS880:
2461 chip_name = "RS780";
2462 rlc_chip_name = "R600";
2463 break;
2464 case CHIP_RV770:
2465 chip_name = "RV770";
2466 rlc_chip_name = "R700";
2467 smc_chip_name = "RV770";
2468 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4);
2469 break;
2470 case CHIP_RV730:
2471 chip_name = "RV730";
2472 rlc_chip_name = "R700";
2473 smc_chip_name = "RV730";
2474 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4);
2475 break;
2476 case CHIP_RV710:
2477 chip_name = "RV710";
2478 rlc_chip_name = "R700";
2479 smc_chip_name = "RV710";
2480 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4);
2481 break;
2482 case CHIP_RV740:
2483 chip_name = "RV730";
2484 rlc_chip_name = "R700";
2485 smc_chip_name = "RV740";
2486 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4);
2487 break;
2488 case CHIP_CEDAR:
2489 chip_name = "CEDAR";
2490 rlc_chip_name = "CEDAR";
2491 smc_chip_name = "CEDAR";
2492 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4);
2493 break;
2494 case CHIP_REDWOOD:
2495 chip_name = "REDWOOD";
2496 rlc_chip_name = "REDWOOD";
2497 smc_chip_name = "REDWOOD";
2498 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4);
2499 break;
2500 case CHIP_JUNIPER:
2501 chip_name = "JUNIPER";
2502 rlc_chip_name = "JUNIPER";
2503 smc_chip_name = "JUNIPER";
2504 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4);
2505 break;
2506 case CHIP_CYPRESS:
2507 case CHIP_HEMLOCK:
2508 chip_name = "CYPRESS";
2509 rlc_chip_name = "CYPRESS";
2510 smc_chip_name = "CYPRESS";
2511 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4);
2512 break;
2513 case CHIP_PALM:
2514 chip_name = "PALM";
2515 rlc_chip_name = "SUMO";
2516 break;
2517 case CHIP_SUMO:
2518 chip_name = "SUMO";
2519 rlc_chip_name = "SUMO";
2520 break;
2521 case CHIP_SUMO2:
2522 chip_name = "SUMO2";
2523 rlc_chip_name = "SUMO";
2524 break;
2525 default: BUG();
2526 }
2527
2528 if (rdev->family >= CHIP_CEDAR) {
2529 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2530 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2531 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2532 } else if (rdev->family >= CHIP_RV770) {
2533 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2534 me_req_size = R700_PM4_UCODE_SIZE * 4;
2535 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2536 } else {
2537 pfp_req_size = R600_PFP_UCODE_SIZE * 4;
2538 me_req_size = R600_PM4_UCODE_SIZE * 12;
2539 rlc_req_size = R600_RLC_UCODE_SIZE * 4;
2540 }
2541
2542 DRM_INFO("Loading %s Microcode\n", chip_name);
2543
2544 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", chip_name);
2545 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
2546 if (err)
2547 goto out;
2548 if (rdev->pfp_fw->datasize != pfp_req_size) {
2549 pr_err("r600_cp: Bogus length %zu in firmware \"%s\"\n",
2550 rdev->pfp_fw->datasize, fw_name);
2551 err = -EINVAL;
2552 goto out;
2553 }
2554
2555 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", chip_name);
2556 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
2557 if (err)
2558 goto out;
2559 if (rdev->me_fw->datasize != me_req_size) {
2560 pr_err("r600_cp: Bogus length %zu in firmware \"%s\"\n",
2561 rdev->me_fw->datasize, fw_name);
2562 err = -EINVAL;
2563 }
2564
2565 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_rlc", rlc_chip_name);
2566 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
2567 if (err)
2568 goto out;
2569 if (rdev->rlc_fw->datasize != rlc_req_size) {
2570 pr_err("r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2571 rdev->rlc_fw->datasize, fw_name);
2572 err = -EINVAL;
2573 }
2574
2575 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) {
2576 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_smc", smc_chip_name);
2577 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
2578 if (err) {
2579 pr_err("smc: error loading firmware \"%s\"\n", fw_name);
2580 release_firmware(rdev->smc_fw);
2581 rdev->smc_fw = NULL;
2582 err = 0;
2583 } else if (rdev->smc_fw->datasize != smc_req_size) {
2584 pr_err("smc: Bogus length %zu in firmware \"%s\"\n",
2585 rdev->smc_fw->datasize, fw_name);
2586 err = -EINVAL;
2587 }
2588 }
2589
2590 out:
2591 if (err) {
2592 if (err != -EINVAL)
2593 pr_err("r600_cp: Failed to load firmware \"%s\"\n",
2594 fw_name);
2595 release_firmware(rdev->pfp_fw);
2596 rdev->pfp_fw = NULL;
2597 release_firmware(rdev->me_fw);
2598 rdev->me_fw = NULL;
2599 release_firmware(rdev->rlc_fw);
2600 rdev->rlc_fw = NULL;
2601 release_firmware(rdev->smc_fw);
2602 rdev->smc_fw = NULL;
2603 }
2604 return err;
2605 }
2606
r600_gfx_get_rptr(struct radeon_device * rdev,struct radeon_ring * ring)2607 u32 r600_gfx_get_rptr(struct radeon_device *rdev,
2608 struct radeon_ring *ring)
2609 {
2610 u32 rptr;
2611
2612 if (rdev->wb.enabled)
2613 rptr = rdev->wb.wb[ring->rptr_offs/4];
2614 else
2615 rptr = RREG32(R600_CP_RB_RPTR);
2616
2617 return rptr;
2618 }
2619
r600_gfx_get_wptr(struct radeon_device * rdev,struct radeon_ring * ring)2620 u32 r600_gfx_get_wptr(struct radeon_device *rdev,
2621 struct radeon_ring *ring)
2622 {
2623 return RREG32(R600_CP_RB_WPTR);
2624 }
2625
r600_gfx_set_wptr(struct radeon_device * rdev,struct radeon_ring * ring)2626 void r600_gfx_set_wptr(struct radeon_device *rdev,
2627 struct radeon_ring *ring)
2628 {
2629 WREG32(R600_CP_RB_WPTR, ring->wptr);
2630 (void)RREG32(R600_CP_RB_WPTR);
2631 }
2632
2633 /**
2634 * r600_fini_microcode - drop the firmwares image references
2635 *
2636 * @rdev: radeon_device pointer
2637 *
2638 * Drop the pfp, me and rlc firmwares image references.
2639 * Called at driver shutdown.
2640 */
r600_fini_microcode(struct radeon_device * rdev)2641 void r600_fini_microcode(struct radeon_device *rdev)
2642 {
2643 release_firmware(rdev->pfp_fw);
2644 rdev->pfp_fw = NULL;
2645 release_firmware(rdev->me_fw);
2646 rdev->me_fw = NULL;
2647 release_firmware(rdev->rlc_fw);
2648 rdev->rlc_fw = NULL;
2649 release_firmware(rdev->smc_fw);
2650 rdev->smc_fw = NULL;
2651 }
2652
r600_cp_load_microcode(struct radeon_device * rdev)2653 static int r600_cp_load_microcode(struct radeon_device *rdev)
2654 {
2655 const __be32 *fw_data;
2656 int i;
2657
2658 if (!rdev->me_fw || !rdev->pfp_fw)
2659 return -EINVAL;
2660
2661 r600_cp_stop(rdev);
2662
2663 WREG32(CP_RB_CNTL,
2664 #ifdef __BIG_ENDIAN
2665 BUF_SWAP_32BIT |
2666 #endif
2667 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2668
2669 /* Reset cp */
2670 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2671 RREG32(GRBM_SOFT_RESET);
2672 mdelay(15);
2673 WREG32(GRBM_SOFT_RESET, 0);
2674
2675 WREG32(CP_ME_RAM_WADDR, 0);
2676
2677 fw_data = (const __be32 *)rdev->me_fw->data;
2678 WREG32(CP_ME_RAM_WADDR, 0);
2679 for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++)
2680 WREG32(CP_ME_RAM_DATA,
2681 be32_to_cpup(fw_data++));
2682
2683 fw_data = (const __be32 *)rdev->pfp_fw->data;
2684 WREG32(CP_PFP_UCODE_ADDR, 0);
2685 for (i = 0; i < R600_PFP_UCODE_SIZE; i++)
2686 WREG32(CP_PFP_UCODE_DATA,
2687 be32_to_cpup(fw_data++));
2688
2689 WREG32(CP_PFP_UCODE_ADDR, 0);
2690 WREG32(CP_ME_RAM_WADDR, 0);
2691 WREG32(CP_ME_RAM_RADDR, 0);
2692 return 0;
2693 }
2694
r600_cp_start(struct radeon_device * rdev)2695 int r600_cp_start(struct radeon_device *rdev)
2696 {
2697 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2698 int r;
2699 uint32_t cp_me;
2700
2701 r = radeon_ring_lock(rdev, ring, 7);
2702 if (r) {
2703 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2704 return r;
2705 }
2706 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2707 radeon_ring_write(ring, 0x1);
2708 if (rdev->family >= CHIP_RV770) {
2709 radeon_ring_write(ring, 0x0);
2710 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2711 } else {
2712 radeon_ring_write(ring, 0x3);
2713 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2714 }
2715 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2716 radeon_ring_write(ring, 0);
2717 radeon_ring_write(ring, 0);
2718 radeon_ring_unlock_commit(rdev, ring, false);
2719
2720 cp_me = 0xff;
2721 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2722 return 0;
2723 }
2724
r600_cp_resume(struct radeon_device * rdev)2725 int r600_cp_resume(struct radeon_device *rdev)
2726 {
2727 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2728 u32 tmp;
2729 u32 rb_bufsz;
2730 int r;
2731
2732 /* Reset cp */
2733 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2734 RREG32(GRBM_SOFT_RESET);
2735 mdelay(15);
2736 WREG32(GRBM_SOFT_RESET, 0);
2737
2738 /* Set ring buffer size */
2739 rb_bufsz = order_base_2(ring->ring_size / 8);
2740 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2741 #ifdef __BIG_ENDIAN
2742 tmp |= BUF_SWAP_32BIT;
2743 #endif
2744 WREG32(CP_RB_CNTL, tmp);
2745 WREG32(CP_SEM_WAIT_TIMER, 0x0);
2746
2747 /* Set the write pointer delay */
2748 WREG32(CP_RB_WPTR_DELAY, 0);
2749
2750 /* Initialize the ring buffer's read and write pointers */
2751 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2752 WREG32(CP_RB_RPTR_WR, 0);
2753 ring->wptr = 0;
2754 WREG32(CP_RB_WPTR, ring->wptr);
2755
2756 /* set the wb address whether it's enabled or not */
2757 WREG32(CP_RB_RPTR_ADDR,
2758 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2759 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2760 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2761
2762 if (rdev->wb.enabled)
2763 WREG32(SCRATCH_UMSK, 0xff);
2764 else {
2765 tmp |= RB_NO_UPDATE;
2766 WREG32(SCRATCH_UMSK, 0);
2767 }
2768
2769 mdelay(1);
2770 WREG32(CP_RB_CNTL, tmp);
2771
2772 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2773 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2774
2775 r600_cp_start(rdev);
2776 ring->ready = true;
2777 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2778 if (r) {
2779 ring->ready = false;
2780 return r;
2781 }
2782
2783 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2784 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2785
2786 return 0;
2787 }
2788
r600_ring_init(struct radeon_device * rdev,struct radeon_ring * ring,unsigned ring_size)2789 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2790 {
2791 u32 rb_bufsz;
2792 int r;
2793
2794 /* Align ring size */
2795 rb_bufsz = order_base_2(ring_size / 8);
2796 ring_size = (1 << (rb_bufsz + 1)) * 4;
2797 ring->ring_size = ring_size;
2798 ring->align_mask = 16 - 1;
2799
2800 if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2801 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2802 if (r) {
2803 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2804 ring->rptr_save_reg = 0;
2805 }
2806 }
2807 }
2808
r600_cp_fini(struct radeon_device * rdev)2809 void r600_cp_fini(struct radeon_device *rdev)
2810 {
2811 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2812 r600_cp_stop(rdev);
2813 radeon_ring_fini(rdev, ring);
2814 radeon_scratch_free(rdev, ring->rptr_save_reg);
2815 }
2816
2817 /*
2818 * GPU scratch registers helpers function.
2819 */
r600_scratch_init(struct radeon_device * rdev)2820 void r600_scratch_init(struct radeon_device *rdev)
2821 {
2822 int i;
2823
2824 rdev->scratch.num_reg = 7;
2825 rdev->scratch.reg_base = SCRATCH_REG0;
2826 for (i = 0; i < rdev->scratch.num_reg; i++) {
2827 rdev->scratch.free[i] = true;
2828 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2829 }
2830 }
2831
r600_ring_test(struct radeon_device * rdev,struct radeon_ring * ring)2832 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2833 {
2834 uint32_t scratch;
2835 uint32_t tmp = 0;
2836 unsigned i;
2837 int r;
2838
2839 r = radeon_scratch_get(rdev, &scratch);
2840 if (r) {
2841 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2842 return r;
2843 }
2844 WREG32(scratch, 0xCAFEDEAD);
2845 r = radeon_ring_lock(rdev, ring, 3);
2846 if (r) {
2847 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
2848 radeon_scratch_free(rdev, scratch);
2849 return r;
2850 }
2851 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2852 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2853 radeon_ring_write(ring, 0xDEADBEEF);
2854 radeon_ring_unlock_commit(rdev, ring, false);
2855 for (i = 0; i < rdev->usec_timeout; i++) {
2856 tmp = RREG32(scratch);
2857 if (tmp == 0xDEADBEEF)
2858 break;
2859 DRM_UDELAY(1);
2860 }
2861 if (i < rdev->usec_timeout) {
2862 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2863 } else {
2864 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2865 ring->idx, scratch, tmp);
2866 r = -EINVAL;
2867 }
2868 radeon_scratch_free(rdev, scratch);
2869 return r;
2870 }
2871
2872 /*
2873 * CP fences/semaphores
2874 */
2875
r600_fence_ring_emit(struct radeon_device * rdev,struct radeon_fence * fence)2876 void r600_fence_ring_emit(struct radeon_device *rdev,
2877 struct radeon_fence *fence)
2878 {
2879 struct radeon_ring *ring = &rdev->ring[fence->ring];
2880 u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA |
2881 PACKET3_SH_ACTION_ENA;
2882
2883 if (rdev->family >= CHIP_RV770)
2884 cp_coher_cntl |= PACKET3_FULL_CACHE_ENA;
2885
2886 if (rdev->wb.use_event) {
2887 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2888 /* flush read cache over gart */
2889 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2890 radeon_ring_write(ring, cp_coher_cntl);
2891 radeon_ring_write(ring, 0xFFFFFFFF);
2892 radeon_ring_write(ring, 0);
2893 radeon_ring_write(ring, 10); /* poll interval */
2894 /* EVENT_WRITE_EOP - flush caches, send int */
2895 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2896 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2897 radeon_ring_write(ring, lower_32_bits(addr));
2898 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2899 radeon_ring_write(ring, fence->seq);
2900 radeon_ring_write(ring, 0);
2901 } else {
2902 /* flush read cache over gart */
2903 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2904 radeon_ring_write(ring, cp_coher_cntl);
2905 radeon_ring_write(ring, 0xFFFFFFFF);
2906 radeon_ring_write(ring, 0);
2907 radeon_ring_write(ring, 10); /* poll interval */
2908 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2909 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2910 /* wait for 3D idle clean */
2911 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2912 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2913 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2914 /* Emit fence sequence & fire IRQ */
2915 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2916 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2917 radeon_ring_write(ring, fence->seq);
2918 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2919 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2920 radeon_ring_write(ring, RB_INT_STAT);
2921 }
2922 }
2923
2924 /**
2925 * r600_semaphore_ring_emit - emit a semaphore on the CP ring
2926 *
2927 * @rdev: radeon_device pointer
2928 * @ring: radeon ring buffer object
2929 * @semaphore: radeon semaphore object
2930 * @emit_wait: Is this a sempahore wait?
2931 *
2932 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
2933 * from running ahead of semaphore waits.
2934 */
r600_semaphore_ring_emit(struct radeon_device * rdev,struct radeon_ring * ring,struct radeon_semaphore * semaphore,bool emit_wait)2935 bool r600_semaphore_ring_emit(struct radeon_device *rdev,
2936 struct radeon_ring *ring,
2937 struct radeon_semaphore *semaphore,
2938 bool emit_wait)
2939 {
2940 uint64_t addr = semaphore->gpu_addr;
2941 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2942
2943 if (rdev->family < CHIP_CAYMAN)
2944 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2945
2946 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2947 radeon_ring_write(ring, lower_32_bits(addr));
2948 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
2949
2950 /* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */
2951 if (emit_wait && (rdev->family >= CHIP_CEDAR)) {
2952 /* Prevent the PFP from running ahead of the semaphore wait */
2953 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2954 radeon_ring_write(ring, 0x0);
2955 }
2956
2957 return true;
2958 }
2959
2960 /**
2961 * r600_copy_cpdma - copy pages using the CP DMA engine
2962 *
2963 * @rdev: radeon_device pointer
2964 * @src_offset: src GPU address
2965 * @dst_offset: dst GPU address
2966 * @num_gpu_pages: number of GPU pages to xfer
2967 * @fence: radeon fence object
2968 *
2969 * Copy GPU paging using the CP DMA engine (r6xx+).
2970 * Used by the radeon ttm implementation to move pages if
2971 * registered as the asic copy callback.
2972 */
r600_copy_cpdma(struct radeon_device * rdev,uint64_t src_offset,uint64_t dst_offset,unsigned num_gpu_pages,struct reservation_object * resv)2973 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev,
2974 uint64_t src_offset, uint64_t dst_offset,
2975 unsigned num_gpu_pages,
2976 struct reservation_object *resv)
2977 {
2978 struct radeon_fence *fence;
2979 struct radeon_sync sync;
2980 int ring_index = rdev->asic->copy.blit_ring_index;
2981 struct radeon_ring *ring = &rdev->ring[ring_index];
2982 u32 size_in_bytes, cur_size_in_bytes, tmp;
2983 int i, num_loops;
2984 int r = 0;
2985
2986 radeon_sync_create(&sync);
2987
2988 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
2989 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
2990 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24);
2991 if (r) {
2992 DRM_ERROR("radeon: moving bo (%d).\n", r);
2993 radeon_sync_free(rdev, &sync, NULL);
2994 return ERR_PTR(r);
2995 }
2996
2997 radeon_sync_resv(rdev, &sync, resv, false);
2998 radeon_sync_rings(rdev, &sync, ring->idx);
2999
3000 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3001 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3002 radeon_ring_write(ring, WAIT_3D_IDLE_bit);
3003 for (i = 0; i < num_loops; i++) {
3004 cur_size_in_bytes = size_in_bytes;
3005 if (cur_size_in_bytes > 0x1fffff)
3006 cur_size_in_bytes = 0x1fffff;
3007 size_in_bytes -= cur_size_in_bytes;
3008 tmp = upper_32_bits(src_offset) & 0xff;
3009 if (size_in_bytes == 0)
3010 tmp |= PACKET3_CP_DMA_CP_SYNC;
3011 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4));
3012 radeon_ring_write(ring, lower_32_bits(src_offset));
3013 radeon_ring_write(ring, tmp);
3014 radeon_ring_write(ring, lower_32_bits(dst_offset));
3015 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
3016 radeon_ring_write(ring, cur_size_in_bytes);
3017 src_offset += cur_size_in_bytes;
3018 dst_offset += cur_size_in_bytes;
3019 }
3020 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3021 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3022 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit);
3023
3024 r = radeon_fence_emit(rdev, &fence, ring->idx);
3025 if (r) {
3026 radeon_ring_unlock_undo(rdev, ring);
3027 radeon_sync_free(rdev, &sync, NULL);
3028 return ERR_PTR(r);
3029 }
3030
3031 radeon_ring_unlock_commit(rdev, ring, false);
3032 radeon_sync_free(rdev, &sync, fence);
3033
3034 return fence;
3035 }
3036
r600_set_surface_reg(struct radeon_device * rdev,int reg,uint32_t tiling_flags,uint32_t pitch,uint32_t offset,uint32_t obj_size)3037 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
3038 uint32_t tiling_flags, uint32_t pitch,
3039 uint32_t offset, uint32_t obj_size)
3040 {
3041 /* FIXME: implement */
3042 return 0;
3043 }
3044
r600_clear_surface_reg(struct radeon_device * rdev,int reg)3045 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
3046 {
3047 /* FIXME: implement */
3048 }
3049
r600_uvd_init(struct radeon_device * rdev)3050 static void r600_uvd_init(struct radeon_device *rdev)
3051 {
3052 int r;
3053
3054 if (!rdev->has_uvd)
3055 return;
3056
3057 r = radeon_uvd_init(rdev);
3058 if (r) {
3059 dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
3060 /*
3061 * At this point rdev->uvd.vcpu_bo is NULL which trickles down
3062 * to early fails uvd_v1_0_resume() and thus nothing happens
3063 * there. So it is pointless to try to go through that code
3064 * hence why we disable uvd here.
3065 */
3066 rdev->has_uvd = 0;
3067 return;
3068 }
3069 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
3070 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
3071 }
3072
r600_uvd_start(struct radeon_device * rdev)3073 static void r600_uvd_start(struct radeon_device *rdev)
3074 {
3075 int r;
3076
3077 if (!rdev->has_uvd)
3078 return;
3079
3080 r = uvd_v1_0_resume(rdev);
3081 if (r) {
3082 dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
3083 goto error;
3084 }
3085 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
3086 if (r) {
3087 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
3088 goto error;
3089 }
3090 return;
3091
3092 error:
3093 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
3094 }
3095
r600_uvd_resume(struct radeon_device * rdev)3096 static void r600_uvd_resume(struct radeon_device *rdev)
3097 {
3098 struct radeon_ring *ring;
3099 int r;
3100
3101 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
3102 return;
3103
3104 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
3105 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
3106 if (r) {
3107 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
3108 return;
3109 }
3110 r = uvd_v1_0_init(rdev);
3111 if (r) {
3112 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
3113 return;
3114 }
3115 }
3116
r600_startup(struct radeon_device * rdev)3117 static int r600_startup(struct radeon_device *rdev)
3118 {
3119 struct radeon_ring *ring;
3120 int r;
3121
3122 /* enable pcie gen2 link */
3123 r600_pcie_gen2_enable(rdev);
3124
3125 /* scratch needs to be initialized before MC */
3126 r = r600_vram_scratch_init(rdev);
3127 if (r)
3128 return r;
3129
3130 r600_mc_program(rdev);
3131
3132 if (rdev->flags & RADEON_IS_AGP) {
3133 r600_agp_enable(rdev);
3134 } else {
3135 r = r600_pcie_gart_enable(rdev);
3136 if (r)
3137 return r;
3138 }
3139 r600_gpu_init(rdev);
3140
3141 /* allocate wb buffer */
3142 r = radeon_wb_init(rdev);
3143 if (r)
3144 return r;
3145
3146 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3147 if (r) {
3148 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3149 return r;
3150 }
3151
3152 r600_uvd_start(rdev);
3153
3154 /* Enable IRQ */
3155 if (!rdev->irq.installed) {
3156 r = radeon_irq_kms_init(rdev);
3157 if (r)
3158 return r;
3159 }
3160
3161 r = r600_irq_init(rdev);
3162 if (r) {
3163 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3164 radeon_irq_kms_fini(rdev);
3165 return r;
3166 }
3167 r600_irq_set(rdev);
3168
3169 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3170 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3171 RADEON_CP_PACKET2);
3172 if (r)
3173 return r;
3174
3175 r = r600_cp_load_microcode(rdev);
3176 if (r)
3177 return r;
3178 r = r600_cp_resume(rdev);
3179 if (r)
3180 return r;
3181
3182 r600_uvd_resume(rdev);
3183
3184 r = radeon_ib_pool_init(rdev);
3185 if (r) {
3186 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3187 return r;
3188 }
3189
3190 r = radeon_audio_init(rdev);
3191 if (r) {
3192 DRM_ERROR("radeon: audio init failed\n");
3193 return r;
3194 }
3195
3196 return 0;
3197 }
3198
r600_vga_set_state(struct radeon_device * rdev,bool state)3199 void r600_vga_set_state(struct radeon_device *rdev, bool state)
3200 {
3201 uint32_t temp;
3202
3203 temp = RREG32(CONFIG_CNTL);
3204 if (state == false) {
3205 temp &= ~(1<<0);
3206 temp |= (1<<1);
3207 } else {
3208 temp &= ~(1<<1);
3209 }
3210 WREG32(CONFIG_CNTL, temp);
3211 }
3212
r600_resume(struct radeon_device * rdev)3213 int r600_resume(struct radeon_device *rdev)
3214 {
3215 int r;
3216
3217 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
3218 * posting will perform necessary task to bring back GPU into good
3219 * shape.
3220 */
3221 /* post card */
3222 atom_asic_init(rdev->mode_info.atom_context);
3223
3224 if (rdev->pm.pm_method == PM_METHOD_DPM)
3225 radeon_pm_resume(rdev);
3226
3227 rdev->accel_working = true;
3228 r = r600_startup(rdev);
3229 if (r) {
3230 DRM_ERROR("r600 startup failed on resume\n");
3231 rdev->accel_working = false;
3232 return r;
3233 }
3234
3235 return r;
3236 }
3237
r600_suspend(struct radeon_device * rdev)3238 int r600_suspend(struct radeon_device *rdev)
3239 {
3240 radeon_pm_suspend(rdev);
3241 radeon_audio_fini(rdev);
3242 r600_cp_stop(rdev);
3243 if (rdev->has_uvd) {
3244 uvd_v1_0_fini(rdev);
3245 radeon_uvd_suspend(rdev);
3246 }
3247 r600_irq_suspend(rdev);
3248 radeon_wb_disable(rdev);
3249 r600_pcie_gart_disable(rdev);
3250
3251 return 0;
3252 }
3253
3254 /* Plan is to move initialization in that function and use
3255 * helper function so that radeon_device_init pretty much
3256 * do nothing more than calling asic specific function. This
3257 * should also allow to remove a bunch of callback function
3258 * like vram_info.
3259 */
r600_init(struct radeon_device * rdev)3260 int r600_init(struct radeon_device *rdev)
3261 {
3262 int r;
3263
3264 if (r600_debugfs_mc_info_init(rdev)) {
3265 DRM_ERROR("Failed to register debugfs file for mc !\n");
3266 }
3267 /* Read BIOS */
3268 if (!radeon_get_bios(rdev)) {
3269 if (ASIC_IS_AVIVO(rdev))
3270 return -EINVAL;
3271 }
3272 /* Must be an ATOMBIOS */
3273 if (!rdev->is_atom_bios) {
3274 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3275 return -EINVAL;
3276 }
3277 r = radeon_atombios_init(rdev);
3278 if (r)
3279 return r;
3280 /* Post card if necessary */
3281 if (!radeon_card_posted(rdev)) {
3282 if (!rdev->bios) {
3283 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3284 return -EINVAL;
3285 }
3286 DRM_INFO("GPU not posted. posting now...\n");
3287 atom_asic_init(rdev->mode_info.atom_context);
3288 }
3289 /* Initialize scratch registers */
3290 r600_scratch_init(rdev);
3291 /* Initialize surface registers */
3292 radeon_surface_init(rdev);
3293 /* Initialize clocks */
3294 radeon_get_clock_info(rdev->ddev);
3295 /* Fence driver */
3296 r = radeon_fence_driver_init(rdev);
3297 if (r)
3298 return r;
3299 if (rdev->flags & RADEON_IS_AGP) {
3300 r = radeon_agp_init(rdev);
3301 if (r)
3302 radeon_agp_disable(rdev);
3303 }
3304 r = r600_mc_init(rdev);
3305 if (r)
3306 return r;
3307 /* Memory manager */
3308 r = radeon_bo_init(rdev);
3309 if (r)
3310 return r;
3311
3312 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3313 r = r600_init_microcode(rdev);
3314 if (r) {
3315 DRM_ERROR("Failed to load firmware!\n");
3316 return r;
3317 }
3318 }
3319
3320 /* Initialize power management */
3321 radeon_pm_init(rdev);
3322
3323 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3324 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3325
3326 r600_uvd_init(rdev);
3327
3328 rdev->ih.ring_obj = NULL;
3329 r600_ih_ring_init(rdev, 64 * 1024);
3330
3331 r = r600_pcie_gart_init(rdev);
3332 if (r)
3333 return r;
3334
3335 rdev->accel_working = true;
3336 r = r600_startup(rdev);
3337 if (r) {
3338 dev_err(rdev->dev, "disabling GPU acceleration\n");
3339 r600_cp_fini(rdev);
3340 r600_irq_fini(rdev);
3341 radeon_wb_fini(rdev);
3342 radeon_ib_pool_fini(rdev);
3343 radeon_irq_kms_fini(rdev);
3344 r600_pcie_gart_fini(rdev);
3345 rdev->accel_working = false;
3346 }
3347
3348 return 0;
3349 }
3350
r600_fini(struct radeon_device * rdev)3351 void r600_fini(struct radeon_device *rdev)
3352 {
3353 radeon_pm_fini(rdev);
3354 radeon_audio_fini(rdev);
3355 r600_cp_fini(rdev);
3356 r600_irq_fini(rdev);
3357 if (rdev->has_uvd) {
3358 uvd_v1_0_fini(rdev);
3359 radeon_uvd_fini(rdev);
3360 }
3361 radeon_wb_fini(rdev);
3362 radeon_ib_pool_fini(rdev);
3363 radeon_irq_kms_fini(rdev);
3364 r600_pcie_gart_fini(rdev);
3365 r600_vram_scratch_fini(rdev);
3366 radeon_agp_fini(rdev);
3367 radeon_gem_fini(rdev);
3368 radeon_fence_driver_fini(rdev);
3369 radeon_bo_fini(rdev);
3370 radeon_atombios_fini(rdev);
3371 r600_fini_microcode(rdev);
3372 kfree(rdev->bios);
3373 rdev->bios = NULL;
3374 }
3375
3376
3377 /*
3378 * CS stuff
3379 */
r600_ring_ib_execute(struct radeon_device * rdev,struct radeon_ib * ib)3380 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3381 {
3382 struct radeon_ring *ring = &rdev->ring[ib->ring];
3383 u32 next_rptr;
3384
3385 if (ring->rptr_save_reg) {
3386 next_rptr = ring->wptr + 3 + 4;
3387 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3388 radeon_ring_write(ring, ((ring->rptr_save_reg -
3389 PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3390 radeon_ring_write(ring, next_rptr);
3391 } else if (rdev->wb.enabled) {
3392 next_rptr = ring->wptr + 5 + 4;
3393 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3394 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3395 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3396 radeon_ring_write(ring, next_rptr);
3397 radeon_ring_write(ring, 0);
3398 }
3399
3400 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3401 radeon_ring_write(ring,
3402 #ifdef __BIG_ENDIAN
3403 (2 << 0) |
3404 #endif
3405 (ib->gpu_addr & 0xFFFFFFFC));
3406 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3407 radeon_ring_write(ring, ib->length_dw);
3408 }
3409
r600_ib_test(struct radeon_device * rdev,struct radeon_ring * ring)3410 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3411 {
3412 struct radeon_ib ib;
3413 uint32_t scratch;
3414 uint32_t tmp = 0;
3415 unsigned i;
3416 int r;
3417
3418 r = radeon_scratch_get(rdev, &scratch);
3419 if (r) {
3420 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3421 return r;
3422 }
3423 WREG32(scratch, 0xCAFEDEAD);
3424 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3425 if (r) {
3426 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3427 goto free_scratch;
3428 }
3429 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3430 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3431 ib.ptr[2] = 0xDEADBEEF;
3432 ib.length_dw = 3;
3433 r = radeon_ib_schedule(rdev, &ib, NULL, false);
3434 if (r) {
3435 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3436 goto free_ib;
3437 }
3438 r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
3439 RADEON_USEC_IB_TEST_TIMEOUT));
3440 if (r < 0) {
3441 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3442 goto free_ib;
3443 } else if (r == 0) {
3444 DRM_ERROR("radeon: fence wait timed out.\n");
3445 r = -ETIMEDOUT;
3446 goto free_ib;
3447 }
3448 r = 0;
3449 for (i = 0; i < rdev->usec_timeout; i++) {
3450 tmp = RREG32(scratch);
3451 if (tmp == 0xDEADBEEF)
3452 break;
3453 DRM_UDELAY(1);
3454 }
3455 if (i < rdev->usec_timeout) {
3456 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3457 } else {
3458 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3459 scratch, tmp);
3460 r = -EINVAL;
3461 }
3462 free_ib:
3463 radeon_ib_free(rdev, &ib);
3464 free_scratch:
3465 radeon_scratch_free(rdev, scratch);
3466 return r;
3467 }
3468
3469 /*
3470 * Interrupts
3471 *
3472 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
3473 * the same as the CP ring buffer, but in reverse. Rather than the CPU
3474 * writing to the ring and the GPU consuming, the GPU writes to the ring
3475 * and host consumes. As the host irq handler processes interrupts, it
3476 * increments the rptr. When the rptr catches up with the wptr, all the
3477 * current interrupts have been processed.
3478 */
3479
r600_ih_ring_init(struct radeon_device * rdev,unsigned ring_size)3480 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3481 {
3482 u32 rb_bufsz;
3483
3484 /* Align ring size */
3485 rb_bufsz = order_base_2(ring_size / 4);
3486 ring_size = (1 << rb_bufsz) * 4;
3487 rdev->ih.ring_size = ring_size;
3488 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3489 rdev->ih.rptr = 0;
3490 }
3491
r600_ih_ring_alloc(struct radeon_device * rdev)3492 int r600_ih_ring_alloc(struct radeon_device *rdev)
3493 {
3494 int r;
3495
3496 /* Allocate ring buffer */
3497 if (rdev->ih.ring_obj == NULL) {
3498 r = radeon_bo_create(rdev, rdev->ih.ring_size,
3499 PAGE_SIZE, true,
3500 RADEON_GEM_DOMAIN_GTT, 0,
3501 NULL, NULL, &rdev->ih.ring_obj);
3502 if (r) {
3503 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3504 return r;
3505 }
3506 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3507 if (unlikely(r != 0))
3508 return r;
3509 r = radeon_bo_pin(rdev->ih.ring_obj,
3510 RADEON_GEM_DOMAIN_GTT,
3511 (u64 *)&rdev->ih.gpu_addr);
3512 if (r) {
3513 radeon_bo_unreserve(rdev->ih.ring_obj);
3514 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3515 return r;
3516 }
3517 r = radeon_bo_kmap(rdev->ih.ring_obj,
3518 (void **)&rdev->ih.ring);
3519 radeon_bo_unreserve(rdev->ih.ring_obj);
3520 if (r) {
3521 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3522 return r;
3523 }
3524 }
3525 return 0;
3526 }
3527
r600_ih_ring_fini(struct radeon_device * rdev)3528 void r600_ih_ring_fini(struct radeon_device *rdev)
3529 {
3530 int r;
3531 if (rdev->ih.ring_obj) {
3532 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3533 if (likely(r == 0)) {
3534 radeon_bo_kunmap(rdev->ih.ring_obj);
3535 radeon_bo_unpin(rdev->ih.ring_obj);
3536 radeon_bo_unreserve(rdev->ih.ring_obj);
3537 }
3538 radeon_bo_unref(&rdev->ih.ring_obj);
3539 rdev->ih.ring = NULL;
3540 rdev->ih.ring_obj = NULL;
3541 }
3542 }
3543
r600_rlc_stop(struct radeon_device * rdev)3544 void r600_rlc_stop(struct radeon_device *rdev)
3545 {
3546
3547 if ((rdev->family >= CHIP_RV770) &&
3548 (rdev->family <= CHIP_RV740)) {
3549 /* r7xx asics need to soft reset RLC before halting */
3550 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3551 RREG32(SRBM_SOFT_RESET);
3552 mdelay(15);
3553 WREG32(SRBM_SOFT_RESET, 0);
3554 RREG32(SRBM_SOFT_RESET);
3555 }
3556
3557 WREG32(RLC_CNTL, 0);
3558 }
3559
r600_rlc_start(struct radeon_device * rdev)3560 static void r600_rlc_start(struct radeon_device *rdev)
3561 {
3562 WREG32(RLC_CNTL, RLC_ENABLE);
3563 }
3564
r600_rlc_resume(struct radeon_device * rdev)3565 static int r600_rlc_resume(struct radeon_device *rdev)
3566 {
3567 u32 i;
3568 const __be32 *fw_data;
3569
3570 if (!rdev->rlc_fw)
3571 return -EINVAL;
3572
3573 r600_rlc_stop(rdev);
3574
3575 WREG32(RLC_HB_CNTL, 0);
3576
3577 WREG32(RLC_HB_BASE, 0);
3578 WREG32(RLC_HB_RPTR, 0);
3579 WREG32(RLC_HB_WPTR, 0);
3580 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3581 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3582 WREG32(RLC_MC_CNTL, 0);
3583 WREG32(RLC_UCODE_CNTL, 0);
3584
3585 fw_data = (const __be32 *)rdev->rlc_fw->data;
3586 if (rdev->family >= CHIP_RV770) {
3587 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3588 WREG32(RLC_UCODE_ADDR, i);
3589 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3590 }
3591 } else {
3592 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) {
3593 WREG32(RLC_UCODE_ADDR, i);
3594 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3595 }
3596 }
3597 WREG32(RLC_UCODE_ADDR, 0);
3598
3599 r600_rlc_start(rdev);
3600
3601 return 0;
3602 }
3603
r600_enable_interrupts(struct radeon_device * rdev)3604 static void r600_enable_interrupts(struct radeon_device *rdev)
3605 {
3606 u32 ih_cntl = RREG32(IH_CNTL);
3607 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3608
3609 ih_cntl |= ENABLE_INTR;
3610 ih_rb_cntl |= IH_RB_ENABLE;
3611 WREG32(IH_CNTL, ih_cntl);
3612 WREG32(IH_RB_CNTL, ih_rb_cntl);
3613 rdev->ih.enabled = true;
3614 }
3615
r600_disable_interrupts(struct radeon_device * rdev)3616 void r600_disable_interrupts(struct radeon_device *rdev)
3617 {
3618 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3619 u32 ih_cntl = RREG32(IH_CNTL);
3620
3621 ih_rb_cntl &= ~IH_RB_ENABLE;
3622 ih_cntl &= ~ENABLE_INTR;
3623 WREG32(IH_RB_CNTL, ih_rb_cntl);
3624 WREG32(IH_CNTL, ih_cntl);
3625 /* set rptr, wptr to 0 */
3626 WREG32(IH_RB_RPTR, 0);
3627 WREG32(IH_RB_WPTR, 0);
3628 rdev->ih.enabled = false;
3629 rdev->ih.rptr = 0;
3630 }
3631
r600_disable_interrupt_state(struct radeon_device * rdev)3632 static void r600_disable_interrupt_state(struct radeon_device *rdev)
3633 {
3634 u32 tmp;
3635
3636 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3637 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3638 WREG32(DMA_CNTL, tmp);
3639 WREG32(GRBM_INT_CNTL, 0);
3640 WREG32(DxMODE_INT_MASK, 0);
3641 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3642 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
3643 if (ASIC_IS_DCE3(rdev)) {
3644 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3645 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3646 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3647 WREG32(DC_HPD1_INT_CONTROL, tmp);
3648 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3649 WREG32(DC_HPD2_INT_CONTROL, tmp);
3650 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3651 WREG32(DC_HPD3_INT_CONTROL, tmp);
3652 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3653 WREG32(DC_HPD4_INT_CONTROL, tmp);
3654 if (ASIC_IS_DCE32(rdev)) {
3655 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3656 WREG32(DC_HPD5_INT_CONTROL, tmp);
3657 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3658 WREG32(DC_HPD6_INT_CONTROL, tmp);
3659 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3660 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3661 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3662 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3663 } else {
3664 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3665 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3666 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3667 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3668 }
3669 } else {
3670 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3671 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3672 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3673 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3674 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3675 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3676 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3677 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3678 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3679 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3680 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3681 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3682 }
3683 }
3684
r600_irq_init(struct radeon_device * rdev)3685 int r600_irq_init(struct radeon_device *rdev)
3686 {
3687 int ret = 0;
3688 int rb_bufsz;
3689 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3690
3691 /* allocate ring */
3692 ret = r600_ih_ring_alloc(rdev);
3693 if (ret)
3694 return ret;
3695
3696 /* disable irqs */
3697 r600_disable_interrupts(rdev);
3698
3699 /* init rlc */
3700 if (rdev->family >= CHIP_CEDAR)
3701 ret = evergreen_rlc_resume(rdev);
3702 else
3703 ret = r600_rlc_resume(rdev);
3704 if (ret) {
3705 r600_ih_ring_fini(rdev);
3706 return ret;
3707 }
3708
3709 /* setup interrupt control */
3710 /* set dummy read address to ring address */
3711 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3712 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3713 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3714 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3715 */
3716 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3717 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3718 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3719 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3720
3721 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3722 rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
3723
3724 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3725 IH_WPTR_OVERFLOW_CLEAR |
3726 (rb_bufsz << 1));
3727
3728 if (rdev->wb.enabled)
3729 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3730
3731 /* set the writeback address whether it's enabled or not */
3732 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3733 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3734
3735 WREG32(IH_RB_CNTL, ih_rb_cntl);
3736
3737 /* set rptr, wptr to 0 */
3738 WREG32(IH_RB_RPTR, 0);
3739 WREG32(IH_RB_WPTR, 0);
3740
3741 /* Default settings for IH_CNTL (disabled at first) */
3742 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3743 /* RPTR_REARM only works if msi's are enabled */
3744 if (rdev->msi_enabled)
3745 ih_cntl |= RPTR_REARM;
3746 WREG32(IH_CNTL, ih_cntl);
3747
3748 /* force the active interrupt state to all disabled */
3749 if (rdev->family >= CHIP_CEDAR)
3750 evergreen_disable_interrupt_state(rdev);
3751 else
3752 r600_disable_interrupt_state(rdev);
3753
3754 /* at this point everything should be setup correctly to enable master */
3755 pci_set_master(rdev->pdev);
3756
3757 /* enable irqs */
3758 r600_enable_interrupts(rdev);
3759
3760 return ret;
3761 }
3762
r600_irq_suspend(struct radeon_device * rdev)3763 void r600_irq_suspend(struct radeon_device *rdev)
3764 {
3765 r600_irq_disable(rdev);
3766 r600_rlc_stop(rdev);
3767 }
3768
r600_irq_fini(struct radeon_device * rdev)3769 void r600_irq_fini(struct radeon_device *rdev)
3770 {
3771 r600_irq_suspend(rdev);
3772 r600_ih_ring_fini(rdev);
3773 }
3774
r600_irq_set(struct radeon_device * rdev)3775 int r600_irq_set(struct radeon_device *rdev)
3776 {
3777 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3778 u32 mode_int = 0;
3779 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3780 u32 grbm_int_cntl = 0;
3781 u32 hdmi0, hdmi1;
3782 u32 dma_cntl;
3783 u32 thermal_int = 0;
3784
3785 if (!rdev->irq.installed) {
3786 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3787 return -EINVAL;
3788 }
3789 /* don't enable anything if the ih is disabled */
3790 if (!rdev->ih.enabled) {
3791 r600_disable_interrupts(rdev);
3792 /* force the active interrupt state to all disabled */
3793 r600_disable_interrupt_state(rdev);
3794 return 0;
3795 }
3796
3797 if (ASIC_IS_DCE3(rdev)) {
3798 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3799 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3800 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3801 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3802 if (ASIC_IS_DCE32(rdev)) {
3803 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3804 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3805 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3806 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3807 } else {
3808 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3809 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3810 }
3811 } else {
3812 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3813 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3814 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3815 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3816 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3817 }
3818
3819 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3820
3821 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3822 thermal_int = RREG32(CG_THERMAL_INT) &
3823 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
3824 } else if (rdev->family >= CHIP_RV770) {
3825 thermal_int = RREG32(RV770_CG_THERMAL_INT) &
3826 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
3827 }
3828 if (rdev->irq.dpm_thermal) {
3829 DRM_DEBUG("dpm thermal\n");
3830 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
3831 }
3832
3833 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
3834 DRM_DEBUG("r600_irq_set: sw int\n");
3835 cp_int_cntl |= RB_INT_ENABLE;
3836 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3837 }
3838
3839 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3840 DRM_DEBUG("r600_irq_set: sw int dma\n");
3841 dma_cntl |= TRAP_ENABLE;
3842 }
3843
3844 if (rdev->irq.crtc_vblank_int[0] ||
3845 atomic_read(&rdev->irq.pflip[0])) {
3846 DRM_DEBUG("r600_irq_set: vblank 0\n");
3847 mode_int |= D1MODE_VBLANK_INT_MASK;
3848 }
3849 if (rdev->irq.crtc_vblank_int[1] ||
3850 atomic_read(&rdev->irq.pflip[1])) {
3851 DRM_DEBUG("r600_irq_set: vblank 1\n");
3852 mode_int |= D2MODE_VBLANK_INT_MASK;
3853 }
3854 if (rdev->irq.hpd[0]) {
3855 DRM_DEBUG("r600_irq_set: hpd 1\n");
3856 hpd1 |= DC_HPDx_INT_EN;
3857 }
3858 if (rdev->irq.hpd[1]) {
3859 DRM_DEBUG("r600_irq_set: hpd 2\n");
3860 hpd2 |= DC_HPDx_INT_EN;
3861 }
3862 if (rdev->irq.hpd[2]) {
3863 DRM_DEBUG("r600_irq_set: hpd 3\n");
3864 hpd3 |= DC_HPDx_INT_EN;
3865 }
3866 if (rdev->irq.hpd[3]) {
3867 DRM_DEBUG("r600_irq_set: hpd 4\n");
3868 hpd4 |= DC_HPDx_INT_EN;
3869 }
3870 if (rdev->irq.hpd[4]) {
3871 DRM_DEBUG("r600_irq_set: hpd 5\n");
3872 hpd5 |= DC_HPDx_INT_EN;
3873 }
3874 if (rdev->irq.hpd[5]) {
3875 DRM_DEBUG("r600_irq_set: hpd 6\n");
3876 hpd6 |= DC_HPDx_INT_EN;
3877 }
3878 if (rdev->irq.afmt[0]) {
3879 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3880 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3881 }
3882 if (rdev->irq.afmt[1]) {
3883 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3884 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3885 }
3886
3887 WREG32(CP_INT_CNTL, cp_int_cntl);
3888 WREG32(DMA_CNTL, dma_cntl);
3889 WREG32(DxMODE_INT_MASK, mode_int);
3890 WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3891 WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3892 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3893 if (ASIC_IS_DCE3(rdev)) {
3894 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3895 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3896 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3897 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3898 if (ASIC_IS_DCE32(rdev)) {
3899 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3900 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3901 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3902 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
3903 } else {
3904 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3905 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3906 }
3907 } else {
3908 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3909 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3910 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3911 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3912 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3913 }
3914 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3915 WREG32(CG_THERMAL_INT, thermal_int);
3916 } else if (rdev->family >= CHIP_RV770) {
3917 WREG32(RV770_CG_THERMAL_INT, thermal_int);
3918 }
3919
3920 /* posting read */
3921 RREG32(R_000E50_SRBM_STATUS);
3922
3923 return 0;
3924 }
3925
r600_irq_ack(struct radeon_device * rdev)3926 static void r600_irq_ack(struct radeon_device *rdev)
3927 {
3928 u32 tmp;
3929
3930 if (ASIC_IS_DCE3(rdev)) {
3931 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3932 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3933 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3934 if (ASIC_IS_DCE32(rdev)) {
3935 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3936 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
3937 } else {
3938 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3939 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3940 }
3941 } else {
3942 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3943 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3944 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3945 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3946 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
3947 }
3948 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3949 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3950
3951 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3952 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3953 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3954 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3955 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3956 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3957 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3958 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3959 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3960 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3961 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3962 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3963 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3964 if (ASIC_IS_DCE3(rdev)) {
3965 tmp = RREG32(DC_HPD1_INT_CONTROL);
3966 tmp |= DC_HPDx_INT_ACK;
3967 WREG32(DC_HPD1_INT_CONTROL, tmp);
3968 } else {
3969 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3970 tmp |= DC_HPDx_INT_ACK;
3971 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3972 }
3973 }
3974 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3975 if (ASIC_IS_DCE3(rdev)) {
3976 tmp = RREG32(DC_HPD2_INT_CONTROL);
3977 tmp |= DC_HPDx_INT_ACK;
3978 WREG32(DC_HPD2_INT_CONTROL, tmp);
3979 } else {
3980 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3981 tmp |= DC_HPDx_INT_ACK;
3982 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3983 }
3984 }
3985 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3986 if (ASIC_IS_DCE3(rdev)) {
3987 tmp = RREG32(DC_HPD3_INT_CONTROL);
3988 tmp |= DC_HPDx_INT_ACK;
3989 WREG32(DC_HPD3_INT_CONTROL, tmp);
3990 } else {
3991 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3992 tmp |= DC_HPDx_INT_ACK;
3993 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3994 }
3995 }
3996 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3997 tmp = RREG32(DC_HPD4_INT_CONTROL);
3998 tmp |= DC_HPDx_INT_ACK;
3999 WREG32(DC_HPD4_INT_CONTROL, tmp);
4000 }
4001 if (ASIC_IS_DCE32(rdev)) {
4002 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
4003 tmp = RREG32(DC_HPD5_INT_CONTROL);
4004 tmp |= DC_HPDx_INT_ACK;
4005 WREG32(DC_HPD5_INT_CONTROL, tmp);
4006 }
4007 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
4008 tmp = RREG32(DC_HPD6_INT_CONTROL);
4009 tmp |= DC_HPDx_INT_ACK;
4010 WREG32(DC_HPD6_INT_CONTROL, tmp);
4011 }
4012 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
4013 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
4014 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
4015 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
4016 }
4017 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
4018 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
4019 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
4020 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
4021 }
4022 } else {
4023 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
4024 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
4025 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
4026 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
4027 }
4028 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
4029 if (ASIC_IS_DCE3(rdev)) {
4030 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
4031 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
4032 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
4033 } else {
4034 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
4035 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
4036 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
4037 }
4038 }
4039 }
4040 }
4041
r600_irq_disable(struct radeon_device * rdev)4042 void r600_irq_disable(struct radeon_device *rdev)
4043 {
4044 r600_disable_interrupts(rdev);
4045 /* Wait and acknowledge irq */
4046 mdelay(1);
4047 r600_irq_ack(rdev);
4048 r600_disable_interrupt_state(rdev);
4049 }
4050
r600_get_ih_wptr(struct radeon_device * rdev)4051 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
4052 {
4053 u32 wptr, tmp;
4054
4055 if (rdev->wb.enabled)
4056 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
4057 else
4058 wptr = RREG32(IH_RB_WPTR);
4059
4060 if (wptr & RB_OVERFLOW) {
4061 wptr &= ~RB_OVERFLOW;
4062 /* When a ring buffer overflow happen start parsing interrupt
4063 * from the last not overwritten vector (wptr + 16). Hopefully
4064 * this should allow us to catchup.
4065 */
4066 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
4067 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
4068 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
4069 tmp = RREG32(IH_RB_CNTL);
4070 tmp |= IH_WPTR_OVERFLOW_CLEAR;
4071 WREG32(IH_RB_CNTL, tmp);
4072 }
4073 return (wptr & rdev->ih.ptr_mask);
4074 }
4075
4076 /* r600 IV Ring
4077 * Each IV ring entry is 128 bits:
4078 * [7:0] - interrupt source id
4079 * [31:8] - reserved
4080 * [59:32] - interrupt source data
4081 * [127:60] - reserved
4082 *
4083 * The basic interrupt vector entries
4084 * are decoded as follows:
4085 * src_id src_data description
4086 * 1 0 D1 Vblank
4087 * 1 1 D1 Vline
4088 * 5 0 D2 Vblank
4089 * 5 1 D2 Vline
4090 * 19 0 FP Hot plug detection A
4091 * 19 1 FP Hot plug detection B
4092 * 19 2 DAC A auto-detection
4093 * 19 3 DAC B auto-detection
4094 * 21 4 HDMI block A
4095 * 21 5 HDMI block B
4096 * 176 - CP_INT RB
4097 * 177 - CP_INT IB1
4098 * 178 - CP_INT IB2
4099 * 181 - EOP Interrupt
4100 * 233 - GUI Idle
4101 *
4102 * Note, these are based on r600 and may need to be
4103 * adjusted or added to on newer asics
4104 */
4105
r600_irq_process(struct radeon_device * rdev)4106 irqreturn_t r600_irq_process(struct radeon_device *rdev)
4107 {
4108 u32 wptr;
4109 u32 rptr;
4110 u32 src_id, src_data;
4111 u32 ring_index;
4112 bool queue_hotplug = false;
4113 bool queue_hdmi = false;
4114 bool queue_thermal = false;
4115
4116 if (!rdev->ih.enabled || rdev->shutdown)
4117 return IRQ_NONE;
4118
4119 /* No MSIs, need a dummy read to flush PCI DMAs */
4120 if (!rdev->msi_enabled)
4121 RREG32(IH_RB_WPTR);
4122
4123 wptr = r600_get_ih_wptr(rdev);
4124
4125 restart_ih:
4126 /* is somebody else already processing irqs? */
4127 if (atomic_xchg(&rdev->ih.lock, 1))
4128 return IRQ_NONE;
4129
4130 rptr = rdev->ih.rptr;
4131 DRM_DEBUG_VBLANK("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
4132
4133 /* Order reading of wptr vs. reading of IH ring data */
4134 rmb();
4135
4136 /* display interrupts */
4137 r600_irq_ack(rdev);
4138
4139 while (rptr != wptr) {
4140 /* wptr/rptr are in bytes! */
4141 ring_index = rptr / 4;
4142 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
4143 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
4144
4145 switch (src_id) {
4146 case 1: /* D1 vblank/vline */
4147 switch (src_data) {
4148 case 0: /* D1 vblank */
4149 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT))
4150 DRM_DEBUG("IH: D1 vblank - IH event w/o asserted irq bit?\n");
4151
4152 if (rdev->irq.crtc_vblank_int[0]) {
4153 drm_handle_vblank(rdev->ddev, 0);
4154 rdev->pm.vblank_sync = true;
4155 wake_up(&rdev->irq.vblank_queue);
4156 }
4157 if (atomic_read(&rdev->irq.pflip[0]))
4158 radeon_crtc_handle_vblank(rdev, 0);
4159 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
4160 DRM_DEBUG_VBLANK("IH: D1 vblank\n");
4161
4162 break;
4163 case 1: /* D1 vline */
4164 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT))
4165 DRM_DEBUG("IH: D1 vline - IH event w/o asserted irq bit?\n");
4166
4167 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
4168 DRM_DEBUG_VBLANK("IH: D1 vline\n");
4169
4170 break;
4171 default:
4172 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4173 break;
4174 }
4175 break;
4176 case 5: /* D2 vblank/vline */
4177 switch (src_data) {
4178 case 0: /* D2 vblank */
4179 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT))
4180 DRM_DEBUG("IH: D2 vblank - IH event w/o asserted irq bit?\n");
4181
4182 if (rdev->irq.crtc_vblank_int[1]) {
4183 drm_handle_vblank(rdev->ddev, 1);
4184 rdev->pm.vblank_sync = true;
4185 wake_up(&rdev->irq.vblank_queue);
4186 }
4187 if (atomic_read(&rdev->irq.pflip[1]))
4188 radeon_crtc_handle_vblank(rdev, 1);
4189 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
4190 DRM_DEBUG_VBLANK("IH: D2 vblank\n");
4191
4192 break;
4193 case 1: /* D1 vline */
4194 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT))
4195 DRM_DEBUG("IH: D2 vline - IH event w/o asserted irq bit?\n");
4196
4197 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
4198 DRM_DEBUG_VBLANK("IH: D2 vline\n");
4199
4200 break;
4201 default:
4202 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4203 break;
4204 }
4205 break;
4206 case 9: /* D1 pflip */
4207 DRM_DEBUG_VBLANK("IH: D1 flip\n");
4208 if (radeon_use_pflipirq > 0)
4209 radeon_crtc_handle_flip(rdev, 0);
4210 break;
4211 case 11: /* D2 pflip */
4212 DRM_DEBUG_VBLANK("IH: D2 flip\n");
4213 if (radeon_use_pflipirq > 0)
4214 radeon_crtc_handle_flip(rdev, 1);
4215 break;
4216 case 19: /* HPD/DAC hotplug */
4217 switch (src_data) {
4218 case 0:
4219 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT))
4220 DRM_DEBUG("IH: HPD1 - IH event w/o asserted irq bit?\n");
4221
4222 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
4223 queue_hotplug = true;
4224 DRM_DEBUG("IH: HPD1\n");
4225 break;
4226 case 1:
4227 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT))
4228 DRM_DEBUG("IH: HPD2 - IH event w/o asserted irq bit?\n");
4229
4230 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
4231 queue_hotplug = true;
4232 DRM_DEBUG("IH: HPD2\n");
4233 break;
4234 case 4:
4235 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT))
4236 DRM_DEBUG("IH: HPD3 - IH event w/o asserted irq bit?\n");
4237
4238 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
4239 queue_hotplug = true;
4240 DRM_DEBUG("IH: HPD3\n");
4241 break;
4242 case 5:
4243 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT))
4244 DRM_DEBUG("IH: HPD4 - IH event w/o asserted irq bit?\n");
4245
4246 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
4247 queue_hotplug = true;
4248 DRM_DEBUG("IH: HPD4\n");
4249 break;
4250 case 10:
4251 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT))
4252 DRM_DEBUG("IH: HPD5 - IH event w/o asserted irq bit?\n");
4253
4254 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
4255 queue_hotplug = true;
4256 DRM_DEBUG("IH: HPD5\n");
4257 break;
4258 case 12:
4259 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT))
4260 DRM_DEBUG("IH: HPD6 - IH event w/o asserted irq bit?\n");
4261
4262 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
4263 queue_hotplug = true;
4264 DRM_DEBUG("IH: HPD6\n");
4265
4266 break;
4267 default:
4268 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4269 break;
4270 }
4271 break;
4272 case 21: /* hdmi */
4273 switch (src_data) {
4274 case 4:
4275 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG))
4276 DRM_DEBUG("IH: HDMI0 - IH event w/o asserted irq bit?\n");
4277
4278 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4279 queue_hdmi = true;
4280 DRM_DEBUG("IH: HDMI0\n");
4281
4282 break;
4283 case 5:
4284 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG))
4285 DRM_DEBUG("IH: HDMI1 - IH event w/o asserted irq bit?\n");
4286
4287 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4288 queue_hdmi = true;
4289 DRM_DEBUG("IH: HDMI1\n");
4290
4291 break;
4292 default:
4293 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
4294 break;
4295 }
4296 break;
4297 case 124: /* UVD */
4298 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
4299 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
4300 break;
4301 case 176: /* CP_INT in ring buffer */
4302 case 177: /* CP_INT in IB1 */
4303 case 178: /* CP_INT in IB2 */
4304 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
4305 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4306 break;
4307 case 181: /* CP EOP event */
4308 DRM_DEBUG("IH: CP EOP\n");
4309 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4310 break;
4311 case 224: /* DMA trap event */
4312 DRM_DEBUG("IH: DMA trap\n");
4313 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4314 break;
4315 case 230: /* thermal low to high */
4316 DRM_DEBUG("IH: thermal low to high\n");
4317 rdev->pm.dpm.thermal.high_to_low = false;
4318 queue_thermal = true;
4319 break;
4320 case 231: /* thermal high to low */
4321 DRM_DEBUG("IH: thermal high to low\n");
4322 rdev->pm.dpm.thermal.high_to_low = true;
4323 queue_thermal = true;
4324 break;
4325 case 233: /* GUI IDLE */
4326 DRM_DEBUG("IH: GUI idle\n");
4327 break;
4328 default:
4329 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4330 break;
4331 }
4332
4333 /* wptr/rptr are in bytes! */
4334 rptr += 16;
4335 rptr &= rdev->ih.ptr_mask;
4336 WREG32(IH_RB_RPTR, rptr);
4337 }
4338 if (queue_hotplug)
4339 schedule_delayed_work(&rdev->hotplug_work, 0);
4340 if (queue_hdmi)
4341 schedule_work(&rdev->audio_work);
4342 if (queue_thermal && rdev->pm.dpm_enabled)
4343 schedule_work(&rdev->pm.dpm.thermal.work);
4344 rdev->ih.rptr = rptr;
4345 atomic_set(&rdev->ih.lock, 0);
4346
4347 /* make sure wptr hasn't changed while processing */
4348 wptr = r600_get_ih_wptr(rdev);
4349 if (wptr != rptr)
4350 goto restart_ih;
4351
4352 return IRQ_HANDLED;
4353 }
4354
4355 /*
4356 * Debugfs info
4357 */
4358 #if defined(CONFIG_DEBUG_FS)
4359
r600_debugfs_mc_info(struct seq_file * m,void * data)4360 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
4361 {
4362 struct drm_info_node *node = (struct drm_info_node *) m->private;
4363 struct drm_device *dev = node->minor->dev;
4364 struct radeon_device *rdev = dev->dev_private;
4365
4366 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
4367 DREG32_SYS(m, rdev, VM_L2_STATUS);
4368 return 0;
4369 }
4370
4371 static struct drm_info_list r600_mc_info_list[] = {
4372 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
4373 };
4374 #endif
4375
r600_debugfs_mc_info_init(struct radeon_device * rdev)4376 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
4377 {
4378 #if defined(CONFIG_DEBUG_FS)
4379 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
4380 #else
4381 return 0;
4382 #endif
4383 }
4384
4385 /**
4386 * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO
4387 * rdev: radeon device structure
4388 *
4389 * Some R6XX/R7XX don't seem to take into account HDP flushes performed
4390 * through the ring buffer. This leads to corruption in rendering, see
4391 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 . To avoid this, we
4392 * directly perform the HDP flush by writing the register through MMIO.
4393 */
r600_mmio_hdp_flush(struct radeon_device * rdev)4394 void r600_mmio_hdp_flush(struct radeon_device *rdev)
4395 {
4396 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
4397 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4398 * This seems to cause problems on some AGP cards. Just use the old
4399 * method for them.
4400 */
4401 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
4402 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
4403 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
4404 u32 tmp;
4405
4406 WREG32(HDP_DEBUG1, 0);
4407 tmp = readl((void __iomem *)ptr);
4408 } else
4409 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4410 }
4411
r600_set_pcie_lanes(struct radeon_device * rdev,int lanes)4412 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4413 {
4414 u32 link_width_cntl, mask;
4415
4416 if (rdev->flags & RADEON_IS_IGP)
4417 return;
4418
4419 if (!(rdev->flags & RADEON_IS_PCIE))
4420 return;
4421
4422 /* x2 cards have a special sequence */
4423 if (ASIC_IS_X2(rdev))
4424 return;
4425
4426 radeon_gui_idle(rdev);
4427
4428 switch (lanes) {
4429 case 0:
4430 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4431 break;
4432 case 1:
4433 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4434 break;
4435 case 2:
4436 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4437 break;
4438 case 4:
4439 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4440 break;
4441 case 8:
4442 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4443 break;
4444 case 12:
4445 /* not actually supported */
4446 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4447 break;
4448 case 16:
4449 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4450 break;
4451 default:
4452 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
4453 return;
4454 }
4455
4456 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4457 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;
4458 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;
4459 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |
4460 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
4461
4462 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4463 }
4464
r600_get_pcie_lanes(struct radeon_device * rdev)4465 int r600_get_pcie_lanes(struct radeon_device *rdev)
4466 {
4467 u32 link_width_cntl;
4468
4469 if (rdev->flags & RADEON_IS_IGP)
4470 return 0;
4471
4472 if (!(rdev->flags & RADEON_IS_PCIE))
4473 return 0;
4474
4475 /* x2 cards have a special sequence */
4476 if (ASIC_IS_X2(rdev))
4477 return 0;
4478
4479 radeon_gui_idle(rdev);
4480
4481 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4482
4483 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4484 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4485 return 1;
4486 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4487 return 2;
4488 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4489 return 4;
4490 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4491 return 8;
4492 case RADEON_PCIE_LC_LINK_WIDTH_X12:
4493 /* not actually supported */
4494 return 12;
4495 case RADEON_PCIE_LC_LINK_WIDTH_X0:
4496 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4497 default:
4498 return 16;
4499 }
4500 }
4501
r600_pcie_gen2_enable(struct radeon_device * rdev)4502 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4503 {
4504 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4505 u16 link_cntl2;
4506 u32 mask;
4507
4508 if (radeon_pcie_gen2 == 0)
4509 return;
4510
4511 if (rdev->flags & RADEON_IS_IGP)
4512 return;
4513
4514 if (!(rdev->flags & RADEON_IS_PCIE))
4515 return;
4516
4517 /* x2 cards have a special sequence */
4518 if (ASIC_IS_X2(rdev))
4519 return;
4520
4521 /* only RV6xx+ chips are supported */
4522 if (rdev->family <= CHIP_R600)
4523 return;
4524
4525 #ifdef __DragonFly__
4526 if (drm_pcie_get_speed_cap_mask(rdev->ddev, &mask) != 0)
4527 return;
4528 rdev->pdev->bus->max_bus_speed = (mask & 0xff);
4529 #endif
4530
4531 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
4532 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
4533 return;
4534
4535 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4536 if (speed_cntl & LC_CURRENT_DATA_RATE) {
4537 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4538 return;
4539 }
4540
4541 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4542
4543 /* 55 nm r6xx asics */
4544 if ((rdev->family == CHIP_RV670) ||
4545 (rdev->family == CHIP_RV620) ||
4546 (rdev->family == CHIP_RV635)) {
4547 /* advertise upconfig capability */
4548 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4549 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4550 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4551 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4552 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4553 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4554 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4555 LC_RECONFIG_ARC_MISSING_ESCAPE);
4556 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4557 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4558 } else {
4559 link_width_cntl |= LC_UPCONFIGURE_DIS;
4560 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4561 }
4562 }
4563
4564 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4565 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4566 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4567
4568 /* 55 nm r6xx asics */
4569 if ((rdev->family == CHIP_RV670) ||
4570 (rdev->family == CHIP_RV620) ||
4571 (rdev->family == CHIP_RV635)) {
4572 WREG32(MM_CFGREGS_CNTL, 0x8);
4573 link_cntl2 = RREG32(0x4088);
4574 WREG32(MM_CFGREGS_CNTL, 0);
4575 /* not supported yet */
4576 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4577 return;
4578 }
4579
4580 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4581 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4582 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4583 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4584 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
4585 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4586
4587 tmp = RREG32(0x541c);
4588 WREG32(0x541c, tmp | 0x8);
4589 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4590 link_cntl2 = RREG16(0x4088);
4591 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4592 link_cntl2 |= 0x2;
4593 WREG16(0x4088, link_cntl2);
4594 WREG32(MM_CFGREGS_CNTL, 0);
4595
4596 if ((rdev->family == CHIP_RV670) ||
4597 (rdev->family == CHIP_RV620) ||
4598 (rdev->family == CHIP_RV635)) {
4599 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL);
4600 training_cntl &= ~LC_POINT_7_PLUS_EN;
4601 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl);
4602 } else {
4603 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4604 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
4605 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4606 }
4607
4608 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4609 speed_cntl |= LC_GEN2_EN_STRAP;
4610 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4611
4612 } else {
4613 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4614 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4615 if (1)
4616 link_width_cntl |= LC_UPCONFIGURE_DIS;
4617 else
4618 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4619 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4620 }
4621 }
4622
4623 /**
4624 * r600_get_gpu_clock_counter - return GPU clock counter snapshot
4625 *
4626 * @rdev: radeon_device pointer
4627 *
4628 * Fetches a GPU clock counter snapshot (R6xx-cayman).
4629 * Returns the 64 bit clock counter snapshot.
4630 */
r600_get_gpu_clock_counter(struct radeon_device * rdev)4631 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev)
4632 {
4633 uint64_t clock;
4634
4635 mutex_lock(&rdev->gpu_clock_mutex);
4636 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4637 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4638 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4639 mutex_unlock(&rdev->gpu_clock_mutex);
4640 return clock;
4641 }
4642