1 /*
2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
28
29 #include <dev/drm2/drmP.h>
30 #include <dev/drm2/radeon/radeon_drm.h>
31 #include "radeon.h"
32 #include "radeon_asic.h"
33
34 #include "r600d.h"
35 #include "r600_blit_shaders.h"
36 #include "radeon_blit_common.h"
37
38 /* 23 bits of float fractional data */
39 #define I2F_FRAC_BITS 23
40 #define I2F_MASK ((1 << I2F_FRAC_BITS) - 1)
41
42 /*
43 * Converts unsigned integer into 32-bit IEEE floating point representation.
44 * Will be exact from 0 to 2^24. Above that, we round towards zero
45 * as the fractional bits will not fit in a float. (It would be better to
46 * round towards even as the fpu does, but that is slower.)
47 *
48 * Moved from r600_blit.c after that file was removed.
49 */
int2float(uint32_t x)50 __pure uint32_t int2float(uint32_t x)
51 {
52 uint32_t msb, exponent, fraction;
53
54 /* Zero is special */
55 if (!x) return 0;
56
57 /* Get location of the most significant bit */
58 msb = fls(x);
59
60 /*
61 * Use a rotate instead of a shift because that works both leftwards
62 * and rightwards due to the mod(32) behaviour. This means we don't
63 * need to check to see if we are above 2^24 or not.
64 */
65 fraction = ror32(x, (msb - I2F_FRAC_BITS) & 0x1f) & I2F_MASK;
66 exponent = (127 + msb) << I2F_FRAC_BITS;
67
68 return fraction + exponent;
69 }
70
71 /* emits 21 on rv770+, 23 on r600 */
72 static void
set_render_target(struct radeon_device * rdev,int format,int w,int h,u64 gpu_addr)73 set_render_target(struct radeon_device *rdev, int format,
74 int w, int h, u64 gpu_addr)
75 {
76 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
77 u32 cb_color_info;
78 int pitch, slice;
79
80 h = roundup2(h, 8);
81 if (h < 8)
82 h = 8;
83
84 cb_color_info = CB_FORMAT(format) |
85 CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) |
86 CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
87 pitch = (w / 8) - 1;
88 slice = ((w * h) / 64) - 1;
89
90 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
91 radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
92 radeon_ring_write(ring, gpu_addr >> 8);
93
94 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
95 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
96 radeon_ring_write(ring, 2 << 0);
97 }
98
99 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
100 radeon_ring_write(ring, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
101 radeon_ring_write(ring, (pitch << 0) | (slice << 10));
102
103 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
104 radeon_ring_write(ring, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
105 radeon_ring_write(ring, 0);
106
107 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
108 radeon_ring_write(ring, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
109 radeon_ring_write(ring, cb_color_info);
110
111 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
112 radeon_ring_write(ring, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
113 radeon_ring_write(ring, 0);
114
115 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
116 radeon_ring_write(ring, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
117 radeon_ring_write(ring, 0);
118
119 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
120 radeon_ring_write(ring, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
121 radeon_ring_write(ring, 0);
122 }
123
124 /* emits 5dw */
125 static void
cp_set_surface_sync(struct radeon_device * rdev,u32 sync_type,u32 size,u64 mc_addr)126 cp_set_surface_sync(struct radeon_device *rdev,
127 u32 sync_type, u32 size,
128 u64 mc_addr)
129 {
130 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
131 u32 cp_coher_size;
132
133 if (size == 0xffffffff)
134 cp_coher_size = 0xffffffff;
135 else
136 cp_coher_size = ((size + 255) >> 8);
137
138 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
139 radeon_ring_write(ring, sync_type);
140 radeon_ring_write(ring, cp_coher_size);
141 radeon_ring_write(ring, mc_addr >> 8);
142 radeon_ring_write(ring, 10); /* poll interval */
143 }
144
145 /* emits 21dw + 1 surface sync = 26dw */
146 static void
set_shaders(struct radeon_device * rdev)147 set_shaders(struct radeon_device *rdev)
148 {
149 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
150 u64 gpu_addr;
151 u32 sq_pgm_resources;
152
153 /* setup shader regs */
154 sq_pgm_resources = (1 << 0);
155
156 /* VS */
157 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
158 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
159 radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
160 radeon_ring_write(ring, gpu_addr >> 8);
161
162 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
163 radeon_ring_write(ring, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
164 radeon_ring_write(ring, sq_pgm_resources);
165
166 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
167 radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
168 radeon_ring_write(ring, 0);
169
170 /* PS */
171 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
172 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
173 radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
174 radeon_ring_write(ring, gpu_addr >> 8);
175
176 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
177 radeon_ring_write(ring, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
178 radeon_ring_write(ring, sq_pgm_resources | (1 << 28));
179
180 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
181 radeon_ring_write(ring, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
182 radeon_ring_write(ring, 2);
183
184 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
185 radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
186 radeon_ring_write(ring, 0);
187
188 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
189 cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
190 }
191
192 /* emits 9 + 1 sync (5) = 14*/
193 static void
set_vtx_resource(struct radeon_device * rdev,u64 gpu_addr)194 set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
195 {
196 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
197 u32 sq_vtx_constant_word2;
198
199 sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
200 SQ_VTXC_STRIDE(16);
201 #ifdef __BIG_ENDIAN
202 sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
203 #endif
204
205 radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7));
206 radeon_ring_write(ring, 0x460);
207 radeon_ring_write(ring, gpu_addr & 0xffffffff);
208 radeon_ring_write(ring, 48 - 1);
209 radeon_ring_write(ring, sq_vtx_constant_word2);
210 radeon_ring_write(ring, 1 << 0);
211 radeon_ring_write(ring, 0);
212 radeon_ring_write(ring, 0);
213 radeon_ring_write(ring, SQ_TEX_VTX_VALID_BUFFER << 30);
214
215 if ((rdev->family == CHIP_RV610) ||
216 (rdev->family == CHIP_RV620) ||
217 (rdev->family == CHIP_RS780) ||
218 (rdev->family == CHIP_RS880) ||
219 (rdev->family == CHIP_RV710))
220 cp_set_surface_sync(rdev,
221 PACKET3_TC_ACTION_ENA, 48, gpu_addr);
222 else
223 cp_set_surface_sync(rdev,
224 PACKET3_VC_ACTION_ENA, 48, gpu_addr);
225 }
226
227 /* emits 9 */
228 static void
set_tex_resource(struct radeon_device * rdev,int format,int w,int h,int pitch,u64 gpu_addr,u32 size)229 set_tex_resource(struct radeon_device *rdev,
230 int format, int w, int h, int pitch,
231 u64 gpu_addr, u32 size)
232 {
233 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
234 uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
235
236 if (h < 1)
237 h = 1;
238
239 sq_tex_resource_word0 = S_038000_DIM(V_038000_SQ_TEX_DIM_2D) |
240 S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
241 sq_tex_resource_word0 |= S_038000_PITCH((pitch >> 3) - 1) |
242 S_038000_TEX_WIDTH(w - 1);
243
244 sq_tex_resource_word1 = S_038004_DATA_FORMAT(format);
245 sq_tex_resource_word1 |= S_038004_TEX_HEIGHT(h - 1);
246
247 sq_tex_resource_word4 = S_038010_REQUEST_SIZE(1) |
248 S_038010_DST_SEL_X(SQ_SEL_X) |
249 S_038010_DST_SEL_Y(SQ_SEL_Y) |
250 S_038010_DST_SEL_Z(SQ_SEL_Z) |
251 S_038010_DST_SEL_W(SQ_SEL_W);
252
253 cp_set_surface_sync(rdev,
254 PACKET3_TC_ACTION_ENA, size, gpu_addr);
255
256 radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7));
257 radeon_ring_write(ring, 0);
258 radeon_ring_write(ring, sq_tex_resource_word0);
259 radeon_ring_write(ring, sq_tex_resource_word1);
260 radeon_ring_write(ring, gpu_addr >> 8);
261 radeon_ring_write(ring, gpu_addr >> 8);
262 radeon_ring_write(ring, sq_tex_resource_word4);
263 radeon_ring_write(ring, 0);
264 radeon_ring_write(ring, SQ_TEX_VTX_VALID_TEXTURE << 30);
265 }
266
267 /* emits 12 */
268 static void
set_scissors(struct radeon_device * rdev,int x1,int y1,int x2,int y2)269 set_scissors(struct radeon_device *rdev, int x1, int y1,
270 int x2, int y2)
271 {
272 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
273 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
274 radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
275 radeon_ring_write(ring, (x1 << 0) | (y1 << 16));
276 radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
277
278 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
279 radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
280 radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31));
281 radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
282
283 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
284 radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
285 radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31));
286 radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
287 }
288
289 /* emits 10 */
290 static void
draw_auto(struct radeon_device * rdev)291 draw_auto(struct radeon_device *rdev)
292 {
293 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
294 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
295 radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
296 radeon_ring_write(ring, DI_PT_RECTLIST);
297
298 radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0));
299 radeon_ring_write(ring,
300 #ifdef __BIG_ENDIAN
301 (2 << 2) |
302 #endif
303 DI_INDEX_SIZE_16_BIT);
304
305 radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0));
306 radeon_ring_write(ring, 1);
307
308 radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
309 radeon_ring_write(ring, 3);
310 radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX);
311
312 }
313
314 /* emits 14 */
315 static void
set_default_state(struct radeon_device * rdev)316 set_default_state(struct radeon_device *rdev)
317 {
318 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
319 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
320 u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
321 int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
322 int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
323 int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
324 u64 gpu_addr;
325 int dwords;
326
327 switch (rdev->family) {
328 case CHIP_R600:
329 num_ps_gprs = 192;
330 num_vs_gprs = 56;
331 num_temp_gprs = 4;
332 num_gs_gprs = 0;
333 num_es_gprs = 0;
334 num_ps_threads = 136;
335 num_vs_threads = 48;
336 num_gs_threads = 4;
337 num_es_threads = 4;
338 num_ps_stack_entries = 128;
339 num_vs_stack_entries = 128;
340 num_gs_stack_entries = 0;
341 num_es_stack_entries = 0;
342 break;
343 case CHIP_RV630:
344 case CHIP_RV635:
345 num_ps_gprs = 84;
346 num_vs_gprs = 36;
347 num_temp_gprs = 4;
348 num_gs_gprs = 0;
349 num_es_gprs = 0;
350 num_ps_threads = 144;
351 num_vs_threads = 40;
352 num_gs_threads = 4;
353 num_es_threads = 4;
354 num_ps_stack_entries = 40;
355 num_vs_stack_entries = 40;
356 num_gs_stack_entries = 32;
357 num_es_stack_entries = 16;
358 break;
359 case CHIP_RV610:
360 case CHIP_RV620:
361 case CHIP_RS780:
362 case CHIP_RS880:
363 default:
364 num_ps_gprs = 84;
365 num_vs_gprs = 36;
366 num_temp_gprs = 4;
367 num_gs_gprs = 0;
368 num_es_gprs = 0;
369 num_ps_threads = 136;
370 num_vs_threads = 48;
371 num_gs_threads = 4;
372 num_es_threads = 4;
373 num_ps_stack_entries = 40;
374 num_vs_stack_entries = 40;
375 num_gs_stack_entries = 32;
376 num_es_stack_entries = 16;
377 break;
378 case CHIP_RV670:
379 num_ps_gprs = 144;
380 num_vs_gprs = 40;
381 num_temp_gprs = 4;
382 num_gs_gprs = 0;
383 num_es_gprs = 0;
384 num_ps_threads = 136;
385 num_vs_threads = 48;
386 num_gs_threads = 4;
387 num_es_threads = 4;
388 num_ps_stack_entries = 40;
389 num_vs_stack_entries = 40;
390 num_gs_stack_entries = 32;
391 num_es_stack_entries = 16;
392 break;
393 case CHIP_RV770:
394 num_ps_gprs = 192;
395 num_vs_gprs = 56;
396 num_temp_gprs = 4;
397 num_gs_gprs = 0;
398 num_es_gprs = 0;
399 num_ps_threads = 188;
400 num_vs_threads = 60;
401 num_gs_threads = 0;
402 num_es_threads = 0;
403 num_ps_stack_entries = 256;
404 num_vs_stack_entries = 256;
405 num_gs_stack_entries = 0;
406 num_es_stack_entries = 0;
407 break;
408 case CHIP_RV730:
409 case CHIP_RV740:
410 num_ps_gprs = 84;
411 num_vs_gprs = 36;
412 num_temp_gprs = 4;
413 num_gs_gprs = 0;
414 num_es_gprs = 0;
415 num_ps_threads = 188;
416 num_vs_threads = 60;
417 num_gs_threads = 0;
418 num_es_threads = 0;
419 num_ps_stack_entries = 128;
420 num_vs_stack_entries = 128;
421 num_gs_stack_entries = 0;
422 num_es_stack_entries = 0;
423 break;
424 case CHIP_RV710:
425 num_ps_gprs = 192;
426 num_vs_gprs = 56;
427 num_temp_gprs = 4;
428 num_gs_gprs = 0;
429 num_es_gprs = 0;
430 num_ps_threads = 144;
431 num_vs_threads = 48;
432 num_gs_threads = 0;
433 num_es_threads = 0;
434 num_ps_stack_entries = 128;
435 num_vs_stack_entries = 128;
436 num_gs_stack_entries = 0;
437 num_es_stack_entries = 0;
438 break;
439 }
440
441 if ((rdev->family == CHIP_RV610) ||
442 (rdev->family == CHIP_RV620) ||
443 (rdev->family == CHIP_RS780) ||
444 (rdev->family == CHIP_RS880) ||
445 (rdev->family == CHIP_RV710))
446 sq_config = 0;
447 else
448 sq_config = VC_ENABLE;
449
450 sq_config |= (DX9_CONSTS |
451 ALU_INST_PREFER_VECTOR |
452 PS_PRIO(0) |
453 VS_PRIO(1) |
454 GS_PRIO(2) |
455 ES_PRIO(3));
456
457 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
458 NUM_VS_GPRS(num_vs_gprs) |
459 NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
460 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
461 NUM_ES_GPRS(num_es_gprs));
462 sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
463 NUM_VS_THREADS(num_vs_threads) |
464 NUM_GS_THREADS(num_gs_threads) |
465 NUM_ES_THREADS(num_es_threads));
466 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
467 NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
468 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
469 NUM_ES_STACK_ENTRIES(num_es_stack_entries));
470
471 /* emit an IB pointing at default state */
472 dwords = roundup2(rdev->r600_blit.state_len, 0x10);
473 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
474 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
475 radeon_ring_write(ring,
476 #ifdef __BIG_ENDIAN
477 (2 << 0) |
478 #endif
479 (gpu_addr & 0xFFFFFFFC));
480 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF);
481 radeon_ring_write(ring, dwords);
482
483 /* SQ config */
484 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 6));
485 radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
486 radeon_ring_write(ring, sq_config);
487 radeon_ring_write(ring, sq_gpr_resource_mgmt_1);
488 radeon_ring_write(ring, sq_gpr_resource_mgmt_2);
489 radeon_ring_write(ring, sq_thread_resource_mgmt);
490 radeon_ring_write(ring, sq_stack_resource_mgmt_1);
491 radeon_ring_write(ring, sq_stack_resource_mgmt_2);
492 }
493
r600_blit_init(struct radeon_device * rdev)494 int r600_blit_init(struct radeon_device *rdev)
495 {
496 u32 obj_size;
497 int i, r, dwords;
498 void *ptr;
499 u32 packet2s[16];
500 int num_packet2s = 0;
501
502 rdev->r600_blit.primitives.set_render_target = set_render_target;
503 rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync;
504 rdev->r600_blit.primitives.set_shaders = set_shaders;
505 rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource;
506 rdev->r600_blit.primitives.set_tex_resource = set_tex_resource;
507 rdev->r600_blit.primitives.set_scissors = set_scissors;
508 rdev->r600_blit.primitives.draw_auto = draw_auto;
509 rdev->r600_blit.primitives.set_default_state = set_default_state;
510
511 rdev->r600_blit.ring_size_common = 8; /* sync semaphore */
512 rdev->r600_blit.ring_size_common += 40; /* shaders + def state */
513 rdev->r600_blit.ring_size_common += 5; /* done copy */
514 rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */
515
516 rdev->r600_blit.ring_size_per_loop = 76;
517 /* set_render_target emits 2 extra dwords on rv6xx */
518 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
519 rdev->r600_blit.ring_size_per_loop += 2;
520
521 rdev->r600_blit.max_dim = 8192;
522
523 rdev->r600_blit.state_offset = 0;
524
525 if (rdev->family >= CHIP_RV770)
526 rdev->r600_blit.state_len = r7xx_default_size;
527 else
528 rdev->r600_blit.state_len = r6xx_default_size;
529
530 dwords = rdev->r600_blit.state_len;
531 while (dwords & 0xf) {
532 packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
533 dwords++;
534 }
535
536 obj_size = dwords * 4;
537 obj_size = roundup2(obj_size, 256);
538
539 rdev->r600_blit.vs_offset = obj_size;
540 obj_size += r6xx_vs_size * 4;
541 obj_size = roundup2(obj_size, 256);
542
543 rdev->r600_blit.ps_offset = obj_size;
544 obj_size += r6xx_ps_size * 4;
545 obj_size = roundup2(obj_size, 256);
546
547 /* pin copy shader into vram if not already initialized */
548 if (rdev->r600_blit.shader_obj == NULL) {
549 r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true,
550 RADEON_GEM_DOMAIN_VRAM,
551 NULL, &rdev->r600_blit.shader_obj);
552 if (r) {
553 DRM_ERROR("r600 failed to allocate shader\n");
554 return r;
555 }
556
557 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
558 if (unlikely(r != 0))
559 return r;
560 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
561 &rdev->r600_blit.shader_gpu_addr);
562 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
563 if (r) {
564 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
565 return r;
566 }
567 }
568
569 DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
570 obj_size,
571 rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
572
573 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
574 if (unlikely(r != 0))
575 return r;
576 r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
577 if (r) {
578 DRM_ERROR("failed to map blit object %d\n", r);
579 return r;
580 }
581 if (rdev->family >= CHIP_RV770)
582 memcpy_toio((char *)ptr + rdev->r600_blit.state_offset,
583 r7xx_default_state, rdev->r600_blit.state_len * 4);
584 else
585 memcpy_toio((char *)ptr + rdev->r600_blit.state_offset,
586 r6xx_default_state, rdev->r600_blit.state_len * 4);
587 if (num_packet2s)
588 memcpy_toio((char *)ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
589 packet2s, num_packet2s * 4);
590 for (i = 0; i < r6xx_vs_size; i++)
591 *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(r6xx_vs[i]);
592 for (i = 0; i < r6xx_ps_size; i++)
593 *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(r6xx_ps[i]);
594 radeon_bo_kunmap(rdev->r600_blit.shader_obj);
595 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
596
597 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
598 return 0;
599 }
600
r600_blit_fini(struct radeon_device * rdev)601 void r600_blit_fini(struct radeon_device *rdev)
602 {
603 int r;
604
605 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
606 if (rdev->r600_blit.shader_obj == NULL)
607 return;
608 /* If we can't reserve the bo, unref should be enough to destroy
609 * it when it becomes idle.
610 */
611 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
612 if (!r) {
613 radeon_bo_unpin(rdev->r600_blit.shader_obj);
614 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
615 }
616 radeon_bo_unref(&rdev->r600_blit.shader_obj);
617 }
618
r600_blit_create_rect(unsigned num_gpu_pages,int * width,int * height,int max_dim)619 static unsigned r600_blit_create_rect(unsigned num_gpu_pages,
620 int *width, int *height, int max_dim)
621 {
622 unsigned max_pages;
623 unsigned pages = num_gpu_pages;
624 int w, h;
625
626 if (num_gpu_pages == 0) {
627 /* not supposed to be called with no pages, but just in case */
628 h = 0;
629 w = 0;
630 pages = 0;
631 DRM_ERROR("%s: called with no pages", __func__);
632 } else {
633 int rect_order = 2;
634 h = RECT_UNIT_H;
635 while (num_gpu_pages / rect_order) {
636 h *= 2;
637 rect_order *= 4;
638 if (h >= max_dim) {
639 h = max_dim;
640 break;
641 }
642 }
643 max_pages = (max_dim * h) / (RECT_UNIT_W * RECT_UNIT_H);
644 if (pages > max_pages)
645 pages = max_pages;
646 w = (pages * RECT_UNIT_W * RECT_UNIT_H) / h;
647 w = (w / RECT_UNIT_W) * RECT_UNIT_W;
648 pages = (w * h) / (RECT_UNIT_W * RECT_UNIT_H);
649 KASSERT(pages != 0, ("r600_blit_create_rect: pages == 0"));
650 }
651
652
653 DRM_DEBUG("blit_rectangle: h=%d, w=%d, pages=%d\n", h, w, pages);
654
655 /* return width and height only of the caller wants it */
656 if (height)
657 *height = h;
658 if (width)
659 *width = w;
660
661 return pages;
662 }
663
664
r600_blit_prepare_copy(struct radeon_device * rdev,unsigned num_gpu_pages,struct radeon_fence ** fence,struct radeon_sa_bo ** vb,struct radeon_semaphore ** sem)665 int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages,
666 struct radeon_fence **fence, struct radeon_sa_bo **vb,
667 struct radeon_semaphore **sem)
668 {
669 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
670 int r;
671 int ring_size;
672 int num_loops = 0;
673 int dwords_per_loop = rdev->r600_blit.ring_size_per_loop;
674
675 /* num loops */
676 while (num_gpu_pages) {
677 num_gpu_pages -=
678 r600_blit_create_rect(num_gpu_pages, NULL, NULL,
679 rdev->r600_blit.max_dim);
680 num_loops++;
681 }
682
683 /* 48 bytes for vertex per loop */
684 r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, vb,
685 (num_loops*48)+256, 256, true);
686 if (r) {
687 return r;
688 }
689
690 r = radeon_semaphore_create(rdev, sem);
691 if (r) {
692 radeon_sa_bo_free(rdev, vb, NULL);
693 return r;
694 }
695
696 /* calculate number of loops correctly */
697 ring_size = num_loops * dwords_per_loop;
698 ring_size += rdev->r600_blit.ring_size_common;
699 r = radeon_ring_lock(rdev, ring, ring_size);
700 if (r) {
701 radeon_sa_bo_free(rdev, vb, NULL);
702 radeon_semaphore_free(rdev, sem, NULL);
703 return r;
704 }
705
706 if (radeon_fence_need_sync(*fence, RADEON_RING_TYPE_GFX_INDEX)) {
707 radeon_semaphore_sync_rings(rdev, *sem, (*fence)->ring,
708 RADEON_RING_TYPE_GFX_INDEX);
709 radeon_fence_note_sync(*fence, RADEON_RING_TYPE_GFX_INDEX);
710 } else {
711 radeon_semaphore_free(rdev, sem, NULL);
712 }
713
714 rdev->r600_blit.primitives.set_default_state(rdev);
715 rdev->r600_blit.primitives.set_shaders(rdev);
716 return 0;
717 }
718
r600_blit_done_copy(struct radeon_device * rdev,struct radeon_fence ** fence,struct radeon_sa_bo * vb,struct radeon_semaphore * sem)719 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence,
720 struct radeon_sa_bo *vb, struct radeon_semaphore *sem)
721 {
722 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
723 int r;
724
725 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
726 if (r) {
727 radeon_ring_unlock_undo(rdev, ring);
728 return;
729 }
730
731 radeon_ring_unlock_commit(rdev, ring);
732 radeon_sa_bo_free(rdev, &vb, *fence);
733 radeon_semaphore_free(rdev, &sem, *fence);
734 }
735
r600_kms_blit_copy(struct radeon_device * rdev,u64 src_gpu_addr,u64 dst_gpu_addr,unsigned num_gpu_pages,struct radeon_sa_bo * vb)736 void r600_kms_blit_copy(struct radeon_device *rdev,
737 u64 src_gpu_addr, u64 dst_gpu_addr,
738 unsigned num_gpu_pages,
739 struct radeon_sa_bo *vb)
740 {
741 u64 vb_gpu_addr;
742 u32 *vb_cpu_addr;
743
744 DRM_DEBUG("emitting copy %16jx %16jx %d\n",
745 (uintmax_t)src_gpu_addr, (uintmax_t)dst_gpu_addr, num_gpu_pages);
746 vb_cpu_addr = (u32 *)radeon_sa_bo_cpu_addr(vb);
747 vb_gpu_addr = radeon_sa_bo_gpu_addr(vb);
748
749 while (num_gpu_pages) {
750 int w, h;
751 unsigned size_in_bytes;
752 unsigned pages_per_loop =
753 r600_blit_create_rect(num_gpu_pages, &w, &h,
754 rdev->r600_blit.max_dim);
755
756 size_in_bytes = pages_per_loop * RADEON_GPU_PAGE_SIZE;
757 DRM_DEBUG("rectangle w=%d h=%d\n", w, h);
758
759 vb_cpu_addr[0] = 0;
760 vb_cpu_addr[1] = 0;
761 vb_cpu_addr[2] = 0;
762 vb_cpu_addr[3] = 0;
763
764 vb_cpu_addr[4] = 0;
765 vb_cpu_addr[5] = int2float(h);
766 vb_cpu_addr[6] = 0;
767 vb_cpu_addr[7] = int2float(h);
768
769 vb_cpu_addr[8] = int2float(w);
770 vb_cpu_addr[9] = int2float(h);
771 vb_cpu_addr[10] = int2float(w);
772 vb_cpu_addr[11] = int2float(h);
773
774 rdev->r600_blit.primitives.set_tex_resource(rdev, FMT_8_8_8_8,
775 w, h, w, src_gpu_addr, size_in_bytes);
776 rdev->r600_blit.primitives.set_render_target(rdev, COLOR_8_8_8_8,
777 w, h, dst_gpu_addr);
778 rdev->r600_blit.primitives.set_scissors(rdev, 0, 0, w, h);
779 rdev->r600_blit.primitives.set_vtx_resource(rdev, vb_gpu_addr);
780 rdev->r600_blit.primitives.draw_auto(rdev);
781 rdev->r600_blit.primitives.cp_set_surface_sync(rdev,
782 PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
783 size_in_bytes, dst_gpu_addr);
784
785 vb_cpu_addr += 12;
786 vb_gpu_addr += 4*12;
787 src_gpu_addr += size_in_bytes;
788 dst_gpu_addr += size_in_bytes;
789 num_gpu_pages -= pages_per_loop;
790 }
791 }
792