1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31
32 #include <dev/drm2/drmP.h>
33 #include "radeon.h"
34 #include "radeon_asic.h"
35 #include "atom.h"
36 #include "r520d.h"
37
38 /* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */
39
r520_mc_wait_for_idle(struct radeon_device * rdev)40 int r520_mc_wait_for_idle(struct radeon_device *rdev)
41 {
42 unsigned i;
43 uint32_t tmp;
44
45 for (i = 0; i < rdev->usec_timeout; i++) {
46 /* read MC_STATUS */
47 tmp = RREG32_MC(R520_MC_STATUS);
48 if (tmp & R520_MC_STATUS_IDLE) {
49 return 0;
50 }
51 DRM_UDELAY(1);
52 }
53 return -1;
54 }
55
r520_gpu_init(struct radeon_device * rdev)56 static void r520_gpu_init(struct radeon_device *rdev)
57 {
58 unsigned pipe_select_current, gb_pipe_select, tmp;
59
60 rv515_vga_render_disable(rdev);
61 /*
62 * DST_PIPE_CONFIG 0x170C
63 * GB_TILE_CONFIG 0x4018
64 * GB_FIFO_SIZE 0x4024
65 * GB_PIPE_SELECT 0x402C
66 * GB_PIPE_SELECT2 0x4124
67 * Z_PIPE_SHIFT 0
68 * Z_PIPE_MASK 0x000000003
69 * GB_FIFO_SIZE2 0x4128
70 * SC_SFIFO_SIZE_SHIFT 0
71 * SC_SFIFO_SIZE_MASK 0x000000003
72 * SC_MFIFO_SIZE_SHIFT 2
73 * SC_MFIFO_SIZE_MASK 0x00000000C
74 * FG_SFIFO_SIZE_SHIFT 4
75 * FG_SFIFO_SIZE_MASK 0x000000030
76 * ZB_MFIFO_SIZE_SHIFT 6
77 * ZB_MFIFO_SIZE_MASK 0x0000000C0
78 * GA_ENHANCE 0x4274
79 * SU_REG_DEST 0x42C8
80 */
81 /* workaround for RV530 */
82 if (rdev->family == CHIP_RV530) {
83 WREG32(0x4128, 0xFF);
84 }
85 r420_pipes_init(rdev);
86 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
87 tmp = RREG32(R300_DST_PIPE_CONFIG);
88 pipe_select_current = (tmp >> 2) & 3;
89 tmp = (1 << pipe_select_current) |
90 (((gb_pipe_select >> 8) & 0xF) << 4);
91 WREG32_PLL(0x000D, tmp);
92 if (r520_mc_wait_for_idle(rdev)) {
93 DRM_ERROR("Failed to wait MC idle while "
94 "programming pipes. Bad things might happen.\n");
95 }
96 }
97
r520_vram_get_type(struct radeon_device * rdev)98 static void r520_vram_get_type(struct radeon_device *rdev)
99 {
100 uint32_t tmp;
101
102 rdev->mc.vram_width = 128;
103 rdev->mc.vram_is_ddr = true;
104 tmp = RREG32_MC(R520_MC_CNTL0);
105 switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
106 case 0:
107 rdev->mc.vram_width = 32;
108 break;
109 case 1:
110 rdev->mc.vram_width = 64;
111 break;
112 case 2:
113 rdev->mc.vram_width = 128;
114 break;
115 case 3:
116 rdev->mc.vram_width = 256;
117 break;
118 default:
119 rdev->mc.vram_width = 128;
120 break;
121 }
122 if (tmp & R520_MC_CHANNEL_SIZE)
123 rdev->mc.vram_width *= 2;
124 }
125
r520_mc_init(struct radeon_device * rdev)126 static void r520_mc_init(struct radeon_device *rdev)
127 {
128
129 r520_vram_get_type(rdev);
130 r100_vram_init_sizes(rdev);
131 radeon_vram_location(rdev, &rdev->mc, 0);
132 rdev->mc.gtt_base_align = 0;
133 if (!(rdev->flags & RADEON_IS_AGP))
134 radeon_gtt_location(rdev, &rdev->mc);
135 radeon_update_bandwidth_info(rdev);
136 }
137
r520_mc_program(struct radeon_device * rdev)138 static void r520_mc_program(struct radeon_device *rdev)
139 {
140 struct rv515_mc_save save;
141
142 /* Stops all mc clients */
143 rv515_mc_stop(rdev, &save);
144
145 /* Wait for mc idle */
146 if (r520_mc_wait_for_idle(rdev))
147 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
148 /* Write VRAM size in case we are limiting it */
149 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
150 /* Program MC, should be a 32bits limited address space */
151 WREG32_MC(R_000004_MC_FB_LOCATION,
152 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
153 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
154 WREG32(R_000134_HDP_FB_LOCATION,
155 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
156 if (rdev->flags & RADEON_IS_AGP) {
157 WREG32_MC(R_000005_MC_AGP_LOCATION,
158 S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) |
159 S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
160 WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
161 WREG32_MC(R_000007_AGP_BASE_2,
162 S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
163 } else {
164 WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF);
165 WREG32_MC(R_000006_AGP_BASE, 0);
166 WREG32_MC(R_000007_AGP_BASE_2, 0);
167 }
168
169 rv515_mc_resume(rdev, &save);
170 }
171
r520_startup(struct radeon_device * rdev)172 static int r520_startup(struct radeon_device *rdev)
173 {
174 int r;
175
176 r520_mc_program(rdev);
177 /* Resume clock */
178 rv515_clock_startup(rdev);
179 /* Initialize GPU configuration (# pipes, ...) */
180 r520_gpu_init(rdev);
181 /* Initialize GART (initialize after TTM so we can allocate
182 * memory through TTM but finalize after TTM) */
183 if (rdev->flags & RADEON_IS_PCIE) {
184 r = rv370_pcie_gart_enable(rdev);
185 if (r)
186 return r;
187 }
188
189 /* allocate wb buffer */
190 r = radeon_wb_init(rdev);
191 if (r)
192 return r;
193
194 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
195 if (r) {
196 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
197 return r;
198 }
199
200 /* Enable IRQ */
201 rs600_irq_set(rdev);
202 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
203 /* 1M ring buffer */
204 r = r100_cp_init(rdev, 1024 * 1024);
205 if (r) {
206 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
207 return r;
208 }
209
210 r = radeon_ib_pool_init(rdev);
211 if (r) {
212 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
213 return r;
214 }
215
216 return 0;
217 }
218
r520_resume(struct radeon_device * rdev)219 int r520_resume(struct radeon_device *rdev)
220 {
221 int r;
222
223 /* Make sur GART are not working */
224 if (rdev->flags & RADEON_IS_PCIE)
225 rv370_pcie_gart_disable(rdev);
226 /* Resume clock before doing reset */
227 rv515_clock_startup(rdev);
228 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
229 if (radeon_asic_reset(rdev)) {
230 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
231 RREG32(R_000E40_RBBM_STATUS),
232 RREG32(R_0007C0_CP_STAT));
233 }
234 /* post */
235 atom_asic_init(rdev->mode_info.atom_context);
236 /* Resume clock after posting */
237 rv515_clock_startup(rdev);
238 /* Initialize surface registers */
239 radeon_surface_init(rdev);
240
241 rdev->accel_working = true;
242 r = r520_startup(rdev);
243 if (r) {
244 rdev->accel_working = false;
245 }
246 return r;
247 }
248
r520_init(struct radeon_device * rdev)249 int r520_init(struct radeon_device *rdev)
250 {
251 int r;
252
253 /* Initialize scratch registers */
254 radeon_scratch_init(rdev);
255 /* Initialize surface registers */
256 radeon_surface_init(rdev);
257 /* restore some register to sane defaults */
258 r100_restore_sanity(rdev);
259 /* TODO: disable VGA need to use VGA request */
260 /* BIOS*/
261 if (!radeon_get_bios(rdev)) {
262 if (ASIC_IS_AVIVO(rdev))
263 return -EINVAL;
264 }
265 if (rdev->is_atom_bios) {
266 r = radeon_atombios_init(rdev);
267 if (r)
268 return r;
269 } else {
270 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
271 return -EINVAL;
272 }
273 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
274 if (radeon_asic_reset(rdev)) {
275 dev_warn(rdev->dev,
276 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
277 RREG32(R_000E40_RBBM_STATUS),
278 RREG32(R_0007C0_CP_STAT));
279 }
280 /* check if cards are posted or not */
281 if (radeon_boot_test_post_card(rdev) == false)
282 return -EINVAL;
283
284 if (!radeon_card_posted(rdev) && rdev->bios) {
285 DRM_INFO("GPU not posted. posting now...\n");
286 atom_asic_init(rdev->mode_info.atom_context);
287 }
288 /* Initialize clocks */
289 radeon_get_clock_info(rdev->ddev);
290 /* initialize AGP */
291 if (rdev->flags & RADEON_IS_AGP) {
292 r = radeon_agp_init(rdev);
293 if (r) {
294 radeon_agp_disable(rdev);
295 }
296 }
297 /* initialize memory controller */
298 r520_mc_init(rdev);
299 rv515_debugfs(rdev);
300 /* Fence driver */
301 r = radeon_fence_driver_init(rdev);
302 if (r)
303 return r;
304 r = radeon_irq_kms_init(rdev);
305 if (r)
306 return r;
307 /* Memory manager */
308 r = radeon_bo_init(rdev);
309 if (r)
310 return r;
311 r = rv370_pcie_gart_init(rdev);
312 if (r)
313 return r;
314 rv515_set_safe_registers(rdev);
315
316 rdev->accel_working = true;
317 r = r520_startup(rdev);
318 if (r) {
319 /* Somethings want wront with the accel init stop accel */
320 dev_err(rdev->dev, "Disabling GPU acceleration\n");
321 r100_cp_fini(rdev);
322 radeon_wb_fini(rdev);
323 radeon_ib_pool_fini(rdev);
324 radeon_irq_kms_fini(rdev);
325 rv370_pcie_gart_fini(rdev);
326 radeon_agp_fini(rdev);
327 rdev->accel_working = false;
328 }
329 return 0;
330 }
331