1 /* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
2 * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com
3 */
4 /*-
5 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
6 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
7 * All Rights Reserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 *
28 * Authors:
29 * Gareth Hughes <gareth@valinux.com>
30 */
31
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34
35 #include "dev/drm/drmP.h"
36 #include "dev/drm/drm.h"
37 #include "dev/drm/r128_drm.h"
38 #include "dev/drm/r128_drv.h"
39
40 #define R128_FIFO_DEBUG 0
41
42 /* CCE microcode (from ATI) */
43 static u32 r128_cce_microcode[] = {
44 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0,
45 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0,
46 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1,
47 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11,
48 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28,
49 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9,
50 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656,
51 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1,
52 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071,
53 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2,
54 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1,
55 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1,
56 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1,
57 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2,
58 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1,
59 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82,
60 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729,
61 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008,
62 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0,
63 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1,
64 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1,
65 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0,
66 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370,
67 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1,
68 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793,
69 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1,
70 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1,
71 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1,
72 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1,
73 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894,
74 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14,
75 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1,
76 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1,
77 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1,
78 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
79 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
80 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
81 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
82 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
83 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
84 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
85 };
86
R128_READ_PLL(struct drm_device * dev,int addr)87 static int R128_READ_PLL(struct drm_device * dev, int addr)
88 {
89 drm_r128_private_t *dev_priv = dev->dev_private;
90
91 R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
92 return R128_READ(R128_CLOCK_CNTL_DATA);
93 }
94
95 #if R128_FIFO_DEBUG
r128_status(drm_r128_private_t * dev_priv)96 static void r128_status(drm_r128_private_t * dev_priv)
97 {
98 printk("GUI_STAT = 0x%08x\n",
99 (unsigned int)R128_READ(R128_GUI_STAT));
100 printk("PM4_STAT = 0x%08x\n",
101 (unsigned int)R128_READ(R128_PM4_STAT));
102 printk("PM4_BUFFER_DL_WPTR = 0x%08x\n",
103 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR));
104 printk("PM4_BUFFER_DL_RPTR = 0x%08x\n",
105 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR));
106 printk("PM4_MICRO_CNTL = 0x%08x\n",
107 (unsigned int)R128_READ(R128_PM4_MICRO_CNTL));
108 printk("PM4_BUFFER_CNTL = 0x%08x\n",
109 (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL));
110 }
111 #endif
112
113 /* ================================================================
114 * Engine, FIFO control
115 */
116
r128_do_pixcache_flush(drm_r128_private_t * dev_priv)117 static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv)
118 {
119 u32 tmp;
120 int i;
121
122 tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL;
123 R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp);
124
125 for (i = 0; i < dev_priv->usec_timeout; i++) {
126 if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY)) {
127 return 0;
128 }
129 DRM_UDELAY(1);
130 }
131
132 #if R128_FIFO_DEBUG
133 DRM_ERROR("failed!\n");
134 #endif
135 return -EBUSY;
136 }
137
r128_do_wait_for_fifo(drm_r128_private_t * dev_priv,int entries)138 static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries)
139 {
140 int i;
141
142 for (i = 0; i < dev_priv->usec_timeout; i++) {
143 int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK;
144 if (slots >= entries)
145 return 0;
146 DRM_UDELAY(1);
147 }
148
149 #if R128_FIFO_DEBUG
150 DRM_ERROR("failed!\n");
151 #endif
152 return -EBUSY;
153 }
154
r128_do_wait_for_idle(drm_r128_private_t * dev_priv)155 static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv)
156 {
157 int i, ret;
158
159 ret = r128_do_wait_for_fifo(dev_priv, 64);
160 if (ret)
161 return ret;
162
163 for (i = 0; i < dev_priv->usec_timeout; i++) {
164 if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) {
165 r128_do_pixcache_flush(dev_priv);
166 return 0;
167 }
168 DRM_UDELAY(1);
169 }
170
171 #if R128_FIFO_DEBUG
172 DRM_ERROR("failed!\n");
173 #endif
174 return -EBUSY;
175 }
176
177 /* ================================================================
178 * CCE control, initialization
179 */
180
181 /* Load the microcode for the CCE */
r128_cce_load_microcode(drm_r128_private_t * dev_priv)182 static void r128_cce_load_microcode(drm_r128_private_t * dev_priv)
183 {
184 int i;
185
186 DRM_DEBUG("\n");
187
188 r128_do_wait_for_idle(dev_priv);
189
190 R128_WRITE(R128_PM4_MICROCODE_ADDR, 0);
191 for (i = 0; i < 256; i++) {
192 R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]);
193 R128_WRITE(R128_PM4_MICROCODE_DATAL,
194 r128_cce_microcode[i * 2 + 1]);
195 }
196 }
197
198 /* Flush any pending commands to the CCE. This should only be used just
199 * prior to a wait for idle, as it informs the engine that the command
200 * stream is ending.
201 */
r128_do_cce_flush(drm_r128_private_t * dev_priv)202 static void r128_do_cce_flush(drm_r128_private_t * dev_priv)
203 {
204 u32 tmp;
205
206 tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE;
207 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp);
208 }
209
210 /* Wait for the CCE to go idle.
211 */
r128_do_cce_idle(drm_r128_private_t * dev_priv)212 int r128_do_cce_idle(drm_r128_private_t * dev_priv)
213 {
214 int i;
215
216 for (i = 0; i < dev_priv->usec_timeout; i++) {
217 if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) {
218 int pm4stat = R128_READ(R128_PM4_STAT);
219 if (((pm4stat & R128_PM4_FIFOCNT_MASK) >=
220 dev_priv->cce_fifo_size) &&
221 !(pm4stat & (R128_PM4_BUSY |
222 R128_PM4_GUI_ACTIVE))) {
223 return r128_do_pixcache_flush(dev_priv);
224 }
225 }
226 DRM_UDELAY(1);
227 }
228
229 #if R128_FIFO_DEBUG
230 DRM_ERROR("failed!\n");
231 r128_status(dev_priv);
232 #endif
233 return -EBUSY;
234 }
235
236 /* Start the Concurrent Command Engine.
237 */
r128_do_cce_start(drm_r128_private_t * dev_priv)238 static void r128_do_cce_start(drm_r128_private_t * dev_priv)
239 {
240 r128_do_wait_for_idle(dev_priv);
241
242 R128_WRITE(R128_PM4_BUFFER_CNTL,
243 dev_priv->cce_mode | dev_priv->ring.size_l2qw
244 | R128_PM4_BUFFER_CNTL_NOUPDATE);
245 R128_READ(R128_PM4_BUFFER_ADDR); /* as per the sample code */
246 R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN);
247
248 dev_priv->cce_running = 1;
249 }
250
251 /* Reset the Concurrent Command Engine. This will not flush any pending
252 * commands, so you must wait for the CCE command stream to complete
253 * before calling this routine.
254 */
r128_do_cce_reset(drm_r128_private_t * dev_priv)255 static void r128_do_cce_reset(drm_r128_private_t * dev_priv)
256 {
257 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
258 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
259 dev_priv->ring.tail = 0;
260 }
261
262 /* Stop the Concurrent Command Engine. This will not flush any pending
263 * commands, so you must flush the command stream and wait for the CCE
264 * to go idle before calling this routine.
265 */
r128_do_cce_stop(drm_r128_private_t * dev_priv)266 static void r128_do_cce_stop(drm_r128_private_t * dev_priv)
267 {
268 R128_WRITE(R128_PM4_MICRO_CNTL, 0);
269 R128_WRITE(R128_PM4_BUFFER_CNTL,
270 R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE);
271
272 dev_priv->cce_running = 0;
273 }
274
275 /* Reset the engine. This will stop the CCE if it is running.
276 */
r128_do_engine_reset(struct drm_device * dev)277 static int r128_do_engine_reset(struct drm_device * dev)
278 {
279 drm_r128_private_t *dev_priv = dev->dev_private;
280 u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
281
282 r128_do_pixcache_flush(dev_priv);
283
284 clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX);
285 mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL);
286
287 R128_WRITE_PLL(R128_MCLK_CNTL,
288 mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP);
289
290 gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL);
291
292 /* Taken from the sample code - do not change */
293 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI);
294 R128_READ(R128_GEN_RESET_CNTL);
295 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI);
296 R128_READ(R128_GEN_RESET_CNTL);
297
298 R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl);
299 R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index);
300 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl);
301
302 /* Reset the CCE ring */
303 r128_do_cce_reset(dev_priv);
304
305 /* The CCE is no longer running after an engine reset */
306 dev_priv->cce_running = 0;
307
308 /* Reset any pending vertex, indirect buffers */
309 r128_freelist_reset(dev);
310
311 return 0;
312 }
313
r128_cce_init_ring_buffer(struct drm_device * dev,drm_r128_private_t * dev_priv)314 static void r128_cce_init_ring_buffer(struct drm_device * dev,
315 drm_r128_private_t * dev_priv)
316 {
317 u32 ring_start;
318 u32 tmp;
319
320 DRM_DEBUG("\n");
321
322 /* The manual (p. 2) says this address is in "VM space". This
323 * means it's an offset from the start of AGP space.
324 */
325 #if __OS_HAS_AGP
326 if (!dev_priv->is_pci)
327 ring_start = dev_priv->cce_ring->offset - dev->agp->base;
328 else
329 #endif
330 ring_start = dev_priv->cce_ring->offset - dev->sg->vaddr;
331
332 R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET);
333
334 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
335 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
336
337 /* Set watermark control */
338 R128_WRITE(R128_PM4_BUFFER_WM_CNTL,
339 ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT)
340 | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT)
341 | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT)
342 | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT));
343
344 /* Force read. Why? Because it's in the examples... */
345 R128_READ(R128_PM4_BUFFER_ADDR);
346
347 /* Turn on bus mastering */
348 tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS;
349 R128_WRITE(R128_BUS_CNTL, tmp);
350 }
351
r128_do_init_cce(struct drm_device * dev,drm_r128_init_t * init)352 static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init)
353 {
354 drm_r128_private_t *dev_priv;
355
356 DRM_DEBUG("\n");
357
358 dev_priv = drm_alloc(sizeof(drm_r128_private_t), DRM_MEM_DRIVER);
359 if (dev_priv == NULL)
360 return -ENOMEM;
361
362 memset(dev_priv, 0, sizeof(drm_r128_private_t));
363
364 dev_priv->is_pci = init->is_pci;
365
366 if (dev_priv->is_pci && !dev->sg) {
367 DRM_ERROR("PCI GART memory not allocated!\n");
368 dev->dev_private = (void *)dev_priv;
369 r128_do_cleanup_cce(dev);
370 return -EINVAL;
371 }
372
373 dev_priv->usec_timeout = init->usec_timeout;
374 if (dev_priv->usec_timeout < 1 ||
375 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) {
376 DRM_DEBUG("TIMEOUT problem!\n");
377 dev->dev_private = (void *)dev_priv;
378 r128_do_cleanup_cce(dev);
379 return -EINVAL;
380 }
381
382 dev_priv->cce_mode = init->cce_mode;
383
384 /* GH: Simple idle check.
385 */
386 atomic_set(&dev_priv->idle_count, 0);
387
388 /* We don't support anything other than bus-mastering ring mode,
389 * but the ring can be in either AGP or PCI space for the ring
390 * read pointer.
391 */
392 if ((init->cce_mode != R128_PM4_192BM) &&
393 (init->cce_mode != R128_PM4_128BM_64INDBM) &&
394 (init->cce_mode != R128_PM4_64BM_128INDBM) &&
395 (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) {
396 DRM_DEBUG("Bad cce_mode!\n");
397 dev->dev_private = (void *)dev_priv;
398 r128_do_cleanup_cce(dev);
399 return -EINVAL;
400 }
401
402 switch (init->cce_mode) {
403 case R128_PM4_NONPM4:
404 dev_priv->cce_fifo_size = 0;
405 break;
406 case R128_PM4_192PIO:
407 case R128_PM4_192BM:
408 dev_priv->cce_fifo_size = 192;
409 break;
410 case R128_PM4_128PIO_64INDBM:
411 case R128_PM4_128BM_64INDBM:
412 dev_priv->cce_fifo_size = 128;
413 break;
414 case R128_PM4_64PIO_128INDBM:
415 case R128_PM4_64BM_128INDBM:
416 case R128_PM4_64PIO_64VCBM_64INDBM:
417 case R128_PM4_64BM_64VCBM_64INDBM:
418 case R128_PM4_64PIO_64VCPIO_64INDPIO:
419 dev_priv->cce_fifo_size = 64;
420 break;
421 }
422
423 switch (init->fb_bpp) {
424 case 16:
425 dev_priv->color_fmt = R128_DATATYPE_RGB565;
426 break;
427 case 32:
428 default:
429 dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
430 break;
431 }
432 dev_priv->front_offset = init->front_offset;
433 dev_priv->front_pitch = init->front_pitch;
434 dev_priv->back_offset = init->back_offset;
435 dev_priv->back_pitch = init->back_pitch;
436
437 switch (init->depth_bpp) {
438 case 16:
439 dev_priv->depth_fmt = R128_DATATYPE_RGB565;
440 break;
441 case 24:
442 case 32:
443 default:
444 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
445 break;
446 }
447 dev_priv->depth_offset = init->depth_offset;
448 dev_priv->depth_pitch = init->depth_pitch;
449 dev_priv->span_offset = init->span_offset;
450
451 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) |
452 (dev_priv->front_offset >> 5));
453 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) |
454 (dev_priv->back_offset >> 5));
455 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
456 (dev_priv->depth_offset >> 5) |
457 R128_DST_TILE);
458 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
459 (dev_priv->span_offset >> 5));
460
461 dev_priv->sarea = drm_getsarea(dev);
462 if (!dev_priv->sarea) {
463 DRM_ERROR("could not find sarea!\n");
464 dev->dev_private = (void *)dev_priv;
465 r128_do_cleanup_cce(dev);
466 return -EINVAL;
467 }
468
469 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
470 if (!dev_priv->mmio) {
471 DRM_ERROR("could not find mmio region!\n");
472 dev->dev_private = (void *)dev_priv;
473 r128_do_cleanup_cce(dev);
474 return -EINVAL;
475 }
476 dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset);
477 if (!dev_priv->cce_ring) {
478 DRM_ERROR("could not find cce ring region!\n");
479 dev->dev_private = (void *)dev_priv;
480 r128_do_cleanup_cce(dev);
481 return -EINVAL;
482 }
483 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
484 if (!dev_priv->ring_rptr) {
485 DRM_ERROR("could not find ring read pointer!\n");
486 dev->dev_private = (void *)dev_priv;
487 r128_do_cleanup_cce(dev);
488 return -EINVAL;
489 }
490 dev->agp_buffer_token = init->buffers_offset;
491 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
492 if (!dev->agp_buffer_map) {
493 DRM_ERROR("could not find dma buffer region!\n");
494 dev->dev_private = (void *)dev_priv;
495 r128_do_cleanup_cce(dev);
496 return -EINVAL;
497 }
498
499 if (!dev_priv->is_pci) {
500 dev_priv->agp_textures =
501 drm_core_findmap(dev, init->agp_textures_offset);
502 if (!dev_priv->agp_textures) {
503 DRM_ERROR("could not find agp texture region!\n");
504 dev->dev_private = (void *)dev_priv;
505 r128_do_cleanup_cce(dev);
506 return -EINVAL;
507 }
508 }
509
510 dev_priv->sarea_priv =
511 (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->virtual +
512 init->sarea_priv_offset);
513
514 #if __OS_HAS_AGP
515 if (!dev_priv->is_pci) {
516 drm_core_ioremap(dev_priv->cce_ring, dev);
517 drm_core_ioremap(dev_priv->ring_rptr, dev);
518 drm_core_ioremap(dev->agp_buffer_map, dev);
519 if (!dev_priv->cce_ring->virtual ||
520 !dev_priv->ring_rptr->virtual ||
521 !dev->agp_buffer_map->virtual) {
522 DRM_ERROR("Could not ioremap agp regions!\n");
523 dev->dev_private = (void *)dev_priv;
524 r128_do_cleanup_cce(dev);
525 return -ENOMEM;
526 }
527 } else
528 #endif
529 {
530 dev_priv->cce_ring->virtual =
531 (void *)dev_priv->cce_ring->offset;
532 dev_priv->ring_rptr->virtual =
533 (void *)dev_priv->ring_rptr->offset;
534 dev->agp_buffer_map->virtual =
535 (void *)dev->agp_buffer_map->offset;
536 }
537
538 #if __OS_HAS_AGP
539 if (!dev_priv->is_pci)
540 dev_priv->cce_buffers_offset = dev->agp->base;
541 else
542 #endif
543 dev_priv->cce_buffers_offset = dev->sg->vaddr;
544
545 dev_priv->ring.start = (u32 *) dev_priv->cce_ring->virtual;
546 dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->virtual
547 + init->ring_size / sizeof(u32));
548 dev_priv->ring.size = init->ring_size;
549 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
550
551 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
552
553 dev_priv->ring.high_mark = 128;
554
555 dev_priv->sarea_priv->last_frame = 0;
556 R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
557
558 dev_priv->sarea_priv->last_dispatch = 0;
559 R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch);
560
561 #if __OS_HAS_AGP
562 if (dev_priv->is_pci) {
563 #endif
564 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
565 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN;
566 dev_priv->gart_info.table_size = R128_PCIGART_TABLE_SIZE;
567 dev_priv->gart_info.addr = NULL;
568 dev_priv->gart_info.bus_addr = 0;
569 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
570 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
571 DRM_ERROR("failed to init PCI GART!\n");
572 dev->dev_private = (void *)dev_priv;
573 r128_do_cleanup_cce(dev);
574 return -ENOMEM;
575 }
576 R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr);
577 #if __OS_HAS_AGP
578 }
579 #endif
580
581 r128_cce_init_ring_buffer(dev, dev_priv);
582 r128_cce_load_microcode(dev_priv);
583
584 dev->dev_private = (void *)dev_priv;
585
586 r128_do_engine_reset(dev);
587
588 return 0;
589 }
590
r128_do_cleanup_cce(struct drm_device * dev)591 int r128_do_cleanup_cce(struct drm_device * dev)
592 {
593
594 /* Make sure interrupts are disabled here because the uninstall ioctl
595 * may not have been called from userspace and after dev_private
596 * is freed, it's too late.
597 */
598 if (dev->irq_enabled)
599 drm_irq_uninstall(dev);
600
601 if (dev->dev_private) {
602 drm_r128_private_t *dev_priv = dev->dev_private;
603
604 #if __OS_HAS_AGP
605 if (!dev_priv->is_pci) {
606 if (dev_priv->cce_ring != NULL)
607 drm_core_ioremapfree(dev_priv->cce_ring, dev);
608 if (dev_priv->ring_rptr != NULL)
609 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
610 if (dev->agp_buffer_map != NULL) {
611 drm_core_ioremapfree(dev->agp_buffer_map, dev);
612 dev->agp_buffer_map = NULL;
613 }
614 } else
615 #endif
616 {
617 if (dev_priv->gart_info.bus_addr)
618 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
619 DRM_ERROR("failed to cleanup PCI GART!\n");
620 }
621
622 drm_free(dev->dev_private, sizeof(drm_r128_private_t),
623 DRM_MEM_DRIVER);
624 dev->dev_private = NULL;
625 }
626
627 return 0;
628 }
629
r128_cce_init(struct drm_device * dev,void * data,struct drm_file * file_priv)630 int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
631 {
632 drm_r128_init_t *init = data;
633
634 DRM_DEBUG("\n");
635
636 LOCK_TEST_WITH_RETURN(dev, file_priv);
637
638 switch (init->func) {
639 case R128_INIT_CCE:
640 return r128_do_init_cce(dev, init);
641 case R128_CLEANUP_CCE:
642 return r128_do_cleanup_cce(dev);
643 }
644
645 return -EINVAL;
646 }
647
r128_cce_start(struct drm_device * dev,void * data,struct drm_file * file_priv)648 int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
649 {
650 drm_r128_private_t *dev_priv = dev->dev_private;
651 DRM_DEBUG("\n");
652
653 LOCK_TEST_WITH_RETURN(dev, file_priv);
654
655 if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {
656 DRM_DEBUG("while CCE running\n");
657 return 0;
658 }
659
660 r128_do_cce_start(dev_priv);
661
662 return 0;
663 }
664
665 /* Stop the CCE. The engine must have been idled before calling this
666 * routine.
667 */
r128_cce_stop(struct drm_device * dev,void * data,struct drm_file * file_priv)668 int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
669 {
670 drm_r128_private_t *dev_priv = dev->dev_private;
671 drm_r128_cce_stop_t *stop = data;
672 int ret;
673 DRM_DEBUG("\n");
674
675 LOCK_TEST_WITH_RETURN(dev, file_priv);
676
677 /* Flush any pending CCE commands. This ensures any outstanding
678 * commands are exectuted by the engine before we turn it off.
679 */
680 if (stop->flush) {
681 r128_do_cce_flush(dev_priv);
682 }
683
684 /* If we fail to make the engine go idle, we return an error
685 * code so that the DRM ioctl wrapper can try again.
686 */
687 if (stop->idle) {
688 ret = r128_do_cce_idle(dev_priv);
689 if (ret)
690 return ret;
691 }
692
693 /* Finally, we can turn off the CCE. If the engine isn't idle,
694 * we will get some dropped triangles as they won't be fully
695 * rendered before the CCE is shut down.
696 */
697 r128_do_cce_stop(dev_priv);
698
699 /* Reset the engine */
700 r128_do_engine_reset(dev);
701
702 return 0;
703 }
704
705 /* Just reset the CCE ring. Called as part of an X Server engine reset.
706 */
r128_cce_reset(struct drm_device * dev,void * data,struct drm_file * file_priv)707 int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
708 {
709 drm_r128_private_t *dev_priv = dev->dev_private;
710 DRM_DEBUG("\n");
711
712 LOCK_TEST_WITH_RETURN(dev, file_priv);
713
714 if (!dev_priv) {
715 DRM_DEBUG("called before init done\n");
716 return -EINVAL;
717 }
718
719 r128_do_cce_reset(dev_priv);
720
721 /* The CCE is no longer running after an engine reset */
722 dev_priv->cce_running = 0;
723
724 return 0;
725 }
726
r128_cce_idle(struct drm_device * dev,void * data,struct drm_file * file_priv)727 int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
728 {
729 drm_r128_private_t *dev_priv = dev->dev_private;
730 DRM_DEBUG("\n");
731
732 LOCK_TEST_WITH_RETURN(dev, file_priv);
733
734 if (dev_priv->cce_running) {
735 r128_do_cce_flush(dev_priv);
736 }
737
738 return r128_do_cce_idle(dev_priv);
739 }
740
r128_engine_reset(struct drm_device * dev,void * data,struct drm_file * file_priv)741 int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
742 {
743 DRM_DEBUG("\n");
744
745 LOCK_TEST_WITH_RETURN(dev, file_priv);
746
747 return r128_do_engine_reset(dev);
748 }
749
r128_fullscreen(struct drm_device * dev,void * data,struct drm_file * file_priv)750 int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
751 {
752 return -EINVAL;
753 }
754
755 /* ================================================================
756 * Freelist management
757 */
758 #define R128_BUFFER_USED 0xffffffff
759 #define R128_BUFFER_FREE 0
760
761 #if 0
762 static int r128_freelist_init(struct drm_device * dev)
763 {
764 struct drm_device_dma *dma = dev->dma;
765 drm_r128_private_t *dev_priv = dev->dev_private;
766 struct drm_buf *buf;
767 drm_r128_buf_priv_t *buf_priv;
768 drm_r128_freelist_t *entry;
769 int i;
770
771 dev_priv->head = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);
772 if (dev_priv->head == NULL)
773 return -ENOMEM;
774
775 memset(dev_priv->head, 0, sizeof(drm_r128_freelist_t));
776 dev_priv->head->age = R128_BUFFER_USED;
777
778 for (i = 0; i < dma->buf_count; i++) {
779 buf = dma->buflist[i];
780 buf_priv = buf->dev_private;
781
782 entry = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);
783 if (!entry)
784 return -ENOMEM;
785
786 entry->age = R128_BUFFER_FREE;
787 entry->buf = buf;
788 entry->prev = dev_priv->head;
789 entry->next = dev_priv->head->next;
790 if (!entry->next)
791 dev_priv->tail = entry;
792
793 buf_priv->discard = 0;
794 buf_priv->dispatched = 0;
795 buf_priv->list_entry = entry;
796
797 dev_priv->head->next = entry;
798
799 if (dev_priv->head->next)
800 dev_priv->head->next->prev = entry;
801 }
802
803 return 0;
804
805 }
806 #endif
807
r128_freelist_get(struct drm_device * dev)808 static struct drm_buf *r128_freelist_get(struct drm_device * dev)
809 {
810 struct drm_device_dma *dma = dev->dma;
811 drm_r128_private_t *dev_priv = dev->dev_private;
812 drm_r128_buf_priv_t *buf_priv;
813 struct drm_buf *buf;
814 int i, t;
815
816 /* FIXME: Optimize -- use freelist code */
817
818 for (i = 0; i < dma->buf_count; i++) {
819 buf = dma->buflist[i];
820 buf_priv = buf->dev_private;
821 if (buf->file_priv == 0)
822 return buf;
823 }
824
825 for (t = 0; t < dev_priv->usec_timeout; t++) {
826 u32 done_age = R128_READ(R128_LAST_DISPATCH_REG);
827
828 for (i = 0; i < dma->buf_count; i++) {
829 buf = dma->buflist[i];
830 buf_priv = buf->dev_private;
831 if (buf->pending && buf_priv->age <= done_age) {
832 /* The buffer has been processed, so it
833 * can now be used.
834 */
835 buf->pending = 0;
836 return buf;
837 }
838 }
839 DRM_UDELAY(1);
840 }
841
842 DRM_DEBUG("returning NULL!\n");
843 return NULL;
844 }
845
r128_freelist_reset(struct drm_device * dev)846 void r128_freelist_reset(struct drm_device * dev)
847 {
848 struct drm_device_dma *dma = dev->dma;
849 int i;
850
851 for (i = 0; i < dma->buf_count; i++) {
852 struct drm_buf *buf = dma->buflist[i];
853 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
854 buf_priv->age = 0;
855 }
856 }
857
858 /* ================================================================
859 * CCE command submission
860 */
861
r128_wait_ring(drm_r128_private_t * dev_priv,int n)862 int r128_wait_ring(drm_r128_private_t * dev_priv, int n)
863 {
864 drm_r128_ring_buffer_t *ring = &dev_priv->ring;
865 int i;
866
867 for (i = 0; i < dev_priv->usec_timeout; i++) {
868 r128_update_ring_snapshot(dev_priv);
869 if (ring->space >= n)
870 return 0;
871 DRM_UDELAY(1);
872 }
873
874 /* FIXME: This is being ignored... */
875 DRM_ERROR("failed!\n");
876 return -EBUSY;
877 }
878
r128_cce_get_buffers(struct drm_device * dev,struct drm_file * file_priv,struct drm_dma * d)879 static int r128_cce_get_buffers(struct drm_device * dev,
880 struct drm_file *file_priv,
881 struct drm_dma * d)
882 {
883 int i;
884 struct drm_buf *buf;
885
886 for (i = d->granted_count; i < d->request_count; i++) {
887 buf = r128_freelist_get(dev);
888 if (!buf)
889 return -EAGAIN;
890
891 buf->file_priv = file_priv;
892
893 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
894 sizeof(buf->idx)))
895 return -EFAULT;
896 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
897 sizeof(buf->total)))
898 return -EFAULT;
899
900 d->granted_count++;
901 }
902 return 0;
903 }
904
r128_cce_buffers(struct drm_device * dev,void * data,struct drm_file * file_priv)905 int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
906 {
907 struct drm_device_dma *dma = dev->dma;
908 int ret = 0;
909 struct drm_dma *d = data;
910
911 LOCK_TEST_WITH_RETURN(dev, file_priv);
912
913 /* Please don't send us buffers.
914 */
915 if (d->send_count != 0) {
916 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
917 DRM_CURRENTPID, d->send_count);
918 return -EINVAL;
919 }
920
921 /* We'll send you buffers.
922 */
923 if (d->request_count < 0 || d->request_count > dma->buf_count) {
924 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
925 DRM_CURRENTPID, d->request_count, dma->buf_count);
926 return -EINVAL;
927 }
928
929 d->granted_count = 0;
930
931 if (d->request_count) {
932 ret = r128_cce_get_buffers(dev, file_priv, d);
933 }
934
935 return ret;
936 }
937