1 /* Target-dependent code for GDB, the GNU debugger. 2 3 Copyright (C) 2000-2024 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #ifndef PPC_TDEP_H 21 #define PPC_TDEP_H 22 23 #include "gdbarch.h" 24 25 struct gdbarch; 26 class frame_info_ptr; 27 struct value; 28 struct regcache; 29 struct type; 30 31 /* From ppc-sysv-tdep.c ... */ 32 enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch, 33 struct value *function, 34 struct type *valtype, 35 struct regcache *regcache, 36 gdb_byte *readbuf, 37 const gdb_byte *writebuf); 38 enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch, 39 struct value *function, 40 struct type *valtype, 41 struct regcache *regcache, 42 gdb_byte *readbuf, 43 const gdb_byte *writebuf); 44 45 CORE_ADDR ppc_sysv_abi_push_dummy_call 46 (struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, 47 CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, 48 function_call_return_method return_method, CORE_ADDR struct_addr); 49 50 CORE_ADDR ppc64_sysv_abi_push_dummy_call 51 (struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, 52 CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, 53 function_call_return_method return_method, CORE_ADDR struct_addr); 54 55 enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch, 56 struct value *function, 57 struct type *valtype, 58 struct regcache *regcache, 59 gdb_byte *readbuf, 60 const gdb_byte *writebuf); 61 62 /* From rs6000-tdep.c... */ 63 int altivec_register_p (struct gdbarch *gdbarch, int regno); 64 int vsx_register_p (struct gdbarch *gdbarch, int regno); 65 int spe_register_p (struct gdbarch *gdbarch, int regno); 66 67 /* Return non-zero if the architecture described by GDBARCH has 68 floating-point registers (f0 --- f31 and fpscr). */ 69 int ppc_floating_point_unit_p (struct gdbarch *gdbarch); 70 71 /* Return non-zero if the architecture described by GDBARCH has 72 Altivec registers (vr0 --- vr31, vrsave and vscr). */ 73 int ppc_altivec_support_p (struct gdbarch *gdbarch); 74 75 /* Return non-zero if the architecture described by GDBARCH has 76 VSX registers (vsr0 --- vsr63). */ 77 int vsx_support_p (struct gdbarch *gdbarch); 78 std::vector<CORE_ADDR> ppc_deal_with_atomic_sequence 79 (struct regcache *regcache); 80 81 82 /* Register set description. */ 83 84 struct ppc_reg_offsets 85 { 86 /* General-purpose registers. */ 87 int r0_offset; 88 int gpr_size; /* size for r0-31, pc, ps, lr, ctr. */ 89 int xr_size; /* size for cr, xer, mq. */ 90 int pc_offset; 91 int ps_offset; 92 int cr_offset; 93 int lr_offset; 94 int ctr_offset; 95 int xer_offset; 96 int mq_offset; 97 98 /* Floating-point registers. */ 99 int f0_offset; 100 int fpscr_offset; 101 int fpscr_size; 102 }; 103 104 extern void ppc_supply_reg (struct regcache *regcache, int regnum, 105 const gdb_byte *regs, size_t offset, int regsize); 106 107 extern void ppc_collect_reg (const struct regcache *regcache, int regnum, 108 gdb_byte *regs, size_t offset, int regsize); 109 110 /* Supply register REGNUM in the general-purpose register set REGSET 111 from the buffer specified by GREGS and LEN to register cache 112 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 113 114 extern void ppc_supply_gregset (const struct regset *regset, 115 struct regcache *regcache, 116 int regnum, const void *gregs, size_t len); 117 118 /* Supply register REGNUM in the floating-point register set REGSET 119 from the buffer specified by FPREGS and LEN to register cache 120 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 121 122 extern void ppc_supply_fpregset (const struct regset *regset, 123 struct regcache *regcache, 124 int regnum, const void *fpregs, size_t len); 125 126 /* Supply register REGNUM in the Altivec register set REGSET 127 from the buffer specified by VRREGS and LEN to register cache 128 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 129 130 extern void ppc_supply_vrregset (const struct regset *regset, 131 struct regcache *regcache, 132 int regnum, const void *vrregs, size_t len); 133 134 /* Supply register REGNUM in the VSX register set REGSET 135 from the buffer specified by VSXREGS and LEN to register cache 136 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 137 138 extern void ppc_supply_vsxregset (const struct regset *regset, 139 struct regcache *regcache, 140 int regnum, const void *vsxregs, size_t len); 141 142 /* Collect register REGNUM in the general-purpose register set 143 REGSET, from register cache REGCACHE into the buffer specified by 144 GREGS and LEN. If REGNUM is -1, do this for all registers in 145 REGSET. */ 146 147 extern void ppc_collect_gregset (const struct regset *regset, 148 const struct regcache *regcache, 149 int regnum, void *gregs, size_t len); 150 151 /* Collect register REGNUM in the floating-point register set 152 REGSET, from register cache REGCACHE into the buffer specified by 153 FPREGS and LEN. If REGNUM is -1, do this for all registers in 154 REGSET. */ 155 156 extern void ppc_collect_fpregset (const struct regset *regset, 157 const struct regcache *regcache, 158 int regnum, void *fpregs, size_t len); 159 160 /* Collect register REGNUM in the Altivec register set 161 REGSET from register cache REGCACHE into the buffer specified by 162 VRREGS and LEN. If REGNUM is -1, do this for all registers in 163 REGSET. */ 164 165 extern void ppc_collect_vrregset (const struct regset *regset, 166 const struct regcache *regcache, 167 int regnum, void *vrregs, size_t len); 168 169 /* Collect register REGNUM in the VSX register set 170 REGSET from register cache REGCACHE into the buffer specified by 171 VSXREGS and LEN. If REGNUM is -1, do this for all registers in 172 REGSET. */ 173 174 extern void ppc_collect_vsxregset (const struct regset *regset, 175 const struct regcache *regcache, 176 int regnum, void *vsxregs, size_t len); 177 178 /* Implementation of the gdbarch get_return_buf_addr hook. */ 179 180 extern CORE_ADDR ppc_sysv_get_return_buf_addr (type*, const frame_info_ptr &); 181 182 /* Private data that this module attaches to struct gdbarch. */ 183 184 /* ELF ABI version used by the inferior. */ 185 enum powerpc_elf_abi 186 { 187 POWERPC_ELF_AUTO, 188 POWERPC_ELF_V1, 189 POWERPC_ELF_V2, 190 POWERPC_ELF_LAST 191 }; 192 193 /* Vector ABI used by the inferior. */ 194 enum powerpc_vector_abi 195 { 196 POWERPC_VEC_AUTO, 197 POWERPC_VEC_GENERIC, 198 POWERPC_VEC_ALTIVEC, 199 POWERPC_VEC_SPE, 200 POWERPC_VEC_LAST 201 }; 202 203 /* long double ABI version used by the inferior. */ 204 enum powerpc_long_double_abi 205 { 206 POWERPC_LONG_DOUBLE_AUTO, 207 POWERPC_LONG_DOUBLE_IBM128, 208 POWERPC_LONG_DOUBLE_IEEE128, 209 POWERPC_LONG_DOUBLE_LAST 210 }; 211 212 struct ppc_gdbarch_tdep : gdbarch_tdep_base 213 { 214 int wordsize = 0; /* Size in bytes of fixed-point word. */ 215 int soft_float = 0; /* Avoid FP registers for arguments? */ 216 217 enum powerpc_elf_abi elf_abi {}; /* ELF ABI version. */ 218 219 /* Format to use for the "long double" data type. */ 220 enum powerpc_long_double_abi long_double_abi {}; 221 222 /* How to pass vector arguments. Never set to AUTO or LAST. */ 223 enum powerpc_vector_abi vector_abi {}; 224 225 int ppc_gp0_regnum = 0; /* GPR register 0 */ 226 int ppc_toc_regnum = 0; /* TOC register */ 227 int ppc_ps_regnum = 0; /* Processor (or machine) status (%msr) */ 228 int ppc_cr_regnum = 0; /* Condition register */ 229 int ppc_lr_regnum = 0; /* Link register */ 230 int ppc_ctr_regnum = 0; /* Count register */ 231 int ppc_xer_regnum = 0; /* Integer exception register */ 232 233 /* Not all PPC and RS6000 variants will have the registers 234 represented below. A -1 is used to indicate that the register 235 is not present in this variant. */ 236 237 /* Floating-point registers. */ 238 int ppc_fp0_regnum = 0; /* Floating-point register 0. */ 239 int ppc_fpscr_regnum = 0; /* fp status and condition register. */ 240 241 /* Multiplier-Quotient Register (older POWER architectures only). */ 242 int ppc_mq_regnum = 0; 243 244 /* POWER7 VSX registers. */ 245 int ppc_vsr0_regnum = 0; /* First VSX register. */ 246 int ppc_vsr0_upper_regnum = 0; /* First right most dword vsx register. */ 247 int ppc_efpr0_regnum = 0; /* First Extended FP register. */ 248 249 /* Altivec registers. */ 250 int ppc_vr0_regnum = 0; /* First AltiVec register. */ 251 int ppc_vrsave_regnum = 0; /* Last AltiVec register. */ 252 253 /* Altivec pseudo-register vX aliases for the raw vrX 254 registers. */ 255 int ppc_v0_alias_regnum = 0; 256 257 /* SPE registers. */ 258 int ppc_ev0_upper_regnum = 0; /* First GPR upper half register. */ 259 int ppc_ev0_regnum = 0; /* First ev register. */ 260 int ppc_acc_regnum = 0; /* SPE 'acc' register. */ 261 int ppc_spefscr_regnum = 0; /* SPE 'spefscr' register. */ 262 263 /* Program Priority Register. */ 264 int ppc_ppr_regnum = 0; 265 266 /* Data Stream Control Register. */ 267 int ppc_dscr_regnum = 0; 268 269 /* Target Address Register. */ 270 int ppc_tar_regnum = 0; 271 272 /* Decimal 128 registers. */ 273 int ppc_dl0_regnum = 0; /* First Decimal128 argument register pair. */ 274 275 int have_ebb = 0; 276 277 /* PMU registers. */ 278 int ppc_mmcr0_regnum = 0; 279 int ppc_mmcr2_regnum = 0; 280 int ppc_siar_regnum = 0; 281 int ppc_sdar_regnum = 0; 282 int ppc_sier_regnum = 0; 283 284 /* Hardware Transactional Memory registers. */ 285 int have_htm_spr = 0; 286 int have_htm_core = 0; 287 int have_htm_fpu = 0; 288 int have_htm_altivec = 0; 289 int have_htm_vsx = 0; 290 int ppc_cppr_regnum = 0; 291 int ppc_cdscr_regnum = 0; 292 int ppc_ctar_regnum = 0; 293 294 /* HTM pseudo registers. */ 295 int ppc_cdl0_regnum = 0; 296 int ppc_cvsr0_regnum = 0; 297 int ppc_cefpr0_regnum = 0; 298 299 /* Offset to ABI specific location where link register is saved. */ 300 int lr_frame_offset = 0; 301 302 /* An array of integers, such that sim_regno[I] is the simulator 303 register number for GDB register number I, or -1 if the 304 simulator does not implement that register. */ 305 int *sim_regno = nullptr; 306 307 /* ISA-specific types. */ 308 struct type *ppc_builtin_type_vec64 = nullptr; 309 struct type *ppc_builtin_type_vec128 = nullptr; 310 311 int (*ppc_syscall_record) (struct regcache *regcache) = nullptr; 312 }; 313 314 315 /* Constants for register set sizes. */ 316 enum 317 { 318 ppc_num_gprs = 32, /* 32 general-purpose registers. */ 319 ppc_num_fprs = 32, /* 32 floating-point registers. */ 320 ppc_num_srs = 16, /* 16 segment registers. */ 321 ppc_num_vrs = 32, /* 32 Altivec vector registers. */ 322 ppc_num_vshrs = 32, /* 32 doublewords (dword 1 of vs0~vs31). */ 323 ppc_num_vsrs = 64, /* 64 VSX vector registers. */ 324 ppc_num_efprs = 32 /* 32 Extended FP registers. */ 325 }; 326 327 328 /* Register number constants. These are GDB internal register 329 numbers; they are not used for the simulator or remote targets. 330 Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given 331 numbers above PPC_NUM_REGS. So are segment registers and other 332 target-defined registers. */ 333 enum { 334 PPC_R0_REGNUM = 0, 335 PPC_F0_REGNUM = 32, 336 PPC_PC_REGNUM = 64, 337 PPC_MSR_REGNUM = 65, 338 PPC_CR_REGNUM = 66, 339 PPC_LR_REGNUM = 67, 340 PPC_CTR_REGNUM = 68, 341 PPC_XER_REGNUM = 69, 342 PPC_FPSCR_REGNUM = 70, 343 PPC_MQ_REGNUM = 71, 344 PPC_SPE_UPPER_GP0_REGNUM = 72, 345 PPC_SPE_ACC_REGNUM = 104, 346 PPC_SPE_FSCR_REGNUM = 105, 347 PPC_VR0_REGNUM = 106, 348 PPC_VSCR_REGNUM = 138, 349 PPC_VRSAVE_REGNUM = 139, 350 PPC_VSR0_UPPER_REGNUM = 140, 351 PPC_VSR31_UPPER_REGNUM = 171, 352 PPC_PPR_REGNUM = 172, 353 PPC_DSCR_REGNUM = 173, 354 PPC_TAR_REGNUM = 174, 355 356 /* EBB registers. */ 357 PPC_BESCR_REGNUM = 175, 358 PPC_EBBHR_REGNUM = 176, 359 PPC_EBBRR_REGNUM = 177, 360 361 /* PMU registers. */ 362 PPC_MMCR0_REGNUM = 178, 363 PPC_MMCR2_REGNUM = 179, 364 PPC_SIAR_REGNUM = 180, 365 PPC_SDAR_REGNUM = 181, 366 PPC_SIER_REGNUM = 182, 367 368 /* Hardware transactional memory registers. */ 369 PPC_TFHAR_REGNUM = 183, 370 PPC_TEXASR_REGNUM = 184, 371 PPC_TFIAR_REGNUM = 185, 372 373 PPC_CR0_REGNUM = 186, 374 PPC_CCR_REGNUM = 218, 375 PPC_CXER_REGNUM = 219, 376 PPC_CLR_REGNUM = 220, 377 PPC_CCTR_REGNUM = 221, 378 379 PPC_CF0_REGNUM = 222, 380 PPC_CFPSCR_REGNUM = 254, 381 382 PPC_CVR0_REGNUM = 255, 383 PPC_CVSCR_REGNUM = 287, 384 PPC_CVRSAVE_REGNUM = 288, 385 386 PPC_CVSR0_UPPER_REGNUM = 289, 387 388 PPC_CPPR_REGNUM = 321, 389 PPC_CDSCR_REGNUM = 322, 390 PPC_CTAR_REGNUM = 323, 391 PPC_NUM_REGS 392 }; 393 394 /* Big enough to hold the size of the largest register in bytes. */ 395 #define PPC_MAX_REGISTER_SIZE 64 396 397 #define PPC_IS_EBB_REGNUM(i) \ 398 ((i) >= PPC_BESCR_REGNUM && (i) <= PPC_EBBRR_REGNUM) 399 400 #define PPC_IS_PMU_REGNUM(i) \ 401 ((i) >= PPC_MMCR0_REGNUM && (i) <= PPC_SIER_REGNUM) 402 403 #define PPC_IS_TMSPR_REGNUM(i) \ 404 ((i) >= PPC_TFHAR_REGNUM && (i) <= PPC_TFIAR_REGNUM) 405 406 #define PPC_IS_CKPTGP_REGNUM(i) \ 407 ((i) >= PPC_CR0_REGNUM && (i) <= PPC_CCTR_REGNUM) 408 409 #define PPC_IS_CKPTFP_REGNUM(i) \ 410 ((i) >= PPC_CF0_REGNUM && (i) <= PPC_CFPSCR_REGNUM) 411 412 #define PPC_IS_CKPTVMX_REGNUM(i) \ 413 ((i) >= PPC_CVR0_REGNUM && (i) <= PPC_CVRSAVE_REGNUM) 414 415 #define PPC_IS_CKPTVSX_REGNUM(i) \ 416 ((i) >= PPC_CVSR0_UPPER_REGNUM && (i) < (PPC_CVSR0_UPPER_REGNUM + 32)) 417 418 /* An instruction to match. */ 419 420 struct ppc_insn_pattern 421 { 422 unsigned int mask; /* mask the insn with this... */ 423 unsigned int data; /* ...and see if it matches this. */ 424 int optional; /* If non-zero, this insn may be absent. */ 425 }; 426 427 extern int ppc_insns_match_pattern (const frame_info_ptr &frame, CORE_ADDR pc, 428 const struct ppc_insn_pattern *pattern, 429 unsigned int *insns); 430 extern CORE_ADDR ppc_insn_d_field (unsigned int insn); 431 432 extern CORE_ADDR ppc_insn_ds_field (unsigned int insn); 433 extern CORE_ADDR ppc_insn_prefix_dform (unsigned int insn1, 434 unsigned int insn2); 435 436 extern int ppc_process_record (struct gdbarch *gdbarch, 437 struct regcache *regcache, CORE_ADDR addr); 438 439 /* Instruction size. */ 440 #define PPC_INSN_SIZE 4 441 442 /* Estimate for the maximum number of instructions in a function epilogue. */ 443 #define PPC_MAX_EPILOGUE_INSTRUCTIONS 52 444 445 struct ppc_inferior_data 446 { 447 /* This is an optional in case we add more fields to ppc_inferior_data, we 448 don't want it instantiated as soon as we get the ppc_inferior_data for an 449 inferior. */ 450 std::optional<displaced_step_buffers> disp_step_buf; 451 }; 452 453 extern ppc_inferior_data * get_ppc_per_inferior (inferior *inf); 454 455 extern const struct target_desc *tdesc_powerpc_vsx64l; 456 extern const struct target_desc *tdesc_powerpc_vsx64; 457 extern const struct target_desc *tdesc_powerpc_vsx32; 458 extern const struct target_desc *tdesc_powerpc_altivec64; 459 extern const struct target_desc *tdesc_powerpc_altivec32; 460 461 #endif /* ppc-tdep.h */ 462