1 /*
2 * Copyright (c) 2017-2018 Cavium, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 /*
29 * File: qlnx_os.c
30 * Author : David C Somayajulu, Cavium, Inc., San Jose, CA 95131.
31 */
32
33 #include <sys/cdefs.h>
34 #include "qlnx_os.h"
35 #include "bcm_osal.h"
36 #include "reg_addr.h"
37 #include "ecore_gtt_reg_addr.h"
38 #include "ecore.h"
39 #include "ecore_chain.h"
40 #include "ecore_status.h"
41 #include "ecore_hw.h"
42 #include "ecore_rt_defs.h"
43 #include "ecore_init_ops.h"
44 #include "ecore_int.h"
45 #include "ecore_cxt.h"
46 #include "ecore_spq.h"
47 #include "ecore_init_fw_funcs.h"
48 #include "ecore_sp_commands.h"
49 #include "ecore_dev_api.h"
50 #include "ecore_l2_api.h"
51 #include "ecore_mcp.h"
52 #include "ecore_hw_defs.h"
53 #include "mcp_public.h"
54 #include "ecore_iro.h"
55 #include "nvm_cfg.h"
56 #include "ecore_dev_api.h"
57 #include "ecore_dbg_fw_funcs.h"
58 #include "ecore_iov_api.h"
59 #include "ecore_vf_api.h"
60
61 #include "qlnx_ioctl.h"
62 #include "qlnx_def.h"
63 #include "qlnx_ver.h"
64
65 #ifdef QLNX_ENABLE_IWARP
66 #include "qlnx_rdma.h"
67 #endif /* #ifdef QLNX_ENABLE_IWARP */
68
69 #include <sys/smp.h>
70
71 /*
72 * static functions
73 */
74 /*
75 * ioctl related functions
76 */
77 static void qlnx_add_sysctls(qlnx_host_t *ha);
78
79 /*
80 * main driver
81 */
82 static void qlnx_release(qlnx_host_t *ha);
83 static void qlnx_fp_isr(void *arg);
84 static void qlnx_init_ifnet(device_t dev, qlnx_host_t *ha);
85 static void qlnx_init(void *arg);
86 static void qlnx_init_locked(qlnx_host_t *ha);
87 static int qlnx_set_multi(qlnx_host_t *ha, uint32_t add_multi);
88 static int qlnx_set_promisc(qlnx_host_t *ha);
89 static int qlnx_set_allmulti(qlnx_host_t *ha);
90 static int qlnx_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
91 static int qlnx_media_change(struct ifnet *ifp);
92 static void qlnx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr);
93 static void qlnx_stop(qlnx_host_t *ha);
94 static int qlnx_send(qlnx_host_t *ha, struct qlnx_fastpath *fp,
95 struct mbuf **m_headp);
96 static int qlnx_get_ifq_snd_maxlen(qlnx_host_t *ha);
97 static uint32_t qlnx_get_optics(qlnx_host_t *ha,
98 struct qlnx_link_output *if_link);
99 static int qlnx_transmit(struct ifnet *ifp, struct mbuf *mp);
100 static int qlnx_transmit_locked(struct ifnet *ifp, struct qlnx_fastpath *fp,
101 struct mbuf *mp);
102 static void qlnx_qflush(struct ifnet *ifp);
103
104 static int qlnx_alloc_parent_dma_tag(qlnx_host_t *ha);
105 static void qlnx_free_parent_dma_tag(qlnx_host_t *ha);
106 static int qlnx_alloc_tx_dma_tag(qlnx_host_t *ha);
107 static void qlnx_free_tx_dma_tag(qlnx_host_t *ha);
108 static int qlnx_alloc_rx_dma_tag(qlnx_host_t *ha);
109 static void qlnx_free_rx_dma_tag(qlnx_host_t *ha);
110
111 static int qlnx_get_mfw_version(qlnx_host_t *ha, uint32_t *mfw_ver);
112 static int qlnx_get_flash_size(qlnx_host_t *ha, uint32_t *flash_size);
113
114 static int qlnx_nic_setup(struct ecore_dev *cdev,
115 struct ecore_pf_params *func_params);
116 static int qlnx_nic_start(struct ecore_dev *cdev);
117 static int qlnx_slowpath_start(qlnx_host_t *ha);
118 static int qlnx_slowpath_stop(qlnx_host_t *ha);
119 static int qlnx_init_hw(qlnx_host_t *ha);
120 static void qlnx_set_id(struct ecore_dev *cdev, char name[NAME_SIZE],
121 char ver_str[VER_SIZE]);
122 static void qlnx_unload(qlnx_host_t *ha);
123 static int qlnx_load(qlnx_host_t *ha);
124 static void qlnx_hw_set_multi(qlnx_host_t *ha, uint8_t *mta, uint32_t mcnt,
125 uint32_t add_mac);
126 static void qlnx_dump_buf8(qlnx_host_t *ha, const char *msg, void *dbuf,
127 uint32_t len);
128 static int qlnx_alloc_rx_buffer(qlnx_host_t *ha, struct qlnx_rx_queue *rxq);
129 static void qlnx_reuse_rx_data(struct qlnx_rx_queue *rxq);
130 static void qlnx_update_rx_prod(struct ecore_hwfn *p_hwfn,
131 struct qlnx_rx_queue *rxq);
132 static int qlnx_set_rx_accept_filter(qlnx_host_t *ha, uint8_t filter);
133 static int qlnx_grc_dumpsize(qlnx_host_t *ha, uint32_t *num_dwords,
134 int hwfn_index);
135 static int qlnx_idle_chk_size(qlnx_host_t *ha, uint32_t *num_dwords,
136 int hwfn_index);
137 static void qlnx_timer(void *arg);
138 static int qlnx_alloc_tx_br(qlnx_host_t *ha, struct qlnx_fastpath *fp);
139 static void qlnx_free_tx_br(qlnx_host_t *ha, struct qlnx_fastpath *fp);
140 static void qlnx_trigger_dump(qlnx_host_t *ha);
141 static uint16_t qlnx_num_tx_compl(qlnx_host_t *ha, struct qlnx_fastpath *fp,
142 struct qlnx_tx_queue *txq);
143 static void qlnx_tx_int(qlnx_host_t *ha, struct qlnx_fastpath *fp,
144 struct qlnx_tx_queue *txq);
145 static int qlnx_rx_int(qlnx_host_t *ha, struct qlnx_fastpath *fp, int budget,
146 int lro_enable);
147 static void qlnx_fp_taskqueue(void *context, int pending);
148 static void qlnx_sample_storm_stats(qlnx_host_t *ha);
149 static int qlnx_alloc_tpa_mbuf(qlnx_host_t *ha, uint16_t rx_buf_size,
150 struct qlnx_agg_info *tpa);
151 static void qlnx_free_tpa_mbuf(qlnx_host_t *ha, struct qlnx_agg_info *tpa);
152
153 #if __FreeBSD_version >= 1100000
154 static uint64_t qlnx_get_counter(if_t ifp, ift_counter cnt);
155 #endif
156
157 /*
158 * Hooks to the Operating Systems
159 */
160 static int qlnx_pci_probe (device_t);
161 static int qlnx_pci_attach (device_t);
162 static int qlnx_pci_detach (device_t);
163
164 #ifndef QLNX_VF
165
166 #ifdef CONFIG_ECORE_SRIOV
167
168 static int qlnx_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params);
169 static void qlnx_iov_uninit(device_t dev);
170 static int qlnx_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params);
171 static void qlnx_initialize_sriov(qlnx_host_t *ha);
172 static void qlnx_pf_taskqueue(void *context, int pending);
173 static int qlnx_create_pf_taskqueues(qlnx_host_t *ha);
174 static void qlnx_destroy_pf_taskqueues(qlnx_host_t *ha);
175 static void qlnx_inform_vf_link_state(struct ecore_hwfn *p_hwfn, qlnx_host_t *ha);
176
177 #endif /* #ifdef CONFIG_ECORE_SRIOV */
178
179 static device_method_t qlnx_pci_methods[] = {
180 /* Device interface */
181 DEVMETHOD(device_probe, qlnx_pci_probe),
182 DEVMETHOD(device_attach, qlnx_pci_attach),
183 DEVMETHOD(device_detach, qlnx_pci_detach),
184
185 #ifdef CONFIG_ECORE_SRIOV
186 DEVMETHOD(pci_iov_init, qlnx_iov_init),
187 DEVMETHOD(pci_iov_uninit, qlnx_iov_uninit),
188 DEVMETHOD(pci_iov_add_vf, qlnx_iov_add_vf),
189 #endif /* #ifdef CONFIG_ECORE_SRIOV */
190 { 0, 0 }
191 };
192
193 static driver_t qlnx_pci_driver = {
194 "ql", qlnx_pci_methods, sizeof (qlnx_host_t),
195 };
196
197 static devclass_t qlnx_devclass;
198
199 MODULE_VERSION(if_qlnxe,1);
200 DRIVER_MODULE(if_qlnxe, pci, qlnx_pci_driver, qlnx_devclass, 0, 0);
201
202 MODULE_DEPEND(if_qlnxe, pci, 1, 1, 1);
203 MODULE_DEPEND(if_qlnxe, ether, 1, 1, 1);
204
205 #else
206
207 static device_method_t qlnxv_pci_methods[] = {
208 /* Device interface */
209 DEVMETHOD(device_probe, qlnx_pci_probe),
210 DEVMETHOD(device_attach, qlnx_pci_attach),
211 DEVMETHOD(device_detach, qlnx_pci_detach),
212 { 0, 0 }
213 };
214
215 static driver_t qlnxv_pci_driver = {
216 "ql", qlnxv_pci_methods, sizeof (qlnx_host_t),
217 };
218
219 static devclass_t qlnxv_devclass;
220 MODULE_VERSION(if_qlnxev,1);
221 DRIVER_MODULE(if_qlnxev, pci, qlnxv_pci_driver, qlnxv_devclass, 0, 0);
222
223 MODULE_DEPEND(if_qlnxev, pci, 1, 1, 1);
224 MODULE_DEPEND(if_qlnxev, ether, 1, 1, 1);
225
226 #endif /* #ifdef QLNX_VF */
227
228 MALLOC_DEFINE(M_QLNXBUF, "qlnxbuf", "Buffers for qlnx driver");
229
230 char qlnx_dev_str[128];
231 char qlnx_ver_str[VER_SIZE];
232 char qlnx_name_str[NAME_SIZE];
233
234 /*
235 * Some PCI Configuration Space Related Defines
236 */
237
238 #ifndef PCI_VENDOR_QLOGIC
239 #define PCI_VENDOR_QLOGIC 0x1077
240 #endif
241
242 /* 40G Adapter QLE45xxx*/
243 #ifndef QLOGIC_PCI_DEVICE_ID_1634
244 #define QLOGIC_PCI_DEVICE_ID_1634 0x1634
245 #endif
246
247 /* 100G Adapter QLE45xxx*/
248 #ifndef QLOGIC_PCI_DEVICE_ID_1644
249 #define QLOGIC_PCI_DEVICE_ID_1644 0x1644
250 #endif
251
252 /* 25G Adapter QLE45xxx*/
253 #ifndef QLOGIC_PCI_DEVICE_ID_1656
254 #define QLOGIC_PCI_DEVICE_ID_1656 0x1656
255 #endif
256
257 /* 50G Adapter QLE45xxx*/
258 #ifndef QLOGIC_PCI_DEVICE_ID_1654
259 #define QLOGIC_PCI_DEVICE_ID_1654 0x1654
260 #endif
261
262 /* 10G/25G/40G Adapter QLE41xxx*/
263 #ifndef QLOGIC_PCI_DEVICE_ID_8070
264 #define QLOGIC_PCI_DEVICE_ID_8070 0x8070
265 #endif
266
267 /* SRIOV Device (All Speeds) Adapter QLE41xxx*/
268 #ifndef QLOGIC_PCI_DEVICE_ID_8090
269 #define QLOGIC_PCI_DEVICE_ID_8090 0x8090
270 #endif
271
272 SYSCTL_NODE(_hw, OID_AUTO, qlnxe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
273 "qlnxe driver parameters");
274
275 /* Number of Queues: 0 (Auto) or 1 to 32 (fixed queue number) */
276 static int qlnxe_queue_count = QLNX_DEFAULT_RSS;
277
278 #if __FreeBSD_version < 1100000
279
280 TUNABLE_INT("hw.qlnxe.queue_count", &qlnxe_queue_count);
281
282 #endif
283
284 SYSCTL_INT(_hw_qlnxe, OID_AUTO, queue_count, CTLFLAG_RDTUN,
285 &qlnxe_queue_count, 0, "Multi-Queue queue count");
286
287 /*
288 * Note on RDMA personality setting
289 *
290 * Read the personality configured in NVRAM
291 * If the personality is ETH_ONLY, ETH_IWARP or ETH_ROCE and
292 * the configured personality in sysctl is QLNX_PERSONALITY_DEFAULT
293 * use the personality in NVRAM.
294
295 * Otherwise use t the personality configured in sysctl.
296 *
297 */
298 #define QLNX_PERSONALITY_DEFAULT 0x0 /* use personality in NVRAM */
299 #define QLNX_PERSONALITY_ETH_ONLY 0x1 /* Override with ETH_ONLY */
300 #define QLNX_PERSONALITY_ETH_IWARP 0x2 /* Override with ETH_IWARP */
301 #define QLNX_PERSONALITY_ETH_ROCE 0x3 /* Override with ETH_ROCE */
302 #define QLNX_PERSONALITY_BITS_PER_FUNC 4
303 #define QLNX_PERSONALIY_MASK 0xF
304
305 /* RDMA configuration; 64bit field allows setting for 16 physical functions*/
306 static uint64_t qlnxe_rdma_configuration = 0x22222222;
307
308 #if __FreeBSD_version < 1100000
309
310 TUNABLE_QUAD("hw.qlnxe.rdma_configuration", &qlnxe_rdma_configuration);
311
312 SYSCTL_UQUAD(_hw_qlnxe, OID_AUTO, rdma_configuration, CTLFLAG_RDTUN,
313 &qlnxe_rdma_configuration, 0, "RDMA Configuration");
314
315 #else
316
317 SYSCTL_U64(_hw_qlnxe, OID_AUTO, rdma_configuration, CTLFLAG_RDTUN,
318 &qlnxe_rdma_configuration, 0, "RDMA Configuration");
319
320 #endif /* #if __FreeBSD_version < 1100000 */
321
322 int
qlnx_vf_device(qlnx_host_t * ha)323 qlnx_vf_device(qlnx_host_t *ha)
324 {
325 uint16_t device_id;
326
327 device_id = ha->device_id;
328
329 if (device_id == QLOGIC_PCI_DEVICE_ID_8090)
330 return 0;
331
332 return -1;
333 }
334
335 static int
qlnx_valid_device(qlnx_host_t * ha)336 qlnx_valid_device(qlnx_host_t *ha)
337 {
338 uint16_t device_id;
339
340 device_id = ha->device_id;
341
342 #ifndef QLNX_VF
343 if ((device_id == QLOGIC_PCI_DEVICE_ID_1634) ||
344 (device_id == QLOGIC_PCI_DEVICE_ID_1644) ||
345 (device_id == QLOGIC_PCI_DEVICE_ID_1656) ||
346 (device_id == QLOGIC_PCI_DEVICE_ID_1654) ||
347 (device_id == QLOGIC_PCI_DEVICE_ID_8070))
348 return 0;
349 #else
350 if (device_id == QLOGIC_PCI_DEVICE_ID_8090)
351 return 0;
352
353 #endif /* #ifndef QLNX_VF */
354 return -1;
355 }
356
357 #ifdef QLNX_ENABLE_IWARP
358 static int
qlnx_rdma_supported(struct qlnx_host * ha)359 qlnx_rdma_supported(struct qlnx_host *ha)
360 {
361 uint16_t device_id;
362
363 device_id = pci_get_device(ha->pci_dev);
364
365 if ((device_id == QLOGIC_PCI_DEVICE_ID_1634) ||
366 (device_id == QLOGIC_PCI_DEVICE_ID_1656) ||
367 (device_id == QLOGIC_PCI_DEVICE_ID_1654) ||
368 (device_id == QLOGIC_PCI_DEVICE_ID_8070))
369 return (0);
370
371 return (-1);
372 }
373 #endif /* #ifdef QLNX_ENABLE_IWARP */
374
375 /*
376 * Name: qlnx_pci_probe
377 * Function: Validate the PCI device to be a QLA80XX device
378 */
379 static int
qlnx_pci_probe(device_t dev)380 qlnx_pci_probe(device_t dev)
381 {
382 snprintf(qlnx_ver_str, sizeof(qlnx_ver_str), "v%d.%d.%d",
383 QLNX_VERSION_MAJOR, QLNX_VERSION_MINOR, QLNX_VERSION_BUILD);
384 snprintf(qlnx_name_str, sizeof(qlnx_name_str), "qlnx");
385
386 if (pci_get_vendor(dev) != PCI_VENDOR_QLOGIC) {
387 return (ENXIO);
388 }
389
390 switch (pci_get_device(dev)) {
391 #ifndef QLNX_VF
392
393 case QLOGIC_PCI_DEVICE_ID_1644:
394 snprintf(qlnx_dev_str, sizeof(qlnx_dev_str), "%s v%d.%d.%d",
395 "Qlogic 100GbE PCI CNA Adapter-Ethernet Function",
396 QLNX_VERSION_MAJOR, QLNX_VERSION_MINOR,
397 QLNX_VERSION_BUILD);
398 device_set_desc_copy(dev, qlnx_dev_str);
399
400 break;
401
402 case QLOGIC_PCI_DEVICE_ID_1634:
403 snprintf(qlnx_dev_str, sizeof(qlnx_dev_str), "%s v%d.%d.%d",
404 "Qlogic 40GbE PCI CNA Adapter-Ethernet Function",
405 QLNX_VERSION_MAJOR, QLNX_VERSION_MINOR,
406 QLNX_VERSION_BUILD);
407 device_set_desc_copy(dev, qlnx_dev_str);
408
409 break;
410
411 case QLOGIC_PCI_DEVICE_ID_1656:
412 snprintf(qlnx_dev_str, sizeof(qlnx_dev_str), "%s v%d.%d.%d",
413 "Qlogic 25GbE PCI CNA Adapter-Ethernet Function",
414 QLNX_VERSION_MAJOR, QLNX_VERSION_MINOR,
415 QLNX_VERSION_BUILD);
416 device_set_desc_copy(dev, qlnx_dev_str);
417
418 break;
419
420 case QLOGIC_PCI_DEVICE_ID_1654:
421 snprintf(qlnx_dev_str, sizeof(qlnx_dev_str), "%s v%d.%d.%d",
422 "Qlogic 50GbE PCI CNA Adapter-Ethernet Function",
423 QLNX_VERSION_MAJOR, QLNX_VERSION_MINOR,
424 QLNX_VERSION_BUILD);
425 device_set_desc_copy(dev, qlnx_dev_str);
426
427 break;
428
429 case QLOGIC_PCI_DEVICE_ID_8070:
430 snprintf(qlnx_dev_str, sizeof(qlnx_dev_str), "%s v%d.%d.%d",
431 "Qlogic 10GbE/25GbE/40GbE PCI CNA (AH)"
432 " Adapter-Ethernet Function",
433 QLNX_VERSION_MAJOR, QLNX_VERSION_MINOR,
434 QLNX_VERSION_BUILD);
435 device_set_desc_copy(dev, qlnx_dev_str);
436
437 break;
438
439 #else
440 case QLOGIC_PCI_DEVICE_ID_8090:
441 snprintf(qlnx_dev_str, sizeof(qlnx_dev_str), "%s v%d.%d.%d",
442 "Qlogic SRIOV PCI CNA (AH) "
443 "Adapter-Ethernet Function",
444 QLNX_VERSION_MAJOR, QLNX_VERSION_MINOR,
445 QLNX_VERSION_BUILD);
446 device_set_desc_copy(dev, qlnx_dev_str);
447
448 break;
449
450 #endif /* #ifndef QLNX_VF */
451
452 default:
453 return (ENXIO);
454 }
455
456 #ifdef QLNX_ENABLE_IWARP
457 qlnx_rdma_init();
458 #endif /* #ifdef QLNX_ENABLE_IWARP */
459
460 return (BUS_PROBE_DEFAULT);
461 }
462
463 static uint16_t
qlnx_num_tx_compl(qlnx_host_t * ha,struct qlnx_fastpath * fp,struct qlnx_tx_queue * txq)464 qlnx_num_tx_compl(qlnx_host_t *ha, struct qlnx_fastpath *fp,
465 struct qlnx_tx_queue *txq)
466 {
467 u16 hw_bd_cons;
468 u16 ecore_cons_idx;
469 uint16_t diff;
470
471 hw_bd_cons = le16toh(*txq->hw_cons_ptr);
472
473 ecore_cons_idx = ecore_chain_get_cons_idx(&txq->tx_pbl);
474 if (hw_bd_cons < ecore_cons_idx) {
475 diff = (1 << 16) - (ecore_cons_idx - hw_bd_cons);
476 } else {
477 diff = hw_bd_cons - ecore_cons_idx;
478 }
479 return diff;
480 }
481
482 static void
qlnx_sp_intr(void * arg)483 qlnx_sp_intr(void *arg)
484 {
485 struct ecore_hwfn *p_hwfn;
486 qlnx_host_t *ha;
487 int i;
488
489 p_hwfn = arg;
490
491 if (p_hwfn == NULL) {
492 printf("%s: spurious slowpath intr\n", __func__);
493 return;
494 }
495
496 ha = (qlnx_host_t *)p_hwfn->p_dev;
497
498 QL_DPRINT2(ha, "enter\n");
499
500 for (i = 0; i < ha->cdev.num_hwfns; i++) {
501 if (&ha->cdev.hwfns[i] == p_hwfn) {
502 taskqueue_enqueue(ha->sp_taskqueue[i], &ha->sp_task[i]);
503 break;
504 }
505 }
506 QL_DPRINT2(ha, "exit\n");
507
508 return;
509 }
510
511 static void
qlnx_sp_taskqueue(void * context,int pending)512 qlnx_sp_taskqueue(void *context, int pending)
513 {
514 struct ecore_hwfn *p_hwfn;
515
516 p_hwfn = context;
517
518 if (p_hwfn != NULL) {
519 qlnx_sp_isr(p_hwfn);
520 }
521 return;
522 }
523
524 static int
qlnx_create_sp_taskqueues(qlnx_host_t * ha)525 qlnx_create_sp_taskqueues(qlnx_host_t *ha)
526 {
527 int i;
528 uint8_t tq_name[32];
529
530 for (i = 0; i < ha->cdev.num_hwfns; i++) {
531 struct ecore_hwfn *p_hwfn = &ha->cdev.hwfns[i];
532
533 bzero(tq_name, sizeof (tq_name));
534 snprintf(tq_name, sizeof (tq_name), "ql_sp_tq_%d", i);
535
536 TASK_INIT(&ha->sp_task[i], 0, qlnx_sp_taskqueue, p_hwfn);
537
538 ha->sp_taskqueue[i] = taskqueue_create(tq_name, M_NOWAIT,
539 taskqueue_thread_enqueue, &ha->sp_taskqueue[i]);
540
541 if (ha->sp_taskqueue[i] == NULL)
542 return (-1);
543
544 taskqueue_start_threads(&ha->sp_taskqueue[i], 1, PI_NET, "%s",
545 tq_name);
546
547 QL_DPRINT1(ha, "%p\n", ha->sp_taskqueue[i]);
548 }
549
550 return (0);
551 }
552
553 static void
qlnx_destroy_sp_taskqueues(qlnx_host_t * ha)554 qlnx_destroy_sp_taskqueues(qlnx_host_t *ha)
555 {
556 int i;
557
558 for (i = 0; i < ha->cdev.num_hwfns; i++) {
559 if (ha->sp_taskqueue[i] != NULL) {
560 taskqueue_drain(ha->sp_taskqueue[i], &ha->sp_task[i]);
561 taskqueue_free(ha->sp_taskqueue[i]);
562 }
563 }
564 return;
565 }
566
567 static void
qlnx_fp_taskqueue(void * context,int pending)568 qlnx_fp_taskqueue(void *context, int pending)
569 {
570 struct qlnx_fastpath *fp;
571 qlnx_host_t *ha;
572 struct ifnet *ifp;
573
574 fp = context;
575
576 if (fp == NULL)
577 return;
578
579 ha = (qlnx_host_t *)fp->edev;
580
581 ifp = ha->ifp;
582
583 if(ifp->if_drv_flags & IFF_DRV_RUNNING) {
584 if (!drbr_empty(ifp, fp->tx_br)) {
585 if(mtx_trylock(&fp->tx_mtx)) {
586 #ifdef QLNX_TRACE_PERF_DATA
587 tx_pkts = fp->tx_pkts_transmitted;
588 tx_compl = fp->tx_pkts_completed;
589 #endif
590
591 qlnx_transmit_locked(ifp, fp, NULL);
592
593 #ifdef QLNX_TRACE_PERF_DATA
594 fp->tx_pkts_trans_fp +=
595 (fp->tx_pkts_transmitted - tx_pkts);
596 fp->tx_pkts_compl_fp +=
597 (fp->tx_pkts_completed - tx_compl);
598 #endif
599 mtx_unlock(&fp->tx_mtx);
600 }
601 }
602 }
603
604 QL_DPRINT2(ha, "exit \n");
605 return;
606 }
607
608 static int
qlnx_create_fp_taskqueues(qlnx_host_t * ha)609 qlnx_create_fp_taskqueues(qlnx_host_t *ha)
610 {
611 int i;
612 uint8_t tq_name[32];
613 struct qlnx_fastpath *fp;
614
615 for (i = 0; i < ha->num_rss; i++) {
616 fp = &ha->fp_array[i];
617
618 bzero(tq_name, sizeof (tq_name));
619 snprintf(tq_name, sizeof (tq_name), "ql_fp_tq_%d", i);
620
621 TASK_INIT(&fp->fp_task, 0, qlnx_fp_taskqueue, fp);
622
623 fp->fp_taskqueue = taskqueue_create(tq_name, M_NOWAIT,
624 taskqueue_thread_enqueue,
625 &fp->fp_taskqueue);
626
627 if (fp->fp_taskqueue == NULL)
628 return (-1);
629
630 taskqueue_start_threads(&fp->fp_taskqueue, 1, PI_NET, "%s",
631 tq_name);
632
633 QL_DPRINT1(ha, "%p\n",fp->fp_taskqueue);
634 }
635
636 return (0);
637 }
638
639 static void
qlnx_destroy_fp_taskqueues(qlnx_host_t * ha)640 qlnx_destroy_fp_taskqueues(qlnx_host_t *ha)
641 {
642 int i;
643 struct qlnx_fastpath *fp;
644
645 for (i = 0; i < ha->num_rss; i++) {
646 fp = &ha->fp_array[i];
647
648 if (fp->fp_taskqueue != NULL) {
649 taskqueue_drain(fp->fp_taskqueue, &fp->fp_task);
650 taskqueue_free(fp->fp_taskqueue);
651 fp->fp_taskqueue = NULL;
652 }
653 }
654 return;
655 }
656
657 static void
qlnx_drain_fp_taskqueues(qlnx_host_t * ha)658 qlnx_drain_fp_taskqueues(qlnx_host_t *ha)
659 {
660 int i;
661 struct qlnx_fastpath *fp;
662
663 for (i = 0; i < ha->num_rss; i++) {
664 fp = &ha->fp_array[i];
665
666 if (fp->fp_taskqueue != NULL) {
667 QLNX_UNLOCK(ha);
668 taskqueue_drain(fp->fp_taskqueue, &fp->fp_task);
669 QLNX_LOCK(ha);
670 }
671 }
672 return;
673 }
674
675 static void
qlnx_get_params(qlnx_host_t * ha)676 qlnx_get_params(qlnx_host_t *ha)
677 {
678 if ((qlnxe_queue_count < 0) || (qlnxe_queue_count > QLNX_MAX_RSS)) {
679 device_printf(ha->pci_dev, "invalid queue_count value (%d)\n",
680 qlnxe_queue_count);
681 qlnxe_queue_count = 0;
682 }
683 return;
684 }
685
686 static void
qlnx_error_recovery_taskqueue(void * context,int pending)687 qlnx_error_recovery_taskqueue(void *context, int pending)
688 {
689 qlnx_host_t *ha;
690
691 ha = context;
692
693 QL_DPRINT2(ha, "enter\n");
694
695 QLNX_LOCK(ha);
696 qlnx_stop(ha);
697 QLNX_UNLOCK(ha);
698
699 #ifdef QLNX_ENABLE_IWARP
700 qlnx_rdma_dev_remove(ha);
701 #endif /* #ifdef QLNX_ENABLE_IWARP */
702
703 qlnx_slowpath_stop(ha);
704 qlnx_slowpath_start(ha);
705
706 #ifdef QLNX_ENABLE_IWARP
707 qlnx_rdma_dev_add(ha);
708 #endif /* #ifdef QLNX_ENABLE_IWARP */
709
710 qlnx_init(ha);
711
712 callout_reset(&ha->qlnx_callout, hz, qlnx_timer, ha);
713
714 QL_DPRINT2(ha, "exit\n");
715
716 return;
717 }
718
719 static int
qlnx_create_error_recovery_taskqueue(qlnx_host_t * ha)720 qlnx_create_error_recovery_taskqueue(qlnx_host_t *ha)
721 {
722 uint8_t tq_name[32];
723
724 bzero(tq_name, sizeof (tq_name));
725 snprintf(tq_name, sizeof (tq_name), "ql_err_tq");
726
727 TASK_INIT(&ha->err_task, 0, qlnx_error_recovery_taskqueue, ha);
728
729 ha->err_taskqueue = taskqueue_create(tq_name, M_NOWAIT,
730 taskqueue_thread_enqueue, &ha->err_taskqueue);
731
732 if (ha->err_taskqueue == NULL)
733 return (-1);
734
735 taskqueue_start_threads(&ha->err_taskqueue, 1, PI_NET, "%s", tq_name);
736
737 QL_DPRINT1(ha, "%p\n",ha->err_taskqueue);
738
739 return (0);
740 }
741
742 static void
qlnx_destroy_error_recovery_taskqueue(qlnx_host_t * ha)743 qlnx_destroy_error_recovery_taskqueue(qlnx_host_t *ha)
744 {
745 if (ha->err_taskqueue != NULL) {
746 taskqueue_drain(ha->err_taskqueue, &ha->err_task);
747 taskqueue_free(ha->err_taskqueue);
748 }
749
750 ha->err_taskqueue = NULL;
751
752 return;
753 }
754
755 /*
756 * Name: qlnx_pci_attach
757 * Function: attaches the device to the operating system
758 */
759 static int
qlnx_pci_attach(device_t dev)760 qlnx_pci_attach(device_t dev)
761 {
762 qlnx_host_t *ha = NULL;
763 uint32_t rsrc_len_reg = 0;
764 uint32_t rsrc_len_dbells = 0;
765 uint32_t rsrc_len_msix = 0;
766 int i;
767 uint32_t mfw_ver;
768 uint32_t num_sp_msix = 0;
769 uint32_t num_rdma_irqs = 0;
770
771 if ((ha = device_get_softc(dev)) == NULL) {
772 device_printf(dev, "cannot get softc\n");
773 return (ENOMEM);
774 }
775
776 memset(ha, 0, sizeof (qlnx_host_t));
777
778 ha->device_id = pci_get_device(dev);
779
780 if (qlnx_valid_device(ha) != 0) {
781 device_printf(dev, "device is not valid device\n");
782 return (ENXIO);
783 }
784 ha->pci_func = pci_get_function(dev);
785
786 ha->pci_dev = dev;
787
788 sx_init(&ha->hw_lock, "qlnx_hw_lock");
789
790 ha->flags.lock_init = 1;
791
792 pci_enable_busmaster(dev);
793
794 /*
795 * map the PCI BARs
796 */
797
798 ha->reg_rid = PCIR_BAR(0);
799 ha->pci_reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &ha->reg_rid,
800 RF_ACTIVE);
801
802 if (ha->pci_reg == NULL) {
803 device_printf(dev, "unable to map BAR0\n");
804 goto qlnx_pci_attach_err;
805 }
806
807 rsrc_len_reg = (uint32_t) bus_get_resource_count(dev, SYS_RES_MEMORY,
808 ha->reg_rid);
809
810 ha->dbells_rid = PCIR_BAR(2);
811 rsrc_len_dbells = (uint32_t) bus_get_resource_count(dev,
812 SYS_RES_MEMORY,
813 ha->dbells_rid);
814 if (rsrc_len_dbells) {
815 ha->pci_dbells = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
816 &ha->dbells_rid, RF_ACTIVE);
817
818 if (ha->pci_dbells == NULL) {
819 device_printf(dev, "unable to map BAR1\n");
820 goto qlnx_pci_attach_err;
821 }
822 ha->dbells_phys_addr = (uint64_t)
823 bus_get_resource_start(dev, SYS_RES_MEMORY, ha->dbells_rid);
824
825 ha->dbells_size = rsrc_len_dbells;
826 } else {
827 if (qlnx_vf_device(ha) != 0) {
828 device_printf(dev, " BAR1 size is zero\n");
829 goto qlnx_pci_attach_err;
830 }
831 }
832
833 ha->msix_rid = PCIR_BAR(4);
834 ha->msix_bar = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
835 &ha->msix_rid, RF_ACTIVE);
836
837 if (ha->msix_bar == NULL) {
838 device_printf(dev, "unable to map BAR2\n");
839 goto qlnx_pci_attach_err;
840 }
841
842 rsrc_len_msix = (uint32_t) bus_get_resource_count(dev, SYS_RES_MEMORY,
843 ha->msix_rid);
844
845 ha->dbg_level = 0x0000;
846
847 QL_DPRINT1(ha, "\n\t\t\t"
848 "pci_dev = %p pci_reg = %p, reg_len = 0x%08x reg_rid = 0x%08x"
849 "\n\t\t\tdbells = %p, dbells_len = 0x%08x dbells_rid = 0x%08x"
850 "\n\t\t\tmsix = %p, msix_len = 0x%08x msix_rid = 0x%08x"
851 " msix_avail = 0x%x "
852 "\n\t\t\t[ncpus = %d]\n",
853 ha->pci_dev, ha->pci_reg, rsrc_len_reg,
854 ha->reg_rid, ha->pci_dbells, rsrc_len_dbells, ha->dbells_rid,
855 ha->msix_bar, rsrc_len_msix, ha->msix_rid, pci_msix_count(dev),
856 mp_ncpus);
857 /*
858 * allocate dma tags
859 */
860
861 if (qlnx_alloc_parent_dma_tag(ha))
862 goto qlnx_pci_attach_err;
863
864 if (qlnx_alloc_tx_dma_tag(ha))
865 goto qlnx_pci_attach_err;
866
867 if (qlnx_alloc_rx_dma_tag(ha))
868 goto qlnx_pci_attach_err;
869
870
871 if (qlnx_init_hw(ha) != 0)
872 goto qlnx_pci_attach_err;
873
874 ha->flags.hw_init = 1;
875
876 qlnx_get_params(ha);
877
878 if((pci_get_device(dev) == QLOGIC_PCI_DEVICE_ID_1644) &&
879 (qlnxe_queue_count == QLNX_DEFAULT_RSS)) {
880 qlnxe_queue_count = QLNX_MAX_RSS;
881 }
882
883 /*
884 * Allocate MSI-x vectors
885 */
886 if (qlnx_vf_device(ha) != 0) {
887 if (qlnxe_queue_count == 0)
888 ha->num_rss = QLNX_DEFAULT_RSS;
889 else
890 ha->num_rss = qlnxe_queue_count;
891
892 num_sp_msix = ha->cdev.num_hwfns;
893 } else {
894 uint8_t max_rxq;
895 uint8_t max_txq;
896
897 ecore_vf_get_num_rxqs(&ha->cdev.hwfns[0], &max_rxq);
898 ecore_vf_get_num_rxqs(&ha->cdev.hwfns[0], &max_txq);
899
900 if (max_rxq < max_txq)
901 ha->num_rss = max_rxq;
902 else
903 ha->num_rss = max_txq;
904
905 if (ha->num_rss > QLNX_MAX_VF_RSS)
906 ha->num_rss = QLNX_MAX_VF_RSS;
907
908 num_sp_msix = 0;
909 }
910
911 if (ha->num_rss > mp_ncpus)
912 ha->num_rss = mp_ncpus;
913
914 ha->num_tc = QLNX_MAX_TC;
915
916 ha->msix_count = pci_msix_count(dev);
917
918 #ifdef QLNX_ENABLE_IWARP
919
920 num_rdma_irqs = qlnx_rdma_get_num_irqs(ha);
921
922 #endif /* #ifdef QLNX_ENABLE_IWARP */
923
924 if (!ha->msix_count ||
925 (ha->msix_count < (num_sp_msix + 1 + num_rdma_irqs))) {
926 device_printf(dev, "%s: msix_count[%d] not enough\n", __func__,
927 ha->msix_count);
928 goto qlnx_pci_attach_err;
929 }
930
931 if (ha->msix_count > (ha->num_rss + num_sp_msix + num_rdma_irqs))
932 ha->msix_count = ha->num_rss + num_sp_msix + num_rdma_irqs;
933 else
934 ha->num_rss = ha->msix_count - (num_sp_msix + num_rdma_irqs);
935
936 QL_DPRINT1(ha, "\n\t\t\t"
937 "pci_reg = %p, reg_len = 0x%08x reg_rid = 0x%08x"
938 "\n\t\t\tdbells = %p, dbells_len = 0x%08x dbells_rid = 0x%08x"
939 "\n\t\t\tmsix = %p, msix_len = 0x%08x msix_rid = 0x%08x"
940 " msix_avail = 0x%x msix_alloc = 0x%x"
941 "\n\t\t\t[ncpus = %d][num_rss = 0x%x] [num_tc = 0x%x]\n",
942 ha->pci_reg, rsrc_len_reg,
943 ha->reg_rid, ha->pci_dbells, rsrc_len_dbells, ha->dbells_rid,
944 ha->msix_bar, rsrc_len_msix, ha->msix_rid, pci_msix_count(dev),
945 ha->msix_count, mp_ncpus, ha->num_rss, ha->num_tc);
946
947 if (pci_alloc_msix(dev, &ha->msix_count)) {
948 device_printf(dev, "%s: pci_alloc_msix[%d] failed\n", __func__,
949 ha->msix_count);
950 ha->msix_count = 0;
951 goto qlnx_pci_attach_err;
952 }
953
954 /*
955 * Initialize slow path interrupt and task queue
956 */
957
958 if (num_sp_msix) {
959 if (qlnx_create_sp_taskqueues(ha) != 0)
960 goto qlnx_pci_attach_err;
961
962 for (i = 0; i < ha->cdev.num_hwfns; i++) {
963 struct ecore_hwfn *p_hwfn = &ha->cdev.hwfns[i];
964
965 ha->sp_irq_rid[i] = i + 1;
966 ha->sp_irq[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ,
967 &ha->sp_irq_rid[i],
968 (RF_ACTIVE | RF_SHAREABLE));
969 if (ha->sp_irq[i] == NULL) {
970 device_printf(dev,
971 "could not allocate mbx interrupt\n");
972 goto qlnx_pci_attach_err;
973 }
974
975 if (bus_setup_intr(dev, ha->sp_irq[i],
976 (INTR_TYPE_NET | INTR_MPSAFE), NULL,
977 qlnx_sp_intr, p_hwfn, &ha->sp_handle[i])) {
978 device_printf(dev,
979 "could not setup slow path interrupt\n");
980 goto qlnx_pci_attach_err;
981 }
982
983 QL_DPRINT1(ha, "p_hwfn [%p] sp_irq_rid %d"
984 " sp_irq %p sp_handle %p\n", p_hwfn,
985 ha->sp_irq_rid[i], ha->sp_irq[i], ha->sp_handle[i]);
986 }
987 }
988
989 /*
990 * initialize fast path interrupt
991 */
992 if (qlnx_create_fp_taskqueues(ha) != 0)
993 goto qlnx_pci_attach_err;
994
995 for (i = 0; i < ha->num_rss; i++) {
996 ha->irq_vec[i].rss_idx = i;
997 ha->irq_vec[i].ha = ha;
998 ha->irq_vec[i].irq_rid = (1 + num_sp_msix) + i;
999
1000 ha->irq_vec[i].irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1001 &ha->irq_vec[i].irq_rid,
1002 (RF_ACTIVE | RF_SHAREABLE));
1003
1004 if (ha->irq_vec[i].irq == NULL) {
1005 device_printf(dev,
1006 "could not allocate interrupt[%d] irq_rid = %d\n",
1007 i, ha->irq_vec[i].irq_rid);
1008 goto qlnx_pci_attach_err;
1009 }
1010
1011 if (qlnx_alloc_tx_br(ha, &ha->fp_array[i])) {
1012 device_printf(dev, "could not allocate tx_br[%d]\n", i);
1013 goto qlnx_pci_attach_err;
1014 }
1015 }
1016
1017 if (qlnx_vf_device(ha) != 0) {
1018 callout_init(&ha->qlnx_callout, 1);
1019 ha->flags.callout_init = 1;
1020
1021 for (i = 0; i < ha->cdev.num_hwfns; i++) {
1022 if (qlnx_grc_dumpsize(ha, &ha->grcdump_size[i], i) != 0)
1023 goto qlnx_pci_attach_err;
1024 if (ha->grcdump_size[i] == 0)
1025 goto qlnx_pci_attach_err;
1026
1027 ha->grcdump_size[i] = ha->grcdump_size[i] << 2;
1028 QL_DPRINT1(ha, "grcdump_size[%d] = 0x%08x\n",
1029 i, ha->grcdump_size[i]);
1030
1031 ha->grcdump[i] = qlnx_zalloc(ha->grcdump_size[i]);
1032 if (ha->grcdump[i] == NULL) {
1033 device_printf(dev, "grcdump alloc[%d] failed\n", i);
1034 goto qlnx_pci_attach_err;
1035 }
1036
1037 if (qlnx_idle_chk_size(ha, &ha->idle_chk_size[i], i) != 0)
1038 goto qlnx_pci_attach_err;
1039 if (ha->idle_chk_size[i] == 0)
1040 goto qlnx_pci_attach_err;
1041
1042 ha->idle_chk_size[i] = ha->idle_chk_size[i] << 2;
1043 QL_DPRINT1(ha, "idle_chk_size[%d] = 0x%08x\n",
1044 i, ha->idle_chk_size[i]);
1045
1046 ha->idle_chk[i] = qlnx_zalloc(ha->idle_chk_size[i]);
1047
1048 if (ha->idle_chk[i] == NULL) {
1049 device_printf(dev, "idle_chk alloc failed\n");
1050 goto qlnx_pci_attach_err;
1051 }
1052 }
1053
1054 if (qlnx_create_error_recovery_taskqueue(ha) != 0)
1055 goto qlnx_pci_attach_err;
1056 }
1057
1058 if (qlnx_slowpath_start(ha) != 0)
1059 goto qlnx_pci_attach_err;
1060 else
1061 ha->flags.slowpath_start = 1;
1062
1063 if (qlnx_vf_device(ha) != 0) {
1064 if (qlnx_get_flash_size(ha, &ha->flash_size) != 0) {
1065 qlnx_mdelay(__func__, 1000);
1066 qlnx_trigger_dump(ha);
1067
1068 goto qlnx_pci_attach_err0;
1069 }
1070
1071 if (qlnx_get_mfw_version(ha, &mfw_ver) != 0) {
1072 qlnx_mdelay(__func__, 1000);
1073 qlnx_trigger_dump(ha);
1074
1075 goto qlnx_pci_attach_err0;
1076 }
1077 } else {
1078 struct ecore_hwfn *p_hwfn = &ha->cdev.hwfns[0];
1079 ecore_mcp_get_mfw_ver(p_hwfn, NULL, &mfw_ver, NULL);
1080 }
1081
1082 snprintf(ha->mfw_ver, sizeof(ha->mfw_ver), "%d.%d.%d.%d",
1083 ((mfw_ver >> 24) & 0xFF), ((mfw_ver >> 16) & 0xFF),
1084 ((mfw_ver >> 8) & 0xFF), (mfw_ver & 0xFF));
1085 snprintf(ha->stormfw_ver, sizeof(ha->stormfw_ver), "%d.%d.%d.%d",
1086 FW_MAJOR_VERSION, FW_MINOR_VERSION, FW_REVISION_VERSION,
1087 FW_ENGINEERING_VERSION);
1088
1089 QL_DPRINT1(ha, "STORM_FW version %s MFW version %s\n",
1090 ha->stormfw_ver, ha->mfw_ver);
1091
1092 qlnx_init_ifnet(dev, ha);
1093
1094 /*
1095 * add sysctls
1096 */
1097 qlnx_add_sysctls(ha);
1098
1099 qlnx_pci_attach_err0:
1100 /*
1101 * create ioctl device interface
1102 */
1103 if (qlnx_vf_device(ha) != 0) {
1104 if (qlnx_make_cdev(ha)) {
1105 device_printf(dev, "%s: ql_make_cdev failed\n", __func__);
1106 goto qlnx_pci_attach_err;
1107 }
1108
1109 #ifdef QLNX_ENABLE_IWARP
1110 qlnx_rdma_dev_add(ha);
1111 #endif /* #ifdef QLNX_ENABLE_IWARP */
1112 }
1113
1114 #ifndef QLNX_VF
1115 #ifdef CONFIG_ECORE_SRIOV
1116
1117 if (qlnx_vf_device(ha) != 0)
1118 qlnx_initialize_sriov(ha);
1119
1120 #endif /* #ifdef CONFIG_ECORE_SRIOV */
1121 #endif /* #ifdef QLNX_VF */
1122
1123 QL_DPRINT2(ha, "success\n");
1124
1125 return (0);
1126
1127 qlnx_pci_attach_err:
1128
1129 qlnx_release(ha);
1130
1131 return (ENXIO);
1132 }
1133
1134 /*
1135 * Name: qlnx_pci_detach
1136 * Function: Unhooks the device from the operating system
1137 */
1138 static int
qlnx_pci_detach(device_t dev)1139 qlnx_pci_detach(device_t dev)
1140 {
1141 qlnx_host_t *ha = NULL;
1142
1143 if ((ha = device_get_softc(dev)) == NULL) {
1144 device_printf(dev, "%s: cannot get softc\n", __func__);
1145 return (ENOMEM);
1146 }
1147
1148 if (qlnx_vf_device(ha) != 0) {
1149 #ifdef CONFIG_ECORE_SRIOV
1150 int ret;
1151
1152 ret = pci_iov_detach(dev);
1153 if (ret) {
1154 device_printf(dev, "%s: SRIOV in use\n", __func__);
1155 return (ret);
1156 }
1157
1158 #endif /* #ifdef CONFIG_ECORE_SRIOV */
1159
1160 #ifdef QLNX_ENABLE_IWARP
1161 if (qlnx_rdma_dev_remove(ha) != 0)
1162 return (EBUSY);
1163 #endif /* #ifdef QLNX_ENABLE_IWARP */
1164 }
1165
1166 QLNX_LOCK(ha);
1167 qlnx_stop(ha);
1168 QLNX_UNLOCK(ha);
1169
1170 qlnx_release(ha);
1171
1172 return (0);
1173 }
1174
1175 #ifdef QLNX_ENABLE_IWARP
1176
1177 static uint8_t
qlnx_get_personality(uint8_t pci_func)1178 qlnx_get_personality(uint8_t pci_func)
1179 {
1180 uint8_t personality;
1181
1182 personality = (qlnxe_rdma_configuration >>
1183 (pci_func * QLNX_PERSONALITY_BITS_PER_FUNC)) &
1184 QLNX_PERSONALIY_MASK;
1185 return (personality);
1186 }
1187
1188 static void
qlnx_set_personality(qlnx_host_t * ha)1189 qlnx_set_personality(qlnx_host_t *ha)
1190 {
1191 struct ecore_hwfn *p_hwfn;
1192 uint8_t personality;
1193
1194 p_hwfn = &ha->cdev.hwfns[0];
1195
1196 personality = qlnx_get_personality(ha->pci_func);
1197
1198 switch (personality) {
1199 case QLNX_PERSONALITY_DEFAULT:
1200 device_printf(ha->pci_dev, "%s: DEFAULT\n",
1201 __func__);
1202 ha->personality = ECORE_PCI_DEFAULT;
1203 break;
1204
1205 case QLNX_PERSONALITY_ETH_ONLY:
1206 device_printf(ha->pci_dev, "%s: ETH_ONLY\n",
1207 __func__);
1208 ha->personality = ECORE_PCI_ETH;
1209 break;
1210
1211 case QLNX_PERSONALITY_ETH_IWARP:
1212 device_printf(ha->pci_dev, "%s: ETH_IWARP\n",
1213 __func__);
1214 ha->personality = ECORE_PCI_ETH_IWARP;
1215 break;
1216
1217 case QLNX_PERSONALITY_ETH_ROCE:
1218 device_printf(ha->pci_dev, "%s: ETH_ROCE\n",
1219 __func__);
1220 ha->personality = ECORE_PCI_ETH_ROCE;
1221 break;
1222 }
1223
1224 return;
1225 }
1226
1227 #endif /* #ifdef QLNX_ENABLE_IWARP */
1228
1229 static int
qlnx_init_hw(qlnx_host_t * ha)1230 qlnx_init_hw(qlnx_host_t *ha)
1231 {
1232 int rval = 0;
1233 struct ecore_hw_prepare_params params;
1234
1235 ha->cdev.ha = ha;
1236 ecore_init_struct(&ha->cdev);
1237
1238 /* ha->dp_module = ECORE_MSG_PROBE |
1239 ECORE_MSG_INTR |
1240 ECORE_MSG_SP |
1241 ECORE_MSG_LINK |
1242 ECORE_MSG_SPQ |
1243 ECORE_MSG_RDMA;
1244 ha->dp_level = ECORE_LEVEL_VERBOSE;*/
1245 //ha->dp_module = ECORE_MSG_RDMA | ECORE_MSG_INTR | ECORE_MSG_LL2;
1246 ha->dp_level = ECORE_LEVEL_NOTICE;
1247 //ha->dp_level = ECORE_LEVEL_VERBOSE;
1248
1249 ecore_init_dp(&ha->cdev, ha->dp_module, ha->dp_level, ha->pci_dev);
1250
1251 ha->cdev.regview = ha->pci_reg;
1252
1253 ha->personality = ECORE_PCI_DEFAULT;
1254
1255 if (qlnx_vf_device(ha) == 0) {
1256 ha->cdev.b_is_vf = true;
1257
1258 if (ha->pci_dbells != NULL) {
1259 ha->cdev.doorbells = ha->pci_dbells;
1260 ha->cdev.db_phys_addr = ha->dbells_phys_addr;
1261 ha->cdev.db_size = ha->dbells_size;
1262 } else {
1263 ha->pci_dbells = ha->pci_reg;
1264 }
1265 } else {
1266 ha->cdev.doorbells = ha->pci_dbells;
1267 ha->cdev.db_phys_addr = ha->dbells_phys_addr;
1268 ha->cdev.db_size = ha->dbells_size;
1269
1270 #ifdef QLNX_ENABLE_IWARP
1271
1272 if (qlnx_rdma_supported(ha) == 0)
1273 qlnx_set_personality(ha);
1274
1275 #endif /* #ifdef QLNX_ENABLE_IWARP */
1276 }
1277 QL_DPRINT2(ha, "%s: %s\n", __func__,
1278 (ha->personality == ECORE_PCI_ETH_IWARP ? "iwarp": "ethernet"));
1279
1280 bzero(¶ms, sizeof (struct ecore_hw_prepare_params));
1281
1282 params.personality = ha->personality;
1283
1284 params.drv_resc_alloc = false;
1285 params.chk_reg_fifo = false;
1286 params.initiate_pf_flr = true;
1287 params.epoch = 0;
1288
1289 ecore_hw_prepare(&ha->cdev, ¶ms);
1290
1291 qlnx_set_id(&ha->cdev, qlnx_name_str, qlnx_ver_str);
1292
1293 QL_DPRINT1(ha, "ha = %p cdev = %p p_hwfn = %p\n",
1294 ha, &ha->cdev, &ha->cdev.hwfns[0]);
1295
1296 return (rval);
1297 }
1298
1299 static void
qlnx_release(qlnx_host_t * ha)1300 qlnx_release(qlnx_host_t *ha)
1301 {
1302 device_t dev;
1303 int i;
1304
1305 dev = ha->pci_dev;
1306
1307 QL_DPRINT2(ha, "enter\n");
1308
1309 for (i = 0; i < QLNX_MAX_HW_FUNCS; i++) {
1310 if (ha->idle_chk[i] != NULL) {
1311 free(ha->idle_chk[i], M_QLNXBUF);
1312 ha->idle_chk[i] = NULL;
1313 }
1314
1315 if (ha->grcdump[i] != NULL) {
1316 free(ha->grcdump[i], M_QLNXBUF);
1317 ha->grcdump[i] = NULL;
1318 }
1319 }
1320
1321 if (ha->flags.callout_init)
1322 callout_drain(&ha->qlnx_callout);
1323
1324 if (ha->flags.slowpath_start) {
1325 qlnx_slowpath_stop(ha);
1326 }
1327
1328 if (ha->flags.hw_init)
1329 ecore_hw_remove(&ha->cdev);
1330
1331 qlnx_del_cdev(ha);
1332
1333 if (ha->ifp != NULL)
1334 ether_ifdetach(ha->ifp);
1335
1336 qlnx_free_tx_dma_tag(ha);
1337
1338 qlnx_free_rx_dma_tag(ha);
1339
1340 qlnx_free_parent_dma_tag(ha);
1341
1342 if (qlnx_vf_device(ha) != 0) {
1343 qlnx_destroy_error_recovery_taskqueue(ha);
1344 }
1345
1346 for (i = 0; i < ha->num_rss; i++) {
1347 struct qlnx_fastpath *fp = &ha->fp_array[i];
1348
1349 if (ha->irq_vec[i].handle) {
1350 (void)bus_teardown_intr(dev, ha->irq_vec[i].irq,
1351 ha->irq_vec[i].handle);
1352 }
1353
1354 if (ha->irq_vec[i].irq) {
1355 (void)bus_release_resource(dev, SYS_RES_IRQ,
1356 ha->irq_vec[i].irq_rid,
1357 ha->irq_vec[i].irq);
1358 }
1359
1360 qlnx_free_tx_br(ha, fp);
1361 }
1362 qlnx_destroy_fp_taskqueues(ha);
1363
1364 for (i = 0; i < ha->cdev.num_hwfns; i++) {
1365 if (ha->sp_handle[i])
1366 (void)bus_teardown_intr(dev, ha->sp_irq[i],
1367 ha->sp_handle[i]);
1368
1369 if (ha->sp_irq[i])
1370 (void) bus_release_resource(dev, SYS_RES_IRQ,
1371 ha->sp_irq_rid[i], ha->sp_irq[i]);
1372 }
1373
1374 qlnx_destroy_sp_taskqueues(ha);
1375
1376 if (ha->msix_count)
1377 pci_release_msi(dev);
1378
1379 if (ha->flags.lock_init) {
1380 sx_destroy(&ha->hw_lock);
1381 }
1382
1383 if (ha->pci_reg)
1384 (void) bus_release_resource(dev, SYS_RES_MEMORY, ha->reg_rid,
1385 ha->pci_reg);
1386
1387 if (ha->dbells_size && ha->pci_dbells)
1388 (void) bus_release_resource(dev, SYS_RES_MEMORY, ha->dbells_rid,
1389 ha->pci_dbells);
1390
1391 if (ha->msix_bar)
1392 (void) bus_release_resource(dev, SYS_RES_MEMORY, ha->msix_rid,
1393 ha->msix_bar);
1394
1395 QL_DPRINT2(ha, "exit\n");
1396 return;
1397 }
1398
1399 static void
qlnx_trigger_dump(qlnx_host_t * ha)1400 qlnx_trigger_dump(qlnx_host_t *ha)
1401 {
1402 int i;
1403
1404 if (ha->ifp != NULL)
1405 ha->ifp->if_drv_flags &= ~(IFF_DRV_OACTIVE | IFF_DRV_RUNNING);
1406
1407 QL_DPRINT2(ha, "enter\n");
1408
1409 if (qlnx_vf_device(ha) == 0)
1410 return;
1411
1412 ha->error_recovery = 1;
1413
1414 for (i = 0; i < ha->cdev.num_hwfns; i++) {
1415 qlnx_grc_dump(ha, &ha->grcdump_dwords[i], i);
1416 qlnx_idle_chk(ha, &ha->idle_chk_dwords[i], i);
1417 }
1418
1419 QL_DPRINT2(ha, "exit\n");
1420
1421 return;
1422 }
1423
1424 static int
qlnx_trigger_dump_sysctl(SYSCTL_HANDLER_ARGS)1425 qlnx_trigger_dump_sysctl(SYSCTL_HANDLER_ARGS)
1426 {
1427 int err, ret = 0;
1428 qlnx_host_t *ha;
1429
1430 err = sysctl_handle_int(oidp, &ret, 0, req);
1431
1432 if (err || !req->newptr)
1433 return (err);
1434
1435 if (ret == 1) {
1436 ha = (qlnx_host_t *)arg1;
1437 qlnx_trigger_dump(ha);
1438 }
1439 return (err);
1440 }
1441
1442 static int
qlnx_set_tx_coalesce(SYSCTL_HANDLER_ARGS)1443 qlnx_set_tx_coalesce(SYSCTL_HANDLER_ARGS)
1444 {
1445 int err, i, ret = 0, usecs = 0;
1446 qlnx_host_t *ha;
1447 struct ecore_hwfn *p_hwfn;
1448 struct qlnx_fastpath *fp;
1449
1450 err = sysctl_handle_int(oidp, &usecs, 0, req);
1451
1452 if (err || !req->newptr || !usecs || (usecs > 255))
1453 return (err);
1454
1455 ha = (qlnx_host_t *)arg1;
1456
1457 if (qlnx_vf_device(ha) == 0)
1458 return (-1);
1459
1460 for (i = 0; i < ha->num_rss; i++) {
1461 p_hwfn = &ha->cdev.hwfns[(i % ha->cdev.num_hwfns)];
1462
1463 fp = &ha->fp_array[i];
1464
1465 if (fp->txq[0]->handle != NULL) {
1466 ret = ecore_set_queue_coalesce(p_hwfn, 0,
1467 (uint16_t)usecs, fp->txq[0]->handle);
1468 }
1469 }
1470
1471 if (!ret)
1472 ha->tx_coalesce_usecs = (uint8_t)usecs;
1473
1474 return (err);
1475 }
1476
1477 static int
qlnx_set_rx_coalesce(SYSCTL_HANDLER_ARGS)1478 qlnx_set_rx_coalesce(SYSCTL_HANDLER_ARGS)
1479 {
1480 int err, i, ret = 0, usecs = 0;
1481 qlnx_host_t *ha;
1482 struct ecore_hwfn *p_hwfn;
1483 struct qlnx_fastpath *fp;
1484
1485 err = sysctl_handle_int(oidp, &usecs, 0, req);
1486
1487 if (err || !req->newptr || !usecs || (usecs > 255))
1488 return (err);
1489
1490 ha = (qlnx_host_t *)arg1;
1491
1492 if (qlnx_vf_device(ha) == 0)
1493 return (-1);
1494
1495 for (i = 0; i < ha->num_rss; i++) {
1496 p_hwfn = &ha->cdev.hwfns[(i % ha->cdev.num_hwfns)];
1497
1498 fp = &ha->fp_array[i];
1499
1500 if (fp->rxq->handle != NULL) {
1501 ret = ecore_set_queue_coalesce(p_hwfn, (uint16_t)usecs,
1502 0, fp->rxq->handle);
1503 }
1504 }
1505
1506 if (!ret)
1507 ha->rx_coalesce_usecs = (uint8_t)usecs;
1508
1509 return (err);
1510 }
1511
1512 static void
qlnx_add_sp_stats_sysctls(qlnx_host_t * ha)1513 qlnx_add_sp_stats_sysctls(qlnx_host_t *ha)
1514 {
1515 struct sysctl_ctx_list *ctx;
1516 struct sysctl_oid_list *children;
1517 struct sysctl_oid *ctx_oid;
1518
1519 ctx = device_get_sysctl_ctx(ha->pci_dev);
1520 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev));
1521
1522 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "spstat",
1523 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "spstat");
1524 children = SYSCTL_CHILDREN(ctx_oid);
1525
1526 SYSCTL_ADD_QUAD(ctx, children,
1527 OID_AUTO, "sp_interrupts",
1528 CTLFLAG_RD, &ha->sp_interrupts,
1529 "No. of slowpath interrupts");
1530
1531 return;
1532 }
1533
1534 static void
qlnx_add_fp_stats_sysctls(qlnx_host_t * ha)1535 qlnx_add_fp_stats_sysctls(qlnx_host_t *ha)
1536 {
1537 struct sysctl_ctx_list *ctx;
1538 struct sysctl_oid_list *children;
1539 struct sysctl_oid_list *node_children;
1540 struct sysctl_oid *ctx_oid;
1541 int i, j;
1542 uint8_t name_str[16];
1543
1544 ctx = device_get_sysctl_ctx(ha->pci_dev);
1545 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev));
1546
1547 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fpstat",
1548 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "fpstat");
1549 children = SYSCTL_CHILDREN(ctx_oid);
1550
1551 for (i = 0; i < ha->num_rss; i++) {
1552 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
1553 snprintf(name_str, sizeof(name_str), "%d", i);
1554
1555 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str,
1556 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, name_str);
1557 node_children = SYSCTL_CHILDREN(ctx_oid);
1558
1559 /* Tx Related */
1560
1561 SYSCTL_ADD_QUAD(ctx, node_children,
1562 OID_AUTO, "tx_pkts_processed",
1563 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_processed,
1564 "No. of packets processed for transmission");
1565
1566 SYSCTL_ADD_QUAD(ctx, node_children,
1567 OID_AUTO, "tx_pkts_freed",
1568 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_freed,
1569 "No. of freed packets");
1570
1571 SYSCTL_ADD_QUAD(ctx, node_children,
1572 OID_AUTO, "tx_pkts_transmitted",
1573 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_transmitted,
1574 "No. of transmitted packets");
1575
1576 SYSCTL_ADD_QUAD(ctx, node_children,
1577 OID_AUTO, "tx_pkts_completed",
1578 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_completed,
1579 "No. of transmit completions");
1580
1581 SYSCTL_ADD_QUAD(ctx, node_children,
1582 OID_AUTO, "tx_non_tso_pkts",
1583 CTLFLAG_RD, &ha->fp_array[i].tx_non_tso_pkts,
1584 "No. of non LSO transmited packets");
1585
1586 #ifdef QLNX_TRACE_PERF_DATA
1587
1588 SYSCTL_ADD_QUAD(ctx, node_children,
1589 OID_AUTO, "tx_pkts_trans_ctx",
1590 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_trans_ctx,
1591 "No. of transmitted packets in transmit context");
1592
1593 SYSCTL_ADD_QUAD(ctx, node_children,
1594 OID_AUTO, "tx_pkts_compl_ctx",
1595 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_compl_ctx,
1596 "No. of transmit completions in transmit context");
1597
1598 SYSCTL_ADD_QUAD(ctx, node_children,
1599 OID_AUTO, "tx_pkts_trans_fp",
1600 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_trans_fp,
1601 "No. of transmitted packets in taskqueue");
1602
1603 SYSCTL_ADD_QUAD(ctx, node_children,
1604 OID_AUTO, "tx_pkts_compl_fp",
1605 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_compl_fp,
1606 "No. of transmit completions in taskqueue");
1607
1608 SYSCTL_ADD_QUAD(ctx, node_children,
1609 OID_AUTO, "tx_pkts_compl_intr",
1610 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_compl_intr,
1611 "No. of transmit completions in interrupt ctx");
1612 #endif
1613
1614 SYSCTL_ADD_QUAD(ctx, node_children,
1615 OID_AUTO, "tx_tso_pkts",
1616 CTLFLAG_RD, &ha->fp_array[i].tx_tso_pkts,
1617 "No. of LSO transmited packets");
1618
1619 SYSCTL_ADD_QUAD(ctx, node_children,
1620 OID_AUTO, "tx_lso_wnd_min_len",
1621 CTLFLAG_RD, &ha->fp_array[i].tx_lso_wnd_min_len,
1622 "tx_lso_wnd_min_len");
1623
1624 SYSCTL_ADD_QUAD(ctx, node_children,
1625 OID_AUTO, "tx_defrag",
1626 CTLFLAG_RD, &ha->fp_array[i].tx_defrag,
1627 "tx_defrag");
1628
1629 SYSCTL_ADD_QUAD(ctx, node_children,
1630 OID_AUTO, "tx_nsegs_gt_elem_left",
1631 CTLFLAG_RD, &ha->fp_array[i].tx_nsegs_gt_elem_left,
1632 "tx_nsegs_gt_elem_left");
1633
1634 SYSCTL_ADD_UINT(ctx, node_children,
1635 OID_AUTO, "tx_tso_max_nsegs",
1636 CTLFLAG_RD, &ha->fp_array[i].tx_tso_max_nsegs,
1637 ha->fp_array[i].tx_tso_max_nsegs, "tx_tso_max_nsegs");
1638
1639 SYSCTL_ADD_UINT(ctx, node_children,
1640 OID_AUTO, "tx_tso_min_nsegs",
1641 CTLFLAG_RD, &ha->fp_array[i].tx_tso_min_nsegs,
1642 ha->fp_array[i].tx_tso_min_nsegs, "tx_tso_min_nsegs");
1643
1644 SYSCTL_ADD_UINT(ctx, node_children,
1645 OID_AUTO, "tx_tso_max_pkt_len",
1646 CTLFLAG_RD, &ha->fp_array[i].tx_tso_max_pkt_len,
1647 ha->fp_array[i].tx_tso_max_pkt_len,
1648 "tx_tso_max_pkt_len");
1649
1650 SYSCTL_ADD_UINT(ctx, node_children,
1651 OID_AUTO, "tx_tso_min_pkt_len",
1652 CTLFLAG_RD, &ha->fp_array[i].tx_tso_min_pkt_len,
1653 ha->fp_array[i].tx_tso_min_pkt_len,
1654 "tx_tso_min_pkt_len");
1655
1656 for (j = 0; j < QLNX_FP_MAX_SEGS; j++) {
1657 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
1658 snprintf(name_str, sizeof(name_str),
1659 "tx_pkts_nseg_%02d", (j+1));
1660
1661 SYSCTL_ADD_QUAD(ctx, node_children,
1662 OID_AUTO, name_str, CTLFLAG_RD,
1663 &ha->fp_array[i].tx_pkts[j], name_str);
1664 }
1665
1666 #ifdef QLNX_TRACE_PERF_DATA
1667 for (j = 0; j < 18; j++) {
1668 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
1669 snprintf(name_str, sizeof(name_str),
1670 "tx_pkts_hist_%02d", (j+1));
1671
1672 SYSCTL_ADD_QUAD(ctx, node_children,
1673 OID_AUTO, name_str, CTLFLAG_RD,
1674 &ha->fp_array[i].tx_pkts_hist[j], name_str);
1675 }
1676 for (j = 0; j < 5; j++) {
1677 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
1678 snprintf(name_str, sizeof(name_str),
1679 "tx_comInt_%02d", (j+1));
1680
1681 SYSCTL_ADD_QUAD(ctx, node_children,
1682 OID_AUTO, name_str, CTLFLAG_RD,
1683 &ha->fp_array[i].tx_comInt[j], name_str);
1684 }
1685 for (j = 0; j < 18; j++) {
1686 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
1687 snprintf(name_str, sizeof(name_str),
1688 "tx_pkts_q_%02d", (j+1));
1689
1690 SYSCTL_ADD_QUAD(ctx, node_children,
1691 OID_AUTO, name_str, CTLFLAG_RD,
1692 &ha->fp_array[i].tx_pkts_q[j], name_str);
1693 }
1694 #endif
1695
1696 SYSCTL_ADD_QUAD(ctx, node_children,
1697 OID_AUTO, "err_tx_nsegs_gt_elem_left",
1698 CTLFLAG_RD, &ha->fp_array[i].err_tx_nsegs_gt_elem_left,
1699 "err_tx_nsegs_gt_elem_left");
1700
1701 SYSCTL_ADD_QUAD(ctx, node_children,
1702 OID_AUTO, "err_tx_dmamap_create",
1703 CTLFLAG_RD, &ha->fp_array[i].err_tx_dmamap_create,
1704 "err_tx_dmamap_create");
1705
1706 SYSCTL_ADD_QUAD(ctx, node_children,
1707 OID_AUTO, "err_tx_defrag_dmamap_load",
1708 CTLFLAG_RD, &ha->fp_array[i].err_tx_defrag_dmamap_load,
1709 "err_tx_defrag_dmamap_load");
1710
1711 SYSCTL_ADD_QUAD(ctx, node_children,
1712 OID_AUTO, "err_tx_non_tso_max_seg",
1713 CTLFLAG_RD, &ha->fp_array[i].err_tx_non_tso_max_seg,
1714 "err_tx_non_tso_max_seg");
1715
1716 SYSCTL_ADD_QUAD(ctx, node_children,
1717 OID_AUTO, "err_tx_dmamap_load",
1718 CTLFLAG_RD, &ha->fp_array[i].err_tx_dmamap_load,
1719 "err_tx_dmamap_load");
1720
1721 SYSCTL_ADD_QUAD(ctx, node_children,
1722 OID_AUTO, "err_tx_defrag",
1723 CTLFLAG_RD, &ha->fp_array[i].err_tx_defrag,
1724 "err_tx_defrag");
1725
1726 SYSCTL_ADD_QUAD(ctx, node_children,
1727 OID_AUTO, "err_tx_free_pkt_null",
1728 CTLFLAG_RD, &ha->fp_array[i].err_tx_free_pkt_null,
1729 "err_tx_free_pkt_null");
1730
1731 SYSCTL_ADD_QUAD(ctx, node_children,
1732 OID_AUTO, "err_tx_cons_idx_conflict",
1733 CTLFLAG_RD, &ha->fp_array[i].err_tx_cons_idx_conflict,
1734 "err_tx_cons_idx_conflict");
1735
1736 SYSCTL_ADD_QUAD(ctx, node_children,
1737 OID_AUTO, "lro_cnt_64",
1738 CTLFLAG_RD, &ha->fp_array[i].lro_cnt_64,
1739 "lro_cnt_64");
1740
1741 SYSCTL_ADD_QUAD(ctx, node_children,
1742 OID_AUTO, "lro_cnt_128",
1743 CTLFLAG_RD, &ha->fp_array[i].lro_cnt_128,
1744 "lro_cnt_128");
1745
1746 SYSCTL_ADD_QUAD(ctx, node_children,
1747 OID_AUTO, "lro_cnt_256",
1748 CTLFLAG_RD, &ha->fp_array[i].lro_cnt_256,
1749 "lro_cnt_256");
1750
1751 SYSCTL_ADD_QUAD(ctx, node_children,
1752 OID_AUTO, "lro_cnt_512",
1753 CTLFLAG_RD, &ha->fp_array[i].lro_cnt_512,
1754 "lro_cnt_512");
1755
1756 SYSCTL_ADD_QUAD(ctx, node_children,
1757 OID_AUTO, "lro_cnt_1024",
1758 CTLFLAG_RD, &ha->fp_array[i].lro_cnt_1024,
1759 "lro_cnt_1024");
1760
1761 /* Rx Related */
1762
1763 SYSCTL_ADD_QUAD(ctx, node_children,
1764 OID_AUTO, "rx_pkts",
1765 CTLFLAG_RD, &ha->fp_array[i].rx_pkts,
1766 "No. of received packets");
1767
1768 SYSCTL_ADD_QUAD(ctx, node_children,
1769 OID_AUTO, "tpa_start",
1770 CTLFLAG_RD, &ha->fp_array[i].tpa_start,
1771 "No. of tpa_start packets");
1772
1773 SYSCTL_ADD_QUAD(ctx, node_children,
1774 OID_AUTO, "tpa_cont",
1775 CTLFLAG_RD, &ha->fp_array[i].tpa_cont,
1776 "No. of tpa_cont packets");
1777
1778 SYSCTL_ADD_QUAD(ctx, node_children,
1779 OID_AUTO, "tpa_end",
1780 CTLFLAG_RD, &ha->fp_array[i].tpa_end,
1781 "No. of tpa_end packets");
1782
1783 SYSCTL_ADD_QUAD(ctx, node_children,
1784 OID_AUTO, "err_m_getcl",
1785 CTLFLAG_RD, &ha->fp_array[i].err_m_getcl,
1786 "err_m_getcl");
1787
1788 SYSCTL_ADD_QUAD(ctx, node_children,
1789 OID_AUTO, "err_m_getjcl",
1790 CTLFLAG_RD, &ha->fp_array[i].err_m_getjcl,
1791 "err_m_getjcl");
1792
1793 SYSCTL_ADD_QUAD(ctx, node_children,
1794 OID_AUTO, "err_rx_hw_errors",
1795 CTLFLAG_RD, &ha->fp_array[i].err_rx_hw_errors,
1796 "err_rx_hw_errors");
1797
1798 SYSCTL_ADD_QUAD(ctx, node_children,
1799 OID_AUTO, "err_rx_alloc_errors",
1800 CTLFLAG_RD, &ha->fp_array[i].err_rx_alloc_errors,
1801 "err_rx_alloc_errors");
1802 }
1803
1804 return;
1805 }
1806
1807 static void
qlnx_add_hw_stats_sysctls(qlnx_host_t * ha)1808 qlnx_add_hw_stats_sysctls(qlnx_host_t *ha)
1809 {
1810 struct sysctl_ctx_list *ctx;
1811 struct sysctl_oid_list *children;
1812 struct sysctl_oid *ctx_oid;
1813
1814 ctx = device_get_sysctl_ctx(ha->pci_dev);
1815 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev));
1816
1817 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "hwstat",
1818 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "hwstat");
1819 children = SYSCTL_CHILDREN(ctx_oid);
1820
1821 SYSCTL_ADD_QUAD(ctx, children,
1822 OID_AUTO, "no_buff_discards",
1823 CTLFLAG_RD, &ha->hw_stats.common.no_buff_discards,
1824 "No. of packets discarded due to lack of buffer");
1825
1826 SYSCTL_ADD_QUAD(ctx, children,
1827 OID_AUTO, "packet_too_big_discard",
1828 CTLFLAG_RD, &ha->hw_stats.common.packet_too_big_discard,
1829 "No. of packets discarded because packet was too big");
1830
1831 SYSCTL_ADD_QUAD(ctx, children,
1832 OID_AUTO, "ttl0_discard",
1833 CTLFLAG_RD, &ha->hw_stats.common.ttl0_discard,
1834 "ttl0_discard");
1835
1836 SYSCTL_ADD_QUAD(ctx, children,
1837 OID_AUTO, "rx_ucast_bytes",
1838 CTLFLAG_RD, &ha->hw_stats.common.rx_ucast_bytes,
1839 "rx_ucast_bytes");
1840
1841 SYSCTL_ADD_QUAD(ctx, children,
1842 OID_AUTO, "rx_mcast_bytes",
1843 CTLFLAG_RD, &ha->hw_stats.common.rx_mcast_bytes,
1844 "rx_mcast_bytes");
1845
1846 SYSCTL_ADD_QUAD(ctx, children,
1847 OID_AUTO, "rx_bcast_bytes",
1848 CTLFLAG_RD, &ha->hw_stats.common.rx_bcast_bytes,
1849 "rx_bcast_bytes");
1850
1851 SYSCTL_ADD_QUAD(ctx, children,
1852 OID_AUTO, "rx_ucast_pkts",
1853 CTLFLAG_RD, &ha->hw_stats.common.rx_ucast_pkts,
1854 "rx_ucast_pkts");
1855
1856 SYSCTL_ADD_QUAD(ctx, children,
1857 OID_AUTO, "rx_mcast_pkts",
1858 CTLFLAG_RD, &ha->hw_stats.common.rx_mcast_pkts,
1859 "rx_mcast_pkts");
1860
1861 SYSCTL_ADD_QUAD(ctx, children,
1862 OID_AUTO, "rx_bcast_pkts",
1863 CTLFLAG_RD, &ha->hw_stats.common.rx_bcast_pkts,
1864 "rx_bcast_pkts");
1865
1866 SYSCTL_ADD_QUAD(ctx, children,
1867 OID_AUTO, "mftag_filter_discards",
1868 CTLFLAG_RD, &ha->hw_stats.common.mftag_filter_discards,
1869 "mftag_filter_discards");
1870
1871 SYSCTL_ADD_QUAD(ctx, children,
1872 OID_AUTO, "mac_filter_discards",
1873 CTLFLAG_RD, &ha->hw_stats.common.mac_filter_discards,
1874 "mac_filter_discards");
1875
1876 SYSCTL_ADD_QUAD(ctx, children,
1877 OID_AUTO, "tx_ucast_bytes",
1878 CTLFLAG_RD, &ha->hw_stats.common.tx_ucast_bytes,
1879 "tx_ucast_bytes");
1880
1881 SYSCTL_ADD_QUAD(ctx, children,
1882 OID_AUTO, "tx_mcast_bytes",
1883 CTLFLAG_RD, &ha->hw_stats.common.tx_mcast_bytes,
1884 "tx_mcast_bytes");
1885
1886 SYSCTL_ADD_QUAD(ctx, children,
1887 OID_AUTO, "tx_bcast_bytes",
1888 CTLFLAG_RD, &ha->hw_stats.common.tx_bcast_bytes,
1889 "tx_bcast_bytes");
1890
1891 SYSCTL_ADD_QUAD(ctx, children,
1892 OID_AUTO, "tx_ucast_pkts",
1893 CTLFLAG_RD, &ha->hw_stats.common.tx_ucast_pkts,
1894 "tx_ucast_pkts");
1895
1896 SYSCTL_ADD_QUAD(ctx, children,
1897 OID_AUTO, "tx_mcast_pkts",
1898 CTLFLAG_RD, &ha->hw_stats.common.tx_mcast_pkts,
1899 "tx_mcast_pkts");
1900
1901 SYSCTL_ADD_QUAD(ctx, children,
1902 OID_AUTO, "tx_bcast_pkts",
1903 CTLFLAG_RD, &ha->hw_stats.common.tx_bcast_pkts,
1904 "tx_bcast_pkts");
1905
1906 SYSCTL_ADD_QUAD(ctx, children,
1907 OID_AUTO, "tx_err_drop_pkts",
1908 CTLFLAG_RD, &ha->hw_stats.common.tx_err_drop_pkts,
1909 "tx_err_drop_pkts");
1910
1911 SYSCTL_ADD_QUAD(ctx, children,
1912 OID_AUTO, "tpa_coalesced_pkts",
1913 CTLFLAG_RD, &ha->hw_stats.common.tpa_coalesced_pkts,
1914 "tpa_coalesced_pkts");
1915
1916 SYSCTL_ADD_QUAD(ctx, children,
1917 OID_AUTO, "tpa_coalesced_events",
1918 CTLFLAG_RD, &ha->hw_stats.common.tpa_coalesced_events,
1919 "tpa_coalesced_events");
1920
1921 SYSCTL_ADD_QUAD(ctx, children,
1922 OID_AUTO, "tpa_aborts_num",
1923 CTLFLAG_RD, &ha->hw_stats.common.tpa_aborts_num,
1924 "tpa_aborts_num");
1925
1926 SYSCTL_ADD_QUAD(ctx, children,
1927 OID_AUTO, "tpa_not_coalesced_pkts",
1928 CTLFLAG_RD, &ha->hw_stats.common.tpa_not_coalesced_pkts,
1929 "tpa_not_coalesced_pkts");
1930
1931 SYSCTL_ADD_QUAD(ctx, children,
1932 OID_AUTO, "tpa_coalesced_bytes",
1933 CTLFLAG_RD, &ha->hw_stats.common.tpa_coalesced_bytes,
1934 "tpa_coalesced_bytes");
1935
1936 SYSCTL_ADD_QUAD(ctx, children,
1937 OID_AUTO, "rx_64_byte_packets",
1938 CTLFLAG_RD, &ha->hw_stats.common.rx_64_byte_packets,
1939 "rx_64_byte_packets");
1940
1941 SYSCTL_ADD_QUAD(ctx, children,
1942 OID_AUTO, "rx_65_to_127_byte_packets",
1943 CTLFLAG_RD, &ha->hw_stats.common.rx_65_to_127_byte_packets,
1944 "rx_65_to_127_byte_packets");
1945
1946 SYSCTL_ADD_QUAD(ctx, children,
1947 OID_AUTO, "rx_128_to_255_byte_packets",
1948 CTLFLAG_RD, &ha->hw_stats.common.rx_128_to_255_byte_packets,
1949 "rx_128_to_255_byte_packets");
1950
1951 SYSCTL_ADD_QUAD(ctx, children,
1952 OID_AUTO, "rx_256_to_511_byte_packets",
1953 CTLFLAG_RD, &ha->hw_stats.common.rx_256_to_511_byte_packets,
1954 "rx_256_to_511_byte_packets");
1955
1956 SYSCTL_ADD_QUAD(ctx, children,
1957 OID_AUTO, "rx_512_to_1023_byte_packets",
1958 CTLFLAG_RD, &ha->hw_stats.common.rx_512_to_1023_byte_packets,
1959 "rx_512_to_1023_byte_packets");
1960
1961 SYSCTL_ADD_QUAD(ctx, children,
1962 OID_AUTO, "rx_1024_to_1518_byte_packets",
1963 CTLFLAG_RD, &ha->hw_stats.common.rx_1024_to_1518_byte_packets,
1964 "rx_1024_to_1518_byte_packets");
1965
1966 SYSCTL_ADD_QUAD(ctx, children,
1967 OID_AUTO, "rx_1519_to_1522_byte_packets",
1968 CTLFLAG_RD, &ha->hw_stats.bb.rx_1519_to_1522_byte_packets,
1969 "rx_1519_to_1522_byte_packets");
1970
1971 SYSCTL_ADD_QUAD(ctx, children,
1972 OID_AUTO, "rx_1523_to_2047_byte_packets",
1973 CTLFLAG_RD, &ha->hw_stats.bb.rx_1519_to_2047_byte_packets,
1974 "rx_1523_to_2047_byte_packets");
1975
1976 SYSCTL_ADD_QUAD(ctx, children,
1977 OID_AUTO, "rx_2048_to_4095_byte_packets",
1978 CTLFLAG_RD, &ha->hw_stats.bb.rx_2048_to_4095_byte_packets,
1979 "rx_2048_to_4095_byte_packets");
1980
1981 SYSCTL_ADD_QUAD(ctx, children,
1982 OID_AUTO, "rx_4096_to_9216_byte_packets",
1983 CTLFLAG_RD, &ha->hw_stats.bb.rx_4096_to_9216_byte_packets,
1984 "rx_4096_to_9216_byte_packets");
1985
1986 SYSCTL_ADD_QUAD(ctx, children,
1987 OID_AUTO, "rx_9217_to_16383_byte_packets",
1988 CTLFLAG_RD, &ha->hw_stats.bb.rx_9217_to_16383_byte_packets,
1989 "rx_9217_to_16383_byte_packets");
1990
1991 SYSCTL_ADD_QUAD(ctx, children,
1992 OID_AUTO, "rx_crc_errors",
1993 CTLFLAG_RD, &ha->hw_stats.common.rx_crc_errors,
1994 "rx_crc_errors");
1995
1996 SYSCTL_ADD_QUAD(ctx, children,
1997 OID_AUTO, "rx_mac_crtl_frames",
1998 CTLFLAG_RD, &ha->hw_stats.common.rx_mac_crtl_frames,
1999 "rx_mac_crtl_frames");
2000
2001 SYSCTL_ADD_QUAD(ctx, children,
2002 OID_AUTO, "rx_pause_frames",
2003 CTLFLAG_RD, &ha->hw_stats.common.rx_pause_frames,
2004 "rx_pause_frames");
2005
2006 SYSCTL_ADD_QUAD(ctx, children,
2007 OID_AUTO, "rx_pfc_frames",
2008 CTLFLAG_RD, &ha->hw_stats.common.rx_pfc_frames,
2009 "rx_pfc_frames");
2010
2011 SYSCTL_ADD_QUAD(ctx, children,
2012 OID_AUTO, "rx_align_errors",
2013 CTLFLAG_RD, &ha->hw_stats.common.rx_align_errors,
2014 "rx_align_errors");
2015
2016 SYSCTL_ADD_QUAD(ctx, children,
2017 OID_AUTO, "rx_carrier_errors",
2018 CTLFLAG_RD, &ha->hw_stats.common.rx_carrier_errors,
2019 "rx_carrier_errors");
2020
2021 SYSCTL_ADD_QUAD(ctx, children,
2022 OID_AUTO, "rx_oversize_packets",
2023 CTLFLAG_RD, &ha->hw_stats.common.rx_oversize_packets,
2024 "rx_oversize_packets");
2025
2026 SYSCTL_ADD_QUAD(ctx, children,
2027 OID_AUTO, "rx_jabbers",
2028 CTLFLAG_RD, &ha->hw_stats.common.rx_jabbers,
2029 "rx_jabbers");
2030
2031 SYSCTL_ADD_QUAD(ctx, children,
2032 OID_AUTO, "rx_undersize_packets",
2033 CTLFLAG_RD, &ha->hw_stats.common.rx_undersize_packets,
2034 "rx_undersize_packets");
2035
2036 SYSCTL_ADD_QUAD(ctx, children,
2037 OID_AUTO, "rx_fragments",
2038 CTLFLAG_RD, &ha->hw_stats.common.rx_fragments,
2039 "rx_fragments");
2040
2041 SYSCTL_ADD_QUAD(ctx, children,
2042 OID_AUTO, "tx_64_byte_packets",
2043 CTLFLAG_RD, &ha->hw_stats.common.tx_64_byte_packets,
2044 "tx_64_byte_packets");
2045
2046 SYSCTL_ADD_QUAD(ctx, children,
2047 OID_AUTO, "tx_65_to_127_byte_packets",
2048 CTLFLAG_RD, &ha->hw_stats.common.tx_65_to_127_byte_packets,
2049 "tx_65_to_127_byte_packets");
2050
2051 SYSCTL_ADD_QUAD(ctx, children,
2052 OID_AUTO, "tx_128_to_255_byte_packets",
2053 CTLFLAG_RD, &ha->hw_stats.common.tx_128_to_255_byte_packets,
2054 "tx_128_to_255_byte_packets");
2055
2056 SYSCTL_ADD_QUAD(ctx, children,
2057 OID_AUTO, "tx_256_to_511_byte_packets",
2058 CTLFLAG_RD, &ha->hw_stats.common.tx_256_to_511_byte_packets,
2059 "tx_256_to_511_byte_packets");
2060
2061 SYSCTL_ADD_QUAD(ctx, children,
2062 OID_AUTO, "tx_512_to_1023_byte_packets",
2063 CTLFLAG_RD, &ha->hw_stats.common.tx_512_to_1023_byte_packets,
2064 "tx_512_to_1023_byte_packets");
2065
2066 SYSCTL_ADD_QUAD(ctx, children,
2067 OID_AUTO, "tx_1024_to_1518_byte_packets",
2068 CTLFLAG_RD, &ha->hw_stats.common.tx_1024_to_1518_byte_packets,
2069 "tx_1024_to_1518_byte_packets");
2070
2071 SYSCTL_ADD_QUAD(ctx, children,
2072 OID_AUTO, "tx_1519_to_2047_byte_packets",
2073 CTLFLAG_RD, &ha->hw_stats.bb.tx_1519_to_2047_byte_packets,
2074 "tx_1519_to_2047_byte_packets");
2075
2076 SYSCTL_ADD_QUAD(ctx, children,
2077 OID_AUTO, "tx_2048_to_4095_byte_packets",
2078 CTLFLAG_RD, &ha->hw_stats.bb.tx_2048_to_4095_byte_packets,
2079 "tx_2048_to_4095_byte_packets");
2080
2081 SYSCTL_ADD_QUAD(ctx, children,
2082 OID_AUTO, "tx_4096_to_9216_byte_packets",
2083 CTLFLAG_RD, &ha->hw_stats.bb.tx_4096_to_9216_byte_packets,
2084 "tx_4096_to_9216_byte_packets");
2085
2086 SYSCTL_ADD_QUAD(ctx, children,
2087 OID_AUTO, "tx_9217_to_16383_byte_packets",
2088 CTLFLAG_RD, &ha->hw_stats.bb.tx_9217_to_16383_byte_packets,
2089 "tx_9217_to_16383_byte_packets");
2090
2091 SYSCTL_ADD_QUAD(ctx, children,
2092 OID_AUTO, "tx_pause_frames",
2093 CTLFLAG_RD, &ha->hw_stats.common.tx_pause_frames,
2094 "tx_pause_frames");
2095
2096 SYSCTL_ADD_QUAD(ctx, children,
2097 OID_AUTO, "tx_pfc_frames",
2098 CTLFLAG_RD, &ha->hw_stats.common.tx_pfc_frames,
2099 "tx_pfc_frames");
2100
2101 SYSCTL_ADD_QUAD(ctx, children,
2102 OID_AUTO, "tx_lpi_entry_count",
2103 CTLFLAG_RD, &ha->hw_stats.bb.tx_lpi_entry_count,
2104 "tx_lpi_entry_count");
2105
2106 SYSCTL_ADD_QUAD(ctx, children,
2107 OID_AUTO, "tx_total_collisions",
2108 CTLFLAG_RD, &ha->hw_stats.bb.tx_total_collisions,
2109 "tx_total_collisions");
2110
2111 SYSCTL_ADD_QUAD(ctx, children,
2112 OID_AUTO, "brb_truncates",
2113 CTLFLAG_RD, &ha->hw_stats.common.brb_truncates,
2114 "brb_truncates");
2115
2116 SYSCTL_ADD_QUAD(ctx, children,
2117 OID_AUTO, "brb_discards",
2118 CTLFLAG_RD, &ha->hw_stats.common.brb_discards,
2119 "brb_discards");
2120
2121 SYSCTL_ADD_QUAD(ctx, children,
2122 OID_AUTO, "rx_mac_bytes",
2123 CTLFLAG_RD, &ha->hw_stats.common.rx_mac_bytes,
2124 "rx_mac_bytes");
2125
2126 SYSCTL_ADD_QUAD(ctx, children,
2127 OID_AUTO, "rx_mac_uc_packets",
2128 CTLFLAG_RD, &ha->hw_stats.common.rx_mac_uc_packets,
2129 "rx_mac_uc_packets");
2130
2131 SYSCTL_ADD_QUAD(ctx, children,
2132 OID_AUTO, "rx_mac_mc_packets",
2133 CTLFLAG_RD, &ha->hw_stats.common.rx_mac_mc_packets,
2134 "rx_mac_mc_packets");
2135
2136 SYSCTL_ADD_QUAD(ctx, children,
2137 OID_AUTO, "rx_mac_bc_packets",
2138 CTLFLAG_RD, &ha->hw_stats.common.rx_mac_bc_packets,
2139 "rx_mac_bc_packets");
2140
2141 SYSCTL_ADD_QUAD(ctx, children,
2142 OID_AUTO, "rx_mac_frames_ok",
2143 CTLFLAG_RD, &ha->hw_stats.common.rx_mac_frames_ok,
2144 "rx_mac_frames_ok");
2145
2146 SYSCTL_ADD_QUAD(ctx, children,
2147 OID_AUTO, "tx_mac_bytes",
2148 CTLFLAG_RD, &ha->hw_stats.common.tx_mac_bytes,
2149 "tx_mac_bytes");
2150
2151 SYSCTL_ADD_QUAD(ctx, children,
2152 OID_AUTO, "tx_mac_uc_packets",
2153 CTLFLAG_RD, &ha->hw_stats.common.tx_mac_uc_packets,
2154 "tx_mac_uc_packets");
2155
2156 SYSCTL_ADD_QUAD(ctx, children,
2157 OID_AUTO, "tx_mac_mc_packets",
2158 CTLFLAG_RD, &ha->hw_stats.common.tx_mac_mc_packets,
2159 "tx_mac_mc_packets");
2160
2161 SYSCTL_ADD_QUAD(ctx, children,
2162 OID_AUTO, "tx_mac_bc_packets",
2163 CTLFLAG_RD, &ha->hw_stats.common.tx_mac_bc_packets,
2164 "tx_mac_bc_packets");
2165
2166 SYSCTL_ADD_QUAD(ctx, children,
2167 OID_AUTO, "tx_mac_ctrl_frames",
2168 CTLFLAG_RD, &ha->hw_stats.common.tx_mac_ctrl_frames,
2169 "tx_mac_ctrl_frames");
2170 return;
2171 }
2172
2173 static void
qlnx_add_sysctls(qlnx_host_t * ha)2174 qlnx_add_sysctls(qlnx_host_t *ha)
2175 {
2176 device_t dev = ha->pci_dev;
2177 struct sysctl_ctx_list *ctx;
2178 struct sysctl_oid_list *children;
2179
2180 ctx = device_get_sysctl_ctx(dev);
2181 children = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
2182
2183 qlnx_add_fp_stats_sysctls(ha);
2184 qlnx_add_sp_stats_sysctls(ha);
2185
2186 if (qlnx_vf_device(ha) != 0)
2187 qlnx_add_hw_stats_sysctls(ha);
2188
2189 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "Driver_Version",
2190 CTLFLAG_RD, qlnx_ver_str, 0,
2191 "Driver Version");
2192
2193 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "STORMFW_Version",
2194 CTLFLAG_RD, ha->stormfw_ver, 0,
2195 "STORM Firmware Version");
2196
2197 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "MFW_Version",
2198 CTLFLAG_RD, ha->mfw_ver, 0,
2199 "Management Firmware Version");
2200
2201 SYSCTL_ADD_UINT(ctx, children,
2202 OID_AUTO, "personality", CTLFLAG_RD,
2203 &ha->personality, ha->personality,
2204 "\tpersonality = 0 => Ethernet Only\n"
2205 "\tpersonality = 3 => Ethernet and RoCE\n"
2206 "\tpersonality = 4 => Ethernet and iWARP\n"
2207 "\tpersonality = 6 => Default in Shared Memory\n");
2208
2209 ha->dbg_level = 0;
2210 SYSCTL_ADD_UINT(ctx, children,
2211 OID_AUTO, "debug", CTLFLAG_RW,
2212 &ha->dbg_level, ha->dbg_level, "Debug Level");
2213
2214 ha->dp_level = 0x01;
2215 SYSCTL_ADD_UINT(ctx, children,
2216 OID_AUTO, "dp_level", CTLFLAG_RW,
2217 &ha->dp_level, ha->dp_level, "DP Level");
2218
2219 ha->dbg_trace_lro_cnt = 0;
2220 SYSCTL_ADD_UINT(ctx, children,
2221 OID_AUTO, "dbg_trace_lro_cnt", CTLFLAG_RW,
2222 &ha->dbg_trace_lro_cnt, ha->dbg_trace_lro_cnt,
2223 "Trace LRO Counts");
2224
2225 ha->dbg_trace_tso_pkt_len = 0;
2226 SYSCTL_ADD_UINT(ctx, children,
2227 OID_AUTO, "dbg_trace_tso_pkt_len", CTLFLAG_RW,
2228 &ha->dbg_trace_tso_pkt_len, ha->dbg_trace_tso_pkt_len,
2229 "Trace TSO packet lengths");
2230
2231 ha->dp_module = 0;
2232 SYSCTL_ADD_UINT(ctx, children,
2233 OID_AUTO, "dp_module", CTLFLAG_RW,
2234 &ha->dp_module, ha->dp_module, "DP Module");
2235
2236 ha->err_inject = 0;
2237
2238 SYSCTL_ADD_UINT(ctx, children,
2239 OID_AUTO, "err_inject", CTLFLAG_RW,
2240 &ha->err_inject, ha->err_inject, "Error Inject");
2241
2242 ha->storm_stats_enable = 0;
2243
2244 SYSCTL_ADD_UINT(ctx, children,
2245 OID_AUTO, "storm_stats_enable", CTLFLAG_RW,
2246 &ha->storm_stats_enable, ha->storm_stats_enable,
2247 "Enable Storm Statistics Gathering");
2248
2249 ha->storm_stats_index = 0;
2250
2251 SYSCTL_ADD_UINT(ctx, children,
2252 OID_AUTO, "storm_stats_index", CTLFLAG_RD,
2253 &ha->storm_stats_index, ha->storm_stats_index,
2254 "Enable Storm Statistics Gathering Current Index");
2255
2256 ha->grcdump_taken = 0;
2257 SYSCTL_ADD_UINT(ctx, children,
2258 OID_AUTO, "grcdump_taken", CTLFLAG_RD,
2259 &ha->grcdump_taken, ha->grcdump_taken,
2260 "grcdump_taken");
2261
2262 ha->idle_chk_taken = 0;
2263 SYSCTL_ADD_UINT(ctx, children,
2264 OID_AUTO, "idle_chk_taken", CTLFLAG_RD,
2265 &ha->idle_chk_taken, ha->idle_chk_taken,
2266 "idle_chk_taken");
2267
2268 SYSCTL_ADD_UINT(ctx, children,
2269 OID_AUTO, "rx_coalesce_usecs", CTLFLAG_RD,
2270 &ha->rx_coalesce_usecs, ha->rx_coalesce_usecs,
2271 "rx_coalesce_usecs");
2272
2273 SYSCTL_ADD_UINT(ctx, children,
2274 OID_AUTO, "tx_coalesce_usecs", CTLFLAG_RD,
2275 &ha->tx_coalesce_usecs, ha->tx_coalesce_usecs,
2276 "tx_coalesce_usecs");
2277
2278 SYSCTL_ADD_PROC(ctx, children,
2279 OID_AUTO, "trigger_dump",
2280 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
2281 (void *)ha, 0, qlnx_trigger_dump_sysctl, "I", "trigger_dump");
2282
2283 SYSCTL_ADD_PROC(ctx, children,
2284 OID_AUTO, "set_rx_coalesce_usecs",
2285 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
2286 (void *)ha, 0, qlnx_set_rx_coalesce, "I",
2287 "rx interrupt coalesce period microseconds");
2288
2289 SYSCTL_ADD_PROC(ctx, children,
2290 OID_AUTO, "set_tx_coalesce_usecs",
2291 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
2292 (void *)ha, 0, qlnx_set_tx_coalesce, "I",
2293 "tx interrupt coalesce period microseconds");
2294
2295 ha->rx_pkt_threshold = 128;
2296 SYSCTL_ADD_UINT(ctx, children,
2297 OID_AUTO, "rx_pkt_threshold", CTLFLAG_RW,
2298 &ha->rx_pkt_threshold, ha->rx_pkt_threshold,
2299 "No. of Rx Pkts to process at a time");
2300
2301 ha->rx_jumbo_buf_eq_mtu = 0;
2302 SYSCTL_ADD_UINT(ctx, children,
2303 OID_AUTO, "rx_jumbo_buf_eq_mtu", CTLFLAG_RW,
2304 &ha->rx_jumbo_buf_eq_mtu, ha->rx_jumbo_buf_eq_mtu,
2305 "== 0 => Rx Jumbo buffers are capped to 4Kbytes\n"
2306 "otherwise Rx Jumbo buffers are set to >= MTU size\n");
2307
2308 SYSCTL_ADD_QUAD(ctx, children,
2309 OID_AUTO, "err_illegal_intr", CTLFLAG_RD,
2310 &ha->err_illegal_intr, "err_illegal_intr");
2311
2312 SYSCTL_ADD_QUAD(ctx, children,
2313 OID_AUTO, "err_fp_null", CTLFLAG_RD,
2314 &ha->err_fp_null, "err_fp_null");
2315
2316 SYSCTL_ADD_QUAD(ctx, children,
2317 OID_AUTO, "err_get_proto_invalid_type", CTLFLAG_RD,
2318 &ha->err_get_proto_invalid_type, "err_get_proto_invalid_type");
2319 return;
2320 }
2321
2322 /*****************************************************************************
2323 * Operating System Network Interface Functions
2324 *****************************************************************************/
2325
2326 static void
qlnx_init_ifnet(device_t dev,qlnx_host_t * ha)2327 qlnx_init_ifnet(device_t dev, qlnx_host_t *ha)
2328 {
2329 uint16_t device_id;
2330 struct ifnet *ifp;
2331
2332 ifp = ha->ifp = if_alloc(IFT_ETHER);
2333 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2334
2335 device_id = pci_get_device(ha->pci_dev);
2336
2337 #if __FreeBSD_version >= 1000000
2338
2339 if (device_id == QLOGIC_PCI_DEVICE_ID_1634)
2340 ifp->if_baudrate = IF_Gbps(40);
2341 else if ((device_id == QLOGIC_PCI_DEVICE_ID_1656) ||
2342 (device_id == QLOGIC_PCI_DEVICE_ID_8070))
2343 ifp->if_baudrate = IF_Gbps(25);
2344 else if (device_id == QLOGIC_PCI_DEVICE_ID_1654)
2345 ifp->if_baudrate = IF_Gbps(50);
2346 else if (device_id == QLOGIC_PCI_DEVICE_ID_1644)
2347 ifp->if_baudrate = IF_Gbps(100);
2348
2349 ifp->if_capabilities = IFCAP_LINKSTATE;
2350 #else
2351 ifp->if_mtu = ETHERMTU;
2352 ifp->if_baudrate = (1 * 1000 * 1000 *1000);
2353
2354 #endif /* #if __FreeBSD_version >= 1000000 */
2355
2356 ifp->if_init = qlnx_init;
2357 ifp->if_softc = ha;
2358 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2359 ifp->if_ioctl = qlnx_ioctl;
2360 ifp->if_transmit = qlnx_transmit;
2361 ifp->if_qflush = qlnx_qflush;
2362
2363 IFQ_SET_MAXLEN(&ifp->if_snd, qlnx_get_ifq_snd_maxlen(ha));
2364 ifp->if_snd.ifq_drv_maxlen = qlnx_get_ifq_snd_maxlen(ha);
2365 IFQ_SET_READY(&ifp->if_snd);
2366
2367 #if __FreeBSD_version >= 1100036
2368 if_setgetcounterfn(ifp, qlnx_get_counter);
2369 #endif
2370
2371 ha->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2372
2373 memcpy(ha->primary_mac, qlnx_get_mac_addr(ha), ETH_ALEN);
2374
2375 if (!ha->primary_mac[0] && !ha->primary_mac[1] &&
2376 !ha->primary_mac[2] && !ha->primary_mac[3] &&
2377 !ha->primary_mac[4] && !ha->primary_mac[5]) {
2378 uint32_t rnd;
2379
2380 rnd = arc4random();
2381
2382 ha->primary_mac[0] = 0x00;
2383 ha->primary_mac[1] = 0x0e;
2384 ha->primary_mac[2] = 0x1e;
2385 ha->primary_mac[3] = rnd & 0xFF;
2386 ha->primary_mac[4] = (rnd >> 8) & 0xFF;
2387 ha->primary_mac[5] = (rnd >> 16) & 0xFF;
2388 }
2389
2390 ether_ifattach(ifp, ha->primary_mac);
2391 bcopy(IF_LLADDR(ha->ifp), ha->primary_mac, ETHER_ADDR_LEN);
2392
2393 ifp->if_capabilities = IFCAP_HWCSUM;
2394 ifp->if_capabilities |= IFCAP_JUMBO_MTU;
2395
2396 ifp->if_capabilities |= IFCAP_VLAN_MTU;
2397 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
2398 ifp->if_capabilities |= IFCAP_VLAN_HWFILTER;
2399 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
2400 ifp->if_capabilities |= IFCAP_VLAN_HWTSO;
2401 ifp->if_capabilities |= IFCAP_TSO4;
2402 ifp->if_capabilities |= IFCAP_TSO6;
2403 ifp->if_capabilities |= IFCAP_LRO;
2404
2405 ifp->if_hw_tsomax = QLNX_MAX_TSO_FRAME_SIZE -
2406 (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
2407 ifp->if_hw_tsomaxsegcount = QLNX_MAX_SEGMENTS - 1 /* hdr */;
2408 ifp->if_hw_tsomaxsegsize = QLNX_MAX_TX_MBUF_SIZE;
2409
2410 ifp->if_capenable = ifp->if_capabilities;
2411
2412 ifp->if_hwassist = CSUM_IP;
2413 ifp->if_hwassist |= CSUM_TCP | CSUM_UDP;
2414 ifp->if_hwassist |= CSUM_TCP_IPV6 | CSUM_UDP_IPV6;
2415 ifp->if_hwassist |= CSUM_TSO;
2416
2417 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
2418
2419 ifmedia_init(&ha->media, IFM_IMASK, qlnx_media_change,\
2420 qlnx_media_status);
2421
2422 if (device_id == QLOGIC_PCI_DEVICE_ID_1634) {
2423 ifmedia_add(&ha->media, (IFM_ETHER | IFM_40G_LR4), 0, NULL);
2424 ifmedia_add(&ha->media, (IFM_ETHER | IFM_40G_SR4), 0, NULL);
2425 ifmedia_add(&ha->media, (IFM_ETHER | IFM_40G_CR4), 0, NULL);
2426 } else if ((device_id == QLOGIC_PCI_DEVICE_ID_1656) ||
2427 (device_id == QLOGIC_PCI_DEVICE_ID_8070)) {
2428 ifmedia_add(&ha->media, (IFM_ETHER | QLNX_IFM_25G_SR), 0, NULL);
2429 ifmedia_add(&ha->media, (IFM_ETHER | QLNX_IFM_25G_CR), 0, NULL);
2430 } else if (device_id == QLOGIC_PCI_DEVICE_ID_1654) {
2431 ifmedia_add(&ha->media, (IFM_ETHER | IFM_50G_KR2), 0, NULL);
2432 ifmedia_add(&ha->media, (IFM_ETHER | IFM_50G_CR2), 0, NULL);
2433 } else if (device_id == QLOGIC_PCI_DEVICE_ID_1644) {
2434 ifmedia_add(&ha->media,
2435 (IFM_ETHER | QLNX_IFM_100G_LR4), 0, NULL);
2436 ifmedia_add(&ha->media,
2437 (IFM_ETHER | QLNX_IFM_100G_SR4), 0, NULL);
2438 ifmedia_add(&ha->media,
2439 (IFM_ETHER | QLNX_IFM_100G_CR4), 0, NULL);
2440 }
2441
2442 ifmedia_add(&ha->media, (IFM_ETHER | IFM_FDX), 0, NULL);
2443 ifmedia_add(&ha->media, (IFM_ETHER | IFM_AUTO), 0, NULL);
2444
2445 ifmedia_set(&ha->media, (IFM_ETHER | IFM_AUTO));
2446
2447 QL_DPRINT2(ha, "exit\n");
2448
2449 return;
2450 }
2451
2452 static void
qlnx_init_locked(qlnx_host_t * ha)2453 qlnx_init_locked(qlnx_host_t *ha)
2454 {
2455 struct ifnet *ifp = ha->ifp;
2456
2457 QL_DPRINT1(ha, "Driver Initialization start \n");
2458
2459 qlnx_stop(ha);
2460
2461 if (qlnx_load(ha) == 0) {
2462 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2463 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2464
2465 #ifdef QLNX_ENABLE_IWARP
2466 if (qlnx_vf_device(ha) != 0) {
2467 qlnx_rdma_dev_open(ha);
2468 }
2469 #endif /* #ifdef QLNX_ENABLE_IWARP */
2470 }
2471
2472 return;
2473 }
2474
2475 static void
qlnx_init(void * arg)2476 qlnx_init(void *arg)
2477 {
2478 qlnx_host_t *ha;
2479
2480 ha = (qlnx_host_t *)arg;
2481
2482 QL_DPRINT2(ha, "enter\n");
2483
2484 QLNX_LOCK(ha);
2485 qlnx_init_locked(ha);
2486 QLNX_UNLOCK(ha);
2487
2488 QL_DPRINT2(ha, "exit\n");
2489
2490 return;
2491 }
2492
2493 static int
qlnx_config_mcast_mac_addr(qlnx_host_t * ha,uint8_t * mac_addr,uint32_t add_mac)2494 qlnx_config_mcast_mac_addr(qlnx_host_t *ha, uint8_t *mac_addr, uint32_t add_mac)
2495 {
2496 struct ecore_filter_mcast *mcast;
2497 struct ecore_dev *cdev;
2498 int rc;
2499
2500 cdev = &ha->cdev;
2501
2502 mcast = &ha->ecore_mcast;
2503 bzero(mcast, sizeof(struct ecore_filter_mcast));
2504
2505 if (add_mac)
2506 mcast->opcode = ECORE_FILTER_ADD;
2507 else
2508 mcast->opcode = ECORE_FILTER_REMOVE;
2509
2510 mcast->num_mc_addrs = 1;
2511 memcpy(mcast->mac, mac_addr, ETH_ALEN);
2512
2513 rc = ecore_filter_mcast_cmd(cdev, mcast, ECORE_SPQ_MODE_CB, NULL);
2514
2515 return (rc);
2516 }
2517
2518 static int
qlnx_hw_add_mcast(qlnx_host_t * ha,uint8_t * mta)2519 qlnx_hw_add_mcast(qlnx_host_t *ha, uint8_t *mta)
2520 {
2521 int i;
2522
2523 for (i = 0; i < QLNX_MAX_NUM_MULTICAST_ADDRS; i++) {
2524 if (QL_MAC_CMP(ha->mcast[i].addr, mta) == 0)
2525 return 0; /* its been already added */
2526 }
2527
2528 for (i = 0; i < QLNX_MAX_NUM_MULTICAST_ADDRS; i++) {
2529 if ((ha->mcast[i].addr[0] == 0) &&
2530 (ha->mcast[i].addr[1] == 0) &&
2531 (ha->mcast[i].addr[2] == 0) &&
2532 (ha->mcast[i].addr[3] == 0) &&
2533 (ha->mcast[i].addr[4] == 0) &&
2534 (ha->mcast[i].addr[5] == 0)) {
2535 if (qlnx_config_mcast_mac_addr(ha, mta, 1))
2536 return (-1);
2537
2538 bcopy(mta, ha->mcast[i].addr, ETH_ALEN);
2539 ha->nmcast++;
2540
2541 return 0;
2542 }
2543 }
2544 return 0;
2545 }
2546
2547 static int
qlnx_hw_del_mcast(qlnx_host_t * ha,uint8_t * mta)2548 qlnx_hw_del_mcast(qlnx_host_t *ha, uint8_t *mta)
2549 {
2550 int i;
2551
2552 for (i = 0; i < QLNX_MAX_NUM_MULTICAST_ADDRS; i++) {
2553 if (QL_MAC_CMP(ha->mcast[i].addr, mta) == 0) {
2554 if (qlnx_config_mcast_mac_addr(ha, mta, 0))
2555 return (-1);
2556
2557 ha->mcast[i].addr[0] = 0;
2558 ha->mcast[i].addr[1] = 0;
2559 ha->mcast[i].addr[2] = 0;
2560 ha->mcast[i].addr[3] = 0;
2561 ha->mcast[i].addr[4] = 0;
2562 ha->mcast[i].addr[5] = 0;
2563
2564 ha->nmcast--;
2565
2566 return 0;
2567 }
2568 }
2569 return 0;
2570 }
2571
2572 /*
2573 * Name: qls_hw_set_multi
2574 * Function: Sets the Multicast Addresses provided the host O.S into the
2575 * hardware (for the given interface)
2576 */
2577 static void
qlnx_hw_set_multi(qlnx_host_t * ha,uint8_t * mta,uint32_t mcnt,uint32_t add_mac)2578 qlnx_hw_set_multi(qlnx_host_t *ha, uint8_t *mta, uint32_t mcnt,
2579 uint32_t add_mac)
2580 {
2581 int i;
2582
2583 for (i = 0; i < mcnt; i++) {
2584 if (add_mac) {
2585 if (qlnx_hw_add_mcast(ha, mta))
2586 break;
2587 } else {
2588 if (qlnx_hw_del_mcast(ha, mta))
2589 break;
2590 }
2591
2592 mta += ETHER_HDR_LEN;
2593 }
2594 return;
2595 }
2596
2597 static u_int
qlnx_copy_maddr(void * arg,struct sockaddr_dl * sdl,u_int mcnt)2598 qlnx_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int mcnt)
2599 {
2600 uint8_t *mta = arg;
2601
2602 if (mcnt == QLNX_MAX_NUM_MULTICAST_ADDRS)
2603 return (0);
2604
2605 bcopy(LLADDR(sdl), &mta[mcnt * ETHER_HDR_LEN], ETHER_HDR_LEN);
2606
2607 return (1);
2608 }
2609
2610 static int
qlnx_set_multi(qlnx_host_t * ha,uint32_t add_multi)2611 qlnx_set_multi(qlnx_host_t *ha, uint32_t add_multi)
2612 {
2613 uint8_t mta[QLNX_MAX_NUM_MULTICAST_ADDRS * ETHER_HDR_LEN];
2614 struct ifnet *ifp = ha->ifp;
2615 u_int mcnt;
2616
2617 if (qlnx_vf_device(ha) == 0)
2618 return (0);
2619
2620 mcnt = if_foreach_llmaddr(ifp, qlnx_copy_maddr, mta);
2621
2622 QLNX_LOCK(ha);
2623 qlnx_hw_set_multi(ha, mta, mcnt, add_multi);
2624 QLNX_UNLOCK(ha);
2625
2626 return (0);
2627 }
2628
2629 static int
qlnx_set_promisc(qlnx_host_t * ha)2630 qlnx_set_promisc(qlnx_host_t *ha)
2631 {
2632 int rc = 0;
2633 uint8_t filter;
2634
2635 if (qlnx_vf_device(ha) == 0)
2636 return (0);
2637
2638 filter = ha->filter;
2639 filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
2640 filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
2641
2642 rc = qlnx_set_rx_accept_filter(ha, filter);
2643 return (rc);
2644 }
2645
2646 static int
qlnx_set_allmulti(qlnx_host_t * ha)2647 qlnx_set_allmulti(qlnx_host_t *ha)
2648 {
2649 int rc = 0;
2650 uint8_t filter;
2651
2652 if (qlnx_vf_device(ha) == 0)
2653 return (0);
2654
2655 filter = ha->filter;
2656 filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
2657 rc = qlnx_set_rx_accept_filter(ha, filter);
2658
2659 return (rc);
2660 }
2661
2662 static int
qlnx_ioctl(struct ifnet * ifp,u_long cmd,caddr_t data)2663 qlnx_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
2664 {
2665 int ret = 0, mask;
2666 struct ifreq *ifr = (struct ifreq *)data;
2667 struct ifaddr *ifa = (struct ifaddr *)data;
2668 qlnx_host_t *ha;
2669
2670 ha = (qlnx_host_t *)ifp->if_softc;
2671
2672 switch (cmd) {
2673 case SIOCSIFADDR:
2674 QL_DPRINT4(ha, "SIOCSIFADDR (0x%lx)\n", cmd);
2675
2676 if (ifa->ifa_addr->sa_family == AF_INET) {
2677 ifp->if_flags |= IFF_UP;
2678 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2679 QLNX_LOCK(ha);
2680 qlnx_init_locked(ha);
2681 QLNX_UNLOCK(ha);
2682 }
2683 QL_DPRINT4(ha, "SIOCSIFADDR (0x%lx) ipv4 [0x%08x]\n",
2684 cmd, ntohl(IA_SIN(ifa)->sin_addr.s_addr));
2685
2686 arp_ifinit(ifp, ifa);
2687 } else {
2688 ether_ioctl(ifp, cmd, data);
2689 }
2690 break;
2691
2692 case SIOCSIFMTU:
2693 QL_DPRINT4(ha, "SIOCSIFMTU (0x%lx)\n", cmd);
2694
2695 if (ifr->ifr_mtu > QLNX_MAX_MTU) {
2696 ret = EINVAL;
2697 } else {
2698 QLNX_LOCK(ha);
2699 ifp->if_mtu = ifr->ifr_mtu;
2700 ha->max_frame_size =
2701 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2702 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2703 qlnx_init_locked(ha);
2704 }
2705
2706 QLNX_UNLOCK(ha);
2707 }
2708
2709 break;
2710
2711 case SIOCSIFFLAGS:
2712 QL_DPRINT4(ha, "SIOCSIFFLAGS (0x%lx)\n", cmd);
2713
2714 QLNX_LOCK(ha);
2715
2716 if (ifp->if_flags & IFF_UP) {
2717 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2718 if ((ifp->if_flags ^ ha->if_flags) &
2719 IFF_PROMISC) {
2720 ret = qlnx_set_promisc(ha);
2721 } else if ((ifp->if_flags ^ ha->if_flags) &
2722 IFF_ALLMULTI) {
2723 ret = qlnx_set_allmulti(ha);
2724 }
2725 } else {
2726 ha->max_frame_size = ifp->if_mtu +
2727 ETHER_HDR_LEN + ETHER_CRC_LEN;
2728 qlnx_init_locked(ha);
2729 }
2730 } else {
2731 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2732 qlnx_stop(ha);
2733 ha->if_flags = ifp->if_flags;
2734 }
2735
2736 QLNX_UNLOCK(ha);
2737 break;
2738
2739 case SIOCADDMULTI:
2740 QL_DPRINT4(ha, "%s (0x%lx)\n", "SIOCADDMULTI", cmd);
2741
2742 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2743 if (qlnx_set_multi(ha, 1))
2744 ret = EINVAL;
2745 }
2746 break;
2747
2748 case SIOCDELMULTI:
2749 QL_DPRINT4(ha, "%s (0x%lx)\n", "SIOCDELMULTI", cmd);
2750
2751 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2752 if (qlnx_set_multi(ha, 0))
2753 ret = EINVAL;
2754 }
2755 break;
2756
2757 case SIOCSIFMEDIA:
2758 case SIOCGIFMEDIA:
2759 QL_DPRINT4(ha, "SIOCSIFMEDIA/SIOCGIFMEDIA (0x%lx)\n", cmd);
2760
2761 ret = ifmedia_ioctl(ifp, ifr, &ha->media, cmd);
2762 break;
2763
2764 case SIOCSIFCAP:
2765
2766 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2767
2768 QL_DPRINT4(ha, "SIOCSIFCAP (0x%lx)\n", cmd);
2769
2770 if (mask & IFCAP_HWCSUM)
2771 ifp->if_capenable ^= IFCAP_HWCSUM;
2772 if (mask & IFCAP_TSO4)
2773 ifp->if_capenable ^= IFCAP_TSO4;
2774 if (mask & IFCAP_TSO6)
2775 ifp->if_capenable ^= IFCAP_TSO6;
2776 if (mask & IFCAP_VLAN_HWTAGGING)
2777 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2778 if (mask & IFCAP_VLAN_HWTSO)
2779 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2780 if (mask & IFCAP_LRO)
2781 ifp->if_capenable ^= IFCAP_LRO;
2782
2783 QLNX_LOCK(ha);
2784
2785 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2786 qlnx_init_locked(ha);
2787
2788 QLNX_UNLOCK(ha);
2789
2790 VLAN_CAPABILITIES(ifp);
2791 break;
2792
2793 #if (__FreeBSD_version >= 1100101)
2794
2795 case SIOCGI2C:
2796 {
2797 struct ifi2creq i2c;
2798 struct ecore_hwfn *p_hwfn = &ha->cdev.hwfns[0];
2799 struct ecore_ptt *p_ptt;
2800
2801 ret = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
2802
2803 if (ret)
2804 break;
2805
2806 if ((i2c.len > sizeof (i2c.data)) ||
2807 (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2)) {
2808 ret = EINVAL;
2809 break;
2810 }
2811
2812 p_ptt = ecore_ptt_acquire(p_hwfn);
2813
2814 if (!p_ptt) {
2815 QL_DPRINT1(ha, "ecore_ptt_acquire failed\n");
2816 ret = -1;
2817 break;
2818 }
2819
2820 ret = ecore_mcp_phy_sfp_read(p_hwfn, p_ptt,
2821 (ha->pci_func & 0x1), i2c.dev_addr, i2c.offset,
2822 i2c.len, &i2c.data[0]);
2823
2824 ecore_ptt_release(p_hwfn, p_ptt);
2825
2826 if (ret) {
2827 ret = -1;
2828 break;
2829 }
2830
2831 ret = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
2832
2833 QL_DPRINT8(ha, "SIOCGI2C copyout ret = %d \
2834 len = %d addr = 0x%02x offset = 0x%04x \
2835 data[0..7]=0x%02x 0x%02x 0x%02x 0x%02x 0x%02x \
2836 0x%02x 0x%02x 0x%02x\n",
2837 ret, i2c.len, i2c.dev_addr, i2c.offset,
2838 i2c.data[0], i2c.data[1], i2c.data[2], i2c.data[3],
2839 i2c.data[4], i2c.data[5], i2c.data[6], i2c.data[7]);
2840 break;
2841 }
2842 #endif /* #if (__FreeBSD_version >= 1100101) */
2843
2844 default:
2845 QL_DPRINT4(ha, "default (0x%lx)\n", cmd);
2846 ret = ether_ioctl(ifp, cmd, data);
2847 break;
2848 }
2849
2850 return (ret);
2851 }
2852
2853 static int
qlnx_media_change(struct ifnet * ifp)2854 qlnx_media_change(struct ifnet *ifp)
2855 {
2856 qlnx_host_t *ha;
2857 struct ifmedia *ifm;
2858 int ret = 0;
2859
2860 ha = (qlnx_host_t *)ifp->if_softc;
2861
2862 QL_DPRINT2(ha, "enter\n");
2863
2864 ifm = &ha->media;
2865
2866 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2867 ret = EINVAL;
2868
2869 QL_DPRINT2(ha, "exit\n");
2870
2871 return (ret);
2872 }
2873
2874 static void
qlnx_media_status(struct ifnet * ifp,struct ifmediareq * ifmr)2875 qlnx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
2876 {
2877 qlnx_host_t *ha;
2878
2879 ha = (qlnx_host_t *)ifp->if_softc;
2880
2881 QL_DPRINT2(ha, "enter\n");
2882
2883 ifmr->ifm_status = IFM_AVALID;
2884 ifmr->ifm_active = IFM_ETHER;
2885
2886 if (ha->link_up) {
2887 ifmr->ifm_status |= IFM_ACTIVE;
2888 ifmr->ifm_active |=
2889 (IFM_FDX | qlnx_get_optics(ha, &ha->if_link));
2890
2891 if (ha->if_link.link_partner_caps &
2892 (QLNX_LINK_CAP_Pause | QLNX_LINK_CAP_Asym_Pause))
2893 ifmr->ifm_active |=
2894 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
2895 }
2896
2897 QL_DPRINT2(ha, "exit (%s)\n", (ha->link_up ? "link_up" : "link_down"));
2898
2899 return;
2900 }
2901
2902 static void
qlnx_free_tx_pkt(qlnx_host_t * ha,struct qlnx_fastpath * fp,struct qlnx_tx_queue * txq)2903 qlnx_free_tx_pkt(qlnx_host_t *ha, struct qlnx_fastpath *fp,
2904 struct qlnx_tx_queue *txq)
2905 {
2906 u16 idx;
2907 struct mbuf *mp;
2908 bus_dmamap_t map;
2909 int i;
2910 struct eth_tx_bd *tx_data_bd;
2911 struct eth_tx_1st_bd *first_bd;
2912 int nbds = 0;
2913
2914 idx = txq->sw_tx_cons;
2915 mp = txq->sw_tx_ring[idx].mp;
2916 map = txq->sw_tx_ring[idx].map;
2917
2918 if ((mp == NULL) || QL_ERR_INJECT(ha, QL_ERR_INJCT_TX_INT_MBUF_NULL)){
2919 QL_RESET_ERR_INJECT(ha, QL_ERR_INJCT_TX_INT_MBUF_NULL);
2920
2921 QL_DPRINT1(ha, "(mp == NULL) "
2922 " tx_idx = 0x%x"
2923 " ecore_prod_idx = 0x%x"
2924 " ecore_cons_idx = 0x%x"
2925 " hw_bd_cons = 0x%x"
2926 " txq_db_last = 0x%x"
2927 " elem_left = 0x%x\n",
2928 fp->rss_id,
2929 ecore_chain_get_prod_idx(&txq->tx_pbl),
2930 ecore_chain_get_cons_idx(&txq->tx_pbl),
2931 le16toh(*txq->hw_cons_ptr),
2932 txq->tx_db.raw,
2933 ecore_chain_get_elem_left(&txq->tx_pbl));
2934
2935 fp->err_tx_free_pkt_null++;
2936
2937 //DEBUG
2938 qlnx_trigger_dump(ha);
2939
2940 return;
2941 } else {
2942 QLNX_INC_OPACKETS((ha->ifp));
2943 QLNX_INC_OBYTES((ha->ifp), (mp->m_pkthdr.len));
2944
2945 bus_dmamap_sync(ha->tx_tag, map, BUS_DMASYNC_POSTWRITE);
2946 bus_dmamap_unload(ha->tx_tag, map);
2947
2948 fp->tx_pkts_freed++;
2949 fp->tx_pkts_completed++;
2950
2951 m_freem(mp);
2952 }
2953
2954 first_bd = (struct eth_tx_1st_bd *)ecore_chain_consume(&txq->tx_pbl);
2955 nbds = first_bd->data.nbds;
2956
2957 // BD_SET_UNMAP_ADDR_LEN(first_bd, 0, 0);
2958
2959 for (i = 1; i < nbds; i++) {
2960 tx_data_bd = ecore_chain_consume(&txq->tx_pbl);
2961 // BD_SET_UNMAP_ADDR_LEN(tx_data_bd, 0, 0);
2962 }
2963 txq->sw_tx_ring[idx].flags = 0;
2964 txq->sw_tx_ring[idx].mp = NULL;
2965 txq->sw_tx_ring[idx].map = (bus_dmamap_t)0;
2966
2967 return;
2968 }
2969
2970 static void
qlnx_tx_int(qlnx_host_t * ha,struct qlnx_fastpath * fp,struct qlnx_tx_queue * txq)2971 qlnx_tx_int(qlnx_host_t *ha, struct qlnx_fastpath *fp,
2972 struct qlnx_tx_queue *txq)
2973 {
2974 u16 hw_bd_cons;
2975 u16 ecore_cons_idx;
2976 uint16_t diff;
2977 uint16_t idx, idx2;
2978
2979 hw_bd_cons = le16toh(*txq->hw_cons_ptr);
2980
2981 while (hw_bd_cons !=
2982 (ecore_cons_idx = ecore_chain_get_cons_idx(&txq->tx_pbl))) {
2983 if (hw_bd_cons < ecore_cons_idx) {
2984 diff = (1 << 16) - (ecore_cons_idx - hw_bd_cons);
2985 } else {
2986 diff = hw_bd_cons - ecore_cons_idx;
2987 }
2988 if ((diff > TX_RING_SIZE) ||
2989 QL_ERR_INJECT(ha, QL_ERR_INJCT_TX_INT_DIFF)){
2990 QL_RESET_ERR_INJECT(ha, QL_ERR_INJCT_TX_INT_DIFF);
2991
2992 QL_DPRINT1(ha, "(diff = 0x%x) "
2993 " tx_idx = 0x%x"
2994 " ecore_prod_idx = 0x%x"
2995 " ecore_cons_idx = 0x%x"
2996 " hw_bd_cons = 0x%x"
2997 " txq_db_last = 0x%x"
2998 " elem_left = 0x%x\n",
2999 diff,
3000 fp->rss_id,
3001 ecore_chain_get_prod_idx(&txq->tx_pbl),
3002 ecore_chain_get_cons_idx(&txq->tx_pbl),
3003 le16toh(*txq->hw_cons_ptr),
3004 txq->tx_db.raw,
3005 ecore_chain_get_elem_left(&txq->tx_pbl));
3006
3007 fp->err_tx_cons_idx_conflict++;
3008
3009 //DEBUG
3010 qlnx_trigger_dump(ha);
3011 }
3012
3013 idx = (txq->sw_tx_cons + 1) & (TX_RING_SIZE - 1);
3014 idx2 = (txq->sw_tx_cons + 2) & (TX_RING_SIZE - 1);
3015 prefetch(txq->sw_tx_ring[idx].mp);
3016 prefetch(txq->sw_tx_ring[idx2].mp);
3017
3018 qlnx_free_tx_pkt(ha, fp, txq);
3019
3020 txq->sw_tx_cons = (txq->sw_tx_cons + 1) & (TX_RING_SIZE - 1);
3021 }
3022 return;
3023 }
3024
3025 static int
qlnx_transmit_locked(struct ifnet * ifp,struct qlnx_fastpath * fp,struct mbuf * mp)3026 qlnx_transmit_locked(struct ifnet *ifp,struct qlnx_fastpath *fp, struct mbuf *mp)
3027 {
3028 int ret = 0;
3029 struct qlnx_tx_queue *txq;
3030 qlnx_host_t * ha;
3031 uint16_t elem_left;
3032
3033 txq = fp->txq[0];
3034 ha = (qlnx_host_t *)fp->edev;
3035
3036 if ((!(ifp->if_drv_flags & IFF_DRV_RUNNING)) || (!ha->link_up)) {
3037 if(mp != NULL)
3038 ret = drbr_enqueue(ifp, fp->tx_br, mp);
3039 return (ret);
3040 }
3041
3042 if(mp != NULL)
3043 ret = drbr_enqueue(ifp, fp->tx_br, mp);
3044
3045 mp = drbr_peek(ifp, fp->tx_br);
3046
3047 while (mp != NULL) {
3048 if (qlnx_send(ha, fp, &mp)) {
3049 if (mp != NULL) {
3050 drbr_putback(ifp, fp->tx_br, mp);
3051 } else {
3052 fp->tx_pkts_processed++;
3053 drbr_advance(ifp, fp->tx_br);
3054 }
3055 goto qlnx_transmit_locked_exit;
3056
3057 } else {
3058 drbr_advance(ifp, fp->tx_br);
3059 fp->tx_pkts_transmitted++;
3060 fp->tx_pkts_processed++;
3061 }
3062
3063 mp = drbr_peek(ifp, fp->tx_br);
3064 }
3065
3066 qlnx_transmit_locked_exit:
3067 if((qlnx_num_tx_compl(ha,fp, fp->txq[0]) > QLNX_TX_COMPL_THRESH) ||
3068 ((int)(elem_left = ecore_chain_get_elem_left(&txq->tx_pbl))
3069 < QLNX_TX_ELEM_MAX_THRESH))
3070 (void)qlnx_tx_int(ha, fp, fp->txq[0]);
3071
3072 QL_DPRINT2(ha, "%s: exit ret = %d\n", __func__, ret);
3073 return ret;
3074 }
3075
3076 static int
qlnx_transmit(struct ifnet * ifp,struct mbuf * mp)3077 qlnx_transmit(struct ifnet *ifp, struct mbuf *mp)
3078 {
3079 qlnx_host_t *ha = (qlnx_host_t *)ifp->if_softc;
3080 struct qlnx_fastpath *fp;
3081 int rss_id = 0, ret = 0;
3082
3083 #ifdef QLNX_TRACEPERF_DATA
3084 uint64_t tx_pkts = 0, tx_compl = 0;
3085 #endif
3086
3087 QL_DPRINT2(ha, "enter\n");
3088
3089 #if __FreeBSD_version >= 1100000
3090 if (M_HASHTYPE_GET(mp) != M_HASHTYPE_NONE)
3091 #else
3092 if (mp->m_flags & M_FLOWID)
3093 #endif
3094 rss_id = (mp->m_pkthdr.flowid % ECORE_RSS_IND_TABLE_SIZE) %
3095 ha->num_rss;
3096
3097 fp = &ha->fp_array[rss_id];
3098
3099 if (fp->tx_br == NULL) {
3100 ret = EINVAL;
3101 goto qlnx_transmit_exit;
3102 }
3103
3104 if (mtx_trylock(&fp->tx_mtx)) {
3105 #ifdef QLNX_TRACEPERF_DATA
3106 tx_pkts = fp->tx_pkts_transmitted;
3107 tx_compl = fp->tx_pkts_completed;
3108 #endif
3109
3110 ret = qlnx_transmit_locked(ifp, fp, mp);
3111
3112 #ifdef QLNX_TRACEPERF_DATA
3113 fp->tx_pkts_trans_ctx += (fp->tx_pkts_transmitted - tx_pkts);
3114 fp->tx_pkts_compl_ctx += (fp->tx_pkts_completed - tx_compl);
3115 #endif
3116 mtx_unlock(&fp->tx_mtx);
3117 } else {
3118 if (mp != NULL && (fp->fp_taskqueue != NULL)) {
3119 ret = drbr_enqueue(ifp, fp->tx_br, mp);
3120 taskqueue_enqueue(fp->fp_taskqueue, &fp->fp_task);
3121 }
3122 }
3123
3124 qlnx_transmit_exit:
3125
3126 QL_DPRINT2(ha, "exit ret = %d\n", ret);
3127 return ret;
3128 }
3129
3130 static void
qlnx_qflush(struct ifnet * ifp)3131 qlnx_qflush(struct ifnet *ifp)
3132 {
3133 int rss_id;
3134 struct qlnx_fastpath *fp;
3135 struct mbuf *mp;
3136 qlnx_host_t *ha;
3137
3138 ha = (qlnx_host_t *)ifp->if_softc;
3139
3140 QL_DPRINT2(ha, "enter\n");
3141
3142 for (rss_id = 0; rss_id < ha->num_rss; rss_id++) {
3143 fp = &ha->fp_array[rss_id];
3144
3145 if (fp == NULL)
3146 continue;
3147
3148 if (fp->tx_br) {
3149 mtx_lock(&fp->tx_mtx);
3150
3151 while ((mp = drbr_dequeue(ifp, fp->tx_br)) != NULL) {
3152 fp->tx_pkts_freed++;
3153 m_freem(mp);
3154 }
3155 mtx_unlock(&fp->tx_mtx);
3156 }
3157 }
3158 QL_DPRINT2(ha, "exit\n");
3159
3160 return;
3161 }
3162
3163 static void
qlnx_txq_doorbell_wr32(qlnx_host_t * ha,void * reg_addr,uint32_t value)3164 qlnx_txq_doorbell_wr32(qlnx_host_t *ha, void *reg_addr, uint32_t value)
3165 {
3166 struct ecore_dev *cdev;
3167 uint32_t offset;
3168
3169 cdev = &ha->cdev;
3170
3171 offset = (uint32_t)((uint8_t *)reg_addr - (uint8_t *)ha->pci_dbells);
3172
3173 bus_write_4(ha->pci_dbells, offset, value);
3174 bus_barrier(ha->pci_reg, 0, 0, BUS_SPACE_BARRIER_READ);
3175 bus_barrier(ha->pci_dbells, 0, 0, BUS_SPACE_BARRIER_READ);
3176
3177 return;
3178 }
3179
3180 static uint32_t
qlnx_tcp_offset(qlnx_host_t * ha,struct mbuf * mp)3181 qlnx_tcp_offset(qlnx_host_t *ha, struct mbuf *mp)
3182 {
3183 struct ether_vlan_header *eh = NULL;
3184 struct ip *ip = NULL;
3185 struct ip6_hdr *ip6 = NULL;
3186 struct tcphdr *th = NULL;
3187 uint32_t ehdrlen = 0, ip_hlen = 0, offset = 0;
3188 uint16_t etype = 0;
3189 device_t dev;
3190 uint8_t buf[sizeof(struct ip6_hdr)];
3191
3192 dev = ha->pci_dev;
3193
3194 eh = mtod(mp, struct ether_vlan_header *);
3195
3196 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3197 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3198 etype = ntohs(eh->evl_proto);
3199 } else {
3200 ehdrlen = ETHER_HDR_LEN;
3201 etype = ntohs(eh->evl_encap_proto);
3202 }
3203
3204 switch (etype) {
3205 case ETHERTYPE_IP:
3206 ip = (struct ip *)(mp->m_data + ehdrlen);
3207
3208 ip_hlen = sizeof (struct ip);
3209
3210 if (mp->m_len < (ehdrlen + ip_hlen)) {
3211 m_copydata(mp, ehdrlen, sizeof(struct ip), buf);
3212 ip = (struct ip *)buf;
3213 }
3214
3215 th = (struct tcphdr *)(ip + 1);
3216 offset = ip_hlen + ehdrlen + (th->th_off << 2);
3217 break;
3218
3219 case ETHERTYPE_IPV6:
3220 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
3221
3222 ip_hlen = sizeof(struct ip6_hdr);
3223
3224 if (mp->m_len < (ehdrlen + ip_hlen)) {
3225 m_copydata(mp, ehdrlen, sizeof (struct ip6_hdr),
3226 buf);
3227 ip6 = (struct ip6_hdr *)buf;
3228 }
3229 th = (struct tcphdr *)(ip6 + 1);
3230 offset = ip_hlen + ehdrlen + (th->th_off << 2);
3231 break;
3232
3233 default:
3234 break;
3235 }
3236
3237 return (offset);
3238 }
3239
3240 static __inline int
qlnx_tso_check(struct qlnx_fastpath * fp,bus_dma_segment_t * segs,int nsegs,uint32_t offset)3241 qlnx_tso_check(struct qlnx_fastpath *fp, bus_dma_segment_t *segs, int nsegs,
3242 uint32_t offset)
3243 {
3244 int i;
3245 uint32_t sum, nbds_in_hdr = 1;
3246 uint32_t window;
3247 bus_dma_segment_t *s_seg;
3248
3249 /* If the header spans multiple segments, skip those segments */
3250
3251 if (nsegs < ETH_TX_LSO_WINDOW_BDS_NUM)
3252 return (0);
3253
3254 i = 0;
3255
3256 while ((i < nsegs) && (offset >= segs->ds_len)) {
3257 offset = offset - segs->ds_len;
3258 segs++;
3259 i++;
3260 nbds_in_hdr++;
3261 }
3262
3263 window = ETH_TX_LSO_WINDOW_BDS_NUM - nbds_in_hdr;
3264
3265 nsegs = nsegs - i;
3266
3267 while (nsegs >= window) {
3268 sum = 0;
3269 s_seg = segs;
3270
3271 for (i = 0; i < window; i++){
3272 sum += s_seg->ds_len;
3273 s_seg++;
3274 }
3275
3276 if (sum < ETH_TX_LSO_WINDOW_MIN_LEN) {
3277 fp->tx_lso_wnd_min_len++;
3278 return (-1);
3279 }
3280
3281 nsegs = nsegs - 1;
3282 segs++;
3283 }
3284
3285 return (0);
3286 }
3287
3288 static int
qlnx_send(qlnx_host_t * ha,struct qlnx_fastpath * fp,struct mbuf ** m_headp)3289 qlnx_send(qlnx_host_t *ha, struct qlnx_fastpath *fp, struct mbuf **m_headp)
3290 {
3291 bus_dma_segment_t *segs;
3292 bus_dmamap_t map = 0;
3293 uint32_t nsegs = 0;
3294 int ret = -1;
3295 struct mbuf *m_head = *m_headp;
3296 uint16_t idx = 0;
3297 uint16_t elem_left;
3298
3299 uint8_t nbd = 0;
3300 struct qlnx_tx_queue *txq;
3301
3302 struct eth_tx_1st_bd *first_bd;
3303 struct eth_tx_2nd_bd *second_bd;
3304 struct eth_tx_3rd_bd *third_bd;
3305 struct eth_tx_bd *tx_data_bd;
3306
3307 int seg_idx = 0;
3308 uint32_t nbds_in_hdr = 0;
3309 uint32_t offset = 0;
3310
3311 #ifdef QLNX_TRACE_PERF_DATA
3312 uint16_t bd_used;
3313 #endif
3314
3315 QL_DPRINT8(ha, "enter[%d]\n", fp->rss_id);
3316
3317 if (!ha->link_up)
3318 return (-1);
3319
3320 first_bd = NULL;
3321 second_bd = NULL;
3322 third_bd = NULL;
3323 tx_data_bd = NULL;
3324
3325 txq = fp->txq[0];
3326
3327 if ((int)(elem_left = ecore_chain_get_elem_left(&txq->tx_pbl)) <
3328 QLNX_TX_ELEM_MIN_THRESH) {
3329 fp->tx_nsegs_gt_elem_left++;
3330 fp->err_tx_nsegs_gt_elem_left++;
3331
3332 return (ENOBUFS);
3333 }
3334
3335 idx = txq->sw_tx_prod;
3336
3337 map = txq->sw_tx_ring[idx].map;
3338 segs = txq->segs;
3339
3340 ret = bus_dmamap_load_mbuf_sg(ha->tx_tag, map, m_head, segs, &nsegs,
3341 BUS_DMA_NOWAIT);
3342
3343 if (ha->dbg_trace_tso_pkt_len) {
3344 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3345 if (!fp->tx_tso_min_pkt_len) {
3346 fp->tx_tso_min_pkt_len = m_head->m_pkthdr.len;
3347 fp->tx_tso_min_pkt_len = m_head->m_pkthdr.len;
3348 } else {
3349 if (fp->tx_tso_min_pkt_len > m_head->m_pkthdr.len)
3350 fp->tx_tso_min_pkt_len =
3351 m_head->m_pkthdr.len;
3352 if (fp->tx_tso_max_pkt_len < m_head->m_pkthdr.len)
3353 fp->tx_tso_max_pkt_len =
3354 m_head->m_pkthdr.len;
3355 }
3356 }
3357 }
3358
3359 if (m_head->m_pkthdr.csum_flags & CSUM_TSO)
3360 offset = qlnx_tcp_offset(ha, m_head);
3361
3362 if ((ret == EFBIG) ||
3363 ((nsegs > QLNX_MAX_SEGMENTS_NON_TSO) && (
3364 (!(m_head->m_pkthdr.csum_flags & CSUM_TSO)) ||
3365 ((m_head->m_pkthdr.csum_flags & CSUM_TSO) &&
3366 qlnx_tso_check(fp, segs, nsegs, offset))))) {
3367 struct mbuf *m;
3368
3369 QL_DPRINT8(ha, "EFBIG [%d]\n", m_head->m_pkthdr.len);
3370
3371 fp->tx_defrag++;
3372
3373 m = m_defrag(m_head, M_NOWAIT);
3374 if (m == NULL) {
3375 fp->err_tx_defrag++;
3376 fp->tx_pkts_freed++;
3377 m_freem(m_head);
3378 *m_headp = NULL;
3379 QL_DPRINT1(ha, "m_defrag() = NULL [%d]\n", ret);
3380 return (ENOBUFS);
3381 }
3382
3383 m_head = m;
3384 *m_headp = m_head;
3385
3386 if ((ret = bus_dmamap_load_mbuf_sg(ha->tx_tag, map, m_head,
3387 segs, &nsegs, BUS_DMA_NOWAIT))) {
3388 fp->err_tx_defrag_dmamap_load++;
3389
3390 QL_DPRINT1(ha,
3391 "bus_dmamap_load_mbuf_sg failed0 [%d, %d]\n",
3392 ret, m_head->m_pkthdr.len);
3393
3394 fp->tx_pkts_freed++;
3395 m_freem(m_head);
3396 *m_headp = NULL;
3397
3398 return (ret);
3399 }
3400
3401 if ((nsegs > QLNX_MAX_SEGMENTS_NON_TSO) &&
3402 !(m_head->m_pkthdr.csum_flags & CSUM_TSO)) {
3403 fp->err_tx_non_tso_max_seg++;
3404
3405 QL_DPRINT1(ha,
3406 "(%d) nsegs too many for non-TSO [%d, %d]\n",
3407 ret, nsegs, m_head->m_pkthdr.len);
3408
3409 fp->tx_pkts_freed++;
3410 m_freem(m_head);
3411 *m_headp = NULL;
3412
3413 return (ret);
3414 }
3415 if (m_head->m_pkthdr.csum_flags & CSUM_TSO)
3416 offset = qlnx_tcp_offset(ha, m_head);
3417
3418 } else if (ret) {
3419 fp->err_tx_dmamap_load++;
3420
3421 QL_DPRINT1(ha, "bus_dmamap_load_mbuf_sg failed1 [%d, %d]\n",
3422 ret, m_head->m_pkthdr.len);
3423 fp->tx_pkts_freed++;
3424 m_freem(m_head);
3425 *m_headp = NULL;
3426 return (ret);
3427 }
3428
3429 QL_ASSERT(ha, (nsegs != 0), ("qlnx_send: empty packet"));
3430
3431 if (ha->dbg_trace_tso_pkt_len) {
3432 if (nsegs < QLNX_FP_MAX_SEGS)
3433 fp->tx_pkts[(nsegs - 1)]++;
3434 else
3435 fp->tx_pkts[(QLNX_FP_MAX_SEGS - 1)]++;
3436 }
3437
3438 #ifdef QLNX_TRACE_PERF_DATA
3439 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3440 if(m_head->m_pkthdr.len <= 2048)
3441 fp->tx_pkts_hist[0]++;
3442 else if((m_head->m_pkthdr.len > 2048) &&
3443 (m_head->m_pkthdr.len <= 4096))
3444 fp->tx_pkts_hist[1]++;
3445 else if((m_head->m_pkthdr.len > 4096) &&
3446 (m_head->m_pkthdr.len <= 8192))
3447 fp->tx_pkts_hist[2]++;
3448 else if((m_head->m_pkthdr.len > 8192) &&
3449 (m_head->m_pkthdr.len <= 12288 ))
3450 fp->tx_pkts_hist[3]++;
3451 else if((m_head->m_pkthdr.len > 11288) &&
3452 (m_head->m_pkthdr.len <= 16394))
3453 fp->tx_pkts_hist[4]++;
3454 else if((m_head->m_pkthdr.len > 16384) &&
3455 (m_head->m_pkthdr.len <= 20480))
3456 fp->tx_pkts_hist[5]++;
3457 else if((m_head->m_pkthdr.len > 20480) &&
3458 (m_head->m_pkthdr.len <= 24576))
3459 fp->tx_pkts_hist[6]++;
3460 else if((m_head->m_pkthdr.len > 24576) &&
3461 (m_head->m_pkthdr.len <= 28672))
3462 fp->tx_pkts_hist[7]++;
3463 else if((m_head->m_pkthdr.len > 28762) &&
3464 (m_head->m_pkthdr.len <= 32768))
3465 fp->tx_pkts_hist[8]++;
3466 else if((m_head->m_pkthdr.len > 32768) &&
3467 (m_head->m_pkthdr.len <= 36864))
3468 fp->tx_pkts_hist[9]++;
3469 else if((m_head->m_pkthdr.len > 36864) &&
3470 (m_head->m_pkthdr.len <= 40960))
3471 fp->tx_pkts_hist[10]++;
3472 else if((m_head->m_pkthdr.len > 40960) &&
3473 (m_head->m_pkthdr.len <= 45056))
3474 fp->tx_pkts_hist[11]++;
3475 else if((m_head->m_pkthdr.len > 45056) &&
3476 (m_head->m_pkthdr.len <= 49152))
3477 fp->tx_pkts_hist[12]++;
3478 else if((m_head->m_pkthdr.len > 49512) &&
3479 m_head->m_pkthdr.len <= 53248))
3480 fp->tx_pkts_hist[13]++;
3481 else if((m_head->m_pkthdr.len > 53248) &&
3482 (m_head->m_pkthdr.len <= 57344))
3483 fp->tx_pkts_hist[14]++;
3484 else if((m_head->m_pkthdr.len > 53248) &&
3485 (m_head->m_pkthdr.len <= 57344))
3486 fp->tx_pkts_hist[15]++;
3487 else if((m_head->m_pkthdr.len > 57344) &&
3488 (m_head->m_pkthdr.len <= 61440))
3489 fp->tx_pkts_hist[16]++;
3490 else
3491 fp->tx_pkts_hist[17]++;
3492 }
3493
3494 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3495 elem_left = ecore_chain_get_elem_left(&txq->tx_pbl);
3496 bd_used = TX_RING_SIZE - elem_left;
3497
3498 if(bd_used <= 100)
3499 fp->tx_pkts_q[0]++;
3500 else if((bd_used > 100) && (bd_used <= 500))
3501 fp->tx_pkts_q[1]++;
3502 else if((bd_used > 500) && (bd_used <= 1000))
3503 fp->tx_pkts_q[2]++;
3504 else if((bd_used > 1000) && (bd_used <= 2000))
3505 fp->tx_pkts_q[3]++;
3506 else if((bd_used > 3000) && (bd_used <= 4000))
3507 fp->tx_pkts_q[4]++;
3508 else if((bd_used > 4000) && (bd_used <= 5000))
3509 fp->tx_pkts_q[5]++;
3510 else if((bd_used > 6000) && (bd_used <= 7000))
3511 fp->tx_pkts_q[6]++;
3512 else if((bd_used > 7000) && (bd_used <= 8000))
3513 fp->tx_pkts_q[7]++;
3514 else if((bd_used > 8000) && (bd_used <= 9000))
3515 fp->tx_pkts_q[8]++;
3516 else if((bd_used > 9000) && (bd_used <= 10000))
3517 fp->tx_pkts_q[9]++;
3518 else if((bd_used > 10000) && (bd_used <= 11000))
3519 fp->tx_pkts_q[10]++;
3520 else if((bd_used > 11000) && (bd_used <= 12000))
3521 fp->tx_pkts_q[11]++;
3522 else if((bd_used > 12000) && (bd_used <= 13000))
3523 fp->tx_pkts_q[12]++;
3524 else if((bd_used > 13000) && (bd_used <= 14000))
3525 fp->tx_pkts_q[13]++;
3526 else if((bd_used > 14000) && (bd_used <= 15000))
3527 fp->tx_pkts_q[14]++;
3528 else if((bd_used > 15000) && (bd_used <= 16000))
3529 fp->tx_pkts_q[15]++;
3530 else
3531 fp->tx_pkts_q[16]++;
3532 }
3533
3534 #endif /* end of QLNX_TRACE_PERF_DATA */
3535
3536 if ((nsegs + QLNX_TX_ELEM_RESERVE) >
3537 (int)(elem_left = ecore_chain_get_elem_left(&txq->tx_pbl))) {
3538 QL_DPRINT1(ha, "(%d, 0x%x) insuffient BDs"
3539 " in chain[%d] trying to free packets\n",
3540 nsegs, elem_left, fp->rss_id);
3541
3542 fp->tx_nsegs_gt_elem_left++;
3543
3544 (void)qlnx_tx_int(ha, fp, txq);
3545
3546 if ((nsegs + QLNX_TX_ELEM_RESERVE) > (int)(elem_left =
3547 ecore_chain_get_elem_left(&txq->tx_pbl))) {
3548 QL_DPRINT1(ha,
3549 "(%d, 0x%x) insuffient BDs in chain[%d]\n",
3550 nsegs, elem_left, fp->rss_id);
3551
3552 fp->err_tx_nsegs_gt_elem_left++;
3553 fp->tx_ring_full = 1;
3554 if (ha->storm_stats_enable)
3555 ha->storm_stats_gather = 1;
3556 return (ENOBUFS);
3557 }
3558 }
3559
3560 bus_dmamap_sync(ha->tx_tag, map, BUS_DMASYNC_PREWRITE);
3561
3562 txq->sw_tx_ring[idx].mp = m_head;
3563
3564 first_bd = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
3565
3566 memset(first_bd, 0, sizeof(*first_bd));
3567
3568 first_bd->data.bd_flags.bitfields =
3569 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
3570
3571 BD_SET_UNMAP_ADDR_LEN(first_bd, segs->ds_addr, segs->ds_len);
3572
3573 nbd++;
3574
3575 if (m_head->m_pkthdr.csum_flags & CSUM_IP) {
3576 first_bd->data.bd_flags.bitfields |=
3577 (1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT);
3578 }
3579
3580 if (m_head->m_pkthdr.csum_flags &
3581 (CSUM_UDP | CSUM_TCP | CSUM_TCP_IPV6 | CSUM_UDP_IPV6)) {
3582 first_bd->data.bd_flags.bitfields |=
3583 (1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT);
3584 }
3585
3586 if (m_head->m_flags & M_VLANTAG) {
3587 first_bd->data.vlan = m_head->m_pkthdr.ether_vtag;
3588 first_bd->data.bd_flags.bitfields |=
3589 (1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT);
3590 }
3591
3592 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3593 first_bd->data.bd_flags.bitfields |=
3594 (1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT);
3595 first_bd->data.bd_flags.bitfields |=
3596 (1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT);
3597
3598 nbds_in_hdr = 1;
3599
3600 if (offset == segs->ds_len) {
3601 BD_SET_UNMAP_ADDR_LEN(first_bd, segs->ds_addr, offset);
3602 segs++;
3603 seg_idx++;
3604
3605 second_bd = (struct eth_tx_2nd_bd *)
3606 ecore_chain_produce(&txq->tx_pbl);
3607 memset(second_bd, 0, sizeof(*second_bd));
3608 nbd++;
3609
3610 if (seg_idx < nsegs) {
3611 BD_SET_UNMAP_ADDR_LEN(second_bd, \
3612 (segs->ds_addr), (segs->ds_len));
3613 segs++;
3614 seg_idx++;
3615 }
3616
3617 third_bd = (struct eth_tx_3rd_bd *)
3618 ecore_chain_produce(&txq->tx_pbl);
3619 memset(third_bd, 0, sizeof(*third_bd));
3620 third_bd->data.lso_mss = m_head->m_pkthdr.tso_segsz;
3621 third_bd->data.bitfields |=
3622 (nbds_in_hdr<<ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
3623 nbd++;
3624
3625 if (seg_idx < nsegs) {
3626 BD_SET_UNMAP_ADDR_LEN(third_bd, \
3627 (segs->ds_addr), (segs->ds_len));
3628 segs++;
3629 seg_idx++;
3630 }
3631
3632 for (; seg_idx < nsegs; seg_idx++) {
3633 tx_data_bd = (struct eth_tx_bd *)
3634 ecore_chain_produce(&txq->tx_pbl);
3635 memset(tx_data_bd, 0, sizeof(*tx_data_bd));
3636 BD_SET_UNMAP_ADDR_LEN(tx_data_bd, \
3637 segs->ds_addr,\
3638 segs->ds_len);
3639 segs++;
3640 nbd++;
3641 }
3642
3643 } else if (offset < segs->ds_len) {
3644 BD_SET_UNMAP_ADDR_LEN(first_bd, segs->ds_addr, offset);
3645
3646 second_bd = (struct eth_tx_2nd_bd *)
3647 ecore_chain_produce(&txq->tx_pbl);
3648 memset(second_bd, 0, sizeof(*second_bd));
3649 BD_SET_UNMAP_ADDR_LEN(second_bd, \
3650 (segs->ds_addr + offset),\
3651 (segs->ds_len - offset));
3652 nbd++;
3653 segs++;
3654
3655 third_bd = (struct eth_tx_3rd_bd *)
3656 ecore_chain_produce(&txq->tx_pbl);
3657 memset(third_bd, 0, sizeof(*third_bd));
3658
3659 BD_SET_UNMAP_ADDR_LEN(third_bd, \
3660 segs->ds_addr,\
3661 segs->ds_len);
3662 third_bd->data.lso_mss = m_head->m_pkthdr.tso_segsz;
3663 third_bd->data.bitfields |=
3664 (nbds_in_hdr<<ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
3665 segs++;
3666 nbd++;
3667
3668 for (seg_idx = 2; seg_idx < nsegs; seg_idx++) {
3669 tx_data_bd = (struct eth_tx_bd *)
3670 ecore_chain_produce(&txq->tx_pbl);
3671 memset(tx_data_bd, 0, sizeof(*tx_data_bd));
3672 BD_SET_UNMAP_ADDR_LEN(tx_data_bd, \
3673 segs->ds_addr,\
3674 segs->ds_len);
3675 segs++;
3676 nbd++;
3677 }
3678
3679 } else {
3680 offset = offset - segs->ds_len;
3681 segs++;
3682
3683 for (seg_idx = 1; seg_idx < nsegs; seg_idx++) {
3684 if (offset)
3685 nbds_in_hdr++;
3686
3687 tx_data_bd = (struct eth_tx_bd *)
3688 ecore_chain_produce(&txq->tx_pbl);
3689 memset(tx_data_bd, 0, sizeof(*tx_data_bd));
3690
3691 if (second_bd == NULL) {
3692 second_bd = (struct eth_tx_2nd_bd *)
3693 tx_data_bd;
3694 } else if (third_bd == NULL) {
3695 third_bd = (struct eth_tx_3rd_bd *)
3696 tx_data_bd;
3697 }
3698
3699 if (offset && (offset < segs->ds_len)) {
3700 BD_SET_UNMAP_ADDR_LEN(tx_data_bd,\
3701 segs->ds_addr, offset);
3702
3703 tx_data_bd = (struct eth_tx_bd *)
3704 ecore_chain_produce(&txq->tx_pbl);
3705
3706 memset(tx_data_bd, 0,
3707 sizeof(*tx_data_bd));
3708
3709 if (second_bd == NULL) {
3710 second_bd =
3711 (struct eth_tx_2nd_bd *)tx_data_bd;
3712 } else if (third_bd == NULL) {
3713 third_bd =
3714 (struct eth_tx_3rd_bd *)tx_data_bd;
3715 }
3716 BD_SET_UNMAP_ADDR_LEN(tx_data_bd,\
3717 (segs->ds_addr + offset), \
3718 (segs->ds_len - offset));
3719 nbd++;
3720 offset = 0;
3721 } else {
3722 if (offset)
3723 offset = offset - segs->ds_len;
3724 BD_SET_UNMAP_ADDR_LEN(tx_data_bd,\
3725 segs->ds_addr, segs->ds_len);
3726 }
3727 segs++;
3728 nbd++;
3729 }
3730
3731 if (third_bd == NULL) {
3732 third_bd = (struct eth_tx_3rd_bd *)
3733 ecore_chain_produce(&txq->tx_pbl);
3734 memset(third_bd, 0, sizeof(*third_bd));
3735 }
3736
3737 third_bd->data.lso_mss = m_head->m_pkthdr.tso_segsz;
3738 third_bd->data.bitfields |=
3739 (nbds_in_hdr<<ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
3740 }
3741 fp->tx_tso_pkts++;
3742 } else {
3743 segs++;
3744 for (seg_idx = 1; seg_idx < nsegs; seg_idx++) {
3745 tx_data_bd = (struct eth_tx_bd *)
3746 ecore_chain_produce(&txq->tx_pbl);
3747 memset(tx_data_bd, 0, sizeof(*tx_data_bd));
3748 BD_SET_UNMAP_ADDR_LEN(tx_data_bd, segs->ds_addr,\
3749 segs->ds_len);
3750 segs++;
3751 nbd++;
3752 }
3753 first_bd->data.bitfields =
3754 (m_head->m_pkthdr.len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
3755 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
3756 first_bd->data.bitfields =
3757 htole16(first_bd->data.bitfields);
3758 fp->tx_non_tso_pkts++;
3759 }
3760
3761 first_bd->data.nbds = nbd;
3762
3763 if (ha->dbg_trace_tso_pkt_len) {
3764 if (fp->tx_tso_max_nsegs < nsegs)
3765 fp->tx_tso_max_nsegs = nsegs;
3766
3767 if ((nsegs < fp->tx_tso_min_nsegs) || (!fp->tx_tso_min_nsegs))
3768 fp->tx_tso_min_nsegs = nsegs;
3769 }
3770
3771 txq->sw_tx_ring[idx].nsegs = nsegs;
3772 txq->sw_tx_prod = (txq->sw_tx_prod + 1) & (TX_RING_SIZE - 1);
3773
3774 txq->tx_db.data.bd_prod =
3775 htole16(ecore_chain_get_prod_idx(&txq->tx_pbl));
3776
3777 qlnx_txq_doorbell_wr32(ha, txq->doorbell_addr, txq->tx_db.raw);
3778
3779 QL_DPRINT8(ha, "exit[%d]\n", fp->rss_id);
3780 return (0);
3781 }
3782
3783 static void
qlnx_stop(qlnx_host_t * ha)3784 qlnx_stop(qlnx_host_t *ha)
3785 {
3786 struct ifnet *ifp = ha->ifp;
3787 device_t dev;
3788 int i;
3789
3790 dev = ha->pci_dev;
3791
3792 ifp->if_drv_flags &= ~(IFF_DRV_OACTIVE | IFF_DRV_RUNNING);
3793
3794 /*
3795 * We simply lock and unlock each fp->tx_mtx to
3796 * propagate the if_drv_flags
3797 * state to each tx thread
3798 */
3799 QL_DPRINT1(ha, "QLNX STATE = %d\n",ha->state);
3800
3801 if (ha->state == QLNX_STATE_OPEN) {
3802 for (i = 0; i < ha->num_rss; i++) {
3803 struct qlnx_fastpath *fp = &ha->fp_array[i];
3804
3805 mtx_lock(&fp->tx_mtx);
3806 mtx_unlock(&fp->tx_mtx);
3807
3808 if (fp->fp_taskqueue != NULL)
3809 taskqueue_enqueue(fp->fp_taskqueue,
3810 &fp->fp_task);
3811 }
3812 }
3813 #ifdef QLNX_ENABLE_IWARP
3814 if (qlnx_vf_device(ha) != 0) {
3815 qlnx_rdma_dev_close(ha);
3816 }
3817 #endif /* #ifdef QLNX_ENABLE_IWARP */
3818
3819 qlnx_unload(ha);
3820
3821 return;
3822 }
3823
3824 static int
qlnx_get_ifq_snd_maxlen(qlnx_host_t * ha)3825 qlnx_get_ifq_snd_maxlen(qlnx_host_t *ha)
3826 {
3827 return(TX_RING_SIZE - 1);
3828 }
3829
3830 uint8_t *
qlnx_get_mac_addr(qlnx_host_t * ha)3831 qlnx_get_mac_addr(qlnx_host_t *ha)
3832 {
3833 struct ecore_hwfn *p_hwfn;
3834 unsigned char mac[ETHER_ADDR_LEN];
3835 uint8_t p_is_forced;
3836
3837 p_hwfn = &ha->cdev.hwfns[0];
3838
3839 if (qlnx_vf_device(ha) != 0)
3840 return (p_hwfn->hw_info.hw_mac_addr);
3841
3842 ecore_vf_read_bulletin(p_hwfn, &p_is_forced);
3843 if (ecore_vf_bulletin_get_forced_mac(p_hwfn, mac, &p_is_forced) ==
3844 true) {
3845 device_printf(ha->pci_dev, "%s: p_is_forced = %d"
3846 " mac_addr = %02x:%02x:%02x:%02x:%02x:%02x\n", __func__,
3847 p_is_forced, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
3848 memcpy(ha->primary_mac, mac, ETH_ALEN);
3849 }
3850
3851 return (ha->primary_mac);
3852 }
3853
3854 static uint32_t
qlnx_get_optics(qlnx_host_t * ha,struct qlnx_link_output * if_link)3855 qlnx_get_optics(qlnx_host_t *ha, struct qlnx_link_output *if_link)
3856 {
3857 uint32_t ifm_type = 0;
3858
3859 switch (if_link->media_type) {
3860 case MEDIA_MODULE_FIBER:
3861 case MEDIA_UNSPECIFIED:
3862 if (if_link->speed == (100 * 1000))
3863 ifm_type = QLNX_IFM_100G_SR4;
3864 else if (if_link->speed == (40 * 1000))
3865 ifm_type = IFM_40G_SR4;
3866 else if (if_link->speed == (25 * 1000))
3867 ifm_type = QLNX_IFM_25G_SR;
3868 else if (if_link->speed == (10 * 1000))
3869 ifm_type = (IFM_10G_LR | IFM_10G_SR);
3870 else if (if_link->speed == (1 * 1000))
3871 ifm_type = (IFM_1000_SX | IFM_1000_LX);
3872
3873 break;
3874
3875 case MEDIA_DA_TWINAX:
3876 if (if_link->speed == (100 * 1000))
3877 ifm_type = QLNX_IFM_100G_CR4;
3878 else if (if_link->speed == (40 * 1000))
3879 ifm_type = IFM_40G_CR4;
3880 else if (if_link->speed == (25 * 1000))
3881 ifm_type = QLNX_IFM_25G_CR;
3882 else if (if_link->speed == (10 * 1000))
3883 ifm_type = IFM_10G_TWINAX;
3884
3885 break;
3886
3887 default :
3888 ifm_type = IFM_UNKNOWN;
3889 break;
3890 }
3891 return (ifm_type);
3892 }
3893
3894 /*****************************************************************************
3895 * Interrupt Service Functions
3896 *****************************************************************************/
3897
3898 static int
qlnx_rx_jumbo_chain(qlnx_host_t * ha,struct qlnx_fastpath * fp,struct mbuf * mp_head,uint16_t len)3899 qlnx_rx_jumbo_chain(qlnx_host_t *ha, struct qlnx_fastpath *fp,
3900 struct mbuf *mp_head, uint16_t len)
3901 {
3902 struct mbuf *mp, *mpf, *mpl;
3903 struct sw_rx_data *sw_rx_data;
3904 struct qlnx_rx_queue *rxq;
3905 uint16_t len_in_buffer;
3906
3907 rxq = fp->rxq;
3908 mpf = mpl = mp = NULL;
3909
3910 while (len) {
3911 rxq->sw_rx_cons = (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
3912
3913 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_cons];
3914 mp = sw_rx_data->data;
3915
3916 if (mp == NULL) {
3917 QL_DPRINT1(ha, "mp = NULL\n");
3918 fp->err_rx_mp_null++;
3919 rxq->sw_rx_cons =
3920 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
3921
3922 if (mpf != NULL)
3923 m_freem(mpf);
3924
3925 return (-1);
3926 }
3927 bus_dmamap_sync(ha->rx_tag, sw_rx_data->map,
3928 BUS_DMASYNC_POSTREAD);
3929
3930 if (qlnx_alloc_rx_buffer(ha, rxq) != 0) {
3931 QL_DPRINT1(ha, "New buffer allocation failed, dropping"
3932 " incoming packet and reusing its buffer\n");
3933
3934 qlnx_reuse_rx_data(rxq);
3935 fp->err_rx_alloc_errors++;
3936
3937 if (mpf != NULL)
3938 m_freem(mpf);
3939
3940 return (-1);
3941 }
3942 ecore_chain_consume(&rxq->rx_bd_ring);
3943
3944 if (len > rxq->rx_buf_size)
3945 len_in_buffer = rxq->rx_buf_size;
3946 else
3947 len_in_buffer = len;
3948
3949 len = len - len_in_buffer;
3950
3951 mp->m_flags &= ~M_PKTHDR;
3952 mp->m_next = NULL;
3953 mp->m_len = len_in_buffer;
3954
3955 if (mpf == NULL)
3956 mpf = mpl = mp;
3957 else {
3958 mpl->m_next = mp;
3959 mpl = mp;
3960 }
3961 }
3962
3963 if (mpf != NULL)
3964 mp_head->m_next = mpf;
3965
3966 return (0);
3967 }
3968
3969 static void
qlnx_tpa_start(qlnx_host_t * ha,struct qlnx_fastpath * fp,struct qlnx_rx_queue * rxq,struct eth_fast_path_rx_tpa_start_cqe * cqe)3970 qlnx_tpa_start(qlnx_host_t *ha,
3971 struct qlnx_fastpath *fp,
3972 struct qlnx_rx_queue *rxq,
3973 struct eth_fast_path_rx_tpa_start_cqe *cqe)
3974 {
3975 uint32_t agg_index;
3976 struct ifnet *ifp = ha->ifp;
3977 struct mbuf *mp;
3978 struct mbuf *mpf = NULL, *mpl = NULL, *mpc = NULL;
3979 struct sw_rx_data *sw_rx_data;
3980 dma_addr_t addr;
3981 bus_dmamap_t map;
3982 struct eth_rx_bd *rx_bd;
3983 int i;
3984 device_t dev;
3985 #if __FreeBSD_version >= 1100000
3986 uint8_t hash_type;
3987 #endif /* #if __FreeBSD_version >= 1100000 */
3988
3989 dev = ha->pci_dev;
3990 agg_index = cqe->tpa_agg_index;
3991
3992 QL_DPRINT7(ha, "[rss_id = %d]: enter\n \
3993 \t type = 0x%x\n \
3994 \t bitfields = 0x%x\n \
3995 \t seg_len = 0x%x\n \
3996 \t pars_flags = 0x%x\n \
3997 \t vlan_tag = 0x%x\n \
3998 \t rss_hash = 0x%x\n \
3999 \t len_on_first_bd = 0x%x\n \
4000 \t placement_offset = 0x%x\n \
4001 \t tpa_agg_index = 0x%x\n \
4002 \t header_len = 0x%x\n \
4003 \t ext_bd_len_list[0] = 0x%x\n \
4004 \t ext_bd_len_list[1] = 0x%x\n \
4005 \t ext_bd_len_list[2] = 0x%x\n \
4006 \t ext_bd_len_list[3] = 0x%x\n \
4007 \t ext_bd_len_list[4] = 0x%x\n",
4008 fp->rss_id, cqe->type, cqe->bitfields, cqe->seg_len,
4009 cqe->pars_flags.flags, cqe->vlan_tag,
4010 cqe->rss_hash, cqe->len_on_first_bd, cqe->placement_offset,
4011 cqe->tpa_agg_index, cqe->header_len,
4012 cqe->ext_bd_len_list[0], cqe->ext_bd_len_list[1],
4013 cqe->ext_bd_len_list[2], cqe->ext_bd_len_list[3],
4014 cqe->ext_bd_len_list[4]);
4015
4016 if (agg_index >= ETH_TPA_MAX_AGGS_NUM) {
4017 fp->err_rx_tpa_invalid_agg_num++;
4018 return;
4019 }
4020
4021 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_cons];
4022 bus_dmamap_sync(ha->rx_tag, sw_rx_data->map, BUS_DMASYNC_POSTREAD);
4023 mp = sw_rx_data->data;
4024
4025 QL_DPRINT7(ha, "[rss_id = %d]: mp = %p \n ", fp->rss_id, mp);
4026
4027 if (mp == NULL) {
4028 QL_DPRINT7(ha, "[%d]: mp = NULL\n", fp->rss_id);
4029 fp->err_rx_mp_null++;
4030 rxq->sw_rx_cons = (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4031
4032 return;
4033 }
4034
4035 if ((le16toh(cqe->pars_flags.flags)) & CQE_FLAGS_ERR) {
4036 QL_DPRINT7(ha, "[%d]: CQE in CONS = %u has error,"
4037 " flags = %x, dropping incoming packet\n", fp->rss_id,
4038 rxq->sw_rx_cons, le16toh(cqe->pars_flags.flags));
4039
4040 fp->err_rx_hw_errors++;
4041
4042 qlnx_reuse_rx_data(rxq);
4043
4044 QLNX_INC_IERRORS(ifp);
4045
4046 return;
4047 }
4048
4049 if (qlnx_alloc_rx_buffer(ha, rxq) != 0) {
4050 QL_DPRINT7(ha, "[%d]: New buffer allocation failed,"
4051 " dropping incoming packet and reusing its buffer\n",
4052 fp->rss_id);
4053
4054 fp->err_rx_alloc_errors++;
4055 QLNX_INC_IQDROPS(ifp);
4056
4057 /*
4058 * Load the tpa mbuf into the rx ring and save the
4059 * posted mbuf
4060 */
4061
4062 map = sw_rx_data->map;
4063 addr = sw_rx_data->dma_addr;
4064
4065 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_prod];
4066
4067 sw_rx_data->data = rxq->tpa_info[agg_index].rx_buf.data;
4068 sw_rx_data->dma_addr = rxq->tpa_info[agg_index].rx_buf.dma_addr;
4069 sw_rx_data->map = rxq->tpa_info[agg_index].rx_buf.map;
4070
4071 rxq->tpa_info[agg_index].rx_buf.data = mp;
4072 rxq->tpa_info[agg_index].rx_buf.dma_addr = addr;
4073 rxq->tpa_info[agg_index].rx_buf.map = map;
4074
4075 rx_bd = (struct eth_rx_bd *)
4076 ecore_chain_produce(&rxq->rx_bd_ring);
4077
4078 rx_bd->addr.hi = htole32(U64_HI(sw_rx_data->dma_addr));
4079 rx_bd->addr.lo = htole32(U64_LO(sw_rx_data->dma_addr));
4080
4081 bus_dmamap_sync(ha->rx_tag, sw_rx_data->map,
4082 BUS_DMASYNC_PREREAD);
4083
4084 rxq->sw_rx_prod = (rxq->sw_rx_prod + 1) & (RX_RING_SIZE - 1);
4085 rxq->sw_rx_cons = (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4086
4087 ecore_chain_consume(&rxq->rx_bd_ring);
4088
4089 /* Now reuse any buffers posted in ext_bd_len_list */
4090 for (i = 0; i < ETH_TPA_CQE_START_LEN_LIST_SIZE; i++) {
4091 if (cqe->ext_bd_len_list[i] == 0)
4092 break;
4093
4094 qlnx_reuse_rx_data(rxq);
4095 }
4096
4097 rxq->tpa_info[agg_index].agg_state = QLNX_AGG_STATE_ERROR;
4098 return;
4099 }
4100
4101 if (rxq->tpa_info[agg_index].agg_state != QLNX_AGG_STATE_NONE) {
4102 QL_DPRINT7(ha, "[%d]: invalid aggregation state,"
4103 " dropping incoming packet and reusing its buffer\n",
4104 fp->rss_id);
4105
4106 QLNX_INC_IQDROPS(ifp);
4107
4108 /* if we already have mbuf head in aggregation free it */
4109 if (rxq->tpa_info[agg_index].mpf) {
4110 m_freem(rxq->tpa_info[agg_index].mpf);
4111 rxq->tpa_info[agg_index].mpl = NULL;
4112 }
4113 rxq->tpa_info[agg_index].mpf = mp;
4114 rxq->tpa_info[agg_index].mpl = NULL;
4115
4116 rxq->sw_rx_cons = (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4117 ecore_chain_consume(&rxq->rx_bd_ring);
4118
4119 /* Now reuse any buffers posted in ext_bd_len_list */
4120 for (i = 0; i < ETH_TPA_CQE_START_LEN_LIST_SIZE; i++) {
4121 if (cqe->ext_bd_len_list[i] == 0)
4122 break;
4123
4124 qlnx_reuse_rx_data(rxq);
4125 }
4126 rxq->tpa_info[agg_index].agg_state = QLNX_AGG_STATE_ERROR;
4127
4128 return;
4129 }
4130
4131 /*
4132 * first process the ext_bd_len_list
4133 * if this fails then we simply drop the packet
4134 */
4135 ecore_chain_consume(&rxq->rx_bd_ring);
4136 rxq->sw_rx_cons = (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4137
4138 for (i = 0; i < ETH_TPA_CQE_START_LEN_LIST_SIZE; i++) {
4139 QL_DPRINT7(ha, "[%d]: 4\n ", fp->rss_id);
4140
4141 if (cqe->ext_bd_len_list[i] == 0)
4142 break;
4143
4144 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_cons];
4145 bus_dmamap_sync(ha->rx_tag, sw_rx_data->map,
4146 BUS_DMASYNC_POSTREAD);
4147
4148 mpc = sw_rx_data->data;
4149
4150 if (mpc == NULL) {
4151 QL_DPRINT7(ha, "[%d]: mpc = NULL\n", fp->rss_id);
4152 fp->err_rx_mp_null++;
4153 if (mpf != NULL)
4154 m_freem(mpf);
4155 mpf = mpl = NULL;
4156 rxq->tpa_info[agg_index].agg_state =
4157 QLNX_AGG_STATE_ERROR;
4158 ecore_chain_consume(&rxq->rx_bd_ring);
4159 rxq->sw_rx_cons =
4160 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4161 continue;
4162 }
4163
4164 if (qlnx_alloc_rx_buffer(ha, rxq) != 0) {
4165 QL_DPRINT7(ha, "[%d]: New buffer allocation failed,"
4166 " dropping incoming packet and reusing its"
4167 " buffer\n", fp->rss_id);
4168
4169 qlnx_reuse_rx_data(rxq);
4170
4171 if (mpf != NULL)
4172 m_freem(mpf);
4173 mpf = mpl = NULL;
4174
4175 rxq->tpa_info[agg_index].agg_state =
4176 QLNX_AGG_STATE_ERROR;
4177
4178 ecore_chain_consume(&rxq->rx_bd_ring);
4179 rxq->sw_rx_cons =
4180 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4181
4182 continue;
4183 }
4184
4185 mpc->m_flags &= ~M_PKTHDR;
4186 mpc->m_next = NULL;
4187 mpc->m_len = cqe->ext_bd_len_list[i];
4188
4189 if (mpf == NULL) {
4190 mpf = mpl = mpc;
4191 } else {
4192 mpl->m_len = ha->rx_buf_size;
4193 mpl->m_next = mpc;
4194 mpl = mpc;
4195 }
4196
4197 ecore_chain_consume(&rxq->rx_bd_ring);
4198 rxq->sw_rx_cons =
4199 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4200 }
4201
4202 if (rxq->tpa_info[agg_index].agg_state != QLNX_AGG_STATE_NONE) {
4203 QL_DPRINT7(ha, "[%d]: invalid aggregation state, dropping"
4204 " incoming packet and reusing its buffer\n",
4205 fp->rss_id);
4206
4207 QLNX_INC_IQDROPS(ifp);
4208
4209 rxq->tpa_info[agg_index].mpf = mp;
4210 rxq->tpa_info[agg_index].mpl = NULL;
4211
4212 return;
4213 }
4214
4215 rxq->tpa_info[agg_index].placement_offset = cqe->placement_offset;
4216
4217 if (mpf != NULL) {
4218 mp->m_len = ha->rx_buf_size;
4219 mp->m_next = mpf;
4220 rxq->tpa_info[agg_index].mpf = mp;
4221 rxq->tpa_info[agg_index].mpl = mpl;
4222 } else {
4223 mp->m_len = cqe->len_on_first_bd + cqe->placement_offset;
4224 rxq->tpa_info[agg_index].mpf = mp;
4225 rxq->tpa_info[agg_index].mpl = mp;
4226 mp->m_next = NULL;
4227 }
4228
4229 mp->m_flags |= M_PKTHDR;
4230
4231 /* assign packet to this interface interface */
4232 mp->m_pkthdr.rcvif = ifp;
4233
4234 /* assume no hardware checksum has complated */
4235 mp->m_pkthdr.csum_flags = 0;
4236
4237 //mp->m_pkthdr.flowid = fp->rss_id;
4238 mp->m_pkthdr.flowid = cqe->rss_hash;
4239
4240 #if __FreeBSD_version >= 1100000
4241
4242 hash_type = cqe->bitfields &
4243 (ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK <<
4244 ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT);
4245
4246 switch (hash_type) {
4247 case RSS_HASH_TYPE_IPV4:
4248 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_IPV4);
4249 break;
4250
4251 case RSS_HASH_TYPE_TCP_IPV4:
4252 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_TCP_IPV4);
4253 break;
4254
4255 case RSS_HASH_TYPE_IPV6:
4256 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_IPV6);
4257 break;
4258
4259 case RSS_HASH_TYPE_TCP_IPV6:
4260 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_TCP_IPV6);
4261 break;
4262
4263 default:
4264 M_HASHTYPE_SET(mp, M_HASHTYPE_OPAQUE);
4265 break;
4266 }
4267
4268 #else
4269 mp->m_flags |= M_FLOWID;
4270 #endif
4271
4272 mp->m_pkthdr.csum_flags |= (CSUM_IP_CHECKED | CSUM_IP_VALID |
4273 CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
4274
4275 mp->m_pkthdr.csum_data = 0xFFFF;
4276
4277 if (CQE_HAS_VLAN(cqe->pars_flags.flags)) {
4278 mp->m_pkthdr.ether_vtag = le16toh(cqe->vlan_tag);
4279 mp->m_flags |= M_VLANTAG;
4280 }
4281
4282 rxq->tpa_info[agg_index].agg_state = QLNX_AGG_STATE_START;
4283
4284 QL_DPRINT7(ha, "[%d]: 5\n\tagg_state = %d\n\t mpf = %p mpl = %p\n",
4285 fp->rss_id, rxq->tpa_info[agg_index].agg_state,
4286 rxq->tpa_info[agg_index].mpf, rxq->tpa_info[agg_index].mpl);
4287
4288 return;
4289 }
4290
4291 static void
qlnx_tpa_cont(qlnx_host_t * ha,struct qlnx_fastpath * fp,struct qlnx_rx_queue * rxq,struct eth_fast_path_rx_tpa_cont_cqe * cqe)4292 qlnx_tpa_cont(qlnx_host_t *ha, struct qlnx_fastpath *fp,
4293 struct qlnx_rx_queue *rxq,
4294 struct eth_fast_path_rx_tpa_cont_cqe *cqe)
4295 {
4296 struct sw_rx_data *sw_rx_data;
4297 int i;
4298 struct mbuf *mpf = NULL, *mpl = NULL, *mpc = NULL;
4299 struct mbuf *mp;
4300 uint32_t agg_index;
4301 device_t dev;
4302
4303 dev = ha->pci_dev;
4304
4305 QL_DPRINT7(ha, "[%d]: enter\n \
4306 \t type = 0x%x\n \
4307 \t tpa_agg_index = 0x%x\n \
4308 \t len_list[0] = 0x%x\n \
4309 \t len_list[1] = 0x%x\n \
4310 \t len_list[2] = 0x%x\n \
4311 \t len_list[3] = 0x%x\n \
4312 \t len_list[4] = 0x%x\n \
4313 \t len_list[5] = 0x%x\n",
4314 fp->rss_id, cqe->type, cqe->tpa_agg_index,
4315 cqe->len_list[0], cqe->len_list[1], cqe->len_list[2],
4316 cqe->len_list[3], cqe->len_list[4], cqe->len_list[5]);
4317
4318 agg_index = cqe->tpa_agg_index;
4319
4320 if (agg_index >= ETH_TPA_MAX_AGGS_NUM) {
4321 QL_DPRINT7(ha, "[%d]: 0\n ", fp->rss_id);
4322 fp->err_rx_tpa_invalid_agg_num++;
4323 return;
4324 }
4325
4326 for (i = 0; i < ETH_TPA_CQE_CONT_LEN_LIST_SIZE; i++) {
4327 QL_DPRINT7(ha, "[%d]: 1\n ", fp->rss_id);
4328
4329 if (cqe->len_list[i] == 0)
4330 break;
4331
4332 if (rxq->tpa_info[agg_index].agg_state !=
4333 QLNX_AGG_STATE_START) {
4334 qlnx_reuse_rx_data(rxq);
4335 continue;
4336 }
4337
4338 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_cons];
4339 bus_dmamap_sync(ha->rx_tag, sw_rx_data->map,
4340 BUS_DMASYNC_POSTREAD);
4341
4342 mpc = sw_rx_data->data;
4343
4344 if (mpc == NULL) {
4345 QL_DPRINT7(ha, "[%d]: mpc = NULL\n", fp->rss_id);
4346
4347 fp->err_rx_mp_null++;
4348 if (mpf != NULL)
4349 m_freem(mpf);
4350 mpf = mpl = NULL;
4351 rxq->tpa_info[agg_index].agg_state =
4352 QLNX_AGG_STATE_ERROR;
4353 ecore_chain_consume(&rxq->rx_bd_ring);
4354 rxq->sw_rx_cons =
4355 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4356 continue;
4357 }
4358
4359 if (qlnx_alloc_rx_buffer(ha, rxq) != 0) {
4360 QL_DPRINT7(ha, "[%d]: New buffer allocation failed,"
4361 " dropping incoming packet and reusing its"
4362 " buffer\n", fp->rss_id);
4363
4364 qlnx_reuse_rx_data(rxq);
4365
4366 if (mpf != NULL)
4367 m_freem(mpf);
4368 mpf = mpl = NULL;
4369
4370 rxq->tpa_info[agg_index].agg_state =
4371 QLNX_AGG_STATE_ERROR;
4372
4373 ecore_chain_consume(&rxq->rx_bd_ring);
4374 rxq->sw_rx_cons =
4375 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4376
4377 continue;
4378 }
4379
4380 mpc->m_flags &= ~M_PKTHDR;
4381 mpc->m_next = NULL;
4382 mpc->m_len = cqe->len_list[i];
4383
4384 if (mpf == NULL) {
4385 mpf = mpl = mpc;
4386 } else {
4387 mpl->m_len = ha->rx_buf_size;
4388 mpl->m_next = mpc;
4389 mpl = mpc;
4390 }
4391
4392 ecore_chain_consume(&rxq->rx_bd_ring);
4393 rxq->sw_rx_cons =
4394 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4395 }
4396
4397 QL_DPRINT7(ha, "[%d]: 2\n" "\tmpf = %p mpl = %p\n",
4398 fp->rss_id, mpf, mpl);
4399
4400 if (mpf != NULL) {
4401 mp = rxq->tpa_info[agg_index].mpl;
4402 mp->m_len = ha->rx_buf_size;
4403 mp->m_next = mpf;
4404 rxq->tpa_info[agg_index].mpl = mpl;
4405 }
4406
4407 return;
4408 }
4409
4410 static int
qlnx_tpa_end(qlnx_host_t * ha,struct qlnx_fastpath * fp,struct qlnx_rx_queue * rxq,struct eth_fast_path_rx_tpa_end_cqe * cqe)4411 qlnx_tpa_end(qlnx_host_t *ha, struct qlnx_fastpath *fp,
4412 struct qlnx_rx_queue *rxq,
4413 struct eth_fast_path_rx_tpa_end_cqe *cqe)
4414 {
4415 struct sw_rx_data *sw_rx_data;
4416 int i;
4417 struct mbuf *mpf = NULL, *mpl = NULL, *mpc = NULL;
4418 struct mbuf *mp;
4419 uint32_t agg_index;
4420 uint32_t len = 0;
4421 struct ifnet *ifp = ha->ifp;
4422 device_t dev;
4423
4424 dev = ha->pci_dev;
4425
4426 QL_DPRINT7(ha, "[%d]: enter\n \
4427 \t type = 0x%x\n \
4428 \t tpa_agg_index = 0x%x\n \
4429 \t total_packet_len = 0x%x\n \
4430 \t num_of_bds = 0x%x\n \
4431 \t end_reason = 0x%x\n \
4432 \t num_of_coalesced_segs = 0x%x\n \
4433 \t ts_delta = 0x%x\n \
4434 \t len_list[0] = 0x%x\n \
4435 \t len_list[1] = 0x%x\n \
4436 \t len_list[2] = 0x%x\n \
4437 \t len_list[3] = 0x%x\n",
4438 fp->rss_id, cqe->type, cqe->tpa_agg_index,
4439 cqe->total_packet_len, cqe->num_of_bds,
4440 cqe->end_reason, cqe->num_of_coalesced_segs, cqe->ts_delta,
4441 cqe->len_list[0], cqe->len_list[1], cqe->len_list[2],
4442 cqe->len_list[3]);
4443
4444 agg_index = cqe->tpa_agg_index;
4445
4446 if (agg_index >= ETH_TPA_MAX_AGGS_NUM) {
4447 QL_DPRINT7(ha, "[%d]: 0\n ", fp->rss_id);
4448
4449 fp->err_rx_tpa_invalid_agg_num++;
4450 return (0);
4451 }
4452
4453 for (i = 0; i < ETH_TPA_CQE_END_LEN_LIST_SIZE; i++) {
4454 QL_DPRINT7(ha, "[%d]: 1\n ", fp->rss_id);
4455
4456 if (cqe->len_list[i] == 0)
4457 break;
4458
4459 if (rxq->tpa_info[agg_index].agg_state !=
4460 QLNX_AGG_STATE_START) {
4461 QL_DPRINT7(ha, "[%d]: 2\n ", fp->rss_id);
4462
4463 qlnx_reuse_rx_data(rxq);
4464 continue;
4465 }
4466
4467 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_cons];
4468 bus_dmamap_sync(ha->rx_tag, sw_rx_data->map,
4469 BUS_DMASYNC_POSTREAD);
4470
4471 mpc = sw_rx_data->data;
4472
4473 if (mpc == NULL) {
4474 QL_DPRINT7(ha, "[%d]: mpc = NULL\n", fp->rss_id);
4475
4476 fp->err_rx_mp_null++;
4477 if (mpf != NULL)
4478 m_freem(mpf);
4479 mpf = mpl = NULL;
4480 rxq->tpa_info[agg_index].agg_state =
4481 QLNX_AGG_STATE_ERROR;
4482 ecore_chain_consume(&rxq->rx_bd_ring);
4483 rxq->sw_rx_cons =
4484 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4485 continue;
4486 }
4487
4488 if (qlnx_alloc_rx_buffer(ha, rxq) != 0) {
4489 QL_DPRINT7(ha, "[%d]: New buffer allocation failed,"
4490 " dropping incoming packet and reusing its"
4491 " buffer\n", fp->rss_id);
4492
4493 qlnx_reuse_rx_data(rxq);
4494
4495 if (mpf != NULL)
4496 m_freem(mpf);
4497 mpf = mpl = NULL;
4498
4499 rxq->tpa_info[agg_index].agg_state =
4500 QLNX_AGG_STATE_ERROR;
4501
4502 ecore_chain_consume(&rxq->rx_bd_ring);
4503 rxq->sw_rx_cons =
4504 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4505
4506 continue;
4507 }
4508
4509 mpc->m_flags &= ~M_PKTHDR;
4510 mpc->m_next = NULL;
4511 mpc->m_len = cqe->len_list[i];
4512
4513 if (mpf == NULL) {
4514 mpf = mpl = mpc;
4515 } else {
4516 mpl->m_len = ha->rx_buf_size;
4517 mpl->m_next = mpc;
4518 mpl = mpc;
4519 }
4520
4521 ecore_chain_consume(&rxq->rx_bd_ring);
4522 rxq->sw_rx_cons =
4523 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4524 }
4525
4526 QL_DPRINT7(ha, "[%d]: 5\n ", fp->rss_id);
4527
4528 if (mpf != NULL) {
4529 QL_DPRINT7(ha, "[%d]: 6\n ", fp->rss_id);
4530
4531 mp = rxq->tpa_info[agg_index].mpl;
4532 mp->m_len = ha->rx_buf_size;
4533 mp->m_next = mpf;
4534 }
4535
4536 if (rxq->tpa_info[agg_index].agg_state != QLNX_AGG_STATE_START) {
4537 QL_DPRINT7(ha, "[%d]: 7\n ", fp->rss_id);
4538
4539 if (rxq->tpa_info[agg_index].mpf != NULL)
4540 m_freem(rxq->tpa_info[agg_index].mpf);
4541 rxq->tpa_info[agg_index].mpf = NULL;
4542 rxq->tpa_info[agg_index].mpl = NULL;
4543 rxq->tpa_info[agg_index].agg_state = QLNX_AGG_STATE_NONE;
4544 return (0);
4545 }
4546
4547 mp = rxq->tpa_info[agg_index].mpf;
4548 m_adj(mp, rxq->tpa_info[agg_index].placement_offset);
4549 mp->m_pkthdr.len = cqe->total_packet_len;
4550
4551 if (mp->m_next == NULL)
4552 mp->m_len = mp->m_pkthdr.len;
4553 else {
4554 /* compute the total packet length */
4555 mpf = mp;
4556 while (mpf != NULL) {
4557 len += mpf->m_len;
4558 mpf = mpf->m_next;
4559 }
4560
4561 if (cqe->total_packet_len > len) {
4562 mpl = rxq->tpa_info[agg_index].mpl;
4563 mpl->m_len += (cqe->total_packet_len - len);
4564 }
4565 }
4566
4567 QLNX_INC_IPACKETS(ifp);
4568 QLNX_INC_IBYTES(ifp, (cqe->total_packet_len));
4569
4570 QL_DPRINT7(ha, "[%d]: 8 csum_data = 0x%x csum_flags = 0x%" PRIu64 "\n \
4571 m_len = 0x%x m_pkthdr_len = 0x%x\n",
4572 fp->rss_id, mp->m_pkthdr.csum_data,
4573 (uint64_t)mp->m_pkthdr.csum_flags, mp->m_len, mp->m_pkthdr.len);
4574
4575 (*ifp->if_input)(ifp, mp);
4576
4577 rxq->tpa_info[agg_index].mpf = NULL;
4578 rxq->tpa_info[agg_index].mpl = NULL;
4579 rxq->tpa_info[agg_index].agg_state = QLNX_AGG_STATE_NONE;
4580
4581 return (cqe->num_of_coalesced_segs);
4582 }
4583
4584 static int
qlnx_rx_int(qlnx_host_t * ha,struct qlnx_fastpath * fp,int budget,int lro_enable)4585 qlnx_rx_int(qlnx_host_t *ha, struct qlnx_fastpath *fp, int budget,
4586 int lro_enable)
4587 {
4588 uint16_t hw_comp_cons, sw_comp_cons;
4589 int rx_pkt = 0;
4590 struct qlnx_rx_queue *rxq = fp->rxq;
4591 struct ifnet *ifp = ha->ifp;
4592 struct ecore_dev *cdev = &ha->cdev;
4593 struct ecore_hwfn *p_hwfn;
4594
4595 #ifdef QLNX_SOFT_LRO
4596 struct lro_ctrl *lro;
4597
4598 lro = &rxq->lro;
4599 #endif /* #ifdef QLNX_SOFT_LRO */
4600
4601 hw_comp_cons = le16toh(*rxq->hw_cons_ptr);
4602 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
4603
4604 p_hwfn = &ha->cdev.hwfns[(fp->rss_id % cdev->num_hwfns)];
4605
4606 /* Memory barrier to prevent the CPU from doing speculative reads of CQE
4607 * / BD in the while-loop before reading hw_comp_cons. If the CQE is
4608 * read before it is written by FW, then FW writes CQE and SB, and then
4609 * the CPU reads the hw_comp_cons, it will use an old CQE.
4610 */
4611
4612 /* Loop to complete all indicated BDs */
4613 while (sw_comp_cons != hw_comp_cons) {
4614 union eth_rx_cqe *cqe;
4615 struct eth_fast_path_rx_reg_cqe *fp_cqe;
4616 struct sw_rx_data *sw_rx_data;
4617 register struct mbuf *mp;
4618 enum eth_rx_cqe_type cqe_type;
4619 uint16_t len, pad, len_on_first_bd;
4620 uint8_t *data;
4621 #if __FreeBSD_version >= 1100000
4622 uint8_t hash_type;
4623 #endif /* #if __FreeBSD_version >= 1100000 */
4624
4625 /* Get the CQE from the completion ring */
4626 cqe = (union eth_rx_cqe *)
4627 ecore_chain_consume(&rxq->rx_comp_ring);
4628 cqe_type = cqe->fast_path_regular.type;
4629
4630 if (cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH) {
4631 QL_DPRINT3(ha, "Got a slowath CQE\n");
4632
4633 ecore_eth_cqe_completion(p_hwfn,
4634 (struct eth_slow_path_rx_cqe *)cqe);
4635 goto next_cqe;
4636 }
4637
4638 if (cqe_type != ETH_RX_CQE_TYPE_REGULAR) {
4639 switch (cqe_type) {
4640 case ETH_RX_CQE_TYPE_TPA_START:
4641 qlnx_tpa_start(ha, fp, rxq,
4642 &cqe->fast_path_tpa_start);
4643 fp->tpa_start++;
4644 break;
4645
4646 case ETH_RX_CQE_TYPE_TPA_CONT:
4647 qlnx_tpa_cont(ha, fp, rxq,
4648 &cqe->fast_path_tpa_cont);
4649 fp->tpa_cont++;
4650 break;
4651
4652 case ETH_RX_CQE_TYPE_TPA_END:
4653 rx_pkt += qlnx_tpa_end(ha, fp, rxq,
4654 &cqe->fast_path_tpa_end);
4655 fp->tpa_end++;
4656 break;
4657
4658 default:
4659 break;
4660 }
4661
4662 goto next_cqe;
4663 }
4664
4665 /* Get the data from the SW ring */
4666 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_cons];
4667 mp = sw_rx_data->data;
4668
4669 if (mp == NULL) {
4670 QL_DPRINT1(ha, "mp = NULL\n");
4671 fp->err_rx_mp_null++;
4672 rxq->sw_rx_cons =
4673 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4674 goto next_cqe;
4675 }
4676 bus_dmamap_sync(ha->rx_tag, sw_rx_data->map,
4677 BUS_DMASYNC_POSTREAD);
4678
4679 /* non GRO */
4680 fp_cqe = &cqe->fast_path_regular;/* MK CR TPA check assembly */
4681 len = le16toh(fp_cqe->pkt_len);
4682 pad = fp_cqe->placement_offset;
4683 #if 0
4684 QL_DPRINT3(ha, "CQE type = %x, flags = %x, vlan = %x,"
4685 " len %u, parsing flags = %d pad = %d\n",
4686 cqe_type, fp_cqe->bitfields,
4687 le16toh(fp_cqe->vlan_tag),
4688 len, le16toh(fp_cqe->pars_flags.flags), pad);
4689 #endif
4690 data = mtod(mp, uint8_t *);
4691 data = data + pad;
4692
4693 if (0)
4694 qlnx_dump_buf8(ha, __func__, data, len);
4695
4696 /* For every Rx BD consumed, we allocate a new BD so the BD ring
4697 * is always with a fixed size. If allocation fails, we take the
4698 * consumed BD and return it to the ring in the PROD position.
4699 * The packet that was received on that BD will be dropped (and
4700 * not passed to the upper stack).
4701 */
4702 /* If this is an error packet then drop it */
4703 if ((le16toh(cqe->fast_path_regular.pars_flags.flags)) &
4704 CQE_FLAGS_ERR) {
4705 QL_DPRINT1(ha, "CQE in CONS = %u has error, flags = %x,"
4706 " dropping incoming packet\n", sw_comp_cons,
4707 le16toh(cqe->fast_path_regular.pars_flags.flags));
4708 fp->err_rx_hw_errors++;
4709
4710 qlnx_reuse_rx_data(rxq);
4711
4712 QLNX_INC_IERRORS(ifp);
4713
4714 goto next_cqe;
4715 }
4716
4717 if (qlnx_alloc_rx_buffer(ha, rxq) != 0) {
4718 QL_DPRINT1(ha, "New buffer allocation failed, dropping"
4719 " incoming packet and reusing its buffer\n");
4720 qlnx_reuse_rx_data(rxq);
4721
4722 fp->err_rx_alloc_errors++;
4723
4724 QLNX_INC_IQDROPS(ifp);
4725
4726 goto next_cqe;
4727 }
4728
4729 ecore_chain_consume(&rxq->rx_bd_ring);
4730
4731 len_on_first_bd = fp_cqe->len_on_first_bd;
4732 m_adj(mp, pad);
4733 mp->m_pkthdr.len = len;
4734
4735 if ((len > 60 ) && (len > len_on_first_bd)) {
4736 mp->m_len = len_on_first_bd;
4737
4738 if (qlnx_rx_jumbo_chain(ha, fp, mp,
4739 (len - len_on_first_bd)) != 0) {
4740 m_freem(mp);
4741
4742 QLNX_INC_IQDROPS(ifp);
4743
4744 goto next_cqe;
4745 }
4746
4747 } else if (len_on_first_bd < len) {
4748 fp->err_rx_jumbo_chain_pkts++;
4749 } else {
4750 mp->m_len = len;
4751 }
4752
4753 mp->m_flags |= M_PKTHDR;
4754
4755 /* assign packet to this interface interface */
4756 mp->m_pkthdr.rcvif = ifp;
4757
4758 /* assume no hardware checksum has complated */
4759 mp->m_pkthdr.csum_flags = 0;
4760
4761 mp->m_pkthdr.flowid = fp_cqe->rss_hash;
4762
4763 #if __FreeBSD_version >= 1100000
4764
4765 hash_type = fp_cqe->bitfields &
4766 (ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK <<
4767 ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT);
4768
4769 switch (hash_type) {
4770 case RSS_HASH_TYPE_IPV4:
4771 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_IPV4);
4772 break;
4773
4774 case RSS_HASH_TYPE_TCP_IPV4:
4775 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_TCP_IPV4);
4776 break;
4777
4778 case RSS_HASH_TYPE_IPV6:
4779 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_IPV6);
4780 break;
4781
4782 case RSS_HASH_TYPE_TCP_IPV6:
4783 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_TCP_IPV6);
4784 break;
4785
4786 default:
4787 M_HASHTYPE_SET(mp, M_HASHTYPE_OPAQUE);
4788 break;
4789 }
4790
4791 #else
4792 mp->m_flags |= M_FLOWID;
4793 #endif
4794
4795 if (CQE_L3_PACKET(fp_cqe->pars_flags.flags)) {
4796 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4797 }
4798
4799 if (!(CQE_IP_HDR_ERR(fp_cqe->pars_flags.flags))) {
4800 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4801 }
4802
4803 if (CQE_L4_HAS_CSUM(fp_cqe->pars_flags.flags)) {
4804 mp->m_pkthdr.csum_data = 0xFFFF;
4805 mp->m_pkthdr.csum_flags |=
4806 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
4807 }
4808
4809 if (CQE_HAS_VLAN(fp_cqe->pars_flags.flags)) {
4810 mp->m_pkthdr.ether_vtag = le16toh(fp_cqe->vlan_tag);
4811 mp->m_flags |= M_VLANTAG;
4812 }
4813
4814 QLNX_INC_IPACKETS(ifp);
4815 QLNX_INC_IBYTES(ifp, len);
4816
4817 #ifdef QLNX_SOFT_LRO
4818
4819 if (lro_enable) {
4820 #if (__FreeBSD_version >= 1100101) || (defined QLNX_QSORT_LRO)
4821
4822 tcp_lro_queue_mbuf(lro, mp);
4823
4824 #else
4825
4826 if (tcp_lro_rx(lro, mp, 0))
4827 (*ifp->if_input)(ifp, mp);
4828
4829 #endif /* #if (__FreeBSD_version >= 1100101) || (defined QLNX_QSORT_LRO) */
4830
4831 } else {
4832 (*ifp->if_input)(ifp, mp);
4833 }
4834 #else
4835
4836 (*ifp->if_input)(ifp, mp);
4837
4838 #endif /* #ifdef QLNX_SOFT_LRO */
4839
4840 rx_pkt++;
4841
4842 rxq->sw_rx_cons = (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4843
4844 next_cqe: /* don't consume bd rx buffer */
4845 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
4846 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
4847
4848 /* CR TPA - revisit how to handle budget in TPA perhaps
4849 increase on "end" */
4850 if (rx_pkt == budget)
4851 break;
4852 } /* repeat while sw_comp_cons != hw_comp_cons... */
4853
4854 /* Update producers */
4855 qlnx_update_rx_prod(p_hwfn, rxq);
4856
4857 return rx_pkt;
4858 }
4859
4860 /*
4861 * fast path interrupt
4862 */
4863
4864 static void
qlnx_fp_isr(void * arg)4865 qlnx_fp_isr(void *arg)
4866 {
4867 qlnx_ivec_t *ivec = arg;
4868 qlnx_host_t *ha;
4869 struct qlnx_fastpath *fp = NULL;
4870 int idx;
4871
4872 ha = ivec->ha;
4873
4874 if (ha->state != QLNX_STATE_OPEN) {
4875 return;
4876 }
4877
4878 idx = ivec->rss_idx;
4879
4880 if ((idx = ivec->rss_idx) >= ha->num_rss) {
4881 QL_DPRINT1(ha, "illegal interrupt[%d]\n", idx);
4882 ha->err_illegal_intr++;
4883 return;
4884 }
4885 fp = &ha->fp_array[idx];
4886
4887 if (fp == NULL) {
4888 ha->err_fp_null++;
4889 } else {
4890 int rx_int = 0, total_rx_count = 0;
4891 int lro_enable, tc;
4892 struct qlnx_tx_queue *txq;
4893 uint16_t elem_left;
4894
4895 lro_enable = ha->ifp->if_capenable & IFCAP_LRO;
4896
4897 ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
4898
4899 do {
4900 for (tc = 0; tc < ha->num_tc; tc++) {
4901 txq = fp->txq[tc];
4902
4903 if((int)(elem_left =
4904 ecore_chain_get_elem_left(&txq->tx_pbl)) <
4905 QLNX_TX_ELEM_THRESH) {
4906 if (mtx_trylock(&fp->tx_mtx)) {
4907 #ifdef QLNX_TRACE_PERF_DATA
4908 tx_compl = fp->tx_pkts_completed;
4909 #endif
4910
4911 qlnx_tx_int(ha, fp, fp->txq[tc]);
4912 #ifdef QLNX_TRACE_PERF_DATA
4913 fp->tx_pkts_compl_intr +=
4914 (fp->tx_pkts_completed - tx_compl);
4915 if ((fp->tx_pkts_completed - tx_compl) <= 32)
4916 fp->tx_comInt[0]++;
4917 else if (((fp->tx_pkts_completed - tx_compl) > 32) &&
4918 ((fp->tx_pkts_completed - tx_compl) <= 64))
4919 fp->tx_comInt[1]++;
4920 else if(((fp->tx_pkts_completed - tx_compl) > 64) &&
4921 ((fp->tx_pkts_completed - tx_compl) <= 128))
4922 fp->tx_comInt[2]++;
4923 else if(((fp->tx_pkts_completed - tx_compl) > 128))
4924 fp->tx_comInt[3]++;
4925 #endif
4926 mtx_unlock(&fp->tx_mtx);
4927 }
4928 }
4929 }
4930
4931 rx_int = qlnx_rx_int(ha, fp, ha->rx_pkt_threshold,
4932 lro_enable);
4933
4934 if (rx_int) {
4935 fp->rx_pkts += rx_int;
4936 total_rx_count += rx_int;
4937 }
4938
4939 } while (rx_int);
4940
4941 #ifdef QLNX_SOFT_LRO
4942 {
4943 struct lro_ctrl *lro;
4944
4945 lro = &fp->rxq->lro;
4946
4947 if (lro_enable && total_rx_count) {
4948 #if (__FreeBSD_version >= 1100101) || (defined QLNX_QSORT_LRO)
4949
4950 #ifdef QLNX_TRACE_LRO_CNT
4951 if (lro->lro_mbuf_count & ~1023)
4952 fp->lro_cnt_1024++;
4953 else if (lro->lro_mbuf_count & ~511)
4954 fp->lro_cnt_512++;
4955 else if (lro->lro_mbuf_count & ~255)
4956 fp->lro_cnt_256++;
4957 else if (lro->lro_mbuf_count & ~127)
4958 fp->lro_cnt_128++;
4959 else if (lro->lro_mbuf_count & ~63)
4960 fp->lro_cnt_64++;
4961 #endif /* #ifdef QLNX_TRACE_LRO_CNT */
4962
4963 tcp_lro_flush_all(lro);
4964
4965 #else
4966 struct lro_entry *queued;
4967
4968 while ((!SLIST_EMPTY(&lro->lro_active))) {
4969 queued = SLIST_FIRST(&lro->lro_active);
4970 SLIST_REMOVE_HEAD(&lro->lro_active, \
4971 next);
4972 tcp_lro_flush(lro, queued);
4973 }
4974 #endif /* #if (__FreeBSD_version >= 1100101) || (defined QLNX_QSORT_LRO) */
4975 }
4976 }
4977 #endif /* #ifdef QLNX_SOFT_LRO */
4978
4979 ecore_sb_update_sb_idx(fp->sb_info);
4980 rmb();
4981 ecore_sb_ack(fp->sb_info, IGU_INT_ENABLE, 1);
4982 }
4983
4984 return;
4985 }
4986
4987 /*
4988 * slow path interrupt processing function
4989 * can be invoked in polled mode or in interrupt mode via taskqueue.
4990 */
4991 void
qlnx_sp_isr(void * arg)4992 qlnx_sp_isr(void *arg)
4993 {
4994 struct ecore_hwfn *p_hwfn;
4995 qlnx_host_t *ha;
4996
4997 p_hwfn = arg;
4998
4999 ha = (qlnx_host_t *)p_hwfn->p_dev;
5000
5001 ha->sp_interrupts++;
5002
5003 QL_DPRINT2(ha, "enter\n");
5004
5005 ecore_int_sp_dpc(p_hwfn);
5006
5007 QL_DPRINT2(ha, "exit\n");
5008
5009 return;
5010 }
5011
5012 /*****************************************************************************
5013 * Support Functions for DMA'able Memory
5014 *****************************************************************************/
5015
5016 static void
qlnx_dmamap_callback(void * arg,bus_dma_segment_t * segs,int nsegs,int error)5017 qlnx_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
5018 {
5019 *((bus_addr_t *)arg) = 0;
5020
5021 if (error) {
5022 printf("%s: bus_dmamap_load failed (%d)\n", __func__, error);
5023 return;
5024 }
5025
5026 *((bus_addr_t *)arg) = segs[0].ds_addr;
5027
5028 return;
5029 }
5030
5031 static int
qlnx_alloc_dmabuf(qlnx_host_t * ha,qlnx_dma_t * dma_buf)5032 qlnx_alloc_dmabuf(qlnx_host_t *ha, qlnx_dma_t *dma_buf)
5033 {
5034 int ret = 0;
5035 device_t dev;
5036 bus_addr_t b_addr;
5037
5038 dev = ha->pci_dev;
5039
5040 ret = bus_dma_tag_create(
5041 ha->parent_tag,/* parent */
5042 dma_buf->alignment,
5043 ((bus_size_t)(1ULL << 32)),/* boundary */
5044 BUS_SPACE_MAXADDR, /* lowaddr */
5045 BUS_SPACE_MAXADDR, /* highaddr */
5046 NULL, NULL, /* filter, filterarg */
5047 dma_buf->size, /* maxsize */
5048 1, /* nsegments */
5049 dma_buf->size, /* maxsegsize */
5050 0, /* flags */
5051 NULL, NULL, /* lockfunc, lockarg */
5052 &dma_buf->dma_tag);
5053
5054 if (ret) {
5055 QL_DPRINT1(ha, "could not create dma tag\n");
5056 goto qlnx_alloc_dmabuf_exit;
5057 }
5058 ret = bus_dmamem_alloc(dma_buf->dma_tag,
5059 (void **)&dma_buf->dma_b,
5060 (BUS_DMA_ZERO | BUS_DMA_COHERENT | BUS_DMA_NOWAIT),
5061 &dma_buf->dma_map);
5062 if (ret) {
5063 bus_dma_tag_destroy(dma_buf->dma_tag);
5064 QL_DPRINT1(ha, "bus_dmamem_alloc failed\n");
5065 goto qlnx_alloc_dmabuf_exit;
5066 }
5067
5068 ret = bus_dmamap_load(dma_buf->dma_tag,
5069 dma_buf->dma_map,
5070 dma_buf->dma_b,
5071 dma_buf->size,
5072 qlnx_dmamap_callback,
5073 &b_addr, BUS_DMA_NOWAIT);
5074
5075 if (ret || !b_addr) {
5076 bus_dma_tag_destroy(dma_buf->dma_tag);
5077 bus_dmamem_free(dma_buf->dma_tag, dma_buf->dma_b,
5078 dma_buf->dma_map);
5079 ret = -1;
5080 goto qlnx_alloc_dmabuf_exit;
5081 }
5082
5083 dma_buf->dma_addr = b_addr;
5084
5085 qlnx_alloc_dmabuf_exit:
5086
5087 return ret;
5088 }
5089
5090 static void
qlnx_free_dmabuf(qlnx_host_t * ha,qlnx_dma_t * dma_buf)5091 qlnx_free_dmabuf(qlnx_host_t *ha, qlnx_dma_t *dma_buf)
5092 {
5093 bus_dmamap_unload(dma_buf->dma_tag, dma_buf->dma_map);
5094 bus_dmamem_free(dma_buf->dma_tag, dma_buf->dma_b, dma_buf->dma_map);
5095 bus_dma_tag_destroy(dma_buf->dma_tag);
5096 return;
5097 }
5098
5099 void *
qlnx_dma_alloc_coherent(void * ecore_dev,bus_addr_t * phys,uint32_t size)5100 qlnx_dma_alloc_coherent(void *ecore_dev, bus_addr_t *phys, uint32_t size)
5101 {
5102 qlnx_dma_t dma_buf;
5103 qlnx_dma_t *dma_p;
5104 qlnx_host_t *ha;
5105 device_t dev;
5106
5107 ha = (qlnx_host_t *)ecore_dev;
5108 dev = ha->pci_dev;
5109
5110 size = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
5111
5112 memset(&dma_buf, 0, sizeof (qlnx_dma_t));
5113
5114 dma_buf.size = size + PAGE_SIZE;
5115 dma_buf.alignment = 8;
5116
5117 if (qlnx_alloc_dmabuf((qlnx_host_t *)ecore_dev, &dma_buf) != 0)
5118 return (NULL);
5119 bzero((uint8_t *)dma_buf.dma_b, dma_buf.size);
5120
5121 *phys = dma_buf.dma_addr;
5122
5123 dma_p = (qlnx_dma_t *)((uint8_t *)dma_buf.dma_b + size);
5124
5125 memcpy(dma_p, &dma_buf, sizeof(qlnx_dma_t));
5126
5127 QL_DPRINT5(ha, "[%p %p %p %p 0x%08x ]\n",
5128 (void *)dma_buf.dma_map, (void *)dma_buf.dma_tag,
5129 dma_buf.dma_b, (void *)dma_buf.dma_addr, size);
5130
5131 return (dma_buf.dma_b);
5132 }
5133
5134 void
qlnx_dma_free_coherent(void * ecore_dev,void * v_addr,bus_addr_t phys,uint32_t size)5135 qlnx_dma_free_coherent(void *ecore_dev, void *v_addr, bus_addr_t phys,
5136 uint32_t size)
5137 {
5138 qlnx_dma_t dma_buf, *dma_p;
5139 qlnx_host_t *ha;
5140 device_t dev;
5141
5142 ha = (qlnx_host_t *)ecore_dev;
5143 dev = ha->pci_dev;
5144
5145 if (v_addr == NULL)
5146 return;
5147
5148 size = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
5149
5150 dma_p = (qlnx_dma_t *)((uint8_t *)v_addr + size);
5151
5152 QL_DPRINT5(ha, "[%p %p %p %p 0x%08x ]\n",
5153 (void *)dma_p->dma_map, (void *)dma_p->dma_tag,
5154 dma_p->dma_b, (void *)dma_p->dma_addr, size);
5155
5156 dma_buf = *dma_p;
5157
5158 if (!ha->qlnxr_debug)
5159 qlnx_free_dmabuf((qlnx_host_t *)ecore_dev, &dma_buf);
5160 return;
5161 }
5162
5163 static int
qlnx_alloc_parent_dma_tag(qlnx_host_t * ha)5164 qlnx_alloc_parent_dma_tag(qlnx_host_t *ha)
5165 {
5166 int ret;
5167 device_t dev;
5168
5169 dev = ha->pci_dev;
5170
5171 /*
5172 * Allocate parent DMA Tag
5173 */
5174 ret = bus_dma_tag_create(
5175 bus_get_dma_tag(dev), /* parent */
5176 1,((bus_size_t)(1ULL << 32)),/* alignment, boundary */
5177 BUS_SPACE_MAXADDR, /* lowaddr */
5178 BUS_SPACE_MAXADDR, /* highaddr */
5179 NULL, NULL, /* filter, filterarg */
5180 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
5181 0, /* nsegments */
5182 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
5183 0, /* flags */
5184 NULL, NULL, /* lockfunc, lockarg */
5185 &ha->parent_tag);
5186
5187 if (ret) {
5188 QL_DPRINT1(ha, "could not create parent dma tag\n");
5189 return (-1);
5190 }
5191
5192 ha->flags.parent_tag = 1;
5193
5194 return (0);
5195 }
5196
5197 static void
qlnx_free_parent_dma_tag(qlnx_host_t * ha)5198 qlnx_free_parent_dma_tag(qlnx_host_t *ha)
5199 {
5200 if (ha->parent_tag != NULL) {
5201 bus_dma_tag_destroy(ha->parent_tag);
5202 ha->parent_tag = NULL;
5203 }
5204 return;
5205 }
5206
5207 static int
qlnx_alloc_tx_dma_tag(qlnx_host_t * ha)5208 qlnx_alloc_tx_dma_tag(qlnx_host_t *ha)
5209 {
5210 if (bus_dma_tag_create(NULL, /* parent */
5211 1, 0, /* alignment, bounds */
5212 BUS_SPACE_MAXADDR, /* lowaddr */
5213 BUS_SPACE_MAXADDR, /* highaddr */
5214 NULL, NULL, /* filter, filterarg */
5215 QLNX_MAX_TSO_FRAME_SIZE, /* maxsize */
5216 QLNX_MAX_SEGMENTS, /* nsegments */
5217 QLNX_MAX_TX_MBUF_SIZE, /* maxsegsize */
5218 0, /* flags */
5219 NULL, /* lockfunc */
5220 NULL, /* lockfuncarg */
5221 &ha->tx_tag)) {
5222 QL_DPRINT1(ha, "tx_tag alloc failed\n");
5223 return (-1);
5224 }
5225
5226 return (0);
5227 }
5228
5229 static void
qlnx_free_tx_dma_tag(qlnx_host_t * ha)5230 qlnx_free_tx_dma_tag(qlnx_host_t *ha)
5231 {
5232 if (ha->tx_tag != NULL) {
5233 bus_dma_tag_destroy(ha->tx_tag);
5234 ha->tx_tag = NULL;
5235 }
5236 return;
5237 }
5238
5239 static int
qlnx_alloc_rx_dma_tag(qlnx_host_t * ha)5240 qlnx_alloc_rx_dma_tag(qlnx_host_t *ha)
5241 {
5242 if (bus_dma_tag_create(NULL, /* parent */
5243 1, 0, /* alignment, bounds */
5244 BUS_SPACE_MAXADDR, /* lowaddr */
5245 BUS_SPACE_MAXADDR, /* highaddr */
5246 NULL, NULL, /* filter, filterarg */
5247 MJUM9BYTES, /* maxsize */
5248 1, /* nsegments */
5249 MJUM9BYTES, /* maxsegsize */
5250 0, /* flags */
5251 NULL, /* lockfunc */
5252 NULL, /* lockfuncarg */
5253 &ha->rx_tag)) {
5254 QL_DPRINT1(ha, " rx_tag alloc failed\n");
5255
5256 return (-1);
5257 }
5258 return (0);
5259 }
5260
5261 static void
qlnx_free_rx_dma_tag(qlnx_host_t * ha)5262 qlnx_free_rx_dma_tag(qlnx_host_t *ha)
5263 {
5264 if (ha->rx_tag != NULL) {
5265 bus_dma_tag_destroy(ha->rx_tag);
5266 ha->rx_tag = NULL;
5267 }
5268 return;
5269 }
5270
5271 /*********************************
5272 * Exported functions
5273 *********************************/
5274 uint32_t
qlnx_pci_bus_get_bar_size(void * ecore_dev,uint8_t bar_id)5275 qlnx_pci_bus_get_bar_size(void *ecore_dev, uint8_t bar_id)
5276 {
5277 uint32_t bar_size;
5278
5279 bar_id = bar_id * 2;
5280
5281 bar_size = bus_get_resource_count(((qlnx_host_t *)ecore_dev)->pci_dev,
5282 SYS_RES_MEMORY,
5283 PCIR_BAR(bar_id));
5284
5285 return (bar_size);
5286 }
5287
5288 uint32_t
qlnx_pci_read_config_byte(void * ecore_dev,uint32_t pci_reg,uint8_t * reg_value)5289 qlnx_pci_read_config_byte(void *ecore_dev, uint32_t pci_reg, uint8_t *reg_value)
5290 {
5291 *reg_value = pci_read_config(((qlnx_host_t *)ecore_dev)->pci_dev,
5292 pci_reg, 1);
5293 return 0;
5294 }
5295
5296 uint32_t
qlnx_pci_read_config_word(void * ecore_dev,uint32_t pci_reg,uint16_t * reg_value)5297 qlnx_pci_read_config_word(void *ecore_dev, uint32_t pci_reg,
5298 uint16_t *reg_value)
5299 {
5300 *reg_value = pci_read_config(((qlnx_host_t *)ecore_dev)->pci_dev,
5301 pci_reg, 2);
5302 return 0;
5303 }
5304
5305 uint32_t
qlnx_pci_read_config_dword(void * ecore_dev,uint32_t pci_reg,uint32_t * reg_value)5306 qlnx_pci_read_config_dword(void *ecore_dev, uint32_t pci_reg,
5307 uint32_t *reg_value)
5308 {
5309 *reg_value = pci_read_config(((qlnx_host_t *)ecore_dev)->pci_dev,
5310 pci_reg, 4);
5311 return 0;
5312 }
5313
5314 void
qlnx_pci_write_config_byte(void * ecore_dev,uint32_t pci_reg,uint8_t reg_value)5315 qlnx_pci_write_config_byte(void *ecore_dev, uint32_t pci_reg, uint8_t reg_value)
5316 {
5317 pci_write_config(((qlnx_host_t *)ecore_dev)->pci_dev,
5318 pci_reg, reg_value, 1);
5319 return;
5320 }
5321
5322 void
qlnx_pci_write_config_word(void * ecore_dev,uint32_t pci_reg,uint16_t reg_value)5323 qlnx_pci_write_config_word(void *ecore_dev, uint32_t pci_reg,
5324 uint16_t reg_value)
5325 {
5326 pci_write_config(((qlnx_host_t *)ecore_dev)->pci_dev,
5327 pci_reg, reg_value, 2);
5328 return;
5329 }
5330
5331 void
qlnx_pci_write_config_dword(void * ecore_dev,uint32_t pci_reg,uint32_t reg_value)5332 qlnx_pci_write_config_dword(void *ecore_dev, uint32_t pci_reg,
5333 uint32_t reg_value)
5334 {
5335 pci_write_config(((qlnx_host_t *)ecore_dev)->pci_dev,
5336 pci_reg, reg_value, 4);
5337 return;
5338 }
5339
5340 int
qlnx_pci_find_capability(void * ecore_dev,int cap)5341 qlnx_pci_find_capability(void *ecore_dev, int cap)
5342 {
5343 int reg;
5344 qlnx_host_t *ha;
5345
5346 ha = ecore_dev;
5347
5348 if (pci_find_cap(ha->pci_dev, PCIY_EXPRESS, ®) == 0)
5349 return reg;
5350 else {
5351 QL_DPRINT1(ha, "failed\n");
5352 return 0;
5353 }
5354 }
5355
5356 int
qlnx_pci_find_ext_capability(void * ecore_dev,int ext_cap)5357 qlnx_pci_find_ext_capability(void *ecore_dev, int ext_cap)
5358 {
5359 int reg;
5360 qlnx_host_t *ha;
5361
5362 ha = ecore_dev;
5363
5364 if (pci_find_extcap(ha->pci_dev, ext_cap, ®) == 0)
5365 return reg;
5366 else {
5367 QL_DPRINT1(ha, "failed\n");
5368 return 0;
5369 }
5370 }
5371
5372 uint32_t
qlnx_reg_rd32(void * hwfn,uint32_t reg_addr)5373 qlnx_reg_rd32(void *hwfn, uint32_t reg_addr)
5374 {
5375 uint32_t data32;
5376 struct ecore_hwfn *p_hwfn;
5377
5378 p_hwfn = hwfn;
5379
5380 data32 = bus_read_4(((qlnx_host_t *)p_hwfn->p_dev)->pci_reg, \
5381 (bus_size_t)(p_hwfn->reg_offset + reg_addr));
5382
5383 return (data32);
5384 }
5385
5386 void
qlnx_reg_wr32(void * hwfn,uint32_t reg_addr,uint32_t value)5387 qlnx_reg_wr32(void *hwfn, uint32_t reg_addr, uint32_t value)
5388 {
5389 struct ecore_hwfn *p_hwfn = hwfn;
5390
5391 bus_write_4(((qlnx_host_t *)p_hwfn->p_dev)->pci_reg, \
5392 (bus_size_t)(p_hwfn->reg_offset + reg_addr), value);
5393
5394 return;
5395 }
5396
5397 void
qlnx_reg_wr16(void * hwfn,uint32_t reg_addr,uint16_t value)5398 qlnx_reg_wr16(void *hwfn, uint32_t reg_addr, uint16_t value)
5399 {
5400 struct ecore_hwfn *p_hwfn = hwfn;
5401
5402 bus_write_2(((qlnx_host_t *)p_hwfn->p_dev)->pci_reg, \
5403 (bus_size_t)(p_hwfn->reg_offset + reg_addr), value);
5404 return;
5405 }
5406
5407 void
qlnx_dbell_wr32_db(void * hwfn,void * reg_addr,uint32_t value)5408 qlnx_dbell_wr32_db(void *hwfn, void *reg_addr, uint32_t value)
5409 {
5410 struct ecore_dev *cdev;
5411 struct ecore_hwfn *p_hwfn;
5412 uint32_t offset;
5413
5414 p_hwfn = hwfn;
5415
5416 cdev = p_hwfn->p_dev;
5417
5418 offset = (uint32_t)((uint8_t *)reg_addr - (uint8_t *)(p_hwfn->doorbells));
5419 bus_write_4(((qlnx_host_t *)cdev)->pci_dbells, offset, value);
5420
5421 return;
5422 }
5423
5424 void
qlnx_dbell_wr32(void * hwfn,uint32_t reg_addr,uint32_t value)5425 qlnx_dbell_wr32(void *hwfn, uint32_t reg_addr, uint32_t value)
5426 {
5427 struct ecore_hwfn *p_hwfn = hwfn;
5428
5429 bus_write_4(((qlnx_host_t *)p_hwfn->p_dev)->pci_dbells, \
5430 (bus_size_t)(p_hwfn->db_offset + reg_addr), value);
5431
5432 return;
5433 }
5434
5435 uint32_t
qlnx_direct_reg_rd32(void * p_hwfn,uint32_t * reg_addr)5436 qlnx_direct_reg_rd32(void *p_hwfn, uint32_t *reg_addr)
5437 {
5438 uint32_t data32;
5439 bus_size_t offset;
5440 struct ecore_dev *cdev;
5441
5442 cdev = ((struct ecore_hwfn *)p_hwfn)->p_dev;
5443 offset = (bus_size_t)((uint8_t *)reg_addr - (uint8_t *)(cdev->regview));
5444
5445 data32 = bus_read_4(((qlnx_host_t *)cdev)->pci_reg, offset);
5446
5447 return (data32);
5448 }
5449
5450 void
qlnx_direct_reg_wr32(void * p_hwfn,void * reg_addr,uint32_t value)5451 qlnx_direct_reg_wr32(void *p_hwfn, void *reg_addr, uint32_t value)
5452 {
5453 bus_size_t offset;
5454 struct ecore_dev *cdev;
5455
5456 cdev = ((struct ecore_hwfn *)p_hwfn)->p_dev;
5457 offset = (bus_size_t)((uint8_t *)reg_addr - (uint8_t *)(cdev->regview));
5458
5459 bus_write_4(((qlnx_host_t *)cdev)->pci_reg, offset, value);
5460
5461 return;
5462 }
5463
5464 void
qlnx_direct_reg_wr64(void * p_hwfn,void * reg_addr,uint64_t value)5465 qlnx_direct_reg_wr64(void *p_hwfn, void *reg_addr, uint64_t value)
5466 {
5467 bus_size_t offset;
5468 struct ecore_dev *cdev;
5469
5470 cdev = ((struct ecore_hwfn *)p_hwfn)->p_dev;
5471 offset = (bus_size_t)((uint8_t *)reg_addr - (uint8_t *)(cdev->regview));
5472
5473 bus_write_8(((qlnx_host_t *)cdev)->pci_reg, offset, value);
5474 return;
5475 }
5476
5477 void *
qlnx_zalloc(uint32_t size)5478 qlnx_zalloc(uint32_t size)
5479 {
5480 caddr_t va;
5481
5482 va = malloc((unsigned long)size, M_QLNXBUF, M_NOWAIT);
5483 bzero(va, size);
5484 return ((void *)va);
5485 }
5486
5487 void
qlnx_barrier(void * p_dev)5488 qlnx_barrier(void *p_dev)
5489 {
5490 qlnx_host_t *ha;
5491
5492 ha = ((struct ecore_dev *) p_dev)->ha;
5493 bus_barrier(ha->pci_reg, 0, 0, BUS_SPACE_BARRIER_WRITE);
5494 }
5495
5496 void
qlnx_link_update(void * p_hwfn)5497 qlnx_link_update(void *p_hwfn)
5498 {
5499 qlnx_host_t *ha;
5500 int prev_link_state;
5501
5502 ha = (qlnx_host_t *)((struct ecore_hwfn *)p_hwfn)->p_dev;
5503
5504 qlnx_fill_link(ha, p_hwfn, &ha->if_link);
5505
5506 prev_link_state = ha->link_up;
5507 ha->link_up = ha->if_link.link_up;
5508
5509 if (prev_link_state != ha->link_up) {
5510 if (ha->link_up) {
5511 if_link_state_change(ha->ifp, LINK_STATE_UP);
5512 } else {
5513 if_link_state_change(ha->ifp, LINK_STATE_DOWN);
5514 }
5515 }
5516 #ifndef QLNX_VF
5517 #ifdef CONFIG_ECORE_SRIOV
5518
5519 if (qlnx_vf_device(ha) != 0) {
5520 if (ha->sriov_initialized)
5521 qlnx_inform_vf_link_state(p_hwfn, ha);
5522 }
5523
5524 #endif /* #ifdef CONFIG_ECORE_SRIOV */
5525 #endif /* #ifdef QLNX_VF */
5526
5527 return;
5528 }
5529
5530 static void
__qlnx_osal_vf_fill_acquire_resc_req(struct ecore_hwfn * p_hwfn,struct ecore_vf_acquire_sw_info * p_sw_info)5531 __qlnx_osal_vf_fill_acquire_resc_req(struct ecore_hwfn *p_hwfn,
5532 struct ecore_vf_acquire_sw_info *p_sw_info)
5533 {
5534 p_sw_info->driver_version = (QLNX_VERSION_MAJOR << 24) |
5535 (QLNX_VERSION_MINOR << 16) |
5536 QLNX_VERSION_BUILD;
5537 p_sw_info->os_type = VFPF_ACQUIRE_OS_FREEBSD;
5538
5539 return;
5540 }
5541
5542 void
qlnx_osal_vf_fill_acquire_resc_req(void * p_hwfn,void * p_resc_req,void * p_sw_info)5543 qlnx_osal_vf_fill_acquire_resc_req(void *p_hwfn, void *p_resc_req,
5544 void *p_sw_info)
5545 {
5546 __qlnx_osal_vf_fill_acquire_resc_req(p_hwfn, p_sw_info);
5547
5548 return;
5549 }
5550
5551 void
qlnx_fill_link(qlnx_host_t * ha,struct ecore_hwfn * hwfn,struct qlnx_link_output * if_link)5552 qlnx_fill_link(qlnx_host_t *ha, struct ecore_hwfn *hwfn,
5553 struct qlnx_link_output *if_link)
5554 {
5555 struct ecore_mcp_link_params link_params;
5556 struct ecore_mcp_link_state link_state;
5557 uint8_t p_change;
5558 struct ecore_ptt *p_ptt = NULL;
5559
5560 memset(if_link, 0, sizeof(*if_link));
5561 memset(&link_params, 0, sizeof(struct ecore_mcp_link_params));
5562 memset(&link_state, 0, sizeof(struct ecore_mcp_link_state));
5563
5564 ha = (qlnx_host_t *)hwfn->p_dev;
5565
5566 /* Prepare source inputs */
5567 /* we only deal with physical functions */
5568 if (qlnx_vf_device(ha) != 0) {
5569 p_ptt = ecore_ptt_acquire(hwfn);
5570
5571 if (p_ptt == NULL) {
5572 QL_DPRINT1(ha, "ecore_ptt_acquire failed\n");
5573 return;
5574 }
5575
5576 ecore_mcp_get_media_type(hwfn, p_ptt, &if_link->media_type);
5577 ecore_ptt_release(hwfn, p_ptt);
5578
5579 memcpy(&link_params, ecore_mcp_get_link_params(hwfn),
5580 sizeof(link_params));
5581 memcpy(&link_state, ecore_mcp_get_link_state(hwfn),
5582 sizeof(link_state));
5583 } else {
5584 ecore_mcp_get_media_type(hwfn, NULL, &if_link->media_type);
5585 ecore_vf_read_bulletin(hwfn, &p_change);
5586 ecore_vf_get_link_params(hwfn, &link_params);
5587 ecore_vf_get_link_state(hwfn, &link_state);
5588 }
5589
5590 /* Set the link parameters to pass to protocol driver */
5591 if (link_state.link_up) {
5592 if_link->link_up = true;
5593 if_link->speed = link_state.speed;
5594 }
5595
5596 if_link->supported_caps = QLNX_LINK_CAP_FIBRE;
5597
5598 if (link_params.speed.autoneg)
5599 if_link->supported_caps |= QLNX_LINK_CAP_Autoneg;
5600
5601 if (link_params.pause.autoneg ||
5602 (link_params.pause.forced_rx && link_params.pause.forced_tx))
5603 if_link->supported_caps |= QLNX_LINK_CAP_Asym_Pause;
5604
5605 if (link_params.pause.autoneg || link_params.pause.forced_rx ||
5606 link_params.pause.forced_tx)
5607 if_link->supported_caps |= QLNX_LINK_CAP_Pause;
5608
5609 if (link_params.speed.advertised_speeds &
5610 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
5611 if_link->supported_caps |= QLNX_LINK_CAP_1000baseT_Half |
5612 QLNX_LINK_CAP_1000baseT_Full;
5613
5614 if (link_params.speed.advertised_speeds &
5615 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
5616 if_link->supported_caps |= QLNX_LINK_CAP_10000baseKR_Full;
5617
5618 if (link_params.speed.advertised_speeds &
5619 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
5620 if_link->supported_caps |= QLNX_LINK_CAP_25000baseKR_Full;
5621
5622 if (link_params.speed.advertised_speeds &
5623 NVM_CFG1_PORT_DRV_LINK_SPEED_40G)
5624 if_link->supported_caps |= QLNX_LINK_CAP_40000baseLR4_Full;
5625
5626 if (link_params.speed.advertised_speeds &
5627 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
5628 if_link->supported_caps |= QLNX_LINK_CAP_50000baseKR2_Full;
5629
5630 if (link_params.speed.advertised_speeds &
5631 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
5632 if_link->supported_caps |= QLNX_LINK_CAP_100000baseKR4_Full;
5633
5634 if_link->advertised_caps = if_link->supported_caps;
5635
5636 if_link->autoneg = link_params.speed.autoneg;
5637 if_link->duplex = QLNX_LINK_DUPLEX;
5638
5639 /* Link partner capabilities */
5640
5641 if (link_state.partner_adv_speed & ECORE_LINK_PARTNER_SPEED_1G_HD)
5642 if_link->link_partner_caps |= QLNX_LINK_CAP_1000baseT_Half;
5643
5644 if (link_state.partner_adv_speed & ECORE_LINK_PARTNER_SPEED_1G_FD)
5645 if_link->link_partner_caps |= QLNX_LINK_CAP_1000baseT_Full;
5646
5647 if (link_state.partner_adv_speed & ECORE_LINK_PARTNER_SPEED_10G)
5648 if_link->link_partner_caps |= QLNX_LINK_CAP_10000baseKR_Full;
5649
5650 if (link_state.partner_adv_speed & ECORE_LINK_PARTNER_SPEED_25G)
5651 if_link->link_partner_caps |= QLNX_LINK_CAP_25000baseKR_Full;
5652
5653 if (link_state.partner_adv_speed & ECORE_LINK_PARTNER_SPEED_40G)
5654 if_link->link_partner_caps |= QLNX_LINK_CAP_40000baseLR4_Full;
5655
5656 if (link_state.partner_adv_speed & ECORE_LINK_PARTNER_SPEED_50G)
5657 if_link->link_partner_caps |= QLNX_LINK_CAP_50000baseKR2_Full;
5658
5659 if (link_state.partner_adv_speed & ECORE_LINK_PARTNER_SPEED_100G)
5660 if_link->link_partner_caps |= QLNX_LINK_CAP_100000baseKR4_Full;
5661
5662 if (link_state.an_complete)
5663 if_link->link_partner_caps |= QLNX_LINK_CAP_Autoneg;
5664
5665 if (link_state.partner_adv_pause)
5666 if_link->link_partner_caps |= QLNX_LINK_CAP_Pause;
5667
5668 if ((link_state.partner_adv_pause ==
5669 ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE) ||
5670 (link_state.partner_adv_pause ==
5671 ECORE_LINK_PARTNER_BOTH_PAUSE))
5672 if_link->link_partner_caps |= QLNX_LINK_CAP_Asym_Pause;
5673
5674 return;
5675 }
5676
5677 void
qlnx_schedule_recovery(void * p_hwfn)5678 qlnx_schedule_recovery(void *p_hwfn)
5679 {
5680 qlnx_host_t *ha;
5681
5682 ha = (qlnx_host_t *)((struct ecore_hwfn *)p_hwfn)->p_dev;
5683
5684 if (qlnx_vf_device(ha) != 0) {
5685 taskqueue_enqueue(ha->err_taskqueue, &ha->err_task);
5686 }
5687
5688 return;
5689 }
5690
5691 static int
qlnx_nic_setup(struct ecore_dev * cdev,struct ecore_pf_params * func_params)5692 qlnx_nic_setup(struct ecore_dev *cdev, struct ecore_pf_params *func_params)
5693 {
5694 int rc, i;
5695
5696 for (i = 0; i < cdev->num_hwfns; i++) {
5697 struct ecore_hwfn *p_hwfn = &cdev->hwfns[i];
5698 p_hwfn->pf_params = *func_params;
5699
5700 #ifdef QLNX_ENABLE_IWARP
5701 if (qlnx_vf_device((qlnx_host_t *)cdev) != 0) {
5702 p_hwfn->using_ll2 = true;
5703 }
5704 #endif /* #ifdef QLNX_ENABLE_IWARP */
5705 }
5706
5707 rc = ecore_resc_alloc(cdev);
5708 if (rc)
5709 goto qlnx_nic_setup_exit;
5710
5711 ecore_resc_setup(cdev);
5712
5713 qlnx_nic_setup_exit:
5714
5715 return rc;
5716 }
5717
5718 static int
qlnx_nic_start(struct ecore_dev * cdev)5719 qlnx_nic_start(struct ecore_dev *cdev)
5720 {
5721 int rc;
5722 struct ecore_hw_init_params params;
5723
5724 bzero(¶ms, sizeof (struct ecore_hw_init_params));
5725
5726 params.p_tunn = NULL;
5727 params.b_hw_start = true;
5728 params.int_mode = cdev->int_mode;
5729 params.allow_npar_tx_switch = true;
5730 params.bin_fw_data = NULL;
5731
5732 rc = ecore_hw_init(cdev, ¶ms);
5733 if (rc) {
5734 ecore_resc_free(cdev);
5735 return rc;
5736 }
5737
5738 return 0;
5739 }
5740
5741 static int
qlnx_slowpath_start(qlnx_host_t * ha)5742 qlnx_slowpath_start(qlnx_host_t *ha)
5743 {
5744 struct ecore_dev *cdev;
5745 struct ecore_pf_params pf_params;
5746 int rc;
5747
5748 memset(&pf_params, 0, sizeof(struct ecore_pf_params));
5749 pf_params.eth_pf_params.num_cons =
5750 (ha->num_rss) * (ha->num_tc + 1);
5751
5752 #ifdef QLNX_ENABLE_IWARP
5753 if (qlnx_vf_device(ha) != 0) {
5754 if(ha->personality == ECORE_PCI_ETH_IWARP) {
5755 device_printf(ha->pci_dev, "setting parameters required by iWARP dev\n");
5756 pf_params.rdma_pf_params.num_qps = 1024;
5757 pf_params.rdma_pf_params.num_srqs = 1024;
5758 pf_params.rdma_pf_params.gl_pi = ECORE_ROCE_PROTOCOL_INDEX;
5759 pf_params.rdma_pf_params.rdma_protocol = ECORE_RDMA_PROTOCOL_IWARP;
5760 } else if(ha->personality == ECORE_PCI_ETH_ROCE) {
5761 device_printf(ha->pci_dev, "setting parameters required by RoCE dev\n");
5762 pf_params.rdma_pf_params.num_qps = 8192;
5763 pf_params.rdma_pf_params.num_srqs = 8192;
5764 //pf_params.rdma_pf_params.min_dpis = 0;
5765 pf_params.rdma_pf_params.min_dpis = 8;
5766 pf_params.rdma_pf_params.roce_edpm_mode = 0;
5767 pf_params.rdma_pf_params.gl_pi = ECORE_ROCE_PROTOCOL_INDEX;
5768 pf_params.rdma_pf_params.rdma_protocol = ECORE_RDMA_PROTOCOL_ROCE;
5769 }
5770 }
5771 #endif /* #ifdef QLNX_ENABLE_IWARP */
5772
5773 cdev = &ha->cdev;
5774
5775 rc = qlnx_nic_setup(cdev, &pf_params);
5776 if (rc)
5777 goto qlnx_slowpath_start_exit;
5778
5779 cdev->int_mode = ECORE_INT_MODE_MSIX;
5780 cdev->int_coalescing_mode = ECORE_COAL_MODE_ENABLE;
5781
5782 #ifdef QLNX_MAX_COALESCE
5783 cdev->rx_coalesce_usecs = 255;
5784 cdev->tx_coalesce_usecs = 255;
5785 #endif
5786
5787 rc = qlnx_nic_start(cdev);
5788
5789 ha->rx_coalesce_usecs = cdev->rx_coalesce_usecs;
5790 ha->tx_coalesce_usecs = cdev->tx_coalesce_usecs;
5791
5792 #ifdef QLNX_USER_LLDP
5793 (void)qlnx_set_lldp_tlvx(ha, NULL);
5794 #endif /* #ifdef QLNX_USER_LLDP */
5795
5796 qlnx_slowpath_start_exit:
5797
5798 return (rc);
5799 }
5800
5801 static int
qlnx_slowpath_stop(qlnx_host_t * ha)5802 qlnx_slowpath_stop(qlnx_host_t *ha)
5803 {
5804 struct ecore_dev *cdev;
5805 device_t dev = ha->pci_dev;
5806 int i;
5807
5808 cdev = &ha->cdev;
5809
5810 ecore_hw_stop(cdev);
5811
5812 for (i = 0; i < ha->cdev.num_hwfns; i++) {
5813 if (ha->sp_handle[i])
5814 (void)bus_teardown_intr(dev, ha->sp_irq[i],
5815 ha->sp_handle[i]);
5816
5817 ha->sp_handle[i] = NULL;
5818
5819 if (ha->sp_irq[i])
5820 (void) bus_release_resource(dev, SYS_RES_IRQ,
5821 ha->sp_irq_rid[i], ha->sp_irq[i]);
5822 ha->sp_irq[i] = NULL;
5823 }
5824
5825 ecore_resc_free(cdev);
5826
5827 return 0;
5828 }
5829
5830 static void
qlnx_set_id(struct ecore_dev * cdev,char name[NAME_SIZE],char ver_str[VER_SIZE])5831 qlnx_set_id(struct ecore_dev *cdev, char name[NAME_SIZE],
5832 char ver_str[VER_SIZE])
5833 {
5834 int i;
5835
5836 memcpy(cdev->name, name, NAME_SIZE);
5837
5838 for_each_hwfn(cdev, i) {
5839 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i);
5840 }
5841
5842 cdev->drv_type = DRV_ID_DRV_TYPE_FREEBSD;
5843
5844 return ;
5845 }
5846
5847 void
qlnx_get_protocol_stats(void * cdev,int proto_type,void * proto_stats)5848 qlnx_get_protocol_stats(void *cdev, int proto_type, void *proto_stats)
5849 {
5850 enum ecore_mcp_protocol_type type;
5851 union ecore_mcp_protocol_stats *stats;
5852 struct ecore_eth_stats eth_stats;
5853 qlnx_host_t *ha;
5854
5855 ha = cdev;
5856 stats = proto_stats;
5857 type = proto_type;
5858
5859 switch (type) {
5860 case ECORE_MCP_LAN_STATS:
5861 ecore_get_vport_stats((struct ecore_dev *)cdev, ð_stats);
5862 stats->lan_stats.ucast_rx_pkts = eth_stats.common.rx_ucast_pkts;
5863 stats->lan_stats.ucast_tx_pkts = eth_stats.common.tx_ucast_pkts;
5864 stats->lan_stats.fcs_err = -1;
5865 break;
5866
5867 default:
5868 ha->err_get_proto_invalid_type++;
5869
5870 QL_DPRINT1(ha, "invalid protocol type 0x%x\n", type);
5871 break;
5872 }
5873 return;
5874 }
5875
5876 static int
qlnx_get_mfw_version(qlnx_host_t * ha,uint32_t * mfw_ver)5877 qlnx_get_mfw_version(qlnx_host_t *ha, uint32_t *mfw_ver)
5878 {
5879 struct ecore_hwfn *p_hwfn;
5880 struct ecore_ptt *p_ptt;
5881
5882 p_hwfn = &ha->cdev.hwfns[0];
5883 p_ptt = ecore_ptt_acquire(p_hwfn);
5884
5885 if (p_ptt == NULL) {
5886 QL_DPRINT1(ha, "ecore_ptt_acquire failed\n");
5887 return (-1);
5888 }
5889 ecore_mcp_get_mfw_ver(p_hwfn, p_ptt, mfw_ver, NULL);
5890
5891 ecore_ptt_release(p_hwfn, p_ptt);
5892
5893 return (0);
5894 }
5895
5896 static int
qlnx_get_flash_size(qlnx_host_t * ha,uint32_t * flash_size)5897 qlnx_get_flash_size(qlnx_host_t *ha, uint32_t *flash_size)
5898 {
5899 struct ecore_hwfn *p_hwfn;
5900 struct ecore_ptt *p_ptt;
5901
5902 p_hwfn = &ha->cdev.hwfns[0];
5903 p_ptt = ecore_ptt_acquire(p_hwfn);
5904
5905 if (p_ptt == NULL) {
5906 QL_DPRINT1(ha,"ecore_ptt_acquire failed\n");
5907 return (-1);
5908 }
5909 ecore_mcp_get_flash_size(p_hwfn, p_ptt, flash_size);
5910
5911 ecore_ptt_release(p_hwfn, p_ptt);
5912
5913 return (0);
5914 }
5915
5916 static int
qlnx_alloc_mem_arrays(qlnx_host_t * ha)5917 qlnx_alloc_mem_arrays(qlnx_host_t *ha)
5918 {
5919 struct ecore_dev *cdev;
5920
5921 cdev = &ha->cdev;
5922
5923 bzero(&ha->txq_array[0], (sizeof(struct qlnx_tx_queue) * QLNX_MAX_RSS));
5924 bzero(&ha->rxq_array[0], (sizeof(struct qlnx_rx_queue) * QLNX_MAX_RSS));
5925 bzero(&ha->sb_array[0], (sizeof(struct ecore_sb_info) * QLNX_MAX_RSS));
5926
5927 return 0;
5928 }
5929
5930 static void
qlnx_init_fp(qlnx_host_t * ha)5931 qlnx_init_fp(qlnx_host_t *ha)
5932 {
5933 int rss_id, txq_array_index, tc;
5934
5935 for (rss_id = 0; rss_id < ha->num_rss; rss_id++) {
5936 struct qlnx_fastpath *fp = &ha->fp_array[rss_id];
5937
5938 fp->rss_id = rss_id;
5939 fp->edev = ha;
5940 fp->sb_info = &ha->sb_array[rss_id];
5941 fp->rxq = &ha->rxq_array[rss_id];
5942 fp->rxq->rxq_id = rss_id;
5943
5944 for (tc = 0; tc < ha->num_tc; tc++) {
5945 txq_array_index = tc * ha->num_rss + rss_id;
5946 fp->txq[tc] = &ha->txq_array[txq_array_index];
5947 fp->txq[tc]->index = txq_array_index;
5948 }
5949
5950 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d", qlnx_name_str,
5951 rss_id);
5952
5953 fp->tx_ring_full = 0;
5954
5955 /* reset all the statistics counters */
5956
5957 fp->tx_pkts_processed = 0;
5958 fp->tx_pkts_freed = 0;
5959 fp->tx_pkts_transmitted = 0;
5960 fp->tx_pkts_completed = 0;
5961
5962 #ifdef QLNX_TRACE_PERF_DATA
5963 fp->tx_pkts_trans_ctx = 0;
5964 fp->tx_pkts_compl_ctx = 0;
5965 fp->tx_pkts_trans_fp = 0;
5966 fp->tx_pkts_compl_fp = 0;
5967 fp->tx_pkts_compl_intr = 0;
5968 #endif
5969 fp->tx_lso_wnd_min_len = 0;
5970 fp->tx_defrag = 0;
5971 fp->tx_nsegs_gt_elem_left = 0;
5972 fp->tx_tso_max_nsegs = 0;
5973 fp->tx_tso_min_nsegs = 0;
5974 fp->err_tx_nsegs_gt_elem_left = 0;
5975 fp->err_tx_dmamap_create = 0;
5976 fp->err_tx_defrag_dmamap_load = 0;
5977 fp->err_tx_non_tso_max_seg = 0;
5978 fp->err_tx_dmamap_load = 0;
5979 fp->err_tx_defrag = 0;
5980 fp->err_tx_free_pkt_null = 0;
5981 fp->err_tx_cons_idx_conflict = 0;
5982
5983 fp->rx_pkts = 0;
5984 fp->err_m_getcl = 0;
5985 fp->err_m_getjcl = 0;
5986 }
5987 return;
5988 }
5989
5990 void
qlnx_free_mem_sb(qlnx_host_t * ha,struct ecore_sb_info * sb_info)5991 qlnx_free_mem_sb(qlnx_host_t *ha, struct ecore_sb_info *sb_info)
5992 {
5993 struct ecore_dev *cdev;
5994
5995 cdev = &ha->cdev;
5996
5997 if (sb_info->sb_virt) {
5998 OSAL_DMA_FREE_COHERENT(cdev, ((void *)sb_info->sb_virt),
5999 (sb_info->sb_phys), (sizeof(*sb_info->sb_virt)));
6000 sb_info->sb_virt = NULL;
6001 }
6002 }
6003
6004 static int
qlnx_sb_init(struct ecore_dev * cdev,struct ecore_sb_info * sb_info,void * sb_virt_addr,bus_addr_t sb_phy_addr,u16 sb_id)6005 qlnx_sb_init(struct ecore_dev *cdev, struct ecore_sb_info *sb_info,
6006 void *sb_virt_addr, bus_addr_t sb_phy_addr, u16 sb_id)
6007 {
6008 struct ecore_hwfn *p_hwfn;
6009 int hwfn_index, rc;
6010 u16 rel_sb_id;
6011
6012 hwfn_index = sb_id % cdev->num_hwfns;
6013 p_hwfn = &cdev->hwfns[hwfn_index];
6014 rel_sb_id = sb_id / cdev->num_hwfns;
6015
6016 QL_DPRINT2(((qlnx_host_t *)cdev),
6017 "hwfn_index = %d p_hwfn = %p sb_id = 0x%x rel_sb_id = 0x%x \
6018 sb_info = %p sb_virt_addr = %p sb_phy_addr = %p\n",
6019 hwfn_index, p_hwfn, sb_id, rel_sb_id, sb_info,
6020 sb_virt_addr, (void *)sb_phy_addr);
6021
6022 rc = ecore_int_sb_init(p_hwfn, p_hwfn->p_main_ptt, sb_info,
6023 sb_virt_addr, sb_phy_addr, rel_sb_id);
6024
6025 return rc;
6026 }
6027
6028 /* This function allocates fast-path status block memory */
6029 int
qlnx_alloc_mem_sb(qlnx_host_t * ha,struct ecore_sb_info * sb_info,u16 sb_id)6030 qlnx_alloc_mem_sb(qlnx_host_t *ha, struct ecore_sb_info *sb_info, u16 sb_id)
6031 {
6032 struct status_block_e4 *sb_virt;
6033 bus_addr_t sb_phys;
6034 int rc;
6035 uint32_t size;
6036 struct ecore_dev *cdev;
6037
6038 cdev = &ha->cdev;
6039
6040 size = sizeof(*sb_virt);
6041 sb_virt = OSAL_DMA_ALLOC_COHERENT(cdev, (&sb_phys), size);
6042
6043 if (!sb_virt) {
6044 QL_DPRINT1(ha, "Status block allocation failed\n");
6045 return -ENOMEM;
6046 }
6047
6048 rc = qlnx_sb_init(cdev, sb_info, sb_virt, sb_phys, sb_id);
6049 if (rc) {
6050 OSAL_DMA_FREE_COHERENT(cdev, sb_virt, sb_phys, size);
6051 }
6052
6053 return rc;
6054 }
6055
6056 static void
qlnx_free_rx_buffers(qlnx_host_t * ha,struct qlnx_rx_queue * rxq)6057 qlnx_free_rx_buffers(qlnx_host_t *ha, struct qlnx_rx_queue *rxq)
6058 {
6059 int i;
6060 struct sw_rx_data *rx_buf;
6061
6062 for (i = 0; i < rxq->num_rx_buffers; i++) {
6063 rx_buf = &rxq->sw_rx_ring[i];
6064
6065 if (rx_buf->data != NULL) {
6066 if (rx_buf->map != NULL) {
6067 bus_dmamap_unload(ha->rx_tag, rx_buf->map);
6068 bus_dmamap_destroy(ha->rx_tag, rx_buf->map);
6069 rx_buf->map = NULL;
6070 }
6071 m_freem(rx_buf->data);
6072 rx_buf->data = NULL;
6073 }
6074 }
6075 return;
6076 }
6077
6078 static void
qlnx_free_mem_rxq(qlnx_host_t * ha,struct qlnx_rx_queue * rxq)6079 qlnx_free_mem_rxq(qlnx_host_t *ha, struct qlnx_rx_queue *rxq)
6080 {
6081 struct ecore_dev *cdev;
6082 int i;
6083
6084 cdev = &ha->cdev;
6085
6086 qlnx_free_rx_buffers(ha, rxq);
6087
6088 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
6089 qlnx_free_tpa_mbuf(ha, &rxq->tpa_info[i]);
6090 if (rxq->tpa_info[i].mpf != NULL)
6091 m_freem(rxq->tpa_info[i].mpf);
6092 }
6093
6094 bzero((void *)&rxq->sw_rx_ring[0],
6095 (sizeof (struct sw_rx_data) * RX_RING_SIZE));
6096
6097 /* Free the real RQ ring used by FW */
6098 if (rxq->rx_bd_ring.p_virt_addr) {
6099 ecore_chain_free(cdev, &rxq->rx_bd_ring);
6100 rxq->rx_bd_ring.p_virt_addr = NULL;
6101 }
6102
6103 /* Free the real completion ring used by FW */
6104 if (rxq->rx_comp_ring.p_virt_addr &&
6105 rxq->rx_comp_ring.pbl_sp.p_virt_table) {
6106 ecore_chain_free(cdev, &rxq->rx_comp_ring);
6107 rxq->rx_comp_ring.p_virt_addr = NULL;
6108 rxq->rx_comp_ring.pbl_sp.p_virt_table = NULL;
6109 }
6110
6111 #ifdef QLNX_SOFT_LRO
6112 {
6113 struct lro_ctrl *lro;
6114
6115 lro = &rxq->lro;
6116 tcp_lro_free(lro);
6117 }
6118 #endif /* #ifdef QLNX_SOFT_LRO */
6119
6120 return;
6121 }
6122
6123 static int
qlnx_alloc_rx_buffer(qlnx_host_t * ha,struct qlnx_rx_queue * rxq)6124 qlnx_alloc_rx_buffer(qlnx_host_t *ha, struct qlnx_rx_queue *rxq)
6125 {
6126 register struct mbuf *mp;
6127 uint16_t rx_buf_size;
6128 struct sw_rx_data *sw_rx_data;
6129 struct eth_rx_bd *rx_bd;
6130 dma_addr_t dma_addr;
6131 bus_dmamap_t map;
6132 bus_dma_segment_t segs[1];
6133 int nsegs;
6134 int ret;
6135 struct ecore_dev *cdev;
6136
6137 cdev = &ha->cdev;
6138
6139 rx_buf_size = rxq->rx_buf_size;
6140
6141 mp = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, rx_buf_size);
6142
6143 if (mp == NULL) {
6144 QL_DPRINT1(ha, "Failed to allocate Rx data\n");
6145 return -ENOMEM;
6146 }
6147
6148 mp->m_len = mp->m_pkthdr.len = rx_buf_size;
6149
6150 map = (bus_dmamap_t)0;
6151
6152 ret = bus_dmamap_load_mbuf_sg(ha->rx_tag, map, mp, segs, &nsegs,
6153 BUS_DMA_NOWAIT);
6154 dma_addr = segs[0].ds_addr;
6155
6156 if (ret || !dma_addr || (nsegs != 1)) {
6157 m_freem(mp);
6158 QL_DPRINT1(ha, "bus_dmamap_load failed[%d, 0x%016llx, %d]\n",
6159 ret, (long long unsigned int)dma_addr, nsegs);
6160 return -ENOMEM;
6161 }
6162
6163 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_prod];
6164 sw_rx_data->data = mp;
6165 sw_rx_data->dma_addr = dma_addr;
6166 sw_rx_data->map = map;
6167
6168 /* Advance PROD and get BD pointer */
6169 rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
6170 rx_bd->addr.hi = htole32(U64_HI(dma_addr));
6171 rx_bd->addr.lo = htole32(U64_LO(dma_addr));
6172 bus_dmamap_sync(ha->rx_tag, map, BUS_DMASYNC_PREREAD);
6173
6174 rxq->sw_rx_prod = (rxq->sw_rx_prod + 1) & (RX_RING_SIZE - 1);
6175
6176 return 0;
6177 }
6178
6179 static int
qlnx_alloc_tpa_mbuf(qlnx_host_t * ha,uint16_t rx_buf_size,struct qlnx_agg_info * tpa)6180 qlnx_alloc_tpa_mbuf(qlnx_host_t *ha, uint16_t rx_buf_size,
6181 struct qlnx_agg_info *tpa)
6182 {
6183 struct mbuf *mp;
6184 dma_addr_t dma_addr;
6185 bus_dmamap_t map;
6186 bus_dma_segment_t segs[1];
6187 int nsegs;
6188 int ret;
6189 struct sw_rx_data *rx_buf;
6190
6191 mp = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, rx_buf_size);
6192
6193 if (mp == NULL) {
6194 QL_DPRINT1(ha, "Failed to allocate Rx data\n");
6195 return -ENOMEM;
6196 }
6197
6198 mp->m_len = mp->m_pkthdr.len = rx_buf_size;
6199
6200 map = (bus_dmamap_t)0;
6201
6202 ret = bus_dmamap_load_mbuf_sg(ha->rx_tag, map, mp, segs, &nsegs,
6203 BUS_DMA_NOWAIT);
6204 dma_addr = segs[0].ds_addr;
6205
6206 if (ret || !dma_addr || (nsegs != 1)) {
6207 m_freem(mp);
6208 QL_DPRINT1(ha, "bus_dmamap_load failed[%d, 0x%016llx, %d]\n",
6209 ret, (long long unsigned int)dma_addr, nsegs);
6210 return -ENOMEM;
6211 }
6212
6213 rx_buf = &tpa->rx_buf;
6214
6215 memset(rx_buf, 0, sizeof (struct sw_rx_data));
6216
6217 rx_buf->data = mp;
6218 rx_buf->dma_addr = dma_addr;
6219 rx_buf->map = map;
6220
6221 bus_dmamap_sync(ha->rx_tag, map, BUS_DMASYNC_PREREAD);
6222
6223 return (0);
6224 }
6225
6226 static void
qlnx_free_tpa_mbuf(qlnx_host_t * ha,struct qlnx_agg_info * tpa)6227 qlnx_free_tpa_mbuf(qlnx_host_t *ha, struct qlnx_agg_info *tpa)
6228 {
6229 struct sw_rx_data *rx_buf;
6230
6231 rx_buf = &tpa->rx_buf;
6232
6233 if (rx_buf->data != NULL) {
6234 if (rx_buf->map != NULL) {
6235 bus_dmamap_unload(ha->rx_tag, rx_buf->map);
6236 bus_dmamap_destroy(ha->rx_tag, rx_buf->map);
6237 rx_buf->map = NULL;
6238 }
6239 m_freem(rx_buf->data);
6240 rx_buf->data = NULL;
6241 }
6242 return;
6243 }
6244
6245 /* This function allocates all memory needed per Rx queue */
6246 static int
qlnx_alloc_mem_rxq(qlnx_host_t * ha,struct qlnx_rx_queue * rxq)6247 qlnx_alloc_mem_rxq(qlnx_host_t *ha, struct qlnx_rx_queue *rxq)
6248 {
6249 int i, rc, num_allocated;
6250 struct ifnet *ifp;
6251 struct ecore_dev *cdev;
6252
6253 cdev = &ha->cdev;
6254 ifp = ha->ifp;
6255
6256 rxq->num_rx_buffers = RX_RING_SIZE;
6257
6258 rxq->rx_buf_size = ha->rx_buf_size;
6259
6260 /* Allocate the parallel driver ring for Rx buffers */
6261 bzero((void *)&rxq->sw_rx_ring[0],
6262 (sizeof (struct sw_rx_data) * RX_RING_SIZE));
6263
6264 /* Allocate FW Rx ring */
6265
6266 rc = ecore_chain_alloc(cdev,
6267 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
6268 ECORE_CHAIN_MODE_NEXT_PTR,
6269 ECORE_CHAIN_CNT_TYPE_U16,
6270 RX_RING_SIZE,
6271 sizeof(struct eth_rx_bd),
6272 &rxq->rx_bd_ring, NULL);
6273
6274 if (rc)
6275 goto err;
6276
6277 /* Allocate FW completion ring */
6278 rc = ecore_chain_alloc(cdev,
6279 ECORE_CHAIN_USE_TO_CONSUME,
6280 ECORE_CHAIN_MODE_PBL,
6281 ECORE_CHAIN_CNT_TYPE_U16,
6282 RX_RING_SIZE,
6283 sizeof(union eth_rx_cqe),
6284 &rxq->rx_comp_ring, NULL);
6285
6286 if (rc)
6287 goto err;
6288
6289 /* Allocate buffers for the Rx ring */
6290
6291 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
6292 rc = qlnx_alloc_tpa_mbuf(ha, rxq->rx_buf_size,
6293 &rxq->tpa_info[i]);
6294 if (rc)
6295 break;
6296 }
6297
6298 for (i = 0; i < rxq->num_rx_buffers; i++) {
6299 rc = qlnx_alloc_rx_buffer(ha, rxq);
6300 if (rc)
6301 break;
6302 }
6303 num_allocated = i;
6304 if (!num_allocated) {
6305 QL_DPRINT1(ha, "Rx buffers allocation failed\n");
6306 goto err;
6307 } else if (num_allocated < rxq->num_rx_buffers) {
6308 QL_DPRINT1(ha, "Allocated less buffers than"
6309 " desired (%d allocated)\n", num_allocated);
6310 }
6311
6312 #ifdef QLNX_SOFT_LRO
6313
6314 {
6315 struct lro_ctrl *lro;
6316
6317 lro = &rxq->lro;
6318
6319 #if (__FreeBSD_version >= 1100101) || (defined QLNX_QSORT_LRO)
6320 if (tcp_lro_init_args(lro, ifp, 0, rxq->num_rx_buffers)) {
6321 QL_DPRINT1(ha, "tcp_lro_init[%d] failed\n",
6322 rxq->rxq_id);
6323 goto err;
6324 }
6325 #else
6326 if (tcp_lro_init(lro)) {
6327 QL_DPRINT1(ha, "tcp_lro_init[%d] failed\n",
6328 rxq->rxq_id);
6329 goto err;
6330 }
6331 #endif /* #if (__FreeBSD_version >= 1100101) || (defined QLNX_QSORT_LRO) */
6332
6333 lro->ifp = ha->ifp;
6334 }
6335 #endif /* #ifdef QLNX_SOFT_LRO */
6336 return 0;
6337
6338 err:
6339 qlnx_free_mem_rxq(ha, rxq);
6340 return -ENOMEM;
6341 }
6342
6343 static void
qlnx_free_mem_txq(qlnx_host_t * ha,struct qlnx_fastpath * fp,struct qlnx_tx_queue * txq)6344 qlnx_free_mem_txq(qlnx_host_t *ha, struct qlnx_fastpath *fp,
6345 struct qlnx_tx_queue *txq)
6346 {
6347 struct ecore_dev *cdev;
6348
6349 cdev = &ha->cdev;
6350
6351 bzero((void *)&txq->sw_tx_ring[0],
6352 (sizeof (struct sw_tx_bd) * TX_RING_SIZE));
6353
6354 /* Free the real RQ ring used by FW */
6355 if (txq->tx_pbl.p_virt_addr) {
6356 ecore_chain_free(cdev, &txq->tx_pbl);
6357 txq->tx_pbl.p_virt_addr = NULL;
6358 }
6359 return;
6360 }
6361
6362 /* This function allocates all memory needed per Tx queue */
6363 static int
qlnx_alloc_mem_txq(qlnx_host_t * ha,struct qlnx_fastpath * fp,struct qlnx_tx_queue * txq)6364 qlnx_alloc_mem_txq(qlnx_host_t *ha, struct qlnx_fastpath *fp,
6365 struct qlnx_tx_queue *txq)
6366 {
6367 int ret = ECORE_SUCCESS;
6368 union eth_tx_bd_types *p_virt;
6369 struct ecore_dev *cdev;
6370
6371 cdev = &ha->cdev;
6372
6373 bzero((void *)&txq->sw_tx_ring[0],
6374 (sizeof (struct sw_tx_bd) * TX_RING_SIZE));
6375
6376 /* Allocate the real Tx ring to be used by FW */
6377 ret = ecore_chain_alloc(cdev,
6378 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
6379 ECORE_CHAIN_MODE_PBL,
6380 ECORE_CHAIN_CNT_TYPE_U16,
6381 TX_RING_SIZE,
6382 sizeof(*p_virt),
6383 &txq->tx_pbl, NULL);
6384
6385 if (ret != ECORE_SUCCESS) {
6386 goto err;
6387 }
6388
6389 txq->num_tx_buffers = TX_RING_SIZE;
6390
6391 return 0;
6392
6393 err:
6394 qlnx_free_mem_txq(ha, fp, txq);
6395 return -ENOMEM;
6396 }
6397
6398 static void
qlnx_free_tx_br(qlnx_host_t * ha,struct qlnx_fastpath * fp)6399 qlnx_free_tx_br(qlnx_host_t *ha, struct qlnx_fastpath *fp)
6400 {
6401 struct mbuf *mp;
6402 struct ifnet *ifp = ha->ifp;
6403
6404 if (mtx_initialized(&fp->tx_mtx)) {
6405 if (fp->tx_br != NULL) {
6406 mtx_lock(&fp->tx_mtx);
6407
6408 while ((mp = drbr_dequeue(ifp, fp->tx_br)) != NULL) {
6409 fp->tx_pkts_freed++;
6410 m_freem(mp);
6411 }
6412
6413 mtx_unlock(&fp->tx_mtx);
6414
6415 buf_ring_free(fp->tx_br, M_DEVBUF);
6416 fp->tx_br = NULL;
6417 }
6418 mtx_destroy(&fp->tx_mtx);
6419 }
6420 return;
6421 }
6422
6423 static void
qlnx_free_mem_fp(qlnx_host_t * ha,struct qlnx_fastpath * fp)6424 qlnx_free_mem_fp(qlnx_host_t *ha, struct qlnx_fastpath *fp)
6425 {
6426 int tc;
6427
6428 qlnx_free_mem_sb(ha, fp->sb_info);
6429
6430 qlnx_free_mem_rxq(ha, fp->rxq);
6431
6432 for (tc = 0; tc < ha->num_tc; tc++)
6433 qlnx_free_mem_txq(ha, fp, fp->txq[tc]);
6434
6435 return;
6436 }
6437
6438 static int
qlnx_alloc_tx_br(qlnx_host_t * ha,struct qlnx_fastpath * fp)6439 qlnx_alloc_tx_br(qlnx_host_t *ha, struct qlnx_fastpath *fp)
6440 {
6441 snprintf(fp->tx_mtx_name, sizeof(fp->tx_mtx_name),
6442 "qlnx%d_fp%d_tx_mq_lock", ha->dev_unit, fp->rss_id);
6443
6444 mtx_init(&fp->tx_mtx, fp->tx_mtx_name, NULL, MTX_DEF);
6445
6446 fp->tx_br = buf_ring_alloc(TX_RING_SIZE, M_DEVBUF,
6447 M_NOWAIT, &fp->tx_mtx);
6448 if (fp->tx_br == NULL) {
6449 QL_DPRINT1(ha, "buf_ring_alloc failed for fp[%d, %d]\n",
6450 ha->dev_unit, fp->rss_id);
6451 return -ENOMEM;
6452 }
6453 return 0;
6454 }
6455
6456 static int
qlnx_alloc_mem_fp(qlnx_host_t * ha,struct qlnx_fastpath * fp)6457 qlnx_alloc_mem_fp(qlnx_host_t *ha, struct qlnx_fastpath *fp)
6458 {
6459 int rc, tc;
6460
6461 rc = qlnx_alloc_mem_sb(ha, fp->sb_info, fp->rss_id);
6462 if (rc)
6463 goto err;
6464
6465 if (ha->rx_jumbo_buf_eq_mtu) {
6466 if (ha->max_frame_size <= MCLBYTES)
6467 ha->rx_buf_size = MCLBYTES;
6468 else if (ha->max_frame_size <= MJUMPAGESIZE)
6469 ha->rx_buf_size = MJUMPAGESIZE;
6470 else if (ha->max_frame_size <= MJUM9BYTES)
6471 ha->rx_buf_size = MJUM9BYTES;
6472 else if (ha->max_frame_size <= MJUM16BYTES)
6473 ha->rx_buf_size = MJUM16BYTES;
6474 } else {
6475 if (ha->max_frame_size <= MCLBYTES)
6476 ha->rx_buf_size = MCLBYTES;
6477 else
6478 ha->rx_buf_size = MJUMPAGESIZE;
6479 }
6480
6481 rc = qlnx_alloc_mem_rxq(ha, fp->rxq);
6482 if (rc)
6483 goto err;
6484
6485 for (tc = 0; tc < ha->num_tc; tc++) {
6486 rc = qlnx_alloc_mem_txq(ha, fp, fp->txq[tc]);
6487 if (rc)
6488 goto err;
6489 }
6490
6491 return 0;
6492
6493 err:
6494 qlnx_free_mem_fp(ha, fp);
6495 return -ENOMEM;
6496 }
6497
6498 static void
qlnx_free_mem_load(qlnx_host_t * ha)6499 qlnx_free_mem_load(qlnx_host_t *ha)
6500 {
6501 int i;
6502 struct ecore_dev *cdev;
6503
6504 cdev = &ha->cdev;
6505
6506 for (i = 0; i < ha->num_rss; i++) {
6507 struct qlnx_fastpath *fp = &ha->fp_array[i];
6508
6509 qlnx_free_mem_fp(ha, fp);
6510 }
6511 return;
6512 }
6513
6514 static int
qlnx_alloc_mem_load(qlnx_host_t * ha)6515 qlnx_alloc_mem_load(qlnx_host_t *ha)
6516 {
6517 int rc = 0, rss_id;
6518
6519 for (rss_id = 0; rss_id < ha->num_rss; rss_id++) {
6520 struct qlnx_fastpath *fp = &ha->fp_array[rss_id];
6521
6522 rc = qlnx_alloc_mem_fp(ha, fp);
6523 if (rc)
6524 break;
6525 }
6526 return (rc);
6527 }
6528
6529 static int
qlnx_start_vport(struct ecore_dev * cdev,u8 vport_id,u16 mtu,u8 drop_ttl0_flg,u8 inner_vlan_removal_en_flg,u8 tx_switching,u8 hw_lro_enable)6530 qlnx_start_vport(struct ecore_dev *cdev,
6531 u8 vport_id,
6532 u16 mtu,
6533 u8 drop_ttl0_flg,
6534 u8 inner_vlan_removal_en_flg,
6535 u8 tx_switching,
6536 u8 hw_lro_enable)
6537 {
6538 int rc, i;
6539 struct ecore_sp_vport_start_params vport_start_params = { 0 };
6540 qlnx_host_t *ha;
6541
6542 ha = (qlnx_host_t *)cdev;
6543
6544 vport_start_params.remove_inner_vlan = inner_vlan_removal_en_flg;
6545 vport_start_params.tx_switching = 0;
6546 vport_start_params.handle_ptp_pkts = 0;
6547 vport_start_params.only_untagged = 0;
6548 vport_start_params.drop_ttl0 = drop_ttl0_flg;
6549
6550 vport_start_params.tpa_mode =
6551 (hw_lro_enable ? ECORE_TPA_MODE_RSC : ECORE_TPA_MODE_NONE);
6552 vport_start_params.max_buffers_per_cqe = QLNX_TPA_MAX_AGG_BUFFERS;
6553
6554 vport_start_params.vport_id = vport_id;
6555 vport_start_params.mtu = mtu;
6556
6557 QL_DPRINT2(ha, "Setting mtu to %d and VPORT ID = %d\n", mtu, vport_id);
6558
6559 for_each_hwfn(cdev, i) {
6560 struct ecore_hwfn *p_hwfn = &cdev->hwfns[i];
6561
6562 vport_start_params.concrete_fid = p_hwfn->hw_info.concrete_fid;
6563 vport_start_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
6564
6565 rc = ecore_sp_vport_start(p_hwfn, &vport_start_params);
6566
6567 if (rc) {
6568 QL_DPRINT1(ha, "Failed to start VPORT V-PORT %d"
6569 " with MTU %d\n" , vport_id, mtu);
6570 return -ENOMEM;
6571 }
6572
6573 ecore_hw_start_fastpath(p_hwfn);
6574
6575 QL_DPRINT2(ha, "Started V-PORT %d with MTU %d\n",
6576 vport_id, mtu);
6577 }
6578 return 0;
6579 }
6580
6581 static int
qlnx_update_vport(struct ecore_dev * cdev,struct qlnx_update_vport_params * params)6582 qlnx_update_vport(struct ecore_dev *cdev,
6583 struct qlnx_update_vport_params *params)
6584 {
6585 struct ecore_sp_vport_update_params sp_params;
6586 int rc, i, j, fp_index;
6587 struct ecore_hwfn *p_hwfn;
6588 struct ecore_rss_params *rss;
6589 qlnx_host_t *ha = (qlnx_host_t *)cdev;
6590 struct qlnx_fastpath *fp;
6591
6592 memset(&sp_params, 0, sizeof(sp_params));
6593 /* Translate protocol params into sp params */
6594 sp_params.vport_id = params->vport_id;
6595
6596 sp_params.update_vport_active_rx_flg =
6597 params->update_vport_active_rx_flg;
6598 sp_params.vport_active_rx_flg = params->vport_active_rx_flg;
6599
6600 sp_params.update_vport_active_tx_flg =
6601 params->update_vport_active_tx_flg;
6602 sp_params.vport_active_tx_flg = params->vport_active_tx_flg;
6603
6604 sp_params.update_inner_vlan_removal_flg =
6605 params->update_inner_vlan_removal_flg;
6606 sp_params.inner_vlan_removal_flg = params->inner_vlan_removal_flg;
6607
6608 sp_params.sge_tpa_params = params->sge_tpa_params;
6609
6610 /* RSS - is a bit tricky, since upper-layer isn't familiar with hwfns.
6611 * We need to re-fix the rss values per engine for CMT.
6612 */
6613 if (params->rss_params->update_rss_config)
6614 sp_params.rss_params = params->rss_params;
6615 else
6616 sp_params.rss_params = NULL;
6617
6618 for_each_hwfn(cdev, i) {
6619 p_hwfn = &cdev->hwfns[i];
6620
6621 if ((cdev->num_hwfns > 1) &&
6622 params->rss_params->update_rss_config &&
6623 params->rss_params->rss_enable) {
6624 rss = params->rss_params;
6625
6626 for (j = 0; j < ECORE_RSS_IND_TABLE_SIZE; j++) {
6627 fp_index = ((cdev->num_hwfns * j) + i) %
6628 ha->num_rss;
6629
6630 fp = &ha->fp_array[fp_index];
6631 rss->rss_ind_table[j] = fp->rxq->handle;
6632 }
6633
6634 for (j = 0; j < ECORE_RSS_IND_TABLE_SIZE;) {
6635 QL_DPRINT3(ha, "%p %p %p %p %p %p %p %p \n",
6636 rss->rss_ind_table[j],
6637 rss->rss_ind_table[j+1],
6638 rss->rss_ind_table[j+2],
6639 rss->rss_ind_table[j+3],
6640 rss->rss_ind_table[j+4],
6641 rss->rss_ind_table[j+5],
6642 rss->rss_ind_table[j+6],
6643 rss->rss_ind_table[j+7]);
6644 j += 8;
6645 }
6646 }
6647
6648 sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
6649
6650 QL_DPRINT1(ha, "Update sp vport ID=%d\n", params->vport_id);
6651
6652 rc = ecore_sp_vport_update(p_hwfn, &sp_params,
6653 ECORE_SPQ_MODE_EBLOCK, NULL);
6654 if (rc) {
6655 QL_DPRINT1(ha, "Failed to update VPORT\n");
6656 return rc;
6657 }
6658
6659 QL_DPRINT2(ha, "Updated V-PORT %d: tx_active_flag %d, \
6660 rx_active_flag %d [tx_update %d], [rx_update %d]\n",
6661 params->vport_id, params->vport_active_tx_flg,
6662 params->vport_active_rx_flg,
6663 params->update_vport_active_tx_flg,
6664 params->update_vport_active_rx_flg);
6665 }
6666
6667 return 0;
6668 }
6669
6670 static void
qlnx_reuse_rx_data(struct qlnx_rx_queue * rxq)6671 qlnx_reuse_rx_data(struct qlnx_rx_queue *rxq)
6672 {
6673 struct eth_rx_bd *rx_bd_cons =
6674 ecore_chain_consume(&rxq->rx_bd_ring);
6675 struct eth_rx_bd *rx_bd_prod =
6676 ecore_chain_produce(&rxq->rx_bd_ring);
6677 struct sw_rx_data *sw_rx_data_cons =
6678 &rxq->sw_rx_ring[rxq->sw_rx_cons];
6679 struct sw_rx_data *sw_rx_data_prod =
6680 &rxq->sw_rx_ring[rxq->sw_rx_prod];
6681
6682 sw_rx_data_prod->data = sw_rx_data_cons->data;
6683 memcpy(rx_bd_prod, rx_bd_cons, sizeof(struct eth_rx_bd));
6684
6685 rxq->sw_rx_cons = (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
6686 rxq->sw_rx_prod = (rxq->sw_rx_prod + 1) & (RX_RING_SIZE - 1);
6687
6688 return;
6689 }
6690
6691 static void
qlnx_update_rx_prod(struct ecore_hwfn * p_hwfn,struct qlnx_rx_queue * rxq)6692 qlnx_update_rx_prod(struct ecore_hwfn *p_hwfn, struct qlnx_rx_queue *rxq)
6693 {
6694
6695 uint16_t bd_prod;
6696 uint16_t cqe_prod;
6697 union {
6698 struct eth_rx_prod_data rx_prod_data;
6699 uint32_t data32;
6700 } rx_prods;
6701
6702 bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
6703 cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
6704
6705 /* Update producers */
6706 rx_prods.rx_prod_data.bd_prod = htole16(bd_prod);
6707 rx_prods.rx_prod_data.cqe_prod = htole16(cqe_prod);
6708
6709 /* Make sure that the BD and SGE data is updated before updating the
6710 * producers since FW might read the BD/SGE right after the producer
6711 * is updated.
6712 */
6713 wmb();
6714
6715 internal_ram_wr(p_hwfn, rxq->hw_rxq_prod_addr,
6716 sizeof(rx_prods), &rx_prods.data32);
6717
6718 /* mmiowb is needed to synchronize doorbell writes from more than one
6719 * processor. It guarantees that the write arrives to the device before
6720 * the napi lock is released and another qlnx_poll is called (possibly
6721 * on another CPU). Without this barrier, the next doorbell can bypass
6722 * this doorbell. This is applicable to IA64/Altix systems.
6723 */
6724 wmb();
6725
6726 return;
6727 }
6728
6729 static uint32_t qlnx_hash_key[] = {
6730 ((0x6d << 24)|(0x5a << 16)|(0x56 << 8)|0xda),
6731 ((0x25 << 24)|(0x5b << 16)|(0x0e << 8)|0xc2),
6732 ((0x41 << 24)|(0x67 << 16)|(0x25 << 8)|0x3d),
6733 ((0x43 << 24)|(0xa3 << 16)|(0x8f << 8)|0xb0),
6734 ((0xd0 << 24)|(0xca << 16)|(0x2b << 8)|0xcb),
6735 ((0xae << 24)|(0x7b << 16)|(0x30 << 8)|0xb4),
6736 ((0x77 << 24)|(0xcb << 16)|(0x2d << 8)|0xa3),
6737 ((0x80 << 24)|(0x30 << 16)|(0xf2 << 8)|0x0c),
6738 ((0x6a << 24)|(0x42 << 16)|(0xb7 << 8)|0x3b),
6739 ((0xbe << 24)|(0xac << 16)|(0x01 << 8)|0xfa)};
6740
6741 static int
qlnx_start_queues(qlnx_host_t * ha)6742 qlnx_start_queues(qlnx_host_t *ha)
6743 {
6744 int rc, tc, i, vport_id = 0,
6745 drop_ttl0_flg = 1, vlan_removal_en = 1,
6746 tx_switching = 0, hw_lro_enable = 0;
6747 struct ecore_dev *cdev = &ha->cdev;
6748 struct ecore_rss_params *rss_params = &ha->rss_params;
6749 struct qlnx_update_vport_params vport_update_params;
6750 struct ifnet *ifp;
6751 struct ecore_hwfn *p_hwfn;
6752 struct ecore_sge_tpa_params tpa_params;
6753 struct ecore_queue_start_common_params qparams;
6754 struct qlnx_fastpath *fp;
6755
6756 ifp = ha->ifp;
6757
6758 QL_DPRINT1(ha, "Num RSS = %d\n", ha->num_rss);
6759
6760 if (!ha->num_rss) {
6761 QL_DPRINT1(ha, "Cannot update V-VPORT as active as there"
6762 " are no Rx queues\n");
6763 return -EINVAL;
6764 }
6765
6766 #ifndef QLNX_SOFT_LRO
6767 hw_lro_enable = ifp->if_capenable & IFCAP_LRO;
6768 #endif /* #ifndef QLNX_SOFT_LRO */
6769
6770 rc = qlnx_start_vport(cdev, vport_id, ifp->if_mtu, drop_ttl0_flg,
6771 vlan_removal_en, tx_switching, hw_lro_enable);
6772
6773 if (rc) {
6774 QL_DPRINT1(ha, "Start V-PORT failed %d\n", rc);
6775 return rc;
6776 }
6777
6778 QL_DPRINT2(ha, "Start vport ramrod passed, "
6779 "vport_id = %d, MTU = %d, vlan_removal_en = %d\n",
6780 vport_id, (int)(ifp->if_mtu + 0xe), vlan_removal_en);
6781
6782 for_each_rss(i) {
6783 struct ecore_rxq_start_ret_params rx_ret_params;
6784 struct ecore_txq_start_ret_params tx_ret_params;
6785
6786 fp = &ha->fp_array[i];
6787 p_hwfn = &cdev->hwfns[(fp->rss_id % cdev->num_hwfns)];
6788
6789 bzero(&qparams, sizeof(struct ecore_queue_start_common_params));
6790 bzero(&rx_ret_params,
6791 sizeof (struct ecore_rxq_start_ret_params));
6792
6793 qparams.queue_id = i ;
6794 qparams.vport_id = vport_id;
6795 qparams.stats_id = vport_id;
6796 qparams.p_sb = fp->sb_info;
6797 qparams.sb_idx = RX_PI;
6798
6799
6800 rc = ecore_eth_rx_queue_start(p_hwfn,
6801 p_hwfn->hw_info.opaque_fid,
6802 &qparams,
6803 fp->rxq->rx_buf_size, /* bd_max_bytes */
6804 /* bd_chain_phys_addr */
6805 fp->rxq->rx_bd_ring.p_phys_addr,
6806 /* cqe_pbl_addr */
6807 ecore_chain_get_pbl_phys(&fp->rxq->rx_comp_ring),
6808 /* cqe_pbl_size */
6809 ecore_chain_get_page_cnt(&fp->rxq->rx_comp_ring),
6810 &rx_ret_params);
6811
6812 if (rc) {
6813 QL_DPRINT1(ha, "Start RXQ #%d failed %d\n", i, rc);
6814 return rc;
6815 }
6816
6817 fp->rxq->hw_rxq_prod_addr = rx_ret_params.p_prod;
6818 fp->rxq->handle = rx_ret_params.p_handle;
6819 fp->rxq->hw_cons_ptr =
6820 &fp->sb_info->sb_virt->pi_array[RX_PI];
6821
6822 qlnx_update_rx_prod(p_hwfn, fp->rxq);
6823
6824 for (tc = 0; tc < ha->num_tc; tc++) {
6825 struct qlnx_tx_queue *txq = fp->txq[tc];
6826
6827 bzero(&qparams,
6828 sizeof(struct ecore_queue_start_common_params));
6829 bzero(&tx_ret_params,
6830 sizeof (struct ecore_txq_start_ret_params));
6831
6832 qparams.queue_id = txq->index / cdev->num_hwfns ;
6833 qparams.vport_id = vport_id;
6834 qparams.stats_id = vport_id;
6835 qparams.p_sb = fp->sb_info;
6836 qparams.sb_idx = TX_PI(tc);
6837
6838 rc = ecore_eth_tx_queue_start(p_hwfn,
6839 p_hwfn->hw_info.opaque_fid,
6840 &qparams, tc,
6841 /* bd_chain_phys_addr */
6842 ecore_chain_get_pbl_phys(&txq->tx_pbl),
6843 ecore_chain_get_page_cnt(&txq->tx_pbl),
6844 &tx_ret_params);
6845
6846 if (rc) {
6847 QL_DPRINT1(ha, "Start TXQ #%d failed %d\n",
6848 txq->index, rc);
6849 return rc;
6850 }
6851
6852 txq->doorbell_addr = tx_ret_params.p_doorbell;
6853 txq->handle = tx_ret_params.p_handle;
6854
6855 txq->hw_cons_ptr =
6856 &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
6857 SET_FIELD(txq->tx_db.data.params,
6858 ETH_DB_DATA_DEST, DB_DEST_XCM);
6859 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
6860 DB_AGG_CMD_SET);
6861 SET_FIELD(txq->tx_db.data.params,
6862 ETH_DB_DATA_AGG_VAL_SEL,
6863 DQ_XCM_ETH_TX_BD_PROD_CMD);
6864
6865 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
6866 }
6867 }
6868
6869 /* Fill struct with RSS params */
6870 if (ha->num_rss > 1) {
6871 rss_params->update_rss_config = 1;
6872 rss_params->rss_enable = 1;
6873 rss_params->update_rss_capabilities = 1;
6874 rss_params->update_rss_ind_table = 1;
6875 rss_params->update_rss_key = 1;
6876 rss_params->rss_caps = ECORE_RSS_IPV4 | ECORE_RSS_IPV6 |
6877 ECORE_RSS_IPV4_TCP | ECORE_RSS_IPV6_TCP;
6878 rss_params->rss_table_size_log = 7; /* 2^7 = 128 */
6879
6880 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
6881 fp = &ha->fp_array[(i % ha->num_rss)];
6882 rss_params->rss_ind_table[i] = fp->rxq->handle;
6883 }
6884
6885 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
6886 rss_params->rss_key[i] = (__le32)qlnx_hash_key[i];
6887
6888 } else {
6889 memset(rss_params, 0, sizeof(*rss_params));
6890 }
6891
6892 /* Prepare and send the vport enable */
6893 memset(&vport_update_params, 0, sizeof(vport_update_params));
6894 vport_update_params.vport_id = vport_id;
6895 vport_update_params.update_vport_active_tx_flg = 1;
6896 vport_update_params.vport_active_tx_flg = 1;
6897 vport_update_params.update_vport_active_rx_flg = 1;
6898 vport_update_params.vport_active_rx_flg = 1;
6899 vport_update_params.rss_params = rss_params;
6900 vport_update_params.update_inner_vlan_removal_flg = 1;
6901 vport_update_params.inner_vlan_removal_flg = 1;
6902
6903 if (hw_lro_enable) {
6904 memset(&tpa_params, 0, sizeof (struct ecore_sge_tpa_params));
6905
6906 tpa_params.max_buffers_per_cqe = QLNX_TPA_MAX_AGG_BUFFERS;
6907
6908 tpa_params.update_tpa_en_flg = 1;
6909 tpa_params.tpa_ipv4_en_flg = 1;
6910 tpa_params.tpa_ipv6_en_flg = 1;
6911
6912 tpa_params.update_tpa_param_flg = 1;
6913 tpa_params.tpa_pkt_split_flg = 0;
6914 tpa_params.tpa_hdr_data_split_flg = 0;
6915 tpa_params.tpa_gro_consistent_flg = 0;
6916 tpa_params.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
6917 tpa_params.tpa_max_size = (uint16_t)(-1);
6918 tpa_params.tpa_min_size_to_start = ifp->if_mtu/2;
6919 tpa_params.tpa_min_size_to_cont = ifp->if_mtu/2;
6920
6921 vport_update_params.sge_tpa_params = &tpa_params;
6922 }
6923
6924 rc = qlnx_update_vport(cdev, &vport_update_params);
6925 if (rc) {
6926 QL_DPRINT1(ha, "Update V-PORT failed %d\n", rc);
6927 return rc;
6928 }
6929
6930 return 0;
6931 }
6932
6933 static int
qlnx_drain_txq(qlnx_host_t * ha,struct qlnx_fastpath * fp,struct qlnx_tx_queue * txq)6934 qlnx_drain_txq(qlnx_host_t *ha, struct qlnx_fastpath *fp,
6935 struct qlnx_tx_queue *txq)
6936 {
6937 uint16_t hw_bd_cons;
6938 uint16_t ecore_cons_idx;
6939
6940 QL_DPRINT2(ha, "enter\n");
6941
6942 hw_bd_cons = le16toh(*txq->hw_cons_ptr);
6943
6944 while (hw_bd_cons !=
6945 (ecore_cons_idx = ecore_chain_get_cons_idx(&txq->tx_pbl))) {
6946 mtx_lock(&fp->tx_mtx);
6947
6948 (void)qlnx_tx_int(ha, fp, txq);
6949
6950 mtx_unlock(&fp->tx_mtx);
6951
6952 qlnx_mdelay(__func__, 2);
6953
6954 hw_bd_cons = le16toh(*txq->hw_cons_ptr);
6955 }
6956
6957 QL_DPRINT2(ha, "[%d, %d]: done\n", fp->rss_id, txq->index);
6958
6959 return 0;
6960 }
6961
6962 static int
qlnx_stop_queues(qlnx_host_t * ha)6963 qlnx_stop_queues(qlnx_host_t *ha)
6964 {
6965 struct qlnx_update_vport_params vport_update_params;
6966 struct ecore_dev *cdev;
6967 struct qlnx_fastpath *fp;
6968 int rc, tc, i;
6969
6970 cdev = &ha->cdev;
6971
6972 /* Disable the vport */
6973
6974 memset(&vport_update_params, 0, sizeof(vport_update_params));
6975
6976 vport_update_params.vport_id = 0;
6977 vport_update_params.update_vport_active_tx_flg = 1;
6978 vport_update_params.vport_active_tx_flg = 0;
6979 vport_update_params.update_vport_active_rx_flg = 1;
6980 vport_update_params.vport_active_rx_flg = 0;
6981 vport_update_params.rss_params = &ha->rss_params;
6982 vport_update_params.rss_params->update_rss_config = 0;
6983 vport_update_params.rss_params->rss_enable = 0;
6984 vport_update_params.update_inner_vlan_removal_flg = 0;
6985 vport_update_params.inner_vlan_removal_flg = 0;
6986
6987 QL_DPRINT1(ha, "Update vport ID= %d\n", vport_update_params.vport_id);
6988
6989 rc = qlnx_update_vport(cdev, &vport_update_params);
6990 if (rc) {
6991 QL_DPRINT1(ha, "Failed to update vport\n");
6992 return rc;
6993 }
6994
6995 /* Flush Tx queues. If needed, request drain from MCP */
6996 for_each_rss(i) {
6997 fp = &ha->fp_array[i];
6998
6999 for (tc = 0; tc < ha->num_tc; tc++) {
7000 struct qlnx_tx_queue *txq = fp->txq[tc];
7001
7002 rc = qlnx_drain_txq(ha, fp, txq);
7003 if (rc)
7004 return rc;
7005 }
7006 }
7007
7008 /* Stop all Queues in reverse order*/
7009 for (i = ha->num_rss - 1; i >= 0; i--) {
7010 struct ecore_hwfn *p_hwfn = &cdev->hwfns[(i % cdev->num_hwfns)];
7011
7012 fp = &ha->fp_array[i];
7013
7014 /* Stop the Tx Queue(s)*/
7015 for (tc = 0; tc < ha->num_tc; tc++) {
7016 int tx_queue_id;
7017
7018 tx_queue_id = tc * ha->num_rss + i;
7019 rc = ecore_eth_tx_queue_stop(p_hwfn,
7020 fp->txq[tc]->handle);
7021
7022 if (rc) {
7023 QL_DPRINT1(ha, "Failed to stop TXQ #%d\n",
7024 tx_queue_id);
7025 return rc;
7026 }
7027 }
7028
7029 /* Stop the Rx Queue*/
7030 rc = ecore_eth_rx_queue_stop(p_hwfn, fp->rxq->handle, false,
7031 false);
7032 if (rc) {
7033 QL_DPRINT1(ha, "Failed to stop RXQ #%d\n", i);
7034 return rc;
7035 }
7036 }
7037
7038 /* Stop the vport */
7039 for_each_hwfn(cdev, i) {
7040 struct ecore_hwfn *p_hwfn = &cdev->hwfns[i];
7041
7042 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid, 0);
7043
7044 if (rc) {
7045 QL_DPRINT1(ha, "Failed to stop VPORT\n");
7046 return rc;
7047 }
7048 }
7049
7050 return rc;
7051 }
7052
7053 static int
qlnx_set_ucast_rx_mac(qlnx_host_t * ha,enum ecore_filter_opcode opcode,unsigned char mac[ETH_ALEN])7054 qlnx_set_ucast_rx_mac(qlnx_host_t *ha,
7055 enum ecore_filter_opcode opcode,
7056 unsigned char mac[ETH_ALEN])
7057 {
7058 struct ecore_filter_ucast ucast;
7059 struct ecore_dev *cdev;
7060 int rc;
7061
7062 cdev = &ha->cdev;
7063
7064 bzero(&ucast, sizeof(struct ecore_filter_ucast));
7065
7066 ucast.opcode = opcode;
7067 ucast.type = ECORE_FILTER_MAC;
7068 ucast.is_rx_filter = 1;
7069 ucast.vport_to_add_to = 0;
7070 memcpy(&ucast.mac[0], mac, ETH_ALEN);
7071
7072 rc = ecore_filter_ucast_cmd(cdev, &ucast, ECORE_SPQ_MODE_CB, NULL);
7073
7074 return (rc);
7075 }
7076
7077 static int
qlnx_remove_all_ucast_mac(qlnx_host_t * ha)7078 qlnx_remove_all_ucast_mac(qlnx_host_t *ha)
7079 {
7080 struct ecore_filter_ucast ucast;
7081 struct ecore_dev *cdev;
7082 int rc;
7083
7084 bzero(&ucast, sizeof(struct ecore_filter_ucast));
7085
7086 ucast.opcode = ECORE_FILTER_REPLACE;
7087 ucast.type = ECORE_FILTER_MAC;
7088 ucast.is_rx_filter = 1;
7089
7090 cdev = &ha->cdev;
7091
7092 rc = ecore_filter_ucast_cmd(cdev, &ucast, ECORE_SPQ_MODE_CB, NULL);
7093
7094 return (rc);
7095 }
7096
7097 static int
qlnx_remove_all_mcast_mac(qlnx_host_t * ha)7098 qlnx_remove_all_mcast_mac(qlnx_host_t *ha)
7099 {
7100 struct ecore_filter_mcast *mcast;
7101 struct ecore_dev *cdev;
7102 int rc, i;
7103
7104 cdev = &ha->cdev;
7105
7106 mcast = &ha->ecore_mcast;
7107 bzero(mcast, sizeof(struct ecore_filter_mcast));
7108
7109 mcast->opcode = ECORE_FILTER_REMOVE;
7110
7111 for (i = 0; i < QLNX_MAX_NUM_MULTICAST_ADDRS; i++) {
7112 if (ha->mcast[i].addr[0] || ha->mcast[i].addr[1] ||
7113 ha->mcast[i].addr[2] || ha->mcast[i].addr[3] ||
7114 ha->mcast[i].addr[4] || ha->mcast[i].addr[5]) {
7115 memcpy(&mcast->mac[i][0], &ha->mcast[i].addr[0], ETH_ALEN);
7116 mcast->num_mc_addrs++;
7117 }
7118 }
7119 mcast = &ha->ecore_mcast;
7120
7121 rc = ecore_filter_mcast_cmd(cdev, mcast, ECORE_SPQ_MODE_CB, NULL);
7122
7123 bzero(ha->mcast, (sizeof(qlnx_mcast_t) * QLNX_MAX_NUM_MULTICAST_ADDRS));
7124 ha->nmcast = 0;
7125
7126 return (rc);
7127 }
7128
7129 static int
qlnx_clean_filters(qlnx_host_t * ha)7130 qlnx_clean_filters(qlnx_host_t *ha)
7131 {
7132 int rc = 0;
7133
7134 /* Remove all unicast macs */
7135 rc = qlnx_remove_all_ucast_mac(ha);
7136 if (rc)
7137 return rc;
7138
7139 /* Remove all multicast macs */
7140 rc = qlnx_remove_all_mcast_mac(ha);
7141 if (rc)
7142 return rc;
7143
7144 rc = qlnx_set_ucast_rx_mac(ha, ECORE_FILTER_FLUSH, ha->primary_mac);
7145
7146 return (rc);
7147 }
7148
7149 static int
qlnx_set_rx_accept_filter(qlnx_host_t * ha,uint8_t filter)7150 qlnx_set_rx_accept_filter(qlnx_host_t *ha, uint8_t filter)
7151 {
7152 struct ecore_filter_accept_flags accept;
7153 int rc = 0;
7154 struct ecore_dev *cdev;
7155
7156 cdev = &ha->cdev;
7157
7158 bzero(&accept, sizeof(struct ecore_filter_accept_flags));
7159
7160 accept.update_rx_mode_config = 1;
7161 accept.rx_accept_filter = filter;
7162
7163 accept.update_tx_mode_config = 1;
7164 accept.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
7165 ECORE_ACCEPT_MCAST_MATCHED | ECORE_ACCEPT_BCAST;
7166
7167 rc = ecore_filter_accept_cmd(cdev, 0, accept, false, false,
7168 ECORE_SPQ_MODE_CB, NULL);
7169
7170 return (rc);
7171 }
7172
7173 static int
qlnx_set_rx_mode(qlnx_host_t * ha)7174 qlnx_set_rx_mode(qlnx_host_t *ha)
7175 {
7176 int rc = 0;
7177 uint8_t filter;
7178 const struct ifnet *ifp = ha->ifp;
7179 struct sockaddr_dl *sdl;
7180
7181 if (ifp->if_type == IFT_ETHER && ifp->if_addr != NULL &&
7182 ifp->if_addr->ifa_addr != NULL) {
7183 sdl = (struct sockaddr_dl *) ifp->if_addr->ifa_addr;
7184
7185 rc = qlnx_set_ucast_rx_mac(ha, ECORE_FILTER_REPLACE, LLADDR(sdl));
7186 } else {
7187 rc = qlnx_set_ucast_rx_mac(ha, ECORE_FILTER_REPLACE, ha->primary_mac);
7188 }
7189 if (rc)
7190 return rc;
7191
7192 rc = qlnx_remove_all_mcast_mac(ha);
7193 if (rc)
7194 return rc;
7195
7196 filter = ECORE_ACCEPT_UCAST_MATCHED |
7197 ECORE_ACCEPT_MCAST_MATCHED |
7198 ECORE_ACCEPT_BCAST;
7199
7200 if (qlnx_vf_device(ha) == 0) {
7201 filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
7202 filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
7203 }
7204 ha->filter = filter;
7205
7206 rc = qlnx_set_rx_accept_filter(ha, filter);
7207
7208 return (rc);
7209 }
7210
7211 static int
qlnx_set_link(qlnx_host_t * ha,bool link_up)7212 qlnx_set_link(qlnx_host_t *ha, bool link_up)
7213 {
7214 int i, rc = 0;
7215 struct ecore_dev *cdev;
7216 struct ecore_hwfn *hwfn;
7217 struct ecore_ptt *ptt;
7218
7219 if (qlnx_vf_device(ha) == 0)
7220 return (0);
7221
7222 cdev = &ha->cdev;
7223
7224 for_each_hwfn(cdev, i) {
7225 hwfn = &cdev->hwfns[i];
7226
7227 ptt = ecore_ptt_acquire(hwfn);
7228 if (!ptt)
7229 return -EBUSY;
7230
7231 rc = ecore_mcp_set_link(hwfn, ptt, link_up);
7232
7233 ecore_ptt_release(hwfn, ptt);
7234
7235 if (rc)
7236 return rc;
7237 }
7238 return (rc);
7239 }
7240
7241 #if __FreeBSD_version >= 1100000
7242 static uint64_t
qlnx_get_counter(if_t ifp,ift_counter cnt)7243 qlnx_get_counter(if_t ifp, ift_counter cnt)
7244 {
7245 qlnx_host_t *ha;
7246 uint64_t count;
7247
7248 ha = (qlnx_host_t *)if_getsoftc(ifp);
7249
7250 switch (cnt) {
7251 case IFCOUNTER_IPACKETS:
7252 count = ha->hw_stats.common.rx_ucast_pkts +
7253 ha->hw_stats.common.rx_mcast_pkts +
7254 ha->hw_stats.common.rx_bcast_pkts;
7255 break;
7256
7257 case IFCOUNTER_IERRORS:
7258 count = ha->hw_stats.common.rx_crc_errors +
7259 ha->hw_stats.common.rx_align_errors +
7260 ha->hw_stats.common.rx_oversize_packets +
7261 ha->hw_stats.common.rx_undersize_packets;
7262 break;
7263
7264 case IFCOUNTER_OPACKETS:
7265 count = ha->hw_stats.common.tx_ucast_pkts +
7266 ha->hw_stats.common.tx_mcast_pkts +
7267 ha->hw_stats.common.tx_bcast_pkts;
7268 break;
7269
7270 case IFCOUNTER_OERRORS:
7271 count = ha->hw_stats.common.tx_err_drop_pkts;
7272 break;
7273
7274 case IFCOUNTER_COLLISIONS:
7275 return (0);
7276
7277 case IFCOUNTER_IBYTES:
7278 count = ha->hw_stats.common.rx_ucast_bytes +
7279 ha->hw_stats.common.rx_mcast_bytes +
7280 ha->hw_stats.common.rx_bcast_bytes;
7281 break;
7282
7283 case IFCOUNTER_OBYTES:
7284 count = ha->hw_stats.common.tx_ucast_bytes +
7285 ha->hw_stats.common.tx_mcast_bytes +
7286 ha->hw_stats.common.tx_bcast_bytes;
7287 break;
7288
7289 case IFCOUNTER_IMCASTS:
7290 count = ha->hw_stats.common.rx_mcast_bytes;
7291 break;
7292
7293 case IFCOUNTER_OMCASTS:
7294 count = ha->hw_stats.common.tx_mcast_bytes;
7295 break;
7296
7297 case IFCOUNTER_IQDROPS:
7298 case IFCOUNTER_OQDROPS:
7299 case IFCOUNTER_NOPROTO:
7300
7301 default:
7302 return (if_get_counter_default(ifp, cnt));
7303 }
7304 return (count);
7305 }
7306 #endif
7307
7308 static void
qlnx_timer(void * arg)7309 qlnx_timer(void *arg)
7310 {
7311 qlnx_host_t *ha;
7312
7313 ha = (qlnx_host_t *)arg;
7314
7315 if (ha->error_recovery) {
7316 ha->error_recovery = 0;
7317 taskqueue_enqueue(ha->err_taskqueue, &ha->err_task);
7318 return;
7319 }
7320
7321 ecore_get_vport_stats(&ha->cdev, &ha->hw_stats);
7322
7323 if (ha->storm_stats_gather)
7324 qlnx_sample_storm_stats(ha);
7325
7326 callout_reset(&ha->qlnx_callout, hz, qlnx_timer, ha);
7327
7328 return;
7329 }
7330
7331 static int
qlnx_load(qlnx_host_t * ha)7332 qlnx_load(qlnx_host_t *ha)
7333 {
7334 int i;
7335 int rc = 0;
7336 struct ecore_dev *cdev;
7337 device_t dev;
7338
7339 cdev = &ha->cdev;
7340 dev = ha->pci_dev;
7341
7342 QL_DPRINT2(ha, "enter\n");
7343
7344 rc = qlnx_alloc_mem_arrays(ha);
7345 if (rc)
7346 goto qlnx_load_exit0;
7347
7348 qlnx_init_fp(ha);
7349
7350 rc = qlnx_alloc_mem_load(ha);
7351 if (rc)
7352 goto qlnx_load_exit1;
7353
7354 QL_DPRINT2(ha, "Allocated %d RSS queues on %d TC/s\n",
7355 ha->num_rss, ha->num_tc);
7356
7357 for (i = 0; i < ha->num_rss; i++) {
7358 if ((rc = bus_setup_intr(dev, ha->irq_vec[i].irq,
7359 (INTR_TYPE_NET | INTR_MPSAFE),
7360 NULL, qlnx_fp_isr, &ha->irq_vec[i],
7361 &ha->irq_vec[i].handle))) {
7362 QL_DPRINT1(ha, "could not setup interrupt\n");
7363 goto qlnx_load_exit2;
7364 }
7365
7366 QL_DPRINT2(ha, "rss_id = %d irq_rid %d \
7367 irq %p handle %p\n", i,
7368 ha->irq_vec[i].irq_rid,
7369 ha->irq_vec[i].irq, ha->irq_vec[i].handle);
7370
7371 bus_bind_intr(dev, ha->irq_vec[i].irq, (i % mp_ncpus));
7372 }
7373
7374 rc = qlnx_start_queues(ha);
7375 if (rc)
7376 goto qlnx_load_exit2;
7377
7378 QL_DPRINT2(ha, "Start VPORT, RXQ and TXQ succeeded\n");
7379
7380 /* Add primary mac and set Rx filters */
7381 rc = qlnx_set_rx_mode(ha);
7382 if (rc)
7383 goto qlnx_load_exit2;
7384
7385 /* Ask for link-up using current configuration */
7386 qlnx_set_link(ha, true);
7387
7388 if (qlnx_vf_device(ha) == 0)
7389 qlnx_link_update(&ha->cdev.hwfns[0]);
7390
7391 ha->state = QLNX_STATE_OPEN;
7392
7393 bzero(&ha->hw_stats, sizeof(struct ecore_eth_stats));
7394
7395 if (ha->flags.callout_init)
7396 callout_reset(&ha->qlnx_callout, hz, qlnx_timer, ha);
7397
7398 goto qlnx_load_exit0;
7399
7400 qlnx_load_exit2:
7401 qlnx_free_mem_load(ha);
7402
7403 qlnx_load_exit1:
7404 ha->num_rss = 0;
7405
7406 qlnx_load_exit0:
7407 QL_DPRINT2(ha, "exit [%d]\n", rc);
7408 return rc;
7409 }
7410
7411 static void
qlnx_drain_soft_lro(qlnx_host_t * ha)7412 qlnx_drain_soft_lro(qlnx_host_t *ha)
7413 {
7414 #ifdef QLNX_SOFT_LRO
7415
7416 struct ifnet *ifp;
7417 int i;
7418
7419 ifp = ha->ifp;
7420
7421 if (ifp->if_capenable & IFCAP_LRO) {
7422 for (i = 0; i < ha->num_rss; i++) {
7423 struct qlnx_fastpath *fp = &ha->fp_array[i];
7424 struct lro_ctrl *lro;
7425
7426 lro = &fp->rxq->lro;
7427
7428 #if (__FreeBSD_version >= 1100101) || (defined QLNX_QSORT_LRO)
7429
7430 tcp_lro_flush_all(lro);
7431
7432 #else
7433 struct lro_entry *queued;
7434
7435 while ((!SLIST_EMPTY(&lro->lro_active))){
7436 queued = SLIST_FIRST(&lro->lro_active);
7437 SLIST_REMOVE_HEAD(&lro->lro_active, next);
7438 tcp_lro_flush(lro, queued);
7439 }
7440
7441 #endif /* #if (__FreeBSD_version >= 1100101) || (defined QLNX_QSORT_LRO) */
7442 }
7443 }
7444
7445 #endif /* #ifdef QLNX_SOFT_LRO */
7446
7447 return;
7448 }
7449
7450 static void
qlnx_unload(qlnx_host_t * ha)7451 qlnx_unload(qlnx_host_t *ha)
7452 {
7453 struct ecore_dev *cdev;
7454 device_t dev;
7455 int i;
7456
7457 cdev = &ha->cdev;
7458 dev = ha->pci_dev;
7459
7460 QL_DPRINT2(ha, "enter\n");
7461 QL_DPRINT1(ha, " QLNX STATE = %d\n",ha->state);
7462
7463 if (ha->state == QLNX_STATE_OPEN) {
7464 qlnx_set_link(ha, false);
7465 qlnx_clean_filters(ha);
7466 qlnx_stop_queues(ha);
7467 ecore_hw_stop_fastpath(cdev);
7468
7469 for (i = 0; i < ha->num_rss; i++) {
7470 if (ha->irq_vec[i].handle) {
7471 (void)bus_teardown_intr(dev,
7472 ha->irq_vec[i].irq,
7473 ha->irq_vec[i].handle);
7474 ha->irq_vec[i].handle = NULL;
7475 }
7476 }
7477
7478 qlnx_drain_fp_taskqueues(ha);
7479 qlnx_drain_soft_lro(ha);
7480 qlnx_free_mem_load(ha);
7481 }
7482
7483 if (ha->flags.callout_init)
7484 callout_drain(&ha->qlnx_callout);
7485
7486 qlnx_mdelay(__func__, 1000);
7487
7488 ha->state = QLNX_STATE_CLOSED;
7489
7490 QL_DPRINT2(ha, "exit\n");
7491 return;
7492 }
7493
7494 static int
qlnx_grc_dumpsize(qlnx_host_t * ha,uint32_t * num_dwords,int hwfn_index)7495 qlnx_grc_dumpsize(qlnx_host_t *ha, uint32_t *num_dwords, int hwfn_index)
7496 {
7497 int rval = -1;
7498 struct ecore_hwfn *p_hwfn;
7499 struct ecore_ptt *p_ptt;
7500
7501 ecore_dbg_set_app_ver(ecore_dbg_get_fw_func_ver());
7502
7503 p_hwfn = &ha->cdev.hwfns[hwfn_index];
7504 p_ptt = ecore_ptt_acquire(p_hwfn);
7505
7506 if (!p_ptt) {
7507 QL_DPRINT1(ha, "ecore_ptt_acquire failed\n");
7508 return (rval);
7509 }
7510
7511 rval = ecore_dbg_grc_get_dump_buf_size(p_hwfn, p_ptt, num_dwords);
7512
7513 if (rval == DBG_STATUS_OK)
7514 rval = 0;
7515 else {
7516 QL_DPRINT1(ha, "ecore_dbg_grc_get_dump_buf_size failed"
7517 "[0x%x]\n", rval);
7518 }
7519
7520 ecore_ptt_release(p_hwfn, p_ptt);
7521
7522 return (rval);
7523 }
7524
7525 static int
qlnx_idle_chk_size(qlnx_host_t * ha,uint32_t * num_dwords,int hwfn_index)7526 qlnx_idle_chk_size(qlnx_host_t *ha, uint32_t *num_dwords, int hwfn_index)
7527 {
7528 int rval = -1;
7529 struct ecore_hwfn *p_hwfn;
7530 struct ecore_ptt *p_ptt;
7531
7532 ecore_dbg_set_app_ver(ecore_dbg_get_fw_func_ver());
7533
7534 p_hwfn = &ha->cdev.hwfns[hwfn_index];
7535 p_ptt = ecore_ptt_acquire(p_hwfn);
7536
7537 if (!p_ptt) {
7538 QL_DPRINT1(ha, "ecore_ptt_acquire failed\n");
7539 return (rval);
7540 }
7541
7542 rval = ecore_dbg_idle_chk_get_dump_buf_size(p_hwfn, p_ptt, num_dwords);
7543
7544 if (rval == DBG_STATUS_OK)
7545 rval = 0;
7546 else {
7547 QL_DPRINT1(ha, "ecore_dbg_idle_chk_get_dump_buf_size failed"
7548 " [0x%x]\n", rval);
7549 }
7550
7551 ecore_ptt_release(p_hwfn, p_ptt);
7552
7553 return (rval);
7554 }
7555
7556 static void
qlnx_sample_storm_stats(qlnx_host_t * ha)7557 qlnx_sample_storm_stats(qlnx_host_t *ha)
7558 {
7559 int i, index;
7560 struct ecore_dev *cdev;
7561 qlnx_storm_stats_t *s_stats;
7562 uint32_t reg;
7563 struct ecore_ptt *p_ptt;
7564 struct ecore_hwfn *hwfn;
7565
7566 if (ha->storm_stats_index >= QLNX_STORM_STATS_SAMPLES_PER_HWFN) {
7567 ha->storm_stats_gather = 0;
7568 return;
7569 }
7570
7571 cdev = &ha->cdev;
7572
7573 for_each_hwfn(cdev, i) {
7574 hwfn = &cdev->hwfns[i];
7575
7576 p_ptt = ecore_ptt_acquire(hwfn);
7577 if (!p_ptt)
7578 return;
7579
7580 index = ha->storm_stats_index +
7581 (i * QLNX_STORM_STATS_SAMPLES_PER_HWFN);
7582
7583 s_stats = &ha->storm_stats[index];
7584
7585 /* XSTORM */
7586 reg = XSEM_REG_FAST_MEMORY +
7587 SEM_FAST_REG_STORM_ACTIVE_CYCLES_BB_K2;
7588 s_stats->xstorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);
7589
7590 reg = XSEM_REG_FAST_MEMORY +
7591 SEM_FAST_REG_STORM_STALL_CYCLES_BB_K2;
7592 s_stats->xstorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);
7593
7594 reg = XSEM_REG_FAST_MEMORY +
7595 SEM_FAST_REG_IDLE_SLEEPING_CYCLES_BB_K2;
7596 s_stats->xstorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);
7597
7598 reg = XSEM_REG_FAST_MEMORY +
7599 SEM_FAST_REG_IDLE_INACTIVE_CYCLES_BB_K2;
7600 s_stats->xstorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);
7601
7602 /* YSTORM */
7603 reg = YSEM_REG_FAST_MEMORY +
7604 SEM_FAST_REG_STORM_ACTIVE_CYCLES_BB_K2;
7605 s_stats->ystorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);
7606
7607 reg = YSEM_REG_FAST_MEMORY +
7608 SEM_FAST_REG_STORM_STALL_CYCLES_BB_K2;
7609 s_stats->ystorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);
7610
7611 reg = YSEM_REG_FAST_MEMORY +
7612 SEM_FAST_REG_IDLE_SLEEPING_CYCLES_BB_K2;
7613 s_stats->ystorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);
7614
7615 reg = YSEM_REG_FAST_MEMORY +
7616 SEM_FAST_REG_IDLE_INACTIVE_CYCLES_BB_K2;
7617 s_stats->ystorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);
7618
7619 /* PSTORM */
7620 reg = PSEM_REG_FAST_MEMORY +
7621 SEM_FAST_REG_STORM_ACTIVE_CYCLES_BB_K2;
7622 s_stats->pstorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);
7623
7624 reg = PSEM_REG_FAST_MEMORY +
7625 SEM_FAST_REG_STORM_STALL_CYCLES_BB_K2;
7626 s_stats->pstorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);
7627
7628 reg = PSEM_REG_FAST_MEMORY +
7629 SEM_FAST_REG_IDLE_SLEEPING_CYCLES_BB_K2;
7630 s_stats->pstorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);
7631
7632 reg = PSEM_REG_FAST_MEMORY +
7633 SEM_FAST_REG_IDLE_INACTIVE_CYCLES_BB_K2;
7634 s_stats->pstorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);
7635
7636 /* TSTORM */
7637 reg = TSEM_REG_FAST_MEMORY +
7638 SEM_FAST_REG_STORM_ACTIVE_CYCLES_BB_K2;
7639 s_stats->tstorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);
7640
7641 reg = TSEM_REG_FAST_MEMORY +
7642 SEM_FAST_REG_STORM_STALL_CYCLES_BB_K2;
7643 s_stats->tstorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);
7644
7645 reg = TSEM_REG_FAST_MEMORY +
7646 SEM_FAST_REG_IDLE_SLEEPING_CYCLES_BB_K2;
7647 s_stats->tstorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);
7648
7649 reg = TSEM_REG_FAST_MEMORY +
7650 SEM_FAST_REG_IDLE_INACTIVE_CYCLES_BB_K2;
7651 s_stats->tstorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);
7652
7653 /* MSTORM */
7654 reg = MSEM_REG_FAST_MEMORY +
7655 SEM_FAST_REG_STORM_ACTIVE_CYCLES_BB_K2;
7656 s_stats->mstorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);
7657
7658 reg = MSEM_REG_FAST_MEMORY +
7659 SEM_FAST_REG_STORM_STALL_CYCLES_BB_K2;
7660 s_stats->mstorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);
7661
7662 reg = MSEM_REG_FAST_MEMORY +
7663 SEM_FAST_REG_IDLE_SLEEPING_CYCLES_BB_K2;
7664 s_stats->mstorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);
7665
7666 reg = MSEM_REG_FAST_MEMORY +
7667 SEM_FAST_REG_IDLE_INACTIVE_CYCLES_BB_K2;
7668 s_stats->mstorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);
7669
7670 /* USTORM */
7671 reg = USEM_REG_FAST_MEMORY +
7672 SEM_FAST_REG_STORM_ACTIVE_CYCLES_BB_K2;
7673 s_stats->ustorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);
7674
7675 reg = USEM_REG_FAST_MEMORY +
7676 SEM_FAST_REG_STORM_STALL_CYCLES_BB_K2;
7677 s_stats->ustorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);
7678
7679 reg = USEM_REG_FAST_MEMORY +
7680 SEM_FAST_REG_IDLE_SLEEPING_CYCLES_BB_K2;
7681 s_stats->ustorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);
7682
7683 reg = USEM_REG_FAST_MEMORY +
7684 SEM_FAST_REG_IDLE_INACTIVE_CYCLES_BB_K2;
7685 s_stats->ustorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);
7686
7687 ecore_ptt_release(hwfn, p_ptt);
7688 }
7689
7690 ha->storm_stats_index++;
7691
7692 return;
7693 }
7694
7695 /*
7696 * Name: qlnx_dump_buf8
7697 * Function: dumps a buffer as bytes
7698 */
7699 static void
qlnx_dump_buf8(qlnx_host_t * ha,const char * msg,void * dbuf,uint32_t len)7700 qlnx_dump_buf8(qlnx_host_t *ha, const char *msg, void *dbuf, uint32_t len)
7701 {
7702 device_t dev;
7703 uint32_t i = 0;
7704 uint8_t *buf;
7705
7706 dev = ha->pci_dev;
7707 buf = dbuf;
7708
7709 device_printf(dev, "%s: %s 0x%x dump start\n", __func__, msg, len);
7710
7711 while (len >= 16) {
7712 device_printf(dev,"0x%08x:"
7713 " %02x %02x %02x %02x %02x %02x %02x %02x"
7714 " %02x %02x %02x %02x %02x %02x %02x %02x\n", i,
7715 buf[0], buf[1], buf[2], buf[3],
7716 buf[4], buf[5], buf[6], buf[7],
7717 buf[8], buf[9], buf[10], buf[11],
7718 buf[12], buf[13], buf[14], buf[15]);
7719 i += 16;
7720 len -= 16;
7721 buf += 16;
7722 }
7723 switch (len) {
7724 case 1:
7725 device_printf(dev,"0x%08x: %02x\n", i, buf[0]);
7726 break;
7727 case 2:
7728 device_printf(dev,"0x%08x: %02x %02x\n", i, buf[0], buf[1]);
7729 break;
7730 case 3:
7731 device_printf(dev,"0x%08x: %02x %02x %02x\n",
7732 i, buf[0], buf[1], buf[2]);
7733 break;
7734 case 4:
7735 device_printf(dev,"0x%08x: %02x %02x %02x %02x\n", i,
7736 buf[0], buf[1], buf[2], buf[3]);
7737 break;
7738 case 5:
7739 device_printf(dev,"0x%08x:"
7740 " %02x %02x %02x %02x %02x\n", i,
7741 buf[0], buf[1], buf[2], buf[3], buf[4]);
7742 break;
7743 case 6:
7744 device_printf(dev,"0x%08x:"
7745 " %02x %02x %02x %02x %02x %02x\n", i,
7746 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
7747 break;
7748 case 7:
7749 device_printf(dev,"0x%08x:"
7750 " %02x %02x %02x %02x %02x %02x %02x\n", i,
7751 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]);
7752 break;
7753 case 8:
7754 device_printf(dev,"0x%08x:"
7755 " %02x %02x %02x %02x %02x %02x %02x %02x\n", i,
7756 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7757 buf[7]);
7758 break;
7759 case 9:
7760 device_printf(dev,"0x%08x:"
7761 " %02x %02x %02x %02x %02x %02x %02x %02x"
7762 " %02x\n", i,
7763 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7764 buf[7], buf[8]);
7765 break;
7766 case 10:
7767 device_printf(dev,"0x%08x:"
7768 " %02x %02x %02x %02x %02x %02x %02x %02x"
7769 " %02x %02x\n", i,
7770 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7771 buf[7], buf[8], buf[9]);
7772 break;
7773 case 11:
7774 device_printf(dev,"0x%08x:"
7775 " %02x %02x %02x %02x %02x %02x %02x %02x"
7776 " %02x %02x %02x\n", i,
7777 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7778 buf[7], buf[8], buf[9], buf[10]);
7779 break;
7780 case 12:
7781 device_printf(dev,"0x%08x:"
7782 " %02x %02x %02x %02x %02x %02x %02x %02x"
7783 " %02x %02x %02x %02x\n", i,
7784 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7785 buf[7], buf[8], buf[9], buf[10], buf[11]);
7786 break;
7787 case 13:
7788 device_printf(dev,"0x%08x:"
7789 " %02x %02x %02x %02x %02x %02x %02x %02x"
7790 " %02x %02x %02x %02x %02x\n", i,
7791 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7792 buf[7], buf[8], buf[9], buf[10], buf[11], buf[12]);
7793 break;
7794 case 14:
7795 device_printf(dev,"0x%08x:"
7796 " %02x %02x %02x %02x %02x %02x %02x %02x"
7797 " %02x %02x %02x %02x %02x %02x\n", i,
7798 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7799 buf[7], buf[8], buf[9], buf[10], buf[11], buf[12],
7800 buf[13]);
7801 break;
7802 case 15:
7803 device_printf(dev,"0x%08x:"
7804 " %02x %02x %02x %02x %02x %02x %02x %02x"
7805 " %02x %02x %02x %02x %02x %02x %02x\n", i,
7806 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7807 buf[7], buf[8], buf[9], buf[10], buf[11], buf[12],
7808 buf[13], buf[14]);
7809 break;
7810 default:
7811 break;
7812 }
7813
7814 device_printf(dev, "%s: %s dump end\n", __func__, msg);
7815
7816 return;
7817 }
7818
7819 #ifdef CONFIG_ECORE_SRIOV
7820
7821 static void
__qlnx_osal_iov_vf_cleanup(struct ecore_hwfn * p_hwfn,uint8_t rel_vf_id)7822 __qlnx_osal_iov_vf_cleanup(struct ecore_hwfn *p_hwfn, uint8_t rel_vf_id)
7823 {
7824 struct ecore_public_vf_info *vf_info;
7825
7826 vf_info = ecore_iov_get_public_vf_info(p_hwfn, rel_vf_id, false);
7827
7828 if (!vf_info)
7829 return;
7830
7831 /* Clear the VF mac */
7832 memset(vf_info->forced_mac, 0, ETH_ALEN);
7833
7834 vf_info->forced_vlan = 0;
7835
7836 return;
7837 }
7838
7839 void
qlnx_osal_iov_vf_cleanup(void * p_hwfn,uint8_t relative_vf_id)7840 qlnx_osal_iov_vf_cleanup(void *p_hwfn, uint8_t relative_vf_id)
7841 {
7842 __qlnx_osal_iov_vf_cleanup(p_hwfn, relative_vf_id);
7843 return;
7844 }
7845
7846 static int
__qlnx_iov_chk_ucast(struct ecore_hwfn * p_hwfn,int vfid,struct ecore_filter_ucast * params)7847 __qlnx_iov_chk_ucast(struct ecore_hwfn *p_hwfn, int vfid,
7848 struct ecore_filter_ucast *params)
7849 {
7850 struct ecore_public_vf_info *vf;
7851
7852 if (!ecore_iov_vf_has_vport_instance(p_hwfn, vfid)) {
7853 QL_DPRINT1(((qlnx_host_t *)p_hwfn->p_dev),
7854 "VF[%d] vport not initialized\n", vfid);
7855 return ECORE_INVAL;
7856 }
7857
7858 vf = ecore_iov_get_public_vf_info(p_hwfn, vfid, true);
7859 if (!vf)
7860 return -EINVAL;
7861
7862 /* No real decision to make; Store the configured MAC */
7863 if (params->type == ECORE_FILTER_MAC ||
7864 params->type == ECORE_FILTER_MAC_VLAN)
7865 memcpy(params->mac, vf->forced_mac, ETH_ALEN);
7866
7867 return 0;
7868 }
7869
7870 int
qlnx_iov_chk_ucast(void * p_hwfn,int vfid,void * params)7871 qlnx_iov_chk_ucast(void *p_hwfn, int vfid, void *params)
7872 {
7873 return (__qlnx_iov_chk_ucast(p_hwfn, vfid, params));
7874 }
7875
7876 static int
__qlnx_iov_update_vport(struct ecore_hwfn * hwfn,uint8_t vfid,struct ecore_sp_vport_update_params * params,uint16_t * tlvs)7877 __qlnx_iov_update_vport(struct ecore_hwfn *hwfn, uint8_t vfid,
7878 struct ecore_sp_vport_update_params *params, uint16_t * tlvs)
7879 {
7880 uint8_t mask;
7881 struct ecore_filter_accept_flags *flags;
7882
7883 if (!ecore_iov_vf_has_vport_instance(hwfn, vfid)) {
7884 QL_DPRINT1(((qlnx_host_t *)hwfn->p_dev),
7885 "VF[%d] vport not initialized\n", vfid);
7886 return ECORE_INVAL;
7887 }
7888
7889 /* Untrusted VFs can't even be trusted to know that fact.
7890 * Simply indicate everything is configured fine, and trace
7891 * configuration 'behind their back'.
7892 */
7893 mask = ECORE_ACCEPT_UCAST_UNMATCHED | ECORE_ACCEPT_MCAST_UNMATCHED;
7894 flags = ¶ms->accept_flags;
7895 if (!(*tlvs & BIT(ECORE_IOV_VP_UPDATE_ACCEPT_PARAM)))
7896 return 0;
7897
7898 return 0;
7899
7900 }
7901 int
qlnx_iov_update_vport(void * hwfn,uint8_t vfid,void * params,uint16_t * tlvs)7902 qlnx_iov_update_vport(void *hwfn, uint8_t vfid, void *params, uint16_t *tlvs)
7903 {
7904 return(__qlnx_iov_update_vport(hwfn, vfid, params, tlvs));
7905 }
7906
7907 static int
qlnx_find_hwfn_index(struct ecore_hwfn * p_hwfn)7908 qlnx_find_hwfn_index(struct ecore_hwfn *p_hwfn)
7909 {
7910 int i;
7911 struct ecore_dev *cdev;
7912
7913 cdev = p_hwfn->p_dev;
7914
7915 for (i = 0; i < cdev->num_hwfns; i++) {
7916 if (&cdev->hwfns[i] == p_hwfn)
7917 break;
7918 }
7919
7920 if (i >= cdev->num_hwfns)
7921 return (-1);
7922
7923 return (i);
7924 }
7925
7926 static int
__qlnx_pf_vf_msg(struct ecore_hwfn * p_hwfn,uint16_t rel_vf_id)7927 __qlnx_pf_vf_msg(struct ecore_hwfn *p_hwfn, uint16_t rel_vf_id)
7928 {
7929 qlnx_host_t *ha = (qlnx_host_t *)p_hwfn->p_dev;
7930 int i;
7931
7932 QL_DPRINT2(ha, "ha = %p cdev = %p p_hwfn = %p rel_vf_id = %d\n",
7933 ha, p_hwfn->p_dev, p_hwfn, rel_vf_id);
7934
7935 if ((i = qlnx_find_hwfn_index(p_hwfn)) == -1)
7936 return (-1);
7937
7938 if (ha->sriov_task[i].pf_taskqueue != NULL) {
7939 atomic_testandset_32(&ha->sriov_task[i].flags,
7940 QLNX_SRIOV_TASK_FLAGS_VF_PF_MSG);
7941
7942 taskqueue_enqueue(ha->sriov_task[i].pf_taskqueue,
7943 &ha->sriov_task[i].pf_task);
7944 }
7945
7946 return (ECORE_SUCCESS);
7947 }
7948
7949 int
qlnx_pf_vf_msg(void * p_hwfn,uint16_t relative_vf_id)7950 qlnx_pf_vf_msg(void *p_hwfn, uint16_t relative_vf_id)
7951 {
7952 return (__qlnx_pf_vf_msg(p_hwfn, relative_vf_id));
7953 }
7954
7955 static void
__qlnx_vf_flr_update(struct ecore_hwfn * p_hwfn)7956 __qlnx_vf_flr_update(struct ecore_hwfn *p_hwfn)
7957 {
7958 qlnx_host_t *ha = (qlnx_host_t *)p_hwfn->p_dev;
7959 int i;
7960
7961 if (!ha->sriov_initialized)
7962 return;
7963
7964 QL_DPRINT2(ha, "ha = %p cdev = %p p_hwfn = %p \n",
7965 ha, p_hwfn->p_dev, p_hwfn);
7966
7967 if ((i = qlnx_find_hwfn_index(p_hwfn)) == -1)
7968 return;
7969
7970 if (ha->sriov_task[i].pf_taskqueue != NULL) {
7971 atomic_testandset_32(&ha->sriov_task[i].flags,
7972 QLNX_SRIOV_TASK_FLAGS_VF_FLR_UPDATE);
7973
7974 taskqueue_enqueue(ha->sriov_task[i].pf_taskqueue,
7975 &ha->sriov_task[i].pf_task);
7976 }
7977
7978 return;
7979 }
7980
7981 void
qlnx_vf_flr_update(void * p_hwfn)7982 qlnx_vf_flr_update(void *p_hwfn)
7983 {
7984 __qlnx_vf_flr_update(p_hwfn);
7985
7986 return;
7987 }
7988
7989 #ifndef QLNX_VF
7990
7991 static void
qlnx_vf_bulleting_update(struct ecore_hwfn * p_hwfn)7992 qlnx_vf_bulleting_update(struct ecore_hwfn *p_hwfn)
7993 {
7994 qlnx_host_t *ha = (qlnx_host_t *)p_hwfn->p_dev;
7995 int i;
7996
7997 QL_DPRINT2(ha, "ha = %p cdev = %p p_hwfn = %p \n",
7998 ha, p_hwfn->p_dev, p_hwfn);
7999
8000 if ((i = qlnx_find_hwfn_index(p_hwfn)) == -1)
8001 return;
8002
8003 QL_DPRINT2(ha, "ha = %p cdev = %p p_hwfn = %p i = %d\n",
8004 ha, p_hwfn->p_dev, p_hwfn, i);
8005
8006 if (ha->sriov_task[i].pf_taskqueue != NULL) {
8007 atomic_testandset_32(&ha->sriov_task[i].flags,
8008 QLNX_SRIOV_TASK_FLAGS_BULLETIN_UPDATE);
8009
8010 taskqueue_enqueue(ha->sriov_task[i].pf_taskqueue,
8011 &ha->sriov_task[i].pf_task);
8012 }
8013 }
8014
8015 static void
qlnx_initialize_sriov(qlnx_host_t * ha)8016 qlnx_initialize_sriov(qlnx_host_t *ha)
8017 {
8018 device_t dev;
8019 nvlist_t *pf_schema, *vf_schema;
8020 int iov_error;
8021
8022 dev = ha->pci_dev;
8023
8024 pf_schema = pci_iov_schema_alloc_node();
8025 vf_schema = pci_iov_schema_alloc_node();
8026
8027 pci_iov_schema_add_unicast_mac(vf_schema, "mac-addr", 0, NULL);
8028 pci_iov_schema_add_bool(vf_schema, "allow-set-mac",
8029 IOV_SCHEMA_HASDEFAULT, FALSE);
8030 pci_iov_schema_add_bool(vf_schema, "allow-promisc",
8031 IOV_SCHEMA_HASDEFAULT, FALSE);
8032 pci_iov_schema_add_uint16(vf_schema, "num-queues",
8033 IOV_SCHEMA_HASDEFAULT, 1);
8034
8035 iov_error = pci_iov_attach(dev, pf_schema, vf_schema);
8036
8037 if (iov_error != 0) {
8038 ha->sriov_initialized = 0;
8039 } else {
8040 device_printf(dev, "SRIOV initialized\n");
8041 ha->sriov_initialized = 1;
8042 }
8043
8044 return;
8045 }
8046
8047 static void
qlnx_sriov_disable(qlnx_host_t * ha)8048 qlnx_sriov_disable(qlnx_host_t *ha)
8049 {
8050 struct ecore_dev *cdev;
8051 int i, j;
8052
8053 cdev = &ha->cdev;
8054
8055 ecore_iov_set_vfs_to_disable(cdev, true);
8056
8057 for_each_hwfn(cdev, i) {
8058 struct ecore_hwfn *hwfn = &cdev->hwfns[i];
8059 struct ecore_ptt *ptt = ecore_ptt_acquire(hwfn);
8060
8061 if (!ptt) {
8062 QL_DPRINT1(ha, "Failed to acquire ptt\n");
8063 return;
8064 }
8065 /* Clean WFQ db and configure equal weight for all vports */
8066 ecore_clean_wfq_db(hwfn, ptt);
8067
8068 ecore_for_each_vf(hwfn, j) {
8069 int k = 0;
8070
8071 if (!ecore_iov_is_valid_vfid(hwfn, j, true, false))
8072 continue;
8073
8074 if (ecore_iov_is_vf_started(hwfn, j)) {
8075 /* Wait until VF is disabled before releasing */
8076
8077 for (k = 0; k < 100; k++) {
8078 if (!ecore_iov_is_vf_stopped(hwfn, j)) {
8079 qlnx_mdelay(__func__, 10);
8080 } else
8081 break;
8082 }
8083 }
8084
8085 if (k < 100)
8086 ecore_iov_release_hw_for_vf(&cdev->hwfns[i],
8087 ptt, j);
8088 else {
8089 QL_DPRINT1(ha,
8090 "Timeout waiting for VF's FLR to end\n");
8091 }
8092 }
8093 ecore_ptt_release(hwfn, ptt);
8094 }
8095
8096 ecore_iov_set_vfs_to_disable(cdev, false);
8097
8098 return;
8099 }
8100
8101 static void
qlnx_sriov_enable_qid_config(struct ecore_hwfn * hwfn,u16 vfid,struct ecore_iov_vf_init_params * params)8102 qlnx_sriov_enable_qid_config(struct ecore_hwfn *hwfn, u16 vfid,
8103 struct ecore_iov_vf_init_params *params)
8104 {
8105 u16 base, i;
8106
8107 /* Since we have an equal resource distribution per-VF, and we assume
8108 * PF has acquired the ECORE_PF_L2_QUE first queues, we start setting
8109 * sequentially from there.
8110 */
8111 base = FEAT_NUM(hwfn, ECORE_PF_L2_QUE) + vfid * params->num_queues;
8112
8113 params->rel_vf_id = vfid;
8114
8115 for (i = 0; i < params->num_queues; i++) {
8116 params->req_rx_queue[i] = base + i;
8117 params->req_tx_queue[i] = base + i;
8118 }
8119
8120 /* PF uses indices 0 for itself; Set vport/RSS afterwards */
8121 params->vport_id = vfid + 1;
8122 params->rss_eng_id = vfid + 1;
8123
8124 return;
8125 }
8126
8127 static int
qlnx_iov_init(device_t dev,uint16_t num_vfs,const nvlist_t * nvlist_params)8128 qlnx_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *nvlist_params)
8129 {
8130 qlnx_host_t *ha;
8131 struct ecore_dev *cdev;
8132 struct ecore_iov_vf_init_params params;
8133 int ret, j, i;
8134 uint32_t max_vfs;
8135
8136 if ((ha = device_get_softc(dev)) == NULL) {
8137 device_printf(dev, "%s: cannot get softc\n", __func__);
8138 return (-1);
8139 }
8140
8141 if (qlnx_create_pf_taskqueues(ha) != 0)
8142 goto qlnx_iov_init_err0;
8143
8144 cdev = &ha->cdev;
8145
8146 max_vfs = RESC_NUM(&cdev->hwfns[0], ECORE_VPORT);
8147
8148 QL_DPRINT2(ha," dev = %p enter num_vfs = %d max_vfs = %d\n",
8149 dev, num_vfs, max_vfs);
8150
8151 if (num_vfs >= max_vfs) {
8152 QL_DPRINT1(ha, "Can start at most %d VFs\n",
8153 (RESC_NUM(&cdev->hwfns[0], ECORE_VPORT) - 1));
8154 goto qlnx_iov_init_err0;
8155 }
8156
8157 ha->vf_attr = malloc(((sizeof (qlnx_vf_attr_t) * num_vfs)), M_QLNXBUF,
8158 M_NOWAIT);
8159
8160 if (ha->vf_attr == NULL)
8161 goto qlnx_iov_init_err0;
8162
8163 memset(¶ms, 0, sizeof(params));
8164
8165 /* Initialize HW for VF access */
8166 for_each_hwfn(cdev, j) {
8167 struct ecore_hwfn *hwfn = &cdev->hwfns[j];
8168 struct ecore_ptt *ptt = ecore_ptt_acquire(hwfn);
8169
8170 /* Make sure not to use more than 16 queues per VF */
8171 params.num_queues = min_t(int,
8172 (FEAT_NUM(hwfn, ECORE_VF_L2_QUE) / num_vfs),
8173 16);
8174
8175 if (!ptt) {
8176 QL_DPRINT1(ha, "Failed to acquire ptt\n");
8177 goto qlnx_iov_init_err1;
8178 }
8179
8180 for (i = 0; i < num_vfs; i++) {
8181 if (!ecore_iov_is_valid_vfid(hwfn, i, false, true))
8182 continue;
8183
8184 qlnx_sriov_enable_qid_config(hwfn, i, ¶ms);
8185
8186 ret = ecore_iov_init_hw_for_vf(hwfn, ptt, ¶ms);
8187
8188 if (ret) {
8189 QL_DPRINT1(ha, "Failed to enable VF[%d]\n", i);
8190 ecore_ptt_release(hwfn, ptt);
8191 goto qlnx_iov_init_err1;
8192 }
8193 }
8194
8195 ecore_ptt_release(hwfn, ptt);
8196 }
8197
8198 ha->num_vfs = num_vfs;
8199 qlnx_inform_vf_link_state(&cdev->hwfns[0], ha);
8200
8201 QL_DPRINT2(ha," dev = %p exit num_vfs = %d\n", dev, num_vfs);
8202
8203 return (0);
8204
8205 qlnx_iov_init_err1:
8206 qlnx_sriov_disable(ha);
8207
8208 qlnx_iov_init_err0:
8209 qlnx_destroy_pf_taskqueues(ha);
8210 ha->num_vfs = 0;
8211
8212 return (-1);
8213 }
8214
8215 static void
qlnx_iov_uninit(device_t dev)8216 qlnx_iov_uninit(device_t dev)
8217 {
8218 qlnx_host_t *ha;
8219
8220 if ((ha = device_get_softc(dev)) == NULL) {
8221 device_printf(dev, "%s: cannot get softc\n", __func__);
8222 return;
8223 }
8224
8225 QL_DPRINT2(ha," dev = %p enter\n", dev);
8226
8227 qlnx_sriov_disable(ha);
8228 qlnx_destroy_pf_taskqueues(ha);
8229
8230 free(ha->vf_attr, M_QLNXBUF);
8231 ha->vf_attr = NULL;
8232
8233 ha->num_vfs = 0;
8234
8235 QL_DPRINT2(ha," dev = %p exit\n", dev);
8236 return;
8237 }
8238
8239 static int
qlnx_iov_add_vf(device_t dev,uint16_t vfnum,const nvlist_t * params)8240 qlnx_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
8241 {
8242 qlnx_host_t *ha;
8243 qlnx_vf_attr_t *vf_attr;
8244 unsigned const char *mac;
8245 size_t size;
8246 struct ecore_hwfn *p_hwfn;
8247
8248 if ((ha = device_get_softc(dev)) == NULL) {
8249 device_printf(dev, "%s: cannot get softc\n", __func__);
8250 return (-1);
8251 }
8252
8253 QL_DPRINT2(ha," dev = %p enter vfnum = %d\n", dev, vfnum);
8254
8255 if (vfnum > (ha->num_vfs - 1)) {
8256 QL_DPRINT1(ha, " VF[%d] is greater than max allowed [%d]\n",
8257 vfnum, (ha->num_vfs - 1));
8258 }
8259
8260 vf_attr = &ha->vf_attr[vfnum];
8261
8262 if (nvlist_exists_binary(params, "mac-addr")) {
8263 mac = nvlist_get_binary(params, "mac-addr", &size);
8264 bcopy(mac, vf_attr->mac_addr, ETHER_ADDR_LEN);
8265 device_printf(dev,
8266 "%s: mac_addr = %02x:%02x:%02x:%02x:%02x:%02x\n",
8267 __func__, vf_attr->mac_addr[0],
8268 vf_attr->mac_addr[1], vf_attr->mac_addr[2],
8269 vf_attr->mac_addr[3], vf_attr->mac_addr[4],
8270 vf_attr->mac_addr[5]);
8271 p_hwfn = &ha->cdev.hwfns[0];
8272 ecore_iov_bulletin_set_mac(p_hwfn, vf_attr->mac_addr,
8273 vfnum);
8274 }
8275
8276 QL_DPRINT2(ha," dev = %p exit vfnum = %d\n", dev, vfnum);
8277 return (0);
8278 }
8279
8280 static void
qlnx_handle_vf_msg(qlnx_host_t * ha,struct ecore_hwfn * p_hwfn)8281 qlnx_handle_vf_msg(qlnx_host_t *ha, struct ecore_hwfn *p_hwfn)
8282 {
8283 uint64_t events[ECORE_VF_ARRAY_LENGTH];
8284 struct ecore_ptt *ptt;
8285 int i;
8286
8287 ptt = ecore_ptt_acquire(p_hwfn);
8288 if (!ptt) {
8289 QL_DPRINT1(ha, "Can't acquire PTT; re-scheduling\n");
8290 __qlnx_pf_vf_msg(p_hwfn, 0);
8291 return;
8292 }
8293
8294 ecore_iov_pf_get_pending_events(p_hwfn, events);
8295
8296 QL_DPRINT2(ha, "Event mask of VF events:"
8297 "0x%" PRIu64 "0x%" PRIu64 " 0x%" PRIu64 "\n",
8298 events[0], events[1], events[2]);
8299
8300 ecore_for_each_vf(p_hwfn, i) {
8301 /* Skip VFs with no pending messages */
8302 if (!(events[i / 64] & (1ULL << (i % 64))))
8303 continue;
8304
8305 QL_DPRINT2(ha,
8306 "Handling VF message from VF 0x%02x [Abs 0x%02x]\n",
8307 i, p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
8308
8309 /* Copy VF's message to PF's request buffer for that VF */
8310 if (ecore_iov_copy_vf_msg(p_hwfn, ptt, i))
8311 continue;
8312
8313 ecore_iov_process_mbx_req(p_hwfn, ptt, i);
8314 }
8315
8316 ecore_ptt_release(p_hwfn, ptt);
8317
8318 return;
8319 }
8320
8321 static void
qlnx_handle_vf_flr_update(qlnx_host_t * ha,struct ecore_hwfn * p_hwfn)8322 qlnx_handle_vf_flr_update(qlnx_host_t *ha, struct ecore_hwfn *p_hwfn)
8323 {
8324 struct ecore_ptt *ptt;
8325 int ret;
8326
8327 ptt = ecore_ptt_acquire(p_hwfn);
8328
8329 if (!ptt) {
8330 QL_DPRINT1(ha, "Can't acquire PTT; re-scheduling\n");
8331 __qlnx_vf_flr_update(p_hwfn);
8332 return;
8333 }
8334
8335 ret = ecore_iov_vf_flr_cleanup(p_hwfn, ptt);
8336
8337 if (ret) {
8338 QL_DPRINT1(ha, "ecore_iov_vf_flr_cleanup failed; re-scheduling\n");
8339 }
8340
8341 ecore_ptt_release(p_hwfn, ptt);
8342
8343 return;
8344 }
8345
8346 static void
qlnx_handle_bulletin_update(qlnx_host_t * ha,struct ecore_hwfn * p_hwfn)8347 qlnx_handle_bulletin_update(qlnx_host_t *ha, struct ecore_hwfn *p_hwfn)
8348 {
8349 struct ecore_ptt *ptt;
8350 int i;
8351
8352 ptt = ecore_ptt_acquire(p_hwfn);
8353
8354 if (!ptt) {
8355 QL_DPRINT1(ha, "Can't acquire PTT; re-scheduling\n");
8356 qlnx_vf_bulleting_update(p_hwfn);
8357 return;
8358 }
8359
8360 ecore_for_each_vf(p_hwfn, i) {
8361 QL_DPRINT1(ha, "ecore_iov_post_vf_bulletin[%p, %d]\n",
8362 p_hwfn, i);
8363 ecore_iov_post_vf_bulletin(p_hwfn, i, ptt);
8364 }
8365
8366 ecore_ptt_release(p_hwfn, ptt);
8367
8368 return;
8369 }
8370
8371 static void
qlnx_pf_taskqueue(void * context,int pending)8372 qlnx_pf_taskqueue(void *context, int pending)
8373 {
8374 struct ecore_hwfn *p_hwfn;
8375 qlnx_host_t *ha;
8376 int i;
8377
8378 p_hwfn = context;
8379
8380 if (p_hwfn == NULL)
8381 return;
8382
8383 ha = (qlnx_host_t *)(p_hwfn->p_dev);
8384
8385 if ((i = qlnx_find_hwfn_index(p_hwfn)) == -1)
8386 return;
8387
8388 if (atomic_testandclear_32(&ha->sriov_task[i].flags,
8389 QLNX_SRIOV_TASK_FLAGS_VF_PF_MSG))
8390 qlnx_handle_vf_msg(ha, p_hwfn);
8391
8392 if (atomic_testandclear_32(&ha->sriov_task[i].flags,
8393 QLNX_SRIOV_TASK_FLAGS_VF_FLR_UPDATE))
8394 qlnx_handle_vf_flr_update(ha, p_hwfn);
8395
8396 if (atomic_testandclear_32(&ha->sriov_task[i].flags,
8397 QLNX_SRIOV_TASK_FLAGS_BULLETIN_UPDATE))
8398 qlnx_handle_bulletin_update(ha, p_hwfn);
8399
8400 return;
8401 }
8402
8403 static int
qlnx_create_pf_taskqueues(qlnx_host_t * ha)8404 qlnx_create_pf_taskqueues(qlnx_host_t *ha)
8405 {
8406 int i;
8407 uint8_t tq_name[32];
8408
8409 for (i = 0; i < ha->cdev.num_hwfns; i++) {
8410 struct ecore_hwfn *p_hwfn = &ha->cdev.hwfns[i];
8411
8412 bzero(tq_name, sizeof (tq_name));
8413 snprintf(tq_name, sizeof (tq_name), "ql_pf_tq_%d", i);
8414
8415 TASK_INIT(&ha->sriov_task[i].pf_task, 0, qlnx_pf_taskqueue, p_hwfn);
8416
8417 ha->sriov_task[i].pf_taskqueue = taskqueue_create(tq_name, M_NOWAIT,
8418 taskqueue_thread_enqueue,
8419 &ha->sriov_task[i].pf_taskqueue);
8420
8421 if (ha->sriov_task[i].pf_taskqueue == NULL)
8422 return (-1);
8423
8424 taskqueue_start_threads(&ha->sriov_task[i].pf_taskqueue, 1,
8425 PI_NET, "%s", tq_name);
8426
8427 QL_DPRINT1(ha, "%p\n", ha->sriov_task[i].pf_taskqueue);
8428 }
8429
8430 return (0);
8431 }
8432
8433 static void
qlnx_destroy_pf_taskqueues(qlnx_host_t * ha)8434 qlnx_destroy_pf_taskqueues(qlnx_host_t *ha)
8435 {
8436 int i;
8437
8438 for (i = 0; i < ha->cdev.num_hwfns; i++) {
8439 if (ha->sriov_task[i].pf_taskqueue != NULL) {
8440 taskqueue_drain(ha->sriov_task[i].pf_taskqueue,
8441 &ha->sriov_task[i].pf_task);
8442 taskqueue_free(ha->sriov_task[i].pf_taskqueue);
8443 ha->sriov_task[i].pf_taskqueue = NULL;
8444 }
8445 }
8446 return;
8447 }
8448
8449 static void
qlnx_inform_vf_link_state(struct ecore_hwfn * p_hwfn,qlnx_host_t * ha)8450 qlnx_inform_vf_link_state(struct ecore_hwfn *p_hwfn, qlnx_host_t *ha)
8451 {
8452 struct ecore_mcp_link_capabilities caps;
8453 struct ecore_mcp_link_params params;
8454 struct ecore_mcp_link_state link;
8455 int i;
8456
8457 if (!p_hwfn->pf_iov_info)
8458 return;
8459
8460 memset(¶ms, 0, sizeof(struct ecore_mcp_link_params));
8461 memset(&link, 0, sizeof(struct ecore_mcp_link_state));
8462 memset(&caps, 0, sizeof(struct ecore_mcp_link_capabilities));
8463
8464 memcpy(&caps, ecore_mcp_get_link_capabilities(p_hwfn), sizeof(caps));
8465 memcpy(&link, ecore_mcp_get_link_state(p_hwfn), sizeof(link));
8466 memcpy(¶ms, ecore_mcp_get_link_params(p_hwfn), sizeof(params));
8467
8468 QL_DPRINT2(ha, "called\n");
8469
8470 /* Update bulletin of all future possible VFs with link configuration */
8471 for (i = 0; i < p_hwfn->p_dev->p_iov_info->total_vfs; i++) {
8472 /* Modify link according to the VF's configured link state */
8473
8474 link.link_up = false;
8475
8476 if (ha->link_up) {
8477 link.link_up = true;
8478 /* Set speed according to maximum supported by HW.
8479 * that is 40G for regular devices and 100G for CMT
8480 * mode devices.
8481 */
8482 link.speed = (p_hwfn->p_dev->num_hwfns > 1) ?
8483 100000 : link.speed;
8484 }
8485 QL_DPRINT2(ha, "link [%d] = %d\n", i, link.link_up);
8486 ecore_iov_set_link(p_hwfn, i, ¶ms, &link, &caps);
8487 }
8488
8489 qlnx_vf_bulleting_update(p_hwfn);
8490
8491 return;
8492 }
8493 #endif /* #ifndef QLNX_VF */
8494 #endif /* #ifdef CONFIG_ECORE_SRIOV */
8495