1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui
23 *
24 */
25
26 #include <linux/firmware.h>
27 #include <drm/drmP.h>
28 #include "amdgpu.h"
29 #include "amdgpu_psp.h"
30 #include "amdgpu_ucode.h"
31 #include "soc15_common.h"
32 #include "psp_v3_1.h"
33 #include "psp_v10_0.h"
34
35 static void psp_set_funcs(struct amdgpu_device *adev);
36
psp_early_init(void * handle)37 static int psp_early_init(void *handle)
38 {
39 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
40 struct psp_context *psp = &adev->psp;
41
42 psp_set_funcs(adev);
43
44 switch (adev->asic_type) {
45 case CHIP_VEGA10:
46 case CHIP_VEGA12:
47 case CHIP_VEGA20:
48 psp_v3_1_set_psp_funcs(psp);
49 break;
50 case CHIP_RAVEN:
51 psp_v10_0_set_psp_funcs(psp);
52 break;
53 default:
54 return -EINVAL;
55 }
56
57 psp->adev = adev;
58
59 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
60 return 0;
61
62 return 0;
63 }
64
psp_sw_init(void * handle)65 static int psp_sw_init(void *handle)
66 {
67 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
68 struct psp_context *psp = &adev->psp;
69 int ret;
70
71 ret = psp_init_microcode(psp);
72 if (ret) {
73 DRM_ERROR("Failed to load psp firmware!\n");
74 return ret;
75 }
76
77 return 0;
78 }
79
psp_sw_fini(void * handle)80 static int psp_sw_fini(void *handle)
81 {
82 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
83
84 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
85 return 0;
86
87 release_firmware(adev->psp.sos_fw);
88 adev->psp.sos_fw = NULL;
89 release_firmware(adev->psp.asd_fw);
90 adev->psp.asd_fw = NULL;
91 return 0;
92 }
93
psp_wait_for(struct psp_context * psp,uint32_t reg_index,uint32_t reg_val,uint32_t mask,bool check_changed)94 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
95 uint32_t reg_val, uint32_t mask, bool check_changed)
96 {
97 uint32_t val;
98 int i;
99 struct amdgpu_device *adev = psp->adev;
100
101 for (i = 0; i < adev->usec_timeout; i++) {
102 val = RREG32(reg_index);
103 if (check_changed) {
104 if (val != reg_val)
105 return 0;
106 } else {
107 if ((val & mask) == reg_val)
108 return 0;
109 }
110 udelay(1);
111 }
112
113 return -ETIME;
114 }
115
116 static int
psp_cmd_submit_buf(struct psp_context * psp,struct amdgpu_firmware_info * ucode,struct psp_gfx_cmd_resp * cmd,uint64_t fence_mc_addr,int index)117 psp_cmd_submit_buf(struct psp_context *psp,
118 struct amdgpu_firmware_info *ucode,
119 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr,
120 int index)
121 {
122 int ret;
123
124 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
125
126 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
127
128 ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
129 fence_mc_addr, index);
130
131 while (*((unsigned int *)psp->fence_buf) != index) {
132 msleep(1);
133 }
134
135 if (ucode) {
136 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
137 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
138 }
139
140 return ret;
141 }
142
psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint64_t tmr_mc,uint32_t size)143 static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd,
144 uint64_t tmr_mc, uint32_t size)
145 {
146 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
147 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
148 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
149 cmd->cmd.cmd_setup_tmr.buf_size = size;
150 }
151
152 /* Set up Trusted Memory Region */
psp_tmr_init(struct psp_context * psp)153 static int psp_tmr_init(struct psp_context *psp)
154 {
155 int ret;
156
157 /*
158 * Allocate 3M memory aligned to 1M from Frame Buffer (local
159 * physical).
160 *
161 * Note: this memory need be reserved till the driver
162 * uninitializes.
163 */
164 ret = amdgpu_bo_create_kernel(psp->adev, 0x300000, 0x100000,
165 AMDGPU_GEM_DOMAIN_VRAM,
166 &psp->tmr_bo, (u64 *)&psp->tmr_mc_addr, &psp->tmr_buf);
167
168 return ret;
169 }
170
psp_tmr_load(struct psp_context * psp)171 static int psp_tmr_load(struct psp_context *psp)
172 {
173 int ret;
174 struct psp_gfx_cmd_resp *cmd;
175
176 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
177 if (!cmd)
178 return -ENOMEM;
179
180 psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, 0x300000);
181
182 ret = psp_cmd_submit_buf(psp, NULL, cmd,
183 psp->fence_buf_mc_addr, 1);
184 if (ret)
185 goto failed;
186
187 kfree(cmd);
188
189 return 0;
190
191 failed:
192 kfree(cmd);
193 return ret;
194 }
195
psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint64_t asd_mc,uint64_t asd_mc_shared,uint32_t size,uint32_t shared_size)196 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
197 uint64_t asd_mc, uint64_t asd_mc_shared,
198 uint32_t size, uint32_t shared_size)
199 {
200 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
201 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
202 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
203 cmd->cmd.cmd_load_ta.app_len = size;
204
205 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
206 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
207 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
208 }
209
psp_asd_init(struct psp_context * psp)210 static int psp_asd_init(struct psp_context *psp)
211 {
212 int ret;
213
214 /*
215 * Allocate 16k memory aligned to 4k from Frame Buffer (local
216 * physical) for shared ASD <-> Driver
217 */
218 ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
219 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
220 &psp->asd_shared_bo,
221 (u64 *)&psp->asd_shared_mc_addr,
222 &psp->asd_shared_buf);
223
224 return ret;
225 }
226
psp_asd_load(struct psp_context * psp)227 static int psp_asd_load(struct psp_context *psp)
228 {
229 int ret;
230 struct psp_gfx_cmd_resp *cmd;
231
232 /* If PSP version doesn't match ASD version, asd loading will be failed.
233 * add workaround to bypass it for sriov now.
234 * TODO: add version check to make it common
235 */
236 if (amdgpu_sriov_vf(psp->adev))
237 return 0;
238
239 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
240 if (!cmd)
241 return -ENOMEM;
242
243 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
244 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
245
246 psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
247 psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
248
249 ret = psp_cmd_submit_buf(psp, NULL, cmd,
250 psp->fence_buf_mc_addr, 2);
251
252 kfree(cmd);
253
254 return ret;
255 }
256
psp_hw_start(struct psp_context * psp)257 static int psp_hw_start(struct psp_context *psp)
258 {
259 struct amdgpu_device *adev = psp->adev;
260 int ret;
261
262 if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
263 ret = psp_bootloader_load_sysdrv(psp);
264 if (ret)
265 return ret;
266
267 ret = psp_bootloader_load_sos(psp);
268 if (ret)
269 return ret;
270 }
271
272 ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
273 if (ret)
274 return ret;
275
276 ret = psp_tmr_load(psp);
277 if (ret)
278 return ret;
279
280 ret = psp_asd_load(psp);
281 if (ret)
282 return ret;
283
284 return 0;
285 }
286
psp_np_fw_load(struct psp_context * psp)287 static int psp_np_fw_load(struct psp_context *psp)
288 {
289 int i, ret;
290 struct amdgpu_firmware_info *ucode;
291 struct amdgpu_device* adev = psp->adev;
292
293 for (i = 0; i < adev->firmware.max_ucodes; i++) {
294 ucode = &adev->firmware.ucode[i];
295 if (!ucode->fw)
296 continue;
297
298 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
299 psp_smu_reload_quirk(psp))
300 continue;
301 if (amdgpu_sriov_vf(adev) &&
302 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
303 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
304 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
305 /*skip ucode loading in SRIOV VF */
306 continue;
307
308 ret = psp_prep_cmd_buf(ucode, psp->cmd);
309 if (ret)
310 return ret;
311
312 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
313 psp->fence_buf_mc_addr, i + 3);
314 if (ret)
315 return ret;
316
317 #if 0
318 /* check if firmware loaded sucessfully */
319 if (!amdgpu_psp_check_fw_loading_status(adev, i))
320 return -EINVAL;
321 #endif
322 }
323
324 return 0;
325 }
326
psp_load_fw(struct amdgpu_device * adev)327 static int psp_load_fw(struct amdgpu_device *adev)
328 {
329 int ret;
330 struct psp_context *psp = &adev->psp;
331
332 if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset != 0)
333 goto skip_memalloc;
334
335 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
336 if (!psp->cmd)
337 return -ENOMEM;
338
339 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
340 AMDGPU_GEM_DOMAIN_GTT,
341 &psp->fw_pri_bo,
342 (u64 *)&psp->fw_pri_mc_addr,
343 &psp->fw_pri_buf);
344 if (ret)
345 goto failed;
346
347 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
348 AMDGPU_GEM_DOMAIN_VRAM,
349 &psp->fence_buf_bo,
350 (u64 *)&psp->fence_buf_mc_addr,
351 &psp->fence_buf);
352 if (ret)
353 goto failed_mem2;
354
355 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
356 AMDGPU_GEM_DOMAIN_VRAM,
357 &psp->cmd_buf_bo, (u64 *)&psp->cmd_buf_mc_addr,
358 (void **)&psp->cmd_buf_mem);
359 if (ret)
360 goto failed_mem1;
361
362 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
363
364 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
365 if (ret)
366 goto failed_mem;
367
368 ret = psp_tmr_init(psp);
369 if (ret)
370 goto failed_mem;
371
372 ret = psp_asd_init(psp);
373 if (ret)
374 goto failed_mem;
375
376 skip_memalloc:
377 ret = psp_hw_start(psp);
378 if (ret)
379 goto failed_mem;
380
381 ret = psp_np_fw_load(psp);
382 if (ret)
383 goto failed_mem;
384
385 return 0;
386
387 failed_mem:
388 amdgpu_bo_free_kernel(&psp->cmd_buf_bo,
389 (u64 *)&psp->cmd_buf_mc_addr,
390 (void **)&psp->cmd_buf_mem);
391 failed_mem1:
392 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
393 (u64 *)&psp->fence_buf_mc_addr, &psp->fence_buf);
394 failed_mem2:
395 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
396 (u64 *)&psp->fw_pri_mc_addr, &psp->fw_pri_buf);
397 failed:
398 kfree(psp->cmd);
399 psp->cmd = NULL;
400 return ret;
401 }
402
psp_hw_init(void * handle)403 static int psp_hw_init(void *handle)
404 {
405 int ret;
406 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
407
408
409 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
410 return 0;
411
412 mutex_lock(&adev->firmware.mutex);
413 /*
414 * This sequence is just used on hw_init only once, no need on
415 * resume.
416 */
417 ret = amdgpu_ucode_init_bo(adev);
418 if (ret)
419 goto failed;
420
421 ret = psp_load_fw(adev);
422 if (ret) {
423 DRM_ERROR("PSP firmware loading failed\n");
424 goto failed;
425 }
426
427 mutex_unlock(&adev->firmware.mutex);
428 return 0;
429
430 failed:
431 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
432 mutex_unlock(&adev->firmware.mutex);
433 return -EINVAL;
434 }
435
psp_hw_fini(void * handle)436 static int psp_hw_fini(void *handle)
437 {
438 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
439 struct psp_context *psp = &adev->psp;
440
441 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
442 return 0;
443
444 amdgpu_ucode_fini_bo(adev);
445
446 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
447
448 amdgpu_bo_free_kernel(&psp->tmr_bo, (u64 *)&psp->tmr_mc_addr, &psp->tmr_buf);
449 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
450 (u64 *)&psp->fw_pri_mc_addr, &psp->fw_pri_buf);
451 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
452 (u64 *)&psp->fence_buf_mc_addr, &psp->fence_buf);
453 amdgpu_bo_free_kernel(&psp->asd_shared_bo, (u64 *)&psp->asd_shared_mc_addr,
454 &psp->asd_shared_buf);
455 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, (u64 *)&psp->cmd_buf_mc_addr,
456 (void **)&psp->cmd_buf_mem);
457
458 kfree(psp->cmd);
459 psp->cmd = NULL;
460
461 return 0;
462 }
463
psp_suspend(void * handle)464 static int psp_suspend(void *handle)
465 {
466 int ret;
467 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
468 struct psp_context *psp = &adev->psp;
469
470 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
471 return 0;
472
473 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
474 if (ret) {
475 DRM_ERROR("PSP ring stop failed\n");
476 return ret;
477 }
478
479 return 0;
480 }
481
psp_resume(void * handle)482 static int psp_resume(void *handle)
483 {
484 int ret;
485 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
486 struct psp_context *psp = &adev->psp;
487
488 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
489 return 0;
490
491 DRM_INFO("PSP is resuming...\n");
492
493 mutex_lock(&adev->firmware.mutex);
494
495 ret = psp_hw_start(psp);
496 if (ret)
497 goto failed;
498
499 ret = psp_np_fw_load(psp);
500 if (ret)
501 goto failed;
502
503 mutex_unlock(&adev->firmware.mutex);
504
505 return 0;
506
507 failed:
508 DRM_ERROR("PSP resume failed\n");
509 mutex_unlock(&adev->firmware.mutex);
510 return ret;
511 }
512
psp_gpu_reset(struct amdgpu_device * adev)513 int psp_gpu_reset(struct amdgpu_device *adev)
514 {
515 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
516 return 0;
517
518 return psp_mode1_reset(&adev->psp);
519 }
520
psp_check_fw_loading_status(struct amdgpu_device * adev,enum AMDGPU_UCODE_ID ucode_type)521 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
522 enum AMDGPU_UCODE_ID ucode_type)
523 {
524 struct amdgpu_firmware_info *ucode = NULL;
525
526 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
527 DRM_INFO("firmware is not loaded by PSP\n");
528 return true;
529 }
530
531 if (!adev->firmware.fw_size)
532 return false;
533
534 ucode = &adev->firmware.ucode[ucode_type];
535 if (!ucode->fw || !ucode->ucode_size)
536 return false;
537
538 return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
539 }
540
psp_set_clockgating_state(void * handle,enum amd_clockgating_state state)541 static int psp_set_clockgating_state(void *handle,
542 enum amd_clockgating_state state)
543 {
544 return 0;
545 }
546
psp_set_powergating_state(void * handle,enum amd_powergating_state state)547 static int psp_set_powergating_state(void *handle,
548 enum amd_powergating_state state)
549 {
550 return 0;
551 }
552
553 const struct amd_ip_funcs psp_ip_funcs = {
554 .name = "psp",
555 .early_init = psp_early_init,
556 .late_init = NULL,
557 .sw_init = psp_sw_init,
558 .sw_fini = psp_sw_fini,
559 .hw_init = psp_hw_init,
560 .hw_fini = psp_hw_fini,
561 .suspend = psp_suspend,
562 .resume = psp_resume,
563 .is_idle = NULL,
564 .check_soft_reset = NULL,
565 .wait_for_idle = NULL,
566 .soft_reset = NULL,
567 .set_clockgating_state = psp_set_clockgating_state,
568 .set_powergating_state = psp_set_powergating_state,
569 };
570
571 static const struct amdgpu_psp_funcs psp_funcs = {
572 .check_fw_loading_status = psp_check_fw_loading_status,
573 };
574
psp_set_funcs(struct amdgpu_device * adev)575 static void psp_set_funcs(struct amdgpu_device *adev)
576 {
577 if (NULL == adev->firmware.funcs)
578 adev->firmware.funcs = &psp_funcs;
579 }
580
581 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
582 {
583 .type = AMD_IP_BLOCK_TYPE_PSP,
584 .major = 3,
585 .minor = 1,
586 .rev = 0,
587 .funcs = &psp_ip_funcs,
588 };
589
590 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
591 {
592 .type = AMD_IP_BLOCK_TYPE_PSP,
593 .major = 10,
594 .minor = 0,
595 .rev = 0,
596 .funcs = &psp_ip_funcs,
597 };
598