1 /*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * William Jolitz.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
39 */
40
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
43
44 #include "opt_cpu.h"
45
46 #include <sys/param.h>
47 #include <sys/bus.h>
48 #include <sys/cpu.h>
49 #include <sys/eventhandler.h>
50 #include <sys/limits.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/sysctl.h>
54 #include <sys/power.h>
55
56 #include <machine/asmacros.h>
57 #include <machine/clock.h>
58 #include <machine/cputypes.h>
59 #include <machine/frame.h>
60 #include <machine/intr_machdep.h>
61 #include <machine/md_var.h>
62 #include <machine/segments.h>
63 #include <machine/specialreg.h>
64
65 #include <amd64/vmm/intel/vmx_controls.h>
66 #include <x86/isa/icu.h>
67 #include <x86/vmware.h>
68
69 #ifdef __i386__
70 #define IDENTBLUE_CYRIX486 0
71 #define IDENTBLUE_IBMCPU 1
72 #define IDENTBLUE_CYRIXM2 2
73
74 static void identifycyrix(void);
75 static void print_transmeta_info(void);
76 #endif
77 static u_int find_cpu_vendor_id(void);
78 static void print_AMD_info(void);
79 static void print_INTEL_info(void);
80 static void print_INTEL_TLB(u_int data);
81 static void print_hypervisor_info(void);
82 static void print_svm_info(void);
83 static void print_via_padlock_info(void);
84 static void print_vmx_info(void);
85
86 #ifdef __i386__
87 int cpu; /* Are we 386, 386sx, 486, etc? */
88 int cpu_class;
89 #endif
90 u_int cpu_feature; /* Feature flags */
91 u_int cpu_feature2; /* Feature flags */
92 u_int amd_feature; /* AMD feature flags */
93 u_int amd_feature2; /* AMD feature flags */
94 u_int amd_pminfo; /* AMD advanced power management info */
95 u_int amd_extended_feature_extensions;
96 u_int via_feature_rng; /* VIA RNG features */
97 u_int via_feature_xcrypt; /* VIA ACE features */
98 u_int cpu_high; /* Highest arg to CPUID */
99 u_int cpu_exthigh; /* Highest arg to extended CPUID */
100 u_int cpu_id; /* Stepping ID */
101 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
102 u_int cpu_procinfo2; /* Multicore info */
103 char cpu_vendor[20]; /* CPU Origin code */
104 u_int cpu_vendor_id; /* CPU vendor ID */
105 u_int cpu_fxsr; /* SSE enabled */
106 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
107 u_int cpu_clflush_line_size = 32;
108 u_int cpu_stdext_feature; /* %ebx */
109 u_int cpu_stdext_feature2; /* %ecx */
110 u_int cpu_stdext_feature3; /* %edx */
111 uint64_t cpu_ia32_arch_caps;
112 u_int cpu_max_ext_state_size;
113 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
114 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
115 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
116 u_int cpu_maxphyaddr; /* Max phys addr width in bits */
117 char machine[] = MACHINE;
118
119 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
120 &via_feature_rng, 0,
121 "VIA RNG feature available in CPU");
122 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
123 &via_feature_xcrypt, 0,
124 "VIA xcrypt feature available in CPU");
125
126 #ifdef __amd64__
127 #ifdef SCTL_MASK32
128 extern int adaptive_machine_arch;
129 #endif
130
131 static int
sysctl_hw_machine(SYSCTL_HANDLER_ARGS)132 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
133 {
134 #ifdef SCTL_MASK32
135 static const char machine32[] = "i386";
136 #endif
137 int error;
138
139 #ifdef SCTL_MASK32
140 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
141 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
142 else
143 #endif
144 error = SYSCTL_OUT(req, machine, sizeof(machine));
145 return (error);
146
147 }
148 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
149 CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
150 #else
151 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
152 machine, 0, "Machine class");
153 #endif
154
155 static char cpu_model[128];
156 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE,
157 cpu_model, 0, "Machine model");
158
159 static int hw_clockrate;
160 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
161 &hw_clockrate, 0, "CPU instruction clock rate");
162
163 u_int hv_high;
164 char hv_vendor[16];
165 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor,
166 0, "Hypervisor vendor");
167
168 static eventhandler_tag tsc_post_tag;
169
170 static char cpu_brand[48];
171
172 #ifdef __i386__
173 #define MAX_BRAND_INDEX 8
174
175 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
176 NULL, /* No brand */
177 "Intel Celeron",
178 "Intel Pentium III",
179 "Intel Pentium III Xeon",
180 NULL,
181 NULL,
182 NULL,
183 NULL,
184 "Intel Pentium 4"
185 };
186
187 static struct {
188 char *cpu_name;
189 int cpu_class;
190 } cpus[] = {
191 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
192 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
193 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
194 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
195 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
196 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
197 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
198 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
199 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
200 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
201 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
202 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
203 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
204 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
205 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
206 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
207 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
208 };
209 #endif
210
211 static struct {
212 char *vendor;
213 u_int vendor_id;
214 } cpu_vendors[] = {
215 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
216 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
217 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
218 #ifdef __i386__
219 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
220 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */
221 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
222 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */
223 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */
224 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */
225 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */
226 #if 0
227 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
228 { "TransmetaCPU", CPU_VENDOR_TRANSMETA },
229 #endif
230 #endif
231 };
232
233 void
printcpuinfo(void)234 printcpuinfo(void)
235 {
236 u_int regs[4], i;
237 char *brand;
238
239 printf("CPU: ");
240 #ifdef __i386__
241 cpu_class = cpus[cpu].cpu_class;
242 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
243 #else
244 strncpy(cpu_model, "Hammer", sizeof (cpu_model));
245 #endif
246
247 /* Check for extended CPUID information and a processor name. */
248 if (cpu_exthigh >= 0x80000004) {
249 brand = cpu_brand;
250 for (i = 0x80000002; i < 0x80000005; i++) {
251 do_cpuid(i, regs);
252 memcpy(brand, regs, sizeof(regs));
253 brand += sizeof(regs);
254 }
255 }
256
257 switch (cpu_vendor_id) {
258 case CPU_VENDOR_INTEL:
259 #ifdef __i386__
260 if ((cpu_id & 0xf00) > 0x300) {
261 u_int brand_index;
262
263 cpu_model[0] = '\0';
264
265 switch (cpu_id & 0x3000) {
266 case 0x1000:
267 strcpy(cpu_model, "Overdrive ");
268 break;
269 case 0x2000:
270 strcpy(cpu_model, "Dual ");
271 break;
272 }
273
274 switch (cpu_id & 0xf00) {
275 case 0x400:
276 strcat(cpu_model, "i486 ");
277 /* Check the particular flavor of 486 */
278 switch (cpu_id & 0xf0) {
279 case 0x00:
280 case 0x10:
281 strcat(cpu_model, "DX");
282 break;
283 case 0x20:
284 strcat(cpu_model, "SX");
285 break;
286 case 0x30:
287 strcat(cpu_model, "DX2");
288 break;
289 case 0x40:
290 strcat(cpu_model, "SL");
291 break;
292 case 0x50:
293 strcat(cpu_model, "SX2");
294 break;
295 case 0x70:
296 strcat(cpu_model,
297 "DX2 Write-Back Enhanced");
298 break;
299 case 0x80:
300 strcat(cpu_model, "DX4");
301 break;
302 }
303 break;
304 case 0x500:
305 /* Check the particular flavor of 586 */
306 strcat(cpu_model, "Pentium");
307 switch (cpu_id & 0xf0) {
308 case 0x00:
309 strcat(cpu_model, " A-step");
310 break;
311 case 0x10:
312 strcat(cpu_model, "/P5");
313 break;
314 case 0x20:
315 strcat(cpu_model, "/P54C");
316 break;
317 case 0x30:
318 strcat(cpu_model, "/P24T");
319 break;
320 case 0x40:
321 strcat(cpu_model, "/P55C");
322 break;
323 case 0x70:
324 strcat(cpu_model, "/P54C");
325 break;
326 case 0x80:
327 strcat(cpu_model, "/P55C (quarter-micron)");
328 break;
329 default:
330 /* nothing */
331 break;
332 }
333 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
334 /*
335 * XXX - If/when Intel fixes the bug, this
336 * should also check the version of the
337 * CPU, not just that it's a Pentium.
338 */
339 has_f00f_bug = 1;
340 #endif
341 break;
342 case 0x600:
343 /* Check the particular flavor of 686 */
344 switch (cpu_id & 0xf0) {
345 case 0x00:
346 strcat(cpu_model, "Pentium Pro A-step");
347 break;
348 case 0x10:
349 strcat(cpu_model, "Pentium Pro");
350 break;
351 case 0x30:
352 case 0x50:
353 case 0x60:
354 strcat(cpu_model,
355 "Pentium II/Pentium II Xeon/Celeron");
356 cpu = CPU_PII;
357 break;
358 case 0x70:
359 case 0x80:
360 case 0xa0:
361 case 0xb0:
362 strcat(cpu_model,
363 "Pentium III/Pentium III Xeon/Celeron");
364 cpu = CPU_PIII;
365 break;
366 default:
367 strcat(cpu_model, "Unknown 80686");
368 break;
369 }
370 break;
371 case 0xf00:
372 strcat(cpu_model, "Pentium 4");
373 cpu = CPU_P4;
374 break;
375 default:
376 strcat(cpu_model, "unknown");
377 break;
378 }
379
380 /*
381 * If we didn't get a brand name from the extended
382 * CPUID, try to look it up in the brand table.
383 */
384 if (cpu_high > 0 && *cpu_brand == '\0') {
385 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
386 if (brand_index <= MAX_BRAND_INDEX &&
387 cpu_brandtable[brand_index] != NULL)
388 strcpy(cpu_brand,
389 cpu_brandtable[brand_index]);
390 }
391 }
392 #else
393 /* Please make up your mind folks! */
394 strcat(cpu_model, "EM64T");
395 #endif
396 break;
397 case CPU_VENDOR_AMD:
398 /*
399 * Values taken from AMD Processor Recognition
400 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
401 * (also describes ``Features'' encodings.
402 */
403 strcpy(cpu_model, "AMD ");
404 #ifdef __i386__
405 switch (cpu_id & 0xFF0) {
406 case 0x410:
407 strcat(cpu_model, "Standard Am486DX");
408 break;
409 case 0x430:
410 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
411 break;
412 case 0x470:
413 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
414 break;
415 case 0x480:
416 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
417 break;
418 case 0x490:
419 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
420 break;
421 case 0x4E0:
422 strcat(cpu_model, "Am5x86 Write-Through");
423 break;
424 case 0x4F0:
425 strcat(cpu_model, "Am5x86 Write-Back");
426 break;
427 case 0x500:
428 strcat(cpu_model, "K5 model 0");
429 break;
430 case 0x510:
431 strcat(cpu_model, "K5 model 1");
432 break;
433 case 0x520:
434 strcat(cpu_model, "K5 PR166 (model 2)");
435 break;
436 case 0x530:
437 strcat(cpu_model, "K5 PR200 (model 3)");
438 break;
439 case 0x560:
440 strcat(cpu_model, "K6");
441 break;
442 case 0x570:
443 strcat(cpu_model, "K6 266 (model 1)");
444 break;
445 case 0x580:
446 strcat(cpu_model, "K6-2");
447 break;
448 case 0x590:
449 strcat(cpu_model, "K6-III");
450 break;
451 case 0x5a0:
452 strcat(cpu_model, "Geode LX");
453 break;
454 default:
455 strcat(cpu_model, "Unknown");
456 break;
457 }
458 #else
459 if ((cpu_id & 0xf00) == 0xf00)
460 strcat(cpu_model, "AMD64 Processor");
461 else
462 strcat(cpu_model, "Unknown");
463 #endif
464 break;
465 #ifdef __i386__
466 case CPU_VENDOR_CYRIX:
467 strcpy(cpu_model, "Cyrix ");
468 switch (cpu_id & 0xff0) {
469 case 0x440:
470 strcat(cpu_model, "MediaGX");
471 break;
472 case 0x520:
473 strcat(cpu_model, "6x86");
474 break;
475 case 0x540:
476 cpu_class = CPUCLASS_586;
477 strcat(cpu_model, "GXm");
478 break;
479 case 0x600:
480 strcat(cpu_model, "6x86MX");
481 break;
482 default:
483 /*
484 * Even though CPU supports the cpuid
485 * instruction, it can be disabled.
486 * Therefore, this routine supports all Cyrix
487 * CPUs.
488 */
489 switch (cyrix_did & 0xf0) {
490 case 0x00:
491 switch (cyrix_did & 0x0f) {
492 case 0x00:
493 strcat(cpu_model, "486SLC");
494 break;
495 case 0x01:
496 strcat(cpu_model, "486DLC");
497 break;
498 case 0x02:
499 strcat(cpu_model, "486SLC2");
500 break;
501 case 0x03:
502 strcat(cpu_model, "486DLC2");
503 break;
504 case 0x04:
505 strcat(cpu_model, "486SRx");
506 break;
507 case 0x05:
508 strcat(cpu_model, "486DRx");
509 break;
510 case 0x06:
511 strcat(cpu_model, "486SRx2");
512 break;
513 case 0x07:
514 strcat(cpu_model, "486DRx2");
515 break;
516 case 0x08:
517 strcat(cpu_model, "486SRu");
518 break;
519 case 0x09:
520 strcat(cpu_model, "486DRu");
521 break;
522 case 0x0a:
523 strcat(cpu_model, "486SRu2");
524 break;
525 case 0x0b:
526 strcat(cpu_model, "486DRu2");
527 break;
528 default:
529 strcat(cpu_model, "Unknown");
530 break;
531 }
532 break;
533 case 0x10:
534 switch (cyrix_did & 0x0f) {
535 case 0x00:
536 strcat(cpu_model, "486S");
537 break;
538 case 0x01:
539 strcat(cpu_model, "486S2");
540 break;
541 case 0x02:
542 strcat(cpu_model, "486Se");
543 break;
544 case 0x03:
545 strcat(cpu_model, "486S2e");
546 break;
547 case 0x0a:
548 strcat(cpu_model, "486DX");
549 break;
550 case 0x0b:
551 strcat(cpu_model, "486DX2");
552 break;
553 case 0x0f:
554 strcat(cpu_model, "486DX4");
555 break;
556 default:
557 strcat(cpu_model, "Unknown");
558 break;
559 }
560 break;
561 case 0x20:
562 if ((cyrix_did & 0x0f) < 8)
563 strcat(cpu_model, "6x86"); /* Where did you get it? */
564 else
565 strcat(cpu_model, "5x86");
566 break;
567 case 0x30:
568 strcat(cpu_model, "6x86");
569 break;
570 case 0x40:
571 if ((cyrix_did & 0xf000) == 0x3000) {
572 cpu_class = CPUCLASS_586;
573 strcat(cpu_model, "GXm");
574 } else
575 strcat(cpu_model, "MediaGX");
576 break;
577 case 0x50:
578 strcat(cpu_model, "6x86MX");
579 break;
580 case 0xf0:
581 switch (cyrix_did & 0x0f) {
582 case 0x0d:
583 strcat(cpu_model, "Overdrive CPU");
584 break;
585 case 0x0e:
586 strcpy(cpu_model, "Texas Instruments 486SXL");
587 break;
588 case 0x0f:
589 strcat(cpu_model, "486SLC/DLC");
590 break;
591 default:
592 strcat(cpu_model, "Unknown");
593 break;
594 }
595 break;
596 default:
597 strcat(cpu_model, "Unknown");
598 break;
599 }
600 break;
601 }
602 break;
603 case CPU_VENDOR_RISE:
604 strcpy(cpu_model, "Rise ");
605 switch (cpu_id & 0xff0) {
606 case 0x500: /* 6401 and 6441 (Kirin) */
607 case 0x520: /* 6510 (Lynx) */
608 strcat(cpu_model, "mP6");
609 break;
610 default:
611 strcat(cpu_model, "Unknown");
612 }
613 break;
614 #endif
615 case CPU_VENDOR_CENTAUR:
616 #ifdef __i386__
617 switch (cpu_id & 0xff0) {
618 case 0x540:
619 strcpy(cpu_model, "IDT WinChip C6");
620 break;
621 case 0x580:
622 strcpy(cpu_model, "IDT WinChip 2");
623 break;
624 case 0x590:
625 strcpy(cpu_model, "IDT WinChip 3");
626 break;
627 case 0x660:
628 strcpy(cpu_model, "VIA C3 Samuel");
629 break;
630 case 0x670:
631 if (cpu_id & 0x8)
632 strcpy(cpu_model, "VIA C3 Ezra");
633 else
634 strcpy(cpu_model, "VIA C3 Samuel 2");
635 break;
636 case 0x680:
637 strcpy(cpu_model, "VIA C3 Ezra-T");
638 break;
639 case 0x690:
640 strcpy(cpu_model, "VIA C3 Nehemiah");
641 break;
642 case 0x6a0:
643 case 0x6d0:
644 strcpy(cpu_model, "VIA C7 Esther");
645 break;
646 case 0x6f0:
647 strcpy(cpu_model, "VIA Nano");
648 break;
649 default:
650 strcpy(cpu_model, "VIA/IDT Unknown");
651 }
652 #else
653 strcpy(cpu_model, "VIA ");
654 if ((cpu_id & 0xff0) == 0x6f0)
655 strcat(cpu_model, "Nano Processor");
656 else
657 strcat(cpu_model, "Unknown");
658 #endif
659 break;
660 #ifdef __i386__
661 case CPU_VENDOR_IBM:
662 strcpy(cpu_model, "Blue Lightning CPU");
663 break;
664 case CPU_VENDOR_NSC:
665 switch (cpu_id & 0xff0) {
666 case 0x540:
667 strcpy(cpu_model, "Geode SC1100");
668 cpu = CPU_GEODE1100;
669 break;
670 default:
671 strcpy(cpu_model, "Geode/NSC unknown");
672 break;
673 }
674 break;
675 #endif
676 default:
677 strcat(cpu_model, "Unknown");
678 break;
679 }
680
681 /*
682 * Replace cpu_model with cpu_brand minus leading spaces if
683 * we have one.
684 */
685 brand = cpu_brand;
686 while (*brand == ' ')
687 ++brand;
688 if (*brand != '\0')
689 strcpy(cpu_model, brand);
690
691 printf("%s (", cpu_model);
692 if (tsc_freq != 0) {
693 hw_clockrate = (tsc_freq + 5000) / 1000000;
694 printf("%jd.%02d-MHz ",
695 (intmax_t)(tsc_freq + 4999) / 1000000,
696 (u_int)((tsc_freq + 4999) / 10000) % 100);
697 }
698 #ifdef __i386__
699 switch(cpu_class) {
700 case CPUCLASS_286:
701 printf("286");
702 break;
703 case CPUCLASS_386:
704 printf("386");
705 break;
706 #if defined(I486_CPU)
707 case CPUCLASS_486:
708 printf("486");
709 break;
710 #endif
711 #if defined(I586_CPU)
712 case CPUCLASS_586:
713 printf("586");
714 break;
715 #endif
716 #if defined(I686_CPU)
717 case CPUCLASS_686:
718 printf("686");
719 break;
720 #endif
721 default:
722 printf("Unknown"); /* will panic below... */
723 }
724 #else
725 printf("K8");
726 #endif
727 printf("-class CPU)\n");
728 if (*cpu_vendor)
729 printf(" Origin=\"%s\"", cpu_vendor);
730 if (cpu_id)
731 printf(" Id=0x%x", cpu_id);
732
733 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
734 cpu_vendor_id == CPU_VENDOR_AMD ||
735 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
736 #ifdef __i386__
737 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
738 cpu_vendor_id == CPU_VENDOR_RISE ||
739 cpu_vendor_id == CPU_VENDOR_NSC ||
740 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
741 #endif
742 0) {
743 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id));
744 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id));
745 printf(" Stepping=%u", cpu_id & CPUID_STEPPING);
746 #ifdef __i386__
747 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
748 printf("\n DIR=0x%04x", cyrix_did);
749 #endif
750
751 /*
752 * AMD CPUID Specification
753 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
754 *
755 * Intel Processor Identification and CPUID Instruction
756 * http://www.intel.com/assets/pdf/appnote/241618.pdf
757 */
758 if (cpu_high > 0) {
759
760 /*
761 * Here we should probably set up flags indicating
762 * whether or not various features are available.
763 * The interesting ones are probably VME, PSE, PAE,
764 * and PGE. The code already assumes without bothering
765 * to check that all CPUs >= Pentium have a TSC and
766 * MSRs.
767 */
768 printf("\n Features=0x%b", cpu_feature,
769 "\020"
770 "\001FPU" /* Integral FPU */
771 "\002VME" /* Extended VM86 mode support */
772 "\003DE" /* Debugging Extensions (CR4.DE) */
773 "\004PSE" /* 4MByte page tables */
774 "\005TSC" /* Timestamp counter */
775 "\006MSR" /* Machine specific registers */
776 "\007PAE" /* Physical address extension */
777 "\010MCE" /* Machine Check support */
778 "\011CX8" /* CMPEXCH8 instruction */
779 "\012APIC" /* SMP local APIC */
780 "\013oldMTRR" /* Previous implementation of MTRR */
781 "\014SEP" /* Fast System Call */
782 "\015MTRR" /* Memory Type Range Registers */
783 "\016PGE" /* PG_G (global bit) support */
784 "\017MCA" /* Machine Check Architecture */
785 "\020CMOV" /* CMOV instruction */
786 "\021PAT" /* Page attributes table */
787 "\022PSE36" /* 36 bit address space support */
788 "\023PN" /* Processor Serial number */
789 "\024CLFLUSH" /* Has the CLFLUSH instruction */
790 "\025<b20>"
791 "\026DTS" /* Debug Trace Store */
792 "\027ACPI" /* ACPI support */
793 "\030MMX" /* MMX instructions */
794 "\031FXSR" /* FXSAVE/FXRSTOR */
795 "\032SSE" /* Streaming SIMD Extensions */
796 "\033SSE2" /* Streaming SIMD Extensions #2 */
797 "\034SS" /* Self snoop */
798 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
799 "\036TM" /* Thermal Monitor clock slowdown */
800 "\037IA64" /* CPU can execute IA64 instructions */
801 "\040PBE" /* Pending Break Enable */
802 );
803
804 if (cpu_feature2 != 0) {
805 printf("\n Features2=0x%b", cpu_feature2,
806 "\020"
807 "\001SSE3" /* SSE3 */
808 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
809 "\003DTES64" /* 64-bit Debug Trace */
810 "\004MON" /* MONITOR/MWAIT Instructions */
811 "\005DS_CPL" /* CPL Qualified Debug Store */
812 "\006VMX" /* Virtual Machine Extensions */
813 "\007SMX" /* Safer Mode Extensions */
814 "\010EST" /* Enhanced SpeedStep */
815 "\011TM2" /* Thermal Monitor 2 */
816 "\012SSSE3" /* SSSE3 */
817 "\013CNXT-ID" /* L1 context ID available */
818 "\014SDBG" /* IA32 silicon debug */
819 "\015FMA" /* Fused Multiply Add */
820 "\016CX16" /* CMPXCHG16B Instruction */
821 "\017xTPR" /* Send Task Priority Messages*/
822 "\020PDCM" /* Perf/Debug Capability MSR */
823 "\021<b16>"
824 "\022PCID" /* Process-context Identifiers*/
825 "\023DCA" /* Direct Cache Access */
826 "\024SSE4.1" /* SSE 4.1 */
827 "\025SSE4.2" /* SSE 4.2 */
828 "\026x2APIC" /* xAPIC Extensions */
829 "\027MOVBE" /* MOVBE Instruction */
830 "\030POPCNT" /* POPCNT Instruction */
831 "\031TSCDLT" /* TSC-Deadline Timer */
832 "\032AESNI" /* AES Crypto */
833 "\033XSAVE" /* XSAVE/XRSTOR States */
834 "\034OSXSAVE" /* OS-Enabled State Management*/
835 "\035AVX" /* Advanced Vector Extensions */
836 "\036F16C" /* Half-precision conversions */
837 "\037RDRAND" /* RDRAND Instruction */
838 "\040HV" /* Hypervisor */
839 );
840 }
841
842 if (amd_feature != 0) {
843 printf("\n AMD Features=0x%b", amd_feature,
844 "\020" /* in hex */
845 "\001<s0>" /* Same */
846 "\002<s1>" /* Same */
847 "\003<s2>" /* Same */
848 "\004<s3>" /* Same */
849 "\005<s4>" /* Same */
850 "\006<s5>" /* Same */
851 "\007<s6>" /* Same */
852 "\010<s7>" /* Same */
853 "\011<s8>" /* Same */
854 "\012<s9>" /* Same */
855 "\013<b10>" /* Undefined */
856 "\014SYSCALL" /* Have SYSCALL/SYSRET */
857 "\015<s12>" /* Same */
858 "\016<s13>" /* Same */
859 "\017<s14>" /* Same */
860 "\020<s15>" /* Same */
861 "\021<s16>" /* Same */
862 "\022<s17>" /* Same */
863 "\023<b18>" /* Reserved, unknown */
864 "\024MP" /* Multiprocessor Capable */
865 "\025NX" /* Has EFER.NXE, NX */
866 "\026<b21>" /* Undefined */
867 "\027MMX+" /* AMD MMX Extensions */
868 "\030<s23>" /* Same */
869 "\031<s24>" /* Same */
870 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
871 "\033Page1GB" /* 1-GB large page support */
872 "\034RDTSCP" /* RDTSCP */
873 "\035<b28>" /* Undefined */
874 "\036LM" /* 64 bit long mode */
875 "\0373DNow!+" /* AMD 3DNow! Extensions */
876 "\0403DNow!" /* AMD 3DNow! */
877 );
878 }
879
880 if (amd_feature2 != 0) {
881 printf("\n AMD Features2=0x%b", amd_feature2,
882 "\020"
883 "\001LAHF" /* LAHF/SAHF in long mode */
884 "\002CMP" /* CMP legacy */
885 "\003SVM" /* Secure Virtual Mode */
886 "\004ExtAPIC" /* Extended APIC register */
887 "\005CR8" /* CR8 in legacy mode */
888 "\006ABM" /* LZCNT instruction */
889 "\007SSE4A" /* SSE4A */
890 "\010MAS" /* Misaligned SSE mode */
891 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
892 "\012OSVW" /* OS visible workaround */
893 "\013IBS" /* Instruction based sampling */
894 "\014XOP" /* XOP extended instructions */
895 "\015SKINIT" /* SKINIT/STGI */
896 "\016WDT" /* Watchdog timer */
897 "\017<b14>"
898 "\020LWP" /* Lightweight Profiling */
899 "\021FMA4" /* 4-operand FMA instructions */
900 "\022TCE" /* Translation Cache Extension */
901 "\023<b18>"
902 "\024NodeId" /* NodeId MSR support */
903 "\025<b20>"
904 "\026TBM" /* Trailing Bit Manipulation */
905 "\027Topology" /* Topology Extensions */
906 "\030PCXC" /* Core perf count */
907 "\031PNXC" /* NB perf count */
908 "\032<b25>"
909 "\033DBE" /* Data Breakpoint extension */
910 "\034PTSC" /* Performance TSC */
911 "\035PL2I" /* L2I perf count */
912 "\036MWAITX" /* MONITORX/MWAITX instructions */
913 "\037<b30>"
914 "\040<b31>"
915 );
916 }
917
918 if (cpu_stdext_feature != 0) {
919 printf("\n Structured Extended Features=0x%b",
920 cpu_stdext_feature,
921 "\020"
922 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
923 "\001FSGSBASE"
924 "\002TSCADJ"
925 "\003SGX"
926 /* Bit Manipulation Instructions */
927 "\004BMI1"
928 /* Hardware Lock Elision */
929 "\005HLE"
930 /* Advanced Vector Instructions 2 */
931 "\006AVX2"
932 /* FDP_EXCPTN_ONLY */
933 "\007FDPEXC"
934 /* Supervisor Mode Execution Prot. */
935 "\010SMEP"
936 /* Bit Manipulation Instructions */
937 "\011BMI2"
938 "\012ERMS"
939 /* Invalidate Processor Context ID */
940 "\013INVPCID"
941 /* Restricted Transactional Memory */
942 "\014RTM"
943 "\015PQM"
944 "\016NFPUSG"
945 /* Intel Memory Protection Extensions */
946 "\017MPX"
947 "\020PQE"
948 /* AVX512 Foundation */
949 "\021AVX512F"
950 "\022AVX512DQ"
951 /* Enhanced NRBG */
952 "\023RDSEED"
953 /* ADCX + ADOX */
954 "\024ADX"
955 /* Supervisor Mode Access Prevention */
956 "\025SMAP"
957 "\026AVX512IFMA"
958 "\027PCOMMIT"
959 "\030CLFLUSHOPT"
960 "\031CLWB"
961 "\032PROCTRACE"
962 "\033AVX512PF"
963 "\034AVX512ER"
964 "\035AVX512CD"
965 "\036SHA"
966 "\037AVX512BW"
967 "\040AVX512VL"
968 );
969 }
970
971 if (cpu_stdext_feature2 != 0) {
972 printf("\n Structured Extended Features2=0x%b",
973 cpu_stdext_feature2,
974 "\020"
975 "\001PREFETCHWT1"
976 "\002AVX512VBMI"
977 "\003UMIP"
978 "\004PKU"
979 "\005OSPKE"
980 "\006WAITPKG"
981 "\007AVX512VBMI2"
982 "\011GFNI"
983 "\012VAES"
984 "\013VPCLMULQDQ"
985 "\014AVX512VNNI"
986 "\015AVX512BITALG"
987 "\016AVX512VPOPCNTDQ"
988 "\027RDPID"
989 "\032CLDEMOTE"
990 "\034MOVDIRI"
991 "\035MOVDIRI64B"
992 "\036ENQCMD"
993 "\037SGXLC"
994 );
995 }
996
997 if (cpu_stdext_feature3 != 0) {
998 printf("\n Structured Extended Features3=0x%b",
999 cpu_stdext_feature3,
1000 "\020"
1001 "\003AVX512_4VNNIW"
1002 "\004AVX512_4FMAPS"
1003 "\011AVX512VP2INTERSECT"
1004 "\012MCUOPT"
1005 "\013MD_CLEAR"
1006 "\016TSXFA"
1007 "\023PCONFIG"
1008 "\033IBPB"
1009 "\034STIBP"
1010 "\035L1DFL"
1011 "\036ARCH_CAP"
1012 "\037CORE_CAP"
1013 "\040SSBD"
1014 );
1015 }
1016
1017 if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
1018 cpuid_count(0xd, 0x1, regs);
1019 if (regs[0] != 0) {
1020 printf("\n XSAVE Features=0x%b",
1021 regs[0],
1022 "\020"
1023 "\001XSAVEOPT"
1024 "\002XSAVEC"
1025 "\003XINUSE"
1026 "\004XSAVES");
1027 }
1028 }
1029
1030 if (cpu_ia32_arch_caps != 0) {
1031 printf("\n IA32_ARCH_CAPS=0x%b",
1032 (u_int)cpu_ia32_arch_caps,
1033 "\020"
1034 "\001RDCL_NO"
1035 "\002IBRS_ALL"
1036 "\003RSBA"
1037 "\004SKIP_L1DFL_VME"
1038 "\005SSB_NO"
1039 "\006MDS_NO"
1040 "\010TSX_CTRL"
1041 "\011TAA_NO"
1042 );
1043 }
1044
1045 if (amd_extended_feature_extensions != 0) {
1046 printf("\n "
1047 "AMD Extended Feature Extensions ID EBX="
1048 "0x%b", amd_extended_feature_extensions,
1049 "\020"
1050 "\001CLZERO"
1051 "\002IRPerf"
1052 "\003XSaveErPtr");
1053 }
1054
1055 if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1056 print_via_padlock_info();
1057
1058 if (cpu_feature2 & CPUID2_VMX)
1059 print_vmx_info();
1060
1061 if (amd_feature2 & AMDID2_SVM)
1062 print_svm_info();
1063
1064 if ((cpu_feature & CPUID_HTT) &&
1065 cpu_vendor_id == CPU_VENDOR_AMD)
1066 cpu_feature &= ~CPUID_HTT;
1067
1068 /*
1069 * If this CPU supports P-state invariant TSC then
1070 * mention the capability.
1071 */
1072 if (tsc_is_invariant) {
1073 printf("\n TSC: P-state invariant");
1074 if (tsc_perf_stat)
1075 printf(", performance statistics");
1076 }
1077 }
1078 #ifdef __i386__
1079 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1080 printf(" DIR=0x%04x", cyrix_did);
1081 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
1082 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
1083 #ifndef CYRIX_CACHE_REALLY_WORKS
1084 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1085 printf("\n CPU cache: write-through mode");
1086 #endif
1087 #endif
1088 }
1089
1090 /* Avoid ugly blank lines: only print newline when we have to. */
1091 if (*cpu_vendor || cpu_id)
1092 printf("\n");
1093
1094 if (bootverbose) {
1095 if (cpu_vendor_id == CPU_VENDOR_AMD)
1096 print_AMD_info();
1097 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1098 print_INTEL_info();
1099 #ifdef __i386__
1100 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1101 print_transmeta_info();
1102 #endif
1103 }
1104
1105 print_hypervisor_info();
1106 }
1107
1108 #ifdef __i386__
1109 void
panicifcpuunsupported(void)1110 panicifcpuunsupported(void)
1111 {
1112
1113 #if !defined(lint)
1114 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1115 #error This kernel is not configured for one of the supported CPUs
1116 #endif
1117 #else /* lint */
1118 #endif /* lint */
1119 /*
1120 * Now that we have told the user what they have,
1121 * let them know if that machine type isn't configured.
1122 */
1123 switch (cpu_class) {
1124 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
1125 case CPUCLASS_386:
1126 #if !defined(I486_CPU)
1127 case CPUCLASS_486:
1128 #endif
1129 #if !defined(I586_CPU)
1130 case CPUCLASS_586:
1131 #endif
1132 #if !defined(I686_CPU)
1133 case CPUCLASS_686:
1134 #endif
1135 panic("CPU class not configured");
1136 default:
1137 break;
1138 }
1139 }
1140
1141 static volatile u_int trap_by_rdmsr;
1142
1143 /*
1144 * Special exception 6 handler.
1145 * The rdmsr instruction generates invalid opcodes fault on 486-class
1146 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
1147 * function identblue() when this handler is called. Stacked eip should
1148 * be advanced.
1149 */
1150 inthand_t bluetrap6;
1151 #ifdef __GNUCLIKE_ASM
1152 __asm
1153 (" \n\
1154 .text \n\
1155 .p2align 2,0x90 \n\
1156 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
1157 " __XSTRING(CNAME(bluetrap6)) ": \n\
1158 ss \n\
1159 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1160 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1161 iret \n\
1162 ");
1163 #endif
1164
1165 /*
1166 * Special exception 13 handler.
1167 * Accessing non-existent MSR generates general protection fault.
1168 */
1169 inthand_t bluetrap13;
1170 #ifdef __GNUCLIKE_ASM
1171 __asm
1172 (" \n\
1173 .text \n\
1174 .p2align 2,0x90 \n\
1175 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
1176 " __XSTRING(CNAME(bluetrap13)) ": \n\
1177 ss \n\
1178 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1179 popl %eax /* discard error code */ \n\
1180 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1181 iret \n\
1182 ");
1183 #endif
1184
1185 /*
1186 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1187 * support cpuid instruction. This function should be called after
1188 * loading interrupt descriptor table register.
1189 *
1190 * I don't like this method that handles fault, but I couldn't get
1191 * information for any other methods. Does blue giant know?
1192 */
1193 static int
identblue(void)1194 identblue(void)
1195 {
1196
1197 trap_by_rdmsr = 0;
1198
1199 /*
1200 * Cyrix 486-class CPU does not support rdmsr instruction.
1201 * The rdmsr instruction generates invalid opcode fault, and exception
1202 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
1203 * bluetrap6() set the magic number to trap_by_rdmsr.
1204 */
1205 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1206 GSEL(GCODE_SEL, SEL_KPL));
1207
1208 /*
1209 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1210 * In this case, rdmsr generates general protection fault, and
1211 * exception will be trapped by bluetrap13().
1212 */
1213 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1214 GSEL(GCODE_SEL, SEL_KPL));
1215
1216 rdmsr(0x1002); /* Cyrix CPU generates fault. */
1217
1218 if (trap_by_rdmsr == 0xa8c1d)
1219 return IDENTBLUE_CYRIX486;
1220 else if (trap_by_rdmsr == 0xa89c4)
1221 return IDENTBLUE_CYRIXM2;
1222 return IDENTBLUE_IBMCPU;
1223 }
1224
1225
1226 /*
1227 * identifycyrix() set lower 16 bits of cyrix_did as follows:
1228 *
1229 * F E D C B A 9 8 7 6 5 4 3 2 1 0
1230 * +-------+-------+---------------+
1231 * | SID | RID | Device ID |
1232 * | (DIR 1) | (DIR 0) |
1233 * +-------+-------+---------------+
1234 */
1235 static void
identifycyrix(void)1236 identifycyrix(void)
1237 {
1238 register_t saveintr;
1239 int ccr2_test = 0, dir_test = 0;
1240 u_char ccr2, ccr3;
1241
1242 saveintr = intr_disable();
1243
1244 ccr2 = read_cyrix_reg(CCR2);
1245 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1246 read_cyrix_reg(CCR2);
1247 if (read_cyrix_reg(CCR2) != ccr2)
1248 ccr2_test = 1;
1249 write_cyrix_reg(CCR2, ccr2);
1250
1251 ccr3 = read_cyrix_reg(CCR3);
1252 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1253 read_cyrix_reg(CCR3);
1254 if (read_cyrix_reg(CCR3) != ccr3)
1255 dir_test = 1; /* CPU supports DIRs. */
1256 write_cyrix_reg(CCR3, ccr3);
1257
1258 if (dir_test) {
1259 /* Device ID registers are available. */
1260 cyrix_did = read_cyrix_reg(DIR1) << 8;
1261 cyrix_did += read_cyrix_reg(DIR0);
1262 } else if (ccr2_test)
1263 cyrix_did = 0x0010; /* 486S A-step */
1264 else
1265 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
1266
1267 intr_restore(saveintr);
1268 }
1269 #endif
1270
1271 /* Update TSC freq with the value indicated by the caller. */
1272 static void
tsc_freq_changed(void * arg __unused,const struct cf_level * level,int status)1273 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1274 {
1275
1276 /* If there was an error during the transition, don't do anything. */
1277 if (status != 0)
1278 return;
1279
1280 /* Total setting for this level gives the new frequency in MHz. */
1281 hw_clockrate = level->total_set.freq;
1282 }
1283
1284 static void
hook_tsc_freq(void * arg __unused)1285 hook_tsc_freq(void *arg __unused)
1286 {
1287
1288 if (tsc_is_invariant)
1289 return;
1290
1291 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1292 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1293 }
1294
1295 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1296
1297 static const char *const vm_bnames[] = {
1298 "QEMU", /* QEMU */
1299 "Plex86", /* Plex86 */
1300 "Bochs", /* Bochs */
1301 "Xen", /* Xen */
1302 "BHYVE", /* bhyve */
1303 "Seabios", /* KVM */
1304 NULL
1305 };
1306
1307 static const char *const vm_pnames[] = {
1308 "VMware Virtual Platform", /* VMWare VM */
1309 "Virtual Machine", /* Microsoft VirtualPC */
1310 "VirtualBox", /* Sun xVM VirtualBox */
1311 "Parallels Virtual Platform", /* Parallels VM */
1312 "KVM", /* KVM */
1313 NULL
1314 };
1315
1316 void
identify_hypervisor(void)1317 identify_hypervisor(void)
1318 {
1319 u_int regs[4];
1320 char *p;
1321 int i;
1322
1323 /*
1324 * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1325 * http://lkml.org/lkml/2008/10/1/246
1326 *
1327 * KB1009458: Mechanisms to determine if software is running in
1328 * a VMware virtual machine
1329 * http://kb.vmware.com/kb/1009458
1330 */
1331 if (cpu_feature2 & CPUID2_HV) {
1332 vm_guest = VM_GUEST_VM;
1333 do_cpuid(0x40000000, regs);
1334
1335 /*
1336 * KVM from Linux kernels prior to commit
1337 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1338 * to 0 rather than a valid hv_high value. Check for
1339 * the KVM signature bytes and fixup %eax to the
1340 * highest supported leaf in that case.
1341 */
1342 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1343 regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1344 regs[0] = 0x40000001;
1345
1346 if (regs[0] >= 0x40000000) {
1347 hv_high = regs[0];
1348 ((u_int *)&hv_vendor)[0] = regs[1];
1349 ((u_int *)&hv_vendor)[1] = regs[2];
1350 ((u_int *)&hv_vendor)[2] = regs[3];
1351 hv_vendor[12] = '\0';
1352 if (strcmp(hv_vendor, "VMwareVMware") == 0)
1353 vm_guest = VM_GUEST_VMWARE;
1354 else if (strcmp(hv_vendor, "Microsoft Hv") == 0)
1355 vm_guest = VM_GUEST_HV;
1356 else if (strcmp(hv_vendor, "KVMKVMKVM") == 0)
1357 vm_guest = VM_GUEST_KVM;
1358 else if (strcmp(hv_vendor, "bhyve bhyve") == 0)
1359 vm_guest = VM_GUEST_BHYVE;
1360 }
1361 return;
1362 }
1363
1364 /*
1365 * Examine SMBIOS strings for older hypervisors.
1366 */
1367 p = kern_getenv("smbios.system.serial");
1368 if (p != NULL) {
1369 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1370 vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1371 if (regs[1] == VMW_HVMAGIC) {
1372 vm_guest = VM_GUEST_VMWARE;
1373 freeenv(p);
1374 return;
1375 }
1376 }
1377 freeenv(p);
1378 }
1379
1380 /*
1381 * XXX: Some of these entries may not be needed since they were
1382 * added to FreeBSD before the checks above.
1383 */
1384 p = kern_getenv("smbios.bios.vendor");
1385 if (p != NULL) {
1386 for (i = 0; vm_bnames[i] != NULL; i++)
1387 if (strcmp(p, vm_bnames[i]) == 0) {
1388 vm_guest = VM_GUEST_VM;
1389 freeenv(p);
1390 return;
1391 }
1392 freeenv(p);
1393 }
1394 p = kern_getenv("smbios.system.product");
1395 if (p != NULL) {
1396 for (i = 0; vm_pnames[i] != NULL; i++)
1397 if (strcmp(p, vm_pnames[i]) == 0) {
1398 vm_guest = VM_GUEST_VM;
1399 freeenv(p);
1400 return;
1401 }
1402 freeenv(p);
1403 }
1404 }
1405
1406 bool
fix_cpuid(void)1407 fix_cpuid(void)
1408 {
1409 uint64_t msr;
1410
1411 /*
1412 * Clear "Limit CPUID Maxval" bit and return true if the caller should
1413 * get the largest standard CPUID function number again if it is set
1414 * from BIOS. It is necessary for probing correct CPU topology later
1415 * and for the correct operation of the AVX-aware userspace.
1416 */
1417 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1418 ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1419 CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1420 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1421 CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1422 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1423 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1424 msr &= ~IA32_MISC_EN_LIMCPUID;
1425 wrmsr(MSR_IA32_MISC_ENABLE, msr);
1426 return (true);
1427 }
1428 }
1429
1430 /*
1431 * Re-enable AMD Topology Extension that could be disabled by BIOS
1432 * on some notebook processors. Without the extension it's really
1433 * hard to determine the correct CPU cache topology.
1434 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1435 * Models 60h-6Fh Processors, Publication # 50742.
1436 */
1437 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1438 CPUID_TO_FAMILY(cpu_id) == 0x15) {
1439 msr = rdmsr(MSR_EXTFEATURES);
1440 if ((msr & ((uint64_t)1 << 54)) == 0) {
1441 msr |= (uint64_t)1 << 54;
1442 wrmsr(MSR_EXTFEATURES, msr);
1443 return (true);
1444 }
1445 }
1446 return (false);
1447 }
1448
1449 void
identify_cpu1(void)1450 identify_cpu1(void)
1451 {
1452 u_int regs[4];
1453
1454 do_cpuid(0, regs);
1455 cpu_high = regs[0];
1456 ((u_int *)&cpu_vendor)[0] = regs[1];
1457 ((u_int *)&cpu_vendor)[1] = regs[3];
1458 ((u_int *)&cpu_vendor)[2] = regs[2];
1459 cpu_vendor[12] = '\0';
1460
1461 do_cpuid(1, regs);
1462 cpu_id = regs[0];
1463 cpu_procinfo = regs[1];
1464 cpu_feature = regs[3];
1465 cpu_feature2 = regs[2];
1466 }
1467
1468 void
identify_cpu2(void)1469 identify_cpu2(void)
1470 {
1471 u_int regs[4], cpu_stdext_disable;
1472
1473 if (cpu_high >= 7) {
1474 cpuid_count(7, 0, regs);
1475 cpu_stdext_feature = regs[1];
1476
1477 /*
1478 * Some hypervisors failed to filter out unsupported
1479 * extended features. Allow to disable the
1480 * extensions, activation of which requires setting a
1481 * bit in CR4, and which VM monitors do not support.
1482 */
1483 cpu_stdext_disable = 0;
1484 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1485 cpu_stdext_feature &= ~cpu_stdext_disable;
1486
1487 cpu_stdext_feature2 = regs[2];
1488 cpu_stdext_feature3 = regs[3];
1489
1490 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1491 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1492 }
1493 }
1494
1495 /*
1496 * Final stage of CPU identification.
1497 */
1498 void
finishidentcpu(void)1499 finishidentcpu(void)
1500 {
1501 u_int regs[4];
1502 #ifdef __i386__
1503 u_char ccr3;
1504 #endif
1505
1506 cpu_vendor_id = find_cpu_vendor_id();
1507
1508 if (fix_cpuid()) {
1509 do_cpuid(0, regs);
1510 cpu_high = regs[0];
1511 }
1512
1513 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1514 do_cpuid(5, regs);
1515 cpu_mon_mwait_flags = regs[2];
1516 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE;
1517 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE;
1518 }
1519
1520 identify_cpu2();
1521
1522 #ifdef __i386__
1523 if (cpu_high > 0 &&
1524 (cpu_vendor_id == CPU_VENDOR_INTEL ||
1525 cpu_vendor_id == CPU_VENDOR_AMD ||
1526 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1527 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1528 cpu_vendor_id == CPU_VENDOR_NSC)) {
1529 do_cpuid(0x80000000, regs);
1530 if (regs[0] >= 0x80000000)
1531 cpu_exthigh = regs[0];
1532 }
1533 #else
1534 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1535 cpu_vendor_id == CPU_VENDOR_AMD ||
1536 cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1537 do_cpuid(0x80000000, regs);
1538 cpu_exthigh = regs[0];
1539 }
1540 #endif
1541 if (cpu_exthigh >= 0x80000001) {
1542 do_cpuid(0x80000001, regs);
1543 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1544 amd_feature2 = regs[2];
1545 }
1546 if (cpu_exthigh >= 0x80000007) {
1547 do_cpuid(0x80000007, regs);
1548 amd_pminfo = regs[3];
1549 }
1550 if (cpu_exthigh >= 0x80000008) {
1551 do_cpuid(0x80000008, regs);
1552 cpu_maxphyaddr = regs[0] & 0xff;
1553 amd_extended_feature_extensions = regs[1];
1554 cpu_procinfo2 = regs[2];
1555 } else {
1556 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1557 }
1558
1559 #ifdef __i386__
1560 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1561 if (cpu == CPU_486) {
1562 /*
1563 * These conditions are equivalent to:
1564 * - CPU does not support cpuid instruction.
1565 * - Cyrix/IBM CPU is detected.
1566 */
1567 if (identblue() == IDENTBLUE_IBMCPU) {
1568 strcpy(cpu_vendor, "IBM");
1569 cpu_vendor_id = CPU_VENDOR_IBM;
1570 cpu = CPU_BLUE;
1571 return;
1572 }
1573 }
1574 switch (cpu_id & 0xf00) {
1575 case 0x600:
1576 /*
1577 * Cyrix's datasheet does not describe DIRs.
1578 * Therefor, I assume it does not have them
1579 * and use the result of the cpuid instruction.
1580 * XXX they seem to have it for now at least. -Peter
1581 */
1582 identifycyrix();
1583 cpu = CPU_M2;
1584 break;
1585 default:
1586 identifycyrix();
1587 /*
1588 * This routine contains a trick.
1589 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1590 */
1591 switch (cyrix_did & 0x00f0) {
1592 case 0x00:
1593 case 0xf0:
1594 cpu = CPU_486DLC;
1595 break;
1596 case 0x10:
1597 cpu = CPU_CY486DX;
1598 break;
1599 case 0x20:
1600 if ((cyrix_did & 0x000f) < 8)
1601 cpu = CPU_M1;
1602 else
1603 cpu = CPU_M1SC;
1604 break;
1605 case 0x30:
1606 cpu = CPU_M1;
1607 break;
1608 case 0x40:
1609 /* MediaGX CPU */
1610 cpu = CPU_M1SC;
1611 break;
1612 default:
1613 /* M2 and later CPUs are treated as M2. */
1614 cpu = CPU_M2;
1615
1616 /*
1617 * enable cpuid instruction.
1618 */
1619 ccr3 = read_cyrix_reg(CCR3);
1620 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1621 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1622 write_cyrix_reg(CCR3, ccr3);
1623
1624 do_cpuid(0, regs);
1625 cpu_high = regs[0]; /* eax */
1626 do_cpuid(1, regs);
1627 cpu_id = regs[0]; /* eax */
1628 cpu_feature = regs[3]; /* edx */
1629 break;
1630 }
1631 }
1632 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1633 /*
1634 * There are BlueLightning CPUs that do not change
1635 * undefined flags by dividing 5 by 2. In this case,
1636 * the CPU identification routine in locore.s leaves
1637 * cpu_vendor null string and puts CPU_486 into the
1638 * cpu.
1639 */
1640 if (identblue() == IDENTBLUE_IBMCPU) {
1641 strcpy(cpu_vendor, "IBM");
1642 cpu_vendor_id = CPU_VENDOR_IBM;
1643 cpu = CPU_BLUE;
1644 return;
1645 }
1646 }
1647 #endif
1648 }
1649
1650 int
pti_get_default(void)1651 pti_get_default(void)
1652 {
1653
1654 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0)
1655 return (0);
1656 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1657 return (0);
1658 return (1);
1659 }
1660
1661 static u_int
find_cpu_vendor_id(void)1662 find_cpu_vendor_id(void)
1663 {
1664 int i;
1665
1666 for (i = 0; i < nitems(cpu_vendors); i++)
1667 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1668 return (cpu_vendors[i].vendor_id);
1669 return (0);
1670 }
1671
1672 static void
print_AMD_assoc(int i)1673 print_AMD_assoc(int i)
1674 {
1675 if (i == 255)
1676 printf(", fully associative\n");
1677 else
1678 printf(", %d-way associative\n", i);
1679 }
1680
1681 static void
print_AMD_l2_assoc(int i)1682 print_AMD_l2_assoc(int i)
1683 {
1684 switch (i & 0x0f) {
1685 case 0: printf(", disabled/not present\n"); break;
1686 case 1: printf(", direct mapped\n"); break;
1687 case 2: printf(", 2-way associative\n"); break;
1688 case 4: printf(", 4-way associative\n"); break;
1689 case 6: printf(", 8-way associative\n"); break;
1690 case 8: printf(", 16-way associative\n"); break;
1691 case 15: printf(", fully associative\n"); break;
1692 default: printf(", reserved configuration\n"); break;
1693 }
1694 }
1695
1696 static void
print_AMD_info(void)1697 print_AMD_info(void)
1698 {
1699 #ifdef __i386__
1700 uint64_t amd_whcr;
1701 #endif
1702 u_int regs[4];
1703
1704 if (cpu_exthigh >= 0x80000005) {
1705 do_cpuid(0x80000005, regs);
1706 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1707 print_AMD_assoc(regs[0] >> 24);
1708
1709 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1710 print_AMD_assoc((regs[0] >> 8) & 0xff);
1711
1712 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1713 print_AMD_assoc(regs[1] >> 24);
1714
1715 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1716 print_AMD_assoc((regs[1] >> 8) & 0xff);
1717
1718 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1719 printf(", %d bytes/line", regs[2] & 0xff);
1720 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1721 print_AMD_assoc((regs[2] >> 16) & 0xff);
1722
1723 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1724 printf(", %d bytes/line", regs[3] & 0xff);
1725 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1726 print_AMD_assoc((regs[3] >> 16) & 0xff);
1727 }
1728
1729 if (cpu_exthigh >= 0x80000006) {
1730 do_cpuid(0x80000006, regs);
1731 if ((regs[0] >> 16) != 0) {
1732 printf("L2 2MB data TLB: %d entries",
1733 (regs[0] >> 16) & 0xfff);
1734 print_AMD_l2_assoc(regs[0] >> 28);
1735 printf("L2 2MB instruction TLB: %d entries",
1736 regs[0] & 0xfff);
1737 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1738 } else {
1739 printf("L2 2MB unified TLB: %d entries",
1740 regs[0] & 0xfff);
1741 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1742 }
1743 if ((regs[1] >> 16) != 0) {
1744 printf("L2 4KB data TLB: %d entries",
1745 (regs[1] >> 16) & 0xfff);
1746 print_AMD_l2_assoc(regs[1] >> 28);
1747
1748 printf("L2 4KB instruction TLB: %d entries",
1749 (regs[1] >> 16) & 0xfff);
1750 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1751 } else {
1752 printf("L2 4KB unified TLB: %d entries",
1753 (regs[1] >> 16) & 0xfff);
1754 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1755 }
1756 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1757 printf(", %d bytes/line", regs[2] & 0xff);
1758 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1759 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1760 }
1761
1762 #ifdef __i386__
1763 if (((cpu_id & 0xf00) == 0x500)
1764 && (((cpu_id & 0x0f0) > 0x80)
1765 || (((cpu_id & 0x0f0) == 0x80)
1766 && (cpu_id & 0x00f) > 0x07))) {
1767 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1768 amd_whcr = rdmsr(0xc0000082);
1769 if (!(amd_whcr & (0x3ff << 22))) {
1770 printf("Write Allocate Disable\n");
1771 } else {
1772 printf("Write Allocate Enable Limit: %dM bytes\n",
1773 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1774 printf("Write Allocate 15-16M bytes: %s\n",
1775 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1776 }
1777 } else if (((cpu_id & 0xf00) == 0x500)
1778 && ((cpu_id & 0x0f0) > 0x50)) {
1779 /* K6, K6-2(old core) */
1780 amd_whcr = rdmsr(0xc0000082);
1781 if (!(amd_whcr & (0x7f << 1))) {
1782 printf("Write Allocate Disable\n");
1783 } else {
1784 printf("Write Allocate Enable Limit: %dM bytes\n",
1785 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1786 printf("Write Allocate 15-16M bytes: %s\n",
1787 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1788 printf("Hardware Write Allocate Control: %s\n",
1789 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1790 }
1791 }
1792 #endif
1793 /*
1794 * Opteron Rev E shows a bug as in very rare occasions a read memory
1795 * barrier is not performed as expected if it is followed by a
1796 * non-atomic read-modify-write instruction.
1797 * As long as that bug pops up very rarely (intensive machine usage
1798 * on other operating systems generally generates one unexplainable
1799 * crash any 2 months) and as long as a model specific fix would be
1800 * impractical at this stage, print out a warning string if the broken
1801 * model and family are identified.
1802 */
1803 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1804 CPUID_TO_MODEL(cpu_id) <= 0x3f)
1805 printf("WARNING: This architecture revision has known SMP "
1806 "hardware bugs which may cause random instability\n");
1807 }
1808
1809 static void
print_INTEL_info(void)1810 print_INTEL_info(void)
1811 {
1812 u_int regs[4];
1813 u_int rounds, regnum;
1814 u_int nwaycode, nway;
1815
1816 if (cpu_high >= 2) {
1817 rounds = 0;
1818 do {
1819 do_cpuid(0x2, regs);
1820 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1821 break; /* we have a buggy CPU */
1822
1823 for (regnum = 0; regnum <= 3; ++regnum) {
1824 if (regs[regnum] & (1<<31))
1825 continue;
1826 if (regnum != 0)
1827 print_INTEL_TLB(regs[regnum] & 0xff);
1828 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1829 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1830 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1831 }
1832 } while (--rounds > 0);
1833 }
1834
1835 if (cpu_exthigh >= 0x80000006) {
1836 do_cpuid(0x80000006, regs);
1837 nwaycode = (regs[2] >> 12) & 0x0f;
1838 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1839 nway = 1 << (nwaycode / 2);
1840 else
1841 nway = 0;
1842 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1843 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1844 }
1845 }
1846
1847 static void
print_INTEL_TLB(u_int data)1848 print_INTEL_TLB(u_int data)
1849 {
1850 switch (data) {
1851 case 0x0:
1852 case 0x40:
1853 default:
1854 break;
1855 case 0x1:
1856 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1857 break;
1858 case 0x2:
1859 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1860 break;
1861 case 0x3:
1862 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1863 break;
1864 case 0x4:
1865 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1866 break;
1867 case 0x6:
1868 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1869 break;
1870 case 0x8:
1871 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1872 break;
1873 case 0x9:
1874 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1875 break;
1876 case 0xa:
1877 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1878 break;
1879 case 0xb:
1880 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1881 break;
1882 case 0xc:
1883 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1884 break;
1885 case 0xd:
1886 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1887 break;
1888 case 0xe:
1889 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1890 break;
1891 case 0x1d:
1892 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1893 break;
1894 case 0x21:
1895 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1896 break;
1897 case 0x22:
1898 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1899 break;
1900 case 0x23:
1901 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1902 break;
1903 case 0x24:
1904 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
1905 break;
1906 case 0x25:
1907 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1908 break;
1909 case 0x29:
1910 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1911 break;
1912 case 0x2c:
1913 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1914 break;
1915 case 0x30:
1916 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1917 break;
1918 case 0x39: /* De-listed in SDM rev. 54 */
1919 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1920 break;
1921 case 0x3b: /* De-listed in SDM rev. 54 */
1922 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
1923 break;
1924 case 0x3c: /* De-listed in SDM rev. 54 */
1925 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1926 break;
1927 case 0x41:
1928 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
1929 break;
1930 case 0x42:
1931 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
1932 break;
1933 case 0x43:
1934 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
1935 break;
1936 case 0x44:
1937 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
1938 break;
1939 case 0x45:
1940 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
1941 break;
1942 case 0x46:
1943 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
1944 break;
1945 case 0x47:
1946 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
1947 break;
1948 case 0x48:
1949 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
1950 break;
1951 case 0x49:
1952 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
1953 CPUID_TO_MODEL(cpu_id) == 0x6)
1954 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
1955 else
1956 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
1957 break;
1958 case 0x4a:
1959 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
1960 break;
1961 case 0x4b:
1962 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
1963 break;
1964 case 0x4c:
1965 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
1966 break;
1967 case 0x4d:
1968 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
1969 break;
1970 case 0x4e:
1971 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
1972 break;
1973 case 0x4f:
1974 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
1975 break;
1976 case 0x50:
1977 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
1978 break;
1979 case 0x51:
1980 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
1981 break;
1982 case 0x52:
1983 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
1984 break;
1985 case 0x55:
1986 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
1987 break;
1988 case 0x56:
1989 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
1990 break;
1991 case 0x57:
1992 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
1993 break;
1994 case 0x59:
1995 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
1996 break;
1997 case 0x5a:
1998 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
1999 break;
2000 case 0x5b:
2001 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
2002 break;
2003 case 0x5c:
2004 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2005 break;
2006 case 0x5d:
2007 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2008 break;
2009 case 0x60:
2010 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2011 break;
2012 case 0x61:
2013 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2014 break;
2015 case 0x63:
2016 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2017 break;
2018 case 0x64:
2019 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2020 break;
2021 case 0x66:
2022 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2023 break;
2024 case 0x67:
2025 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2026 break;
2027 case 0x68:
2028 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2029 break;
2030 case 0x6a:
2031 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2032 break;
2033 case 0x6b:
2034 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2035 break;
2036 case 0x6c:
2037 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2038 break;
2039 case 0x6d:
2040 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2041 break;
2042 case 0x70:
2043 printf("Trace cache: 12K-uops, 8-way set associative\n");
2044 break;
2045 case 0x71:
2046 printf("Trace cache: 16K-uops, 8-way set associative\n");
2047 break;
2048 case 0x72:
2049 printf("Trace cache: 32K-uops, 8-way set associative\n");
2050 break;
2051 case 0x76:
2052 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2053 break;
2054 case 0x78:
2055 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2056 break;
2057 case 0x79:
2058 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2059 break;
2060 case 0x7a:
2061 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2062 break;
2063 case 0x7b:
2064 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2065 break;
2066 case 0x7c:
2067 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2068 break;
2069 case 0x7d:
2070 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2071 break;
2072 case 0x7f:
2073 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2074 break;
2075 case 0x80:
2076 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2077 break;
2078 case 0x82:
2079 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2080 break;
2081 case 0x83:
2082 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2083 break;
2084 case 0x84:
2085 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2086 break;
2087 case 0x85:
2088 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2089 break;
2090 case 0x86:
2091 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2092 break;
2093 case 0x87:
2094 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2095 break;
2096 case 0xa0:
2097 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2098 break;
2099 case 0xb0:
2100 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2101 break;
2102 case 0xb1:
2103 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2104 break;
2105 case 0xb2:
2106 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2107 break;
2108 case 0xb3:
2109 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2110 break;
2111 case 0xb4:
2112 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2113 break;
2114 case 0xb5:
2115 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2116 break;
2117 case 0xb6:
2118 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2119 break;
2120 case 0xba:
2121 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2122 break;
2123 case 0xc0:
2124 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2125 break;
2126 case 0xc1:
2127 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2128 break;
2129 case 0xc2:
2130 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2131 break;
2132 case 0xc3:
2133 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2134 break;
2135 case 0xc4:
2136 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2137 break;
2138 case 0xca:
2139 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2140 break;
2141 case 0xd0:
2142 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2143 break;
2144 case 0xd1:
2145 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2146 break;
2147 case 0xd2:
2148 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2149 break;
2150 case 0xd6:
2151 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2152 break;
2153 case 0xd7:
2154 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2155 break;
2156 case 0xd8:
2157 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2158 break;
2159 case 0xdc:
2160 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2161 break;
2162 case 0xdd:
2163 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2164 break;
2165 case 0xde:
2166 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2167 break;
2168 case 0xe2:
2169 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2170 break;
2171 case 0xe3:
2172 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2173 break;
2174 case 0xe4:
2175 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2176 break;
2177 case 0xea:
2178 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2179 break;
2180 case 0xeb:
2181 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2182 break;
2183 case 0xec:
2184 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2185 break;
2186 case 0xf0:
2187 printf("64-Byte prefetching\n");
2188 break;
2189 case 0xf1:
2190 printf("128-Byte prefetching\n");
2191 break;
2192 }
2193 }
2194
2195 static void
print_svm_info(void)2196 print_svm_info(void)
2197 {
2198 u_int features, regs[4];
2199 uint64_t msr;
2200 int comma;
2201
2202 printf("\n SVM: ");
2203 do_cpuid(0x8000000A, regs);
2204 features = regs[3];
2205
2206 msr = rdmsr(MSR_VM_CR);
2207 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2208 printf("(disabled in BIOS) ");
2209
2210 if (!bootverbose) {
2211 comma = 0;
2212 if (features & (1 << 0)) {
2213 printf("%sNP", comma ? "," : "");
2214 comma = 1;
2215 }
2216 if (features & (1 << 3)) {
2217 printf("%sNRIP", comma ? "," : "");
2218 comma = 1;
2219 }
2220 if (features & (1 << 5)) {
2221 printf("%sVClean", comma ? "," : "");
2222 comma = 1;
2223 }
2224 if (features & (1 << 6)) {
2225 printf("%sAFlush", comma ? "," : "");
2226 comma = 1;
2227 }
2228 if (features & (1 << 7)) {
2229 printf("%sDAssist", comma ? "," : "");
2230 comma = 1;
2231 }
2232 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2233 return;
2234 }
2235
2236 printf("Features=0x%b", features,
2237 "\020"
2238 "\001NP" /* Nested paging */
2239 "\002LbrVirt" /* LBR virtualization */
2240 "\003SVML" /* SVM lock */
2241 "\004NRIPS" /* NRIP save */
2242 "\005TscRateMsr" /* MSR based TSC rate control */
2243 "\006VmcbClean" /* VMCB clean bits */
2244 "\007FlushByAsid" /* Flush by ASID */
2245 "\010DecodeAssist" /* Decode assist */
2246 "\011<b8>"
2247 "\012<b9>"
2248 "\013PauseFilter" /* PAUSE intercept filter */
2249 "\014<b11>"
2250 "\015PauseFilterThreshold" /* PAUSE filter threshold */
2251 "\016AVIC" /* virtual interrupt controller */
2252 );
2253 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2254 }
2255
2256 #ifdef __i386__
2257 static void
print_transmeta_info(void)2258 print_transmeta_info(void)
2259 {
2260 u_int regs[4], nreg = 0;
2261
2262 do_cpuid(0x80860000, regs);
2263 nreg = regs[0];
2264 if (nreg >= 0x80860001) {
2265 do_cpuid(0x80860001, regs);
2266 printf(" Processor revision %u.%u.%u.%u\n",
2267 (regs[1] >> 24) & 0xff,
2268 (regs[1] >> 16) & 0xff,
2269 (regs[1] >> 8) & 0xff,
2270 regs[1] & 0xff);
2271 }
2272 if (nreg >= 0x80860002) {
2273 do_cpuid(0x80860002, regs);
2274 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
2275 (regs[1] >> 24) & 0xff,
2276 (regs[1] >> 16) & 0xff,
2277 (regs[1] >> 8) & 0xff,
2278 regs[1] & 0xff,
2279 regs[2]);
2280 }
2281 if (nreg >= 0x80860006) {
2282 char info[65];
2283 do_cpuid(0x80860003, (u_int*) &info[0]);
2284 do_cpuid(0x80860004, (u_int*) &info[16]);
2285 do_cpuid(0x80860005, (u_int*) &info[32]);
2286 do_cpuid(0x80860006, (u_int*) &info[48]);
2287 info[64] = 0;
2288 printf(" %s\n", info);
2289 }
2290 }
2291 #endif
2292
2293 static void
print_via_padlock_info(void)2294 print_via_padlock_info(void)
2295 {
2296 u_int regs[4];
2297
2298 do_cpuid(0xc0000001, regs);
2299 printf("\n VIA Padlock Features=0x%b", regs[3],
2300 "\020"
2301 "\003RNG" /* RNG */
2302 "\007AES" /* ACE */
2303 "\011AES-CTR" /* ACE2 */
2304 "\013SHA1,SHA256" /* PHE */
2305 "\015RSA" /* PMM */
2306 );
2307 }
2308
2309 static uint32_t
vmx_settable(uint64_t basic,int msr,int true_msr)2310 vmx_settable(uint64_t basic, int msr, int true_msr)
2311 {
2312 uint64_t val;
2313
2314 if (basic & (1ULL << 55))
2315 val = rdmsr(true_msr);
2316 else
2317 val = rdmsr(msr);
2318
2319 /* Just report the controls that can be set to 1. */
2320 return (val >> 32);
2321 }
2322
2323 static void
print_vmx_info(void)2324 print_vmx_info(void)
2325 {
2326 uint64_t basic, msr;
2327 uint32_t entry, exit, mask, pin, proc, proc2;
2328 int comma;
2329
2330 printf("\n VT-x: ");
2331 msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2332 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2333 printf("(disabled in BIOS) ");
2334 basic = rdmsr(MSR_VMX_BASIC);
2335 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2336 MSR_VMX_TRUE_PINBASED_CTLS);
2337 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2338 MSR_VMX_TRUE_PROCBASED_CTLS);
2339 if (proc & PROCBASED_SECONDARY_CONTROLS)
2340 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2341 MSR_VMX_PROCBASED_CTLS2);
2342 else
2343 proc2 = 0;
2344 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2345 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2346
2347 if (!bootverbose) {
2348 comma = 0;
2349 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2350 entry & VM_ENTRY_LOAD_PAT) {
2351 printf("%sPAT", comma ? "," : "");
2352 comma = 1;
2353 }
2354 if (proc & PROCBASED_HLT_EXITING) {
2355 printf("%sHLT", comma ? "," : "");
2356 comma = 1;
2357 }
2358 if (proc & PROCBASED_MTF) {
2359 printf("%sMTF", comma ? "," : "");
2360 comma = 1;
2361 }
2362 if (proc & PROCBASED_PAUSE_EXITING) {
2363 printf("%sPAUSE", comma ? "," : "");
2364 comma = 1;
2365 }
2366 if (proc2 & PROCBASED2_ENABLE_EPT) {
2367 printf("%sEPT", comma ? "," : "");
2368 comma = 1;
2369 }
2370 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2371 printf("%sUG", comma ? "," : "");
2372 comma = 1;
2373 }
2374 if (proc2 & PROCBASED2_ENABLE_VPID) {
2375 printf("%sVPID", comma ? "," : "");
2376 comma = 1;
2377 }
2378 if (proc & PROCBASED_USE_TPR_SHADOW &&
2379 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2380 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2381 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2382 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2383 printf("%sVID", comma ? "," : "");
2384 comma = 1;
2385 if (pin & PINBASED_POSTED_INTERRUPT)
2386 printf(",PostIntr");
2387 }
2388 return;
2389 }
2390
2391 mask = basic >> 32;
2392 printf("Basic Features=0x%b", mask,
2393 "\020"
2394 "\02132PA" /* 32-bit physical addresses */
2395 "\022SMM" /* SMM dual-monitor */
2396 "\027INS/OUTS" /* VM-exit info for INS and OUTS */
2397 "\030TRUE" /* TRUE_CTLS MSRs */
2398 );
2399 printf("\n Pin-Based Controls=0x%b", pin,
2400 "\020"
2401 "\001ExtINT" /* External-interrupt exiting */
2402 "\004NMI" /* NMI exiting */
2403 "\006VNMI" /* Virtual NMIs */
2404 "\007PreTmr" /* Activate VMX-preemption timer */
2405 "\010PostIntr" /* Process posted interrupts */
2406 );
2407 printf("\n Primary Processor Controls=0x%b", proc,
2408 "\020"
2409 "\003INTWIN" /* Interrupt-window exiting */
2410 "\004TSCOff" /* Use TSC offsetting */
2411 "\010HLT" /* HLT exiting */
2412 "\012INVLPG" /* INVLPG exiting */
2413 "\013MWAIT" /* MWAIT exiting */
2414 "\014RDPMC" /* RDPMC exiting */
2415 "\015RDTSC" /* RDTSC exiting */
2416 "\020CR3-LD" /* CR3-load exiting */
2417 "\021CR3-ST" /* CR3-store exiting */
2418 "\024CR8-LD" /* CR8-load exiting */
2419 "\025CR8-ST" /* CR8-store exiting */
2420 "\026TPR" /* Use TPR shadow */
2421 "\027NMIWIN" /* NMI-window exiting */
2422 "\030MOV-DR" /* MOV-DR exiting */
2423 "\031IO" /* Unconditional I/O exiting */
2424 "\032IOmap" /* Use I/O bitmaps */
2425 "\034MTF" /* Monitor trap flag */
2426 "\035MSRmap" /* Use MSR bitmaps */
2427 "\036MONITOR" /* MONITOR exiting */
2428 "\037PAUSE" /* PAUSE exiting */
2429 );
2430 if (proc & PROCBASED_SECONDARY_CONTROLS)
2431 printf("\n Secondary Processor Controls=0x%b", proc2,
2432 "\020"
2433 "\001APIC" /* Virtualize APIC accesses */
2434 "\002EPT" /* Enable EPT */
2435 "\003DT" /* Descriptor-table exiting */
2436 "\004RDTSCP" /* Enable RDTSCP */
2437 "\005x2APIC" /* Virtualize x2APIC mode */
2438 "\006VPID" /* Enable VPID */
2439 "\007WBINVD" /* WBINVD exiting */
2440 "\010UG" /* Unrestricted guest */
2441 "\011APIC-reg" /* APIC-register virtualization */
2442 "\012VID" /* Virtual-interrupt delivery */
2443 "\013PAUSE-loop" /* PAUSE-loop exiting */
2444 "\014RDRAND" /* RDRAND exiting */
2445 "\015INVPCID" /* Enable INVPCID */
2446 "\016VMFUNC" /* Enable VM functions */
2447 "\017VMCS" /* VMCS shadowing */
2448 "\020EPT#VE" /* EPT-violation #VE */
2449 "\021XSAVES" /* Enable XSAVES/XRSTORS */
2450 );
2451 printf("\n Exit Controls=0x%b", mask,
2452 "\020"
2453 "\003DR" /* Save debug controls */
2454 /* Ignore Host address-space size */
2455 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2456 "\020AckInt" /* Acknowledge interrupt on exit */
2457 "\023PAT-SV" /* Save MSR_PAT */
2458 "\024PAT-LD" /* Load MSR_PAT */
2459 "\025EFER-SV" /* Save MSR_EFER */
2460 "\026EFER-LD" /* Load MSR_EFER */
2461 "\027PTMR-SV" /* Save VMX-preemption timer value */
2462 );
2463 printf("\n Entry Controls=0x%b", mask,
2464 "\020"
2465 "\003DR" /* Save debug controls */
2466 /* Ignore IA-32e mode guest */
2467 /* Ignore Entry to SMM */
2468 /* Ignore Deactivate dual-monitor treatment */
2469 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2470 "\017PAT" /* Load MSR_PAT */
2471 "\020EFER" /* Load MSR_EFER */
2472 );
2473 if (proc & PROCBASED_SECONDARY_CONTROLS &&
2474 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2475 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2476 mask = msr;
2477 printf("\n EPT Features=0x%b", mask,
2478 "\020"
2479 "\001XO" /* Execute-only translations */
2480 "\007PW4" /* Page-walk length of 4 */
2481 "\011UC" /* EPT paging-structure mem can be UC */
2482 "\017WB" /* EPT paging-structure mem can be WB */
2483 "\0212M" /* EPT PDE can map a 2-Mbyte page */
2484 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */
2485 "\025INVEPT" /* INVEPT is supported */
2486 "\026AD" /* Accessed and dirty flags for EPT */
2487 "\032single" /* INVEPT single-context type */
2488 "\033all" /* INVEPT all-context type */
2489 );
2490 mask = msr >> 32;
2491 printf("\n VPID Features=0x%b", mask,
2492 "\020"
2493 "\001INVVPID" /* INVVPID is supported */
2494 "\011individual" /* INVVPID individual-address type */
2495 "\012single" /* INVVPID single-context type */
2496 "\013all" /* INVVPID all-context type */
2497 /* INVVPID single-context-retaining-globals type */
2498 "\014single-globals"
2499 );
2500 }
2501 }
2502
2503 static void
print_hypervisor_info(void)2504 print_hypervisor_info(void)
2505 {
2506
2507 if (*hv_vendor)
2508 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2509 }
2510