1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008, 2014 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 */
36
37 #ifndef MLX4_H
38 #define MLX4_H
39
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/rbtree.h>
43 #include <linux/timer.h>
44 #include <linux/semaphore.h>
45 #include <linux/workqueue.h>
46 #include <linux/device.h>
47 #include <linux/mlx4/device.h>
48 #include <linux/mlx4/driver.h>
49 #include <linux/mlx4/doorbell.h>
50 #include <linux/mlx4/cmd.h>
51
52 #define DRV_NAME "mlx4_core"
53 #define PFX DRV_NAME ": "
54 #define DRV_VERSION "2.1"
55 #define DRV_RELDATE __DATE__
56
57 #define DRV_STACK_NAME "Linux-MLNX_OFED"
58 #define DRV_STACK_VERSION "2.1"
59 #define DRV_NAME_FOR_FW DRV_STACK_NAME","DRV_STACK_VERSION
60
61 #define MLX4_FS_UDP_UC_EN (1 << 1)
62 #define MLX4_FS_TCP_UC_EN (1 << 2)
63 #define MLX4_FS_NUM_OF_L2_ADDR 8
64 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
65 #define MLX4_FS_NUM_MCG (1 << 17)
66
67 struct mlx4_set_port_prio2tc_context {
68 u8 prio2tc[4];
69 };
70
71 struct mlx4_port_scheduler_tc_cfg_be {
72 __be16 pg;
73 __be16 bw_precentage;
74 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
75 __be16 max_bw_value;
76 };
77
78 struct mlx4_set_port_scheduler_context {
79 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
80 };
81
82 enum {
83 MLX4_HCR_BASE = 0x80680,
84 MLX4_HCR_SIZE = 0x0001c,
85 MLX4_CLR_INT_SIZE = 0x00008,
86 MLX4_SLAVE_COMM_BASE = 0x0,
87 MLX4_COMM_PAGESIZE = 0x1000,
88 MLX4_CLOCK_SIZE = 0x00008
89 };
90
91 enum {
92 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
93 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
94 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
95 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE)/16 - 2),
96 };
97
98 enum {
99 MLX4_NUM_PDS = 1 << 15
100 };
101
102 enum {
103 MLX4_CMPT_TYPE_QP = 0,
104 MLX4_CMPT_TYPE_SRQ = 1,
105 MLX4_CMPT_TYPE_CQ = 2,
106 MLX4_CMPT_TYPE_EQ = 3,
107 MLX4_CMPT_NUM_TYPE
108 };
109
110 enum {
111 MLX4_CMPT_SHIFT = 24,
112 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
113 };
114
115 enum mlx4_mpt_state {
116 MLX4_MPT_DISABLED = 0,
117 MLX4_MPT_EN_HW,
118 MLX4_MPT_EN_SW
119 };
120
121 #define MLX4_COMM_TIME 10000
122 enum {
123 MLX4_COMM_CMD_RESET,
124 MLX4_COMM_CMD_VHCR0,
125 MLX4_COMM_CMD_VHCR1,
126 MLX4_COMM_CMD_VHCR2,
127 MLX4_COMM_CMD_VHCR_EN,
128 MLX4_COMM_CMD_VHCR_POST,
129 MLX4_COMM_CMD_FLR = 254
130 };
131
132 /*The flag indicates that the slave should delay the RESET cmd*/
133 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
134 /*indicates how many retries will be done if we are in the middle of FLR*/
135 #define NUM_OF_RESET_RETRIES 10
136 #define SLEEP_TIME_IN_RESET (2 * 1000)
137 enum mlx4_resource {
138 RES_QP,
139 RES_CQ,
140 RES_SRQ,
141 RES_XRCD,
142 RES_MPT,
143 RES_MTT,
144 RES_MAC,
145 RES_VLAN,
146 RES_NPORT_ID,
147 RES_COUNTER,
148 RES_FS_RULE,
149 RES_EQ,
150 MLX4_NUM_OF_RESOURCE_TYPE
151 };
152
153 enum mlx4_alloc_mode {
154 RES_OP_RESERVE,
155 RES_OP_RESERVE_AND_MAP,
156 RES_OP_MAP_ICM,
157 };
158
159 enum mlx4_res_tracker_free_type {
160 RES_TR_FREE_ALL,
161 RES_TR_FREE_SLAVES_ONLY,
162 RES_TR_FREE_STRUCTS_ONLY,
163 };
164
165 /*
166 *Virtual HCR structures.
167 * mlx4_vhcr is the sw representation, in machine endianess
168 *
169 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
170 * to FW to go through communication channel.
171 * It is big endian, and has the same structure as the physical HCR
172 * used by command interface
173 */
174 struct mlx4_vhcr {
175 u64 in_param;
176 u64 out_param;
177 u32 in_modifier;
178 u32 errno;
179 u16 op;
180 u16 token;
181 u8 op_modifier;
182 u8 e_bit;
183 };
184
185 struct mlx4_vhcr_cmd {
186 __be64 in_param;
187 __be32 in_modifier;
188 u32 reserved1;
189 __be64 out_param;
190 __be16 token;
191 u16 reserved;
192 u8 status;
193 u8 flags;
194 __be16 opcode;
195 } __packed;
196
197 struct mlx4_cmd_info {
198 u16 opcode;
199 bool has_inbox;
200 bool has_outbox;
201 bool out_is_imm;
202 bool encode_slave_id;
203 bool skip_err_print;
204 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
205 struct mlx4_cmd_mailbox *inbox);
206 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
207 struct mlx4_cmd_mailbox *inbox,
208 struct mlx4_cmd_mailbox *outbox,
209 struct mlx4_cmd_info *cmd);
210 };
211
212 enum {
213 MLX4_DEBUG_MASK_CMD_TIME = 0x100,
214 };
215
216 #ifdef CONFIG_MLX4_DEBUG
217 extern int mlx4_debug_level;
218 #else /* CONFIG_MLX4_DEBUG */
219 #define mlx4_debug_level (0)
220 #endif /* CONFIG_MLX4_DEBUG */
221
222 #define mlx4_dbg(mdev, format, arg...) \
223 do { \
224 if (mlx4_debug_level) \
225 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
226 } while (0)
227
228 #define mlx4_err(mdev, format, arg...) \
229 dev_err(&mdev->pdev->dev, format, ##arg)
230 #define mlx4_info(mdev, format, arg...) \
231 dev_info(&mdev->pdev->dev, format, ##arg)
232 #define mlx4_warn(mdev, format, arg...) \
233 dev_warn(&mdev->pdev->dev, format, ##arg)
234
235 extern int mlx4_log_num_mgm_entry_size;
236 extern int log_mtts_per_seg;
237 extern int mlx4_blck_lb;
238 extern int mlx4_set_4k_mtu;
239
240 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
241 #define ALL_SLAVES 0xff
242
243 struct mlx4_bitmap {
244 u32 last;
245 u32 top;
246 u32 max;
247 u32 reserved_top;
248 u32 mask;
249 u32 avail;
250 spinlock_t lock;
251 unsigned long *table;
252 };
253
254 struct mlx4_buddy {
255 unsigned long **bits;
256 unsigned int *num_free;
257 u32 max_order;
258 spinlock_t lock;
259 };
260
261 struct mlx4_icm;
262
263 struct mlx4_icm_table {
264 u64 virt;
265 int num_icm;
266 u32 num_obj;
267 int obj_size;
268 int lowmem;
269 int coherent;
270 struct mutex mutex;
271 struct mlx4_icm **icm;
272 };
273
274 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
275 #define MLX4_MPT_FLAG_FREE (0x3UL << 28)
276 #define MLX4_MPT_FLAG_MIO (1 << 17)
277 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
278 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
279 #define MLX4_MPT_FLAG_REGION (1 << 8)
280
281 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
282 #define MLX4_MPT_PD_FLAG_RAE (1 << 28)
283 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
284
285 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7)
286
287 #define MLX4_MPT_STATUS_SW 0xF0
288 #define MLX4_MPT_STATUS_HW 0x00
289
290 /*
291 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
292 */
293 struct mlx4_mpt_entry {
294 __be32 flags;
295 __be32 qpn;
296 __be32 key;
297 __be32 pd_flags;
298 __be64 start;
299 __be64 length;
300 __be32 lkey;
301 __be32 win_cnt;
302 u8 reserved1[3];
303 u8 mtt_rep;
304 __be64 mtt_addr;
305 __be32 mtt_sz;
306 __be32 entity_size;
307 __be32 first_byte_offset;
308 } __packed;
309
310 /*
311 * Must be packed because start is 64 bits but only aligned to 32 bits.
312 */
313 struct mlx4_eq_context {
314 __be32 flags;
315 u16 reserved1[3];
316 __be16 page_offset;
317 u8 log_eq_size;
318 u8 reserved2[4];
319 u8 eq_period;
320 u8 reserved3;
321 u8 eq_max_count;
322 u8 reserved4[3];
323 u8 intr;
324 u8 log_page_size;
325 u8 reserved5[2];
326 u8 mtt_base_addr_h;
327 __be32 mtt_base_addr_l;
328 u32 reserved6[2];
329 __be32 consumer_index;
330 __be32 producer_index;
331 u32 reserved7[4];
332 };
333
334 struct mlx4_cq_context {
335 __be32 flags;
336 u16 reserved1[3];
337 __be16 page_offset;
338 __be32 logsize_usrpage;
339 __be16 cq_period;
340 __be16 cq_max_count;
341 u8 reserved2[3];
342 u8 comp_eqn;
343 u8 log_page_size;
344 u8 reserved3[2];
345 u8 mtt_base_addr_h;
346 __be32 mtt_base_addr_l;
347 __be32 last_notified_index;
348 __be32 solicit_producer_index;
349 __be32 consumer_index;
350 __be32 producer_index;
351 u32 reserved4[2];
352 __be64 db_rec_addr;
353 };
354
355 struct mlx4_srq_context {
356 __be32 state_logsize_srqn;
357 u8 logstride;
358 u8 reserved1;
359 __be16 xrcd;
360 __be32 pg_offset_cqn;
361 u32 reserved2;
362 u8 log_page_size;
363 u8 reserved3[2];
364 u8 mtt_base_addr_h;
365 __be32 mtt_base_addr_l;
366 __be32 pd;
367 __be16 limit_watermark;
368 __be16 wqe_cnt;
369 u16 reserved4;
370 __be16 wqe_counter;
371 u32 reserved5;
372 __be64 db_rec_addr;
373 };
374
375 struct mlx4_eq {
376 struct mlx4_dev *dev;
377 void __iomem *doorbell;
378 int eqn;
379 u32 cons_index;
380 u16 irq;
381 u16 have_irq;
382 int nent;
383 struct mlx4_buf_list *page_list;
384 struct mlx4_mtt mtt;
385 };
386
387 struct mlx4_slave_eqe {
388 u8 type;
389 u8 port;
390 u32 param;
391 };
392
393 struct mlx4_slave_event_eq_info {
394 int eqn;
395 u16 token;
396 };
397
398 struct mlx4_profile {
399 int num_qp;
400 int rdmarc_per_qp;
401 int num_srq;
402 int num_cq;
403 int num_mcg;
404 int num_mpt;
405 unsigned num_mtt_segs;
406 };
407
408 struct mlx4_fw {
409 u64 clr_int_base;
410 u64 catas_offset;
411 u64 comm_base;
412 u64 clock_offset;
413 struct mlx4_icm *fw_icm;
414 struct mlx4_icm *aux_icm;
415 u32 catas_size;
416 u16 fw_pages;
417 u8 clr_int_bar;
418 u8 catas_bar;
419 u8 comm_bar;
420 u8 clock_bar;
421 };
422
423 struct mlx4_comm {
424 u32 slave_write;
425 u32 slave_read;
426 };
427
428 enum {
429 MLX4_MCAST_CONFIG = 0,
430 MLX4_MCAST_DISABLE = 1,
431 MLX4_MCAST_ENABLE = 2,
432 };
433
434 #define VLAN_FLTR_SIZE 128
435
436 struct mlx4_vlan_fltr {
437 __be32 entry[VLAN_FLTR_SIZE];
438 };
439
440 struct mlx4_mcast_entry {
441 struct list_head list;
442 u64 addr;
443 };
444
445 struct mlx4_promisc_qp {
446 struct list_head list;
447 u32 qpn;
448 };
449
450 struct mlx4_steer_index {
451 struct list_head list;
452 unsigned int index;
453 struct list_head duplicates;
454 };
455
456 #define MLX4_EVENT_TYPES_NUM 64
457
458 struct mlx4_slave_state {
459 u8 comm_toggle;
460 u8 last_cmd;
461 u8 init_port_mask;
462 bool active;
463 bool old_vlan_api;
464 u8 function;
465 dma_addr_t vhcr_dma;
466 u16 mtu[MLX4_MAX_PORTS + 1];
467 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
468 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
469 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
470 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
471 /* event type to eq number lookup */
472 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
473 u16 eq_pi;
474 u16 eq_ci;
475 spinlock_t lock;
476 /*initialized via the kzalloc*/
477 u8 is_slave_going_down;
478 u32 cookie;
479 enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
480 };
481
482 #define MLX4_VGT 4095
483 #define NO_INDX (-1)
484
485
486 struct mlx4_vport_state {
487 u64 mac;
488 u16 default_vlan;
489 u8 default_qos;
490 u32 tx_rate;
491 bool spoofchk;
492 u32 link_state;
493 };
494
495 struct mlx4_vf_admin_state {
496 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
497 };
498
499 struct mlx4_vport_oper_state {
500 struct mlx4_vport_state state;
501 int mac_idx;
502 int vlan_idx;
503 };
504 struct mlx4_vf_oper_state {
505 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
506 };
507
508 struct slave_list {
509 struct mutex mutex;
510 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
511 };
512
513 struct resource_allocator {
514 spinlock_t alloc_lock;
515 union {
516 int res_reserved;
517 int res_port_rsvd[MLX4_MAX_PORTS];
518 };
519 union {
520 int res_free;
521 int res_port_free[MLX4_MAX_PORTS];
522 };
523 int *quota;
524 int *allocated;
525 int *guaranteed;
526 };
527
528 struct mlx4_resource_tracker {
529 spinlock_t lock;
530 /* tree for each resources */
531 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
532 /* num_of_slave's lists, one per slave */
533 struct slave_list *slave_list;
534 struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE];
535 };
536
537 #define SLAVE_EVENT_EQ_SIZE 128
538 struct mlx4_slave_event_eq {
539 u32 eqn;
540 u32 cons;
541 u32 prod;
542 spinlock_t event_lock;
543 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
544 };
545
546 struct mlx4_master_qp0_state {
547 int proxy_qp0_active;
548 int qp0_active;
549 int port_active;
550 };
551
552 struct mlx4_mfunc_master_ctx {
553 struct mlx4_slave_state *slave_state;
554 struct mlx4_vf_admin_state *vf_admin;
555 struct mlx4_vf_oper_state *vf_oper;
556 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
557 int init_port_ref[MLX4_MAX_PORTS + 1];
558 u16 max_mtu[MLX4_MAX_PORTS + 1];
559 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
560 struct mlx4_resource_tracker res_tracker;
561 struct workqueue_struct *comm_wq;
562 struct work_struct comm_work;
563 struct work_struct arm_comm_work;
564 struct work_struct slave_event_work;
565 struct work_struct slave_flr_event_work;
566 spinlock_t slave_state_lock;
567 __be32 comm_arm_bit_vector[4];
568 struct mlx4_eqe cmd_eqe;
569 struct mlx4_slave_event_eq slave_eq;
570 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
571 };
572
573 struct mlx4_mfunc {
574 struct mlx4_comm __iomem *comm;
575 struct mlx4_vhcr_cmd *vhcr;
576 dma_addr_t vhcr_dma;
577
578 struct mlx4_mfunc_master_ctx master;
579 };
580
581 #define MGM_QPN_MASK 0x00FFFFFF
582 #define MGM_BLCK_LB_BIT 30
583
584 struct mlx4_mgm {
585 __be32 next_gid_index;
586 __be32 members_count;
587 u32 reserved[2];
588 u8 gid[16];
589 __be32 qp[MLX4_MAX_QP_PER_MGM];
590 };
591
592 struct mlx4_cmd {
593 struct pci_pool *pool;
594 void __iomem *hcr;
595 struct mutex hcr_mutex;
596 struct mutex slave_cmd_mutex;
597 struct semaphore poll_sem;
598 struct semaphore event_sem;
599 int max_cmds;
600 spinlock_t context_lock;
601 int free_head;
602 struct mlx4_cmd_context *context;
603 u16 token_mask;
604 u8 use_events;
605 u8 toggle;
606 u8 comm_toggle;
607 };
608
609 enum {
610 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0,
611 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1,
612 };
613 struct mlx4_vf_immed_vlan_work {
614 struct work_struct work;
615 struct mlx4_priv *priv;
616 int flags;
617 int slave;
618 int vlan_ix;
619 int orig_vlan_ix;
620 u8 port;
621 u8 qos;
622 u16 vlan_id;
623 u16 orig_vlan_id;
624 };
625
626
627 struct mlx4_uar_table {
628 struct mlx4_bitmap bitmap;
629 };
630
631 struct mlx4_mr_table {
632 struct mlx4_bitmap mpt_bitmap;
633 struct mlx4_buddy mtt_buddy;
634 u64 mtt_base;
635 u64 mpt_base;
636 struct mlx4_icm_table mtt_table;
637 struct mlx4_icm_table dmpt_table;
638 };
639
640 struct mlx4_cq_table {
641 struct mlx4_bitmap bitmap;
642 spinlock_t lock;
643 rwlock_t cq_table_lock;
644 struct radix_tree_root tree;
645 struct mlx4_icm_table table;
646 struct mlx4_icm_table cmpt_table;
647 };
648
649 struct mlx4_eq_table {
650 struct mlx4_bitmap bitmap;
651 char *irq_names;
652 void __iomem *clr_int;
653 void __iomem **uar_map;
654 u32 clr_mask;
655 struct mlx4_eq *eq;
656 struct mlx4_icm_table table;
657 struct mlx4_icm_table cmpt_table;
658 int have_irq;
659 u8 inta_pin;
660 };
661
662 struct mlx4_srq_table {
663 struct mlx4_bitmap bitmap;
664 spinlock_t lock;
665 struct radix_tree_root tree;
666 struct mlx4_icm_table table;
667 struct mlx4_icm_table cmpt_table;
668 };
669
670 struct mlx4_qp_table {
671 struct mlx4_bitmap bitmap;
672 u32 rdmarc_base;
673 int rdmarc_shift;
674 spinlock_t lock;
675 struct mlx4_icm_table qp_table;
676 struct mlx4_icm_table auxc_table;
677 struct mlx4_icm_table altc_table;
678 struct mlx4_icm_table rdmarc_table;
679 struct mlx4_icm_table cmpt_table;
680 };
681
682 struct mlx4_mcg_table {
683 struct mutex mutex;
684 struct mlx4_bitmap bitmap;
685 struct mlx4_icm_table table;
686 };
687
688 struct mlx4_catas_err {
689 u32 __iomem *map;
690 struct timer_list timer;
691 struct list_head list;
692 };
693
694 #define MLX4_MAX_MAC_NUM 128
695 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
696
697 struct mlx4_mac_table {
698 __be64 entries[MLX4_MAX_MAC_NUM];
699 int refs[MLX4_MAX_MAC_NUM];
700 struct mutex mutex;
701 int total;
702 int max;
703 };
704
705 #define MLX4_MAX_VLAN_NUM 128
706 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
707
708 struct mlx4_vlan_table {
709 __be32 entries[MLX4_MAX_VLAN_NUM];
710 int refs[MLX4_MAX_VLAN_NUM];
711 struct mutex mutex;
712 int total;
713 int max;
714 };
715
716 #define SET_PORT_GEN_ALL_VALID 0x7
717 #define SET_PORT_PROMISC_SHIFT 31
718 #define SET_PORT_MC_PROMISC_SHIFT 30
719
720 enum {
721 MCAST_DIRECT_ONLY = 0,
722 MCAST_DIRECT = 1,
723 MCAST_DEFAULT = 2
724 };
725
726
727 struct mlx4_set_port_general_context {
728 u8 reserved[3];
729 u8 flags;
730 u16 reserved2;
731 __be16 mtu;
732 u8 pptx;
733 u8 pfctx;
734 u16 reserved3;
735 u8 pprx;
736 u8 pfcrx;
737 u16 reserved4;
738 };
739
740 struct mlx4_set_port_rqp_calc_context {
741 __be32 base_qpn;
742 u8 rererved;
743 u8 n_mac;
744 u8 n_vlan;
745 u8 n_prio;
746 u8 reserved2[3];
747 u8 mac_miss;
748 u8 intra_no_vlan;
749 u8 no_vlan;
750 u8 intra_vlan_miss;
751 u8 vlan_miss;
752 u8 reserved3[3];
753 u8 no_vlan_prio;
754 __be32 promisc;
755 __be32 mcast;
756 };
757
758 struct mlx4_port_info {
759 struct mlx4_dev *dev;
760 int port;
761 char dev_name[16];
762 struct device_attribute port_attr;
763 enum mlx4_port_type tmp_type;
764 char dev_mtu_name[16];
765 struct device_attribute port_mtu_attr;
766 struct mlx4_mac_table mac_table;
767 struct mlx4_vlan_table vlan_table;
768 int base_qpn;
769 };
770
771 struct mlx4_sense {
772 struct mlx4_dev *dev;
773 u8 do_sense_port[MLX4_MAX_PORTS + 1];
774 u8 sense_allowed[MLX4_MAX_PORTS + 1];
775 struct delayed_work sense_poll;
776 };
777
778 struct mlx4_msix_ctl {
779 u64 pool_bm;
780 struct mutex pool_lock;
781 };
782
783 struct mlx4_steer {
784 struct list_head promisc_qps[MLX4_NUM_STEERS];
785 struct list_head steer_entries[MLX4_NUM_STEERS];
786 };
787
788 enum {
789 MLX4_PCI_DEV_IS_VF = 1 << 0,
790 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
791 };
792
793 struct mlx4_roce_gid_entry {
794 u8 raw[16];
795 };
796
797 struct counter_index {
798 struct list_head list;
799 u32 index;
800 };
801
802 struct mlx4_counters {
803 struct mlx4_bitmap bitmap;
804 struct list_head global_port_list[MLX4_MAX_PORTS];
805 struct list_head vf_list[MLX4_MAX_NUM_VF][MLX4_MAX_PORTS];
806 struct mutex mutex;
807 };
808
809 enum {
810 MLX4_NO_RR = 0,
811 MLX4_USE_RR = 1,
812 };
813
814 struct mlx4_priv {
815 struct mlx4_dev dev;
816
817 struct list_head dev_list;
818 struct list_head ctx_list;
819 spinlock_t ctx_lock;
820
821 int pci_dev_data;
822
823 struct list_head pgdir_list;
824 struct mutex pgdir_mutex;
825
826 struct mlx4_fw fw;
827 struct mlx4_cmd cmd;
828 struct mlx4_mfunc mfunc;
829
830 struct mlx4_bitmap pd_bitmap;
831 struct mlx4_bitmap xrcd_bitmap;
832 struct mlx4_uar_table uar_table;
833 struct mlx4_mr_table mr_table;
834 struct mlx4_cq_table cq_table;
835 struct mlx4_eq_table eq_table;
836 struct mlx4_srq_table srq_table;
837 struct mlx4_qp_table qp_table;
838 struct mlx4_mcg_table mcg_table;
839 struct mlx4_counters counters_table;
840
841 struct mlx4_catas_err catas_err;
842
843 void __iomem *clr_base;
844
845 struct mlx4_uar driver_uar;
846 void __iomem *kar;
847 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
848 struct mlx4_sense sense;
849 struct mutex port_mutex;
850 struct mlx4_msix_ctl msix_ctl;
851 struct mlx4_steer *steer;
852 struct list_head bf_list;
853 struct mutex bf_mutex;
854 struct io_mapping *bf_mapping;
855 void __iomem *clock_mapping;
856 int reserved_mtts;
857 int fs_hash_mode;
858 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
859 __be64 slave_node_guids[MLX4_MFUNC_MAX];
860 struct mlx4_roce_gid_entry roce_gids[MLX4_MAX_PORTS][128];
861 atomic_t opreq_count;
862 struct work_struct opreq_task;
863 };
864
mlx4_priv(struct mlx4_dev * dev)865 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
866 {
867 return container_of(dev, struct mlx4_priv, dev);
868 }
869
870 #define MLX4_SENSE_RANGE (HZ * 3)
871
872 extern struct workqueue_struct *mlx4_wq;
873
874 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
875 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr);
876 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt,
877 int align, u32 skip_mask);
878 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt,
879 int use_rr);
880 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
881 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
882 u32 reserved_bot, u32 resetrved_top);
883 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
884
885 int mlx4_reset(struct mlx4_dev *dev);
886
887 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
888 void mlx4_free_eq_table(struct mlx4_dev *dev);
889
890 int mlx4_init_pd_table(struct mlx4_dev *dev);
891 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
892 int mlx4_init_uar_table(struct mlx4_dev *dev);
893 int mlx4_init_mr_table(struct mlx4_dev *dev);
894 int mlx4_init_eq_table(struct mlx4_dev *dev);
895 int mlx4_init_cq_table(struct mlx4_dev *dev);
896 int mlx4_init_qp_table(struct mlx4_dev *dev);
897 int mlx4_init_srq_table(struct mlx4_dev *dev);
898 int mlx4_init_mcg_table(struct mlx4_dev *dev);
899
900 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
901 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
902 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
903 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
904 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
905 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
906 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
907 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
908 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
909 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
910 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
911 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
912 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
913 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
914 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
915 int __mlx4_mpt_reserve(struct mlx4_dev *dev);
916 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
917 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index);
918 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
919 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
920 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
921
922 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
923 struct mlx4_vhcr *vhcr,
924 struct mlx4_cmd_mailbox *inbox,
925 struct mlx4_cmd_mailbox *outbox,
926 struct mlx4_cmd_info *cmd);
927 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
928 struct mlx4_vhcr *vhcr,
929 struct mlx4_cmd_mailbox *inbox,
930 struct mlx4_cmd_mailbox *outbox,
931 struct mlx4_cmd_info *cmd);
932 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
933 struct mlx4_vhcr *vhcr,
934 struct mlx4_cmd_mailbox *inbox,
935 struct mlx4_cmd_mailbox *outbox,
936 struct mlx4_cmd_info *cmd);
937 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
938 struct mlx4_vhcr *vhcr,
939 struct mlx4_cmd_mailbox *inbox,
940 struct mlx4_cmd_mailbox *outbox,
941 struct mlx4_cmd_info *cmd);
942 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
943 struct mlx4_vhcr *vhcr,
944 struct mlx4_cmd_mailbox *inbox,
945 struct mlx4_cmd_mailbox *outbox,
946 struct mlx4_cmd_info *cmd);
947 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
948 struct mlx4_vhcr *vhcr,
949 struct mlx4_cmd_mailbox *inbox,
950 struct mlx4_cmd_mailbox *outbox,
951 struct mlx4_cmd_info *cmd);
952 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
953 struct mlx4_vhcr *vhcr,
954 struct mlx4_cmd_mailbox *inbox,
955 struct mlx4_cmd_mailbox *outbox,
956 struct mlx4_cmd_info *cmd);
957 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
958 int *base, u8 flags);
959 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
960 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
961 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
962 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
963 int start_index, int npages, u64 *page_list);
964 int __mlx4_counter_alloc(struct mlx4_dev *dev, int slave, int port, u32 *idx);
965 void __mlx4_counter_free(struct mlx4_dev *dev, int slave, int port, u32 idx);
966
967 int __mlx4_slave_counters_free(struct mlx4_dev *dev, int slave);
968 int __mlx4_clear_if_stat(struct mlx4_dev *dev,
969 u8 counter_index);
970 u8 mlx4_get_default_counter_index(struct mlx4_dev *dev, int slave, int port);
971
972 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
973 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
974
975 void mlx4_start_catas_poll(struct mlx4_dev *dev);
976 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
977 void mlx4_catas_init(void);
978 int mlx4_restart_one(struct pci_dev *pdev);
979 int mlx4_register_device(struct mlx4_dev *dev);
980 void mlx4_unregister_device(struct mlx4_dev *dev);
981 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
982 unsigned long param);
983
984 struct mlx4_dev_cap;
985 struct mlx4_init_hca_param;
986
987 u64 mlx4_make_profile(struct mlx4_dev *dev,
988 struct mlx4_profile *request,
989 struct mlx4_dev_cap *dev_cap,
990 struct mlx4_init_hca_param *init_hca);
991 void mlx4_master_comm_channel(struct work_struct *work);
992 void mlx4_master_arm_comm_channel(struct work_struct *work);
993 void mlx4_gen_slave_eqe(struct work_struct *work);
994 void mlx4_master_handle_slave_flr(struct work_struct *work);
995
996 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
997 struct mlx4_vhcr *vhcr,
998 struct mlx4_cmd_mailbox *inbox,
999 struct mlx4_cmd_mailbox *outbox,
1000 struct mlx4_cmd_info *cmd);
1001 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
1002 struct mlx4_vhcr *vhcr,
1003 struct mlx4_cmd_mailbox *inbox,
1004 struct mlx4_cmd_mailbox *outbox,
1005 struct mlx4_cmd_info *cmd);
1006 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
1007 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
1008 struct mlx4_cmd_mailbox *outbox,
1009 struct mlx4_cmd_info *cmd);
1010 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
1011 struct mlx4_vhcr *vhcr,
1012 struct mlx4_cmd_mailbox *inbox,
1013 struct mlx4_cmd_mailbox *outbox,
1014 struct mlx4_cmd_info *cmd);
1015 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1016 struct mlx4_vhcr *vhcr,
1017 struct mlx4_cmd_mailbox *inbox,
1018 struct mlx4_cmd_mailbox *outbox,
1019 struct mlx4_cmd_info *cmd);
1020 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
1021 struct mlx4_vhcr *vhcr,
1022 struct mlx4_cmd_mailbox *inbox,
1023 struct mlx4_cmd_mailbox *outbox,
1024 struct mlx4_cmd_info *cmd);
1025 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1026 struct mlx4_vhcr *vhcr,
1027 struct mlx4_cmd_mailbox *inbox,
1028 struct mlx4_cmd_mailbox *outbox,
1029 struct mlx4_cmd_info *cmd);
1030 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1031 struct mlx4_vhcr *vhcr,
1032 struct mlx4_cmd_mailbox *inbox,
1033 struct mlx4_cmd_mailbox *outbox,
1034 struct mlx4_cmd_info *cmd);
1035 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1036 struct mlx4_vhcr *vhcr,
1037 struct mlx4_cmd_mailbox *inbox,
1038 struct mlx4_cmd_mailbox *outbox,
1039 struct mlx4_cmd_info *cmd);
1040 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1041 struct mlx4_vhcr *vhcr,
1042 struct mlx4_cmd_mailbox *inbox,
1043 struct mlx4_cmd_mailbox *outbox,
1044 struct mlx4_cmd_info *cmd);
1045 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1046 struct mlx4_vhcr *vhcr,
1047 struct mlx4_cmd_mailbox *inbox,
1048 struct mlx4_cmd_mailbox *outbox,
1049 struct mlx4_cmd_info *cmd);
1050 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1051 struct mlx4_vhcr *vhcr,
1052 struct mlx4_cmd_mailbox *inbox,
1053 struct mlx4_cmd_mailbox *outbox,
1054 struct mlx4_cmd_info *cmd);
1055 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1056 struct mlx4_vhcr *vhcr,
1057 struct mlx4_cmd_mailbox *inbox,
1058 struct mlx4_cmd_mailbox *outbox,
1059 struct mlx4_cmd_info *cmd);
1060 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1061 struct mlx4_vhcr *vhcr,
1062 struct mlx4_cmd_mailbox *inbox,
1063 struct mlx4_cmd_mailbox *outbox,
1064 struct mlx4_cmd_info *cmd);
1065 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1066 struct mlx4_vhcr *vhcr,
1067 struct mlx4_cmd_mailbox *inbox,
1068 struct mlx4_cmd_mailbox *outbox,
1069 struct mlx4_cmd_info *cmd);
1070 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1071 struct mlx4_vhcr *vhcr,
1072 struct mlx4_cmd_mailbox *inbox,
1073 struct mlx4_cmd_mailbox *outbox,
1074 struct mlx4_cmd_info *cmd);
1075 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1076 struct mlx4_vhcr *vhcr,
1077 struct mlx4_cmd_mailbox *inbox,
1078 struct mlx4_cmd_mailbox *outbox,
1079 struct mlx4_cmd_info *cmd);
1080 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1081 struct mlx4_vhcr *vhcr,
1082 struct mlx4_cmd_mailbox *inbox,
1083 struct mlx4_cmd_mailbox *outbox,
1084 struct mlx4_cmd_info *cmd);
1085 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1086 struct mlx4_vhcr *vhcr,
1087 struct mlx4_cmd_mailbox *inbox,
1088 struct mlx4_cmd_mailbox *outbox,
1089 struct mlx4_cmd_info *cmd);
1090 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1091 struct mlx4_vhcr *vhcr,
1092 struct mlx4_cmd_mailbox *inbox,
1093 struct mlx4_cmd_mailbox *outbox,
1094 struct mlx4_cmd_info *cmd);
1095 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1096 struct mlx4_vhcr *vhcr,
1097 struct mlx4_cmd_mailbox *inbox,
1098 struct mlx4_cmd_mailbox *outbox,
1099 struct mlx4_cmd_info *cmd);
1100 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1101 struct mlx4_vhcr *vhcr,
1102 struct mlx4_cmd_mailbox *inbox,
1103 struct mlx4_cmd_mailbox *outbox,
1104 struct mlx4_cmd_info *cmd);
1105 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1106 struct mlx4_vhcr *vhcr,
1107 struct mlx4_cmd_mailbox *inbox,
1108 struct mlx4_cmd_mailbox *outbox,
1109 struct mlx4_cmd_info *cmd);
1110 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1111 struct mlx4_vhcr *vhcr,
1112 struct mlx4_cmd_mailbox *inbox,
1113 struct mlx4_cmd_mailbox *outbox,
1114 struct mlx4_cmd_info *cmd);
1115 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1116 struct mlx4_vhcr *vhcr,
1117 struct mlx4_cmd_mailbox *inbox,
1118 struct mlx4_cmd_mailbox *outbox,
1119 struct mlx4_cmd_info *cmd);
1120 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1121 struct mlx4_vhcr *vhcr,
1122 struct mlx4_cmd_mailbox *inbox,
1123 struct mlx4_cmd_mailbox *outbox,
1124 struct mlx4_cmd_info *cmd);
1125 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1126 struct mlx4_vhcr *vhcr,
1127 struct mlx4_cmd_mailbox *inbox,
1128 struct mlx4_cmd_mailbox *outbox,
1129 struct mlx4_cmd_info *cmd);
1130
1131 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1132
1133 int mlx4_cmd_init(struct mlx4_dev *dev);
1134 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
1135 int mlx4_multi_func_init(struct mlx4_dev *dev);
1136 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1137 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1138 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1139 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1140
1141 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1142 unsigned long timeout);
1143
1144 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1145 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1146
1147 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1148
1149 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1150
1151 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1152
1153 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1154 enum mlx4_port_type *type);
1155 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1156 enum mlx4_port_type *stype,
1157 enum mlx4_port_type *defaults);
1158 void mlx4_start_sense(struct mlx4_dev *dev);
1159 void mlx4_stop_sense(struct mlx4_dev *dev);
1160 void mlx4_sense_init(struct mlx4_dev *dev);
1161 int mlx4_check_port_params(struct mlx4_dev *dev,
1162 enum mlx4_port_type *port_type);
1163 int mlx4_change_port_types(struct mlx4_dev *dev,
1164 enum mlx4_port_type *port_types);
1165
1166 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1167 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1168 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1169 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1170
1171 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1172 /* resource tracker functions*/
1173 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1174 enum mlx4_resource resource_type,
1175 u64 resource_id, int *slave);
1176 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1177 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1178
1179 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1180 enum mlx4_res_tracker_free_type type);
1181
1182 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1183 struct mlx4_vhcr *vhcr,
1184 struct mlx4_cmd_mailbox *inbox,
1185 struct mlx4_cmd_mailbox *outbox,
1186 struct mlx4_cmd_info *cmd);
1187 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1188 struct mlx4_vhcr *vhcr,
1189 struct mlx4_cmd_mailbox *inbox,
1190 struct mlx4_cmd_mailbox *outbox,
1191 struct mlx4_cmd_info *cmd);
1192 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1193 struct mlx4_vhcr *vhcr,
1194 struct mlx4_cmd_mailbox *inbox,
1195 struct mlx4_cmd_mailbox *outbox,
1196 struct mlx4_cmd_info *cmd);
1197 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1198 struct mlx4_vhcr *vhcr,
1199 struct mlx4_cmd_mailbox *inbox,
1200 struct mlx4_cmd_mailbox *outbox,
1201 struct mlx4_cmd_info *cmd);
1202 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1203 struct mlx4_vhcr *vhcr,
1204 struct mlx4_cmd_mailbox *inbox,
1205 struct mlx4_cmd_mailbox *outbox,
1206 struct mlx4_cmd_info *cmd);
1207 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1208 struct mlx4_vhcr *vhcr,
1209 struct mlx4_cmd_mailbox *inbox,
1210 struct mlx4_cmd_mailbox *outbox,
1211 struct mlx4_cmd_info *cmd);
1212 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1213
1214 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1215 int *gid_tbl_len, int *pkey_tbl_len);
1216
1217 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1218 struct mlx4_vhcr *vhcr,
1219 struct mlx4_cmd_mailbox *inbox,
1220 struct mlx4_cmd_mailbox *outbox,
1221 struct mlx4_cmd_info *cmd);
1222
1223 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1224 struct mlx4_vhcr *vhcr,
1225 struct mlx4_cmd_mailbox *inbox,
1226 struct mlx4_cmd_mailbox *outbox,
1227 struct mlx4_cmd_info *cmd);
1228 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1229 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1230 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1231 int block_mcast_loopback, enum mlx4_protocol prot,
1232 enum mlx4_steer_type steer);
1233 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1234 u8 gid[16], u8 port,
1235 int block_mcast_loopback,
1236 enum mlx4_protocol prot, u64 *reg_id);
1237 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1238 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1239 struct mlx4_vhcr *vhcr,
1240 struct mlx4_cmd_mailbox *inbox,
1241 struct mlx4_cmd_mailbox *outbox,
1242 struct mlx4_cmd_info *cmd);
1243 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1244 struct mlx4_vhcr *vhcr,
1245 struct mlx4_cmd_mailbox *inbox,
1246 struct mlx4_cmd_mailbox *outbox,
1247 struct mlx4_cmd_info *cmd);
1248 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1249 int port, void *buf);
1250 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1251 struct mlx4_vhcr *vhcr,
1252 struct mlx4_cmd_mailbox *inbox,
1253 struct mlx4_cmd_mailbox *outbox,
1254 struct mlx4_cmd_info *cmd);
1255 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1256 struct mlx4_vhcr *vhcr,
1257 struct mlx4_cmd_mailbox *inbox,
1258 struct mlx4_cmd_mailbox *outbox,
1259 struct mlx4_cmd_info *cmd);
1260 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1261 struct mlx4_vhcr *vhcr,
1262 struct mlx4_cmd_mailbox *inbox,
1263 struct mlx4_cmd_mailbox *outbox,
1264 struct mlx4_cmd_info *cmd);
1265 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1266 struct mlx4_vhcr *vhcr,
1267 struct mlx4_cmd_mailbox *inbox,
1268 struct mlx4_cmd_mailbox *outbox,
1269 struct mlx4_cmd_info *cmd);
1270 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1271 struct mlx4_vhcr *vhcr,
1272 struct mlx4_cmd_mailbox *inbox,
1273 struct mlx4_cmd_mailbox *outbox,
1274 struct mlx4_cmd_info *cmd);
1275 int mlx4_MOD_STAT_CFG_wrapper(struct mlx4_dev *dev, int slave,
1276 struct mlx4_vhcr *vhcr,
1277 struct mlx4_cmd_mailbox *inbox,
1278 struct mlx4_cmd_mailbox *outbox,
1279 struct mlx4_cmd_info *cmd);
1280
1281 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1282 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1283
set_param_l(u64 * arg,u32 val)1284 static inline void set_param_l(u64 *arg, u32 val)
1285 {
1286 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
1287 }
1288
set_param_h(u64 * arg,u32 val)1289 static inline void set_param_h(u64 *arg, u32 val)
1290 {
1291 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1292 }
1293
get_param_l(u64 * arg)1294 static inline u32 get_param_l(u64 *arg)
1295 {
1296 return (u32) (*arg & 0xffffffff);
1297 }
1298
get_param_h(u64 * arg)1299 static inline u32 get_param_h(u64 *arg)
1300 {
1301 return (u32)(*arg >> 32);
1302 }
1303
mlx4_tlock(struct mlx4_dev * dev)1304 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1305 {
1306 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1307 }
1308
1309 #define NOT_MASKED_PD_BITS 17
1310
1311 void sys_tune_init(void);
1312 void sys_tune_fini(void);
1313
1314 void mlx4_init_quotas(struct mlx4_dev *dev);
1315
1316 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave);
1317 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave);
1318 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work);
1319
1320 #endif /* MLX4_H */
1321