1 /*-
2 * Copyright (c) 2003-2008 Joseph Koshy
3 * Copyright (c) 2007 The FreeBSD Foundation
4 * All rights reserved.
5 *
6 * Portions of this software were developed by A. Joseph Koshy under
7 * sponsorship from the FreeBSD Foundation and Google, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
33
34 /* Support for the AMD K7 and later processors */
35
36 #include <sys/param.h>
37 #include <sys/lock.h>
38 #include <sys/malloc.h>
39 #include <sys/mutex.h>
40 #include <sys/pmc.h>
41 #include <sys/pmckern.h>
42 #include <sys/smp.h>
43 #include <sys/systm.h>
44
45 #include <machine/cpu.h>
46 #include <machine/cpufunc.h>
47 #include <machine/md_var.h>
48 #include <machine/specialreg.h>
49
50 #ifdef HWPMC_DEBUG
51 enum pmc_class amd_pmc_class;
52 #endif
53 int AMD_cpufamily = 0, npmc = 0;
54 /* AMD K7 & K8 PMCs */
55 struct amd_descr {
56 struct pmc_descr pm_descr; /* "base class" */
57 uint32_t pm_evsel; /* address of EVSEL register */
58 uint32_t pm_perfctr; /* address of PERFCTR register */
59 };
60
61 static struct amd_descr amd_pmcdesc[AMD_NPMCS] =
62 {
63 {
64 .pm_descr =
65 {
66 .pd_name = "",
67 .pd_class = -1,
68 .pd_caps = AMD_PMC_CAPS,
69 .pd_width = 48
70 },
71 .pm_evsel = AMD_PMC_EVSEL_0,
72 .pm_perfctr = AMD_PMC_PERFCTR_0
73 },
74 {
75 .pm_descr =
76 {
77 .pd_name = "",
78 .pd_class = -1,
79 .pd_caps = AMD_PMC_CAPS,
80 .pd_width = 48
81 },
82 .pm_evsel = AMD_PMC_EVSEL_1,
83 .pm_perfctr = AMD_PMC_PERFCTR_1
84 },
85 {
86 .pm_descr =
87 {
88 .pd_name = "",
89 .pd_class = -1,
90 .pd_caps = AMD_PMC_CAPS,
91 .pd_width = 48
92 },
93 .pm_evsel = AMD_PMC_EVSEL_2,
94 .pm_perfctr = AMD_PMC_PERFCTR_2
95 },
96 {
97 .pm_descr =
98 {
99 .pd_name = "",
100 .pd_class = -1,
101 .pd_caps = AMD_PMC_CAPS,
102 .pd_width = 48
103 },
104 .pm_evsel = AMD_PMC_EVSEL_3,
105 .pm_perfctr = AMD_PMC_PERFCTR_3
106 },
107 {
108 .pm_descr =
109 {
110 .pd_name = "",
111 .pd_class = -1,
112 .pd_caps = AMD_PMC_CAPS,
113 .pd_width = 48
114 },
115 .pm_evsel = AMD_PMC_EVSEL_4,
116 .pm_perfctr = AMD_PMC_PERFCTR_4
117 },
118 {
119 .pm_descr =
120 {
121 .pd_name = "",
122 .pd_class = -1,
123 .pd_caps = AMD_PMC_CAPS,
124 .pd_width = 48
125 },
126 .pm_evsel = AMD_PMC_EVSEL_5,
127 .pm_perfctr = AMD_PMC_PERFCTR_5
128 },
129 };
130
131 struct amd_event_code_map {
132 enum pmc_event pe_ev; /* enum value */
133 uint16_t pe_code; /* encoded event mask */
134 uint8_t pe_mask; /* bits allowed in unit mask */
135 };
136
137 const struct amd_event_code_map amd_event_codes[] = {
138 #if defined(__i386__) /* 32 bit Athlon (K7) only */
139 { PMC_EV_K7_DC_ACCESSES, 0x40, 0 },
140 { PMC_EV_K7_DC_MISSES, 0x41, 0 },
141 { PMC_EV_K7_DC_REFILLS_FROM_L2, 0x42, AMD_PMC_UNITMASK_MOESI },
142 { PMC_EV_K7_DC_REFILLS_FROM_SYSTEM, 0x43, AMD_PMC_UNITMASK_MOESI },
143 { PMC_EV_K7_DC_WRITEBACKS, 0x44, AMD_PMC_UNITMASK_MOESI },
144 { PMC_EV_K7_L1_DTLB_MISS_AND_L2_DTLB_HITS, 0x45, 0 },
145 { PMC_EV_K7_L1_AND_L2_DTLB_MISSES, 0x46, 0 },
146 { PMC_EV_K7_MISALIGNED_REFERENCES, 0x47, 0 },
147
148 { PMC_EV_K7_IC_FETCHES, 0x80, 0 },
149 { PMC_EV_K7_IC_MISSES, 0x81, 0 },
150
151 { PMC_EV_K7_L1_ITLB_MISSES, 0x84, 0 },
152 { PMC_EV_K7_L1_L2_ITLB_MISSES, 0x85, 0 },
153
154 { PMC_EV_K7_RETIRED_INSTRUCTIONS, 0xC0, 0 },
155 { PMC_EV_K7_RETIRED_OPS, 0xC1, 0 },
156 { PMC_EV_K7_RETIRED_BRANCHES, 0xC2, 0 },
157 { PMC_EV_K7_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0 },
158 { PMC_EV_K7_RETIRED_TAKEN_BRANCHES, 0xC4, 0 },
159 { PMC_EV_K7_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0 },
160 { PMC_EV_K7_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0 },
161 { PMC_EV_K7_RETIRED_RESYNC_BRANCHES, 0xC7, 0 },
162 { PMC_EV_K7_INTERRUPTS_MASKED_CYCLES, 0xCD, 0 },
163 { PMC_EV_K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0 },
164 { PMC_EV_K7_HARDWARE_INTERRUPTS, 0xCF, 0 },
165 #endif
166
167 { PMC_EV_K8_FP_DISPATCHED_FPU_OPS, 0x00, 0x3F },
168 { PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED, 0x01, 0x00 },
169 { PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS, 0x02, 0x00 },
170
171 { PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD, 0x20, 0x7F },
172 { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE,
173 0x21, 0x00 },
174 { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x22, 0x00 },
175 { PMC_EV_K8_LS_BUFFER2_FULL, 0x23, 0x00 },
176 { PMC_EV_K8_LS_LOCKED_OPERATION, 0x24, 0x07 },
177 { PMC_EV_K8_LS_MICROARCHITECTURAL_LATE_CANCEL, 0x25, 0x00 },
178 { PMC_EV_K8_LS_RETIRED_CFLUSH_INSTRUCTIONS, 0x26, 0x00 },
179 { PMC_EV_K8_LS_RETIRED_CPUID_INSTRUCTIONS, 0x27, 0x00 },
180
181 { PMC_EV_K8_DC_ACCESS, 0x40, 0x00 },
182 { PMC_EV_K8_DC_MISS, 0x41, 0x00 },
183 { PMC_EV_K8_DC_REFILL_FROM_L2, 0x42, 0x1F },
184 { PMC_EV_K8_DC_REFILL_FROM_SYSTEM, 0x43, 0x1F },
185 { PMC_EV_K8_DC_COPYBACK, 0x44, 0x1F },
186 { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_HIT, 0x45, 0x00 },
187 { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_MISS, 0x46, 0x00 },
188 { PMC_EV_K8_DC_MISALIGNED_DATA_REFERENCE, 0x47, 0x00 },
189 { PMC_EV_K8_DC_MICROARCHITECTURAL_LATE_CANCEL, 0x48, 0x00 },
190 { PMC_EV_K8_DC_MICROARCHITECTURAL_EARLY_CANCEL, 0x49, 0x00 },
191 { PMC_EV_K8_DC_ONE_BIT_ECC_ERROR, 0x4A, 0x03 },
192 { PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS, 0x4B, 0x07 },
193 { PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS, 0x4C, 0x03 },
194
195 { PMC_EV_K8_BU_CPU_CLK_UNHALTED, 0x76, 0x00 },
196 { PMC_EV_K8_BU_INTERNAL_L2_REQUEST, 0x7D, 0x1F },
197 { PMC_EV_K8_BU_FILL_REQUEST_L2_MISS, 0x7E, 0x07 },
198 { PMC_EV_K8_BU_FILL_INTO_L2, 0x7F, 0x03 },
199
200 { PMC_EV_K8_IC_FETCH, 0x80, 0x00 },
201 { PMC_EV_K8_IC_MISS, 0x81, 0x00 },
202 { PMC_EV_K8_IC_REFILL_FROM_L2, 0x82, 0x00 },
203 { PMC_EV_K8_IC_REFILL_FROM_SYSTEM, 0x83, 0x00 },
204 { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_HIT, 0x84, 0x00 },
205 { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_MISS, 0x85, 0x00 },
206 { PMC_EV_K8_IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x86, 0x00 },
207 { PMC_EV_K8_IC_INSTRUCTION_FETCH_STALL, 0x87, 0x00 },
208 { PMC_EV_K8_IC_RETURN_STACK_HIT, 0x88, 0x00 },
209 { PMC_EV_K8_IC_RETURN_STACK_OVERFLOW, 0x89, 0x00 },
210
211 { PMC_EV_K8_FR_RETIRED_X86_INSTRUCTIONS, 0xC0, 0x00 },
212 { PMC_EV_K8_FR_RETIRED_UOPS, 0xC1, 0x00 },
213 { PMC_EV_K8_FR_RETIRED_BRANCHES, 0xC2, 0x00 },
214 { PMC_EV_K8_FR_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0x00 },
215 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES, 0xC4, 0x00 },
216 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0x00 },
217 { PMC_EV_K8_FR_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0x00 },
218 { PMC_EV_K8_FR_RETIRED_RESYNCS, 0xC7, 0x00 },
219 { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS, 0xC8, 0x00 },
220 { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS_MISPREDICTED, 0xC9, 0x00 },
221 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE,
222 0xCA, 0x00 },
223 { PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS, 0xCB, 0x0F },
224 { PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS,
225 0xCC, 0x07 },
226 { PMC_EV_K8_FR_INTERRUPTS_MASKED_CYCLES, 0xCD, 0x00 },
227 { PMC_EV_K8_FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0x00 },
228 { PMC_EV_K8_FR_TAKEN_HARDWARE_INTERRUPTS, 0xCF, 0x00 },
229
230 { PMC_EV_K8_FR_DECODER_EMPTY, 0xD0, 0x00 },
231 { PMC_EV_K8_FR_DISPATCH_STALLS, 0xD1, 0x00 },
232 { PMC_EV_K8_FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE,
233 0xD2, 0x00 },
234 { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SERIALIZATION, 0xD3, 0x00 },
235 { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SEGMENT_LOAD, 0xD4, 0x00 },
236 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL,
237 0xD5, 0x00 },
238 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL,
239 0xD6, 0x00 },
240 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FPU_IS_FULL, 0xD7, 0x00 },
241 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_LS_IS_FULL, 0xD8, 0x00 },
242 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET,
243 0xD9, 0x00 },
244 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING,
245 0xDA, 0x00 },
246 { PMC_EV_K8_FR_FPU_EXCEPTIONS, 0xDB, 0x0F },
247 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR0, 0xDC, 0x00 },
248 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR1, 0xDD, 0x00 },
249 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR2, 0xDE, 0x00 },
250 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR3, 0xDF, 0x00 },
251
252 { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT, 0xE0, 0x7 },
253 { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW, 0xE1, 0x00 },
254 { PMC_EV_K8_NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED,
255 0xE2, 0x00 },
256 { PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND, 0xE3, 0x07 },
257 { PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION, 0xE4, 0x0F },
258 { PMC_EV_K8_NB_SIZED_COMMANDS, 0xEB, 0x7F },
259 { PMC_EV_K8_NB_PROBE_RESULT, 0xEC, 0x0F },
260 { PMC_EV_K8_NB_HT_BUS0_BANDWIDTH, 0xF6, 0x0F },
261 { PMC_EV_K8_NB_HT_BUS1_BANDWIDTH, 0xF7, 0x0F },
262 { PMC_EV_K8_NB_HT_BUS2_BANDWIDTH, 0xF8, 0x0F },
263 { PMC_EV_F17H_FPU_PIPEASSIGMENT, 0x00, 0xFF },
264 { PMC_EV_F17H_FP_SCHED_EMPTY, 0x01, 0x00 },
265 { PMC_EV_F17H_FP_RET_X87_FPOPS, 0x02, 0x07 },
266 { PMC_EV_F17H_FP_RET_SSEAVX_OPS, 0x03, 0xFF },
267 { PMC_EV_F17H_FP_NUM_MOVELIM_SCAL_OPT, 0x04, 0x0F },
268 { PMC_EV_F17H_FP_RET_SEROPS, 0x05, 0x0F },
269 { PMC_EV_F17H_LS_BAD_STATUS2, 0x24, 0x07 },
270 { PMC_EV_F17H_LS_LOCKS, 0x25, 0x0F },
271 { PMC_EV_F17H_LS_RET_CLFLUSH_INST, 0x26, 0x00 },
272 { PMC_EV_F17H_LS_RET_CPUID_INST, 0x27, 0x00 },
273 { PMC_EV_F17H_LS_DISPATCH, 0x29, 0x07 },
274 { PMC_EV_F17H_LS_SMI_RX, 0x2B, 0x00 },
275 { PMC_EV_F17H_LS_STLF, 0x35, 0x00 },
276 { PMC_EV_F17H_LS_STLF_COMMITCANCEL, 0x37, 0x00 },
277 { PMC_EV_F17H_LS_DC_ACCESS, 0x40, 0x00 },
278 { PMC_EV_F17H_LS_MAB_ALLOCPIPE, 0x41, 0x1F },
279 { PMC_EV_F17H_LS_REFFILS_FROM_SYS, 0x43, 0x5B },
280 { PMC_EV_F17H_LS_L1_DTLBMISS, 0x45, 0xFF },
281 { PMC_EV_F17H_LS_TABLEWALKER, 0x46, 0x0F },
282 { PMC_EV_F17H_LS_MISAL_ACCESS, 0x47, 0x00 },
283 { PMC_EV_F17H_LS_PREF_INST_DISPATCH, 0x4B, 0x07 },
284 { PMC_EV_F17H_LS_HWPF_ALLOCATED, 0x4C, 0x03 },
285 { PMC_EV_F17H_LS_HWPF_HIT, 0x4D, 0x03 },
286 { PMC_EV_F17H_LS_TW_INPROG_DSIDE, 0x4E, 0x0F },
287 { PMC_EV_F17H_LS_INEF_SW_PREF, 0x52, 0x03 },
288 { PMC_EV_F17H_LS_MAB_MCH_CNT, 0x55, 0x00 },
289 { PMC_EV_F17H_LS_HW_PF_MABALLOC, 0x57, 0x07 },
290 { PMC_EV_F17H_LS_HW_PF_MATCH, 0x58, 0x07 },
291 { PMC_EV_F17H_LS_SW_PF_DCFILLS, 0x59, 0x5B },
292 { PMC_EV_F17H_LS_HW_PF_DCFILLS, 0x5A, 0x5B },
293 { PMC_EV_F17H_LS_TW_DCFILLS, 0x5B, 0x5B },
294 { PMC_EV_F17H_LS_ALLOC_MAB_COUNT, 0x5F, 0x00 },
295 { PMC_EV_F17H_LS_TW_INITLEVEL, 0x6E, 0xFF },
296 { PMC_EV_F17H_LS_NOT_HALTED_CYCLE, 0x76, 0x00 },
297 { PMC_EV_F17H_LS_TW_RETURN_TYPES, 0x170, 0xCD },
298 { PMC_EV_F17H_IC_FW32, 0x80, 0x00 },
299 { PMC_EV_F17H_IC_FW32_MISS, 0x81, 0x00 },
300 { PMC_EV_F17H_IC_CACHEFILL_L2, 0x82, 0x00 },
301 { PMC_EV_F17H_IC_CACHEFILL_SYS, 0x83, 0x00 },
302 { PMC_EV_F17H_BP_L1TLBMISS_L2HIT, 0x84, 0x00 },
303 { PMC_EV_F17H_BP_L1TLBMISS_L2MISS, 0x85, 0x00 },
304 { PMC_EV_F17H_IC_FETCHSTALL, 0x87, 0x07 },
305 { PMC_EV_F17H_BP_L1_BTBCORRECT, 0x8A, 0x00 },
306 { PMC_EV_F17H_BP_L2_BTBCORRECT, 0x8B, 0x00 },
307 { PMC_EV_F17H_IC_CACHEINVAL, 0x8C, 0x03 },
308 { PMC_EV_F17H_BP_TLB_REL, 0x99, 0x00 },
309 { PMC_EV_F17H_ICOC_MODE_SWITCH, 0x28A, 0x03 },
310 { PMC_EV_F17H_DE_DISPATCH_TOKEN_STALLS, 0xAF, 0x7F },
311 { PMC_EV_F17H_EX_RET_INST, 0xC0, 0x00 },
312 { PMC_EV_F17H_EX_RET_COPS, 0xC1, 0x00 },
313 { PMC_EV_F17H_EX_RET_BRN, 0xC2, 0x00 },
314 { PMC_EV_F17H_EX_RET_BRN_MISP, 0xC3, 0x00 },
315 { PMC_EV_F17H_EX_RET_BRN_TKN, 0xC4, 0x00 },
316 { PMC_EV_F17H_EX_RET_BRN_TKN_MISP, 0xC5, 0x00 },
317 { PMC_EV_F17H_EX_RET_BRN_FAR, 0xC6, 0x00 },
318 { PMC_EV_F17H_EX_RET_BRN_RESYNC, 0xC7, 0x00 },
319 { PMC_EV_F17H_EX_RET_BRN_NEAR_RET, 0xC8, 0x00 },
320 { PMC_EV_F17H_EX_RET_BRN_NEAR_RET_MISPRED, 0xC9, 0x00 },
321 { PMC_EV_F17H_EX_RET_BRN_IND_MISP, 0xCA, 0x00 },
322 { PMC_EV_F17H_EX_RET_MMX_FP_INSTR, 0xCB, 0x07 },
323 { PMC_EV_F17H_EX_RET_COND_BRN, 0xD1, 0x00 },
324 { PMC_EV_F17H_EX_DIV_BUSY, 0xD3, 0x00 },
325 { PMC_EV_F17H_EX_DIV_COUNT, 0xD4, 0x00 },
326 { PMC_EV_F17H_L2_REQUEST_G1, 0x60, 0xFF },
327 { PMC_EV_F17H_L2_REQUEST_G2, 0x61, 0xFF },
328 { PMC_EV_F17H_L2_LATENCY, 0x62, 0x01 },
329 { PMC_EV_F17H_L2_WBCREQ, 0x63, 0x7F },
330 { PMC_EV_F17H_L2_CACHEREQSTAT, 0x64, 0xFF },
331 { PMC_EV_F17H_L2_SMCEVENTS, 0x67, 0x7F },
332 { PMC_EV_F17H_L2_FILLPENDING, 0x6D, 0x01 },
333 { PMC_EV_F17H_EX_TAGGED_IBSOPS, 0x1CF, 0x07 },
334 { PMC_EV_F17H_EX_RET_FUSED_BRNCH_INST, 0x1D0, 0x00 }
335
336 };
337
338 const int amd_event_codes_size = nitems(amd_event_codes);
339
340 /*
341 * Per-processor information
342 */
343
344 struct amd_cpu {
345 struct pmc_hw pc_amdpmcs[AMD_NPMCS];
346 };
347
348 static struct amd_cpu **amd_pcpu;
349
350 /*
351 * read a pmc register
352 */
353
354 static int
amd_read_pmc(int cpu,int ri,pmc_value_t * v)355 amd_read_pmc(int cpu, int ri, pmc_value_t *v)
356 {
357 enum pmc_mode mode;
358 const struct amd_descr *pd;
359 struct pmc *pm;
360 pmc_value_t tmp;
361
362 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
363 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
364 KASSERT(ri >= 0 && ri < npmc,
365 ("[amd,%d] illegal row-index %d", __LINE__, ri));
366 KASSERT(amd_pcpu[cpu],
367 ("[amd,%d] null per-cpu, cpu %d", __LINE__, cpu));
368
369 pm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc;
370 pd = &amd_pmcdesc[ri];
371
372 KASSERT(pm != NULL,
373 ("[amd,%d] No owner for HWPMC [cpu%d,pmc%d]", __LINE__,
374 cpu, ri));
375
376 mode = PMC_TO_MODE(pm);
377
378 PMCDBG2(MDP,REA,1,"amd-read id=%d class=%d", ri, pd->pm_descr.pd_class);
379
380 #ifdef HWPMC_DEBUG
381 KASSERT(pd->pm_descr.pd_class == amd_pmc_class,
382 ("[amd,%d] unknown PMC class (%d)", __LINE__,
383 pd->pm_descr.pd_class));
384 #endif
385
386 tmp = rdmsr(pd->pm_perfctr); /* RDMSR serializes */
387 PMCDBG2(MDP,REA,2,"amd-read (pre-munge) id=%d -> %jd", ri, tmp);
388 if (PMC_IS_SAMPLING_MODE(mode)) {
389 /* Sign extend 48 bit value to 64 bits. */
390 tmp = (pmc_value_t) (((int64_t) tmp << 16) >> 16);
391 tmp = AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
392 }
393 *v = tmp;
394
395 PMCDBG2(MDP,REA,2,"amd-read (post-munge) id=%d -> %jd", ri, *v);
396
397 return 0;
398 }
399
400 /*
401 * Write a PMC MSR.
402 */
403
404 static int
amd_write_pmc(int cpu,int ri,pmc_value_t v)405 amd_write_pmc(int cpu, int ri, pmc_value_t v)
406 {
407 const struct amd_descr *pd;
408 enum pmc_mode mode;
409 struct pmc *pm;
410
411 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
412 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
413 KASSERT(ri >= 0 && ri < npmc,
414 ("[amd,%d] illegal row-index %d", __LINE__, ri));
415
416 pm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc;
417 pd = &amd_pmcdesc[ri];
418
419 KASSERT(pm != NULL,
420 ("[amd,%d] PMC not owned (cpu%d,pmc%d)", __LINE__,
421 cpu, ri));
422
423 mode = PMC_TO_MODE(pm);
424
425 #ifdef HWPMC_DEBUG
426 KASSERT(pd->pm_descr.pd_class == amd_pmc_class,
427 ("[amd,%d] unknown PMC class (%d)", __LINE__,
428 pd->pm_descr.pd_class));
429 #endif
430
431 /* use 2's complement of the count for sampling mode PMCs */
432 if (PMC_IS_SAMPLING_MODE(mode))
433 v = AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
434
435 PMCDBG3(MDP,WRI,1,"amd-write cpu=%d ri=%d v=%jx", cpu, ri, v);
436
437 /* write the PMC value */
438 wrmsr(pd->pm_perfctr, v);
439 return 0;
440 }
441
442 /*
443 * configure hardware pmc according to the configuration recorded in
444 * pmc 'pm'.
445 */
446
447 static int
amd_config_pmc(int cpu,int ri,struct pmc * pm)448 amd_config_pmc(int cpu, int ri, struct pmc *pm)
449 {
450 struct pmc_hw *phw;
451
452 PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
453
454 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
455 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
456 KASSERT(ri >= 0 && ri < npmc,
457 ("[amd,%d] illegal row-index %d", __LINE__, ri));
458
459 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
460
461 KASSERT(pm == NULL || phw->phw_pmc == NULL,
462 ("[amd,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
463 __LINE__, pm, phw->phw_pmc));
464
465 phw->phw_pmc = pm;
466 return 0;
467 }
468
469 /*
470 * Retrieve a configured PMC pointer from hardware state.
471 */
472
473 static int
amd_get_config(int cpu,int ri,struct pmc ** ppm)474 amd_get_config(int cpu, int ri, struct pmc **ppm)
475 {
476 *ppm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc;
477
478 return 0;
479 }
480
481 /*
482 * Machine dependent actions taken during the context switch in of a
483 * thread.
484 */
485
486 static int
amd_switch_in(struct pmc_cpu * pc,struct pmc_process * pp)487 amd_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
488 {
489 (void) pc;
490
491 PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp,
492 (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) != 0);
493
494 /* enable the RDPMC instruction if needed */
495 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS)
496 load_cr4(rcr4() | CR4_PCE);
497
498 return 0;
499 }
500
501 /*
502 * Machine dependent actions taken during the context switch out of a
503 * thread.
504 */
505
506 static int
amd_switch_out(struct pmc_cpu * pc,struct pmc_process * pp)507 amd_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
508 {
509 (void) pc;
510 (void) pp; /* can be NULL */
511
512 PMCDBG3(MDP,SWO,1, "pc=%p pp=%p enable-msr=%d", pc, pp, pp ?
513 (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) == 1 : 0);
514
515 /* always turn off the RDPMC instruction */
516 load_cr4(rcr4() & ~CR4_PCE);
517
518 return 0;
519 }
520
521 /*
522 * Check if a given allocation is feasible.
523 */
524
525 static int
amd_allocate_pmc(int cpu,int ri,struct pmc * pm,const struct pmc_op_pmcallocate * a)526 amd_allocate_pmc(int cpu, int ri, struct pmc *pm,
527 const struct pmc_op_pmcallocate *a)
528 {
529 int i;
530 uint32_t allowed_unitmask, caps, unitmask;
531 enum pmc_event pe;
532 const struct pmc_descr *pd;
533
534 (void) cpu;
535 #if defined(__i386__)
536 uint32_t config;
537 #elif defined(__amd64__)
538 uint64_t config;
539 uint16_t eventval, extevent;
540 #endif
541
542 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
543 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
544 KASSERT(ri >= 0 && ri < npmc,
545 ("[amd,%d] illegal row index %d", __LINE__, ri));
546
547 pd = &amd_pmcdesc[ri].pm_descr;
548
549 /* check class match */
550 if (pd->pd_class != a->pm_class)
551 return EINVAL;
552
553 caps = pm->pm_caps;
554
555 PMCDBG2(MDP,ALL,1,"amd-allocate ri=%d caps=0x%x", ri, caps);
556
557 if ((pd->pd_caps & caps) != caps)
558 return EPERM;
559
560 pe = a->pm_ev;
561
562 /* map ev to the correct event mask code */
563 config = allowed_unitmask = 0;
564 for (i = 0; i < amd_event_codes_size; i++)
565 if (amd_event_codes[i].pe_ev == pe) {
566 #if defined(__i386__)
567 config =
568 AMD_PMC_TO_EVENTMASK(
569 amd_event_codes[i].pe_code);
570 #elif defined(__amd64__)
571 eventval =
572 AMD_PMC_TO_EVENTMASK(
573 amd_event_codes[i].pe_code);
574 if (eventval & AMD_PMC_EXTENDEDEVMASK) {
575 extevent = (eventval & AMD_PMC_EXTENDEDEVMASK);
576 config = (uint64_t)
577 extevent << AMD_PMC_EXTENDEDEVBIT;
578 config |= eventval & AMD_PMC_EVENTMASK_EXT;
579 } else {
580 config |=
581 AMD_PMC_TO_EVENTMASK(
582 amd_event_codes[i].pe_code);
583 }
584
585 #endif
586 allowed_unitmask =
587 AMD_PMC_TO_UNITMASK(amd_event_codes[i].pe_mask);
588 break;
589 }
590 if (i == amd_event_codes_size)
591 return EINVAL;
592
593 unitmask = a->pm_md.pm_amd.pm_amd_config & AMD_PMC_UNITMASK;
594 if (unitmask & ~allowed_unitmask) /* disallow reserved bits */
595 return EINVAL;
596
597 if (unitmask && (caps & PMC_CAP_QUALIFIER))
598 config |= unitmask;
599
600 if (caps & PMC_CAP_THRESHOLD)
601 config |= a->pm_md.pm_amd.pm_amd_config & AMD_PMC_COUNTERMASK;
602
603 /* set at least one of the 'usr' or 'os' caps */
604 if (caps & PMC_CAP_USER)
605 config |= AMD_PMC_USR;
606 if (caps & PMC_CAP_SYSTEM)
607 config |= AMD_PMC_OS;
608 if ((caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == 0)
609 config |= (AMD_PMC_USR|AMD_PMC_OS);
610
611 if (caps & PMC_CAP_EDGE)
612 config |= AMD_PMC_EDGE;
613 if (caps & PMC_CAP_INVERT)
614 config |= AMD_PMC_INVERT;
615 if (caps & PMC_CAP_INTERRUPT)
616 config |= AMD_PMC_INT;
617
618 pm->pm_md.pm_amd.pm_amd_evsel = config; /* save config value */
619
620 PMCDBG2(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, config);
621
622 return 0;
623 }
624
625 /*
626 * Release machine dependent state associated with a PMC. This is a
627 * no-op on this architecture.
628 *
629 */
630
631 /* ARGSUSED0 */
632 static int
amd_release_pmc(int cpu,int ri,struct pmc * pmc)633 amd_release_pmc(int cpu, int ri, struct pmc *pmc)
634 {
635 #ifdef HWPMC_DEBUG
636 const struct amd_descr *pd;
637 #endif
638 struct pmc_hw *phw;
639
640 (void) pmc;
641
642 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
643 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
644 KASSERT(ri >= 0 && ri < AMD_NPMCS,
645 ("[amd,%d] illegal row-index %d", __LINE__, ri));
646
647 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
648
649 KASSERT(phw->phw_pmc == NULL,
650 ("[amd,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
651
652 #ifdef HWPMC_DEBUG
653 pd = &amd_pmcdesc[ri];
654 if (pd->pm_descr.pd_class == amd_pmc_class)
655 KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel),
656 ("[amd,%d] PMC %d released while active", __LINE__, ri));
657 #endif
658
659 return 0;
660 }
661
662 /*
663 * start a PMC.
664 */
665
666 static int
amd_start_pmc(int cpu,int ri)667 amd_start_pmc(int cpu, int ri)
668 {
669 struct pmc *pm;
670 struct pmc_hw *phw;
671 const struct amd_descr *pd;
672 #if defined(__i386__)
673 uint32_t config = 0;
674 #elif defined(__amd64__)
675 uint64_t config = 0;
676 #endif
677
678 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
679 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
680 KASSERT(ri >= 0 && ri < npmc,
681 ("[amd,%d] illegal row-index %d", __LINE__, ri));
682
683 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
684 pm = phw->phw_pmc;
685 pd = &amd_pmcdesc[ri];
686
687 KASSERT(pm != NULL,
688 ("[amd,%d] starting cpu%d,pmc%d with null pmc record", __LINE__,
689 cpu, ri));
690
691 PMCDBG2(MDP,STA,1,"amd-start cpu=%d ri=%d", cpu, ri);
692
693 KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel),
694 ("[amd,%d] pmc%d,cpu%d: Starting active PMC \"%s\"", __LINE__,
695 ri, cpu, pd->pm_descr.pd_name));
696
697 /* turn on the PMC ENABLE bit */
698 config = pm->pm_md.pm_amd.pm_amd_evsel | AMD_PMC_ENABLE;
699
700 PMCDBG1(MDP,STA,2,"amd-start config=0x%x", config);
701
702 wrmsr(pd->pm_evsel, config);
703 return 0;
704 }
705
706 /*
707 * Stop a PMC.
708 */
709
710 static int
amd_stop_pmc(int cpu,int ri)711 amd_stop_pmc(int cpu, int ri)
712 {
713 struct pmc *pm;
714 struct pmc_hw *phw;
715 const struct amd_descr *pd;
716 #if defined(__i386__)
717 uint32_t config = 0;
718 #elif defined(__amd64__)
719 uint64_t config = 0;
720 #endif
721
722 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
723 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
724 KASSERT(ri >= 0 && ri < npmc,
725 ("[amd,%d] illegal row-index %d", __LINE__, ri));
726
727 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
728 pm = phw->phw_pmc;
729 pd = &amd_pmcdesc[ri];
730
731 KASSERT(pm != NULL,
732 ("[amd,%d] cpu%d,pmc%d no PMC to stop", __LINE__,
733 cpu, ri));
734 KASSERT(!AMD_PMC_IS_STOPPED(pd->pm_evsel),
735 ("[amd,%d] PMC%d, CPU%d \"%s\" already stopped",
736 __LINE__, ri, cpu, pd->pm_descr.pd_name));
737
738 PMCDBG1(MDP,STO,1,"amd-stop ri=%d", ri);
739
740 /* turn off the PMC ENABLE bit */
741 config = pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE;
742 wrmsr(pd->pm_evsel, config);
743 return 0;
744 }
745
746 /*
747 * Interrupt handler. This function needs to return '1' if the
748 * interrupt was this CPU's PMCs or '0' otherwise. It is not allowed
749 * to sleep or do anything a 'fast' interrupt handler is not allowed
750 * to do.
751 */
752
753 static int
amd_intr(int cpu,struct trapframe * tf)754 amd_intr(int cpu, struct trapframe *tf)
755 {
756 int i, error, retval;
757 uint32_t evsel, perfctr;
758 struct pmc *pm;
759 struct amd_cpu *pac;
760 pmc_value_t v;
761 #if defined(__i386__)
762 uint32_t config = 0;
763 #elif defined(__amd64__)
764 uint64_t config = 0;
765 #endif
766
767 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
768 ("[amd,%d] out of range CPU %d", __LINE__, cpu));
769
770 PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *) tf,
771 TRAPF_USERMODE(tf));
772
773 retval = 0;
774
775 pac = amd_pcpu[cpu];
776
777 /*
778 * look for all PMCs that have interrupted:
779 * - look for a running, sampling PMC which has overflowed
780 * and which has a valid 'struct pmc' association
781 *
782 * If found, we call a helper to process the interrupt.
783 *
784 * If multiple PMCs interrupt at the same time, the AMD64
785 * processor appears to deliver as many NMIs as there are
786 * outstanding PMC interrupts. So we process only one NMI
787 * interrupt at a time.
788 */
789
790 for (i = 0; retval == 0 && i < npmc; i++) {
791
792 if ((pm = pac->pc_amdpmcs[i].phw_pmc) == NULL ||
793 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
794 continue;
795 }
796
797 if (!AMD_PMC_HAS_OVERFLOWED(i))
798 continue;
799
800 retval = 1; /* Found an interrupting PMC. */
801
802 if (pm->pm_state != PMC_STATE_RUNNING)
803 continue;
804
805 /* Stop the PMC, reload count. */
806 if (i <= 3) {
807 evsel = AMD_PMC_EVSEL_0 + i;
808 perfctr = AMD_PMC_PERFCTR_0 + i;
809 } else if (i == 4) {
810 evsel = AMD_PMC_EVSEL_4;
811 perfctr = AMD_PMC_PERFCTR_4;
812 } else if (i == 5) {
813 evsel = AMD_PMC_EVSEL_5;
814 perfctr = AMD_PMC_PERFCTR_5;
815 }
816 v = pm->pm_sc.pm_reloadcount;
817 config = rdmsr(evsel);
818
819
820 KASSERT((config & ~AMD_PMC_ENABLE) ==
821 (pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE),
822 ("[amd,%d] config mismatch reg=0x%jx pm=0x%jx", __LINE__,
823 (uintmax_t)config, (uintmax_t)pm->pm_md.pm_amd.pm_amd_evsel));
824
825 wrmsr(evsel, config & ~AMD_PMC_ENABLE);
826 wrmsr(perfctr, AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v));
827
828 /* Restart the counter if logging succeeded. */
829 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
830 TRAPF_USERMODE(tf));
831 if (error == 0)
832 wrmsr(evsel, config);
833 }
834
835 atomic_add_int(retval ? &pmc_stats.pm_intr_processed :
836 &pmc_stats.pm_intr_ignored, 1);
837
838 PMCDBG1(MDP,INT,2, "retval=%d", retval);
839 return (retval);
840 }
841
842 /*
843 * describe a PMC
844 */
845 static int
amd_describe(int cpu,int ri,struct pmc_info * pi,struct pmc ** ppmc)846 amd_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
847 {
848 int error;
849 size_t copied;
850 const struct amd_descr *pd;
851 struct pmc_hw *phw;
852
853 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
854 ("[amd,%d] illegal CPU %d", __LINE__, cpu));
855 KASSERT(ri >= 0 && ri < npmc,
856 ("[amd,%d] row-index %d out of range", __LINE__, ri));
857
858 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
859 pd = &amd_pmcdesc[ri];
860
861 if ((error = copystr(pd->pm_descr.pd_name, pi->pm_name,
862 PMC_NAME_MAX, &copied)) != 0)
863 return error;
864
865 pi->pm_class = pd->pm_descr.pd_class;
866
867 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
868 pi->pm_enabled = TRUE;
869 *ppmc = phw->phw_pmc;
870 } else {
871 pi->pm_enabled = FALSE;
872 *ppmc = NULL;
873 }
874
875 return 0;
876 }
877
878 /*
879 * i386 specific entry points
880 */
881
882 /*
883 * return the MSR address of the given PMC.
884 */
885
886 static int
amd_get_msr(int ri,uint32_t * msr)887 amd_get_msr(int ri, uint32_t *msr)
888 {
889 KASSERT(ri >= 0 && ri < AMD_NPMCS,
890 ("[amd,%d] ri %d out of range", __LINE__, ri));
891
892 *msr = amd_pmcdesc[ri].pm_perfctr - AMD_PMC_PERFCTR_0;
893
894 return (0);
895 }
896
897 /*
898 * processor dependent initialization.
899 */
900
901 static int
amd_pcpu_init(struct pmc_mdep * md,int cpu)902 amd_pcpu_init(struct pmc_mdep *md, int cpu)
903 {
904 int classindex = 0, first_ri, n;
905 struct pmc_cpu *pc;
906 struct amd_cpu *pac;
907 struct pmc_hw *phw;
908
909 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
910 ("[amd,%d] insane cpu number %d", __LINE__, cpu));
911
912 PMCDBG1(MDP,INI,1,"amd-init cpu=%d", cpu);
913
914 amd_pcpu[cpu] = pac = malloc(sizeof(struct amd_cpu), M_PMC,
915 M_WAITOK|M_ZERO);
916
917 /*
918 * Set the content of the hardware descriptors to a known
919 * state and initialize pointers in the MI per-cpu descriptor.
920 */
921 pc = pmc_pcpu[cpu];
922 #if defined(__amd64__)
923 if (AMD_cpufamily == 0xF)
924 classindex = PMC_MDEP_CLASS_INDEX_K8;
925 else if (AMD_cpufamily == 0x17)
926 classindex = PMC_MDEP_CLASS_INDEX_F17H;
927 else
928 (void) printf("pmc:AMD CPU family unknown.\n");
929 #elif defined(__i386__)
930 classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ?
931 PMC_MDEP_CLASS_INDEX_K8 : PMC_MDEP_CLASS_INDEX_K7;
932 #endif
933 first_ri = md->pmd_classdep[classindex].pcd_ri;
934
935 KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu pointer", __LINE__));
936
937 for (n = 0, phw = pac->pc_amdpmcs; n < npmc; n++, phw++) {
938 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
939 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n);
940 phw->phw_pmc = NULL;
941 pc->pc_hwpmcs[n + first_ri] = phw;
942 }
943
944 return (0);
945 }
946
947
948 /*
949 * processor dependent cleanup prior to the KLD
950 * being unloaded
951 */
952
953 static int
amd_pcpu_fini(struct pmc_mdep * md,int cpu)954 amd_pcpu_fini(struct pmc_mdep *md, int cpu)
955 {
956 int classindex = 0, first_ri, i;
957 struct pmc_cpu *pc;
958 struct amd_cpu *pac;
959 #if defined(__i386__)
960 uint32_t evsel;
961 #elif defined(__amd64__)
962 uint64_t evsel;
963 #endif
964
965 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
966 ("[amd,%d] insane cpu number (%d)", __LINE__, cpu));
967
968 PMCDBG1(MDP,INI,1,"amd-cleanup cpu=%d", cpu);
969
970 /*
971 * First, turn off all PMCs on this CPU.
972 */
973 for (i = 0; i < 4; i++) { /* XXX this loop is now not needed */
974 evsel = rdmsr(AMD_PMC_EVSEL_0 + i);
975 evsel &= ~AMD_PMC_ENABLE;
976 wrmsr(AMD_PMC_EVSEL_0 + i, evsel);
977 }
978 if (AMD_cpufamily == 0x17) {
979 for (i = 0; i < 4; i += 2) {
980 evsel = rdmsr(AMD_PMC_EVSEL_4 + i);
981 evsel &= ~AMD_PMC_ENABLE;
982 wrmsr(AMD_PMC_EVSEL_4 + i, evsel);
983 }
984 }
985
986 /*
987 * Next, free up allocated space.
988 */
989 if ((pac = amd_pcpu[cpu]) == NULL)
990 return (0);
991
992 amd_pcpu[cpu] = NULL;
993
994 #ifdef HWPMC_DEBUG
995 for (i = 0; i < npmc; i++) {
996 KASSERT(pac->pc_amdpmcs[i].phw_pmc == NULL,
997 ("[amd,%d] CPU%d/PMC%d in use", __LINE__, cpu, i));
998 KASSERT(AMD_PMC_IS_STOPPED(AMD_PMC_EVSEL_0 + i),
999 ("[amd,%d] CPU%d/PMC%d not stopped", __LINE__, cpu, i));
1000 }
1001 #endif
1002
1003 pc = pmc_pcpu[cpu];
1004 KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu state", __LINE__));
1005
1006 #if defined(__amd64__)
1007 if (AMD_cpufamily == 0xF)
1008 classindex = PMC_MDEP_CLASS_INDEX_K8;
1009 else if (AMD_cpufamily == 0x17)
1010 classindex = PMC_MDEP_CLASS_INDEX_F17H;
1011 #elif defined(__i386__)
1012 classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ? PMC_MDEP_CLASS_INDEX_K8 :
1013 PMC_MDEP_CLASS_INDEX_K7;
1014 #endif
1015 first_ri = md->pmd_classdep[classindex].pcd_ri;
1016
1017 /*
1018 * Reset pointers in the MI 'per-cpu' state.
1019 */
1020 for (i = 0; i < npmc; i++) {
1021 pc->pc_hwpmcs[i + first_ri] = NULL;
1022 }
1023
1024
1025 free(pac, M_PMC);
1026
1027 return (0);
1028 }
1029
1030 /*
1031 * Initialize ourselves.
1032 */
1033
1034 struct pmc_mdep *
pmc_amd_initialize(void)1035 pmc_amd_initialize(void)
1036 {
1037 int classindex, error, i, ncpus;
1038 struct pmc_classdep *pcd;
1039 enum pmc_cputype cputype;
1040 struct pmc_mdep *pmc_mdep;
1041 enum pmc_class class;
1042 char *name;
1043
1044 /*
1045 * The presence of hardware performance counters on the AMD
1046 * Athlon, Duron or later processors, is _not_ indicated by
1047 * any of the processor feature flags set by the 'CPUID'
1048 * instruction, so we only check the 'instruction family'
1049 * field returned by CPUID for instruction family >= 6.
1050 */
1051 name = NULL;
1052 AMD_cpufamily = CPUID_TO_FAMILY(cpu_id);
1053 if (AMD_cpufamily == 0x17)
1054 npmc = AMD_FAM17H_COUNTERS;
1055 else
1056 npmc = AMD_LEGACY_COUNTERS;
1057
1058 switch (cpu_id & 0xF00) {
1059 #if defined(__i386__)
1060 case 0x600: /* Athlon(tm) processor */
1061 classindex = PMC_MDEP_CLASS_INDEX_K7;
1062 cputype = PMC_CPU_AMD_K7;
1063 class = PMC_CLASS_K7;
1064 name = "K7";
1065 break;
1066 #endif
1067 case 0xF00:
1068 /* AMD64 bit Processors */
1069 if (AMD_cpufamily == 0xF) {
1070 /* Athlon64/Opteron processor */
1071 classindex = PMC_MDEP_CLASS_INDEX_K8;
1072 cputype = PMC_CPU_AMD_K8;
1073 class = PMC_CLASS_K8;
1074 name = "K8";
1075 break;
1076 } else if (AMD_cpufamily == 0x17) {
1077 /* AMD F17H Processor */
1078 classindex = PMC_MDEP_CLASS_INDEX_F17H;
1079 cputype = PMC_CPU_AMD_F17H;
1080 class = PMC_CLASS_F17H;
1081 name = "F17H";
1082 break;
1083 } else
1084 (void) printf("pmc: Unknown AMD64 CPU.\n");
1085
1086 default:
1087 (void) printf("pmc: Unknown AMD CPU.\n");
1088 return NULL;
1089 }
1090
1091 #ifdef HWPMC_DEBUG
1092 amd_pmc_class = class;
1093 #endif
1094
1095 /*
1096 * Allocate space for pointers to PMC HW descriptors and for
1097 * the MDEP structure used by MI code.
1098 */
1099 amd_pcpu = malloc(sizeof(struct amd_cpu *) * pmc_cpu_max(), M_PMC,
1100 M_WAITOK|M_ZERO);
1101
1102 /*
1103 * These processors have two classes of PMCs: the TSC and
1104 * programmable PMCs.
1105 */
1106 pmc_mdep = pmc_mdep_alloc(2);
1107
1108 pmc_mdep->pmd_cputype = cputype;
1109
1110 ncpus = pmc_cpu_max();
1111
1112 /* Initialize the TSC. */
1113 error = pmc_tsc_initialize(pmc_mdep, ncpus);
1114 if (error)
1115 goto error;
1116
1117 /* Initialize AMD K7 and K8 PMC handling. */
1118 pcd = &pmc_mdep->pmd_classdep[classindex];
1119
1120 pcd->pcd_caps = AMD_PMC_CAPS;
1121 pcd->pcd_class = class;
1122 pcd->pcd_num = npmc;
1123 pcd->pcd_ri = pmc_mdep->pmd_npmc;
1124 pcd->pcd_width = 48;
1125
1126 /* fill in the correct pmc name and class */
1127 for (i = 0; i < npmc; i++) {
1128 (void) snprintf(amd_pmcdesc[i].pm_descr.pd_name,
1129 sizeof(amd_pmcdesc[i].pm_descr.pd_name), "%s-%d",
1130 name, i);
1131 amd_pmcdesc[i].pm_descr.pd_class = class;
1132 }
1133
1134 pcd->pcd_allocate_pmc = amd_allocate_pmc;
1135 pcd->pcd_config_pmc = amd_config_pmc;
1136 pcd->pcd_describe = amd_describe;
1137 pcd->pcd_get_config = amd_get_config;
1138 pcd->pcd_get_msr = amd_get_msr;
1139 pcd->pcd_pcpu_fini = amd_pcpu_fini;
1140 pcd->pcd_pcpu_init = amd_pcpu_init;
1141 pcd->pcd_read_pmc = amd_read_pmc;
1142 pcd->pcd_release_pmc = amd_release_pmc;
1143 pcd->pcd_start_pmc = amd_start_pmc;
1144 pcd->pcd_stop_pmc = amd_stop_pmc;
1145 pcd->pcd_write_pmc = amd_write_pmc;
1146
1147 pmc_mdep->pmd_pcpu_init = NULL;
1148 pmc_mdep->pmd_pcpu_fini = NULL;
1149 pmc_mdep->pmd_intr = amd_intr;
1150 pmc_mdep->pmd_switch_in = amd_switch_in;
1151 pmc_mdep->pmd_switch_out = amd_switch_out;
1152
1153 pmc_mdep->pmd_npmc += npmc;
1154
1155 PMCDBG0(MDP,INI,0,"amd-initialize");
1156
1157 return (pmc_mdep);
1158
1159 error:
1160 if (error) {
1161 free(pmc_mdep, M_PMC);
1162 pmc_mdep = NULL;
1163 }
1164
1165 return (NULL);
1166 }
1167
1168 /*
1169 * Finalization code for AMD CPUs.
1170 */
1171
1172 void
pmc_amd_finalize(struct pmc_mdep * md)1173 pmc_amd_finalize(struct pmc_mdep *md)
1174 {
1175 #if defined(INVARIANTS)
1176 int classindex, i, ncpus, pmcclass;
1177 #endif
1178
1179 pmc_tsc_finalize(md);
1180
1181 KASSERT(amd_pcpu != NULL, ("[amd,%d] NULL per-cpu array pointer",
1182 __LINE__));
1183
1184 #if defined(INVARIANTS)
1185 switch (md->pmd_cputype) {
1186 #if defined(__i386__)
1187 case PMC_CPU_AMD_K7:
1188 classindex = PMC_MDEP_CLASS_INDEX_K7;
1189 pmcclass = PMC_CLASS_K7;
1190 break;
1191 #endif
1192 default:
1193 if (AMD_cpufamily == 0xF) {
1194 classindex = PMC_MDEP_CLASS_INDEX_K8;
1195 pmcclass = PMC_CLASS_K8;
1196 } else if (AMD_cpufamily == 0x17) {
1197 classindex = PMC_MDEP_CLASS_INDEX_F17H;
1198 pmcclass = PMC_CLASS_F17H;
1199 } else {
1200 classindex = PMC_MDEP_CLASS_INDEX_K8;
1201 pmcclass = PMC_CLASS_K8;
1202 (void) printf("pmc:AMD CPU family unknown.\n");
1203 }
1204
1205 }
1206
1207 KASSERT(md->pmd_classdep[classindex].pcd_class == pmcclass,
1208 ("[amd,%d] pmc class mismatch", __LINE__));
1209
1210 ncpus = pmc_cpu_max();
1211
1212 for (i = 0; i < ncpus; i++)
1213 KASSERT(amd_pcpu[i] == NULL, ("[amd,%d] non-null pcpu",
1214 __LINE__));
1215 #endif
1216
1217 free(amd_pcpu, M_PMC);
1218 amd_pcpu = NULL;
1219 }
1220