1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 1991 Regents of the University of California.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * the Systems Programming Group of the University of Utah Computer
10 * Science Department and William Jolitz of UUNET Technologies Inc.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * Derived from hp300 version by Mike Hibler, this version by William
37 * Jolitz uses a recursive map [a pde points to the page directory] to
38 * map the page tables using the pagetables themselves. This is done to
39 * reduce the impact on kernel virtual memory for lots of sparse address
40 * space, and to reduce the cost of memory to each process.
41 *
42 * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90
43 * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91
44 */
45
46 #ifndef _MACHINE_PMAP_H_
47 #define _MACHINE_PMAP_H_
48
49 /*
50 * Page-directory and page-table entries follow this format, with a few
51 * of the fields not present here and there, depending on a lot of things.
52 */
53 /* ---- Intel Nomenclature ---- */
54 #define X86_PG_V 0x001 /* P Valid */
55 #define X86_PG_RW 0x002 /* R/W Read/Write */
56 #define X86_PG_U 0x004 /* U/S User/Supervisor */
57 #define X86_PG_NC_PWT 0x008 /* PWT Write through */
58 #define X86_PG_NC_PCD 0x010 /* PCD Cache disable */
59 #define X86_PG_A 0x020 /* A Accessed */
60 #define X86_PG_M 0x040 /* D Dirty */
61 #define X86_PG_PS 0x080 /* PS Page size (0=4k,1=2M) */
62 #define X86_PG_PTE_PAT 0x080 /* PAT PAT index */
63 #define X86_PG_G 0x100 /* G Global */
64 #define X86_PG_AVAIL1 0x200 /* / Available for system */
65 #define X86_PG_AVAIL2 0x400 /* < programmers use */
66 #define X86_PG_AVAIL3 0x800 /* \ */
67 #define X86_PG_PDE_PAT 0x1000 /* PAT PAT index */
68 #define X86_PG_PKU(idx) ((pt_entry_t)idx << 59)
69 #define X86_PG_NX (1ul<<63) /* No-execute */
70 #define X86_PG_AVAIL(x) (1ul << (x))
71
72 /* Page level cache control fields used to determine the PAT type */
73 #define X86_PG_PDE_CACHE (X86_PG_PDE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD)
74 #define X86_PG_PTE_CACHE (X86_PG_PTE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD)
75
76 /* Protection keys indexes */
77 #define PMAP_MAX_PKRU_IDX 0xf
78 #define X86_PG_PKU_MASK X86_PG_PKU(PMAP_MAX_PKRU_IDX)
79
80 /*
81 * Intel extended page table (EPT) bit definitions.
82 */
83 #define EPT_PG_READ 0x001 /* R Read */
84 #define EPT_PG_WRITE 0x002 /* W Write */
85 #define EPT_PG_EXECUTE 0x004 /* X Execute */
86 #define EPT_PG_IGNORE_PAT 0x040 /* IPAT Ignore PAT */
87 #define EPT_PG_PS 0x080 /* PS Page size */
88 #define EPT_PG_A 0x100 /* A Accessed */
89 #define EPT_PG_M 0x200 /* D Dirty */
90 #define EPT_PG_MEMORY_TYPE(x) ((x) << 3) /* MT Memory Type */
91
92 /*
93 * Define the PG_xx macros in terms of the bits on x86 PTEs.
94 */
95 #define PG_V X86_PG_V
96 #define PG_RW X86_PG_RW
97 #define PG_U X86_PG_U
98 #define PG_NC_PWT X86_PG_NC_PWT
99 #define PG_NC_PCD X86_PG_NC_PCD
100 #define PG_A X86_PG_A
101 #define PG_M X86_PG_M
102 #define PG_PS X86_PG_PS
103 #define PG_PTE_PAT X86_PG_PTE_PAT
104 #define PG_G X86_PG_G
105 #define PG_AVAIL1 X86_PG_AVAIL1
106 #define PG_AVAIL2 X86_PG_AVAIL2
107 #define PG_AVAIL3 X86_PG_AVAIL3
108 #define PG_PDE_PAT X86_PG_PDE_PAT
109 #define PG_NX X86_PG_NX
110 #define PG_PDE_CACHE X86_PG_PDE_CACHE
111 #define PG_PTE_CACHE X86_PG_PTE_CACHE
112
113 /* Our various interpretations of the above */
114 #define PG_W X86_PG_AVAIL3 /* "Wired" pseudoflag */
115 #define PG_MANAGED X86_PG_AVAIL2
116 #define EPT_PG_EMUL_V X86_PG_AVAIL(52)
117 #define EPT_PG_EMUL_RW X86_PG_AVAIL(53)
118 #define PG_PROMOTED X86_PG_AVAIL(54) /* PDE only */
119 #define PG_FRAME (0x000ffffffffff000ul)
120 #define PG_PS_FRAME (0x000fffffffe00000ul)
121 #define PG_PS_PDP_FRAME (0x000fffffc0000000ul)
122
123 /*
124 * Promotion to a 2MB (PDE) page mapping requires that the corresponding 4KB
125 * (PTE) page mappings have identical settings for the following fields:
126 */
127 #define PG_PTE_PROMOTE (PG_NX | PG_MANAGED | PG_W | PG_G | PG_PTE_CACHE | \
128 PG_M | PG_A | PG_U | PG_RW | PG_V | PG_PKU_MASK)
129
130 /*
131 * Page Protection Exception bits
132 */
133
134 #define PGEX_P 0x01 /* Protection violation vs. not present */
135 #define PGEX_W 0x02 /* during a Write cycle */
136 #define PGEX_U 0x04 /* access from User mode (UPL) */
137 #define PGEX_RSV 0x08 /* reserved PTE field is non-zero */
138 #define PGEX_I 0x10 /* during an instruction fetch */
139 #define PGEX_PK 0x20 /* protection key violation */
140 #define PGEX_SGX 0x8000 /* SGX-related */
141
142 /*
143 * undef the PG_xx macros that define bits in the regular x86 PTEs that
144 * have a different position in nested PTEs. This is done when compiling
145 * code that needs to be aware of the differences between regular x86 and
146 * nested PTEs.
147 *
148 * The appropriate bitmask will be calculated at runtime based on the pmap
149 * type.
150 */
151 #ifdef AMD64_NPT_AWARE
152 #undef PG_AVAIL1 /* X86_PG_AVAIL1 aliases with EPT_PG_M */
153 #undef PG_G
154 #undef PG_A
155 #undef PG_M
156 #undef PG_PDE_PAT
157 #undef PG_PDE_CACHE
158 #undef PG_PTE_PAT
159 #undef PG_PTE_CACHE
160 #undef PG_RW
161 #undef PG_V
162 #endif
163
164 /*
165 * Pte related macros. This is complicated by having to deal with
166 * the sign extension of the 48th bit.
167 */
168 #define KV4ADDR(l4, l3, l2, l1) ( \
169 ((unsigned long)-1 << 47) | \
170 ((unsigned long)(l4) << PML4SHIFT) | \
171 ((unsigned long)(l3) << PDPSHIFT) | \
172 ((unsigned long)(l2) << PDRSHIFT) | \
173 ((unsigned long)(l1) << PAGE_SHIFT))
174 #define KV5ADDR(l5, l4, l3, l2, l1) ( \
175 ((unsigned long)-1 << 56) | \
176 ((unsigned long)(l5) << PML5SHIFT) | \
177 ((unsigned long)(l4) << PML4SHIFT) | \
178 ((unsigned long)(l3) << PDPSHIFT) | \
179 ((unsigned long)(l2) << PDRSHIFT) | \
180 ((unsigned long)(l1) << PAGE_SHIFT))
181
182 #define UVADDR(l5, l4, l3, l2, l1) ( \
183 ((unsigned long)(l5) << PML5SHIFT) | \
184 ((unsigned long)(l4) << PML4SHIFT) | \
185 ((unsigned long)(l3) << PDPSHIFT) | \
186 ((unsigned long)(l2) << PDRSHIFT) | \
187 ((unsigned long)(l1) << PAGE_SHIFT))
188
189 /*
190 * Number of kernel PML4 slots. Can be anywhere from 1 to 64 or so,
191 * but setting it larger than NDMPML4E makes no sense.
192 *
193 * Each slot provides .5 TB of kernel virtual space.
194 */
195 #define NKPML4E 4
196
197 /*
198 * Number of PML4 slots for the KASAN shadow map. It requires 1 byte of memory
199 * for every 8 bytes of the kernel address space.
200 */
201 #define NKASANPML4E ((NKPML4E + 7) / 8)
202
203 /*
204 * Number of PML4 slots for the KMSAN shadow and origin maps. These are
205 * one-to-one with the kernel map.
206 */
207 #define NKMSANSHADPML4E NKPML4E
208 #define NKMSANORIGPML4E NKPML4E
209
210 /*
211 * We use the same numbering of the page table pages for 5-level and
212 * 4-level paging structures.
213 */
214 #define NUPML5E (NPML5EPG / 2) /* number of userland PML5
215 pages */
216 #define NUPML4E (NUPML5E * NPML4EPG) /* number of userland PML4
217 pages */
218 #define NUPDPE (NUPML4E * NPDPEPG) /* number of userland PDP
219 pages */
220 #define NUPDE (NUPDPE * NPDEPG) /* number of userland PD
221 entries */
222 #define NUP4ML4E (NPML4EPG / 2)
223
224 /*
225 * NDMPML4E is the maximum number of PML4 entries that will be
226 * used to implement the direct map. It must be a power of two,
227 * and should generally exceed NKPML4E. The maximum possible
228 * value is 64; using 128 will make the direct map intrude into
229 * the recursive page table map.
230 */
231 #define NDMPML4E 8
232
233 /*
234 * These values control the layout of virtual memory. The starting address
235 * of the direct map, which is controlled by DMPML4I, must be a multiple of
236 * its size. (See the PHYS_TO_DMAP() and DMAP_TO_PHYS() macros.)
237 *
238 * Note: KPML4I is the index of the (single) level 4 page that maps
239 * the KVA that holds KERNBASE, while KPML4BASE is the index of the
240 * first level 4 page that maps VM_MIN_KERNEL_ADDRESS. If NKPML4E
241 * is 1, these are the same, otherwise KPML4BASE < KPML4I and extra
242 * level 4 PDEs are needed to map from VM_MIN_KERNEL_ADDRESS up to
243 * KERNBASE.
244 *
245 * (KPML4I combines with KPDPI to choose where KERNBASE starts.
246 * Or, in other words, KPML4I provides bits 39..47 of KERNBASE,
247 * and KPDPI provides bits 30..38.)
248 */
249 #define PML4PML4I (NPML4EPG / 2) /* Index of recursive pml4 mapping */
250 #define PML5PML5I (NPML5EPG / 2) /* Index of recursive pml5 mapping */
251
252 #define KPML4BASE (NPML4EPG-NKPML4E) /* KVM at highest addresses */
253 #define DMPML4I rounddown(KPML4BASE-NDMPML4E, NDMPML4E) /* Below KVM */
254
255 #define KPML4I (NPML4EPG-1)
256 #define KPDPI (NPDPEPG-2) /* kernbase at -2GB */
257
258 #define KASANPML4I (DMPML4I - NKASANPML4E) /* Below the direct map */
259
260 #define KMSANSHADPML4I (KPML4BASE - NKMSANSHADPML4E)
261 #define KMSANORIGPML4I (DMPML4I - NKMSANORIGPML4E)
262
263 /* Large map: index of the first and max last pml4 entry */
264 #define LMSPML4I (PML4PML4I + 1)
265 #define LMEPML4I (KASANPML4I - 1)
266
267 /*
268 * XXX doesn't really belong here I guess...
269 */
270 #define ISA_HOLE_START 0xa0000
271 #define ISA_HOLE_LENGTH (0x100000-ISA_HOLE_START)
272
273 #define PMAP_PCID_NONE 0xffffffff
274 #define PMAP_PCID_KERN 0
275 #define PMAP_PCID_OVERMAX 0x1000
276 #define PMAP_PCID_OVERMAX_KERN 0x800
277 #define PMAP_PCID_USER_PT 0x800
278
279 #define PMAP_NO_CR3 0xffffffffffffffff
280 #define PMAP_UCR3_NOMASK 0xffffffffffffffff
281
282 #ifndef LOCORE
283
284 #include <sys/queue.h>
285 #include <sys/_cpuset.h>
286 #include <sys/_lock.h>
287 #include <sys/_mutex.h>
288 #include <sys/_pctrie.h>
289 #include <sys/_rangeset.h>
290 #include <sys/_smr.h>
291
292 #include <vm/_vm_radix.h>
293
294 typedef u_int64_t pd_entry_t;
295 typedef u_int64_t pt_entry_t;
296 typedef u_int64_t pdp_entry_t;
297 typedef u_int64_t pml4_entry_t;
298 typedef u_int64_t pml5_entry_t;
299
300 /*
301 * Address of current address space page table maps and directories.
302 */
303 #ifdef _KERNEL
304 #define addr_P4Tmap (KV4ADDR(PML4PML4I, 0, 0, 0))
305 #define addr_P4Dmap (KV4ADDR(PML4PML4I, PML4PML4I, 0, 0))
306 #define addr_P4DPmap (KV4ADDR(PML4PML4I, PML4PML4I, PML4PML4I, 0))
307 #define addr_P4ML4map (KV4ADDR(PML4PML4I, PML4PML4I, PML4PML4I, PML4PML4I))
308 #define addr_P4ML4pml4e (addr_PML4map + (PML4PML4I * sizeof(pml4_entry_t)))
309 #define P4Tmap ((pt_entry_t *)(addr_P4Tmap))
310 #define P4Dmap ((pd_entry_t *)(addr_P4Dmap))
311
312 #define addr_P5Tmap (KV5ADDR(PML5PML5I, 0, 0, 0, 0))
313 #define addr_P5Dmap (KV5ADDR(PML5PML5I, PML5PML5I, 0, 0, 0))
314 #define addr_P5DPmap (KV5ADDR(PML5PML5I, PML5PML5I, PML5PML5I, 0, 0))
315 #define addr_P5ML4map (KV5ADDR(PML5PML5I, PML5PML5I, PML5PML5I, PML5PML5I, 0))
316 #define addr_P5ML5map \
317 (KVADDR(PML5PML5I, PML5PML5I, PML5PML5I, PML5PML5I, PML5PML5I))
318 #define addr_P5ML5pml5e (addr_P5ML5map + (PML5PML5I * sizeof(pml5_entry_t)))
319 #define P5Tmap ((pt_entry_t *)(addr_P5Tmap))
320 #define P5Dmap ((pd_entry_t *)(addr_P5Dmap))
321
322 extern int nkpt; /* Initial number of kernel page tables */
323 extern u_int64_t KPML4phys; /* physical address of kernel level 4 */
324 extern u_int64_t KPML5phys; /* physical address of kernel level 5 */
325
326 /*
327 * virtual address to page table entry and
328 * to physical address.
329 * Note: these work recursively, thus vtopte of a pte will give
330 * the corresponding pde that in turn maps it.
331 */
332 pt_entry_t *vtopte(vm_offset_t);
333 #define vtophys(va) pmap_kextract(((vm_offset_t) (va)))
334
335 #define pte_load_store(ptep, pte) atomic_swap_long(ptep, pte)
336 #define pte_load_clear(ptep) atomic_swap_long(ptep, 0)
337 #define pte_store(ptep, pte) do { \
338 *(u_long *)(ptep) = (u_long)(pte); \
339 } while (0)
340 #define pte_clear(ptep) pte_store(ptep, 0)
341
342 #define pde_store(pdep, pde) pte_store(pdep, pde)
343
344 extern pt_entry_t pg_nx;
345
346 #endif /* _KERNEL */
347
348 /*
349 * Pmap stuff
350 */
351 struct pv_entry;
352 struct pv_chunk;
353
354 /*
355 * Locks
356 * (p) PV list lock
357 */
358 struct md_page {
359 TAILQ_HEAD(, pv_entry) pv_list; /* (p) */
360 int pv_gen; /* (p) */
361 int pat_mode;
362 };
363
364 enum pmap_type {
365 PT_X86, /* regular x86 page tables */
366 PT_EPT, /* Intel's nested page tables */
367 PT_RVI, /* AMD's nested page tables */
368 };
369
370 struct pmap_pcids {
371 uint32_t pm_pcid;
372 uint32_t pm_gen;
373 };
374
375 /*
376 * The kernel virtual address (KVA) of the level 4 page table page is always
377 * within the direct map (DMAP) region.
378 */
379 struct pmap {
380 struct mtx pm_mtx;
381 pml4_entry_t *pm_pmltop; /* KVA of top level page table */
382 pml4_entry_t *pm_pmltopu; /* KVA of user top page table */
383 uint64_t pm_cr3;
384 uint64_t pm_ucr3;
385 TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */
386 cpuset_t pm_active; /* active on cpus */
387 enum pmap_type pm_type; /* regular or nested tables */
388 struct pmap_statistics pm_stats; /* pmap statistics */
389 struct vm_radix pm_root; /* spare page table pages */
390 long pm_eptgen; /* EPT pmap generation id */
391 smr_t pm_eptsmr;
392 int pm_flags;
393 struct pmap_pcids pm_pcids[MAXCPU];
394 struct rangeset pm_pkru;
395 };
396
397 /* flags */
398 #define PMAP_NESTED_IPIMASK 0xff
399 #define PMAP_PDE_SUPERPAGE (1 << 8) /* supports 2MB superpages */
400 #define PMAP_EMULATE_AD_BITS (1 << 9) /* needs A/D bits emulation */
401 #define PMAP_SUPPORTS_EXEC_ONLY (1 << 10) /* execute only mappings ok */
402
403 typedef struct pmap *pmap_t;
404
405 #ifdef _KERNEL
406 extern struct pmap kernel_pmap_store;
407 #define kernel_pmap (&kernel_pmap_store)
408
409 #define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx)
410 #define PMAP_LOCK_ASSERT(pmap, type) \
411 mtx_assert(&(pmap)->pm_mtx, (type))
412 #define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx)
413 #define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \
414 NULL, MTX_DEF | MTX_DUPOK)
415 #define PMAP_LOCKED(pmap) mtx_owned(&(pmap)->pm_mtx)
416 #define PMAP_MTX(pmap) (&(pmap)->pm_mtx)
417 #define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx)
418 #define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx)
419
420 int pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags);
421 int pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype);
422 #endif
423
424 /*
425 * For each vm_page_t, there is a list of all currently valid virtual
426 * mappings of that page. An entry is a pv_entry_t, the list is pv_list.
427 */
428 typedef struct pv_entry {
429 vm_offset_t pv_va; /* virtual address for mapping */
430 TAILQ_ENTRY(pv_entry) pv_next;
431 } *pv_entry_t;
432
433 /*
434 * pv_entries are allocated in chunks per-process. This avoids the
435 * need to track per-pmap assignments.
436 */
437 #define _NPCM 3
438 #define _NPCPV 168
439 #define PV_CHUNK_HEADER \
440 pmap_t pc_pmap; \
441 TAILQ_ENTRY(pv_chunk) pc_list; \
442 uint64_t pc_map[_NPCM]; /* bitmap; 1 = free */ \
443 TAILQ_ENTRY(pv_chunk) pc_lru;
444
445 struct pv_chunk_header {
446 PV_CHUNK_HEADER
447 };
448
449 struct pv_chunk {
450 PV_CHUNK_HEADER
451 struct pv_entry pc_pventry[_NPCPV];
452 };
453
454 #ifdef _KERNEL
455
456 extern caddr_t CADDR1;
457 extern pt_entry_t *CMAP1;
458 extern vm_offset_t virtual_avail;
459 extern vm_offset_t virtual_end;
460 extern vm_paddr_t dmaplimit;
461 extern int pmap_pcid_enabled;
462 extern int invpcid_works;
463 extern int pmap_pcid_invlpg_workaround;
464 extern int pmap_pcid_invlpg_workaround_uena;
465
466 #define pmap_page_get_memattr(m) ((vm_memattr_t)(m)->md.pat_mode)
467 #define pmap_page_is_write_mapped(m) (((m)->a.flags & PGA_WRITEABLE) != 0)
468 #define pmap_unmapbios(va, sz) pmap_unmapdev((va), (sz))
469
470 #define pmap_vm_page_alloc_check(m) \
471 KASSERT(m->phys_addr < kernphys || \
472 m->phys_addr >= kernphys + (vm_offset_t)&_end - KERNSTART, \
473 ("allocating kernel page %p pa %#lx kernphys %#lx end %p", \
474 m, m->phys_addr, kernphys, &_end));
475
476 struct thread;
477
478 void pmap_activate_boot(pmap_t pmap);
479 void pmap_activate_sw(struct thread *);
480 void pmap_allow_2m_x_ept_recalculate(void);
481 void pmap_bootstrap(vm_paddr_t *);
482 int pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde);
483 int pmap_change_attr(vm_offset_t, vm_size_t, int);
484 int pmap_change_prot(vm_offset_t, vm_size_t, vm_prot_t);
485 void pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate);
486 void pmap_flush_cache_range(vm_offset_t, vm_offset_t);
487 void pmap_flush_cache_phys_range(vm_paddr_t, vm_paddr_t, vm_memattr_t);
488 void pmap_init_pat(void);
489 void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
490 void *pmap_kenter_temporary(vm_paddr_t pa, int i);
491 vm_paddr_t pmap_kextract(vm_offset_t);
492 void pmap_kremove(vm_offset_t);
493 int pmap_large_map(vm_paddr_t, vm_size_t, void **, vm_memattr_t);
494 void pmap_large_map_wb(void *sva, vm_size_t len);
495 void pmap_large_unmap(void *sva, vm_size_t len);
496 void *pmap_mapbios(vm_paddr_t, vm_size_t);
497 void *pmap_mapdev(vm_paddr_t, vm_size_t);
498 void *pmap_mapdev_attr(vm_paddr_t, vm_size_t, int);
499 void *pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size);
500 bool pmap_not_in_di(void);
501 boolean_t pmap_page_is_mapped(vm_page_t m);
502 void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma);
503 void pmap_page_set_memattr_noflush(vm_page_t m, vm_memattr_t ma);
504 void pmap_pinit_pml4(vm_page_t);
505 void pmap_pinit_pml5(vm_page_t);
506 bool pmap_ps_enabled(pmap_t pmap);
507 void pmap_unmapdev(vm_offset_t, vm_size_t);
508 void pmap_invalidate_page(pmap_t, vm_offset_t);
509 void pmap_invalidate_range(pmap_t, vm_offset_t, vm_offset_t);
510 void pmap_invalidate_all(pmap_t);
511 void pmap_invalidate_cache(void);
512 void pmap_invalidate_cache_pages(vm_page_t *pages, int count);
513 void pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva);
514 void pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva);
515 void pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num);
516 boolean_t pmap_map_io_transient(vm_page_t *, vm_offset_t *, int, boolean_t);
517 void pmap_unmap_io_transient(vm_page_t *, vm_offset_t *, int, boolean_t);
518 void pmap_map_delete(pmap_t, vm_offset_t, vm_offset_t);
519 void pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec);
520 void pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva);
521 void pmap_pti_pcid_invalidate(uint64_t ucr3, uint64_t kcr3);
522 void pmap_pti_pcid_invlpg(uint64_t ucr3, uint64_t kcr3, vm_offset_t va);
523 void pmap_pti_pcid_invlrng(uint64_t ucr3, uint64_t kcr3, vm_offset_t sva,
524 vm_offset_t eva);
525 int pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
526 int pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
527 u_int keyidx, int flags);
528 void pmap_thread_init_invl_gen(struct thread *td);
529 int pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap);
530 void pmap_page_array_startup(long count);
531 vm_page_t pmap_page_alloc_below_4g(bool zeroed);
532
533 #ifdef KASAN
534 void pmap_kasan_enter(vm_offset_t);
535 #endif
536 #ifdef KMSAN
537 void pmap_kmsan_enter(vm_offset_t);
538 #endif
539
540 /*
541 * Returns a pointer to a set of CPUs on which the pmap is currently active.
542 * Note that the set can be modified without any mutual exclusion, so a copy
543 * must be made if a stable value is required.
544 */
545 static __inline volatile cpuset_t *
pmap_invalidate_cpu_mask(pmap_t pmap)546 pmap_invalidate_cpu_mask(pmap_t pmap)
547 {
548 return (&pmap->pm_active);
549 }
550
551 #if defined(_SYS_PCPU_H_) && defined(_MACHINE_CPUFUNC_H_)
552 /*
553 * It seems that AlderLake+ small cores have some microarchitectural
554 * bug, which results in the INVLPG instruction failing to flush all
555 * global TLB entries when PCID is enabled. Work around it for now,
556 * by doing global invalidation on small cores instead of INVLPG.
557 */
558 static __inline void
pmap_invlpg(pmap_t pmap,vm_offset_t va)559 pmap_invlpg(pmap_t pmap, vm_offset_t va)
560 {
561 if (pmap == kernel_pmap && PCPU_GET(pcid_invlpg_workaround)) {
562 struct invpcid_descr d = { 0 };
563
564 invpcid(&d, INVPCID_CTXGLOB);
565 } else {
566 invlpg(va);
567 }
568 }
569 #endif /* sys/pcpu.h && machine/cpufunc.h */
570
571 #endif /* _KERNEL */
572
573 /* Return various clipped indexes for a given VA */
574 static __inline vm_pindex_t
pmap_pte_index(vm_offset_t va)575 pmap_pte_index(vm_offset_t va)
576 {
577
578 return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1));
579 }
580
581 static __inline vm_pindex_t
pmap_pde_index(vm_offset_t va)582 pmap_pde_index(vm_offset_t va)
583 {
584
585 return ((va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1));
586 }
587
588 static __inline vm_pindex_t
pmap_pdpe_index(vm_offset_t va)589 pmap_pdpe_index(vm_offset_t va)
590 {
591
592 return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1));
593 }
594
595 static __inline vm_pindex_t
pmap_pml4e_index(vm_offset_t va)596 pmap_pml4e_index(vm_offset_t va)
597 {
598
599 return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1));
600 }
601
602 static __inline vm_pindex_t
pmap_pml5e_index(vm_offset_t va)603 pmap_pml5e_index(vm_offset_t va)
604 {
605
606 return ((va >> PML5SHIFT) & ((1ul << NPML5EPGSHIFT) - 1));
607 }
608
609 #endif /* !LOCORE */
610
611 #endif /* !_MACHINE_PMAP_H_ */
612