1 /* 2 * Copyright © 2012-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DPLL_MGR_H_ 26 #define _INTEL_DPLL_MGR_H_ 27 28 /*FIXME: Move this to a more appropriate place. */ 29 #define abs_diff(a, b) ({ \ 30 typeof(a) __a = (a); \ 31 typeof(b) __b = (b); \ 32 (void) (&__a == &__b); \ 33 __a > __b ? (__a - __b) : (__b - __a); }) 34 35 struct drm_i915_private; 36 struct intel_crtc; 37 struct intel_crtc_state; 38 struct intel_encoder; 39 40 struct intel_shared_dpll; 41 struct intel_dpll_mgr; 42 43 /** 44 * enum intel_dpll_id - possible DPLL ids 45 * 46 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0. 47 */ 48 enum intel_dpll_id { 49 /** 50 * @DPLL_ID_PRIVATE: non-shared dpll in use 51 */ 52 DPLL_ID_PRIVATE = -1, 53 54 /** 55 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB 56 */ 57 DPLL_ID_PCH_PLL_A = 0, 58 /** 59 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB 60 */ 61 DPLL_ID_PCH_PLL_B = 1, 62 63 64 /** 65 * @DPLL_ID_WRPLL1: HSW and BDW WRPLL1 66 */ 67 DPLL_ID_WRPLL1 = 0, 68 /** 69 * @DPLL_ID_WRPLL2: HSW and BDW WRPLL2 70 */ 71 DPLL_ID_WRPLL2 = 1, 72 /** 73 * @DPLL_ID_SPLL: HSW and BDW SPLL 74 */ 75 DPLL_ID_SPLL = 2, 76 /** 77 * @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL 78 */ 79 DPLL_ID_LCPLL_810 = 3, 80 /** 81 * @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL 82 */ 83 DPLL_ID_LCPLL_1350 = 4, 84 /** 85 * @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL 86 */ 87 DPLL_ID_LCPLL_2700 = 5, 88 89 90 /** 91 * @DPLL_ID_SKL_DPLL0: SKL and later DPLL0 92 */ 93 DPLL_ID_SKL_DPLL0 = 0, 94 /** 95 * @DPLL_ID_SKL_DPLL1: SKL and later DPLL1 96 */ 97 DPLL_ID_SKL_DPLL1 = 1, 98 /** 99 * @DPLL_ID_SKL_DPLL2: SKL and later DPLL2 100 */ 101 DPLL_ID_SKL_DPLL2 = 2, 102 /** 103 * @DPLL_ID_SKL_DPLL3: SKL and later DPLL3 104 */ 105 DPLL_ID_SKL_DPLL3 = 3, 106 }; 107 #define I915_NUM_PLLS 6 108 109 struct intel_dpll_hw_state { 110 /* i9xx, pch plls */ 111 uint32_t dpll; 112 uint32_t dpll_md; 113 uint32_t fp0; 114 uint32_t fp1; 115 116 /* hsw, bdw */ 117 uint32_t wrpll; 118 uint32_t spll; 119 120 /* skl */ 121 /* 122 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in 123 * lower part of ctrl1 and they get shifted into position when writing 124 * the register. This allows us to easily compare the state to share 125 * the DPLL. 126 */ 127 uint32_t ctrl1; 128 /* HDMI only, 0 when used for DP */ 129 uint32_t cfgcr1, cfgcr2; 130 131 /* cnl */ 132 uint32_t cfgcr0; 133 /* CNL also uses cfgcr1 */ 134 135 /* bxt */ 136 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, 137 pcsdw12; 138 }; 139 140 /** 141 * struct intel_shared_dpll_state - hold the DPLL atomic state 142 * 143 * This structure holds an atomic state for the DPLL, that can represent 144 * either its current state (in struct &intel_shared_dpll) or a desired 145 * future state which would be applied by an atomic mode set (stored in 146 * a struct &intel_atomic_state). 147 * 148 * See also intel_get_shared_dpll() and intel_release_shared_dpll(). 149 */ 150 struct intel_shared_dpll_state { 151 /** 152 * @crtc_mask: mask of CRTC using this DPLL, active or not 153 */ 154 unsigned crtc_mask; 155 156 /** 157 * @hw_state: hardware configuration for the DPLL stored in 158 * struct &intel_dpll_hw_state. 159 */ 160 struct intel_dpll_hw_state hw_state; 161 }; 162 163 /** 164 * struct intel_shared_dpll_funcs - platform specific hooks for managing DPLLs 165 */ 166 struct intel_shared_dpll_funcs { 167 /** 168 * @prepare: 169 * 170 * Optional hook to perform operations prior to enabling the PLL. 171 * Called from intel_prepare_shared_dpll() function unless the PLL 172 * is already enabled. 173 */ 174 void (*prepare)(struct drm_i915_private *dev_priv, 175 struct intel_shared_dpll *pll); 176 177 /** 178 * @enable: 179 * 180 * Hook for enabling the pll, called from intel_enable_shared_dpll() 181 * if the pll is not already enabled. 182 */ 183 void (*enable)(struct drm_i915_private *dev_priv, 184 struct intel_shared_dpll *pll); 185 186 /** 187 * @disable: 188 * 189 * Hook for disabling the pll, called from intel_disable_shared_dpll() 190 * only when it is safe to disable the pll, i.e., there are no more 191 * tracked users for it. 192 */ 193 void (*disable)(struct drm_i915_private *dev_priv, 194 struct intel_shared_dpll *pll); 195 196 /** 197 * @get_hw_state: 198 * 199 * Hook for reading the values currently programmed to the DPLL 200 * registers. This is used for initial hw state readout and state 201 * verification after a mode set. 202 */ 203 bool (*get_hw_state)(struct drm_i915_private *dev_priv, 204 struct intel_shared_dpll *pll, 205 struct intel_dpll_hw_state *hw_state); 206 }; 207 208 /** 209 * struct intel_shared_dpll - display PLL with tracked state and users 210 */ 211 struct intel_shared_dpll { 212 /** 213 * @state: 214 * 215 * Store the state for the pll, including the its hw state 216 * and CRTCs using it. 217 */ 218 struct intel_shared_dpll_state state; 219 220 /** 221 * @active_mask: mask of active CRTCs (i.e. DPMS on) using this DPLL 222 */ 223 unsigned active_mask; 224 225 /** 226 * @on: is the PLL actually active? Disabled during modeset 227 */ 228 bool on; 229 230 /** 231 * @name: DPLL name; used for logging 232 */ 233 const char *name; 234 235 /** 236 * @id: unique indentifier for this DPLL; should match the index in the 237 * dev_priv->shared_dplls array 238 */ 239 enum intel_dpll_id id; 240 241 /** 242 * @funcs: platform specific hooks 243 */ 244 struct intel_shared_dpll_funcs funcs; 245 246 #define INTEL_DPLL_ALWAYS_ON (1 << 0) 247 /** 248 * @flags: 249 * 250 * INTEL_DPLL_ALWAYS_ON 251 * Inform the state checker that the DPLL is kept enabled even if 252 * not in use by any CRTC. 253 */ 254 uint32_t flags; 255 }; 256 257 #define SKL_DPLL0 0 258 #define SKL_DPLL1 1 259 #define SKL_DPLL2 2 260 #define SKL_DPLL3 3 261 262 /* shared dpll functions */ 263 struct intel_shared_dpll * 264 intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, 265 enum intel_dpll_id id); 266 enum intel_dpll_id 267 intel_get_shared_dpll_id(struct drm_i915_private *dev_priv, 268 struct intel_shared_dpll *pll); 269 void assert_shared_dpll(struct drm_i915_private *dev_priv, 270 struct intel_shared_dpll *pll, 271 bool state); 272 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) 273 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) 274 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, 275 struct intel_crtc_state *state, 276 struct intel_encoder *encoder); 277 void intel_release_shared_dpll(struct intel_shared_dpll *dpll, 278 struct intel_crtc *crtc, 279 struct drm_atomic_state *state); 280 void intel_prepare_shared_dpll(struct intel_crtc *crtc); 281 void intel_enable_shared_dpll(struct intel_crtc *crtc); 282 void intel_disable_shared_dpll(struct intel_crtc *crtc); 283 void intel_shared_dpll_swap_state(struct drm_atomic_state *state); 284 void intel_shared_dpll_init(struct drm_device *dev); 285 286 void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, 287 struct intel_dpll_hw_state *hw_state); 288 289 #endif /* _INTEL_DPLL_MGR_H_ */ 290