1 /*- 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #ifndef _I915_DRM_H_ 31 #define _I915_DRM_H_ 32 33 /* Please note that modifications to all structs defined here are 34 * subject to backwards-compatibility constraints. 35 */ 36 37 #include <dev/drm2/drm.h> 38 39 /* Each region is a minimum of 16k, and there are at most 255 of them. 40 */ 41 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 42 * of chars for next/prev indices */ 43 #define I915_LOG_MIN_TEX_REGION_SIZE 14 44 45 typedef struct _drm_i915_init { 46 enum { 47 I915_INIT_DMA = 0x01, 48 I915_CLEANUP_DMA = 0x02, 49 I915_RESUME_DMA = 0x03, 50 51 /* Since this struct isn't versioned, just used a new 52 * 'func' code to indicate the presence of dri2 sarea 53 * info. */ 54 I915_INIT_DMA2 = 0x04 55 } func; 56 unsigned int mmio_offset; 57 int sarea_priv_offset; 58 unsigned int ring_start; 59 unsigned int ring_end; 60 unsigned int ring_size; 61 unsigned int front_offset; 62 unsigned int back_offset; 63 unsigned int depth_offset; 64 unsigned int w; 65 unsigned int h; 66 unsigned int pitch; 67 unsigned int pitch_bits; 68 unsigned int back_pitch; 69 unsigned int depth_pitch; 70 unsigned int cpp; 71 unsigned int chipset; 72 unsigned int sarea_handle; 73 } drm_i915_init_t; 74 75 typedef struct _drm_i915_sarea { 76 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 77 int last_upload; /* last time texture was uploaded */ 78 int last_enqueue; /* last time a buffer was enqueued */ 79 int last_dispatch; /* age of the most recently dispatched buffer */ 80 int ctxOwner; /* last context to upload state */ 81 int texAge; 82 int pf_enabled; /* is pageflipping allowed? */ 83 int pf_active; 84 int pf_current_page; /* which buffer is being displayed? */ 85 int perf_boxes; /* performance boxes to be displayed */ 86 int width, height; /* screen size in pixels */ 87 88 drm_handle_t front_handle; 89 int front_offset; 90 int front_size; 91 92 drm_handle_t back_handle; 93 int back_offset; 94 int back_size; 95 96 drm_handle_t depth_handle; 97 int depth_offset; 98 int depth_size; 99 100 drm_handle_t tex_handle; 101 int tex_offset; 102 int tex_size; 103 int log_tex_granularity; 104 int pitch; 105 int rotation; /* 0, 90, 180 or 270 */ 106 int rotated_offset; 107 int rotated_size; 108 int rotated_pitch; 109 int virtualX, virtualY; 110 111 unsigned int front_tiled; 112 unsigned int back_tiled; 113 unsigned int depth_tiled; 114 unsigned int rotated_tiled; 115 unsigned int rotated2_tiled; 116 117 int pipeA_x; 118 int pipeA_y; 119 int pipeA_w; 120 int pipeA_h; 121 int pipeB_x; 122 int pipeB_y; 123 int pipeB_w; 124 int pipeB_h; 125 126 /* Triple buffering */ 127 drm_handle_t third_handle; 128 int third_offset; 129 int third_size; 130 unsigned int third_tiled; 131 132 /* buffer object handles for the static buffers. May change 133 * over the lifetime of the client, though it doesn't in our current 134 * implementation. 135 */ 136 unsigned int front_bo_handle; 137 unsigned int back_bo_handle; 138 unsigned int third_bo_handle; 139 unsigned int depth_bo_handle; 140 } drm_i915_sarea_t; 141 142 /* due to userspace building against these headers we need some compat here */ 143 #define planeA_x pipeA_x 144 #define planeA_y pipeA_y 145 #define planeA_w pipeA_w 146 #define planeA_h pipeA_h 147 #define planeB_x pipeB_x 148 #define planeB_y pipeB_y 149 #define planeB_w pipeB_w 150 #define planeB_h pipeB_h 151 152 /* Driver specific fence types and classes. 153 */ 154 155 /* The only fence class we support */ 156 #define DRM_I915_FENCE_CLASS_ACCEL 0 157 /* Fence type that guarantees read-write flush */ 158 #define DRM_I915_FENCE_TYPE_RW 2 159 /* MI_FLUSH programmed just before the fence */ 160 #define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000 161 162 /* Flags for perf_boxes 163 */ 164 #define I915_BOX_RING_EMPTY 0x1 165 #define I915_BOX_FLIP 0x2 166 #define I915_BOX_WAIT 0x4 167 #define I915_BOX_TEXTURE_LOAD 0x8 168 #define I915_BOX_LOST_CONTEXT 0x10 169 170 /* I915 specific ioctls 171 * The device specific ioctl range is 0x40 to 0x79. 172 */ 173 #define DRM_I915_INIT 0x00 174 #define DRM_I915_FLUSH 0x01 175 #define DRM_I915_FLIP 0x02 176 #define DRM_I915_BATCHBUFFER 0x03 177 #define DRM_I915_IRQ_EMIT 0x04 178 #define DRM_I915_IRQ_WAIT 0x05 179 #define DRM_I915_GETPARAM 0x06 180 #define DRM_I915_SETPARAM 0x07 181 #define DRM_I915_ALLOC 0x08 182 #define DRM_I915_FREE 0x09 183 #define DRM_I915_INIT_HEAP 0x0a 184 #define DRM_I915_CMDBUFFER 0x0b 185 #define DRM_I915_DESTROY_HEAP 0x0c 186 #define DRM_I915_SET_VBLANK_PIPE 0x0d 187 #define DRM_I915_GET_VBLANK_PIPE 0x0e 188 #define DRM_I915_VBLANK_SWAP 0x0f 189 #define DRM_I915_MMIO 0x10 190 #define DRM_I915_HWS_ADDR 0x11 191 #define DRM_I915_EXECBUFFER 0x12 192 #define DRM_I915_GEM_INIT 0x13 193 #define DRM_I915_GEM_EXECBUFFER 0x14 194 #define DRM_I915_GEM_PIN 0x15 195 #define DRM_I915_GEM_UNPIN 0x16 196 #define DRM_I915_GEM_BUSY 0x17 197 #define DRM_I915_GEM_THROTTLE 0x18 198 #define DRM_I915_GEM_ENTERVT 0x19 199 #define DRM_I915_GEM_LEAVEVT 0x1a 200 #define DRM_I915_GEM_CREATE 0x1b 201 #define DRM_I915_GEM_PREAD 0x1c 202 #define DRM_I915_GEM_PWRITE 0x1d 203 #define DRM_I915_GEM_MMAP 0x1e 204 #define DRM_I915_GEM_SET_DOMAIN 0x1f 205 #define DRM_I915_GEM_SW_FINISH 0x20 206 #define DRM_I915_GEM_SET_TILING 0x21 207 #define DRM_I915_GEM_GET_TILING 0x22 208 #define DRM_I915_GEM_GET_APERTURE 0x23 209 #define DRM_I915_GEM_MMAP_GTT 0x24 210 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 211 #define DRM_I915_GEM_MADVISE 0x26 212 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 213 #define DRM_I915_OVERLAY_ATTRS 0x28 214 #define DRM_I915_GEM_EXECBUFFER2 0x29 215 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 216 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 217 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 218 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 219 220 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 221 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 222 #define DRM_IOCTL_I915_FLIP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t) 223 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 224 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 225 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 226 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 227 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 228 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 229 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 230 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 231 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 232 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 233 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 234 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 235 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 236 #define DRM_IOCTL_I915_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio) 237 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 238 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 239 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 240 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 241 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 242 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 243 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 244 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 245 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 246 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 247 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 248 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 249 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 250 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 251 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 252 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 253 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 254 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 255 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 256 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 257 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 258 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 259 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 260 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 261 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 262 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 263 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 264 265 /* Asynchronous page flipping: 266 */ 267 typedef struct drm_i915_flip { 268 /* 269 * This is really talking about planes, and we could rename it 270 * except for the fact that some of the duplicated i915_drm.h files 271 * out there check for HAVE_I915_FLIP and so might pick up this 272 * version. 273 */ 274 int pipes; 275 } drm_i915_flip_t; 276 277 /* Allow drivers to submit batchbuffers directly to hardware, relying 278 * on the security mechanisms provided by hardware. 279 */ 280 typedef struct drm_i915_batchbuffer { 281 int start; /* agp offset */ 282 int used; /* nr bytes in use */ 283 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 284 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 285 int num_cliprects; /* mulitpass with multiple cliprects? */ 286 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 287 } drm_i915_batchbuffer_t; 288 289 /* As above, but pass a pointer to userspace buffer which can be 290 * validated by the kernel prior to sending to hardware. 291 */ 292 typedef struct _drm_i915_cmdbuffer { 293 char __user *buf; /* pointer to userspace command buffer */ 294 int sz; /* nr bytes in buf */ 295 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 296 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 297 int num_cliprects; /* mulitpass with multiple cliprects? */ 298 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 299 } drm_i915_cmdbuffer_t; 300 301 /* Userspace can request & wait on irq's: 302 */ 303 typedef struct drm_i915_irq_emit { 304 int __user *irq_seq; 305 } drm_i915_irq_emit_t; 306 307 typedef struct drm_i915_irq_wait { 308 int irq_seq; 309 } drm_i915_irq_wait_t; 310 311 /* Ioctl to query kernel params: 312 */ 313 #define I915_PARAM_IRQ_ACTIVE 1 314 #define I915_PARAM_ALLOW_BATCHBUFFER 2 315 #define I915_PARAM_LAST_DISPATCH 3 316 #define I915_PARAM_CHIPSET_ID 4 317 #define I915_PARAM_HAS_GEM 5 318 #define I915_PARAM_NUM_FENCES_AVAIL 6 319 #define I915_PARAM_HAS_OVERLAY 7 320 #define I915_PARAM_HAS_PAGEFLIPPING 8 321 #define I915_PARAM_HAS_EXECBUF2 9 322 #define I915_PARAM_HAS_BSD 10 323 #define I915_PARAM_HAS_BLT 11 324 #define I915_PARAM_HAS_RELAXED_FENCING 12 325 #define I915_PARAM_HAS_COHERENT_RINGS 13 326 #define I915_PARAM_HAS_EXEC_CONSTANTS 14 327 #define I915_PARAM_HAS_RELAXED_DELTA 15 328 #define I915_PARAM_HAS_GEN7_SOL_RESET 16 329 #define I915_PARAM_HAS_LLC 17 330 #define I915_PARAM_HAS_ALIASING_PPGTT 18 331 332 typedef struct drm_i915_getparam { 333 int param; 334 int __user *value; 335 } drm_i915_getparam_t; 336 337 /* Ioctl to set kernel params: 338 */ 339 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 340 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 341 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 342 #define I915_SETPARAM_NUM_USED_FENCES 4 343 344 typedef struct drm_i915_setparam { 345 int param; 346 int value; 347 } drm_i915_setparam_t; 348 349 /* A memory manager for regions of shared memory: 350 */ 351 #define I915_MEM_REGION_AGP 1 352 353 typedef struct drm_i915_mem_alloc { 354 int region; 355 int alignment; 356 int size; 357 int __user *region_offset; /* offset from start of fb or agp */ 358 } drm_i915_mem_alloc_t; 359 360 typedef struct drm_i915_mem_free { 361 int region; 362 int region_offset; 363 } drm_i915_mem_free_t; 364 365 typedef struct drm_i915_mem_init_heap { 366 int region; 367 int size; 368 int start; 369 } drm_i915_mem_init_heap_t; 370 371 /* Allow memory manager to be torn down and re-initialized (eg on 372 * rotate): 373 */ 374 typedef struct drm_i915_mem_destroy_heap { 375 int region; 376 } drm_i915_mem_destroy_heap_t; 377 378 /* Allow X server to configure which pipes to monitor for vblank signals 379 */ 380 #define DRM_I915_VBLANK_PIPE_A 1 381 #define DRM_I915_VBLANK_PIPE_B 2 382 383 typedef struct drm_i915_vblank_pipe { 384 int pipe; 385 } drm_i915_vblank_pipe_t; 386 387 /* Schedule buffer swap at given vertical blank: 388 */ 389 typedef struct drm_i915_vblank_swap { 390 drm_drawable_t drawable; 391 enum drm_vblank_seq_type seqtype; 392 unsigned int sequence; 393 } drm_i915_vblank_swap_t; 394 395 #define I915_MMIO_READ 0 396 #define I915_MMIO_WRITE 1 397 398 #define I915_MMIO_MAY_READ 0x1 399 #define I915_MMIO_MAY_WRITE 0x2 400 401 #define MMIO_REGS_IA_PRIMATIVES_COUNT 0 402 #define MMIO_REGS_IA_VERTICES_COUNT 1 403 #define MMIO_REGS_VS_INVOCATION_COUNT 2 404 #define MMIO_REGS_GS_PRIMITIVES_COUNT 3 405 #define MMIO_REGS_GS_INVOCATION_COUNT 4 406 #define MMIO_REGS_CL_PRIMITIVES_COUNT 5 407 #define MMIO_REGS_CL_INVOCATION_COUNT 6 408 #define MMIO_REGS_PS_INVOCATION_COUNT 7 409 #define MMIO_REGS_PS_DEPTH_COUNT 8 410 411 typedef struct drm_i915_mmio_entry { 412 unsigned int flag; 413 unsigned int offset; 414 unsigned int size; 415 } drm_i915_mmio_entry_t; 416 417 typedef struct drm_i915_mmio { 418 unsigned int read_write:1; 419 unsigned int reg:31; 420 void __user *data; 421 } drm_i915_mmio_t; 422 423 typedef struct drm_i915_hws_addr { 424 uint64_t addr; 425 } drm_i915_hws_addr_t; 426 427 /* 428 * Relocation header is 4 uint32_ts 429 * 0 - 32 bit reloc count 430 * 1 - 32-bit relocation type 431 * 2-3 - 64-bit user buffer handle ptr for another list of relocs. 432 */ 433 #define I915_RELOC_HEADER 4 434 435 /* 436 * type 0 relocation has 4-uint32_t stride 437 * 0 - offset into buffer 438 * 1 - delta to add in 439 * 2 - buffer handle 440 * 3 - reserved (for optimisations later). 441 */ 442 /* 443 * type 1 relocation has 4-uint32_t stride. 444 * Hangs off the first item in the op list. 445 * Performed after all valiations are done. 446 * Try to group relocs into the same relocatee together for 447 * performance reasons. 448 * 0 - offset into buffer 449 * 1 - delta to add in 450 * 2 - buffer index in op list. 451 * 3 - relocatee index in op list. 452 */ 453 #define I915_RELOC_TYPE_0 0 454 #define I915_RELOC0_STRIDE 4 455 #define I915_RELOC_TYPE_1 1 456 #define I915_RELOC1_STRIDE 4 457 458 459 struct drm_i915_gem_init { 460 /** 461 * Beginning offset in the GTT to be managed by the DRM memory 462 * manager. 463 */ 464 uint64_t gtt_start; 465 /** 466 * Ending offset in the GTT to be managed by the DRM memory 467 * manager. 468 */ 469 uint64_t gtt_end; 470 }; 471 472 struct drm_i915_gem_create { 473 /** 474 * Requested size for the object. 475 * 476 * The (page-aligned) allocated size for the object will be returned. 477 */ 478 uint64_t size; 479 /** 480 * Returned handle for the object. 481 * 482 * Object handles are nonzero. 483 */ 484 uint32_t handle; 485 uint32_t pad; 486 }; 487 488 struct drm_i915_gem_pread { 489 /** Handle for the object being read. */ 490 uint32_t handle; 491 uint32_t pad; 492 /** Offset into the object to read from */ 493 uint64_t offset; 494 /** Length of data to read */ 495 uint64_t size; 496 /** Pointer to write the data into. */ 497 uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */ 498 }; 499 500 struct drm_i915_gem_pwrite { 501 /** Handle for the object being written to. */ 502 uint32_t handle; 503 uint32_t pad; 504 /** Offset into the object to write to */ 505 uint64_t offset; 506 /** Length of data to write */ 507 uint64_t size; 508 /** Pointer to read the data from. */ 509 uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */ 510 }; 511 512 struct drm_i915_gem_mmap { 513 /** Handle for the object being mapped. */ 514 uint32_t handle; 515 uint32_t pad; 516 /** Offset in the object to map. */ 517 uint64_t offset; 518 /** 519 * Length of data to map. 520 * 521 * The value will be page-aligned. 522 */ 523 uint64_t size; 524 /** Returned pointer the data was mapped at */ 525 uint64_t addr_ptr; /* void *, but pointers are not 32/64 compatible */ 526 }; 527 528 struct drm_i915_gem_mmap_gtt { 529 /** Handle for the object being mapped. */ 530 uint32_t handle; 531 uint32_t pad; 532 /** 533 * Fake offset to use for subsequent mmap call 534 * 535 * This is a fixed-size type for 32/64 compatibility. 536 */ 537 uint64_t offset; 538 }; 539 540 struct drm_i915_gem_set_domain { 541 /** Handle for the object */ 542 uint32_t handle; 543 544 /** New read domains */ 545 uint32_t read_domains; 546 547 /** New write domain */ 548 uint32_t write_domain; 549 }; 550 551 struct drm_i915_gem_sw_finish { 552 /** Handle for the object */ 553 uint32_t handle; 554 }; 555 556 struct drm_i915_gem_relocation_entry { 557 /** 558 * Handle of the buffer being pointed to by this relocation entry. 559 * 560 * It's appealing to make this be an index into the mm_validate_entry 561 * list to refer to the buffer, but this allows the driver to create 562 * a relocation list for state buffers and not re-write it per 563 * exec using the buffer. 564 */ 565 uint32_t target_handle; 566 567 /** 568 * Value to be added to the offset of the target buffer to make up 569 * the relocation entry. 570 */ 571 uint32_t delta; 572 573 /** Offset in the buffer the relocation entry will be written into */ 574 uint64_t offset; 575 576 /** 577 * Offset value of the target buffer that the relocation entry was last 578 * written as. 579 * 580 * If the buffer has the same offset as last time, we can skip syncing 581 * and writing the relocation. This value is written back out by 582 * the execbuffer ioctl when the relocation is written. 583 */ 584 uint64_t presumed_offset; 585 586 /** 587 * Target memory domains read by this operation. 588 */ 589 uint32_t read_domains; 590 591 /** 592 * Target memory domains written by this operation. 593 * 594 * Note that only one domain may be written by the whole 595 * execbuffer operation, so that where there are conflicts, 596 * the application will get -EINVAL back. 597 */ 598 uint32_t write_domain; 599 }; 600 601 /** @{ 602 * Intel memory domains 603 * 604 * Most of these just align with the various caches in 605 * the system and are used to flush and invalidate as 606 * objects end up cached in different domains. 607 */ 608 /** CPU cache */ 609 #define I915_GEM_DOMAIN_CPU 0x00000001 610 /** Render cache, used by 2D and 3D drawing */ 611 #define I915_GEM_DOMAIN_RENDER 0x00000002 612 /** Sampler cache, used by texture engine */ 613 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 614 /** Command queue, used to load batch buffers */ 615 #define I915_GEM_DOMAIN_COMMAND 0x00000008 616 /** Instruction cache, used by shader programs */ 617 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 618 /** Vertex address cache */ 619 #define I915_GEM_DOMAIN_VERTEX 0x00000020 620 /** GTT domain - aperture and scanout */ 621 #define I915_GEM_DOMAIN_GTT 0x00000040 622 /** @} */ 623 624 struct drm_i915_gem_exec_object { 625 /** 626 * User's handle for a buffer to be bound into the GTT for this 627 * operation. 628 */ 629 uint32_t handle; 630 631 /** Number of relocations to be performed on this buffer */ 632 uint32_t relocation_count; 633 /** 634 * Pointer to array of struct drm_i915_gem_relocation_entry containing 635 * the relocations to be performed in this buffer. 636 */ 637 uint64_t relocs_ptr; 638 639 /** Required alignment in graphics aperture */ 640 uint64_t alignment; 641 642 /** 643 * Returned value of the updated offset of the object, for future 644 * presumed_offset writes. 645 */ 646 uint64_t offset; 647 }; 648 649 struct drm_i915_gem_execbuffer { 650 /** 651 * List of buffers to be validated with their relocations to be 652 * performend on them. 653 * 654 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 655 * 656 * These buffers must be listed in an order such that all relocations 657 * a buffer is performing refer to buffers that have already appeared 658 * in the validate list. 659 */ 660 uint64_t buffers_ptr; 661 uint32_t buffer_count; 662 663 /** Offset in the batchbuffer to start execution from. */ 664 uint32_t batch_start_offset; 665 /** Bytes used in batchbuffer from batch_start_offset */ 666 uint32_t batch_len; 667 uint32_t DR1; 668 uint32_t DR4; 669 uint32_t num_cliprects; 670 uint64_t cliprects_ptr; /* struct drm_clip_rect *cliprects */ 671 }; 672 673 struct drm_i915_gem_exec_object2 { 674 /** 675 * User's handle for a buffer to be bound into the GTT for this 676 * operation. 677 */ 678 uint32_t handle; 679 680 /** Number of relocations to be performed on this buffer */ 681 uint32_t relocation_count; 682 /** 683 * Pointer to array of struct drm_i915_gem_relocation_entry containing 684 * the relocations to be performed in this buffer. 685 */ 686 uint64_t relocs_ptr; 687 688 /** Required alignment in graphics aperture */ 689 uint64_t alignment; 690 691 /** 692 * Returned value of the updated offset of the object, for future 693 * presumed_offset writes. 694 */ 695 uint64_t offset; 696 697 #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 698 uint64_t flags; 699 uint64_t rsvd1; /* now used for context info */ 700 uint64_t rsvd2; 701 }; 702 703 struct drm_i915_gem_execbuffer2 { 704 /** 705 * List of gem_exec_object2 structs 706 */ 707 uint64_t buffers_ptr; 708 uint32_t buffer_count; 709 710 /** Offset in the batchbuffer to start execution from. */ 711 uint32_t batch_start_offset; 712 /** Bytes used in batchbuffer from batch_start_offset */ 713 uint32_t batch_len; 714 uint32_t DR1; 715 uint32_t DR4; 716 uint32_t num_cliprects; 717 /** This is a struct drm_clip_rect *cliprects */ 718 uint64_t cliprects_ptr; 719 #define I915_EXEC_RING_MASK (7<<0) 720 #define I915_EXEC_DEFAULT (0<<0) 721 #define I915_EXEC_RENDER (1<<0) 722 #define I915_EXEC_BSD (2<<0) 723 #define I915_EXEC_BLT (3<<0) 724 725 /* Used for switching the constants addressing mode on gen4+ RENDER ring. 726 * Gen6+ only supports relative addressing to dynamic state (default) and 727 * absolute addressing. 728 * 729 * These flags are ignored for the BSD and BLT rings. 730 */ 731 #define I915_EXEC_CONSTANTS_MASK (3<<6) 732 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 733 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 734 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 735 uint64_t flags; 736 uint64_t rsvd1; 737 uint64_t rsvd2; 738 }; 739 740 /** Resets the SO write offset registers for transform feedback on gen7. */ 741 #define I915_EXEC_GEN7_SOL_RESET (1<<8) 742 743 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 744 #define i915_execbuffer2_set_context_id(eb2, context) \ 745 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 746 #define i915_execbuffer2_get_context_id(eb2) \ 747 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 748 749 struct drm_i915_gem_pin { 750 /** Handle of the buffer to be pinned. */ 751 uint32_t handle; 752 uint32_t pad; 753 754 /** alignment required within the aperture */ 755 uint64_t alignment; 756 757 /** Returned GTT offset of the buffer. */ 758 uint64_t offset; 759 }; 760 761 struct drm_i915_gem_unpin { 762 /** Handle of the buffer to be unpinned. */ 763 uint32_t handle; 764 uint32_t pad; 765 }; 766 767 struct drm_i915_gem_busy { 768 /** Handle of the buffer to check for busy */ 769 uint32_t handle; 770 771 /** Return busy status (1 if busy, 0 if idle) */ 772 uint32_t busy; 773 }; 774 775 #define I915_TILING_NONE 0 776 #define I915_TILING_X 1 777 #define I915_TILING_Y 2 778 779 #define I915_BIT_6_SWIZZLE_NONE 0 780 #define I915_BIT_6_SWIZZLE_9 1 781 #define I915_BIT_6_SWIZZLE_9_10 2 782 #define I915_BIT_6_SWIZZLE_9_11 3 783 #define I915_BIT_6_SWIZZLE_9_10_11 4 784 /* Not seen by userland */ 785 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 786 /* Seen by userland. */ 787 #define I915_BIT_6_SWIZZLE_9_17 6 788 #define I915_BIT_6_SWIZZLE_9_10_17 7 789 790 struct drm_i915_gem_set_tiling { 791 /** Handle of the buffer to have its tiling state updated */ 792 uint32_t handle; 793 794 /** 795 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 796 * I915_TILING_Y). 797 * 798 * This value is to be set on request, and will be updated by the 799 * kernel on successful return with the actual chosen tiling layout. 800 * 801 * The tiling mode may be demoted to I915_TILING_NONE when the system 802 * has bit 6 swizzling that can't be managed correctly by GEM. 803 * 804 * Buffer contents become undefined when changing tiling_mode. 805 */ 806 uint32_t tiling_mode; 807 808 /** 809 * Stride in bytes for the object when in I915_TILING_X or 810 * I915_TILING_Y. 811 */ 812 uint32_t stride; 813 814 /** 815 * Returned address bit 6 swizzling required for CPU access through 816 * mmap mapping. 817 */ 818 uint32_t swizzle_mode; 819 }; 820 821 struct drm_i915_gem_get_tiling { 822 /** Handle of the buffer to get tiling state for. */ 823 uint32_t handle; 824 825 /** 826 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 827 * I915_TILING_Y). 828 */ 829 uint32_t tiling_mode; 830 831 /** 832 * Returned address bit 6 swizzling required for CPU access through 833 * mmap mapping. 834 */ 835 uint32_t swizzle_mode; 836 }; 837 838 struct drm_i915_gem_get_aperture { 839 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 840 uint64_t aper_size; 841 842 /** 843 * Available space in the aperture used by i915_gem_execbuffer, in 844 * bytes 845 */ 846 uint64_t aper_available_size; 847 }; 848 849 struct drm_i915_get_pipe_from_crtc_id { 850 /** ID of CRTC being requested **/ 851 uint32_t crtc_id; 852 853 /** pipe of requested CRTC **/ 854 uint32_t pipe; 855 }; 856 857 #define I915_MADV_WILLNEED 0 858 #define I915_MADV_DONTNEED 1 859 #define I915_MADV_PURGED_INTERNAL 2 /* internal state */ 860 861 struct drm_i915_gem_madvise { 862 /** Handle of the buffer to change the backing store advice */ 863 uint32_t handle; 864 865 /* Advice: either the buffer will be needed again in the near future, 866 * or wont be and could be discarded under memory pressure. 867 */ 868 uint32_t madv; 869 870 /** Whether the backing store still exists. */ 871 uint32_t retained; 872 }; 873 874 #define I915_OVERLAY_TYPE_MASK 0xff 875 #define I915_OVERLAY_YUV_PLANAR 0x01 876 #define I915_OVERLAY_YUV_PACKED 0x02 877 #define I915_OVERLAY_RGB 0x03 878 879 #define I915_OVERLAY_DEPTH_MASK 0xff00 880 #define I915_OVERLAY_RGB24 0x1000 881 #define I915_OVERLAY_RGB16 0x2000 882 #define I915_OVERLAY_RGB15 0x3000 883 #define I915_OVERLAY_YUV422 0x0100 884 #define I915_OVERLAY_YUV411 0x0200 885 #define I915_OVERLAY_YUV420 0x0300 886 #define I915_OVERLAY_YUV410 0x0400 887 888 #define I915_OVERLAY_SWAP_MASK 0xff0000 889 #define I915_OVERLAY_NO_SWAP 0x000000 890 #define I915_OVERLAY_UV_SWAP 0x010000 891 #define I915_OVERLAY_Y_SWAP 0x020000 892 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 893 894 #define I915_OVERLAY_FLAGS_MASK 0xff000000 895 #define I915_OVERLAY_ENABLE 0x01000000 896 897 struct drm_intel_overlay_put_image { 898 /* various flags and src format description */ 899 uint32_t flags; 900 /* source picture description */ 901 uint32_t bo_handle; 902 /* stride values and offsets are in bytes, buffer relative */ 903 uint16_t stride_Y; /* stride for packed formats */ 904 uint16_t stride_UV; 905 uint32_t offset_Y; /* offset for packet formats */ 906 uint32_t offset_U; 907 uint32_t offset_V; 908 /* in pixels */ 909 uint16_t src_width; 910 uint16_t src_height; 911 /* to compensate the scaling factors for partially covered surfaces */ 912 uint16_t src_scan_width; 913 uint16_t src_scan_height; 914 /* output crtc description */ 915 uint32_t crtc_id; 916 uint16_t dst_x; 917 uint16_t dst_y; 918 uint16_t dst_width; 919 uint16_t dst_height; 920 }; 921 922 /* flags */ 923 #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 924 #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 925 struct drm_intel_overlay_attrs { 926 uint32_t flags; 927 uint32_t color_key; 928 int32_t brightness; 929 uint32_t contrast; 930 uint32_t saturation; 931 uint32_t gamma0; 932 uint32_t gamma1; 933 uint32_t gamma2; 934 uint32_t gamma3; 935 uint32_t gamma4; 936 uint32_t gamma5; 937 }; 938 939 /* 940 * Intel sprite handling 941 * 942 * Color keying works with a min/mask/max tuple. Both source and destination 943 * color keying is allowed. 944 * 945 * Source keying: 946 * Sprite pixels within the min & max values, masked against the color channels 947 * specified in the mask field, will be transparent. All other pixels will 948 * be displayed on top of the primary plane. For RGB surfaces, only the min 949 * and mask fields will be used; ranged compares are not allowed. 950 * 951 * Destination keying: 952 * Primary plane pixels that match the min value, masked against the color 953 * channels specified in the mask field, will be replaced by corresponding 954 * pixels from the sprite plane. 955 * 956 * Note that source & destination keying are exclusive; only one can be 957 * active on a given plane. 958 */ 959 960 #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ 961 #define I915_SET_COLORKEY_DESTINATION (1<<1) 962 #define I915_SET_COLORKEY_SOURCE (1<<2) 963 struct drm_intel_sprite_colorkey { 964 uint32_t plane_id; 965 uint32_t min_value; 966 uint32_t channel_mask; 967 uint32_t max_value; 968 uint32_t flags; 969 }; 970 971 struct drm_i915_gem_context_create { 972 /* output: id of new context*/ 973 uint32_t ctx_id; 974 uint32_t pad; 975 }; 976 977 struct drm_i915_gem_context_destroy { 978 uint32_t ctx_id; 979 uint32_t pad; 980 }; 981 982 #endif /* _I915_DRM_H_ */ 983