1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: stable/12/sys/x86/include/intr_machdep.h 367457 2020-11-07 18:10:59Z dim $ 28 */ 29 30 #ifndef __X86_INTR_MACHDEP_H__ 31 #define __X86_INTR_MACHDEP_H__ 32 33 #ifdef _KERNEL 34 35 /* 36 * Values used in determining the allocation of IRQ values among 37 * different types of I/O interrupts. These values are used as 38 * indices into a interrupt source array to map I/O interrupts to a 39 * device interrupt source whether it be a pin on an interrupt 40 * controller or an MSI interrupt. The 16 ISA IRQs are assigned fixed 41 * IDT vectors, but all other device interrupts allocate IDT vectors 42 * on demand. Currently we have 191 IDT vectors available for device 43 * interrupts on each CPU. On many systems with I/O APICs, a lot of 44 * the IRQs are not used, so the total number of IRQ values reserved 45 * can exceed the number of available IDT slots. 46 * 47 * The first 16 IRQs (0 - 15) are reserved for ISA IRQs. Interrupt 48 * pins on I/O APICs for non-ISA interrupts use IRQ values starting at 49 * IRQ 17. This layout matches the GSI numbering used by ACPI so that 50 * IRQ values returned by ACPI methods such as _CRS can be used 51 * directly by the ACPI bus driver. 52 * 53 * MSI interrupts allocate a block of interrupts starting at either 54 * the end of the I/O APIC range or 256, whichever is higher. When 55 * running under the Xen Hypervisor, an additional range of IRQ values 56 * are available for binding to event channel events. We use 256 as 57 * the minimum IRQ value for MSI interrupts to attempt to leave 255 58 * unused since 255 is used in PCI to indicate an invalid INTx IRQ. 59 */ 60 #define MINIMUM_MSI_INT 256 61 62 extern u_int first_msi_irq; 63 extern u_int num_io_irqs; 64 extern u_int num_msi_irqs; 65 66 /* 67 * Default base address for MSI messages on x86 platforms. 68 */ 69 #define MSI_INTEL_ADDR_BASE 0xfee00000 70 71 #ifndef LOCORE 72 73 typedef void inthand_t(void); 74 75 #define IDTVEC(name) __CONCAT(X,name) 76 77 struct intsrc; 78 79 /* 80 * Methods that a PIC provides to mask/unmask a given interrupt source, 81 * "turn on" the interrupt on the CPU side by setting up an IDT entry, and 82 * return the vector associated with this source. 83 */ 84 struct pic { 85 void (*pic_register_sources)(struct pic *); 86 void (*pic_enable_source)(struct intsrc *); 87 void (*pic_disable_source)(struct intsrc *, int); 88 void (*pic_eoi_source)(struct intsrc *); 89 void (*pic_enable_intr)(struct intsrc *); 90 void (*pic_disable_intr)(struct intsrc *); 91 int (*pic_vector)(struct intsrc *); 92 int (*pic_source_pending)(struct intsrc *); 93 void (*pic_suspend)(struct pic *); 94 void (*pic_resume)(struct pic *, bool suspend_cancelled); 95 int (*pic_config_intr)(struct intsrc *, enum intr_trigger, 96 enum intr_polarity); 97 int (*pic_assign_cpu)(struct intsrc *, u_int apic_id); 98 void (*pic_reprogram_pin)(struct intsrc *); 99 TAILQ_ENTRY(pic) pics; 100 }; 101 102 /* Flags for pic_disable_source() */ 103 enum { 104 PIC_EOI, 105 PIC_NO_EOI, 106 }; 107 108 /* 109 * An interrupt source. The upper-layer code uses the PIC methods to 110 * control a given source. The lower-layer PIC drivers can store additional 111 * private data in a given interrupt source such as an interrupt pin number 112 * or an I/O APIC pointer. 113 */ 114 struct intsrc { 115 struct pic *is_pic; 116 struct intr_event *is_event; 117 u_long *is_count; 118 u_long *is_straycount; 119 u_int is_index; 120 u_int is_handlers; 121 u_int is_domain; 122 u_int is_cpu; 123 }; 124 125 struct trapframe; 126 127 #ifdef SMP 128 extern cpuset_t intr_cpus; 129 #endif 130 extern struct mtx icu_lock; 131 extern int elcr_found; 132 #ifdef SMP 133 extern int msix_disable_migration; 134 #endif 135 136 #ifndef DEV_ATPIC 137 void atpic_reset(void); 138 #endif 139 /* XXX: The elcr_* prototypes probably belong somewhere else. */ 140 int elcr_probe(void); 141 enum intr_trigger elcr_read_trigger(u_int irq); 142 void elcr_resume(void); 143 void elcr_write_trigger(u_int irq, enum intr_trigger trigger); 144 #ifdef SMP 145 void intr_add_cpu(u_int cpu); 146 #endif 147 int intr_add_handler(const char *name, int vector, driver_filter_t filter, 148 driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep, 149 int domain); 150 #ifdef SMP 151 int intr_bind(u_int vector, u_char cpu); 152 #endif 153 int intr_config_intr(int vector, enum intr_trigger trig, 154 enum intr_polarity pol); 155 int intr_describe(u_int vector, void *ih, const char *descr); 156 void intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame); 157 u_int intr_next_cpu(int domain); 158 struct intsrc *intr_lookup_source(int vector); 159 int intr_register_pic(struct pic *pic); 160 int intr_register_source(struct intsrc *isrc); 161 int intr_remove_handler(void *cookie); 162 void intr_resume(bool suspend_cancelled); 163 void intr_suspend(void); 164 void intr_reprogram(void); 165 void intrcnt_add(const char *name, u_long **countp); 166 void nexus_add_irq(u_long irq); 167 int msi_alloc(device_t dev, int count, int maxcount, int *irqs); 168 void msi_init(void); 169 int msi_map(int irq, uint64_t *addr, uint32_t *data); 170 int msi_release(int *irqs, int count); 171 int msix_alloc(device_t dev, int *irq); 172 int msix_release(int irq); 173 #ifdef XENHVM 174 void xen_intr_alloc_irqs(void); 175 #endif 176 177 #endif /* !LOCORE */ 178 #endif /* _KERNEL */ 179 #endif /* !__X86_INTR_MACHDEP_H__ */ 180