1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2011 NetApp, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 */
30
31 #ifndef _PCI_EMUL_H_
32 #define _PCI_EMUL_H_
33
34 #include <sys/types.h>
35 #include <sys/queue.h>
36 #include <sys/kernel.h>
37 #include <sys/_pthreadtypes.h>
38
39 #include <dev/pci/pcireg.h>
40
41 #include <assert.h>
42
43 #define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */
44
45 struct vmctx;
46 struct pci_devinst;
47 struct memory_region;
48
49 struct pci_devemu {
50 char *pe_emu; /* Name of device emulation */
51
52 /* instance creation */
53 int (*pe_init)(struct vmctx *, struct pci_devinst *,
54 char *opts);
55
56 /* ACPI DSDT enumeration */
57 void (*pe_write_dsdt)(struct pci_devinst *);
58
59 /* config space read/write callbacks */
60 int (*pe_cfgwrite)(struct vmctx *ctx, int vcpu,
61 struct pci_devinst *pi, int offset,
62 int bytes, uint32_t val);
63 int (*pe_cfgread)(struct vmctx *ctx, int vcpu,
64 struct pci_devinst *pi, int offset,
65 int bytes, uint32_t *retval);
66
67 /* BAR read/write callbacks */
68 void (*pe_barwrite)(struct vmctx *ctx, int vcpu,
69 struct pci_devinst *pi, int baridx,
70 uint64_t offset, int size, uint64_t value);
71 uint64_t (*pe_barread)(struct vmctx *ctx, int vcpu,
72 struct pci_devinst *pi, int baridx,
73 uint64_t offset, int size);
74 };
75 #define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x);
76
77 enum pcibar_type {
78 PCIBAR_NONE,
79 PCIBAR_IO,
80 PCIBAR_MEM32,
81 PCIBAR_MEM64,
82 PCIBAR_MEMHI64
83 };
84
85 struct pcibar {
86 enum pcibar_type type; /* io or memory */
87 uint64_t size;
88 uint64_t addr;
89 };
90
91 #define PI_NAMESZ 40
92
93 struct msix_table_entry {
94 uint64_t addr;
95 uint32_t msg_data;
96 uint32_t vector_control;
97 } __packed;
98
99 /*
100 * In case the structure is modified to hold extra information, use a define
101 * for the size that should be emulated.
102 */
103 #define MSIX_TABLE_ENTRY_SIZE 16
104 #define MAX_MSIX_TABLE_ENTRIES 2048
105 #define PBA_SIZE(msgnum) (roundup2((msgnum), 64) / 8)
106
107 enum lintr_stat {
108 IDLE,
109 ASSERTED,
110 PENDING
111 };
112
113 struct pci_devinst {
114 struct pci_devemu *pi_d;
115 struct vmctx *pi_vmctx;
116 uint8_t pi_bus, pi_slot, pi_func;
117 char pi_name[PI_NAMESZ];
118 int pi_bar_getsize;
119 int pi_prevcap;
120 int pi_capend;
121
122 struct {
123 int8_t pin;
124 enum lintr_stat state;
125 int pirq_pin;
126 int ioapic_irq;
127 pthread_mutex_t lock;
128 } pi_lintr;
129
130 struct {
131 int enabled;
132 uint64_t addr;
133 uint64_t msg_data;
134 int maxmsgnum;
135 } pi_msi;
136
137 struct {
138 int enabled;
139 int table_bar;
140 int pba_bar;
141 uint32_t table_offset;
142 int table_count;
143 uint32_t pba_offset;
144 int pba_size;
145 int function_mask;
146 struct msix_table_entry *table; /* allocated at runtime */
147 void *pba_page;
148 int pba_page_offset;
149 } pi_msix;
150
151 void *pi_arg; /* devemu-private data */
152
153 u_char pi_cfgdata[PCI_REGMAX + 1];
154 struct pcibar pi_bar[PCI_BARMAX + 1];
155 };
156
157 struct msicap {
158 uint8_t capid;
159 uint8_t nextptr;
160 uint16_t msgctrl;
161 uint32_t addrlo;
162 uint32_t addrhi;
163 uint16_t msgdata;
164 } __packed;
165 static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed");
166
167 struct msixcap {
168 uint8_t capid;
169 uint8_t nextptr;
170 uint16_t msgctrl;
171 uint32_t table_info; /* bar index and offset within it */
172 uint32_t pba_info; /* bar index and offset within it */
173 } __packed;
174 static_assert(sizeof(struct msixcap) == 12, "compile-time assertion failed");
175
176 struct pciecap {
177 uint8_t capid;
178 uint8_t nextptr;
179 uint16_t pcie_capabilities;
180
181 uint32_t dev_capabilities; /* all devices */
182 uint16_t dev_control;
183 uint16_t dev_status;
184
185 uint32_t link_capabilities; /* devices with links */
186 uint16_t link_control;
187 uint16_t link_status;
188
189 uint32_t slot_capabilities; /* ports with slots */
190 uint16_t slot_control;
191 uint16_t slot_status;
192
193 uint16_t root_control; /* root ports */
194 uint16_t root_capabilities;
195 uint32_t root_status;
196
197 uint32_t dev_capabilities2; /* all devices */
198 uint16_t dev_control2;
199 uint16_t dev_status2;
200
201 uint32_t link_capabilities2; /* devices with links */
202 uint16_t link_control2;
203 uint16_t link_status2;
204
205 uint32_t slot_capabilities2; /* ports with slots */
206 uint16_t slot_control2;
207 uint16_t slot_status2;
208 } __packed;
209 static_assert(sizeof(struct pciecap) == 60, "compile-time assertion failed");
210
211 typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin,
212 int ioapic_irq, void *arg);
213
214 int init_pci(struct vmctx *ctx);
215 void msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
216 int bytes, uint32_t val);
217 void msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
218 int bytes, uint32_t val);
219 void pci_callback(void);
220 int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx,
221 enum pcibar_type type, uint64_t size);
222 int pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx,
223 uint64_t hostbase, enum pcibar_type type, uint64_t size);
224 int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum);
225 int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type);
226 void pci_generate_msi(struct pci_devinst *pi, int msgnum);
227 void pci_generate_msix(struct pci_devinst *pi, int msgnum);
228 void pci_lintr_assert(struct pci_devinst *pi);
229 void pci_lintr_deassert(struct pci_devinst *pi);
230 void pci_lintr_request(struct pci_devinst *pi);
231 int pci_msi_enabled(struct pci_devinst *pi);
232 int pci_msix_enabled(struct pci_devinst *pi);
233 int pci_msix_table_bar(struct pci_devinst *pi);
234 int pci_msix_pba_bar(struct pci_devinst *pi);
235 int pci_msi_maxmsgnum(struct pci_devinst *pi);
236 int pci_parse_slot(char *opt);
237 void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr);
238 int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum);
239 int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
240 uint64_t value);
241 uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size);
242 int pci_count_lintr(int bus);
243 void pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg);
244 void pci_write_dsdt(void);
245 uint64_t pci_ecfg_base(void);
246 int pci_bus_configured(int bus);
247
248 static __inline void
pci_set_cfgdata8(struct pci_devinst * pi,int offset,uint8_t val)249 pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val)
250 {
251 assert(offset <= PCI_REGMAX);
252 *(uint8_t *)(pi->pi_cfgdata + offset) = val;
253 }
254
255 static __inline void
pci_set_cfgdata16(struct pci_devinst * pi,int offset,uint16_t val)256 pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val)
257 {
258 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
259 *(uint16_t *)(pi->pi_cfgdata + offset) = val;
260 }
261
262 static __inline void
pci_set_cfgdata32(struct pci_devinst * pi,int offset,uint32_t val)263 pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val)
264 {
265 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
266 *(uint32_t *)(pi->pi_cfgdata + offset) = val;
267 }
268
269 static __inline uint8_t
pci_get_cfgdata8(struct pci_devinst * pi,int offset)270 pci_get_cfgdata8(struct pci_devinst *pi, int offset)
271 {
272 assert(offset <= PCI_REGMAX);
273 return (*(uint8_t *)(pi->pi_cfgdata + offset));
274 }
275
276 static __inline uint16_t
pci_get_cfgdata16(struct pci_devinst * pi,int offset)277 pci_get_cfgdata16(struct pci_devinst *pi, int offset)
278 {
279 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
280 return (*(uint16_t *)(pi->pi_cfgdata + offset));
281 }
282
283 static __inline uint32_t
pci_get_cfgdata32(struct pci_devinst * pi,int offset)284 pci_get_cfgdata32(struct pci_devinst *pi, int offset)
285 {
286 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
287 return (*(uint32_t *)(pi->pi_cfgdata + offset));
288 }
289
290 #endif /* _PCI_EMUL_H_ */
291