1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
6 * Copyright (c) 2000, BSDi
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice unmodified, this list of conditions, and the following
14 * disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD: stable/12/sys/dev/pci/pci.c 372478 2022-09-06 05:50:03Z gbe $");
33
34 #include "opt_bus.h"
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
40 #include <sys/limits.h>
41 #include <sys/linker.h>
42 #include <sys/fcntl.h>
43 #include <sys/conf.h>
44 #include <sys/kernel.h>
45 #include <sys/queue.h>
46 #include <sys/sysctl.h>
47 #include <sys/endian.h>
48
49 #include <vm/vm.h>
50 #include <vm/pmap.h>
51 #include <vm/vm_extern.h>
52
53 #include <sys/bus.h>
54 #include <machine/bus.h>
55 #include <sys/rman.h>
56 #include <machine/resource.h>
57 #include <machine/stdarg.h>
58
59 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
60 #include <machine/intr_machdep.h>
61 #endif
62
63 #include <sys/pciio.h>
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcivar.h>
66 #include <dev/pci/pci_private.h>
67
68 #ifdef PCI_IOV
69 #include <sys/nv.h>
70 #include <dev/pci/pci_iov_private.h>
71 #endif
72
73 #include <dev/usb/controller/xhcireg.h>
74 #include <dev/usb/controller/ehcireg.h>
75 #include <dev/usb/controller/ohcireg.h>
76 #include <dev/usb/controller/uhcireg.h>
77
78 #include "pcib_if.h"
79 #include "pci_if.h"
80
81 #define PCIR_IS_BIOS(cfg, reg) \
82 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \
83 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1))
84
85 static int pci_has_quirk(uint32_t devid, int quirk);
86 static pci_addr_t pci_mapbase(uint64_t mapreg);
87 static const char *pci_maptype(uint64_t mapreg);
88 static int pci_maprange(uint64_t mapreg);
89 static pci_addr_t pci_rombase(uint64_t mapreg);
90 static int pci_romsize(uint64_t testval);
91 static void pci_fixancient(pcicfgregs *cfg);
92 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...);
93
94 static int pci_porten(device_t dev);
95 static int pci_memen(device_t dev);
96 static void pci_assign_interrupt(device_t bus, device_t dev,
97 int force_route);
98 static int pci_add_map(device_t bus, device_t dev, int reg,
99 struct resource_list *rl, int force, int prefetch);
100 static int pci_probe(device_t dev);
101 static void pci_load_vendor_data(void);
102 static int pci_describe_parse_line(char **ptr, int *vendor,
103 int *device, char **desc);
104 static char *pci_describe_device(device_t dev);
105 static int pci_modevent(module_t mod, int what, void *arg);
106 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
107 pcicfgregs *cfg);
108 static void pci_read_cap(device_t pcib, pcicfgregs *cfg);
109 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
110 int reg, uint32_t *data);
111 #if 0
112 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
113 int reg, uint32_t data);
114 #endif
115 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
116 static void pci_mask_msix(device_t dev, u_int index);
117 static void pci_unmask_msix(device_t dev, u_int index);
118 static int pci_msi_blacklisted(void);
119 static int pci_msix_blacklisted(void);
120 static void pci_resume_msi(device_t dev);
121 static void pci_resume_msix(device_t dev);
122 static int pci_remap_intr_method(device_t bus, device_t dev,
123 u_int irq);
124 static void pci_hint_device_unit(device_t acdev, device_t child,
125 const char *name, int *unitp);
126 static int pci_reset_post(device_t dev, device_t child);
127 static int pci_reset_prepare(device_t dev, device_t child);
128 static int pci_reset_child(device_t dev, device_t child,
129 int flags);
130
131 static int pci_get_id_method(device_t dev, device_t child,
132 enum pci_id_type type, uintptr_t *rid);
133
134 static struct pci_devinfo * pci_fill_devinfo(device_t pcib, device_t bus, int d,
135 int b, int s, int f, uint16_t vid, uint16_t did);
136
137 static device_method_t pci_methods[] = {
138 /* Device interface */
139 DEVMETHOD(device_probe, pci_probe),
140 DEVMETHOD(device_attach, pci_attach),
141 DEVMETHOD(device_detach, pci_detach),
142 DEVMETHOD(device_shutdown, bus_generic_shutdown),
143 DEVMETHOD(device_suspend, bus_generic_suspend),
144 DEVMETHOD(device_resume, pci_resume),
145
146 /* Bus interface */
147 DEVMETHOD(bus_print_child, pci_print_child),
148 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
149 DEVMETHOD(bus_read_ivar, pci_read_ivar),
150 DEVMETHOD(bus_write_ivar, pci_write_ivar),
151 DEVMETHOD(bus_driver_added, pci_driver_added),
152 DEVMETHOD(bus_setup_intr, pci_setup_intr),
153 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
154 DEVMETHOD(bus_reset_prepare, pci_reset_prepare),
155 DEVMETHOD(bus_reset_post, pci_reset_post),
156 DEVMETHOD(bus_reset_child, pci_reset_child),
157
158 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag),
159 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
160 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
161 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
162 DEVMETHOD(bus_delete_resource, pci_delete_resource),
163 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
164 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
165 DEVMETHOD(bus_release_resource, pci_release_resource),
166 DEVMETHOD(bus_activate_resource, pci_activate_resource),
167 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
168 DEVMETHOD(bus_child_deleted, pci_child_deleted),
169 DEVMETHOD(bus_child_detached, pci_child_detached),
170 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
171 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
172 DEVMETHOD(bus_hint_device_unit, pci_hint_device_unit),
173 DEVMETHOD(bus_remap_intr, pci_remap_intr_method),
174 DEVMETHOD(bus_suspend_child, pci_suspend_child),
175 DEVMETHOD(bus_resume_child, pci_resume_child),
176 DEVMETHOD(bus_rescan, pci_rescan_method),
177
178 /* PCI interface */
179 DEVMETHOD(pci_read_config, pci_read_config_method),
180 DEVMETHOD(pci_write_config, pci_write_config_method),
181 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
182 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
183 DEVMETHOD(pci_enable_io, pci_enable_io_method),
184 DEVMETHOD(pci_disable_io, pci_disable_io_method),
185 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
186 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
187 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
188 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
189 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
190 DEVMETHOD(pci_find_cap, pci_find_cap_method),
191 DEVMETHOD(pci_find_next_cap, pci_find_next_cap_method),
192 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
193 DEVMETHOD(pci_find_next_extcap, pci_find_next_extcap_method),
194 DEVMETHOD(pci_find_htcap, pci_find_htcap_method),
195 DEVMETHOD(pci_find_next_htcap, pci_find_next_htcap_method),
196 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
197 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
198 DEVMETHOD(pci_enable_msi, pci_enable_msi_method),
199 DEVMETHOD(pci_enable_msix, pci_enable_msix_method),
200 DEVMETHOD(pci_disable_msi, pci_disable_msi_method),
201 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
202 DEVMETHOD(pci_release_msi, pci_release_msi_method),
203 DEVMETHOD(pci_msi_count, pci_msi_count_method),
204 DEVMETHOD(pci_msix_count, pci_msix_count_method),
205 DEVMETHOD(pci_msix_pba_bar, pci_msix_pba_bar_method),
206 DEVMETHOD(pci_msix_table_bar, pci_msix_table_bar_method),
207 DEVMETHOD(pci_get_id, pci_get_id_method),
208 DEVMETHOD(pci_alloc_devinfo, pci_alloc_devinfo_method),
209 DEVMETHOD(pci_child_added, pci_child_added_method),
210 #ifdef PCI_IOV
211 DEVMETHOD(pci_iov_attach, pci_iov_attach_method),
212 DEVMETHOD(pci_iov_detach, pci_iov_detach_method),
213 DEVMETHOD(pci_create_iov_child, pci_create_iov_child_method),
214 #endif
215
216 DEVMETHOD_END
217 };
218
219 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc));
220
221 static devclass_t pci_devclass;
222 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL);
223 MODULE_VERSION(pci, 1);
224
225 static char *pci_vendordata;
226 static size_t pci_vendordata_size;
227
228 struct pci_quirk {
229 uint32_t devid; /* Vendor/device of the card */
230 int type;
231 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
232 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */
233 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */
234 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */
235 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */
236 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */
237 #define PCI_QUIRK_REALLOC_BAR 7 /* Can't allocate memory at the default address */
238 int arg1;
239 int arg2;
240 };
241
242 static const struct pci_quirk pci_quirks[] = {
243 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */
244 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
245 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
246 /* As does the Serverworks OSB4 (the SMBus mapping register) */
247 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
248
249 /*
250 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
251 * or the CMIC-SL (AKA ServerWorks GC_LE).
252 */
253 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
254 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
255
256 /*
257 * MSI doesn't work on earlier Intel chipsets including
258 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
259 */
260 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
261 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
262 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
263 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
264 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
265 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
266 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
267
268 /*
269 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
270 * bridge.
271 */
272 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
273
274 /*
275 * MSI-X allocation doesn't work properly for devices passed through
276 * by VMware up to at least ESXi 5.1.
277 */
278 { 0x079015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCI/PCI-X */
279 { 0x07a015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCIe */
280
281 /*
282 * Some virtualization environments emulate an older chipset
283 * but support MSI just fine. QEMU uses the Intel 82440.
284 */
285 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 },
286
287 /*
288 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus
289 * controller depending on SoftPciRst register (PM_IO 0x55 [7]).
290 * It prevents us from attaching hpet(4) when the bit is unset.
291 * Note this quirk only affects SB600 revision A13 and earlier.
292 * For SB600 A21 and later, firmware must set the bit to hide it.
293 * For SB700 and later, it is unused and hardcoded to zero.
294 */
295 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 },
296
297 /*
298 * Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have
299 * a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit
300 * of the command register is set.
301 */
302 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
303 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
304 { 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
305 { 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
306 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
307
308 /*
309 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't
310 * issue MSI interrupts with PCIM_CMD_INTxDIS set either.
311 */
312 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */
313 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */
314 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */
315 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */
316 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */
317 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */
318
319 /*
320 * HPE Gen 10 VGA has a memory range that can't be allocated in the
321 * expected place.
322 */
323 { 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0 },
324
325 { 0 }
326 };
327
328 /* map register information */
329 #define PCI_MAPMEM 0x01 /* memory map */
330 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
331 #define PCI_MAPPORT 0x04 /* port map */
332
333 struct devlist pci_devq;
334 uint32_t pci_generation;
335 uint32_t pci_numdevs = 0;
336 static int pcie_chipset, pcix_chipset;
337
338 /* sysctl vars */
339 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
340
341 static int pci_enable_io_modes = 1;
342 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RWTUN,
343 &pci_enable_io_modes, 1,
344 "Enable I/O and memory bits in the config register. Some BIOSes do not"
345 " enable these bits correctly. We'd like to do this all the time, but"
346 " there are some peripherals that this causes problems with.");
347
348 static int pci_do_realloc_bars = 0;
349 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RWTUN,
350 &pci_do_realloc_bars, 0,
351 "Attempt to allocate a new range for any BARs whose original "
352 "firmware-assigned ranges fail to allocate during the initial device scan.");
353
354 static int pci_do_power_nodriver = 0;
355 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RWTUN,
356 &pci_do_power_nodriver, 0,
357 "Place a function into D3 state when no driver attaches to it. 0 means"
358 " disable. 1 means conservatively place devices into D3 state. 2 means"
359 " aggressively place devices into D3 state. 3 means put absolutely"
360 " everything in D3 state.");
361
362 int pci_do_power_resume = 1;
363 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RWTUN,
364 &pci_do_power_resume, 1,
365 "Transition from D3 -> D0 on resume.");
366
367 int pci_do_power_suspend = 1;
368 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RWTUN,
369 &pci_do_power_suspend, 1,
370 "Transition from D0 -> D3 on suspend.");
371
372 static int pci_do_msi = 1;
373 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RWTUN, &pci_do_msi, 1,
374 "Enable support for MSI interrupts");
375
376 static int pci_do_msix = 1;
377 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RWTUN, &pci_do_msix, 1,
378 "Enable support for MSI-X interrupts");
379
380 static int pci_msix_rewrite_table = 0;
381 SYSCTL_INT(_hw_pci, OID_AUTO, msix_rewrite_table, CTLFLAG_RWTUN,
382 &pci_msix_rewrite_table, 0,
383 "Rewrite entire MSI-X table when updating MSI-X entries");
384
385 static int pci_honor_msi_blacklist = 1;
386 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RDTUN,
387 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X");
388
389 #if defined(__i386__) || defined(__amd64__)
390 static int pci_usb_takeover = 1;
391 #else
392 static int pci_usb_takeover = 0;
393 #endif
394 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN,
395 &pci_usb_takeover, 1,
396 "Enable early takeover of USB controllers. Disable this if you depend on"
397 " BIOS emulation of USB devices, that is you use USB devices (like"
398 " keyboard or mouse) but do not load USB drivers");
399
400 static int pci_clear_bars;
401 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0,
402 "Ignore firmware-assigned resources for BARs.");
403
404 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
405 static int pci_clear_buses;
406 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0,
407 "Ignore firmware-assigned bus numbers.");
408 #endif
409
410 static int pci_enable_ari = 1;
411 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari,
412 0, "Enable support for PCIe Alternative RID Interpretation");
413
414 int pci_enable_aspm = 1;
415 SYSCTL_INT(_hw_pci, OID_AUTO, enable_aspm, CTLFLAG_RDTUN, &pci_enable_aspm,
416 0, "Enable support for PCIe Active State Power Management");
417
418 static int pci_clear_aer_on_attach = 0;
419 SYSCTL_INT(_hw_pci, OID_AUTO, clear_aer_on_attach, CTLFLAG_RWTUN,
420 &pci_clear_aer_on_attach, 0,
421 "Clear port and device AER state on driver attach");
422
423 static int
pci_has_quirk(uint32_t devid,int quirk)424 pci_has_quirk(uint32_t devid, int quirk)
425 {
426 const struct pci_quirk *q;
427
428 for (q = &pci_quirks[0]; q->devid; q++) {
429 if (q->devid == devid && q->type == quirk)
430 return (1);
431 }
432 return (0);
433 }
434
435 /* Find a device_t by bus/slot/function in domain 0 */
436
437 device_t
pci_find_bsf(uint8_t bus,uint8_t slot,uint8_t func)438 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
439 {
440
441 return (pci_find_dbsf(0, bus, slot, func));
442 }
443
444 /* Find a device_t by domain/bus/slot/function */
445
446 device_t
pci_find_dbsf(uint32_t domain,uint8_t bus,uint8_t slot,uint8_t func)447 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
448 {
449 struct pci_devinfo *dinfo;
450
451 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
452 if ((dinfo->cfg.domain == domain) &&
453 (dinfo->cfg.bus == bus) &&
454 (dinfo->cfg.slot == slot) &&
455 (dinfo->cfg.func == func)) {
456 return (dinfo->cfg.dev);
457 }
458 }
459
460 return (NULL);
461 }
462
463 /* Find a device_t by vendor/device ID */
464
465 device_t
pci_find_device(uint16_t vendor,uint16_t device)466 pci_find_device(uint16_t vendor, uint16_t device)
467 {
468 struct pci_devinfo *dinfo;
469
470 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
471 if ((dinfo->cfg.vendor == vendor) &&
472 (dinfo->cfg.device == device)) {
473 return (dinfo->cfg.dev);
474 }
475 }
476
477 return (NULL);
478 }
479
480 device_t
pci_find_class(uint8_t class,uint8_t subclass)481 pci_find_class(uint8_t class, uint8_t subclass)
482 {
483 struct pci_devinfo *dinfo;
484
485 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
486 if (dinfo->cfg.baseclass == class &&
487 dinfo->cfg.subclass == subclass) {
488 return (dinfo->cfg.dev);
489 }
490 }
491
492 return (NULL);
493 }
494
495 static int
pci_printf(pcicfgregs * cfg,const char * fmt,...)496 pci_printf(pcicfgregs *cfg, const char *fmt, ...)
497 {
498 va_list ap;
499 int retval;
500
501 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot,
502 cfg->func);
503 va_start(ap, fmt);
504 retval += vprintf(fmt, ap);
505 va_end(ap);
506 return (retval);
507 }
508
509 /* return base address of memory or port map */
510
511 static pci_addr_t
pci_mapbase(uint64_t mapreg)512 pci_mapbase(uint64_t mapreg)
513 {
514
515 if (PCI_BAR_MEM(mapreg))
516 return (mapreg & PCIM_BAR_MEM_BASE);
517 else
518 return (mapreg & PCIM_BAR_IO_BASE);
519 }
520
521 /* return map type of memory or port map */
522
523 static const char *
pci_maptype(uint64_t mapreg)524 pci_maptype(uint64_t mapreg)
525 {
526
527 if (PCI_BAR_IO(mapreg))
528 return ("I/O Port");
529 if (mapreg & PCIM_BAR_MEM_PREFETCH)
530 return ("Prefetchable Memory");
531 return ("Memory");
532 }
533
534 /* return log2 of map size decoded for memory or port map */
535
536 int
pci_mapsize(uint64_t testval)537 pci_mapsize(uint64_t testval)
538 {
539 int ln2size;
540
541 testval = pci_mapbase(testval);
542 ln2size = 0;
543 if (testval != 0) {
544 while ((testval & 1) == 0)
545 {
546 ln2size++;
547 testval >>= 1;
548 }
549 }
550 return (ln2size);
551 }
552
553 /* return base address of device ROM */
554
555 static pci_addr_t
pci_rombase(uint64_t mapreg)556 pci_rombase(uint64_t mapreg)
557 {
558
559 return (mapreg & PCIM_BIOS_ADDR_MASK);
560 }
561
562 /* return log2 of map size decided for device ROM */
563
564 static int
pci_romsize(uint64_t testval)565 pci_romsize(uint64_t testval)
566 {
567 int ln2size;
568
569 testval = pci_rombase(testval);
570 ln2size = 0;
571 if (testval != 0) {
572 while ((testval & 1) == 0)
573 {
574 ln2size++;
575 testval >>= 1;
576 }
577 }
578 return (ln2size);
579 }
580
581 /* return log2 of address range supported by map register */
582
583 static int
pci_maprange(uint64_t mapreg)584 pci_maprange(uint64_t mapreg)
585 {
586 int ln2range = 0;
587
588 if (PCI_BAR_IO(mapreg))
589 ln2range = 32;
590 else
591 switch (mapreg & PCIM_BAR_MEM_TYPE) {
592 case PCIM_BAR_MEM_32:
593 ln2range = 32;
594 break;
595 case PCIM_BAR_MEM_1MB:
596 ln2range = 20;
597 break;
598 case PCIM_BAR_MEM_64:
599 ln2range = 64;
600 break;
601 }
602 return (ln2range);
603 }
604
605 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
606
607 static void
pci_fixancient(pcicfgregs * cfg)608 pci_fixancient(pcicfgregs *cfg)
609 {
610 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
611 return;
612
613 /* PCI to PCI bridges use header type 1 */
614 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
615 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
616 }
617
618 /* extract header type specific config data */
619
620 static void
pci_hdrtypedata(device_t pcib,int b,int s,int f,pcicfgregs * cfg)621 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
622 {
623 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
624 switch (cfg->hdrtype & PCIM_HDRTYPE) {
625 case PCIM_HDRTYPE_NORMAL:
626 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
627 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
628 cfg->mingnt = REG(PCIR_MINGNT, 1);
629 cfg->maxlat = REG(PCIR_MAXLAT, 1);
630 cfg->nummaps = PCI_MAXMAPS_0;
631 break;
632 case PCIM_HDRTYPE_BRIDGE:
633 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1);
634 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1);
635 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1);
636 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1);
637 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2);
638 cfg->nummaps = PCI_MAXMAPS_1;
639 break;
640 case PCIM_HDRTYPE_CARDBUS:
641 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1);
642 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1);
643 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1);
644 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1);
645 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2);
646 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
647 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
648 cfg->nummaps = PCI_MAXMAPS_2;
649 break;
650 }
651 #undef REG
652 }
653
654 /* read configuration header into pcicfgregs structure */
655 struct pci_devinfo *
pci_read_device(device_t pcib,device_t bus,int d,int b,int s,int f)656 pci_read_device(device_t pcib, device_t bus, int d, int b, int s, int f)
657 {
658 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
659 uint16_t vid, did;
660
661 vid = REG(PCIR_VENDOR, 2);
662 did = REG(PCIR_DEVICE, 2);
663 if (vid != 0xffff)
664 return (pci_fill_devinfo(pcib, bus, d, b, s, f, vid, did));
665
666 return (NULL);
667 }
668
669 struct pci_devinfo *
pci_alloc_devinfo_method(device_t dev)670 pci_alloc_devinfo_method(device_t dev)
671 {
672
673 return (malloc(sizeof(struct pci_devinfo), M_DEVBUF,
674 M_WAITOK | M_ZERO));
675 }
676
677 static struct pci_devinfo *
pci_fill_devinfo(device_t pcib,device_t bus,int d,int b,int s,int f,uint16_t vid,uint16_t did)678 pci_fill_devinfo(device_t pcib, device_t bus, int d, int b, int s, int f,
679 uint16_t vid, uint16_t did)
680 {
681 struct pci_devinfo *devlist_entry;
682 pcicfgregs *cfg;
683
684 devlist_entry = PCI_ALLOC_DEVINFO(bus);
685
686 cfg = &devlist_entry->cfg;
687
688 cfg->domain = d;
689 cfg->bus = b;
690 cfg->slot = s;
691 cfg->func = f;
692 cfg->vendor = vid;
693 cfg->device = did;
694 cfg->cmdreg = REG(PCIR_COMMAND, 2);
695 cfg->statreg = REG(PCIR_STATUS, 2);
696 cfg->baseclass = REG(PCIR_CLASS, 1);
697 cfg->subclass = REG(PCIR_SUBCLASS, 1);
698 cfg->progif = REG(PCIR_PROGIF, 1);
699 cfg->revid = REG(PCIR_REVID, 1);
700 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
701 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
702 cfg->lattimer = REG(PCIR_LATTIMER, 1);
703 cfg->intpin = REG(PCIR_INTPIN, 1);
704 cfg->intline = REG(PCIR_INTLINE, 1);
705
706 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
707 cfg->hdrtype &= ~PCIM_MFDEV;
708 STAILQ_INIT(&cfg->maps);
709
710 cfg->iov = NULL;
711
712 pci_fixancient(cfg);
713 pci_hdrtypedata(pcib, b, s, f, cfg);
714
715 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
716 pci_read_cap(pcib, cfg);
717
718 STAILQ_INSERT_TAIL(&pci_devq, devlist_entry, pci_links);
719
720 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
721 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
722 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
723 devlist_entry->conf.pc_sel.pc_func = cfg->func;
724 devlist_entry->conf.pc_hdr = cfg->hdrtype;
725
726 devlist_entry->conf.pc_subvendor = cfg->subvendor;
727 devlist_entry->conf.pc_subdevice = cfg->subdevice;
728 devlist_entry->conf.pc_vendor = cfg->vendor;
729 devlist_entry->conf.pc_device = cfg->device;
730
731 devlist_entry->conf.pc_class = cfg->baseclass;
732 devlist_entry->conf.pc_subclass = cfg->subclass;
733 devlist_entry->conf.pc_progif = cfg->progif;
734 devlist_entry->conf.pc_revid = cfg->revid;
735
736 pci_numdevs++;
737 pci_generation++;
738
739 return (devlist_entry);
740 }
741 #undef REG
742
743 static void
pci_ea_fill_info(device_t pcib,pcicfgregs * cfg)744 pci_ea_fill_info(device_t pcib, pcicfgregs *cfg)
745 {
746 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \
747 cfg->ea.ea_location + (n), w)
748 int num_ent;
749 int ptr;
750 int a, b;
751 uint32_t val;
752 int ent_size;
753 uint32_t dw[4];
754 uint64_t base, max_offset;
755 struct pci_ea_entry *eae;
756
757 if (cfg->ea.ea_location == 0)
758 return;
759
760 STAILQ_INIT(&cfg->ea.ea_entries);
761
762 /* Determine the number of entries */
763 num_ent = REG(PCIR_EA_NUM_ENT, 2);
764 num_ent &= PCIM_EA_NUM_ENT_MASK;
765
766 /* Find the first entry to care of */
767 ptr = PCIR_EA_FIRST_ENT;
768
769 /* Skip DWORD 2 for type 1 functions */
770 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE)
771 ptr += 4;
772
773 for (a = 0; a < num_ent; a++) {
774
775 eae = malloc(sizeof(*eae), M_DEVBUF, M_WAITOK | M_ZERO);
776 eae->eae_cfg_offset = cfg->ea.ea_location + ptr;
777
778 /* Read a number of dwords in the entry */
779 val = REG(ptr, 4);
780 ptr += 4;
781 ent_size = (val & PCIM_EA_ES);
782
783 for (b = 0; b < ent_size; b++) {
784 dw[b] = REG(ptr, 4);
785 ptr += 4;
786 }
787
788 eae->eae_flags = val;
789 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET;
790
791 base = dw[0] & PCIM_EA_FIELD_MASK;
792 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK;
793 b = 2;
794 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) {
795 base |= (uint64_t)dw[b] << 32UL;
796 b++;
797 }
798 if (((dw[1] & PCIM_EA_IS_64) != 0)
799 && (b < ent_size)) {
800 max_offset |= (uint64_t)dw[b] << 32UL;
801 b++;
802 }
803
804 eae->eae_base = base;
805 eae->eae_max_offset = max_offset;
806
807 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link);
808
809 if (bootverbose) {
810 printf("PCI(EA) dev %04x:%04x, bei %d, flags #%x, base #%jx, max_offset #%jx\n",
811 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags,
812 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset);
813 }
814 }
815 }
816 #undef REG
817
818 static void
pci_read_cap(device_t pcib,pcicfgregs * cfg)819 pci_read_cap(device_t pcib, pcicfgregs *cfg)
820 {
821 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
822 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
823 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
824 uint64_t addr;
825 #endif
826 uint32_t val;
827 int ptr, nextptr, ptrptr;
828
829 switch (cfg->hdrtype & PCIM_HDRTYPE) {
830 case PCIM_HDRTYPE_NORMAL:
831 case PCIM_HDRTYPE_BRIDGE:
832 ptrptr = PCIR_CAP_PTR;
833 break;
834 case PCIM_HDRTYPE_CARDBUS:
835 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
836 break;
837 default:
838 return; /* no extended capabilities support */
839 }
840 nextptr = REG(ptrptr, 1); /* sanity check? */
841
842 /*
843 * Read capability entries.
844 */
845 while (nextptr != 0) {
846 /* Sanity check */
847 if (nextptr > 255) {
848 printf("illegal PCI extended capability offset %d\n",
849 nextptr);
850 return;
851 }
852 /* Find the next entry */
853 ptr = nextptr;
854 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
855
856 /* Process this entry */
857 switch (REG(ptr + PCICAP_ID, 1)) {
858 case PCIY_PMG: /* PCI power management */
859 if (cfg->pp.pp_cap == 0) {
860 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
861 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
862 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE;
863 if ((nextptr - ptr) > PCIR_POWER_DATA)
864 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
865 }
866 break;
867 case PCIY_HT: /* HyperTransport */
868 /* Determine HT-specific capability type. */
869 val = REG(ptr + PCIR_HT_COMMAND, 2);
870
871 if ((val & 0xe000) == PCIM_HTCAP_SLAVE)
872 cfg->ht.ht_slave = ptr;
873
874 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
875 switch (val & PCIM_HTCMD_CAP_MASK) {
876 case PCIM_HTCAP_MSI_MAPPING:
877 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
878 /* Sanity check the mapping window. */
879 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,
880 4);
881 addr <<= 32;
882 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,
883 4);
884 if (addr != MSI_INTEL_ADDR_BASE)
885 device_printf(pcib,
886 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n",
887 cfg->domain, cfg->bus,
888 cfg->slot, cfg->func,
889 (long long)addr);
890 } else
891 addr = MSI_INTEL_ADDR_BASE;
892
893 cfg->ht.ht_msimap = ptr;
894 cfg->ht.ht_msictrl = val;
895 cfg->ht.ht_msiaddr = addr;
896 break;
897 }
898 #endif
899 break;
900 case PCIY_MSI: /* PCI MSI */
901 cfg->msi.msi_location = ptr;
902 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
903 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
904 PCIM_MSICTRL_MMC_MASK)>>1);
905 break;
906 case PCIY_MSIX: /* PCI MSI-X */
907 cfg->msix.msix_location = ptr;
908 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
909 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
910 PCIM_MSIXCTRL_TABLE_SIZE) + 1;
911 val = REG(ptr + PCIR_MSIX_TABLE, 4);
912 cfg->msix.msix_table_bar = PCIR_BAR(val &
913 PCIM_MSIX_BIR_MASK);
914 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
915 val = REG(ptr + PCIR_MSIX_PBA, 4);
916 cfg->msix.msix_pba_bar = PCIR_BAR(val &
917 PCIM_MSIX_BIR_MASK);
918 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
919 break;
920 case PCIY_VPD: /* PCI Vital Product Data */
921 cfg->vpd.vpd_reg = ptr;
922 break;
923 case PCIY_SUBVENDOR:
924 /* Should always be true. */
925 if ((cfg->hdrtype & PCIM_HDRTYPE) ==
926 PCIM_HDRTYPE_BRIDGE) {
927 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
928 cfg->subvendor = val & 0xffff;
929 cfg->subdevice = val >> 16;
930 }
931 break;
932 case PCIY_PCIX: /* PCI-X */
933 /*
934 * Assume we have a PCI-X chipset if we have
935 * at least one PCI-PCI bridge with a PCI-X
936 * capability. Note that some systems with
937 * PCI-express or HT chipsets might match on
938 * this check as well.
939 */
940 if ((cfg->hdrtype & PCIM_HDRTYPE) ==
941 PCIM_HDRTYPE_BRIDGE)
942 pcix_chipset = 1;
943 cfg->pcix.pcix_location = ptr;
944 break;
945 case PCIY_EXPRESS: /* PCI-express */
946 /*
947 * Assume we have a PCI-express chipset if we have
948 * at least one PCI-express device.
949 */
950 pcie_chipset = 1;
951 cfg->pcie.pcie_location = ptr;
952 val = REG(ptr + PCIER_FLAGS, 2);
953 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE;
954 break;
955 case PCIY_EA: /* Enhanced Allocation */
956 cfg->ea.ea_location = ptr;
957 pci_ea_fill_info(pcib, cfg);
958 break;
959 default:
960 break;
961 }
962 }
963
964 #if defined(__powerpc__)
965 /*
966 * Enable the MSI mapping window for all HyperTransport
967 * slaves. PCI-PCI bridges have their windows enabled via
968 * PCIB_MAP_MSI().
969 */
970 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 &&
971 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
972 device_printf(pcib,
973 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n",
974 cfg->domain, cfg->bus, cfg->slot, cfg->func);
975 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
976 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl,
977 2);
978 }
979 #endif
980 /* REG and WREG use carry through to next functions */
981 }
982
983 /*
984 * PCI Vital Product Data
985 */
986
987 #define PCI_VPD_TIMEOUT 1000000
988
989 static int
pci_read_vpd_reg(device_t pcib,pcicfgregs * cfg,int reg,uint32_t * data)990 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
991 {
992 int count = PCI_VPD_TIMEOUT;
993
994 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
995
996 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
997
998 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
999 if (--count < 0)
1000 return (ENXIO);
1001 DELAY(1); /* limit looping */
1002 }
1003 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
1004
1005 return (0);
1006 }
1007
1008 #if 0
1009 static int
1010 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
1011 {
1012 int count = PCI_VPD_TIMEOUT;
1013
1014 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
1015
1016 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
1017 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
1018 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
1019 if (--count < 0)
1020 return (ENXIO);
1021 DELAY(1); /* limit looping */
1022 }
1023
1024 return (0);
1025 }
1026 #endif
1027
1028 #undef PCI_VPD_TIMEOUT
1029
1030 struct vpd_readstate {
1031 device_t pcib;
1032 pcicfgregs *cfg;
1033 uint32_t val;
1034 int bytesinval;
1035 int off;
1036 uint8_t cksum;
1037 };
1038
1039 static int
vpd_nextbyte(struct vpd_readstate * vrs,uint8_t * data)1040 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
1041 {
1042 uint32_t reg;
1043 uint8_t byte;
1044
1045 if (vrs->bytesinval == 0) {
1046 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
1047 return (ENXIO);
1048 vrs->val = le32toh(reg);
1049 vrs->off += 4;
1050 byte = vrs->val & 0xff;
1051 vrs->bytesinval = 3;
1052 } else {
1053 vrs->val = vrs->val >> 8;
1054 byte = vrs->val & 0xff;
1055 vrs->bytesinval--;
1056 }
1057
1058 vrs->cksum += byte;
1059 *data = byte;
1060 return (0);
1061 }
1062
1063 static void
pci_read_vpd(device_t pcib,pcicfgregs * cfg)1064 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
1065 {
1066 struct vpd_readstate vrs;
1067 int state;
1068 int name;
1069 int remain;
1070 int i;
1071 int alloc, off; /* alloc/off for RO/W arrays */
1072 int cksumvalid;
1073 int dflen;
1074 uint8_t byte;
1075 uint8_t byte2;
1076
1077 /* init vpd reader */
1078 vrs.bytesinval = 0;
1079 vrs.off = 0;
1080 vrs.pcib = pcib;
1081 vrs.cfg = cfg;
1082 vrs.cksum = 0;
1083
1084 state = 0;
1085 name = remain = i = 0; /* shut up stupid gcc */
1086 alloc = off = 0; /* shut up stupid gcc */
1087 dflen = 0; /* shut up stupid gcc */
1088 cksumvalid = -1;
1089 while (state >= 0) {
1090 if (vpd_nextbyte(&vrs, &byte)) {
1091 state = -2;
1092 break;
1093 }
1094 #if 0
1095 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
1096 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
1097 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
1098 #endif
1099 switch (state) {
1100 case 0: /* item name */
1101 if (byte & 0x80) {
1102 if (vpd_nextbyte(&vrs, &byte2)) {
1103 state = -2;
1104 break;
1105 }
1106 remain = byte2;
1107 if (vpd_nextbyte(&vrs, &byte2)) {
1108 state = -2;
1109 break;
1110 }
1111 remain |= byte2 << 8;
1112 name = byte & 0x7f;
1113 } else {
1114 remain = byte & 0x7;
1115 name = (byte >> 3) & 0xf;
1116 }
1117 if (vrs.off + remain - vrs.bytesinval > 0x8000) {
1118 pci_printf(cfg,
1119 "VPD data overflow, remain %#x\n", remain);
1120 state = -1;
1121 break;
1122 }
1123 switch (name) {
1124 case 0x2: /* String */
1125 cfg->vpd.vpd_ident = malloc(remain + 1,
1126 M_DEVBUF, M_WAITOK);
1127 i = 0;
1128 state = 1;
1129 break;
1130 case 0xf: /* End */
1131 state = -1;
1132 break;
1133 case 0x10: /* VPD-R */
1134 alloc = 8;
1135 off = 0;
1136 cfg->vpd.vpd_ros = malloc(alloc *
1137 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
1138 M_WAITOK | M_ZERO);
1139 state = 2;
1140 break;
1141 case 0x11: /* VPD-W */
1142 alloc = 8;
1143 off = 0;
1144 cfg->vpd.vpd_w = malloc(alloc *
1145 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
1146 M_WAITOK | M_ZERO);
1147 state = 5;
1148 break;
1149 default: /* Invalid data, abort */
1150 state = -1;
1151 break;
1152 }
1153 break;
1154
1155 case 1: /* Identifier String */
1156 cfg->vpd.vpd_ident[i++] = byte;
1157 remain--;
1158 if (remain == 0) {
1159 cfg->vpd.vpd_ident[i] = '\0';
1160 state = 0;
1161 }
1162 break;
1163
1164 case 2: /* VPD-R Keyword Header */
1165 if (off == alloc) {
1166 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
1167 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
1168 M_DEVBUF, M_WAITOK | M_ZERO);
1169 }
1170 cfg->vpd.vpd_ros[off].keyword[0] = byte;
1171 if (vpd_nextbyte(&vrs, &byte2)) {
1172 state = -2;
1173 break;
1174 }
1175 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
1176 if (vpd_nextbyte(&vrs, &byte2)) {
1177 state = -2;
1178 break;
1179 }
1180 cfg->vpd.vpd_ros[off].len = dflen = byte2;
1181 if (dflen == 0 &&
1182 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
1183 2) == 0) {
1184 /*
1185 * if this happens, we can't trust the rest
1186 * of the VPD.
1187 */
1188 pci_printf(cfg, "bad keyword length: %d\n",
1189 dflen);
1190 cksumvalid = 0;
1191 state = -1;
1192 break;
1193 } else if (dflen == 0) {
1194 cfg->vpd.vpd_ros[off].value = malloc(1 *
1195 sizeof(*cfg->vpd.vpd_ros[off].value),
1196 M_DEVBUF, M_WAITOK);
1197 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1198 } else
1199 cfg->vpd.vpd_ros[off].value = malloc(
1200 (dflen + 1) *
1201 sizeof(*cfg->vpd.vpd_ros[off].value),
1202 M_DEVBUF, M_WAITOK);
1203 remain -= 3;
1204 i = 0;
1205 /* keep in sync w/ state 3's transitions */
1206 if (dflen == 0 && remain == 0)
1207 state = 0;
1208 else if (dflen == 0)
1209 state = 2;
1210 else
1211 state = 3;
1212 break;
1213
1214 case 3: /* VPD-R Keyword Value */
1215 cfg->vpd.vpd_ros[off].value[i++] = byte;
1216 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1217 "RV", 2) == 0 && cksumvalid == -1) {
1218 if (vrs.cksum == 0)
1219 cksumvalid = 1;
1220 else {
1221 if (bootverbose)
1222 pci_printf(cfg,
1223 "bad VPD cksum, remain %hhu\n",
1224 vrs.cksum);
1225 cksumvalid = 0;
1226 state = -1;
1227 break;
1228 }
1229 }
1230 dflen--;
1231 remain--;
1232 /* keep in sync w/ state 2's transitions */
1233 if (dflen == 0)
1234 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1235 if (dflen == 0 && remain == 0) {
1236 cfg->vpd.vpd_rocnt = off;
1237 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
1238 off * sizeof(*cfg->vpd.vpd_ros),
1239 M_DEVBUF, M_WAITOK | M_ZERO);
1240 state = 0;
1241 } else if (dflen == 0)
1242 state = 2;
1243 break;
1244
1245 case 4:
1246 remain--;
1247 if (remain == 0)
1248 state = 0;
1249 break;
1250
1251 case 5: /* VPD-W Keyword Header */
1252 if (off == alloc) {
1253 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
1254 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1255 M_DEVBUF, M_WAITOK | M_ZERO);
1256 }
1257 cfg->vpd.vpd_w[off].keyword[0] = byte;
1258 if (vpd_nextbyte(&vrs, &byte2)) {
1259 state = -2;
1260 break;
1261 }
1262 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1263 if (vpd_nextbyte(&vrs, &byte2)) {
1264 state = -2;
1265 break;
1266 }
1267 cfg->vpd.vpd_w[off].len = dflen = byte2;
1268 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1269 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) *
1270 sizeof(*cfg->vpd.vpd_w[off].value),
1271 M_DEVBUF, M_WAITOK);
1272 remain -= 3;
1273 i = 0;
1274 /* keep in sync w/ state 6's transitions */
1275 if (dflen == 0 && remain == 0)
1276 state = 0;
1277 else if (dflen == 0)
1278 state = 5;
1279 else
1280 state = 6;
1281 break;
1282
1283 case 6: /* VPD-W Keyword Value */
1284 cfg->vpd.vpd_w[off].value[i++] = byte;
1285 dflen--;
1286 remain--;
1287 /* keep in sync w/ state 5's transitions */
1288 if (dflen == 0)
1289 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1290 if (dflen == 0 && remain == 0) {
1291 cfg->vpd.vpd_wcnt = off;
1292 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
1293 off * sizeof(*cfg->vpd.vpd_w),
1294 M_DEVBUF, M_WAITOK | M_ZERO);
1295 state = 0;
1296 } else if (dflen == 0)
1297 state = 5;
1298 break;
1299
1300 default:
1301 pci_printf(cfg, "invalid state: %d\n", state);
1302 state = -1;
1303 break;
1304 }
1305 }
1306
1307 if (cksumvalid == 0 || state < -1) {
1308 /* read-only data bad, clean up */
1309 if (cfg->vpd.vpd_ros != NULL) {
1310 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1311 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1312 free(cfg->vpd.vpd_ros, M_DEVBUF);
1313 cfg->vpd.vpd_ros = NULL;
1314 }
1315 }
1316 if (state < -1) {
1317 /* I/O error, clean up */
1318 pci_printf(cfg, "failed to read VPD data.\n");
1319 if (cfg->vpd.vpd_ident != NULL) {
1320 free(cfg->vpd.vpd_ident, M_DEVBUF);
1321 cfg->vpd.vpd_ident = NULL;
1322 }
1323 if (cfg->vpd.vpd_w != NULL) {
1324 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1325 free(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1326 free(cfg->vpd.vpd_w, M_DEVBUF);
1327 cfg->vpd.vpd_w = NULL;
1328 }
1329 }
1330 cfg->vpd.vpd_cached = 1;
1331 #undef REG
1332 #undef WREG
1333 }
1334
1335 int
pci_get_vpd_ident_method(device_t dev,device_t child,const char ** identptr)1336 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1337 {
1338 struct pci_devinfo *dinfo = device_get_ivars(child);
1339 pcicfgregs *cfg = &dinfo->cfg;
1340
1341 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1342 pci_read_vpd(device_get_parent(dev), cfg);
1343
1344 *identptr = cfg->vpd.vpd_ident;
1345
1346 if (*identptr == NULL)
1347 return (ENXIO);
1348
1349 return (0);
1350 }
1351
1352 int
pci_get_vpd_readonly_method(device_t dev,device_t child,const char * kw,const char ** vptr)1353 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1354 const char **vptr)
1355 {
1356 struct pci_devinfo *dinfo = device_get_ivars(child);
1357 pcicfgregs *cfg = &dinfo->cfg;
1358 int i;
1359
1360 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1361 pci_read_vpd(device_get_parent(dev), cfg);
1362
1363 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1364 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1365 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1366 *vptr = cfg->vpd.vpd_ros[i].value;
1367 return (0);
1368 }
1369
1370 *vptr = NULL;
1371 return (ENXIO);
1372 }
1373
1374 struct pcicfg_vpd *
pci_fetch_vpd_list(device_t dev)1375 pci_fetch_vpd_list(device_t dev)
1376 {
1377 struct pci_devinfo *dinfo = device_get_ivars(dev);
1378 pcicfgregs *cfg = &dinfo->cfg;
1379
1380 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1381 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg);
1382 return (&cfg->vpd);
1383 }
1384
1385 /*
1386 * Find the requested HyperTransport capability and return the offset
1387 * in configuration space via the pointer provided. The function
1388 * returns 0 on success and an error code otherwise.
1389 */
1390 int
pci_find_htcap_method(device_t dev,device_t child,int capability,int * capreg)1391 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg)
1392 {
1393 int ptr, error;
1394 uint16_t val;
1395
1396 error = pci_find_cap(child, PCIY_HT, &ptr);
1397 if (error)
1398 return (error);
1399
1400 /*
1401 * Traverse the capabilities list checking each HT capability
1402 * to see if it matches the requested HT capability.
1403 */
1404 for (;;) {
1405 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2);
1406 if (capability == PCIM_HTCAP_SLAVE ||
1407 capability == PCIM_HTCAP_HOST)
1408 val &= 0xe000;
1409 else
1410 val &= PCIM_HTCMD_CAP_MASK;
1411 if (val == capability) {
1412 if (capreg != NULL)
1413 *capreg = ptr;
1414 return (0);
1415 }
1416
1417 /* Skip to the next HT capability. */
1418 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0)
1419 break;
1420 }
1421
1422 return (ENOENT);
1423 }
1424
1425 /*
1426 * Find the next requested HyperTransport capability after start and return
1427 * the offset in configuration space via the pointer provided. The function
1428 * returns 0 on success and an error code otherwise.
1429 */
1430 int
pci_find_next_htcap_method(device_t dev,device_t child,int capability,int start,int * capreg)1431 pci_find_next_htcap_method(device_t dev, device_t child, int capability,
1432 int start, int *capreg)
1433 {
1434 int ptr;
1435 uint16_t val;
1436
1437 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == PCIY_HT,
1438 ("start capability is not HyperTransport capability"));
1439 ptr = start;
1440
1441 /*
1442 * Traverse the capabilities list checking each HT capability
1443 * to see if it matches the requested HT capability.
1444 */
1445 for (;;) {
1446 /* Skip to the next HT capability. */
1447 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0)
1448 break;
1449
1450 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2);
1451 if (capability == PCIM_HTCAP_SLAVE ||
1452 capability == PCIM_HTCAP_HOST)
1453 val &= 0xe000;
1454 else
1455 val &= PCIM_HTCMD_CAP_MASK;
1456 if (val == capability) {
1457 if (capreg != NULL)
1458 *capreg = ptr;
1459 return (0);
1460 }
1461 }
1462
1463 return (ENOENT);
1464 }
1465
1466 /*
1467 * Find the requested capability and return the offset in
1468 * configuration space via the pointer provided. The function returns
1469 * 0 on success and an error code otherwise.
1470 */
1471 int
pci_find_cap_method(device_t dev,device_t child,int capability,int * capreg)1472 pci_find_cap_method(device_t dev, device_t child, int capability,
1473 int *capreg)
1474 {
1475 struct pci_devinfo *dinfo = device_get_ivars(child);
1476 pcicfgregs *cfg = &dinfo->cfg;
1477 uint32_t status;
1478 uint8_t ptr;
1479
1480 /*
1481 * Check the CAP_LIST bit of the PCI status register first.
1482 */
1483 status = pci_read_config(child, PCIR_STATUS, 2);
1484 if (!(status & PCIM_STATUS_CAPPRESENT))
1485 return (ENXIO);
1486
1487 /*
1488 * Determine the start pointer of the capabilities list.
1489 */
1490 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1491 case PCIM_HDRTYPE_NORMAL:
1492 case PCIM_HDRTYPE_BRIDGE:
1493 ptr = PCIR_CAP_PTR;
1494 break;
1495 case PCIM_HDRTYPE_CARDBUS:
1496 ptr = PCIR_CAP_PTR_2;
1497 break;
1498 default:
1499 /* XXX: panic? */
1500 return (ENXIO); /* no extended capabilities support */
1501 }
1502 ptr = pci_read_config(child, ptr, 1);
1503
1504 /*
1505 * Traverse the capabilities list.
1506 */
1507 while (ptr != 0) {
1508 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1509 if (capreg != NULL)
1510 *capreg = ptr;
1511 return (0);
1512 }
1513 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1514 }
1515
1516 return (ENOENT);
1517 }
1518
1519 /*
1520 * Find the next requested capability after start and return the offset in
1521 * configuration space via the pointer provided. The function returns
1522 * 0 on success and an error code otherwise.
1523 */
1524 int
pci_find_next_cap_method(device_t dev,device_t child,int capability,int start,int * capreg)1525 pci_find_next_cap_method(device_t dev, device_t child, int capability,
1526 int start, int *capreg)
1527 {
1528 uint8_t ptr;
1529
1530 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == capability,
1531 ("start capability is not expected capability"));
1532
1533 ptr = pci_read_config(child, start + PCICAP_NEXTPTR, 1);
1534 while (ptr != 0) {
1535 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1536 if (capreg != NULL)
1537 *capreg = ptr;
1538 return (0);
1539 }
1540 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1541 }
1542
1543 return (ENOENT);
1544 }
1545
1546 /*
1547 * Find the requested extended capability and return the offset in
1548 * configuration space via the pointer provided. The function returns
1549 * 0 on success and an error code otherwise.
1550 */
1551 int
pci_find_extcap_method(device_t dev,device_t child,int capability,int * capreg)1552 pci_find_extcap_method(device_t dev, device_t child, int capability,
1553 int *capreg)
1554 {
1555 struct pci_devinfo *dinfo = device_get_ivars(child);
1556 pcicfgregs *cfg = &dinfo->cfg;
1557 uint32_t ecap;
1558 uint16_t ptr;
1559
1560 /* Only supported for PCI-express devices. */
1561 if (cfg->pcie.pcie_location == 0)
1562 return (ENXIO);
1563
1564 ptr = PCIR_EXTCAP;
1565 ecap = pci_read_config(child, ptr, 4);
1566 if (ecap == 0xffffffff || ecap == 0)
1567 return (ENOENT);
1568 for (;;) {
1569 if (PCI_EXTCAP_ID(ecap) == capability) {
1570 if (capreg != NULL)
1571 *capreg = ptr;
1572 return (0);
1573 }
1574 ptr = PCI_EXTCAP_NEXTPTR(ecap);
1575 if (ptr == 0)
1576 break;
1577 ecap = pci_read_config(child, ptr, 4);
1578 }
1579
1580 return (ENOENT);
1581 }
1582
1583 /*
1584 * Find the next requested extended capability after start and return the
1585 * offset in configuration space via the pointer provided. The function
1586 * returns 0 on success and an error code otherwise.
1587 */
1588 int
pci_find_next_extcap_method(device_t dev,device_t child,int capability,int start,int * capreg)1589 pci_find_next_extcap_method(device_t dev, device_t child, int capability,
1590 int start, int *capreg)
1591 {
1592 struct pci_devinfo *dinfo = device_get_ivars(child);
1593 pcicfgregs *cfg = &dinfo->cfg;
1594 uint32_t ecap;
1595 uint16_t ptr;
1596
1597 /* Only supported for PCI-express devices. */
1598 if (cfg->pcie.pcie_location == 0)
1599 return (ENXIO);
1600
1601 ecap = pci_read_config(child, start, 4);
1602 KASSERT(PCI_EXTCAP_ID(ecap) == capability,
1603 ("start extended capability is not expected capability"));
1604 ptr = PCI_EXTCAP_NEXTPTR(ecap);
1605 while (ptr != 0) {
1606 ecap = pci_read_config(child, ptr, 4);
1607 if (PCI_EXTCAP_ID(ecap) == capability) {
1608 if (capreg != NULL)
1609 *capreg = ptr;
1610 return (0);
1611 }
1612 ptr = PCI_EXTCAP_NEXTPTR(ecap);
1613 }
1614
1615 return (ENOENT);
1616 }
1617
1618 /*
1619 * Support for MSI-X message interrupts.
1620 */
1621 static void
pci_write_msix_entry(device_t dev,u_int index,uint64_t address,uint32_t data)1622 pci_write_msix_entry(device_t dev, u_int index, uint64_t address, uint32_t data)
1623 {
1624 struct pci_devinfo *dinfo = device_get_ivars(dev);
1625 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1626 uint32_t offset;
1627
1628 KASSERT(msix->msix_table_len > index, ("bogus index"));
1629 offset = msix->msix_table_offset + index * 16;
1630 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1631 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1632 bus_write_4(msix->msix_table_res, offset + 8, data);
1633 }
1634
1635 void
pci_enable_msix_method(device_t dev,device_t child,u_int index,uint64_t address,uint32_t data)1636 pci_enable_msix_method(device_t dev, device_t child, u_int index,
1637 uint64_t address, uint32_t data)
1638 {
1639
1640 if (pci_msix_rewrite_table) {
1641 struct pci_devinfo *dinfo = device_get_ivars(child);
1642 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1643
1644 /*
1645 * Some VM hosts require MSIX to be disabled in the
1646 * control register before updating the MSIX table
1647 * entries are allowed. It is not enough to only
1648 * disable MSIX while updating a single entry. MSIX
1649 * must be disabled while updating all entries in the
1650 * table.
1651 */
1652 pci_write_config(child,
1653 msix->msix_location + PCIR_MSIX_CTRL,
1654 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2);
1655 pci_resume_msix(child);
1656 } else
1657 pci_write_msix_entry(child, index, address, data);
1658
1659 /* Enable MSI -> HT mapping. */
1660 pci_ht_map_msi(child, address);
1661 }
1662
1663 void
pci_mask_msix(device_t dev,u_int index)1664 pci_mask_msix(device_t dev, u_int index)
1665 {
1666 struct pci_devinfo *dinfo = device_get_ivars(dev);
1667 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1668 uint32_t offset, val;
1669
1670 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1671 offset = msix->msix_table_offset + index * 16 + 12;
1672 val = bus_read_4(msix->msix_table_res, offset);
1673 val |= PCIM_MSIX_VCTRL_MASK;
1674
1675 /*
1676 * Some devices (e.g. Samsung PM961) do not support reads of this
1677 * register, so always write the new value.
1678 */
1679 bus_write_4(msix->msix_table_res, offset, val);
1680 }
1681
1682 void
pci_unmask_msix(device_t dev,u_int index)1683 pci_unmask_msix(device_t dev, u_int index)
1684 {
1685 struct pci_devinfo *dinfo = device_get_ivars(dev);
1686 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1687 uint32_t offset, val;
1688
1689 KASSERT(msix->msix_table_len > index, ("bogus index"));
1690 offset = msix->msix_table_offset + index * 16 + 12;
1691 val = bus_read_4(msix->msix_table_res, offset);
1692 val &= ~PCIM_MSIX_VCTRL_MASK;
1693
1694 /*
1695 * Some devices (e.g. Samsung PM961) do not support reads of this
1696 * register, so always write the new value.
1697 */
1698 bus_write_4(msix->msix_table_res, offset, val);
1699 }
1700
1701 int
pci_pending_msix(device_t dev,u_int index)1702 pci_pending_msix(device_t dev, u_int index)
1703 {
1704 struct pci_devinfo *dinfo = device_get_ivars(dev);
1705 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1706 uint32_t offset, bit;
1707
1708 KASSERT(msix->msix_table_len > index, ("bogus index"));
1709 offset = msix->msix_pba_offset + (index / 32) * 4;
1710 bit = 1 << index % 32;
1711 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1712 }
1713
1714 /*
1715 * Restore MSI-X registers and table during resume. If MSI-X is
1716 * enabled then walk the virtual table to restore the actual MSI-X
1717 * table.
1718 */
1719 static void
pci_resume_msix(device_t dev)1720 pci_resume_msix(device_t dev)
1721 {
1722 struct pci_devinfo *dinfo = device_get_ivars(dev);
1723 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1724 struct msix_table_entry *mte;
1725 struct msix_vector *mv;
1726 int i;
1727
1728 if (msix->msix_alloc > 0) {
1729 /* First, mask all vectors. */
1730 for (i = 0; i < msix->msix_msgnum; i++)
1731 pci_mask_msix(dev, i);
1732
1733 /* Second, program any messages with at least one handler. */
1734 for (i = 0; i < msix->msix_table_len; i++) {
1735 mte = &msix->msix_table[i];
1736 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1737 continue;
1738 mv = &msix->msix_vectors[mte->mte_vector - 1];
1739 pci_write_msix_entry(dev, i, mv->mv_address,
1740 mv->mv_data);
1741 pci_unmask_msix(dev, i);
1742 }
1743 }
1744 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1745 msix->msix_ctrl, 2);
1746 }
1747
1748 /*
1749 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1750 * returned in *count. After this function returns, each message will be
1751 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1752 */
1753 int
pci_alloc_msix_method(device_t dev,device_t child,int * count)1754 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1755 {
1756 struct pci_devinfo *dinfo = device_get_ivars(child);
1757 pcicfgregs *cfg = &dinfo->cfg;
1758 struct resource_list_entry *rle;
1759 int actual, error, i, irq, max;
1760
1761 /* Don't let count == 0 get us into trouble. */
1762 if (*count == 0)
1763 return (EINVAL);
1764
1765 /* If rid 0 is allocated, then fail. */
1766 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1767 if (rle != NULL && rle->res != NULL)
1768 return (ENXIO);
1769
1770 /* Already have allocated messages? */
1771 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1772 return (ENXIO);
1773
1774 /* If MSI-X is blacklisted for this system, fail. */
1775 if (pci_msix_blacklisted())
1776 return (ENXIO);
1777
1778 /* MSI-X capability present? */
1779 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1780 return (ENODEV);
1781
1782 /* Make sure the appropriate BARs are mapped. */
1783 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1784 cfg->msix.msix_table_bar);
1785 if (rle == NULL || rle->res == NULL ||
1786 !(rman_get_flags(rle->res) & RF_ACTIVE))
1787 return (ENXIO);
1788 cfg->msix.msix_table_res = rle->res;
1789 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1790 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1791 cfg->msix.msix_pba_bar);
1792 if (rle == NULL || rle->res == NULL ||
1793 !(rman_get_flags(rle->res) & RF_ACTIVE))
1794 return (ENXIO);
1795 }
1796 cfg->msix.msix_pba_res = rle->res;
1797
1798 if (bootverbose)
1799 device_printf(child,
1800 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1801 *count, cfg->msix.msix_msgnum);
1802 max = min(*count, cfg->msix.msix_msgnum);
1803 for (i = 0; i < max; i++) {
1804 /* Allocate a message. */
1805 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1806 if (error) {
1807 if (i == 0)
1808 return (error);
1809 break;
1810 }
1811 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1812 irq, 1);
1813 }
1814 actual = i;
1815
1816 if (bootverbose) {
1817 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1818 if (actual == 1)
1819 device_printf(child, "using IRQ %ju for MSI-X\n",
1820 rle->start);
1821 else {
1822 int run;
1823
1824 /*
1825 * Be fancy and try to print contiguous runs of
1826 * IRQ values as ranges. 'irq' is the previous IRQ.
1827 * 'run' is true if we are in a range.
1828 */
1829 device_printf(child, "using IRQs %ju", rle->start);
1830 irq = rle->start;
1831 run = 0;
1832 for (i = 1; i < actual; i++) {
1833 rle = resource_list_find(&dinfo->resources,
1834 SYS_RES_IRQ, i + 1);
1835
1836 /* Still in a run? */
1837 if (rle->start == irq + 1) {
1838 run = 1;
1839 irq++;
1840 continue;
1841 }
1842
1843 /* Finish previous range. */
1844 if (run) {
1845 printf("-%d", irq);
1846 run = 0;
1847 }
1848
1849 /* Start new range. */
1850 printf(",%ju", rle->start);
1851 irq = rle->start;
1852 }
1853
1854 /* Unfinished range? */
1855 if (run)
1856 printf("-%d", irq);
1857 printf(" for MSI-X\n");
1858 }
1859 }
1860
1861 /* Mask all vectors. */
1862 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1863 pci_mask_msix(child, i);
1864
1865 /* Allocate and initialize vector data and virtual table. */
1866 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual,
1867 M_DEVBUF, M_WAITOK | M_ZERO);
1868 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual,
1869 M_DEVBUF, M_WAITOK | M_ZERO);
1870 for (i = 0; i < actual; i++) {
1871 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1872 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1873 cfg->msix.msix_table[i].mte_vector = i + 1;
1874 }
1875
1876 /* Update control register to enable MSI-X. */
1877 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1878 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1879 cfg->msix.msix_ctrl, 2);
1880
1881 /* Update counts of alloc'd messages. */
1882 cfg->msix.msix_alloc = actual;
1883 cfg->msix.msix_table_len = actual;
1884 *count = actual;
1885 return (0);
1886 }
1887
1888 /*
1889 * By default, pci_alloc_msix() will assign the allocated IRQ
1890 * resources consecutively to the first N messages in the MSI-X table.
1891 * However, device drivers may want to use different layouts if they
1892 * either receive fewer messages than they asked for, or they wish to
1893 * populate the MSI-X table sparsely. This method allows the driver
1894 * to specify what layout it wants. It must be called after a
1895 * successful pci_alloc_msix() but before any of the associated
1896 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1897 *
1898 * The 'vectors' array contains 'count' message vectors. The array
1899 * maps directly to the MSI-X table in that index 0 in the array
1900 * specifies the vector for the first message in the MSI-X table, etc.
1901 * The vector value in each array index can either be 0 to indicate
1902 * that no vector should be assigned to a message slot, or it can be a
1903 * number from 1 to N (where N is the count returned from a
1904 * succcessful call to pci_alloc_msix()) to indicate which message
1905 * vector (IRQ) to be used for the corresponding message.
1906 *
1907 * On successful return, each message with a non-zero vector will have
1908 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1909 * 1. Additionally, if any of the IRQs allocated via the previous
1910 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1911 * will be freed back to the system automatically.
1912 *
1913 * For example, suppose a driver has a MSI-X table with 6 messages and
1914 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1915 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1916 * C. After the call to pci_alloc_msix(), the device will be setup to
1917 * have an MSI-X table of ABC--- (where - means no vector assigned).
1918 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 },
1919 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1920 * be freed back to the system. This device will also have valid
1921 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1922 *
1923 * In any case, the SYS_RES_IRQ rid X will always map to the message
1924 * at MSI-X table index X - 1 and will only be valid if a vector is
1925 * assigned to that table entry.
1926 */
1927 int
pci_remap_msix_method(device_t dev,device_t child,int count,const u_int * vectors)1928 pci_remap_msix_method(device_t dev, device_t child, int count,
1929 const u_int *vectors)
1930 {
1931 struct pci_devinfo *dinfo = device_get_ivars(child);
1932 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1933 struct resource_list_entry *rle;
1934 int i, irq, j, *used;
1935
1936 /*
1937 * Have to have at least one message in the table but the
1938 * table can't be bigger than the actual MSI-X table in the
1939 * device.
1940 */
1941 if (count == 0 || count > msix->msix_msgnum)
1942 return (EINVAL);
1943
1944 /* Sanity check the vectors. */
1945 for (i = 0; i < count; i++)
1946 if (vectors[i] > msix->msix_alloc)
1947 return (EINVAL);
1948
1949 /*
1950 * Make sure there aren't any holes in the vectors to be used.
1951 * It's a big pain to support it, and it doesn't really make
1952 * sense anyway. Also, at least one vector must be used.
1953 */
1954 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1955 M_ZERO);
1956 for (i = 0; i < count; i++)
1957 if (vectors[i] != 0)
1958 used[vectors[i] - 1] = 1;
1959 for (i = 0; i < msix->msix_alloc - 1; i++)
1960 if (used[i] == 0 && used[i + 1] == 1) {
1961 free(used, M_DEVBUF);
1962 return (EINVAL);
1963 }
1964 if (used[0] != 1) {
1965 free(used, M_DEVBUF);
1966 return (EINVAL);
1967 }
1968
1969 /* Make sure none of the resources are allocated. */
1970 for (i = 0; i < msix->msix_table_len; i++) {
1971 if (msix->msix_table[i].mte_vector == 0)
1972 continue;
1973 if (msix->msix_table[i].mte_handlers > 0) {
1974 free(used, M_DEVBUF);
1975 return (EBUSY);
1976 }
1977 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1978 KASSERT(rle != NULL, ("missing resource"));
1979 if (rle->res != NULL) {
1980 free(used, M_DEVBUF);
1981 return (EBUSY);
1982 }
1983 }
1984
1985 /* Free the existing resource list entries. */
1986 for (i = 0; i < msix->msix_table_len; i++) {
1987 if (msix->msix_table[i].mte_vector == 0)
1988 continue;
1989 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1990 }
1991
1992 /*
1993 * Build the new virtual table keeping track of which vectors are
1994 * used.
1995 */
1996 free(msix->msix_table, M_DEVBUF);
1997 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count,
1998 M_DEVBUF, M_WAITOK | M_ZERO);
1999 for (i = 0; i < count; i++)
2000 msix->msix_table[i].mte_vector = vectors[i];
2001 msix->msix_table_len = count;
2002
2003 /* Free any unused IRQs and resize the vectors array if necessary. */
2004 j = msix->msix_alloc - 1;
2005 if (used[j] == 0) {
2006 struct msix_vector *vec;
2007
2008 while (used[j] == 0) {
2009 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
2010 msix->msix_vectors[j].mv_irq);
2011 j--;
2012 }
2013 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
2014 M_WAITOK);
2015 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
2016 (j + 1));
2017 free(msix->msix_vectors, M_DEVBUF);
2018 msix->msix_vectors = vec;
2019 msix->msix_alloc = j + 1;
2020 }
2021 free(used, M_DEVBUF);
2022
2023 /* Map the IRQs onto the rids. */
2024 for (i = 0; i < count; i++) {
2025 if (vectors[i] == 0)
2026 continue;
2027 irq = msix->msix_vectors[vectors[i] - 1].mv_irq;
2028 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
2029 irq, 1);
2030 }
2031
2032 if (bootverbose) {
2033 device_printf(child, "Remapped MSI-X IRQs as: ");
2034 for (i = 0; i < count; i++) {
2035 if (i != 0)
2036 printf(", ");
2037 if (vectors[i] == 0)
2038 printf("---");
2039 else
2040 printf("%d",
2041 msix->msix_vectors[vectors[i] - 1].mv_irq);
2042 }
2043 printf("\n");
2044 }
2045
2046 return (0);
2047 }
2048
2049 static int
pci_release_msix(device_t dev,device_t child)2050 pci_release_msix(device_t dev, device_t child)
2051 {
2052 struct pci_devinfo *dinfo = device_get_ivars(child);
2053 struct pcicfg_msix *msix = &dinfo->cfg.msix;
2054 struct resource_list_entry *rle;
2055 int i;
2056
2057 /* Do we have any messages to release? */
2058 if (msix->msix_alloc == 0)
2059 return (ENODEV);
2060
2061 /* Make sure none of the resources are allocated. */
2062 for (i = 0; i < msix->msix_table_len; i++) {
2063 if (msix->msix_table[i].mte_vector == 0)
2064 continue;
2065 if (msix->msix_table[i].mte_handlers > 0)
2066 return (EBUSY);
2067 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2068 KASSERT(rle != NULL, ("missing resource"));
2069 if (rle->res != NULL)
2070 return (EBUSY);
2071 }
2072
2073 /* Update control register to disable MSI-X. */
2074 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
2075 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
2076 msix->msix_ctrl, 2);
2077
2078 /* Free the resource list entries. */
2079 for (i = 0; i < msix->msix_table_len; i++) {
2080 if (msix->msix_table[i].mte_vector == 0)
2081 continue;
2082 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2083 }
2084 free(msix->msix_table, M_DEVBUF);
2085 msix->msix_table_len = 0;
2086
2087 /* Release the IRQs. */
2088 for (i = 0; i < msix->msix_alloc; i++)
2089 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
2090 msix->msix_vectors[i].mv_irq);
2091 free(msix->msix_vectors, M_DEVBUF);
2092 msix->msix_alloc = 0;
2093 return (0);
2094 }
2095
2096 /*
2097 * Return the max supported MSI-X messages this device supports.
2098 * Basically, assuming the MD code can alloc messages, this function
2099 * should return the maximum value that pci_alloc_msix() can return.
2100 * Thus, it is subject to the tunables, etc.
2101 */
2102 int
pci_msix_count_method(device_t dev,device_t child)2103 pci_msix_count_method(device_t dev, device_t child)
2104 {
2105 struct pci_devinfo *dinfo = device_get_ivars(child);
2106 struct pcicfg_msix *msix = &dinfo->cfg.msix;
2107
2108 if (pci_do_msix && msix->msix_location != 0)
2109 return (msix->msix_msgnum);
2110 return (0);
2111 }
2112
2113 int
pci_msix_pba_bar_method(device_t dev,device_t child)2114 pci_msix_pba_bar_method(device_t dev, device_t child)
2115 {
2116 struct pci_devinfo *dinfo = device_get_ivars(child);
2117 struct pcicfg_msix *msix = &dinfo->cfg.msix;
2118
2119 if (pci_do_msix && msix->msix_location != 0)
2120 return (msix->msix_pba_bar);
2121 return (-1);
2122 }
2123
2124 int
pci_msix_table_bar_method(device_t dev,device_t child)2125 pci_msix_table_bar_method(device_t dev, device_t child)
2126 {
2127 struct pci_devinfo *dinfo = device_get_ivars(child);
2128 struct pcicfg_msix *msix = &dinfo->cfg.msix;
2129
2130 if (pci_do_msix && msix->msix_location != 0)
2131 return (msix->msix_table_bar);
2132 return (-1);
2133 }
2134
2135 /*
2136 * HyperTransport MSI mapping control
2137 */
2138 void
pci_ht_map_msi(device_t dev,uint64_t addr)2139 pci_ht_map_msi(device_t dev, uint64_t addr)
2140 {
2141 struct pci_devinfo *dinfo = device_get_ivars(dev);
2142 struct pcicfg_ht *ht = &dinfo->cfg.ht;
2143
2144 if (!ht->ht_msimap)
2145 return;
2146
2147 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
2148 ht->ht_msiaddr >> 20 == addr >> 20) {
2149 /* Enable MSI -> HT mapping. */
2150 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
2151 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
2152 ht->ht_msictrl, 2);
2153 }
2154
2155 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
2156 /* Disable MSI -> HT mapping. */
2157 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
2158 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
2159 ht->ht_msictrl, 2);
2160 }
2161 }
2162
2163 int
pci_get_relaxed_ordering_enabled(device_t dev)2164 pci_get_relaxed_ordering_enabled(device_t dev)
2165 {
2166 struct pci_devinfo *dinfo = device_get_ivars(dev);
2167 int cap;
2168 uint16_t val;
2169
2170 cap = dinfo->cfg.pcie.pcie_location;
2171 if (cap == 0)
2172 return (0);
2173 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
2174 val &= PCIEM_CTL_RELAXED_ORD_ENABLE;
2175 return (val != 0);
2176 }
2177
2178 int
pci_get_max_payload(device_t dev)2179 pci_get_max_payload(device_t dev)
2180 {
2181 struct pci_devinfo *dinfo = device_get_ivars(dev);
2182 int cap;
2183 uint16_t val;
2184
2185 cap = dinfo->cfg.pcie.pcie_location;
2186 if (cap == 0)
2187 return (0);
2188 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
2189 val &= PCIEM_CTL_MAX_PAYLOAD;
2190 val >>= 5;
2191 return (1 << (val + 7));
2192 }
2193
2194 int
pci_get_max_read_req(device_t dev)2195 pci_get_max_read_req(device_t dev)
2196 {
2197 struct pci_devinfo *dinfo = device_get_ivars(dev);
2198 int cap;
2199 uint16_t val;
2200
2201 cap = dinfo->cfg.pcie.pcie_location;
2202 if (cap == 0)
2203 return (0);
2204 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
2205 val &= PCIEM_CTL_MAX_READ_REQUEST;
2206 val >>= 12;
2207 return (1 << (val + 7));
2208 }
2209
2210 int
pci_set_max_read_req(device_t dev,int size)2211 pci_set_max_read_req(device_t dev, int size)
2212 {
2213 struct pci_devinfo *dinfo = device_get_ivars(dev);
2214 int cap;
2215 uint16_t val;
2216
2217 cap = dinfo->cfg.pcie.pcie_location;
2218 if (cap == 0)
2219 return (0);
2220 if (size < 128)
2221 size = 128;
2222 if (size > 4096)
2223 size = 4096;
2224 size = (1 << (fls(size) - 1));
2225 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
2226 val &= ~PCIEM_CTL_MAX_READ_REQUEST;
2227 val |= (fls(size) - 8) << 12;
2228 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2);
2229 return (size);
2230 }
2231
2232 uint32_t
pcie_read_config(device_t dev,int reg,int width)2233 pcie_read_config(device_t dev, int reg, int width)
2234 {
2235 struct pci_devinfo *dinfo = device_get_ivars(dev);
2236 int cap;
2237
2238 cap = dinfo->cfg.pcie.pcie_location;
2239 if (cap == 0) {
2240 if (width == 2)
2241 return (0xffff);
2242 return (0xffffffff);
2243 }
2244
2245 return (pci_read_config(dev, cap + reg, width));
2246 }
2247
2248 void
pcie_write_config(device_t dev,int reg,uint32_t value,int width)2249 pcie_write_config(device_t dev, int reg, uint32_t value, int width)
2250 {
2251 struct pci_devinfo *dinfo = device_get_ivars(dev);
2252 int cap;
2253
2254 cap = dinfo->cfg.pcie.pcie_location;
2255 if (cap == 0)
2256 return;
2257 pci_write_config(dev, cap + reg, value, width);
2258 }
2259
2260 /*
2261 * Adjusts a PCI-e capability register by clearing the bits in mask
2262 * and setting the bits in (value & mask). Bits not set in mask are
2263 * not adjusted.
2264 *
2265 * Returns the old value on success or all ones on failure.
2266 */
2267 uint32_t
pcie_adjust_config(device_t dev,int reg,uint32_t mask,uint32_t value,int width)2268 pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value,
2269 int width)
2270 {
2271 struct pci_devinfo *dinfo = device_get_ivars(dev);
2272 uint32_t old, new;
2273 int cap;
2274
2275 cap = dinfo->cfg.pcie.pcie_location;
2276 if (cap == 0) {
2277 if (width == 2)
2278 return (0xffff);
2279 return (0xffffffff);
2280 }
2281
2282 old = pci_read_config(dev, cap + reg, width);
2283 new = old & ~mask;
2284 new |= (value & mask);
2285 pci_write_config(dev, cap + reg, new, width);
2286 return (old);
2287 }
2288
2289 /*
2290 * Support for MSI message signalled interrupts.
2291 */
2292 void
pci_enable_msi_method(device_t dev,device_t child,uint64_t address,uint16_t data)2293 pci_enable_msi_method(device_t dev, device_t child, uint64_t address,
2294 uint16_t data)
2295 {
2296 struct pci_devinfo *dinfo = device_get_ivars(child);
2297 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2298
2299 /* Write data and address values. */
2300 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR,
2301 address & 0xffffffff, 4);
2302 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
2303 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH,
2304 address >> 32, 4);
2305 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT,
2306 data, 2);
2307 } else
2308 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data,
2309 2);
2310
2311 /* Enable MSI in the control register. */
2312 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
2313 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2314 msi->msi_ctrl, 2);
2315
2316 /* Enable MSI -> HT mapping. */
2317 pci_ht_map_msi(child, address);
2318 }
2319
2320 void
pci_disable_msi_method(device_t dev,device_t child)2321 pci_disable_msi_method(device_t dev, device_t child)
2322 {
2323 struct pci_devinfo *dinfo = device_get_ivars(child);
2324 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2325
2326 /* Disable MSI -> HT mapping. */
2327 pci_ht_map_msi(child, 0);
2328
2329 /* Disable MSI in the control register. */
2330 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
2331 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2332 msi->msi_ctrl, 2);
2333 }
2334
2335 /*
2336 * Restore MSI registers during resume. If MSI is enabled then
2337 * restore the data and address registers in addition to the control
2338 * register.
2339 */
2340 static void
pci_resume_msi(device_t dev)2341 pci_resume_msi(device_t dev)
2342 {
2343 struct pci_devinfo *dinfo = device_get_ivars(dev);
2344 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2345 uint64_t address;
2346 uint16_t data;
2347
2348 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
2349 address = msi->msi_addr;
2350 data = msi->msi_data;
2351 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
2352 address & 0xffffffff, 4);
2353 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
2354 pci_write_config(dev, msi->msi_location +
2355 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
2356 pci_write_config(dev, msi->msi_location +
2357 PCIR_MSI_DATA_64BIT, data, 2);
2358 } else
2359 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
2360 data, 2);
2361 }
2362 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
2363 2);
2364 }
2365
2366 static int
pci_remap_intr_method(device_t bus,device_t dev,u_int irq)2367 pci_remap_intr_method(device_t bus, device_t dev, u_int irq)
2368 {
2369 struct pci_devinfo *dinfo = device_get_ivars(dev);
2370 pcicfgregs *cfg = &dinfo->cfg;
2371 struct resource_list_entry *rle;
2372 struct msix_table_entry *mte;
2373 struct msix_vector *mv;
2374 uint64_t addr;
2375 uint32_t data;
2376 int error, i, j;
2377
2378 /*
2379 * Handle MSI first. We try to find this IRQ among our list
2380 * of MSI IRQs. If we find it, we request updated address and
2381 * data registers and apply the results.
2382 */
2383 if (cfg->msi.msi_alloc > 0) {
2384
2385 /* If we don't have any active handlers, nothing to do. */
2386 if (cfg->msi.msi_handlers == 0)
2387 return (0);
2388 for (i = 0; i < cfg->msi.msi_alloc; i++) {
2389 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
2390 i + 1);
2391 if (rle->start == irq) {
2392 error = PCIB_MAP_MSI(device_get_parent(bus),
2393 dev, irq, &addr, &data);
2394 if (error)
2395 return (error);
2396 pci_disable_msi(dev);
2397 dinfo->cfg.msi.msi_addr = addr;
2398 dinfo->cfg.msi.msi_data = data;
2399 pci_enable_msi(dev, addr, data);
2400 return (0);
2401 }
2402 }
2403 return (ENOENT);
2404 }
2405
2406 /*
2407 * For MSI-X, we check to see if we have this IRQ. If we do,
2408 * we request the updated mapping info. If that works, we go
2409 * through all the slots that use this IRQ and update them.
2410 */
2411 if (cfg->msix.msix_alloc > 0) {
2412 for (i = 0; i < cfg->msix.msix_alloc; i++) {
2413 mv = &cfg->msix.msix_vectors[i];
2414 if (mv->mv_irq == irq) {
2415 error = PCIB_MAP_MSI(device_get_parent(bus),
2416 dev, irq, &addr, &data);
2417 if (error)
2418 return (error);
2419 mv->mv_address = addr;
2420 mv->mv_data = data;
2421 for (j = 0; j < cfg->msix.msix_table_len; j++) {
2422 mte = &cfg->msix.msix_table[j];
2423 if (mte->mte_vector != i + 1)
2424 continue;
2425 if (mte->mte_handlers == 0)
2426 continue;
2427 pci_mask_msix(dev, j);
2428 pci_enable_msix(dev, j, addr, data);
2429 pci_unmask_msix(dev, j);
2430 }
2431 }
2432 }
2433 return (ENOENT);
2434 }
2435
2436 return (ENOENT);
2437 }
2438
2439 /*
2440 * Returns true if the specified device is blacklisted because MSI
2441 * doesn't work.
2442 */
2443 int
pci_msi_device_blacklisted(device_t dev)2444 pci_msi_device_blacklisted(device_t dev)
2445 {
2446
2447 if (!pci_honor_msi_blacklist)
2448 return (0);
2449
2450 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI));
2451 }
2452
2453 /*
2454 * Determine if MSI is blacklisted globally on this system. Currently,
2455 * we just check for blacklisted chipsets as represented by the
2456 * host-PCI bridge at device 0:0:0. In the future, it may become
2457 * necessary to check other system attributes, such as the kenv values
2458 * that give the motherboard manufacturer and model number.
2459 */
2460 static int
pci_msi_blacklisted(void)2461 pci_msi_blacklisted(void)
2462 {
2463 device_t dev;
2464
2465 if (!pci_honor_msi_blacklist)
2466 return (0);
2467
2468 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
2469 if (!(pcie_chipset || pcix_chipset)) {
2470 if (vm_guest != VM_GUEST_NO) {
2471 /*
2472 * Whitelist older chipsets in virtual
2473 * machines known to support MSI.
2474 */
2475 dev = pci_find_bsf(0, 0, 0);
2476 if (dev != NULL)
2477 return (!pci_has_quirk(pci_get_devid(dev),
2478 PCI_QUIRK_ENABLE_MSI_VM));
2479 }
2480 return (1);
2481 }
2482
2483 dev = pci_find_bsf(0, 0, 0);
2484 if (dev != NULL)
2485 return (pci_msi_device_blacklisted(dev));
2486 return (0);
2487 }
2488
2489 /*
2490 * Returns true if the specified device is blacklisted because MSI-X
2491 * doesn't work. Note that this assumes that if MSI doesn't work,
2492 * MSI-X doesn't either.
2493 */
2494 int
pci_msix_device_blacklisted(device_t dev)2495 pci_msix_device_blacklisted(device_t dev)
2496 {
2497
2498 if (!pci_honor_msi_blacklist)
2499 return (0);
2500
2501 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX))
2502 return (1);
2503
2504 return (pci_msi_device_blacklisted(dev));
2505 }
2506
2507 /*
2508 * Determine if MSI-X is blacklisted globally on this system. If MSI
2509 * is blacklisted, assume that MSI-X is as well. Check for additional
2510 * chipsets where MSI works but MSI-X does not.
2511 */
2512 static int
pci_msix_blacklisted(void)2513 pci_msix_blacklisted(void)
2514 {
2515 device_t dev;
2516
2517 if (!pci_honor_msi_blacklist)
2518 return (0);
2519
2520 dev = pci_find_bsf(0, 0, 0);
2521 if (dev != NULL && pci_has_quirk(pci_get_devid(dev),
2522 PCI_QUIRK_DISABLE_MSIX))
2523 return (1);
2524
2525 return (pci_msi_blacklisted());
2526 }
2527
2528 /*
2529 * Attempt to allocate *count MSI messages. The actual number allocated is
2530 * returned in *count. After this function returns, each message will be
2531 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
2532 */
2533 int
pci_alloc_msi_method(device_t dev,device_t child,int * count)2534 pci_alloc_msi_method(device_t dev, device_t child, int *count)
2535 {
2536 struct pci_devinfo *dinfo = device_get_ivars(child);
2537 pcicfgregs *cfg = &dinfo->cfg;
2538 struct resource_list_entry *rle;
2539 int actual, error, i, irqs[32];
2540 uint16_t ctrl;
2541
2542 /* Don't let count == 0 get us into trouble. */
2543 if (*count == 0)
2544 return (EINVAL);
2545
2546 /* If rid 0 is allocated, then fail. */
2547 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
2548 if (rle != NULL && rle->res != NULL)
2549 return (ENXIO);
2550
2551 /* Already have allocated messages? */
2552 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
2553 return (ENXIO);
2554
2555 /* If MSI is blacklisted for this system, fail. */
2556 if (pci_msi_blacklisted())
2557 return (ENXIO);
2558
2559 /* MSI capability present? */
2560 if (cfg->msi.msi_location == 0 || !pci_do_msi)
2561 return (ENODEV);
2562
2563 if (bootverbose)
2564 device_printf(child,
2565 "attempting to allocate %d MSI vectors (%d supported)\n",
2566 *count, cfg->msi.msi_msgnum);
2567
2568 /* Don't ask for more than the device supports. */
2569 actual = min(*count, cfg->msi.msi_msgnum);
2570
2571 /* Don't ask for more than 32 messages. */
2572 actual = min(actual, 32);
2573
2574 /* MSI requires power of 2 number of messages. */
2575 if (!powerof2(actual))
2576 return (EINVAL);
2577
2578 for (;;) {
2579 /* Try to allocate N messages. */
2580 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
2581 actual, irqs);
2582 if (error == 0)
2583 break;
2584 if (actual == 1)
2585 return (error);
2586
2587 /* Try N / 2. */
2588 actual >>= 1;
2589 }
2590
2591 /*
2592 * We now have N actual messages mapped onto SYS_RES_IRQ
2593 * resources in the irqs[] array, so add new resources
2594 * starting at rid 1.
2595 */
2596 for (i = 0; i < actual; i++)
2597 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2598 irqs[i], irqs[i], 1);
2599
2600 if (bootverbose) {
2601 if (actual == 1)
2602 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
2603 else {
2604 int run;
2605
2606 /*
2607 * Be fancy and try to print contiguous runs
2608 * of IRQ values as ranges. 'run' is true if
2609 * we are in a range.
2610 */
2611 device_printf(child, "using IRQs %d", irqs[0]);
2612 run = 0;
2613 for (i = 1; i < actual; i++) {
2614
2615 /* Still in a run? */
2616 if (irqs[i] == irqs[i - 1] + 1) {
2617 run = 1;
2618 continue;
2619 }
2620
2621 /* Finish previous range. */
2622 if (run) {
2623 printf("-%d", irqs[i - 1]);
2624 run = 0;
2625 }
2626
2627 /* Start new range. */
2628 printf(",%d", irqs[i]);
2629 }
2630
2631 /* Unfinished range? */
2632 if (run)
2633 printf("-%d", irqs[actual - 1]);
2634 printf(" for MSI\n");
2635 }
2636 }
2637
2638 /* Update control register with actual count. */
2639 ctrl = cfg->msi.msi_ctrl;
2640 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2641 ctrl |= (ffs(actual) - 1) << 4;
2642 cfg->msi.msi_ctrl = ctrl;
2643 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2644
2645 /* Update counts of alloc'd messages. */
2646 cfg->msi.msi_alloc = actual;
2647 cfg->msi.msi_handlers = 0;
2648 *count = actual;
2649 return (0);
2650 }
2651
2652 /* Release the MSI messages associated with this device. */
2653 int
pci_release_msi_method(device_t dev,device_t child)2654 pci_release_msi_method(device_t dev, device_t child)
2655 {
2656 struct pci_devinfo *dinfo = device_get_ivars(child);
2657 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2658 struct resource_list_entry *rle;
2659 int error, i, irqs[32];
2660
2661 /* Try MSI-X first. */
2662 error = pci_release_msix(dev, child);
2663 if (error != ENODEV)
2664 return (error);
2665
2666 /* Do we have any messages to release? */
2667 if (msi->msi_alloc == 0)
2668 return (ENODEV);
2669 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2670
2671 /* Make sure none of the resources are allocated. */
2672 if (msi->msi_handlers > 0)
2673 return (EBUSY);
2674 for (i = 0; i < msi->msi_alloc; i++) {
2675 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2676 KASSERT(rle != NULL, ("missing MSI resource"));
2677 if (rle->res != NULL)
2678 return (EBUSY);
2679 irqs[i] = rle->start;
2680 }
2681
2682 /* Update control register with 0 count. */
2683 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2684 ("%s: MSI still enabled", __func__));
2685 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2686 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2687 msi->msi_ctrl, 2);
2688
2689 /* Release the messages. */
2690 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2691 for (i = 0; i < msi->msi_alloc; i++)
2692 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2693
2694 /* Update alloc count. */
2695 msi->msi_alloc = 0;
2696 msi->msi_addr = 0;
2697 msi->msi_data = 0;
2698 return (0);
2699 }
2700
2701 /*
2702 * Return the max supported MSI messages this device supports.
2703 * Basically, assuming the MD code can alloc messages, this function
2704 * should return the maximum value that pci_alloc_msi() can return.
2705 * Thus, it is subject to the tunables, etc.
2706 */
2707 int
pci_msi_count_method(device_t dev,device_t child)2708 pci_msi_count_method(device_t dev, device_t child)
2709 {
2710 struct pci_devinfo *dinfo = device_get_ivars(child);
2711 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2712
2713 if (pci_do_msi && msi->msi_location != 0)
2714 return (msi->msi_msgnum);
2715 return (0);
2716 }
2717
2718 /* free pcicfgregs structure and all depending data structures */
2719
2720 int
pci_freecfg(struct pci_devinfo * dinfo)2721 pci_freecfg(struct pci_devinfo *dinfo)
2722 {
2723 struct devlist *devlist_head;
2724 struct pci_map *pm, *next;
2725 int i;
2726
2727 devlist_head = &pci_devq;
2728
2729 if (dinfo->cfg.vpd.vpd_reg) {
2730 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2731 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2732 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2733 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2734 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2735 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2736 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2737 }
2738 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) {
2739 free(pm, M_DEVBUF);
2740 }
2741 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2742 free(dinfo, M_DEVBUF);
2743
2744 /* increment the generation count */
2745 pci_generation++;
2746
2747 /* we're losing one device */
2748 pci_numdevs--;
2749 return (0);
2750 }
2751
2752 /*
2753 * PCI power manangement
2754 */
2755 int
pci_set_powerstate_method(device_t dev,device_t child,int state)2756 pci_set_powerstate_method(device_t dev, device_t child, int state)
2757 {
2758 struct pci_devinfo *dinfo = device_get_ivars(child);
2759 pcicfgregs *cfg = &dinfo->cfg;
2760 uint16_t status;
2761 int oldstate, highest, delay;
2762
2763 if (cfg->pp.pp_cap == 0)
2764 return (EOPNOTSUPP);
2765
2766 /*
2767 * Optimize a no state change request away. While it would be OK to
2768 * write to the hardware in theory, some devices have shown odd
2769 * behavior when going from D3 -> D3.
2770 */
2771 oldstate = pci_get_powerstate(child);
2772 if (oldstate == state)
2773 return (0);
2774
2775 /*
2776 * The PCI power management specification states that after a state
2777 * transition between PCI power states, system software must
2778 * guarantee a minimal delay before the function accesses the device.
2779 * Compute the worst case delay that we need to guarantee before we
2780 * access the device. Many devices will be responsive much more
2781 * quickly than this delay, but there are some that don't respond
2782 * instantly to state changes. Transitions to/from D3 state require
2783 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2784 * is done below with DELAY rather than a sleeper function because
2785 * this function can be called from contexts where we cannot sleep.
2786 */
2787 highest = (oldstate > state) ? oldstate : state;
2788 if (highest == PCI_POWERSTATE_D3)
2789 delay = 10000;
2790 else if (highest == PCI_POWERSTATE_D2)
2791 delay = 200;
2792 else
2793 delay = 0;
2794 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2795 & ~PCIM_PSTAT_DMASK;
2796 switch (state) {
2797 case PCI_POWERSTATE_D0:
2798 status |= PCIM_PSTAT_D0;
2799 break;
2800 case PCI_POWERSTATE_D1:
2801 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2802 return (EOPNOTSUPP);
2803 status |= PCIM_PSTAT_D1;
2804 break;
2805 case PCI_POWERSTATE_D2:
2806 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2807 return (EOPNOTSUPP);
2808 status |= PCIM_PSTAT_D2;
2809 break;
2810 case PCI_POWERSTATE_D3:
2811 status |= PCIM_PSTAT_D3;
2812 break;
2813 default:
2814 return (EINVAL);
2815 }
2816
2817 if (bootverbose)
2818 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate,
2819 state);
2820
2821 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2822 if (delay)
2823 DELAY(delay);
2824 return (0);
2825 }
2826
2827 int
pci_get_powerstate_method(device_t dev,device_t child)2828 pci_get_powerstate_method(device_t dev, device_t child)
2829 {
2830 struct pci_devinfo *dinfo = device_get_ivars(child);
2831 pcicfgregs *cfg = &dinfo->cfg;
2832 uint16_t status;
2833 int result;
2834
2835 if (cfg->pp.pp_cap != 0) {
2836 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2837 switch (status & PCIM_PSTAT_DMASK) {
2838 case PCIM_PSTAT_D0:
2839 result = PCI_POWERSTATE_D0;
2840 break;
2841 case PCIM_PSTAT_D1:
2842 result = PCI_POWERSTATE_D1;
2843 break;
2844 case PCIM_PSTAT_D2:
2845 result = PCI_POWERSTATE_D2;
2846 break;
2847 case PCIM_PSTAT_D3:
2848 result = PCI_POWERSTATE_D3;
2849 break;
2850 default:
2851 result = PCI_POWERSTATE_UNKNOWN;
2852 break;
2853 }
2854 } else {
2855 /* No support, device is always at D0 */
2856 result = PCI_POWERSTATE_D0;
2857 }
2858 return (result);
2859 }
2860
2861 /*
2862 * Some convenience functions for PCI device drivers.
2863 */
2864
2865 static __inline void
pci_set_command_bit(device_t dev,device_t child,uint16_t bit)2866 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2867 {
2868 uint16_t command;
2869
2870 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2871 command |= bit;
2872 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2873 }
2874
2875 static __inline void
pci_clear_command_bit(device_t dev,device_t child,uint16_t bit)2876 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2877 {
2878 uint16_t command;
2879
2880 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2881 command &= ~bit;
2882 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2883 }
2884
2885 int
pci_enable_busmaster_method(device_t dev,device_t child)2886 pci_enable_busmaster_method(device_t dev, device_t child)
2887 {
2888 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2889 return (0);
2890 }
2891
2892 int
pci_disable_busmaster_method(device_t dev,device_t child)2893 pci_disable_busmaster_method(device_t dev, device_t child)
2894 {
2895 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2896 return (0);
2897 }
2898
2899 int
pci_enable_io_method(device_t dev,device_t child,int space)2900 pci_enable_io_method(device_t dev, device_t child, int space)
2901 {
2902 uint16_t bit;
2903
2904 switch(space) {
2905 case SYS_RES_IOPORT:
2906 bit = PCIM_CMD_PORTEN;
2907 break;
2908 case SYS_RES_MEMORY:
2909 bit = PCIM_CMD_MEMEN;
2910 break;
2911 default:
2912 return (EINVAL);
2913 }
2914 pci_set_command_bit(dev, child, bit);
2915 return (0);
2916 }
2917
2918 int
pci_disable_io_method(device_t dev,device_t child,int space)2919 pci_disable_io_method(device_t dev, device_t child, int space)
2920 {
2921 uint16_t bit;
2922
2923 switch(space) {
2924 case SYS_RES_IOPORT:
2925 bit = PCIM_CMD_PORTEN;
2926 break;
2927 case SYS_RES_MEMORY:
2928 bit = PCIM_CMD_MEMEN;
2929 break;
2930 default:
2931 return (EINVAL);
2932 }
2933 pci_clear_command_bit(dev, child, bit);
2934 return (0);
2935 }
2936
2937 /*
2938 * New style pci driver. Parent device is either a pci-host-bridge or a
2939 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2940 */
2941
2942 void
pci_print_verbose(struct pci_devinfo * dinfo)2943 pci_print_verbose(struct pci_devinfo *dinfo)
2944 {
2945
2946 if (bootverbose) {
2947 pcicfgregs *cfg = &dinfo->cfg;
2948
2949 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2950 cfg->vendor, cfg->device, cfg->revid);
2951 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2952 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2953 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2954 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2955 cfg->mfdev);
2956 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2957 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2958 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2959 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2960 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2961 if (cfg->intpin > 0)
2962 printf("\tintpin=%c, irq=%d\n",
2963 cfg->intpin +'a' -1, cfg->intline);
2964 if (cfg->pp.pp_cap) {
2965 uint16_t status;
2966
2967 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2968 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2969 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2970 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2971 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2972 status & PCIM_PSTAT_DMASK);
2973 }
2974 if (cfg->msi.msi_location) {
2975 int ctrl;
2976
2977 ctrl = cfg->msi.msi_ctrl;
2978 printf("\tMSI supports %d message%s%s%s\n",
2979 cfg->msi.msi_msgnum,
2980 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2981 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2982 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2983 }
2984 if (cfg->msix.msix_location) {
2985 printf("\tMSI-X supports %d message%s ",
2986 cfg->msix.msix_msgnum,
2987 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2988 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2989 printf("in map 0x%x\n",
2990 cfg->msix.msix_table_bar);
2991 else
2992 printf("in maps 0x%x and 0x%x\n",
2993 cfg->msix.msix_table_bar,
2994 cfg->msix.msix_pba_bar);
2995 }
2996 }
2997 }
2998
2999 static int
pci_porten(device_t dev)3000 pci_porten(device_t dev)
3001 {
3002 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0;
3003 }
3004
3005 static int
pci_memen(device_t dev)3006 pci_memen(device_t dev)
3007 {
3008 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0;
3009 }
3010
3011 void
pci_read_bar(device_t dev,int reg,pci_addr_t * mapp,pci_addr_t * testvalp,int * bar64)3012 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp,
3013 int *bar64)
3014 {
3015 struct pci_devinfo *dinfo;
3016 pci_addr_t map, testval;
3017 int ln2range;
3018 uint16_t cmd;
3019
3020 /*
3021 * The device ROM BAR is special. It is always a 32-bit
3022 * memory BAR. Bit 0 is special and should not be set when
3023 * sizing the BAR.
3024 */
3025 dinfo = device_get_ivars(dev);
3026 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) {
3027 map = pci_read_config(dev, reg, 4);
3028 pci_write_config(dev, reg, 0xfffffffe, 4);
3029 testval = pci_read_config(dev, reg, 4);
3030 pci_write_config(dev, reg, map, 4);
3031 *mapp = map;
3032 *testvalp = testval;
3033 if (bar64 != NULL)
3034 *bar64 = 0;
3035 return;
3036 }
3037
3038 map = pci_read_config(dev, reg, 4);
3039 ln2range = pci_maprange(map);
3040 if (ln2range == 64)
3041 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
3042
3043 /*
3044 * Disable decoding via the command register before
3045 * determining the BAR's length since we will be placing it in
3046 * a weird state.
3047 */
3048 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
3049 pci_write_config(dev, PCIR_COMMAND,
3050 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
3051
3052 /*
3053 * Determine the BAR's length by writing all 1's. The bottom
3054 * log_2(size) bits of the BAR will stick as 0 when we read
3055 * the value back.
3056 *
3057 * NB: according to the PCI Local Bus Specification, rev. 3.0:
3058 * "Software writes 0FFFFFFFFh to both registers, reads them back,
3059 * and combines the result into a 64-bit value." (section 6.2.5.1)
3060 *
3061 * Writes to both registers must be performed before attempting to
3062 * read back the size value.
3063 */
3064 testval = 0;
3065 pci_write_config(dev, reg, 0xffffffff, 4);
3066 if (ln2range == 64) {
3067 pci_write_config(dev, reg + 4, 0xffffffff, 4);
3068 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
3069 }
3070 testval |= pci_read_config(dev, reg, 4);
3071
3072 /*
3073 * Restore the original value of the BAR. We may have reprogrammed
3074 * the BAR of the low-level console device and when booting verbose,
3075 * we need the console device addressable.
3076 */
3077 pci_write_config(dev, reg, map, 4);
3078 if (ln2range == 64)
3079 pci_write_config(dev, reg + 4, map >> 32, 4);
3080 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
3081
3082 *mapp = map;
3083 *testvalp = testval;
3084 if (bar64 != NULL)
3085 *bar64 = (ln2range == 64);
3086 }
3087
3088 static void
pci_write_bar(device_t dev,struct pci_map * pm,pci_addr_t base)3089 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base)
3090 {
3091 struct pci_devinfo *dinfo;
3092 int ln2range;
3093
3094 /* The device ROM BAR is always a 32-bit memory BAR. */
3095 dinfo = device_get_ivars(dev);
3096 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
3097 ln2range = 32;
3098 else
3099 ln2range = pci_maprange(pm->pm_value);
3100 pci_write_config(dev, pm->pm_reg, base, 4);
3101 if (ln2range == 64)
3102 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4);
3103 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4);
3104 if (ln2range == 64)
3105 pm->pm_value |= (pci_addr_t)pci_read_config(dev,
3106 pm->pm_reg + 4, 4) << 32;
3107 }
3108
3109 struct pci_map *
pci_find_bar(device_t dev,int reg)3110 pci_find_bar(device_t dev, int reg)
3111 {
3112 struct pci_devinfo *dinfo;
3113 struct pci_map *pm;
3114
3115 dinfo = device_get_ivars(dev);
3116 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
3117 if (pm->pm_reg == reg)
3118 return (pm);
3119 }
3120 return (NULL);
3121 }
3122
3123 struct pci_map *
pci_first_bar(device_t dev)3124 pci_first_bar(device_t dev)
3125 {
3126 struct pci_devinfo *dinfo;
3127
3128 dinfo = device_get_ivars(dev);
3129 return (STAILQ_FIRST(&dinfo->cfg.maps));
3130 }
3131
3132 struct pci_map *
pci_next_bar(struct pci_map * pm)3133 pci_next_bar(struct pci_map *pm)
3134 {
3135 return (STAILQ_NEXT(pm, pm_link));
3136 }
3137
3138 int
pci_bar_enabled(device_t dev,struct pci_map * pm)3139 pci_bar_enabled(device_t dev, struct pci_map *pm)
3140 {
3141 struct pci_devinfo *dinfo;
3142 uint16_t cmd;
3143
3144 dinfo = device_get_ivars(dev);
3145 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) &&
3146 !(pm->pm_value & PCIM_BIOS_ENABLE))
3147 return (0);
3148 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
3149 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value))
3150 return ((cmd & PCIM_CMD_MEMEN) != 0);
3151 else
3152 return ((cmd & PCIM_CMD_PORTEN) != 0);
3153 }
3154
3155 struct pci_map *
pci_add_bar(device_t dev,int reg,pci_addr_t value,pci_addr_t size)3156 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size)
3157 {
3158 struct pci_devinfo *dinfo;
3159 struct pci_map *pm, *prev;
3160
3161 dinfo = device_get_ivars(dev);
3162 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO);
3163 pm->pm_reg = reg;
3164 pm->pm_value = value;
3165 pm->pm_size = size;
3166 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) {
3167 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x",
3168 reg));
3169 if (STAILQ_NEXT(prev, pm_link) == NULL ||
3170 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg)
3171 break;
3172 }
3173 if (prev != NULL)
3174 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link);
3175 else
3176 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link);
3177 return (pm);
3178 }
3179
3180 static void
pci_restore_bars(device_t dev)3181 pci_restore_bars(device_t dev)
3182 {
3183 struct pci_devinfo *dinfo;
3184 struct pci_map *pm;
3185 int ln2range;
3186
3187 dinfo = device_get_ivars(dev);
3188 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
3189 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
3190 ln2range = 32;
3191 else
3192 ln2range = pci_maprange(pm->pm_value);
3193 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4);
3194 if (ln2range == 64)
3195 pci_write_config(dev, pm->pm_reg + 4,
3196 pm->pm_value >> 32, 4);
3197 }
3198 }
3199
3200 /*
3201 * Add a resource based on a pci map register. Return 1 if the map
3202 * register is a 32bit map register or 2 if it is a 64bit register.
3203 */
3204 static int
pci_add_map(device_t bus,device_t dev,int reg,struct resource_list * rl,int force,int prefetch)3205 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl,
3206 int force, int prefetch)
3207 {
3208 struct pci_map *pm;
3209 pci_addr_t base, map, testval;
3210 pci_addr_t start, end, count;
3211 int barlen, basezero, flags, maprange, mapsize, type;
3212 uint16_t cmd;
3213 struct resource *res;
3214
3215 /*
3216 * The BAR may already exist if the device is a CardBus card
3217 * whose CIS is stored in this BAR.
3218 */
3219 pm = pci_find_bar(dev, reg);
3220 if (pm != NULL) {
3221 maprange = pci_maprange(pm->pm_value);
3222 barlen = maprange == 64 ? 2 : 1;
3223 return (barlen);
3224 }
3225
3226 pci_read_bar(dev, reg, &map, &testval, NULL);
3227 if (PCI_BAR_MEM(map)) {
3228 type = SYS_RES_MEMORY;
3229 if (map & PCIM_BAR_MEM_PREFETCH)
3230 prefetch = 1;
3231 } else
3232 type = SYS_RES_IOPORT;
3233 mapsize = pci_mapsize(testval);
3234 base = pci_mapbase(map);
3235 #ifdef __PCI_BAR_ZERO_VALID
3236 basezero = 0;
3237 #else
3238 basezero = base == 0;
3239 #endif
3240 maprange = pci_maprange(map);
3241 barlen = maprange == 64 ? 2 : 1;
3242
3243 /*
3244 * For I/O registers, if bottom bit is set, and the next bit up
3245 * isn't clear, we know we have a BAR that doesn't conform to the
3246 * spec, so ignore it. Also, sanity check the size of the data
3247 * areas to the type of memory involved. Memory must be at least
3248 * 16 bytes in size, while I/O ranges must be at least 4.
3249 */
3250 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
3251 return (barlen);
3252 if ((type == SYS_RES_MEMORY && mapsize < 4) ||
3253 (type == SYS_RES_IOPORT && mapsize < 2))
3254 return (barlen);
3255
3256 /* Save a record of this BAR. */
3257 pm = pci_add_bar(dev, reg, map, mapsize);
3258 if (bootverbose) {
3259 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
3260 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize);
3261 if (type == SYS_RES_IOPORT && !pci_porten(dev))
3262 printf(", port disabled\n");
3263 else if (type == SYS_RES_MEMORY && !pci_memen(dev))
3264 printf(", memory disabled\n");
3265 else
3266 printf(", enabled\n");
3267 }
3268
3269 /*
3270 * If base is 0, then we have problems if this architecture does
3271 * not allow that. It is best to ignore such entries for the
3272 * moment. These will be allocated later if the driver specifically
3273 * requests them. However, some removable buses look better when
3274 * all resources are allocated, so allow '0' to be overridden.
3275 *
3276 * Similarly treat maps whose values is the same as the test value
3277 * read back. These maps have had all f's written to them by the
3278 * BIOS in an attempt to disable the resources.
3279 */
3280 if (!force && (basezero || map == testval))
3281 return (barlen);
3282 if ((u_long)base != base) {
3283 device_printf(bus,
3284 "pci%d:%d:%d:%d bar %#x too many address bits",
3285 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev),
3286 pci_get_function(dev), reg);
3287 return (barlen);
3288 }
3289
3290 /*
3291 * This code theoretically does the right thing, but has
3292 * undesirable side effects in some cases where peripherals
3293 * respond oddly to having these bits enabled. Let the user
3294 * be able to turn them off (since pci_enable_io_modes is 1 by
3295 * default).
3296 */
3297 if (pci_enable_io_modes) {
3298 /* Turn on resources that have been left off by a lazy BIOS */
3299 if (type == SYS_RES_IOPORT && !pci_porten(dev)) {
3300 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
3301 cmd |= PCIM_CMD_PORTEN;
3302 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
3303 }
3304 if (type == SYS_RES_MEMORY && !pci_memen(dev)) {
3305 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
3306 cmd |= PCIM_CMD_MEMEN;
3307 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
3308 }
3309 } else {
3310 if (type == SYS_RES_IOPORT && !pci_porten(dev))
3311 return (barlen);
3312 if (type == SYS_RES_MEMORY && !pci_memen(dev))
3313 return (barlen);
3314 }
3315
3316 count = (pci_addr_t)1 << mapsize;
3317 flags = RF_ALIGNMENT_LOG2(mapsize);
3318 if (prefetch)
3319 flags |= RF_PREFETCHABLE;
3320 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) {
3321 start = 0; /* Let the parent decide. */
3322 end = ~0;
3323 } else {
3324 start = base;
3325 end = base + count - 1;
3326 }
3327 resource_list_add(rl, type, reg, start, end, count);
3328
3329 /*
3330 * Try to allocate the resource for this BAR from our parent
3331 * so that this resource range is already reserved. The
3332 * driver for this device will later inherit this resource in
3333 * pci_alloc_resource().
3334 */
3335 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count,
3336 flags);
3337 if ((pci_do_realloc_bars
3338 || pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_REALLOC_BAR))
3339 && res == NULL && (start != 0 || end != ~0)) {
3340 /*
3341 * If the allocation fails, try to allocate a resource for
3342 * this BAR using any available range. The firmware felt
3343 * it was important enough to assign a resource, so don't
3344 * disable decoding if we can help it.
3345 */
3346 resource_list_delete(rl, type, reg);
3347 resource_list_add(rl, type, reg, 0, ~0, count);
3348 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0,
3349 count, flags);
3350 }
3351 if (res == NULL) {
3352 /*
3353 * If the allocation fails, delete the resource list entry
3354 * and disable decoding for this device.
3355 *
3356 * If the driver requests this resource in the future,
3357 * pci_reserve_map() will try to allocate a fresh
3358 * resource range.
3359 */
3360 resource_list_delete(rl, type, reg);
3361 pci_disable_io(dev, type);
3362 if (bootverbose)
3363 device_printf(bus,
3364 "pci%d:%d:%d:%d bar %#x failed to allocate\n",
3365 pci_get_domain(dev), pci_get_bus(dev),
3366 pci_get_slot(dev), pci_get_function(dev), reg);
3367 } else {
3368 start = rman_get_start(res);
3369 pci_write_bar(dev, pm, start);
3370 }
3371 return (barlen);
3372 }
3373
3374 /*
3375 * For ATA devices we need to decide early what addressing mode to use.
3376 * Legacy demands that the primary and secondary ATA ports sits on the
3377 * same addresses that old ISA hardware did. This dictates that we use
3378 * those addresses and ignore the BAR's if we cannot set PCI native
3379 * addressing mode.
3380 */
3381 static void
pci_ata_maps(device_t bus,device_t dev,struct resource_list * rl,int force,uint32_t prefetchmask)3382 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force,
3383 uint32_t prefetchmask)
3384 {
3385 int rid, type, progif;
3386 #if 0
3387 /* if this device supports PCI native addressing use it */
3388 progif = pci_read_config(dev, PCIR_PROGIF, 1);
3389 if ((progif & 0x8a) == 0x8a) {
3390 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
3391 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
3392 printf("Trying ATA native PCI addressing mode\n");
3393 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
3394 }
3395 }
3396 #endif
3397 progif = pci_read_config(dev, PCIR_PROGIF, 1);
3398 type = SYS_RES_IOPORT;
3399 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
3400 pci_add_map(bus, dev, PCIR_BAR(0), rl, force,
3401 prefetchmask & (1 << 0));
3402 pci_add_map(bus, dev, PCIR_BAR(1), rl, force,
3403 prefetchmask & (1 << 1));
3404 } else {
3405 rid = PCIR_BAR(0);
3406 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
3407 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0,
3408 0x1f7, 8, 0);
3409 rid = PCIR_BAR(1);
3410 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
3411 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6,
3412 0x3f6, 1, 0);
3413 }
3414 if (progif & PCIP_STORAGE_IDE_MODESEC) {
3415 pci_add_map(bus, dev, PCIR_BAR(2), rl, force,
3416 prefetchmask & (1 << 2));
3417 pci_add_map(bus, dev, PCIR_BAR(3), rl, force,
3418 prefetchmask & (1 << 3));
3419 } else {
3420 rid = PCIR_BAR(2);
3421 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
3422 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170,
3423 0x177, 8, 0);
3424 rid = PCIR_BAR(3);
3425 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
3426 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376,
3427 0x376, 1, 0);
3428 }
3429 pci_add_map(bus, dev, PCIR_BAR(4), rl, force,
3430 prefetchmask & (1 << 4));
3431 pci_add_map(bus, dev, PCIR_BAR(5), rl, force,
3432 prefetchmask & (1 << 5));
3433 }
3434
3435 static void
pci_assign_interrupt(device_t bus,device_t dev,int force_route)3436 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
3437 {
3438 struct pci_devinfo *dinfo = device_get_ivars(dev);
3439 pcicfgregs *cfg = &dinfo->cfg;
3440 char tunable_name[64];
3441 int irq;
3442
3443 /* Has to have an intpin to have an interrupt. */
3444 if (cfg->intpin == 0)
3445 return;
3446
3447 /* Let the user override the IRQ with a tunable. */
3448 irq = PCI_INVALID_IRQ;
3449 snprintf(tunable_name, sizeof(tunable_name),
3450 "hw.pci%d.%d.%d.INT%c.irq",
3451 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
3452 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
3453 irq = PCI_INVALID_IRQ;
3454
3455 /*
3456 * If we didn't get an IRQ via the tunable, then we either use the
3457 * IRQ value in the intline register or we ask the bus to route an
3458 * interrupt for us. If force_route is true, then we only use the
3459 * value in the intline register if the bus was unable to assign an
3460 * IRQ.
3461 */
3462 if (!PCI_INTERRUPT_VALID(irq)) {
3463 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
3464 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
3465 if (!PCI_INTERRUPT_VALID(irq))
3466 irq = cfg->intline;
3467 }
3468
3469 /* If after all that we don't have an IRQ, just bail. */
3470 if (!PCI_INTERRUPT_VALID(irq))
3471 return;
3472
3473 /* Update the config register if it changed. */
3474 if (irq != cfg->intline) {
3475 cfg->intline = irq;
3476 pci_write_config(dev, PCIR_INTLINE, irq, 1);
3477 }
3478
3479 /* Add this IRQ as rid 0 interrupt resource. */
3480 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
3481 }
3482
3483 /* Perform early OHCI takeover from SMM. */
3484 static void
ohci_early_takeover(device_t self)3485 ohci_early_takeover(device_t self)
3486 {
3487 struct resource *res;
3488 uint32_t ctl;
3489 int rid;
3490 int i;
3491
3492 rid = PCIR_BAR(0);
3493 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3494 if (res == NULL)
3495 return;
3496
3497 ctl = bus_read_4(res, OHCI_CONTROL);
3498 if (ctl & OHCI_IR) {
3499 if (bootverbose)
3500 printf("ohci early: "
3501 "SMM active, request owner change\n");
3502 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR);
3503 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) {
3504 DELAY(1000);
3505 ctl = bus_read_4(res, OHCI_CONTROL);
3506 }
3507 if (ctl & OHCI_IR) {
3508 if (bootverbose)
3509 printf("ohci early: "
3510 "SMM does not respond, resetting\n");
3511 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET);
3512 }
3513 /* Disable interrupts */
3514 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
3515 }
3516
3517 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3518 }
3519
3520 /* Perform early UHCI takeover from SMM. */
3521 static void
uhci_early_takeover(device_t self)3522 uhci_early_takeover(device_t self)
3523 {
3524 struct resource *res;
3525 int rid;
3526
3527 /*
3528 * Set the PIRQD enable bit and switch off all the others. We don't
3529 * want legacy support to interfere with us XXX Does this also mean
3530 * that the BIOS won't touch the keyboard anymore if it is connected
3531 * to the ports of the root hub?
3532 */
3533 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2);
3534
3535 /* Disable interrupts */
3536 rid = PCI_UHCI_BASE_REG;
3537 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE);
3538 if (res != NULL) {
3539 bus_write_2(res, UHCI_INTR, 0);
3540 bus_release_resource(self, SYS_RES_IOPORT, rid, res);
3541 }
3542 }
3543
3544 /* Perform early EHCI takeover from SMM. */
3545 static void
ehci_early_takeover(device_t self)3546 ehci_early_takeover(device_t self)
3547 {
3548 struct resource *res;
3549 uint32_t cparams;
3550 uint32_t eec;
3551 uint8_t eecp;
3552 uint8_t bios_sem;
3553 uint8_t offs;
3554 int rid;
3555 int i;
3556
3557 rid = PCIR_BAR(0);
3558 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3559 if (res == NULL)
3560 return;
3561
3562 cparams = bus_read_4(res, EHCI_HCCPARAMS);
3563
3564 /* Synchronise with the BIOS if it owns the controller. */
3565 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0;
3566 eecp = EHCI_EECP_NEXT(eec)) {
3567 eec = pci_read_config(self, eecp, 4);
3568 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) {
3569 continue;
3570 }
3571 bios_sem = pci_read_config(self, eecp +
3572 EHCI_LEGSUP_BIOS_SEM, 1);
3573 if (bios_sem == 0) {
3574 continue;
3575 }
3576 if (bootverbose)
3577 printf("ehci early: "
3578 "SMM active, request owner change\n");
3579
3580 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1);
3581
3582 for (i = 0; (i < 100) && (bios_sem != 0); i++) {
3583 DELAY(1000);
3584 bios_sem = pci_read_config(self, eecp +
3585 EHCI_LEGSUP_BIOS_SEM, 1);
3586 }
3587
3588 if (bios_sem != 0) {
3589 if (bootverbose)
3590 printf("ehci early: "
3591 "SMM does not respond\n");
3592 }
3593 /* Disable interrupts */
3594 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION));
3595 bus_write_4(res, offs + EHCI_USBINTR, 0);
3596 }
3597 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3598 }
3599
3600 /* Perform early XHCI takeover from SMM. */
3601 static void
xhci_early_takeover(device_t self)3602 xhci_early_takeover(device_t self)
3603 {
3604 struct resource *res;
3605 uint32_t cparams;
3606 uint32_t eec;
3607 uint8_t eecp;
3608 uint8_t bios_sem;
3609 uint8_t offs;
3610 int rid;
3611 int i;
3612
3613 rid = PCIR_BAR(0);
3614 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3615 if (res == NULL)
3616 return;
3617
3618 cparams = bus_read_4(res, XHCI_HCSPARAMS0);
3619
3620 eec = -1;
3621
3622 /* Synchronise with the BIOS if it owns the controller. */
3623 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
3624 eecp += XHCI_XECP_NEXT(eec) << 2) {
3625 eec = bus_read_4(res, eecp);
3626
3627 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
3628 continue;
3629
3630 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM);
3631 if (bios_sem == 0)
3632 continue;
3633
3634 if (bootverbose)
3635 printf("xhci early: "
3636 "SMM active, request owner change\n");
3637
3638 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1);
3639
3640 /* wait a maximum of 5 second */
3641
3642 for (i = 0; (i < 5000) && (bios_sem != 0); i++) {
3643 DELAY(1000);
3644 bios_sem = bus_read_1(res, eecp +
3645 XHCI_XECP_BIOS_SEM);
3646 }
3647
3648 if (bios_sem != 0) {
3649 if (bootverbose)
3650 printf("xhci early: "
3651 "SMM does not respond\n");
3652 }
3653
3654 /* Disable interrupts */
3655 offs = bus_read_1(res, XHCI_CAPLENGTH);
3656 bus_write_4(res, offs + XHCI_USBCMD, 0);
3657 bus_read_4(res, offs + XHCI_USBSTS);
3658 }
3659 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3660 }
3661
3662 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
3663 static void
pci_reserve_secbus(device_t bus,device_t dev,pcicfgregs * cfg,struct resource_list * rl)3664 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg,
3665 struct resource_list *rl)
3666 {
3667 struct resource *res;
3668 char *cp;
3669 rman_res_t start, end, count;
3670 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus;
3671
3672 switch (cfg->hdrtype & PCIM_HDRTYPE) {
3673 case PCIM_HDRTYPE_BRIDGE:
3674 sec_reg = PCIR_SECBUS_1;
3675 sub_reg = PCIR_SUBBUS_1;
3676 break;
3677 case PCIM_HDRTYPE_CARDBUS:
3678 sec_reg = PCIR_SECBUS_2;
3679 sub_reg = PCIR_SUBBUS_2;
3680 break;
3681 default:
3682 return;
3683 }
3684
3685 /*
3686 * If the existing bus range is valid, attempt to reserve it
3687 * from our parent. If this fails for any reason, clear the
3688 * secbus and subbus registers.
3689 *
3690 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus?
3691 * This would at least preserve the existing sec_bus if it is
3692 * valid.
3693 */
3694 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1);
3695 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1);
3696
3697 /* Quirk handling. */
3698 switch (pci_get_devid(dev)) {
3699 case 0x12258086: /* Intel 82454KX/GX (Orion) */
3700 sup_bus = pci_read_config(dev, 0x41, 1);
3701 if (sup_bus != 0xff) {
3702 sec_bus = sup_bus + 1;
3703 sub_bus = sup_bus + 1;
3704 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1);
3705 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1);
3706 }
3707 break;
3708
3709 case 0x00dd10de:
3710 /* Compaq R3000 BIOS sets wrong subordinate bus number. */
3711 if ((cp = kern_getenv("smbios.planar.maker")) == NULL)
3712 break;
3713 if (strncmp(cp, "Compal", 6) != 0) {
3714 freeenv(cp);
3715 break;
3716 }
3717 freeenv(cp);
3718 if ((cp = kern_getenv("smbios.planar.product")) == NULL)
3719 break;
3720 if (strncmp(cp, "08A0", 4) != 0) {
3721 freeenv(cp);
3722 break;
3723 }
3724 freeenv(cp);
3725 if (sub_bus < 0xa) {
3726 sub_bus = 0xa;
3727 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1);
3728 }
3729 break;
3730 }
3731
3732 if (bootverbose)
3733 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus);
3734 if (sec_bus > 0 && sub_bus >= sec_bus) {
3735 start = sec_bus;
3736 end = sub_bus;
3737 count = end - start + 1;
3738
3739 resource_list_add(rl, PCI_RES_BUS, 0, 0, ~0, count);
3740
3741 /*
3742 * If requested, clear secondary bus registers in
3743 * bridge devices to force a complete renumbering
3744 * rather than reserving the existing range. However,
3745 * preserve the existing size.
3746 */
3747 if (pci_clear_buses)
3748 goto clear;
3749
3750 rid = 0;
3751 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid,
3752 start, end, count, 0);
3753 if (res != NULL)
3754 return;
3755
3756 if (bootverbose)
3757 device_printf(bus,
3758 "pci%d:%d:%d:%d secbus failed to allocate\n",
3759 pci_get_domain(dev), pci_get_bus(dev),
3760 pci_get_slot(dev), pci_get_function(dev));
3761 }
3762
3763 clear:
3764 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1);
3765 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1);
3766 }
3767
3768 static struct resource *
pci_alloc_secbus(device_t dev,device_t child,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)3769 pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start,
3770 rman_res_t end, rman_res_t count, u_int flags)
3771 {
3772 struct pci_devinfo *dinfo;
3773 pcicfgregs *cfg;
3774 struct resource_list *rl;
3775 struct resource *res;
3776 int sec_reg, sub_reg;
3777
3778 dinfo = device_get_ivars(child);
3779 cfg = &dinfo->cfg;
3780 rl = &dinfo->resources;
3781 switch (cfg->hdrtype & PCIM_HDRTYPE) {
3782 case PCIM_HDRTYPE_BRIDGE:
3783 sec_reg = PCIR_SECBUS_1;
3784 sub_reg = PCIR_SUBBUS_1;
3785 break;
3786 case PCIM_HDRTYPE_CARDBUS:
3787 sec_reg = PCIR_SECBUS_2;
3788 sub_reg = PCIR_SUBBUS_2;
3789 break;
3790 default:
3791 return (NULL);
3792 }
3793
3794 if (*rid != 0)
3795 return (NULL);
3796
3797 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL)
3798 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count);
3799 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) {
3800 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid,
3801 start, end, count, flags & ~RF_ACTIVE);
3802 if (res == NULL) {
3803 resource_list_delete(rl, PCI_RES_BUS, *rid);
3804 device_printf(child, "allocating %ju bus%s failed\n",
3805 count, count == 1 ? "" : "es");
3806 return (NULL);
3807 }
3808 if (bootverbose)
3809 device_printf(child,
3810 "Lazy allocation of %ju bus%s at %ju\n", count,
3811 count == 1 ? "" : "es", rman_get_start(res));
3812 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1);
3813 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1);
3814 }
3815 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start,
3816 end, count, flags));
3817 }
3818 #endif
3819
3820 static int
pci_ea_bei_to_rid(device_t dev,int bei)3821 pci_ea_bei_to_rid(device_t dev, int bei)
3822 {
3823 #ifdef PCI_IOV
3824 struct pci_devinfo *dinfo;
3825 int iov_pos;
3826 struct pcicfg_iov *iov;
3827
3828 dinfo = device_get_ivars(dev);
3829 iov = dinfo->cfg.iov;
3830 if (iov != NULL)
3831 iov_pos = iov->iov_pos;
3832 else
3833 iov_pos = 0;
3834 #endif
3835
3836 /* Check if matches BAR */
3837 if ((bei >= PCIM_EA_BEI_BAR_0) &&
3838 (bei <= PCIM_EA_BEI_BAR_5))
3839 return (PCIR_BAR(bei));
3840
3841 /* Check ROM */
3842 if (bei == PCIM_EA_BEI_ROM)
3843 return (PCIR_BIOS);
3844
3845 #ifdef PCI_IOV
3846 /* Check if matches VF_BAR */
3847 if ((iov != NULL) && (bei >= PCIM_EA_BEI_VF_BAR_0) &&
3848 (bei <= PCIM_EA_BEI_VF_BAR_5))
3849 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) +
3850 iov_pos);
3851 #endif
3852
3853 return (-1);
3854 }
3855
3856 int
pci_ea_is_enabled(device_t dev,int rid)3857 pci_ea_is_enabled(device_t dev, int rid)
3858 {
3859 struct pci_ea_entry *ea;
3860 struct pci_devinfo *dinfo;
3861
3862 dinfo = device_get_ivars(dev);
3863
3864 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) {
3865 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid)
3866 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0);
3867 }
3868
3869 return (0);
3870 }
3871
3872 void
pci_add_resources_ea(device_t bus,device_t dev,int alloc_iov)3873 pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov)
3874 {
3875 struct pci_ea_entry *ea;
3876 struct pci_devinfo *dinfo;
3877 pci_addr_t start, end, count;
3878 struct resource_list *rl;
3879 int type, flags, rid;
3880 struct resource *res;
3881 uint32_t tmp;
3882 #ifdef PCI_IOV
3883 struct pcicfg_iov *iov;
3884 #endif
3885
3886 dinfo = device_get_ivars(dev);
3887 rl = &dinfo->resources;
3888 flags = 0;
3889
3890 #ifdef PCI_IOV
3891 iov = dinfo->cfg.iov;
3892 #endif
3893
3894 if (dinfo->cfg.ea.ea_location == 0)
3895 return;
3896
3897 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) {
3898
3899 /*
3900 * TODO: Ignore EA-BAR if is not enabled.
3901 * Currently the EA implementation supports
3902 * only situation, where EA structure contains
3903 * predefined entries. In case they are not enabled
3904 * leave them unallocated and proceed with
3905 * a legacy-BAR mechanism.
3906 */
3907 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0)
3908 continue;
3909
3910 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) {
3911 case PCIM_EA_P_MEM_PREFETCH:
3912 case PCIM_EA_P_VF_MEM_PREFETCH:
3913 flags = RF_PREFETCHABLE;
3914 /* FALLTHROUGH */
3915 case PCIM_EA_P_VF_MEM:
3916 case PCIM_EA_P_MEM:
3917 type = SYS_RES_MEMORY;
3918 break;
3919 case PCIM_EA_P_IO:
3920 type = SYS_RES_IOPORT;
3921 break;
3922 default:
3923 continue;
3924 }
3925
3926 if (alloc_iov != 0) {
3927 #ifdef PCI_IOV
3928 /* Allocating IOV, confirm BEI matches */
3929 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) ||
3930 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5))
3931 continue;
3932 #else
3933 continue;
3934 #endif
3935 } else {
3936 /* Allocating BAR, confirm BEI matches */
3937 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) ||
3938 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) &&
3939 (ea->eae_bei != PCIM_EA_BEI_ROM))
3940 continue;
3941 }
3942
3943 rid = pci_ea_bei_to_rid(dev, ea->eae_bei);
3944 if (rid < 0)
3945 continue;
3946
3947 /* Skip resources already allocated by EA */
3948 if ((resource_list_find(rl, SYS_RES_MEMORY, rid) != NULL) ||
3949 (resource_list_find(rl, SYS_RES_IOPORT, rid) != NULL))
3950 continue;
3951
3952 start = ea->eae_base;
3953 count = ea->eae_max_offset + 1;
3954 #ifdef PCI_IOV
3955 if (iov != NULL)
3956 count = count * iov->iov_num_vfs;
3957 #endif
3958 end = start + count - 1;
3959 if (count == 0)
3960 continue;
3961
3962 resource_list_add(rl, type, rid, start, end, count);
3963 res = resource_list_reserve(rl, bus, dev, type, &rid, start, end, count,
3964 flags);
3965 if (res == NULL) {
3966 resource_list_delete(rl, type, rid);
3967
3968 /*
3969 * Failed to allocate using EA, disable entry.
3970 * Another attempt to allocation will be performed
3971 * further, but this time using legacy BAR registers
3972 */
3973 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4);
3974 tmp &= ~PCIM_EA_ENABLE;
3975 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4);
3976
3977 /*
3978 * Disabling entry might fail in case it is hardwired.
3979 * Read flags again to match current status.
3980 */
3981 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4);
3982
3983 continue;
3984 }
3985
3986 /* As per specification, fill BAR with zeros */
3987 pci_write_config(dev, rid, 0, 4);
3988 }
3989 }
3990
3991 void
pci_add_resources(device_t bus,device_t dev,int force,uint32_t prefetchmask)3992 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
3993 {
3994 struct pci_devinfo *dinfo;
3995 pcicfgregs *cfg;
3996 struct resource_list *rl;
3997 const struct pci_quirk *q;
3998 uint32_t devid;
3999 int i;
4000
4001 dinfo = device_get_ivars(dev);
4002 cfg = &dinfo->cfg;
4003 rl = &dinfo->resources;
4004 devid = (cfg->device << 16) | cfg->vendor;
4005
4006 /* Allocate resources using Enhanced Allocation */
4007 pci_add_resources_ea(bus, dev, 0);
4008
4009 /* ATA devices needs special map treatment */
4010 if ((pci_get_class(dev) == PCIC_STORAGE) &&
4011 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
4012 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
4013 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
4014 !pci_read_config(dev, PCIR_BAR(2), 4))) )
4015 pci_ata_maps(bus, dev, rl, force, prefetchmask);
4016 else
4017 for (i = 0; i < cfg->nummaps;) {
4018 /* Skip resources already managed by EA */
4019 if ((resource_list_find(rl, SYS_RES_MEMORY, PCIR_BAR(i)) != NULL) ||
4020 (resource_list_find(rl, SYS_RES_IOPORT, PCIR_BAR(i)) != NULL) ||
4021 pci_ea_is_enabled(dev, PCIR_BAR(i))) {
4022 i++;
4023 continue;
4024 }
4025
4026 /*
4027 * Skip quirked resources.
4028 */
4029 for (q = &pci_quirks[0]; q->devid != 0; q++)
4030 if (q->devid == devid &&
4031 q->type == PCI_QUIRK_UNMAP_REG &&
4032 q->arg1 == PCIR_BAR(i))
4033 break;
4034 if (q->devid != 0) {
4035 i++;
4036 continue;
4037 }
4038 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force,
4039 prefetchmask & (1 << i));
4040 }
4041
4042 /*
4043 * Add additional, quirked resources.
4044 */
4045 for (q = &pci_quirks[0]; q->devid != 0; q++)
4046 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG)
4047 pci_add_map(bus, dev, q->arg1, rl, force, 0);
4048
4049 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
4050 #ifdef __PCI_REROUTE_INTERRUPT
4051 /*
4052 * Try to re-route interrupts. Sometimes the BIOS or
4053 * firmware may leave bogus values in these registers.
4054 * If the re-route fails, then just stick with what we
4055 * have.
4056 */
4057 pci_assign_interrupt(bus, dev, 1);
4058 #else
4059 pci_assign_interrupt(bus, dev, 0);
4060 #endif
4061 }
4062
4063 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS &&
4064 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) {
4065 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI)
4066 xhci_early_takeover(dev);
4067 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI)
4068 ehci_early_takeover(dev);
4069 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI)
4070 ohci_early_takeover(dev);
4071 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI)
4072 uhci_early_takeover(dev);
4073 }
4074
4075 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
4076 /*
4077 * Reserve resources for secondary bus ranges behind bridge
4078 * devices.
4079 */
4080 pci_reserve_secbus(bus, dev, cfg, rl);
4081 #endif
4082 }
4083
4084 static struct pci_devinfo *
pci_identify_function(device_t pcib,device_t dev,int domain,int busno,int slot,int func)4085 pci_identify_function(device_t pcib, device_t dev, int domain, int busno,
4086 int slot, int func)
4087 {
4088 struct pci_devinfo *dinfo;
4089
4090 dinfo = pci_read_device(pcib, dev, domain, busno, slot, func);
4091 if (dinfo != NULL)
4092 pci_add_child(dev, dinfo);
4093
4094 return (dinfo);
4095 }
4096
4097 void
pci_add_children(device_t dev,int domain,int busno)4098 pci_add_children(device_t dev, int domain, int busno)
4099 {
4100 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
4101 device_t pcib = device_get_parent(dev);
4102 struct pci_devinfo *dinfo;
4103 int maxslots;
4104 int s, f, pcifunchigh;
4105 uint8_t hdrtype;
4106 int first_func;
4107
4108 /*
4109 * Try to detect a device at slot 0, function 0. If it exists, try to
4110 * enable ARI. We must enable ARI before detecting the rest of the
4111 * functions on this bus as ARI changes the set of slots and functions
4112 * that are legal on this bus.
4113 */
4114 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0);
4115 if (dinfo != NULL && pci_enable_ari)
4116 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev);
4117
4118 /*
4119 * Start looking for new devices on slot 0 at function 1 because we
4120 * just identified the device at slot 0, function 0.
4121 */
4122 first_func = 1;
4123
4124 maxslots = PCIB_MAXSLOTS(pcib);
4125 for (s = 0; s <= maxslots; s++, first_func = 0) {
4126 pcifunchigh = 0;
4127 f = 0;
4128 DELAY(1);
4129 hdrtype = REG(PCIR_HDRTYPE, 1);
4130 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
4131 continue;
4132 if (hdrtype & PCIM_MFDEV)
4133 pcifunchigh = PCIB_MAXFUNCS(pcib);
4134 for (f = first_func; f <= pcifunchigh; f++)
4135 pci_identify_function(pcib, dev, domain, busno, s, f);
4136 }
4137 #undef REG
4138 }
4139
4140 int
pci_rescan_method(device_t dev)4141 pci_rescan_method(device_t dev)
4142 {
4143 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
4144 device_t pcib = device_get_parent(dev);
4145 device_t child, *devlist, *unchanged;
4146 int devcount, error, i, j, maxslots, oldcount;
4147 int busno, domain, s, f, pcifunchigh;
4148 uint8_t hdrtype;
4149
4150 /* No need to check for ARI on a rescan. */
4151 error = device_get_children(dev, &devlist, &devcount);
4152 if (error)
4153 return (error);
4154 if (devcount != 0) {
4155 unchanged = malloc(devcount * sizeof(device_t), M_TEMP,
4156 M_NOWAIT | M_ZERO);
4157 if (unchanged == NULL) {
4158 free(devlist, M_TEMP);
4159 return (ENOMEM);
4160 }
4161 } else
4162 unchanged = NULL;
4163
4164 domain = pcib_get_domain(dev);
4165 busno = pcib_get_bus(dev);
4166 maxslots = PCIB_MAXSLOTS(pcib);
4167 for (s = 0; s <= maxslots; s++) {
4168 /* If function 0 is not present, skip to the next slot. */
4169 f = 0;
4170 if (REG(PCIR_VENDOR, 2) == 0xffff)
4171 continue;
4172 pcifunchigh = 0;
4173 hdrtype = REG(PCIR_HDRTYPE, 1);
4174 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
4175 continue;
4176 if (hdrtype & PCIM_MFDEV)
4177 pcifunchigh = PCIB_MAXFUNCS(pcib);
4178 for (f = 0; f <= pcifunchigh; f++) {
4179 if (REG(PCIR_VENDOR, 2) == 0xffff)
4180 continue;
4181
4182 /*
4183 * Found a valid function. Check if a
4184 * device_t for this device already exists.
4185 */
4186 for (i = 0; i < devcount; i++) {
4187 child = devlist[i];
4188 if (child == NULL)
4189 continue;
4190 if (pci_get_slot(child) == s &&
4191 pci_get_function(child) == f) {
4192 unchanged[i] = child;
4193 goto next_func;
4194 }
4195 }
4196
4197 pci_identify_function(pcib, dev, domain, busno, s, f);
4198 next_func:;
4199 }
4200 }
4201
4202 /* Remove devices that are no longer present. */
4203 for (i = 0; i < devcount; i++) {
4204 if (unchanged[i] != NULL)
4205 continue;
4206 device_delete_child(dev, devlist[i]);
4207 }
4208
4209 free(devlist, M_TEMP);
4210 oldcount = devcount;
4211
4212 /* Try to attach the devices just added. */
4213 error = device_get_children(dev, &devlist, &devcount);
4214 if (error) {
4215 free(unchanged, M_TEMP);
4216 return (error);
4217 }
4218
4219 for (i = 0; i < devcount; i++) {
4220 for (j = 0; j < oldcount; j++) {
4221 if (devlist[i] == unchanged[j])
4222 goto next_device;
4223 }
4224
4225 device_probe_and_attach(devlist[i]);
4226 next_device:;
4227 }
4228
4229 free(unchanged, M_TEMP);
4230 free(devlist, M_TEMP);
4231 return (0);
4232 #undef REG
4233 }
4234
4235 #ifdef PCI_IOV
4236 device_t
pci_add_iov_child(device_t bus,device_t pf,uint16_t rid,uint16_t vid,uint16_t did)4237 pci_add_iov_child(device_t bus, device_t pf, uint16_t rid, uint16_t vid,
4238 uint16_t did)
4239 {
4240 struct pci_devinfo *vf_dinfo;
4241 device_t pcib;
4242 int busno, slot, func;
4243
4244 pcib = device_get_parent(bus);
4245
4246 PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func);
4247
4248 vf_dinfo = pci_fill_devinfo(pcib, bus, pci_get_domain(pcib), busno,
4249 slot, func, vid, did);
4250
4251 vf_dinfo->cfg.flags |= PCICFG_VF;
4252 pci_add_child(bus, vf_dinfo);
4253
4254 return (vf_dinfo->cfg.dev);
4255 }
4256
4257 device_t
pci_create_iov_child_method(device_t bus,device_t pf,uint16_t rid,uint16_t vid,uint16_t did)4258 pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid,
4259 uint16_t vid, uint16_t did)
4260 {
4261
4262 return (pci_add_iov_child(bus, pf, rid, vid, did));
4263 }
4264 #endif
4265
4266 /*
4267 * For PCIe device set Max_Payload_Size to match PCIe root's.
4268 */
4269 static void
pcie_setup_mps(device_t dev)4270 pcie_setup_mps(device_t dev)
4271 {
4272 struct pci_devinfo *dinfo = device_get_ivars(dev);
4273 device_t root;
4274 uint16_t rmps, mmps, mps;
4275
4276 if (dinfo->cfg.pcie.pcie_location == 0)
4277 return;
4278 root = pci_find_pcie_root_port(dev);
4279 if (root == NULL)
4280 return;
4281 /* Check whether the MPS is already configured. */
4282 rmps = pcie_read_config(root, PCIER_DEVICE_CTL, 2) &
4283 PCIEM_CTL_MAX_PAYLOAD;
4284 mps = pcie_read_config(dev, PCIER_DEVICE_CTL, 2) &
4285 PCIEM_CTL_MAX_PAYLOAD;
4286 if (mps == rmps)
4287 return;
4288 /* Check whether the device is capable of the root's MPS. */
4289 mmps = (pcie_read_config(dev, PCIER_DEVICE_CAP, 2) &
4290 PCIEM_CAP_MAX_PAYLOAD) << 5;
4291 if (rmps > mmps) {
4292 /*
4293 * The device is unable to handle root's MPS. Limit root.
4294 * XXX: We should traverse through all the tree, applying
4295 * it to all the devices.
4296 */
4297 pcie_adjust_config(root, PCIER_DEVICE_CTL,
4298 PCIEM_CTL_MAX_PAYLOAD, mmps, 2);
4299 } else {
4300 pcie_adjust_config(dev, PCIER_DEVICE_CTL,
4301 PCIEM_CTL_MAX_PAYLOAD, rmps, 2);
4302 }
4303 }
4304
4305 static void
pci_add_child_clear_aer(device_t dev,struct pci_devinfo * dinfo)4306 pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo)
4307 {
4308 int aer;
4309 uint32_t r;
4310 uint16_t r2;
4311
4312 if (dinfo->cfg.pcie.pcie_location != 0 &&
4313 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) {
4314 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
4315 PCIER_ROOT_CTL, 2);
4316 r2 &= ~(PCIEM_ROOT_CTL_SERR_CORR |
4317 PCIEM_ROOT_CTL_SERR_NONFATAL | PCIEM_ROOT_CTL_SERR_FATAL);
4318 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
4319 PCIER_ROOT_CTL, r2, 2);
4320 }
4321 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) {
4322 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4);
4323 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4);
4324 if (r != 0 && bootverbose) {
4325 pci_printf(&dinfo->cfg,
4326 "clearing AER UC 0x%08x -> 0x%08x\n",
4327 r, pci_read_config(dev, aer + PCIR_AER_UC_STATUS,
4328 4));
4329 }
4330
4331 r = pci_read_config(dev, aer + PCIR_AER_UC_MASK, 4);
4332 r &= ~(PCIM_AER_UC_TRAINING_ERROR |
4333 PCIM_AER_UC_DL_PROTOCOL_ERROR |
4334 PCIM_AER_UC_SURPRISE_LINK_DOWN |
4335 PCIM_AER_UC_POISONED_TLP |
4336 PCIM_AER_UC_FC_PROTOCOL_ERROR |
4337 PCIM_AER_UC_COMPLETION_TIMEOUT |
4338 PCIM_AER_UC_COMPLETER_ABORT |
4339 PCIM_AER_UC_UNEXPECTED_COMPLETION |
4340 PCIM_AER_UC_RECEIVER_OVERFLOW |
4341 PCIM_AER_UC_MALFORMED_TLP |
4342 PCIM_AER_UC_ECRC_ERROR |
4343 PCIM_AER_UC_UNSUPPORTED_REQUEST |
4344 PCIM_AER_UC_ACS_VIOLATION |
4345 PCIM_AER_UC_INTERNAL_ERROR |
4346 PCIM_AER_UC_MC_BLOCKED_TLP |
4347 PCIM_AER_UC_ATOMIC_EGRESS_BLK |
4348 PCIM_AER_UC_TLP_PREFIX_BLOCKED);
4349 pci_write_config(dev, aer + PCIR_AER_UC_MASK, r, 4);
4350
4351 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4);
4352 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4);
4353 if (r != 0 && bootverbose) {
4354 pci_printf(&dinfo->cfg,
4355 "clearing AER COR 0x%08x -> 0x%08x\n",
4356 r, pci_read_config(dev, aer + PCIR_AER_COR_STATUS,
4357 4));
4358 }
4359
4360 r = pci_read_config(dev, aer + PCIR_AER_COR_MASK, 4);
4361 r &= ~(PCIM_AER_COR_RECEIVER_ERROR |
4362 PCIM_AER_COR_BAD_TLP |
4363 PCIM_AER_COR_BAD_DLLP |
4364 PCIM_AER_COR_REPLAY_ROLLOVER |
4365 PCIM_AER_COR_REPLAY_TIMEOUT |
4366 PCIM_AER_COR_ADVISORY_NF_ERROR |
4367 PCIM_AER_COR_INTERNAL_ERROR |
4368 PCIM_AER_COR_HEADER_LOG_OVFLOW);
4369 pci_write_config(dev, aer + PCIR_AER_COR_MASK, r, 4);
4370
4371 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
4372 PCIER_DEVICE_CTL, 2);
4373 r |= PCIEM_CTL_COR_ENABLE | PCIEM_CTL_NFER_ENABLE |
4374 PCIEM_CTL_FER_ENABLE | PCIEM_CTL_URR_ENABLE;
4375 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
4376 PCIER_DEVICE_CTL, r, 2);
4377 }
4378 }
4379
4380 void
pci_add_child(device_t bus,struct pci_devinfo * dinfo)4381 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
4382 {
4383 device_t dev;
4384
4385 dinfo->cfg.dev = dev = device_add_child(bus, NULL, -1);
4386 device_set_ivars(dev, dinfo);
4387 resource_list_init(&dinfo->resources);
4388 pci_cfg_save(dev, dinfo, 0);
4389 pci_cfg_restore(dev, dinfo);
4390 pci_print_verbose(dinfo);
4391 pci_add_resources(bus, dev, 0, 0);
4392 pcie_setup_mps(dev);
4393 pci_child_added(dinfo->cfg.dev);
4394
4395 if (pci_clear_aer_on_attach)
4396 pci_add_child_clear_aer(dev, dinfo);
4397
4398 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev);
4399 }
4400
4401 void
pci_child_added_method(device_t dev,device_t child)4402 pci_child_added_method(device_t dev, device_t child)
4403 {
4404
4405 }
4406
4407 static int
pci_probe(device_t dev)4408 pci_probe(device_t dev)
4409 {
4410
4411 device_set_desc(dev, "PCI bus");
4412
4413 /* Allow other subclasses to override this driver. */
4414 return (BUS_PROBE_GENERIC);
4415 }
4416
4417 int
pci_attach_common(device_t dev)4418 pci_attach_common(device_t dev)
4419 {
4420 struct pci_softc *sc;
4421 int busno, domain;
4422 #ifdef PCI_RES_BUS
4423 int rid;
4424 #endif
4425
4426 sc = device_get_softc(dev);
4427 domain = pcib_get_domain(dev);
4428 busno = pcib_get_bus(dev);
4429 #ifdef PCI_RES_BUS
4430 rid = 0;
4431 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno,
4432 1, 0);
4433 if (sc->sc_bus == NULL) {
4434 device_printf(dev, "failed to allocate bus number\n");
4435 return (ENXIO);
4436 }
4437 #endif
4438 if (bootverbose)
4439 device_printf(dev, "domain=%d, physical bus=%d\n",
4440 domain, busno);
4441 sc->sc_dma_tag = bus_get_dma_tag(dev);
4442 return (0);
4443 }
4444
4445 int
pci_attach(device_t dev)4446 pci_attach(device_t dev)
4447 {
4448 int busno, domain, error;
4449
4450 error = pci_attach_common(dev);
4451 if (error)
4452 return (error);
4453
4454 /*
4455 * Since there can be multiple independently numbered PCI
4456 * buses on systems with multiple PCI domains, we can't use
4457 * the unit number to decide which bus we are probing. We ask
4458 * the parent pcib what our domain and bus numbers are.
4459 */
4460 domain = pcib_get_domain(dev);
4461 busno = pcib_get_bus(dev);
4462 pci_add_children(dev, domain, busno);
4463 return (bus_generic_attach(dev));
4464 }
4465
4466 int
pci_detach(device_t dev)4467 pci_detach(device_t dev)
4468 {
4469 #ifdef PCI_RES_BUS
4470 struct pci_softc *sc;
4471 #endif
4472 int error;
4473
4474 error = bus_generic_detach(dev);
4475 if (error)
4476 return (error);
4477 #ifdef PCI_RES_BUS
4478 sc = device_get_softc(dev);
4479 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus);
4480 if (error)
4481 return (error);
4482 #endif
4483 return (device_delete_children(dev));
4484 }
4485
4486 static void
pci_hint_device_unit(device_t dev,device_t child,const char * name,int * unitp)4487 pci_hint_device_unit(device_t dev, device_t child, const char *name, int *unitp)
4488 {
4489 int line, unit;
4490 const char *at;
4491 char me1[24], me2[32];
4492 uint8_t b, s, f;
4493 uint32_t d;
4494
4495 d = pci_get_domain(child);
4496 b = pci_get_bus(child);
4497 s = pci_get_slot(child);
4498 f = pci_get_function(child);
4499 snprintf(me1, sizeof(me1), "pci%u:%u:%u", b, s, f);
4500 snprintf(me2, sizeof(me2), "pci%u:%u:%u:%u", d, b, s, f);
4501 line = 0;
4502 while (resource_find_dev(&line, name, &unit, "at", NULL) == 0) {
4503 resource_string_value(name, unit, "at", &at);
4504 if (strcmp(at, me1) != 0 && strcmp(at, me2) != 0)
4505 continue; /* No match, try next candidate */
4506 *unitp = unit;
4507 return;
4508 }
4509 }
4510
4511 static void
pci_set_power_child(device_t dev,device_t child,int state)4512 pci_set_power_child(device_t dev, device_t child, int state)
4513 {
4514 device_t pcib;
4515 int dstate;
4516
4517 /*
4518 * Set the device to the given state. If the firmware suggests
4519 * a different power state, use it instead. If power management
4520 * is not present, the firmware is responsible for managing
4521 * device power. Skip children who aren't attached since they
4522 * are handled separately.
4523 */
4524 pcib = device_get_parent(dev);
4525 dstate = state;
4526 if (device_is_attached(child) &&
4527 PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0)
4528 pci_set_powerstate(child, dstate);
4529 }
4530
4531 int
pci_suspend_child(device_t dev,device_t child)4532 pci_suspend_child(device_t dev, device_t child)
4533 {
4534 struct pci_devinfo *dinfo;
4535 struct resource_list_entry *rle;
4536 int error;
4537
4538 dinfo = device_get_ivars(child);
4539
4540 /*
4541 * Save the PCI configuration space for the child and set the
4542 * device in the appropriate power state for this sleep state.
4543 */
4544 pci_cfg_save(child, dinfo, 0);
4545
4546 /* Suspend devices before potentially powering them down. */
4547 error = bus_generic_suspend_child(dev, child);
4548
4549 if (error)
4550 return (error);
4551
4552 if (pci_do_power_suspend) {
4553 /*
4554 * Make sure this device's interrupt handler is not invoked
4555 * in the case the device uses a shared interrupt that can
4556 * be raised by some other device.
4557 * This is applicable only to regular (legacy) PCI interrupts
4558 * as MSI/MSI-X interrupts are never shared.
4559 */
4560 rle = resource_list_find(&dinfo->resources,
4561 SYS_RES_IRQ, 0);
4562 if (rle != NULL && rle->res != NULL)
4563 (void)bus_suspend_intr(child, rle->res);
4564 pci_set_power_child(dev, child, PCI_POWERSTATE_D3);
4565 }
4566
4567 return (0);
4568 }
4569
4570 int
pci_resume_child(device_t dev,device_t child)4571 pci_resume_child(device_t dev, device_t child)
4572 {
4573 struct pci_devinfo *dinfo;
4574 struct resource_list_entry *rle;
4575
4576 if (pci_do_power_resume)
4577 pci_set_power_child(dev, child, PCI_POWERSTATE_D0);
4578
4579 dinfo = device_get_ivars(child);
4580 pci_cfg_restore(child, dinfo);
4581 if (!device_is_attached(child))
4582 pci_cfg_save(child, dinfo, 1);
4583
4584 bus_generic_resume_child(dev, child);
4585
4586 /*
4587 * Allow interrupts only after fully resuming the driver and hardware.
4588 */
4589 if (pci_do_power_suspend) {
4590 /* See pci_suspend_child for details. */
4591 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
4592 if (rle != NULL && rle->res != NULL)
4593 (void)bus_resume_intr(child, rle->res);
4594 }
4595
4596 return (0);
4597 }
4598
4599 int
pci_resume(device_t dev)4600 pci_resume(device_t dev)
4601 {
4602 device_t child, *devlist;
4603 int error, i, numdevs;
4604
4605 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
4606 return (error);
4607
4608 /*
4609 * Resume critical devices first, then everything else later.
4610 */
4611 for (i = 0; i < numdevs; i++) {
4612 child = devlist[i];
4613 switch (pci_get_class(child)) {
4614 case PCIC_DISPLAY:
4615 case PCIC_MEMORY:
4616 case PCIC_BRIDGE:
4617 case PCIC_BASEPERIPH:
4618 BUS_RESUME_CHILD(dev, child);
4619 break;
4620 }
4621 }
4622 for (i = 0; i < numdevs; i++) {
4623 child = devlist[i];
4624 switch (pci_get_class(child)) {
4625 case PCIC_DISPLAY:
4626 case PCIC_MEMORY:
4627 case PCIC_BRIDGE:
4628 case PCIC_BASEPERIPH:
4629 break;
4630 default:
4631 BUS_RESUME_CHILD(dev, child);
4632 }
4633 }
4634 free(devlist, M_TEMP);
4635 return (0);
4636 }
4637
4638 static void
pci_load_vendor_data(void)4639 pci_load_vendor_data(void)
4640 {
4641 caddr_t data;
4642 void *ptr;
4643 size_t sz;
4644
4645 data = preload_search_by_type("pci_vendor_data");
4646 if (data != NULL) {
4647 ptr = preload_fetch_addr(data);
4648 sz = preload_fetch_size(data);
4649 if (ptr != NULL && sz != 0) {
4650 pci_vendordata = ptr;
4651 pci_vendordata_size = sz;
4652 /* terminate the database */
4653 pci_vendordata[pci_vendordata_size] = '\n';
4654 }
4655 }
4656 }
4657
4658 void
pci_driver_added(device_t dev,driver_t * driver)4659 pci_driver_added(device_t dev, driver_t *driver)
4660 {
4661 int numdevs;
4662 device_t *devlist;
4663 device_t child;
4664 struct pci_devinfo *dinfo;
4665 int i;
4666
4667 if (bootverbose)
4668 device_printf(dev, "driver added\n");
4669 DEVICE_IDENTIFY(driver, dev);
4670 if (device_get_children(dev, &devlist, &numdevs) != 0)
4671 return;
4672 for (i = 0; i < numdevs; i++) {
4673 child = devlist[i];
4674 if (device_get_state(child) != DS_NOTPRESENT)
4675 continue;
4676 dinfo = device_get_ivars(child);
4677 pci_print_verbose(dinfo);
4678 if (bootverbose)
4679 pci_printf(&dinfo->cfg, "reprobing on driver added\n");
4680 pci_cfg_restore(child, dinfo);
4681 if (device_probe_and_attach(child) != 0)
4682 pci_child_detached(dev, child);
4683 }
4684 free(devlist, M_TEMP);
4685 }
4686
4687 int
pci_setup_intr(device_t dev,device_t child,struct resource * irq,int flags,driver_filter_t * filter,driver_intr_t * intr,void * arg,void ** cookiep)4688 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
4689 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep)
4690 {
4691 struct pci_devinfo *dinfo;
4692 struct msix_table_entry *mte;
4693 struct msix_vector *mv;
4694 uint64_t addr;
4695 uint32_t data;
4696 void *cookie;
4697 int error, rid;
4698
4699 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr,
4700 arg, &cookie);
4701 if (error)
4702 return (error);
4703
4704 /* If this is not a direct child, just bail out. */
4705 if (device_get_parent(child) != dev) {
4706 *cookiep = cookie;
4707 return(0);
4708 }
4709
4710 rid = rman_get_rid(irq);
4711 if (rid == 0) {
4712 /* Make sure that INTx is enabled */
4713 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
4714 } else {
4715 /*
4716 * Check to see if the interrupt is MSI or MSI-X.
4717 * Ask our parent to map the MSI and give
4718 * us the address and data register values.
4719 * If we fail for some reason, teardown the
4720 * interrupt handler.
4721 */
4722 dinfo = device_get_ivars(child);
4723 if (dinfo->cfg.msi.msi_alloc > 0) {
4724 if (dinfo->cfg.msi.msi_addr == 0) {
4725 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
4726 ("MSI has handlers, but vectors not mapped"));
4727 error = PCIB_MAP_MSI(device_get_parent(dev),
4728 child, rman_get_start(irq), &addr, &data);
4729 if (error)
4730 goto bad;
4731 dinfo->cfg.msi.msi_addr = addr;
4732 dinfo->cfg.msi.msi_data = data;
4733 }
4734 if (dinfo->cfg.msi.msi_handlers == 0)
4735 pci_enable_msi(child, dinfo->cfg.msi.msi_addr,
4736 dinfo->cfg.msi.msi_data);
4737 dinfo->cfg.msi.msi_handlers++;
4738 } else {
4739 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
4740 ("No MSI or MSI-X interrupts allocated"));
4741 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
4742 ("MSI-X index too high"));
4743 mte = &dinfo->cfg.msix.msix_table[rid - 1];
4744 KASSERT(mte->mte_vector != 0, ("no message vector"));
4745 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
4746 KASSERT(mv->mv_irq == rman_get_start(irq),
4747 ("IRQ mismatch"));
4748 if (mv->mv_address == 0) {
4749 KASSERT(mte->mte_handlers == 0,
4750 ("MSI-X table entry has handlers, but vector not mapped"));
4751 error = PCIB_MAP_MSI(device_get_parent(dev),
4752 child, rman_get_start(irq), &addr, &data);
4753 if (error)
4754 goto bad;
4755 mv->mv_address = addr;
4756 mv->mv_data = data;
4757 }
4758
4759 /*
4760 * The MSIX table entry must be made valid by
4761 * incrementing the mte_handlers before
4762 * calling pci_enable_msix() and
4763 * pci_resume_msix(). Else the MSIX rewrite
4764 * table quirk will not work as expected.
4765 */
4766 mte->mte_handlers++;
4767 if (mte->mte_handlers == 1) {
4768 pci_enable_msix(child, rid - 1, mv->mv_address,
4769 mv->mv_data);
4770 pci_unmask_msix(child, rid - 1);
4771 }
4772 }
4773
4774 /*
4775 * Make sure that INTx is disabled if we are using MSI/MSI-X,
4776 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG,
4777 * in which case we "enable" INTx so MSI/MSI-X actually works.
4778 */
4779 if (!pci_has_quirk(pci_get_devid(child),
4780 PCI_QUIRK_MSI_INTX_BUG))
4781 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
4782 else
4783 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
4784 bad:
4785 if (error) {
4786 (void)bus_generic_teardown_intr(dev, child, irq,
4787 cookie);
4788 return (error);
4789 }
4790 }
4791 *cookiep = cookie;
4792 return (0);
4793 }
4794
4795 int
pci_teardown_intr(device_t dev,device_t child,struct resource * irq,void * cookie)4796 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
4797 void *cookie)
4798 {
4799 struct msix_table_entry *mte;
4800 struct resource_list_entry *rle;
4801 struct pci_devinfo *dinfo;
4802 int error, rid;
4803
4804 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
4805 return (EINVAL);
4806
4807 /* If this isn't a direct child, just bail out */
4808 if (device_get_parent(child) != dev)
4809 return(bus_generic_teardown_intr(dev, child, irq, cookie));
4810
4811 rid = rman_get_rid(irq);
4812 if (rid == 0) {
4813 /* Mask INTx */
4814 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
4815 } else {
4816 /*
4817 * Check to see if the interrupt is MSI or MSI-X. If so,
4818 * decrement the appropriate handlers count and mask the
4819 * MSI-X message, or disable MSI messages if the count
4820 * drops to 0.
4821 */
4822 dinfo = device_get_ivars(child);
4823 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
4824 if (rle->res != irq)
4825 return (EINVAL);
4826 if (dinfo->cfg.msi.msi_alloc > 0) {
4827 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
4828 ("MSI-X index too high"));
4829 if (dinfo->cfg.msi.msi_handlers == 0)
4830 return (EINVAL);
4831 dinfo->cfg.msi.msi_handlers--;
4832 if (dinfo->cfg.msi.msi_handlers == 0)
4833 pci_disable_msi(child);
4834 } else {
4835 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
4836 ("No MSI or MSI-X interrupts allocated"));
4837 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
4838 ("MSI-X index too high"));
4839 mte = &dinfo->cfg.msix.msix_table[rid - 1];
4840 if (mte->mte_handlers == 0)
4841 return (EINVAL);
4842 mte->mte_handlers--;
4843 if (mte->mte_handlers == 0)
4844 pci_mask_msix(child, rid - 1);
4845 }
4846 }
4847 error = bus_generic_teardown_intr(dev, child, irq, cookie);
4848 if (rid > 0)
4849 KASSERT(error == 0,
4850 ("%s: generic teardown failed for MSI/MSI-X", __func__));
4851 return (error);
4852 }
4853
4854 int
pci_print_child(device_t dev,device_t child)4855 pci_print_child(device_t dev, device_t child)
4856 {
4857 struct pci_devinfo *dinfo;
4858 struct resource_list *rl;
4859 int retval = 0;
4860
4861 dinfo = device_get_ivars(child);
4862 rl = &dinfo->resources;
4863
4864 retval += bus_print_child_header(dev, child);
4865
4866 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#jx");
4867 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx");
4868 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd");
4869 if (device_get_flags(dev))
4870 retval += printf(" flags %#x", device_get_flags(dev));
4871
4872 retval += printf(" at device %d.%d", pci_get_slot(child),
4873 pci_get_function(child));
4874
4875 retval += bus_print_child_domain(dev, child);
4876 retval += bus_print_child_footer(dev, child);
4877
4878 return (retval);
4879 }
4880
4881 static const struct
4882 {
4883 int class;
4884 int subclass;
4885 int report; /* 0 = bootverbose, 1 = always */
4886 const char *desc;
4887 } pci_nomatch_tab[] = {
4888 {PCIC_OLD, -1, 1, "old"},
4889 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"},
4890 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"},
4891 {PCIC_STORAGE, -1, 1, "mass storage"},
4892 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"},
4893 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"},
4894 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"},
4895 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"},
4896 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"},
4897 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"},
4898 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"},
4899 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"},
4900 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"},
4901 {PCIC_NETWORK, -1, 1, "network"},
4902 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"},
4903 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"},
4904 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"},
4905 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"},
4906 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"},
4907 {PCIC_DISPLAY, -1, 1, "display"},
4908 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"},
4909 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"},
4910 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"},
4911 {PCIC_MULTIMEDIA, -1, 1, "multimedia"},
4912 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"},
4913 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"},
4914 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"},
4915 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"},
4916 {PCIC_MEMORY, -1, 1, "memory"},
4917 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"},
4918 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"},
4919 {PCIC_BRIDGE, -1, 1, "bridge"},
4920 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"},
4921 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"},
4922 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"},
4923 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"},
4924 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"},
4925 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"},
4926 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"},
4927 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"},
4928 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"},
4929 {PCIC_SIMPLECOMM, -1, 1, "simple comms"},
4930 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */
4931 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"},
4932 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"},
4933 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"},
4934 {PCIC_BASEPERIPH, -1, 0, "base peripheral"},
4935 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"},
4936 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"},
4937 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"},
4938 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"},
4939 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"},
4940 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"},
4941 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"},
4942 {PCIC_INPUTDEV, -1, 1, "input device"},
4943 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"},
4944 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"},
4945 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"},
4946 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"},
4947 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"},
4948 {PCIC_DOCKING, -1, 1, "docking station"},
4949 {PCIC_PROCESSOR, -1, 1, "processor"},
4950 {PCIC_SERIALBUS, -1, 1, "serial bus"},
4951 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"},
4952 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"},
4953 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"},
4954 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"},
4955 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"},
4956 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"},
4957 {PCIC_WIRELESS, -1, 1, "wireless controller"},
4958 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"},
4959 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"},
4960 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"},
4961 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"},
4962 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"},
4963 {PCIC_SATCOM, -1, 1, "satellite communication"},
4964 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"},
4965 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"},
4966 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"},
4967 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"},
4968 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"},
4969 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"},
4970 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"},
4971 {PCIC_DASP, -1, 0, "dasp"},
4972 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"},
4973 {PCIC_DASP, PCIS_DASP_PERFCNTRS, 1, "performance counters"},
4974 {PCIC_DASP, PCIS_DASP_COMM_SYNC, 1, "communication synchronizer"},
4975 {PCIC_DASP, PCIS_DASP_MGMT_CARD, 1, "signal processing management"},
4976 {0, 0, 0, NULL}
4977 };
4978
4979 void
pci_probe_nomatch(device_t dev,device_t child)4980 pci_probe_nomatch(device_t dev, device_t child)
4981 {
4982 int i, report;
4983 const char *cp, *scp;
4984 char *device;
4985
4986 /*
4987 * Look for a listing for this device in a loaded device database.
4988 */
4989 report = 1;
4990 if ((device = pci_describe_device(child)) != NULL) {
4991 device_printf(dev, "<%s>", device);
4992 free(device, M_DEVBUF);
4993 } else {
4994 /*
4995 * Scan the class/subclass descriptions for a general
4996 * description.
4997 */
4998 cp = "unknown";
4999 scp = NULL;
5000 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
5001 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
5002 if (pci_nomatch_tab[i].subclass == -1) {
5003 cp = pci_nomatch_tab[i].desc;
5004 report = pci_nomatch_tab[i].report;
5005 } else if (pci_nomatch_tab[i].subclass ==
5006 pci_get_subclass(child)) {
5007 scp = pci_nomatch_tab[i].desc;
5008 report = pci_nomatch_tab[i].report;
5009 }
5010 }
5011 }
5012 if (report || bootverbose) {
5013 device_printf(dev, "<%s%s%s>",
5014 cp ? cp : "",
5015 ((cp != NULL) && (scp != NULL)) ? ", " : "",
5016 scp ? scp : "");
5017 }
5018 }
5019 if (report || bootverbose) {
5020 printf(" at device %d.%d (no driver attached)\n",
5021 pci_get_slot(child), pci_get_function(child));
5022 }
5023 pci_cfg_save(child, device_get_ivars(child), 1);
5024 }
5025
5026 void
pci_child_detached(device_t dev,device_t child)5027 pci_child_detached(device_t dev, device_t child)
5028 {
5029 struct pci_devinfo *dinfo;
5030 struct resource_list *rl;
5031
5032 dinfo = device_get_ivars(child);
5033 rl = &dinfo->resources;
5034
5035 /*
5036 * Have to deallocate IRQs before releasing any MSI messages and
5037 * have to release MSI messages before deallocating any memory
5038 * BARs.
5039 */
5040 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0)
5041 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n");
5042 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) {
5043 pci_printf(&dinfo->cfg, "Device leaked MSI vectors\n");
5044 (void)pci_release_msi(child);
5045 }
5046 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0)
5047 pci_printf(&dinfo->cfg, "Device leaked memory resources\n");
5048 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0)
5049 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n");
5050 #ifdef PCI_RES_BUS
5051 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0)
5052 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n");
5053 #endif
5054
5055 pci_cfg_save(child, dinfo, 1);
5056 }
5057
5058 /*
5059 * Parse the PCI device database, if loaded, and return a pointer to a
5060 * description of the device.
5061 *
5062 * The database is flat text formatted as follows:
5063 *
5064 * Any line not in a valid format is ignored.
5065 * Lines are terminated with newline '\n' characters.
5066 *
5067 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
5068 * the vendor name.
5069 *
5070 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
5071 * - devices cannot be listed without a corresponding VENDOR line.
5072 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
5073 * another TAB, then the device name.
5074 */
5075
5076 /*
5077 * Assuming (ptr) points to the beginning of a line in the database,
5078 * return the vendor or device and description of the next entry.
5079 * The value of (vendor) or (device) inappropriate for the entry type
5080 * is set to -1. Returns nonzero at the end of the database.
5081 *
5082 * Note that this is slightly unrobust in the face of corrupt data;
5083 * we attempt to safeguard against this by spamming the end of the
5084 * database with a newline when we initialise.
5085 */
5086 static int
pci_describe_parse_line(char ** ptr,int * vendor,int * device,char ** desc)5087 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
5088 {
5089 char *cp = *ptr;
5090 int left;
5091
5092 *device = -1;
5093 *vendor = -1;
5094 **desc = '\0';
5095 for (;;) {
5096 left = pci_vendordata_size - (cp - pci_vendordata);
5097 if (left <= 0) {
5098 *ptr = cp;
5099 return(1);
5100 }
5101
5102 /* vendor entry? */
5103 if (*cp != '\t' &&
5104 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
5105 break;
5106 /* device entry? */
5107 if (*cp == '\t' &&
5108 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
5109 break;
5110
5111 /* skip to next line */
5112 while (*cp != '\n' && left > 0) {
5113 cp++;
5114 left--;
5115 }
5116 if (*cp == '\n') {
5117 cp++;
5118 left--;
5119 }
5120 }
5121 /* skip to next line */
5122 while (*cp != '\n' && left > 0) {
5123 cp++;
5124 left--;
5125 }
5126 if (*cp == '\n' && left > 0)
5127 cp++;
5128 *ptr = cp;
5129 return(0);
5130 }
5131
5132 static char *
pci_describe_device(device_t dev)5133 pci_describe_device(device_t dev)
5134 {
5135 int vendor, device;
5136 char *desc, *vp, *dp, *line;
5137
5138 desc = vp = dp = NULL;
5139
5140 /*
5141 * If we have no vendor data, we can't do anything.
5142 */
5143 if (pci_vendordata == NULL)
5144 goto out;
5145
5146 /*
5147 * Scan the vendor data looking for this device
5148 */
5149 line = pci_vendordata;
5150 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
5151 goto out;
5152 for (;;) {
5153 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
5154 goto out;
5155 if (vendor == pci_get_vendor(dev))
5156 break;
5157 }
5158 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
5159 goto out;
5160 for (;;) {
5161 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
5162 *dp = 0;
5163 break;
5164 }
5165 if (vendor != -1) {
5166 *dp = 0;
5167 break;
5168 }
5169 if (device == pci_get_device(dev))
5170 break;
5171 }
5172 if (dp[0] == '\0')
5173 snprintf(dp, 80, "0x%x", pci_get_device(dev));
5174 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
5175 NULL)
5176 sprintf(desc, "%s, %s", vp, dp);
5177 out:
5178 if (vp != NULL)
5179 free(vp, M_DEVBUF);
5180 if (dp != NULL)
5181 free(dp, M_DEVBUF);
5182 return(desc);
5183 }
5184
5185 int
pci_read_ivar(device_t dev,device_t child,int which,uintptr_t * result)5186 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
5187 {
5188 struct pci_devinfo *dinfo;
5189 pcicfgregs *cfg;
5190
5191 dinfo = device_get_ivars(child);
5192 cfg = &dinfo->cfg;
5193
5194 switch (which) {
5195 case PCI_IVAR_ETHADDR:
5196 /*
5197 * The generic accessor doesn't deal with failure, so
5198 * we set the return value, then return an error.
5199 */
5200 *((uint8_t **) result) = NULL;
5201 return (EINVAL);
5202 case PCI_IVAR_SUBVENDOR:
5203 *result = cfg->subvendor;
5204 break;
5205 case PCI_IVAR_SUBDEVICE:
5206 *result = cfg->subdevice;
5207 break;
5208 case PCI_IVAR_VENDOR:
5209 *result = cfg->vendor;
5210 break;
5211 case PCI_IVAR_DEVICE:
5212 *result = cfg->device;
5213 break;
5214 case PCI_IVAR_DEVID:
5215 *result = (cfg->device << 16) | cfg->vendor;
5216 break;
5217 case PCI_IVAR_CLASS:
5218 *result = cfg->baseclass;
5219 break;
5220 case PCI_IVAR_SUBCLASS:
5221 *result = cfg->subclass;
5222 break;
5223 case PCI_IVAR_PROGIF:
5224 *result = cfg->progif;
5225 break;
5226 case PCI_IVAR_REVID:
5227 *result = cfg->revid;
5228 break;
5229 case PCI_IVAR_INTPIN:
5230 *result = cfg->intpin;
5231 break;
5232 case PCI_IVAR_IRQ:
5233 *result = cfg->intline;
5234 break;
5235 case PCI_IVAR_DOMAIN:
5236 *result = cfg->domain;
5237 break;
5238 case PCI_IVAR_BUS:
5239 *result = cfg->bus;
5240 break;
5241 case PCI_IVAR_SLOT:
5242 *result = cfg->slot;
5243 break;
5244 case PCI_IVAR_FUNCTION:
5245 *result = cfg->func;
5246 break;
5247 case PCI_IVAR_CMDREG:
5248 *result = cfg->cmdreg;
5249 break;
5250 case PCI_IVAR_CACHELNSZ:
5251 *result = cfg->cachelnsz;
5252 break;
5253 case PCI_IVAR_MINGNT:
5254 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) {
5255 *result = -1;
5256 return (EINVAL);
5257 }
5258 *result = cfg->mingnt;
5259 break;
5260 case PCI_IVAR_MAXLAT:
5261 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) {
5262 *result = -1;
5263 return (EINVAL);
5264 }
5265 *result = cfg->maxlat;
5266 break;
5267 case PCI_IVAR_LATTIMER:
5268 *result = cfg->lattimer;
5269 break;
5270 default:
5271 return (ENOENT);
5272 }
5273 return (0);
5274 }
5275
5276 int
pci_write_ivar(device_t dev,device_t child,int which,uintptr_t value)5277 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
5278 {
5279 struct pci_devinfo *dinfo;
5280
5281 dinfo = device_get_ivars(child);
5282
5283 switch (which) {
5284 case PCI_IVAR_INTPIN:
5285 dinfo->cfg.intpin = value;
5286 return (0);
5287 case PCI_IVAR_ETHADDR:
5288 case PCI_IVAR_SUBVENDOR:
5289 case PCI_IVAR_SUBDEVICE:
5290 case PCI_IVAR_VENDOR:
5291 case PCI_IVAR_DEVICE:
5292 case PCI_IVAR_DEVID:
5293 case PCI_IVAR_CLASS:
5294 case PCI_IVAR_SUBCLASS:
5295 case PCI_IVAR_PROGIF:
5296 case PCI_IVAR_REVID:
5297 case PCI_IVAR_IRQ:
5298 case PCI_IVAR_DOMAIN:
5299 case PCI_IVAR_BUS:
5300 case PCI_IVAR_SLOT:
5301 case PCI_IVAR_FUNCTION:
5302 return (EINVAL); /* disallow for now */
5303
5304 default:
5305 return (ENOENT);
5306 }
5307 }
5308
5309 #include "opt_ddb.h"
5310 #ifdef DDB
5311 #include <ddb/ddb.h>
5312 #include <sys/cons.h>
5313
5314 /*
5315 * List resources based on pci map registers, used for within ddb
5316 */
5317
DB_SHOW_COMMAND(pciregs,db_pci_dump)5318 DB_SHOW_COMMAND(pciregs, db_pci_dump)
5319 {
5320 struct pci_devinfo *dinfo;
5321 struct devlist *devlist_head;
5322 struct pci_conf *p;
5323 const char *name;
5324 int i, error, none_count;
5325
5326 none_count = 0;
5327 /* get the head of the device queue */
5328 devlist_head = &pci_devq;
5329
5330 /*
5331 * Go through the list of devices and print out devices
5332 */
5333 for (error = 0, i = 0,
5334 dinfo = STAILQ_FIRST(devlist_head);
5335 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
5336 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
5337
5338 /* Populate pd_name and pd_unit */
5339 name = NULL;
5340 if (dinfo->cfg.dev)
5341 name = device_get_name(dinfo->cfg.dev);
5342
5343 p = &dinfo->conf;
5344 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
5345 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
5346 (name && *name) ? name : "none",
5347 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
5348 none_count++,
5349 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
5350 p->pc_sel.pc_func, (p->pc_class << 16) |
5351 (p->pc_subclass << 8) | p->pc_progif,
5352 (p->pc_subdevice << 16) | p->pc_subvendor,
5353 (p->pc_device << 16) | p->pc_vendor,
5354 p->pc_revid, p->pc_hdr);
5355 }
5356 }
5357 #endif /* DDB */
5358
5359 static struct resource *
pci_reserve_map(device_t dev,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int num,u_int flags)5360 pci_reserve_map(device_t dev, device_t child, int type, int *rid,
5361 rman_res_t start, rman_res_t end, rman_res_t count, u_int num,
5362 u_int flags)
5363 {
5364 struct pci_devinfo *dinfo = device_get_ivars(child);
5365 struct resource_list *rl = &dinfo->resources;
5366 struct resource *res;
5367 struct pci_map *pm;
5368 uint16_t cmd;
5369 pci_addr_t map, testval;
5370 int mapsize;
5371
5372 res = NULL;
5373
5374 /* If rid is managed by EA, ignore it */
5375 if (pci_ea_is_enabled(child, *rid))
5376 goto out;
5377
5378 pm = pci_find_bar(child, *rid);
5379 if (pm != NULL) {
5380 /* This is a BAR that we failed to allocate earlier. */
5381 mapsize = pm->pm_size;
5382 map = pm->pm_value;
5383 } else {
5384 /*
5385 * Weed out the bogons, and figure out how large the
5386 * BAR/map is. BARs that read back 0 here are bogus
5387 * and unimplemented. Note: atapci in legacy mode are
5388 * special and handled elsewhere in the code. If you
5389 * have a atapci device in legacy mode and it fails
5390 * here, that other code is broken.
5391 */
5392 pci_read_bar(child, *rid, &map, &testval, NULL);
5393
5394 /*
5395 * Determine the size of the BAR and ignore BARs with a size
5396 * of 0. Device ROM BARs use a different mask value.
5397 */
5398 if (PCIR_IS_BIOS(&dinfo->cfg, *rid))
5399 mapsize = pci_romsize(testval);
5400 else
5401 mapsize = pci_mapsize(testval);
5402 if (mapsize == 0)
5403 goto out;
5404 pm = pci_add_bar(child, *rid, map, mapsize);
5405 }
5406
5407 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) {
5408 if (type != SYS_RES_MEMORY) {
5409 if (bootverbose)
5410 device_printf(dev,
5411 "child %s requested type %d for rid %#x,"
5412 " but the BAR says it is an memio\n",
5413 device_get_nameunit(child), type, *rid);
5414 goto out;
5415 }
5416 } else {
5417 if (type != SYS_RES_IOPORT) {
5418 if (bootverbose)
5419 device_printf(dev,
5420 "child %s requested type %d for rid %#x,"
5421 " but the BAR says it is an ioport\n",
5422 device_get_nameunit(child), type, *rid);
5423 goto out;
5424 }
5425 }
5426
5427 /*
5428 * For real BARs, we need to override the size that
5429 * the driver requests, because that's what the BAR
5430 * actually uses and we would otherwise have a
5431 * situation where we might allocate the excess to
5432 * another driver, which won't work.
5433 */
5434 count = ((pci_addr_t)1 << mapsize) * num;
5435 if (RF_ALIGNMENT(flags) < mapsize)
5436 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
5437 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH))
5438 flags |= RF_PREFETCHABLE;
5439
5440 /*
5441 * Allocate enough resource, and then write back the
5442 * appropriate BAR for that resource.
5443 */
5444 resource_list_add(rl, type, *rid, start, end, count);
5445 res = resource_list_reserve(rl, dev, child, type, rid, start, end,
5446 count, flags & ~RF_ACTIVE);
5447 if (res == NULL) {
5448 resource_list_delete(rl, type, *rid);
5449 device_printf(child,
5450 "%#jx bytes of rid %#x res %d failed (%#jx, %#jx).\n",
5451 count, *rid, type, start, end);
5452 goto out;
5453 }
5454 if (bootverbose)
5455 device_printf(child,
5456 "Lazy allocation of %#jx bytes rid %#x type %d at %#jx\n",
5457 count, *rid, type, rman_get_start(res));
5458
5459 /* Disable decoding via the CMD register before updating the BAR */
5460 cmd = pci_read_config(child, PCIR_COMMAND, 2);
5461 pci_write_config(child, PCIR_COMMAND,
5462 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
5463
5464 map = rman_get_start(res);
5465 pci_write_bar(child, pm, map);
5466
5467 /* Restore the original value of the CMD register */
5468 pci_write_config(child, PCIR_COMMAND, cmd, 2);
5469 out:
5470 return (res);
5471 }
5472
5473 struct resource *
pci_alloc_multi_resource(device_t dev,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_long num,u_int flags)5474 pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid,
5475 rman_res_t start, rman_res_t end, rman_res_t count, u_long num,
5476 u_int flags)
5477 {
5478 struct pci_devinfo *dinfo;
5479 struct resource_list *rl;
5480 struct resource_list_entry *rle;
5481 struct resource *res;
5482 pcicfgregs *cfg;
5483
5484 /*
5485 * Perform lazy resource allocation
5486 */
5487 dinfo = device_get_ivars(child);
5488 rl = &dinfo->resources;
5489 cfg = &dinfo->cfg;
5490 switch (type) {
5491 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
5492 case PCI_RES_BUS:
5493 return (pci_alloc_secbus(dev, child, rid, start, end, count,
5494 flags));
5495 #endif
5496 case SYS_RES_IRQ:
5497 /*
5498 * Can't alloc legacy interrupt once MSI messages have
5499 * been allocated.
5500 */
5501 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
5502 cfg->msix.msix_alloc > 0))
5503 return (NULL);
5504
5505 /*
5506 * If the child device doesn't have an interrupt
5507 * routed and is deserving of an interrupt, try to
5508 * assign it one.
5509 */
5510 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
5511 (cfg->intpin != 0))
5512 pci_assign_interrupt(dev, child, 0);
5513 break;
5514 case SYS_RES_IOPORT:
5515 case SYS_RES_MEMORY:
5516 #ifdef NEW_PCIB
5517 /*
5518 * PCI-PCI bridge I/O window resources are not BARs.
5519 * For those allocations just pass the request up the
5520 * tree.
5521 */
5522 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) {
5523 switch (*rid) {
5524 case PCIR_IOBASEL_1:
5525 case PCIR_MEMBASE_1:
5526 case PCIR_PMBASEL_1:
5527 /*
5528 * XXX: Should we bother creating a resource
5529 * list entry?
5530 */
5531 return (bus_generic_alloc_resource(dev, child,
5532 type, rid, start, end, count, flags));
5533 }
5534 }
5535 #endif
5536 /* Reserve resources for this BAR if needed. */
5537 rle = resource_list_find(rl, type, *rid);
5538 if (rle == NULL) {
5539 res = pci_reserve_map(dev, child, type, rid, start, end,
5540 count, num, flags);
5541 if (res == NULL)
5542 return (NULL);
5543 }
5544 }
5545 return (resource_list_alloc(rl, dev, child, type, rid,
5546 start, end, count, flags));
5547 }
5548
5549 struct resource *
pci_alloc_resource(device_t dev,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)5550 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
5551 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
5552 {
5553 #ifdef PCI_IOV
5554 struct pci_devinfo *dinfo;
5555 #endif
5556
5557 if (device_get_parent(child) != dev)
5558 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
5559 type, rid, start, end, count, flags));
5560
5561 #ifdef PCI_IOV
5562 dinfo = device_get_ivars(child);
5563 if (dinfo->cfg.flags & PCICFG_VF) {
5564 switch (type) {
5565 /* VFs can't have I/O BARs. */
5566 case SYS_RES_IOPORT:
5567 return (NULL);
5568 case SYS_RES_MEMORY:
5569 return (pci_vf_alloc_mem_resource(dev, child, rid,
5570 start, end, count, flags));
5571 }
5572
5573 /* Fall through for other types of resource allocations. */
5574 }
5575 #endif
5576
5577 return (pci_alloc_multi_resource(dev, child, type, rid, start, end,
5578 count, 1, flags));
5579 }
5580
5581 int
pci_release_resource(device_t dev,device_t child,int type,int rid,struct resource * r)5582 pci_release_resource(device_t dev, device_t child, int type, int rid,
5583 struct resource *r)
5584 {
5585 struct pci_devinfo *dinfo;
5586 struct resource_list *rl;
5587 pcicfgregs *cfg;
5588
5589 if (device_get_parent(child) != dev)
5590 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
5591 type, rid, r));
5592
5593 dinfo = device_get_ivars(child);
5594 cfg = &dinfo->cfg;
5595
5596 #ifdef PCI_IOV
5597 if (dinfo->cfg.flags & PCICFG_VF) {
5598 switch (type) {
5599 /* VFs can't have I/O BARs. */
5600 case SYS_RES_IOPORT:
5601 return (EDOOFUS);
5602 case SYS_RES_MEMORY:
5603 return (pci_vf_release_mem_resource(dev, child, rid,
5604 r));
5605 }
5606
5607 /* Fall through for other types of resource allocations. */
5608 }
5609 #endif
5610
5611 #ifdef NEW_PCIB
5612 /*
5613 * PCI-PCI bridge I/O window resources are not BARs. For
5614 * those allocations just pass the request up the tree.
5615 */
5616 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE &&
5617 (type == SYS_RES_IOPORT || type == SYS_RES_MEMORY)) {
5618 switch (rid) {
5619 case PCIR_IOBASEL_1:
5620 case PCIR_MEMBASE_1:
5621 case PCIR_PMBASEL_1:
5622 return (bus_generic_release_resource(dev, child, type,
5623 rid, r));
5624 }
5625 }
5626 #endif
5627
5628 rl = &dinfo->resources;
5629 return (resource_list_release(rl, dev, child, type, rid, r));
5630 }
5631
5632 int
pci_activate_resource(device_t dev,device_t child,int type,int rid,struct resource * r)5633 pci_activate_resource(device_t dev, device_t child, int type, int rid,
5634 struct resource *r)
5635 {
5636 struct pci_devinfo *dinfo;
5637 int error;
5638
5639 error = bus_generic_activate_resource(dev, child, type, rid, r);
5640 if (error)
5641 return (error);
5642
5643 /* Enable decoding in the command register when activating BARs. */
5644 if (device_get_parent(child) == dev) {
5645 /* Device ROMs need their decoding explicitly enabled. */
5646 dinfo = device_get_ivars(child);
5647 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
5648 pci_write_bar(child, pci_find_bar(child, rid),
5649 rman_get_start(r) | PCIM_BIOS_ENABLE);
5650 switch (type) {
5651 case SYS_RES_IOPORT:
5652 case SYS_RES_MEMORY:
5653 error = PCI_ENABLE_IO(dev, child, type);
5654 break;
5655 }
5656 }
5657 return (error);
5658 }
5659
5660 int
pci_deactivate_resource(device_t dev,device_t child,int type,int rid,struct resource * r)5661 pci_deactivate_resource(device_t dev, device_t child, int type,
5662 int rid, struct resource *r)
5663 {
5664 struct pci_devinfo *dinfo;
5665 int error;
5666
5667 error = bus_generic_deactivate_resource(dev, child, type, rid, r);
5668 if (error)
5669 return (error);
5670
5671 /* Disable decoding for device ROMs. */
5672 if (device_get_parent(child) == dev) {
5673 dinfo = device_get_ivars(child);
5674 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
5675 pci_write_bar(child, pci_find_bar(child, rid),
5676 rman_get_start(r));
5677 }
5678 return (0);
5679 }
5680
5681 void
pci_child_deleted(device_t dev,device_t child)5682 pci_child_deleted(device_t dev, device_t child)
5683 {
5684 struct resource_list_entry *rle;
5685 struct resource_list *rl;
5686 struct pci_devinfo *dinfo;
5687
5688 dinfo = device_get_ivars(child);
5689 rl = &dinfo->resources;
5690
5691 EVENTHANDLER_INVOKE(pci_delete_device, child);
5692
5693 /* Turn off access to resources we're about to free */
5694 if (bus_child_present(child) != 0) {
5695 pci_write_config(child, PCIR_COMMAND, pci_read_config(child,
5696 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2);
5697
5698 pci_disable_busmaster(child);
5699 }
5700
5701 /* Free all allocated resources */
5702 STAILQ_FOREACH(rle, rl, link) {
5703 if (rle->res) {
5704 if (rman_get_flags(rle->res) & RF_ACTIVE ||
5705 resource_list_busy(rl, rle->type, rle->rid)) {
5706 pci_printf(&dinfo->cfg,
5707 "Resource still owned, oops. "
5708 "(type=%d, rid=%d, addr=%lx)\n",
5709 rle->type, rle->rid,
5710 rman_get_start(rle->res));
5711 bus_release_resource(child, rle->type, rle->rid,
5712 rle->res);
5713 }
5714 resource_list_unreserve(rl, dev, child, rle->type,
5715 rle->rid);
5716 }
5717 }
5718 resource_list_free(rl);
5719
5720 pci_freecfg(dinfo);
5721 }
5722
5723 void
pci_delete_resource(device_t dev,device_t child,int type,int rid)5724 pci_delete_resource(device_t dev, device_t child, int type, int rid)
5725 {
5726 struct pci_devinfo *dinfo;
5727 struct resource_list *rl;
5728 struct resource_list_entry *rle;
5729
5730 if (device_get_parent(child) != dev)
5731 return;
5732
5733 dinfo = device_get_ivars(child);
5734 rl = &dinfo->resources;
5735 rle = resource_list_find(rl, type, rid);
5736 if (rle == NULL)
5737 return;
5738
5739 if (rle->res) {
5740 if (rman_get_flags(rle->res) & RF_ACTIVE ||
5741 resource_list_busy(rl, type, rid)) {
5742 device_printf(dev, "delete_resource: "
5743 "Resource still owned by child, oops. "
5744 "(type=%d, rid=%d, addr=%jx)\n",
5745 type, rid, rman_get_start(rle->res));
5746 return;
5747 }
5748 resource_list_unreserve(rl, dev, child, type, rid);
5749 }
5750 resource_list_delete(rl, type, rid);
5751 }
5752
5753 struct resource_list *
pci_get_resource_list(device_t dev,device_t child)5754 pci_get_resource_list (device_t dev, device_t child)
5755 {
5756 struct pci_devinfo *dinfo = device_get_ivars(child);
5757
5758 return (&dinfo->resources);
5759 }
5760
5761 bus_dma_tag_t
pci_get_dma_tag(device_t bus,device_t dev)5762 pci_get_dma_tag(device_t bus, device_t dev)
5763 {
5764 struct pci_softc *sc = device_get_softc(bus);
5765
5766 return (sc->sc_dma_tag);
5767 }
5768
5769 uint32_t
pci_read_config_method(device_t dev,device_t child,int reg,int width)5770 pci_read_config_method(device_t dev, device_t child, int reg, int width)
5771 {
5772 struct pci_devinfo *dinfo = device_get_ivars(child);
5773 pcicfgregs *cfg = &dinfo->cfg;
5774
5775 #ifdef PCI_IOV
5776 /*
5777 * SR-IOV VFs don't implement the VID or DID registers, so we have to
5778 * emulate them here.
5779 */
5780 if (cfg->flags & PCICFG_VF) {
5781 if (reg == PCIR_VENDOR) {
5782 switch (width) {
5783 case 4:
5784 return (cfg->device << 16 | cfg->vendor);
5785 case 2:
5786 return (cfg->vendor);
5787 case 1:
5788 return (cfg->vendor & 0xff);
5789 default:
5790 return (0xffffffff);
5791 }
5792 } else if (reg == PCIR_DEVICE) {
5793 switch (width) {
5794 /* Note that an unaligned 4-byte read is an error. */
5795 case 2:
5796 return (cfg->device);
5797 case 1:
5798 return (cfg->device & 0xff);
5799 default:
5800 return (0xffffffff);
5801 }
5802 }
5803 }
5804 #endif
5805
5806 return (PCIB_READ_CONFIG(device_get_parent(dev),
5807 cfg->bus, cfg->slot, cfg->func, reg, width));
5808 }
5809
5810 void
pci_write_config_method(device_t dev,device_t child,int reg,uint32_t val,int width)5811 pci_write_config_method(device_t dev, device_t child, int reg,
5812 uint32_t val, int width)
5813 {
5814 struct pci_devinfo *dinfo = device_get_ivars(child);
5815 pcicfgregs *cfg = &dinfo->cfg;
5816
5817 PCIB_WRITE_CONFIG(device_get_parent(dev),
5818 cfg->bus, cfg->slot, cfg->func, reg, val, width);
5819 }
5820
5821 int
pci_child_location_str_method(device_t dev,device_t child,char * buf,size_t buflen)5822 pci_child_location_str_method(device_t dev, device_t child, char *buf,
5823 size_t buflen)
5824 {
5825
5826 snprintf(buf, buflen, "slot=%d function=%d dbsf=pci%d:%d:%d:%d",
5827 pci_get_slot(child), pci_get_function(child), pci_get_domain(child),
5828 pci_get_bus(child), pci_get_slot(child), pci_get_function(child));
5829 return (0);
5830 }
5831
5832 int
pci_child_pnpinfo_str_method(device_t dev,device_t child,char * buf,size_t buflen)5833 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
5834 size_t buflen)
5835 {
5836 struct pci_devinfo *dinfo;
5837 pcicfgregs *cfg;
5838
5839 dinfo = device_get_ivars(child);
5840 cfg = &dinfo->cfg;
5841 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
5842 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
5843 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
5844 cfg->progif);
5845 return (0);
5846 }
5847
5848 int
pci_assign_interrupt_method(device_t dev,device_t child)5849 pci_assign_interrupt_method(device_t dev, device_t child)
5850 {
5851 struct pci_devinfo *dinfo = device_get_ivars(child);
5852 pcicfgregs *cfg = &dinfo->cfg;
5853
5854 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
5855 cfg->intpin));
5856 }
5857
5858 static void
pci_lookup(void * arg,const char * name,device_t * dev)5859 pci_lookup(void *arg, const char *name, device_t *dev)
5860 {
5861 long val;
5862 char *end;
5863 int domain, bus, slot, func;
5864
5865 if (*dev != NULL)
5866 return;
5867
5868 /*
5869 * Accept pciconf-style selectors of either pciD:B:S:F or
5870 * pciB:S:F. In the latter case, the domain is assumed to
5871 * be zero.
5872 */
5873 if (strncmp(name, "pci", 3) != 0)
5874 return;
5875 val = strtol(name + 3, &end, 10);
5876 if (val < 0 || val > INT_MAX || *end != ':')
5877 return;
5878 domain = val;
5879 val = strtol(end + 1, &end, 10);
5880 if (val < 0 || val > INT_MAX || *end != ':')
5881 return;
5882 bus = val;
5883 val = strtol(end + 1, &end, 10);
5884 if (val < 0 || val > INT_MAX)
5885 return;
5886 slot = val;
5887 if (*end == ':') {
5888 val = strtol(end + 1, &end, 10);
5889 if (val < 0 || val > INT_MAX || *end != '\0')
5890 return;
5891 func = val;
5892 } else if (*end == '\0') {
5893 func = slot;
5894 slot = bus;
5895 bus = domain;
5896 domain = 0;
5897 } else
5898 return;
5899
5900 if (domain > PCI_DOMAINMAX || bus > PCI_BUSMAX || slot > PCI_SLOTMAX ||
5901 func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX))
5902 return;
5903
5904 *dev = pci_find_dbsf(domain, bus, slot, func);
5905 }
5906
5907 static int
pci_modevent(module_t mod,int what,void * arg)5908 pci_modevent(module_t mod, int what, void *arg)
5909 {
5910 static struct cdev *pci_cdev;
5911 static eventhandler_tag tag;
5912
5913 switch (what) {
5914 case MOD_LOAD:
5915 STAILQ_INIT(&pci_devq);
5916 pci_generation = 0;
5917 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644,
5918 "pci");
5919 pci_load_vendor_data();
5920 tag = EVENTHANDLER_REGISTER(dev_lookup, pci_lookup, NULL,
5921 1000);
5922 break;
5923
5924 case MOD_UNLOAD:
5925 if (tag != NULL)
5926 EVENTHANDLER_DEREGISTER(dev_lookup, tag);
5927 destroy_dev(pci_cdev);
5928 break;
5929 }
5930
5931 return (0);
5932 }
5933
5934 static void
pci_cfg_restore_pcie(device_t dev,struct pci_devinfo * dinfo)5935 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo)
5936 {
5937 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2)
5938 struct pcicfg_pcie *cfg;
5939 int version, pos;
5940
5941 cfg = &dinfo->cfg.pcie;
5942 pos = cfg->pcie_location;
5943
5944 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION;
5945
5946 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl);
5947
5948 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
5949 cfg->pcie_type == PCIEM_TYPE_ENDPOINT ||
5950 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT)
5951 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl);
5952
5953 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
5954 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT &&
5955 (cfg->pcie_flags & PCIEM_FLAGS_SLOT))))
5956 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl);
5957
5958 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
5959 cfg->pcie_type == PCIEM_TYPE_ROOT_EC)
5960 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl);
5961
5962 if (version > 1) {
5963 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2);
5964 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2);
5965 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2);
5966 }
5967 #undef WREG
5968 }
5969
5970 static void
pci_cfg_restore_pcix(device_t dev,struct pci_devinfo * dinfo)5971 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo)
5972 {
5973 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND,
5974 dinfo->cfg.pcix.pcix_command, 2);
5975 }
5976
5977 void
pci_cfg_restore(device_t dev,struct pci_devinfo * dinfo)5978 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
5979 {
5980
5981 /*
5982 * Restore the device to full power mode. We must do this
5983 * before we restore the registers because moving from D3 to
5984 * D0 will cause the chip's BARs and some other registers to
5985 * be reset to some unknown power on reset values. Cut down
5986 * the noise on boot by doing nothing if we are already in
5987 * state D0.
5988 */
5989 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0)
5990 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
5991 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
5992 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
5993 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
5994 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
5995 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
5996 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
5997 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) {
5998 case PCIM_HDRTYPE_NORMAL:
5999 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
6000 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
6001 break;
6002 case PCIM_HDRTYPE_BRIDGE:
6003 pci_write_config(dev, PCIR_SECLAT_1,
6004 dinfo->cfg.bridge.br_seclat, 1);
6005 pci_write_config(dev, PCIR_SUBBUS_1,
6006 dinfo->cfg.bridge.br_subbus, 1);
6007 pci_write_config(dev, PCIR_SECBUS_1,
6008 dinfo->cfg.bridge.br_secbus, 1);
6009 pci_write_config(dev, PCIR_PRIBUS_1,
6010 dinfo->cfg.bridge.br_pribus, 1);
6011 pci_write_config(dev, PCIR_BRIDGECTL_1,
6012 dinfo->cfg.bridge.br_control, 2);
6013 break;
6014 case PCIM_HDRTYPE_CARDBUS:
6015 pci_write_config(dev, PCIR_SECLAT_2,
6016 dinfo->cfg.bridge.br_seclat, 1);
6017 pci_write_config(dev, PCIR_SUBBUS_2,
6018 dinfo->cfg.bridge.br_subbus, 1);
6019 pci_write_config(dev, PCIR_SECBUS_2,
6020 dinfo->cfg.bridge.br_secbus, 1);
6021 pci_write_config(dev, PCIR_PRIBUS_2,
6022 dinfo->cfg.bridge.br_pribus, 1);
6023 pci_write_config(dev, PCIR_BRIDGECTL_2,
6024 dinfo->cfg.bridge.br_control, 2);
6025 break;
6026 }
6027 pci_restore_bars(dev);
6028
6029 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE)
6030 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
6031
6032 /*
6033 * Restore extended capabilities for PCI-Express and PCI-X
6034 */
6035 if (dinfo->cfg.pcie.pcie_location != 0)
6036 pci_cfg_restore_pcie(dev, dinfo);
6037 if (dinfo->cfg.pcix.pcix_location != 0)
6038 pci_cfg_restore_pcix(dev, dinfo);
6039
6040 /* Restore MSI and MSI-X configurations if they are present. */
6041 if (dinfo->cfg.msi.msi_location != 0)
6042 pci_resume_msi(dev);
6043 if (dinfo->cfg.msix.msix_location != 0)
6044 pci_resume_msix(dev);
6045
6046 #ifdef PCI_IOV
6047 if (dinfo->cfg.iov != NULL)
6048 pci_iov_cfg_restore(dev, dinfo);
6049 #endif
6050 }
6051
6052 static void
pci_cfg_save_pcie(device_t dev,struct pci_devinfo * dinfo)6053 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo)
6054 {
6055 #define RREG(n) pci_read_config(dev, pos + (n), 2)
6056 struct pcicfg_pcie *cfg;
6057 int version, pos;
6058
6059 cfg = &dinfo->cfg.pcie;
6060 pos = cfg->pcie_location;
6061
6062 cfg->pcie_flags = RREG(PCIER_FLAGS);
6063
6064 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION;
6065
6066 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL);
6067
6068 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
6069 cfg->pcie_type == PCIEM_TYPE_ENDPOINT ||
6070 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT)
6071 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL);
6072
6073 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
6074 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT &&
6075 (cfg->pcie_flags & PCIEM_FLAGS_SLOT))))
6076 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL);
6077
6078 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
6079 cfg->pcie_type == PCIEM_TYPE_ROOT_EC)
6080 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL);
6081
6082 if (version > 1) {
6083 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2);
6084 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2);
6085 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2);
6086 }
6087 #undef RREG
6088 }
6089
6090 static void
pci_cfg_save_pcix(device_t dev,struct pci_devinfo * dinfo)6091 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo)
6092 {
6093 dinfo->cfg.pcix.pcix_command = pci_read_config(dev,
6094 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2);
6095 }
6096
6097 void
pci_cfg_save(device_t dev,struct pci_devinfo * dinfo,int setstate)6098 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
6099 {
6100 uint32_t cls;
6101 int ps;
6102
6103 /*
6104 * Some drivers apparently write to these registers w/o updating our
6105 * cached copy. No harm happens if we update the copy, so do so here
6106 * so we can restore them. The COMMAND register is modified by the
6107 * bus w/o updating the cache. This should represent the normally
6108 * writable portion of the 'defined' part of type 0/1/2 headers.
6109 */
6110 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
6111 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
6112 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
6113 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
6114 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
6115 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
6116 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
6117 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
6118 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
6119 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
6120 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
6121 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) {
6122 case PCIM_HDRTYPE_NORMAL:
6123 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
6124 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
6125 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
6126 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
6127 break;
6128 case PCIM_HDRTYPE_BRIDGE:
6129 dinfo->cfg.bridge.br_seclat = pci_read_config(dev,
6130 PCIR_SECLAT_1, 1);
6131 dinfo->cfg.bridge.br_subbus = pci_read_config(dev,
6132 PCIR_SUBBUS_1, 1);
6133 dinfo->cfg.bridge.br_secbus = pci_read_config(dev,
6134 PCIR_SECBUS_1, 1);
6135 dinfo->cfg.bridge.br_pribus = pci_read_config(dev,
6136 PCIR_PRIBUS_1, 1);
6137 dinfo->cfg.bridge.br_control = pci_read_config(dev,
6138 PCIR_BRIDGECTL_1, 2);
6139 break;
6140 case PCIM_HDRTYPE_CARDBUS:
6141 dinfo->cfg.bridge.br_seclat = pci_read_config(dev,
6142 PCIR_SECLAT_2, 1);
6143 dinfo->cfg.bridge.br_subbus = pci_read_config(dev,
6144 PCIR_SUBBUS_2, 1);
6145 dinfo->cfg.bridge.br_secbus = pci_read_config(dev,
6146 PCIR_SECBUS_2, 1);
6147 dinfo->cfg.bridge.br_pribus = pci_read_config(dev,
6148 PCIR_PRIBUS_2, 1);
6149 dinfo->cfg.bridge.br_control = pci_read_config(dev,
6150 PCIR_BRIDGECTL_2, 2);
6151 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2);
6152 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2);
6153 break;
6154 }
6155
6156 if (dinfo->cfg.pcie.pcie_location != 0)
6157 pci_cfg_save_pcie(dev, dinfo);
6158
6159 if (dinfo->cfg.pcix.pcix_location != 0)
6160 pci_cfg_save_pcix(dev, dinfo);
6161
6162 #ifdef PCI_IOV
6163 if (dinfo->cfg.iov != NULL)
6164 pci_iov_cfg_save(dev, dinfo);
6165 #endif
6166
6167 /*
6168 * don't set the state for display devices, base peripherals and
6169 * memory devices since bad things happen when they are powered down.
6170 * We should (a) have drivers that can easily detach and (b) use
6171 * generic drivers for these devices so that some device actually
6172 * attaches. We need to make sure that when we implement (a) we don't
6173 * power the device down on a reattach.
6174 */
6175 cls = pci_get_class(dev);
6176 if (!setstate)
6177 return;
6178 switch (pci_do_power_nodriver)
6179 {
6180 case 0: /* NO powerdown at all */
6181 return;
6182 case 1: /* Conservative about what to power down */
6183 if (cls == PCIC_STORAGE)
6184 return;
6185 /*FALLTHROUGH*/
6186 case 2: /* Aggressive about what to power down */
6187 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
6188 cls == PCIC_BASEPERIPH)
6189 return;
6190 /*FALLTHROUGH*/
6191 case 3: /* Power down everything */
6192 break;
6193 }
6194 /*
6195 * PCI spec says we can only go into D3 state from D0 state.
6196 * Transition from D[12] into D0 before going to D3 state.
6197 */
6198 ps = pci_get_powerstate(dev);
6199 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
6200 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
6201 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
6202 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
6203 }
6204
6205 /* Wrapper APIs suitable for device driver use. */
6206 void
pci_save_state(device_t dev)6207 pci_save_state(device_t dev)
6208 {
6209 struct pci_devinfo *dinfo;
6210
6211 dinfo = device_get_ivars(dev);
6212 pci_cfg_save(dev, dinfo, 0);
6213 }
6214
6215 void
pci_restore_state(device_t dev)6216 pci_restore_state(device_t dev)
6217 {
6218 struct pci_devinfo *dinfo;
6219
6220 dinfo = device_get_ivars(dev);
6221 pci_cfg_restore(dev, dinfo);
6222 }
6223
6224 static int
pci_get_id_method(device_t dev,device_t child,enum pci_id_type type,uintptr_t * id)6225 pci_get_id_method(device_t dev, device_t child, enum pci_id_type type,
6226 uintptr_t *id)
6227 {
6228
6229 return (PCIB_GET_ID(device_get_parent(dev), child, type, id));
6230 }
6231
6232 /* Find the upstream port of a given PCI device in a root complex. */
6233 device_t
pci_find_pcie_root_port(device_t dev)6234 pci_find_pcie_root_port(device_t dev)
6235 {
6236 struct pci_devinfo *dinfo;
6237 devclass_t pci_class;
6238 device_t pcib, bus;
6239
6240 pci_class = devclass_find("pci");
6241 KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class,
6242 ("%s: non-pci device %s", __func__, device_get_nameunit(dev)));
6243
6244 /*
6245 * Walk the bridge hierarchy until we find a PCI-e root
6246 * port or a non-PCI device.
6247 */
6248 for (;;) {
6249 bus = device_get_parent(dev);
6250 KASSERT(bus != NULL, ("%s: null parent of %s", __func__,
6251 device_get_nameunit(dev)));
6252
6253 pcib = device_get_parent(bus);
6254 KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__,
6255 device_get_nameunit(bus)));
6256
6257 /*
6258 * pcib's parent must be a PCI bus for this to be a
6259 * PCI-PCI bridge.
6260 */
6261 if (device_get_devclass(device_get_parent(pcib)) != pci_class)
6262 return (NULL);
6263
6264 dinfo = device_get_ivars(pcib);
6265 if (dinfo->cfg.pcie.pcie_location != 0 &&
6266 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT)
6267 return (pcib);
6268
6269 dev = pcib;
6270 }
6271 }
6272
6273 /*
6274 * Wait for pending transactions to complete on a PCI-express function.
6275 *
6276 * The maximum delay is specified in milliseconds in max_delay. Note
6277 * that this function may sleep.
6278 *
6279 * Returns true if the function is idle and false if the timeout is
6280 * exceeded. If dev is not a PCI-express function, this returns true.
6281 */
6282 bool
pcie_wait_for_pending_transactions(device_t dev,u_int max_delay)6283 pcie_wait_for_pending_transactions(device_t dev, u_int max_delay)
6284 {
6285 struct pci_devinfo *dinfo = device_get_ivars(dev);
6286 uint16_t sta;
6287 int cap;
6288
6289 cap = dinfo->cfg.pcie.pcie_location;
6290 if (cap == 0)
6291 return (true);
6292
6293 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2);
6294 while (sta & PCIEM_STA_TRANSACTION_PND) {
6295 if (max_delay == 0)
6296 return (false);
6297
6298 /* Poll once every 100 milliseconds up to the timeout. */
6299 if (max_delay > 100) {
6300 pause_sbt("pcietp", 100 * SBT_1MS, 0, C_HARDCLOCK);
6301 max_delay -= 100;
6302 } else {
6303 pause_sbt("pcietp", max_delay * SBT_1MS, 0,
6304 C_HARDCLOCK);
6305 max_delay = 0;
6306 }
6307 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2);
6308 }
6309
6310 return (true);
6311 }
6312
6313 /*
6314 * Determine the maximum Completion Timeout in microseconds.
6315 *
6316 * For non-PCI-express functions this returns 0.
6317 */
6318 int
pcie_get_max_completion_timeout(device_t dev)6319 pcie_get_max_completion_timeout(device_t dev)
6320 {
6321 struct pci_devinfo *dinfo = device_get_ivars(dev);
6322 int cap;
6323
6324 cap = dinfo->cfg.pcie.pcie_location;
6325 if (cap == 0)
6326 return (0);
6327
6328 /*
6329 * Functions using the 1.x spec use the default timeout range of
6330 * 50 microseconds to 50 milliseconds. Functions that do not
6331 * support programmable timeouts also use this range.
6332 */
6333 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 ||
6334 (pci_read_config(dev, cap + PCIER_DEVICE_CAP2, 4) &
6335 PCIEM_CAP2_COMP_TIMO_RANGES) == 0)
6336 return (50 * 1000);
6337
6338 switch (pci_read_config(dev, cap + PCIER_DEVICE_CTL2, 2) &
6339 PCIEM_CTL2_COMP_TIMO_VAL) {
6340 case PCIEM_CTL2_COMP_TIMO_100US:
6341 return (100);
6342 case PCIEM_CTL2_COMP_TIMO_10MS:
6343 return (10 * 1000);
6344 case PCIEM_CTL2_COMP_TIMO_55MS:
6345 return (55 * 1000);
6346 case PCIEM_CTL2_COMP_TIMO_210MS:
6347 return (210 * 1000);
6348 case PCIEM_CTL2_COMP_TIMO_900MS:
6349 return (900 * 1000);
6350 case PCIEM_CTL2_COMP_TIMO_3500MS:
6351 return (3500 * 1000);
6352 case PCIEM_CTL2_COMP_TIMO_13S:
6353 return (13 * 1000 * 1000);
6354 case PCIEM_CTL2_COMP_TIMO_64S:
6355 return (64 * 1000 * 1000);
6356 default:
6357 return (50 * 1000);
6358 }
6359 }
6360
6361 void
pcie_apei_error(device_t dev,int sev,uint8_t * aerp)6362 pcie_apei_error(device_t dev, int sev, uint8_t *aerp)
6363 {
6364 struct pci_devinfo *dinfo = device_get_ivars(dev);
6365 const char *s;
6366 int aer;
6367 uint32_t r, r1;
6368 uint16_t rs;
6369
6370 if (sev == PCIEM_STA_CORRECTABLE_ERROR)
6371 s = "Correctable";
6372 else if (sev == PCIEM_STA_NON_FATAL_ERROR)
6373 s = "Uncorrectable (Non-Fatal)";
6374 else
6375 s = "Uncorrectable (Fatal)";
6376 device_printf(dev, "%s PCIe error reported by APEI\n", s);
6377 if (aerp) {
6378 if (sev == PCIEM_STA_CORRECTABLE_ERROR) {
6379 r = le32dec(aerp + PCIR_AER_COR_STATUS);
6380 r1 = le32dec(aerp + PCIR_AER_COR_MASK);
6381 } else {
6382 r = le32dec(aerp + PCIR_AER_UC_STATUS);
6383 r1 = le32dec(aerp + PCIR_AER_UC_MASK);
6384 }
6385 device_printf(dev, "status 0x%08x mask 0x%08x", r, r1);
6386 if (sev != PCIEM_STA_CORRECTABLE_ERROR) {
6387 r = le32dec(aerp + PCIR_AER_UC_SEVERITY);
6388 rs = le16dec(aerp + PCIR_AER_CAP_CONTROL);
6389 printf(" severity 0x%08x first %d\n",
6390 r, rs & 0x1f);
6391 } else
6392 printf("\n");
6393 }
6394
6395 /* As kind of recovery just report and clear the error statuses. */
6396 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) {
6397 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4);
6398 if (r != 0) {
6399 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4);
6400 device_printf(dev, "Clearing UC AER errors 0x%08x\n", r);
6401 }
6402
6403 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4);
6404 if (r != 0) {
6405 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4);
6406 device_printf(dev, "Clearing COR AER errors 0x%08x\n", r);
6407 }
6408 }
6409 if (dinfo->cfg.pcie.pcie_location != 0) {
6410 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
6411 PCIER_DEVICE_STA, 2);
6412 if ((rs & (PCIEM_STA_CORRECTABLE_ERROR |
6413 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
6414 PCIEM_STA_UNSUPPORTED_REQ)) != 0) {
6415 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
6416 PCIER_DEVICE_STA, rs, 2);
6417 device_printf(dev, "Clearing PCIe errors 0x%04x\n", rs);
6418 }
6419 }
6420 }
6421
6422 /*
6423 * Perform a Function Level Reset (FLR) on a device.
6424 *
6425 * This function first waits for any pending transactions to complete
6426 * within the timeout specified by max_delay. If transactions are
6427 * still pending, the function will return false without attempting a
6428 * reset.
6429 *
6430 * If dev is not a PCI-express function or does not support FLR, this
6431 * function returns false.
6432 *
6433 * Note that no registers are saved or restored. The caller is
6434 * responsible for saving and restoring any registers including
6435 * PCI-standard registers via pci_save_state() and
6436 * pci_restore_state().
6437 */
6438 bool
pcie_flr(device_t dev,u_int max_delay,bool force)6439 pcie_flr(device_t dev, u_int max_delay, bool force)
6440 {
6441 struct pci_devinfo *dinfo = device_get_ivars(dev);
6442 uint16_t cmd, ctl;
6443 int compl_delay;
6444 int cap;
6445
6446 cap = dinfo->cfg.pcie.pcie_location;
6447 if (cap == 0)
6448 return (false);
6449
6450 if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR))
6451 return (false);
6452
6453 /*
6454 * Disable busmastering to prevent generation of new
6455 * transactions while waiting for the device to go idle. If
6456 * the idle timeout fails, the command register is restored
6457 * which will re-enable busmastering.
6458 */
6459 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
6460 pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2);
6461 if (!pcie_wait_for_pending_transactions(dev, max_delay)) {
6462 if (!force) {
6463 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
6464 return (false);
6465 }
6466 pci_printf(&dinfo->cfg,
6467 "Resetting with transactions pending after %d ms\n",
6468 max_delay);
6469
6470 /*
6471 * Extend the post-FLR delay to cover the maximum
6472 * Completion Timeout delay of anything in flight
6473 * during the FLR delay. Enforce a minimum delay of
6474 * at least 10ms.
6475 */
6476 compl_delay = pcie_get_max_completion_timeout(dev) / 1000;
6477 if (compl_delay < 10)
6478 compl_delay = 10;
6479 } else
6480 compl_delay = 0;
6481
6482 /* Initiate the reset. */
6483 ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
6484 pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl |
6485 PCIEM_CTL_INITIATE_FLR, 2);
6486
6487 /* Wait for 100ms. */
6488 pause_sbt("pcieflr", (100 + compl_delay) * SBT_1MS, 0, C_HARDCLOCK);
6489
6490 if (pci_read_config(dev, cap + PCIER_DEVICE_STA, 2) &
6491 PCIEM_STA_TRANSACTION_PND)
6492 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n");
6493 return (true);
6494 }
6495
6496 /*
6497 * Attempt a power-management reset by cycling the device in/out of D3
6498 * state. PCI spec says we can only go into D3 state from D0 state.
6499 * Transition from D[12] into D0 before going to D3 state.
6500 */
6501 int
pci_power_reset(device_t dev)6502 pci_power_reset(device_t dev)
6503 {
6504 int ps;
6505
6506 ps = pci_get_powerstate(dev);
6507 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
6508 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
6509 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
6510 pci_set_powerstate(dev, ps);
6511 return (0);
6512 }
6513
6514 /*
6515 * Try link drop and retrain of the downstream port of upstream
6516 * switch, for PCIe. According to the PCIe 3.0 spec 6.6.1, this must
6517 * cause Conventional Hot reset of the device in the slot.
6518 * Alternative, for PCIe, could be the secondary bus reset initiatied
6519 * on the upstream switch PCIR_BRIDGECTL_1, bit 6.
6520 */
6521 int
pcie_link_reset(device_t port,int pcie_location)6522 pcie_link_reset(device_t port, int pcie_location)
6523 {
6524 uint16_t v;
6525
6526 v = pci_read_config(port, pcie_location + PCIER_LINK_CTL, 2);
6527 v |= PCIEM_LINK_CTL_LINK_DIS;
6528 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2);
6529 pause_sbt("pcier1", mstosbt(20), 0, 0);
6530 v &= ~PCIEM_LINK_CTL_LINK_DIS;
6531 v |= PCIEM_LINK_CTL_RETRAIN_LINK;
6532 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2);
6533 pause_sbt("pcier2", mstosbt(100), 0, 0); /* 100 ms */
6534 v = pci_read_config(port, pcie_location + PCIER_LINK_STA, 2);
6535 return ((v & PCIEM_LINK_STA_TRAINING) != 0 ? ETIMEDOUT : 0);
6536 }
6537
6538 static int
pci_reset_post(device_t dev,device_t child)6539 pci_reset_post(device_t dev, device_t child)
6540 {
6541
6542 if (dev == device_get_parent(child))
6543 pci_restore_state(child);
6544 return (0);
6545 }
6546
6547 static int
pci_reset_prepare(device_t dev,device_t child)6548 pci_reset_prepare(device_t dev, device_t child)
6549 {
6550
6551 if (dev == device_get_parent(child))
6552 pci_save_state(child);
6553 return (0);
6554 }
6555
6556 static int
pci_reset_child(device_t dev,device_t child,int flags)6557 pci_reset_child(device_t dev, device_t child, int flags)
6558 {
6559 int error;
6560
6561 if (dev == NULL || device_get_parent(child) != dev)
6562 return (0);
6563 if ((flags & DEVF_RESET_DETACH) != 0) {
6564 error = device_get_state(child) == DS_ATTACHED ?
6565 device_detach(child) : 0;
6566 } else {
6567 error = BUS_SUSPEND_CHILD(dev, child);
6568 }
6569 if (error == 0) {
6570 if (!pcie_flr(child, 1000, false)) {
6571 error = BUS_RESET_PREPARE(dev, child);
6572 if (error == 0)
6573 pci_power_reset(child);
6574 BUS_RESET_POST(dev, child);
6575 }
6576 if ((flags & DEVF_RESET_DETACH) != 0)
6577 device_probe_and_attach(child);
6578 else
6579 BUS_RESUME_CHILD(dev, child);
6580 }
6581 return (error);
6582 }
6583
6584 const struct pci_device_table *
pci_match_device(device_t child,const struct pci_device_table * id,size_t nelt)6585 pci_match_device(device_t child, const struct pci_device_table *id, size_t nelt)
6586 {
6587 bool match;
6588 uint16_t vendor, device, subvendor, subdevice, class, subclass, revid;
6589
6590 vendor = pci_get_vendor(child);
6591 device = pci_get_device(child);
6592 subvendor = pci_get_subvendor(child);
6593 subdevice = pci_get_subdevice(child);
6594 class = pci_get_class(child);
6595 subclass = pci_get_subclass(child);
6596 revid = pci_get_revid(child);
6597 while (nelt-- > 0) {
6598 match = true;
6599 if (id->match_flag_vendor)
6600 match &= vendor == id->vendor;
6601 if (id->match_flag_device)
6602 match &= device == id->device;
6603 if (id->match_flag_subvendor)
6604 match &= subvendor == id->subvendor;
6605 if (id->match_flag_subdevice)
6606 match &= subdevice == id->subdevice;
6607 if (id->match_flag_class)
6608 match &= class == id->class_id;
6609 if (id->match_flag_subclass)
6610 match &= subclass == id->subclass;
6611 if (id->match_flag_revid)
6612 match &= revid == id->revid;
6613 if (match)
6614 return (id);
6615 id++;
6616 }
6617 return (NULL);
6618 }
6619
6620 static void
pci_print_faulted_dev_name(const struct pci_devinfo * dinfo)6621 pci_print_faulted_dev_name(const struct pci_devinfo *dinfo)
6622 {
6623 const char *dev_name;
6624 device_t dev;
6625
6626 dev = dinfo->cfg.dev;
6627 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus,
6628 dinfo->cfg.slot, dinfo->cfg.func);
6629 dev_name = device_get_name(dev);
6630 if (dev_name != NULL)
6631 printf(" (%s%d)", dev_name, device_get_unit(dev));
6632 }
6633
6634 void
pci_print_faulted_dev(void)6635 pci_print_faulted_dev(void)
6636 {
6637 struct pci_devinfo *dinfo;
6638 device_t dev;
6639 int aer, i;
6640 uint32_t r1, r2;
6641 uint16_t status;
6642
6643 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
6644 dev = dinfo->cfg.dev;
6645 status = pci_read_config(dev, PCIR_STATUS, 2);
6646 status &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT |
6647 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT |
6648 PCIM_STATUS_SERR | PCIM_STATUS_PERR;
6649 if (status != 0) {
6650 pci_print_faulted_dev_name(dinfo);
6651 printf(" error 0x%04x\n", status);
6652 }
6653 if (dinfo->cfg.pcie.pcie_location != 0) {
6654 status = pci_read_config(dev,
6655 dinfo->cfg.pcie.pcie_location +
6656 PCIER_DEVICE_STA, 2);
6657 if ((status & (PCIEM_STA_CORRECTABLE_ERROR |
6658 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
6659 PCIEM_STA_UNSUPPORTED_REQ)) != 0) {
6660 pci_print_faulted_dev_name(dinfo);
6661 printf(" PCIe DEVCTL 0x%04x DEVSTA 0x%04x\n",
6662 pci_read_config(dev,
6663 dinfo->cfg.pcie.pcie_location +
6664 PCIER_DEVICE_CTL, 2),
6665 status);
6666 }
6667 }
6668 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) {
6669 r1 = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4);
6670 r2 = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4);
6671 if (r1 != 0 || r2 != 0) {
6672 pci_print_faulted_dev_name(dinfo);
6673 printf(" AER UC 0x%08x Mask 0x%08x Svr 0x%08x\n"
6674 " COR 0x%08x Mask 0x%08x Ctl 0x%08x\n",
6675 r1, pci_read_config(dev, aer +
6676 PCIR_AER_UC_MASK, 4),
6677 pci_read_config(dev, aer +
6678 PCIR_AER_UC_SEVERITY, 4),
6679 r2, pci_read_config(dev, aer +
6680 PCIR_AER_COR_MASK, 4),
6681 pci_read_config(dev, aer +
6682 PCIR_AER_CAP_CONTROL, 4));
6683 for (i = 0; i < 4; i++) {
6684 r1 = pci_read_config(dev, aer +
6685 PCIR_AER_HEADER_LOG + i * 4, 4);
6686 printf(" HL%d: 0x%08x\n", i, r1);
6687 }
6688 }
6689 }
6690 }
6691 }
6692
6693 #ifdef DDB
DB_SHOW_COMMAND(pcierr,pci_print_faulted_dev_db)6694 DB_SHOW_COMMAND(pcierr, pci_print_faulted_dev_db)
6695 {
6696
6697 pci_print_faulted_dev();
6698 }
6699
6700 static void
db_clear_pcie_errors(const struct pci_devinfo * dinfo)6701 db_clear_pcie_errors(const struct pci_devinfo *dinfo)
6702 {
6703 device_t dev;
6704 int aer;
6705 uint32_t r;
6706
6707 dev = dinfo->cfg.dev;
6708 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
6709 PCIER_DEVICE_STA, 2);
6710 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
6711 PCIER_DEVICE_STA, r, 2);
6712
6713 if (pci_find_extcap(dev, PCIZ_AER, &aer) != 0)
6714 return;
6715 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4);
6716 if (r != 0)
6717 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4);
6718 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4);
6719 if (r != 0)
6720 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4);
6721 }
6722
DB_COMMAND(pci_clearerr,db_pci_clearerr)6723 DB_COMMAND(pci_clearerr, db_pci_clearerr)
6724 {
6725 struct pci_devinfo *dinfo;
6726 device_t dev;
6727 uint16_t status, status1;
6728
6729 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
6730 dev = dinfo->cfg.dev;
6731 status1 = status = pci_read_config(dev, PCIR_STATUS, 2);
6732 status1 &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT |
6733 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT |
6734 PCIM_STATUS_SERR | PCIM_STATUS_PERR;
6735 if (status1 != 0) {
6736 status &= ~status1;
6737 pci_write_config(dev, PCIR_STATUS, status, 2);
6738 }
6739 if (dinfo->cfg.pcie.pcie_location != 0)
6740 db_clear_pcie_errors(dinfo);
6741 }
6742 }
6743 #endif
6744