1 /*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: stable/9/sys/dev/pci/pcivar.h 303255 2016-07-24 05:24:10Z jhb $
27 *
28 */
29
30 #ifndef _PCIVAR_H_
31 #define _PCIVAR_H_
32
33 #include <sys/queue.h>
34
35 /* some PCI bus constants */
36 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
37 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
38 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
39
40 typedef uint64_t pci_addr_t;
41
42 /* Interesting values for PCI power management */
43 struct pcicfg_pp {
44 uint16_t pp_cap; /* PCI power management capabilities */
45 uint8_t pp_status; /* conf. space addr. of PM control/status reg */
46 uint8_t pp_bse; /* conf. space addr. of PM BSE reg */
47 uint8_t pp_data; /* conf. space addr. of PM data reg */
48 };
49
50 struct pci_map {
51 pci_addr_t pm_value; /* Raw BAR value */
52 pci_addr_t pm_size;
53 uint8_t pm_reg;
54 STAILQ_ENTRY(pci_map) pm_link;
55 };
56
57 struct vpd_readonly {
58 char keyword[2];
59 char *value;
60 int len;
61 };
62
63 struct vpd_write {
64 char keyword[2];
65 char *value;
66 int start;
67 int len;
68 };
69
70 struct pcicfg_vpd {
71 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */
72 char vpd_cached;
73 char *vpd_ident; /* string identifier */
74 int vpd_rocnt;
75 struct vpd_readonly *vpd_ros;
76 int vpd_wcnt;
77 struct vpd_write *vpd_w;
78 };
79
80 /* Interesting values for PCI MSI */
81 struct pcicfg_msi {
82 uint16_t msi_ctrl; /* Message Control */
83 uint8_t msi_location; /* Offset of MSI capability registers. */
84 uint8_t msi_msgnum; /* Number of messages */
85 int msi_alloc; /* Number of allocated messages. */
86 uint64_t msi_addr; /* Contents of address register. */
87 uint16_t msi_data; /* Contents of data register. */
88 u_int msi_handlers;
89 };
90
91 /* Interesting values for PCI MSI-X */
92 struct msix_vector {
93 uint64_t mv_address; /* Contents of address register. */
94 uint32_t mv_data; /* Contents of data register. */
95 int mv_irq;
96 };
97
98 struct msix_table_entry {
99 u_int mte_vector; /* 1-based index into msix_vectors array. */
100 u_int mte_handlers;
101 };
102
103 struct pcicfg_msix {
104 uint16_t msix_ctrl; /* Message Control */
105 uint16_t msix_msgnum; /* Number of messages */
106 uint8_t msix_location; /* Offset of MSI-X capability registers. */
107 uint8_t msix_table_bar; /* BAR containing vector table. */
108 uint8_t msix_pba_bar; /* BAR containing PBA. */
109 uint32_t msix_table_offset;
110 uint32_t msix_pba_offset;
111 int msix_alloc; /* Number of allocated vectors. */
112 int msix_table_len; /* Length of virtual table. */
113 struct msix_table_entry *msix_table; /* Virtual table. */
114 struct msix_vector *msix_vectors; /* Array of allocated vectors. */
115 struct resource *msix_table_res; /* Resource containing vector table. */
116 struct resource *msix_pba_res; /* Resource containing PBA. */
117 };
118
119 /* Interesting values for HyperTransport */
120 struct pcicfg_ht {
121 uint8_t ht_slave; /* Non-zero if device is an HT slave. */
122 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */
123 uint16_t ht_msictrl; /* MSI mapping control */
124 uint64_t ht_msiaddr; /* MSI mapping base address */
125 };
126
127 /* Interesting values for PCI-express */
128 struct pcicfg_pcie {
129 uint8_t pcie_location; /* Offset of PCI-e capability registers. */
130 uint8_t pcie_type; /* Device type. */
131 };
132
133 /* config header information common to all header types */
134 typedef struct pcicfg {
135 struct device *dev; /* device which owns this */
136
137 STAILQ_HEAD(, pci_map) maps; /* BARs */
138
139 uint16_t subvendor; /* card vendor ID */
140 uint16_t subdevice; /* card device ID, assigned by card vendor */
141 uint16_t vendor; /* chip vendor ID */
142 uint16_t device; /* chip device ID, assigned by chip vendor */
143
144 uint16_t cmdreg; /* disable/enable chip and PCI options */
145 uint16_t statreg; /* supported PCI features and error state */
146
147 uint8_t baseclass; /* chip PCI class */
148 uint8_t subclass; /* chip PCI subclass */
149 uint8_t progif; /* chip PCI programming interface */
150 uint8_t revid; /* chip revision ID */
151
152 uint8_t hdrtype; /* chip config header type */
153 uint8_t cachelnsz; /* cache line size in 4byte units */
154 uint8_t intpin; /* PCI interrupt pin */
155 uint8_t intline; /* interrupt line (IRQ for PC arch) */
156
157 uint8_t mingnt; /* min. useful bus grant time in 250ns units */
158 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */
159 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */
160
161 uint8_t mfdev; /* multi-function device (from hdrtype reg) */
162 uint8_t nummaps; /* actual number of PCI maps used */
163
164 uint32_t domain; /* PCI domain */
165 uint8_t bus; /* config space bus address */
166 uint8_t slot; /* config space slot address */
167 uint8_t func; /* config space function number */
168
169 struct pcicfg_pp pp; /* Power management */
170 struct pcicfg_vpd vpd; /* Vital product data */
171 struct pcicfg_msi msi; /* PCI MSI */
172 struct pcicfg_msix msix; /* PCI MSI-X */
173 struct pcicfg_ht ht; /* HyperTransport */
174 struct pcicfg_pcie pcie; /* PCI Express */
175 } pcicfgregs;
176
177 /* additional type 1 device config header information (PCI to PCI bridge) */
178
179 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
180 #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff)
181 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff)
182 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff)
183
184 typedef struct {
185 pci_addr_t pmembase; /* base address of prefetchable memory */
186 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
187 uint32_t membase; /* base address of memory window */
188 uint32_t memlimit; /* topmost address of memory window */
189 uint32_t iobase; /* base address of port window */
190 uint32_t iolimit; /* topmost address of port window */
191 uint16_t secstat; /* secondary bus status register */
192 uint16_t bridgectl; /* bridge control register */
193 uint8_t seclat; /* CardBus latency timer */
194 } pcih1cfgregs;
195
196 /* additional type 2 device config header information (CardBus bridge) */
197
198 typedef struct {
199 uint32_t membase0; /* base address of memory window */
200 uint32_t memlimit0; /* topmost address of memory window */
201 uint32_t membase1; /* base address of memory window */
202 uint32_t memlimit1; /* topmost address of memory window */
203 uint32_t iobase0; /* base address of port window */
204 uint32_t iolimit0; /* topmost address of port window */
205 uint32_t iobase1; /* base address of port window */
206 uint32_t iolimit1; /* topmost address of port window */
207 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
208 uint16_t secstat; /* secondary bus status register */
209 uint16_t bridgectl; /* bridge control register */
210 uint8_t seclat; /* CardBus latency timer */
211 } pcih2cfgregs;
212
213 extern uint32_t pci_numdevs;
214
215 /* Only if the prerequisites are present */
216 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
217 struct pci_devinfo {
218 STAILQ_ENTRY(pci_devinfo) pci_links;
219 struct resource_list resources;
220 pcicfgregs cfg;
221 struct pci_conf conf;
222 };
223 #endif
224
225 #ifdef _SYS_BUS_H_
226
227 #include "pci_if.h"
228
229 enum pci_device_ivars {
230 PCI_IVAR_SUBVENDOR,
231 PCI_IVAR_SUBDEVICE,
232 PCI_IVAR_VENDOR,
233 PCI_IVAR_DEVICE,
234 PCI_IVAR_DEVID,
235 PCI_IVAR_CLASS,
236 PCI_IVAR_SUBCLASS,
237 PCI_IVAR_PROGIF,
238 PCI_IVAR_REVID,
239 PCI_IVAR_INTPIN,
240 PCI_IVAR_IRQ,
241 PCI_IVAR_DOMAIN,
242 PCI_IVAR_BUS,
243 PCI_IVAR_SLOT,
244 PCI_IVAR_FUNCTION,
245 PCI_IVAR_ETHADDR,
246 PCI_IVAR_CMDREG,
247 PCI_IVAR_CACHELNSZ,
248 PCI_IVAR_MINGNT,
249 PCI_IVAR_MAXLAT,
250 PCI_IVAR_LATTIMER
251 };
252
253 /*
254 * Simplified accessors for pci devices
255 */
256 #define PCI_ACCESSOR(var, ivar, type) \
257 __BUS_ACCESSOR(pci, var, PCI, ivar, type)
258
PCI_ACCESSOR(subvendor,SUBVENDOR,uint16_t)259 PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t)
260 PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t)
261 PCI_ACCESSOR(vendor, VENDOR, uint16_t)
262 PCI_ACCESSOR(device, DEVICE, uint16_t)
263 PCI_ACCESSOR(devid, DEVID, uint32_t)
264 PCI_ACCESSOR(class, CLASS, uint8_t)
265 PCI_ACCESSOR(subclass, SUBCLASS, uint8_t)
266 PCI_ACCESSOR(progif, PROGIF, uint8_t)
267 PCI_ACCESSOR(revid, REVID, uint8_t)
268 PCI_ACCESSOR(intpin, INTPIN, uint8_t)
269 PCI_ACCESSOR(irq, IRQ, uint8_t)
270 PCI_ACCESSOR(domain, DOMAIN, uint32_t)
271 PCI_ACCESSOR(bus, BUS, uint8_t)
272 PCI_ACCESSOR(slot, SLOT, uint8_t)
273 PCI_ACCESSOR(function, FUNCTION, uint8_t)
274 PCI_ACCESSOR(ether, ETHADDR, uint8_t *)
275 PCI_ACCESSOR(cmdreg, CMDREG, uint8_t)
276 PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t)
277 PCI_ACCESSOR(mingnt, MINGNT, uint8_t)
278 PCI_ACCESSOR(maxlat, MAXLAT, uint8_t)
279 PCI_ACCESSOR(lattimer, LATTIMER, uint8_t)
280
281 #undef PCI_ACCESSOR
282
283 /*
284 * Operations on configuration space.
285 */
286 static __inline uint32_t
287 pci_read_config(device_t dev, int reg, int width)
288 {
289 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
290 }
291
292 static __inline void
pci_write_config(device_t dev,int reg,uint32_t val,int width)293 pci_write_config(device_t dev, int reg, uint32_t val, int width)
294 {
295 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
296 }
297
298 /*
299 * Ivars for pci bridges.
300 */
301
302 /*typedef enum pci_device_ivars pcib_device_ivars;*/
303 enum pcib_device_ivars {
304 PCIB_IVAR_DOMAIN,
305 PCIB_IVAR_BUS
306 };
307
308 #define PCIB_ACCESSOR(var, ivar, type) \
309 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
310
PCIB_ACCESSOR(domain,DOMAIN,uint32_t)311 PCIB_ACCESSOR(domain, DOMAIN, uint32_t)
312 PCIB_ACCESSOR(bus, BUS, uint32_t)
313
314 #undef PCIB_ACCESSOR
315
316 /*
317 * PCI interrupt validation. Invalid interrupt values such as 0 or 128
318 * on i386 or other platforms should be mapped out in the MD pcireadconf
319 * code and not here, since the only MI invalid IRQ is 255.
320 */
321 #define PCI_INVALID_IRQ 255
322 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ)
323
324 /*
325 * Convenience functions.
326 *
327 * These should be used in preference to manually manipulating
328 * configuration space.
329 */
330 static __inline int
331 pci_enable_busmaster(device_t dev)
332 {
333 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
334 }
335
336 static __inline int
pci_disable_busmaster(device_t dev)337 pci_disable_busmaster(device_t dev)
338 {
339 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
340 }
341
342 static __inline int
pci_enable_io(device_t dev,int space)343 pci_enable_io(device_t dev, int space)
344 {
345 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
346 }
347
348 static __inline int
pci_disable_io(device_t dev,int space)349 pci_disable_io(device_t dev, int space)
350 {
351 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
352 }
353
354 static __inline int
pci_get_vpd_ident(device_t dev,const char ** identptr)355 pci_get_vpd_ident(device_t dev, const char **identptr)
356 {
357 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr));
358 }
359
360 static __inline int
pci_get_vpd_readonly(device_t dev,const char * kw,const char ** identptr)361 pci_get_vpd_readonly(device_t dev, const char *kw, const char **identptr)
362 {
363 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr));
364 }
365
366 /*
367 * Check if the address range falls within the VGA defined address range(s)
368 */
369 static __inline int
pci_is_vga_ioport_range(u_long start,u_long end)370 pci_is_vga_ioport_range(u_long start, u_long end)
371 {
372
373 return (((start >= 0x3b0 && end <= 0x3bb) ||
374 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
375 }
376
377 static __inline int
pci_is_vga_memory_range(u_long start,u_long end)378 pci_is_vga_memory_range(u_long start, u_long end)
379 {
380
381 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
382 }
383
384 /*
385 * PCI power states are as defined by ACPI:
386 *
387 * D0 State in which device is on and running. It is receiving full
388 * power from the system and delivering full functionality to the user.
389 * D1 Class-specific low-power state in which device context may or may not
390 * be lost. Buses in D1 cannot do anything to the bus that would force
391 * devices on that bus to lose context.
392 * D2 Class-specific low-power state in which device context may or may
393 * not be lost. Attains greater power savings than D1. Buses in D2
394 * can cause devices on that bus to lose some context. Devices in D2
395 * must be prepared for the bus to be in D2 or higher.
396 * D3 State in which the device is off and not running. Device context is
397 * lost. Power can be removed from the device.
398 */
399 #define PCI_POWERSTATE_D0 0
400 #define PCI_POWERSTATE_D1 1
401 #define PCI_POWERSTATE_D2 2
402 #define PCI_POWERSTATE_D3 3
403 #define PCI_POWERSTATE_UNKNOWN -1
404
405 static __inline int
pci_set_powerstate(device_t dev,int state)406 pci_set_powerstate(device_t dev, int state)
407 {
408 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
409 }
410
411 static __inline int
pci_get_powerstate(device_t dev)412 pci_get_powerstate(device_t dev)
413 {
414 return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
415 }
416
417 static __inline int
pci_find_cap(device_t dev,int capability,int * capreg)418 pci_find_cap(device_t dev, int capability, int *capreg)
419 {
420 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg));
421 }
422
423 static __inline int
pci_find_extcap(device_t dev,int capability,int * capreg)424 pci_find_extcap(device_t dev, int capability, int *capreg)
425 {
426 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg));
427 }
428
429 static __inline int
pci_alloc_msi(device_t dev,int * count)430 pci_alloc_msi(device_t dev, int *count)
431 {
432 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count));
433 }
434
435 static __inline int
pci_alloc_msix(device_t dev,int * count)436 pci_alloc_msix(device_t dev, int *count)
437 {
438 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count));
439 }
440
441 static __inline int
pci_remap_msix(device_t dev,int count,const u_int * vectors)442 pci_remap_msix(device_t dev, int count, const u_int *vectors)
443 {
444 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors));
445 }
446
447 static __inline int
pci_release_msi(device_t dev)448 pci_release_msi(device_t dev)
449 {
450 return (PCI_RELEASE_MSI(device_get_parent(dev), dev));
451 }
452
453 static __inline int
pci_msi_count(device_t dev)454 pci_msi_count(device_t dev)
455 {
456 return (PCI_MSI_COUNT(device_get_parent(dev), dev));
457 }
458
459 static __inline int
pci_msix_count(device_t dev)460 pci_msix_count(device_t dev)
461 {
462 return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
463 }
464
465 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
466 device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
467 device_t pci_find_device(uint16_t, uint16_t);
468 device_t pci_find_class(uint8_t class, uint8_t subclass);
469
470 /* Can be used by drivers to manage the MSI-X table. */
471 int pci_pending_msix(device_t dev, u_int index);
472
473 int pci_msi_device_blacklisted(device_t dev);
474 int pci_msix_device_blacklisted(device_t dev);
475
476 void pci_ht_map_msi(device_t dev, uint64_t addr);
477
478 device_t pci_find_pcie_root_port(device_t dev);
479 int pci_get_max_payload(device_t dev);
480 int pci_get_max_read_req(device_t dev);
481 void pci_restore_state(device_t dev);
482 void pci_save_state(device_t dev);
483 int pci_set_max_read_req(device_t dev, int size);
484 uint32_t pcie_read_config(device_t dev, int reg, int width);
485 void pcie_write_config(device_t dev, int reg, uint32_t value, int width);
486 uint32_t pcie_adjust_config(device_t dev, int reg, uint32_t mask,
487 uint32_t value, int width);
488
489 #endif /* _SYS_BUS_H_ */
490
491 /*
492 * cdev switch for control device, initialised in generic PCI code
493 */
494 extern struct cdevsw pcicdev;
495
496 /*
497 * List of all PCI devices, generation count for the list.
498 */
499 STAILQ_HEAD(devlist, pci_devinfo);
500
501 extern struct devlist pci_devq;
502 extern uint32_t pci_generation;
503
504 struct pci_map *pci_find_bar(device_t dev, int reg);
505 int pci_bar_enabled(device_t dev, struct pci_map *pm);
506 struct pcicfg_vpd *pci_fetch_vpd_list(device_t dev);
507
508 #define VGA_PCI_BIOS_SHADOW_ADDR 0xC0000
509 #define VGA_PCI_BIOS_SHADOW_SIZE 131072
510
511 int vga_pci_is_boot_display(device_t dev);
512 void * vga_pci_map_bios(device_t dev, size_t *size);
513 void vga_pci_unmap_bios(device_t dev, void *bios);
514
515 #endif /* _PCIVAR_H_ */
516