1 /*-
2 * Copyright (c) 2013-2015 Sandvine Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 #include "opt_bus.h"
29
30 #include <sys/param.h>
31 #include <sys/conf.h>
32 #include <sys/kernel.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/fcntl.h>
36 #include <sys/ioccom.h>
37 #include <sys/iov.h>
38 #include <sys/linker.h>
39 #include <sys/lock.h>
40 #include <sys/malloc.h>
41 #include <sys/module.h>
42 #include <sys/mutex.h>
43 #include <sys/pciio.h>
44 #include <sys/queue.h>
45 #include <sys/rman.h>
46 #include <sys/sysctl.h>
47
48 #include <machine/bus.h>
49 #include <machine/stdarg.h>
50
51 #include <sys/nv.h>
52 #include <sys/iov_schema.h>
53
54 #include <dev/pci/pcireg.h>
55 #include <dev/pci/pcivar.h>
56 #include <dev/pci/pci_iov.h>
57 #include <dev/pci/pci_private.h>
58 #include <dev/pci/pci_iov_private.h>
59 #include <dev/pci/schema_private.h>
60
61 #include "pcib_if.h"
62
63 static MALLOC_DEFINE(M_SRIOV, "sr_iov", "PCI SR-IOV allocations");
64
65 static d_ioctl_t pci_iov_ioctl;
66
67 static struct cdevsw iov_cdevsw = {
68 .d_version = D_VERSION,
69 .d_name = "iov",
70 .d_ioctl = pci_iov_ioctl
71 };
72
73 SYSCTL_DECL(_hw_pci);
74
75 /*
76 * The maximum amount of memory we will allocate for user configuration of an
77 * SR-IOV device. 1MB ought to be enough for anyone, but leave this
78 * configurable just in case.
79 */
80 static u_long pci_iov_max_config = 1024 * 1024;
81 SYSCTL_ULONG(_hw_pci, OID_AUTO, iov_max_config, CTLFLAG_RWTUN,
82 &pci_iov_max_config, 0, "Maximum allowed size of SR-IOV configuration.");
83
84 #define IOV_READ(d, r, w) \
85 pci_read_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, w)
86
87 #define IOV_WRITE(d, r, v, w) \
88 pci_write_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, v, w)
89
90 static nvlist_t *pci_iov_build_schema(nvlist_t **pf_schema,
91 nvlist_t **vf_schema);
92 static void pci_iov_build_pf_schema(nvlist_t *schema,
93 nvlist_t **driver_schema);
94 static void pci_iov_build_vf_schema(nvlist_t *schema,
95 nvlist_t **driver_schema);
96 static int pci_iov_delete_iov_children(struct pci_devinfo *dinfo);
97 static nvlist_t *pci_iov_get_pf_subsystem_schema(void);
98 static nvlist_t *pci_iov_get_vf_subsystem_schema(void);
99
100 int
pci_iov_attach_name(device_t dev,struct nvlist * pf_schema,struct nvlist * vf_schema,const char * fmt,...)101 pci_iov_attach_name(device_t dev, struct nvlist *pf_schema,
102 struct nvlist *vf_schema, const char *fmt, ...)
103 {
104 char buf[NAME_MAX + 1];
105 va_list ap;
106
107 va_start(ap, fmt);
108 vsnprintf(buf, sizeof(buf), fmt, ap);
109 va_end(ap);
110 return (PCI_IOV_ATTACH(device_get_parent(dev), dev, pf_schema,
111 vf_schema, buf));
112 }
113
114 int
pci_iov_attach_method(device_t bus,device_t dev,nvlist_t * pf_schema,nvlist_t * vf_schema,const char * name)115 pci_iov_attach_method(device_t bus, device_t dev, nvlist_t *pf_schema,
116 nvlist_t *vf_schema, const char *name)
117 {
118 struct pci_devinfo *dinfo;
119 struct pcicfg_iov *iov;
120 nvlist_t *schema;
121 uint32_t version;
122 int error;
123 int iov_pos;
124
125 dinfo = device_get_ivars(dev);
126 schema = NULL;
127
128 error = pci_find_extcap(dev, PCIZ_SRIOV, &iov_pos);
129
130 if (error != 0)
131 return (error);
132
133 version = pci_read_config(dev, iov_pos, 4);
134 if (PCI_EXTCAP_VER(version) != 1) {
135 if (bootverbose)
136 device_printf(dev,
137 "Unsupported version of SR-IOV (%d) detected\n",
138 PCI_EXTCAP_VER(version));
139
140 return (ENXIO);
141 }
142
143 iov = malloc(sizeof(*dinfo->cfg.iov), M_SRIOV, M_WAITOK | M_ZERO);
144
145 mtx_lock(&Giant);
146 if (dinfo->cfg.iov != NULL) {
147 error = EBUSY;
148 goto cleanup;
149 }
150 iov->iov_pf = dev;
151 iov->iov_pos = iov_pos;
152
153 schema = pci_iov_build_schema(&pf_schema, &vf_schema);
154 if (schema == NULL) {
155 error = ENOMEM;
156 goto cleanup;
157 }
158
159 error = pci_iov_validate_schema(schema);
160 if (error != 0)
161 goto cleanup;
162 iov->iov_schema = schema;
163
164 iov->iov_cdev = make_dev(&iov_cdevsw, device_get_unit(dev),
165 UID_ROOT, GID_WHEEL, 0600, "iov/%s", name);
166
167 if (iov->iov_cdev == NULL) {
168 error = ENOMEM;
169 goto cleanup;
170 }
171
172 dinfo->cfg.iov = iov;
173 iov->iov_cdev->si_drv1 = dinfo;
174 mtx_unlock(&Giant);
175
176 return (0);
177
178 cleanup:
179 nvlist_destroy(schema);
180 nvlist_destroy(pf_schema);
181 nvlist_destroy(vf_schema);
182 free(iov, M_SRIOV);
183 mtx_unlock(&Giant);
184 return (error);
185 }
186
187 int
pci_iov_detach_method(device_t bus,device_t dev)188 pci_iov_detach_method(device_t bus, device_t dev)
189 {
190 struct pci_devinfo *dinfo;
191 struct pcicfg_iov *iov;
192 int error;
193
194 mtx_lock(&Giant);
195 dinfo = device_get_ivars(dev);
196 iov = dinfo->cfg.iov;
197
198 if (iov == NULL) {
199 mtx_unlock(&Giant);
200 return (0);
201 }
202
203 if ((iov->iov_flags & IOV_BUSY) != 0) {
204 mtx_unlock(&Giant);
205 return (EBUSY);
206 }
207
208 error = pci_iov_delete_iov_children(dinfo);
209 if (error != 0) {
210 mtx_unlock(&Giant);
211 return (error);
212 }
213
214 dinfo->cfg.iov = NULL;
215
216 if (iov->iov_cdev) {
217 destroy_dev(iov->iov_cdev);
218 iov->iov_cdev = NULL;
219 }
220 nvlist_destroy(iov->iov_schema);
221
222 free(iov, M_SRIOV);
223 mtx_unlock(&Giant);
224
225 return (0);
226 }
227
228 static nvlist_t *
pci_iov_build_schema(nvlist_t ** pf,nvlist_t ** vf)229 pci_iov_build_schema(nvlist_t **pf, nvlist_t **vf)
230 {
231 nvlist_t *schema, *pf_driver, *vf_driver;
232
233 /* We always take ownership of the schemas. */
234 pf_driver = *pf;
235 *pf = NULL;
236 vf_driver = *vf;
237 *vf = NULL;
238
239 schema = pci_iov_schema_alloc_node();
240 if (schema == NULL)
241 goto cleanup;
242
243 pci_iov_build_pf_schema(schema, &pf_driver);
244 pci_iov_build_vf_schema(schema, &vf_driver);
245
246 if (nvlist_error(schema) != 0)
247 goto cleanup;
248
249 return (schema);
250
251 cleanup:
252 nvlist_destroy(schema);
253 nvlist_destroy(pf_driver);
254 nvlist_destroy(vf_driver);
255 return (NULL);
256 }
257
258 static void
pci_iov_build_pf_schema(nvlist_t * schema,nvlist_t ** driver_schema)259 pci_iov_build_pf_schema(nvlist_t *schema, nvlist_t **driver_schema)
260 {
261 nvlist_t *pf_schema, *iov_schema;
262
263 pf_schema = pci_iov_schema_alloc_node();
264 if (pf_schema == NULL) {
265 nvlist_set_error(schema, ENOMEM);
266 return;
267 }
268
269 iov_schema = pci_iov_get_pf_subsystem_schema();
270
271 /*
272 * Note that if either *driver_schema or iov_schema is NULL, then
273 * nvlist_move_nvlist will put the schema in the error state and
274 * SR-IOV will fail to initialize later, so we don't have to explicitly
275 * handle that case.
276 */
277 nvlist_move_nvlist(pf_schema, DRIVER_CONFIG_NAME, *driver_schema);
278 nvlist_move_nvlist(pf_schema, IOV_CONFIG_NAME, iov_schema);
279 nvlist_move_nvlist(schema, PF_CONFIG_NAME, pf_schema);
280 *driver_schema = NULL;
281 }
282
283 static void
pci_iov_build_vf_schema(nvlist_t * schema,nvlist_t ** driver_schema)284 pci_iov_build_vf_schema(nvlist_t *schema, nvlist_t **driver_schema)
285 {
286 nvlist_t *vf_schema, *iov_schema;
287
288 vf_schema = pci_iov_schema_alloc_node();
289 if (vf_schema == NULL) {
290 nvlist_set_error(schema, ENOMEM);
291 return;
292 }
293
294 iov_schema = pci_iov_get_vf_subsystem_schema();
295
296 /*
297 * Note that if either *driver_schema or iov_schema is NULL, then
298 * nvlist_move_nvlist will put the schema in the error state and
299 * SR-IOV will fail to initialize later, so we don't have to explicitly
300 * handle that case.
301 */
302 nvlist_move_nvlist(vf_schema, DRIVER_CONFIG_NAME, *driver_schema);
303 nvlist_move_nvlist(vf_schema, IOV_CONFIG_NAME, iov_schema);
304 nvlist_move_nvlist(schema, VF_SCHEMA_NAME, vf_schema);
305 *driver_schema = NULL;
306 }
307
308 static nvlist_t *
pci_iov_get_pf_subsystem_schema(void)309 pci_iov_get_pf_subsystem_schema(void)
310 {
311 nvlist_t *pf;
312
313 pf = pci_iov_schema_alloc_node();
314 if (pf == NULL)
315 return (NULL);
316
317 pci_iov_schema_add_uint16(pf, "num_vfs", IOV_SCHEMA_REQUIRED, -1);
318 pci_iov_schema_add_string(pf, "device", IOV_SCHEMA_REQUIRED, NULL);
319
320 return (pf);
321 }
322
323 static nvlist_t *
pci_iov_get_vf_subsystem_schema(void)324 pci_iov_get_vf_subsystem_schema(void)
325 {
326 nvlist_t *vf;
327
328 vf = pci_iov_schema_alloc_node();
329 if (vf == NULL)
330 return (NULL);
331
332 pci_iov_schema_add_bool(vf, "passthrough", IOV_SCHEMA_HASDEFAULT, 0);
333
334 return (vf);
335 }
336
337 static int
pci_iov_alloc_bar(struct pci_devinfo * dinfo,int bar,pci_addr_t bar_shift)338 pci_iov_alloc_bar(struct pci_devinfo *dinfo, int bar, pci_addr_t bar_shift)
339 {
340 struct resource *res;
341 struct pcicfg_iov *iov;
342 device_t dev, bus;
343 rman_res_t start, end;
344 pci_addr_t bar_size;
345 int rid;
346
347 iov = dinfo->cfg.iov;
348 dev = dinfo->cfg.dev;
349 bus = device_get_parent(dev);
350 rid = iov->iov_pos + PCIR_SRIOV_BAR(bar);
351 bar_size = 1 << bar_shift;
352
353 res = pci_alloc_multi_resource(bus, dev, SYS_RES_MEMORY, &rid, 0,
354 ~0, 1, iov->iov_num_vfs, RF_ACTIVE);
355
356 if (res == NULL)
357 return (ENXIO);
358
359 iov->iov_bar[bar].res = res;
360 iov->iov_bar[bar].bar_size = bar_size;
361 iov->iov_bar[bar].bar_shift = bar_shift;
362
363 start = rman_get_start(res);
364 end = rman_get_end(res);
365 return (rman_manage_region(&iov->rman, start, end));
366 }
367
368 static void
pci_iov_add_bars(struct pcicfg_iov * iov,struct pci_devinfo * dinfo)369 pci_iov_add_bars(struct pcicfg_iov *iov, struct pci_devinfo *dinfo)
370 {
371 struct pci_iov_bar *bar;
372 uint64_t bar_start;
373 int i;
374
375 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
376 bar = &iov->iov_bar[i];
377 if (bar->res != NULL) {
378 bar_start = rman_get_start(bar->res) +
379 dinfo->cfg.vf.index * bar->bar_size;
380
381 pci_add_bar(dinfo->cfg.dev, PCIR_BAR(i), bar_start,
382 bar->bar_shift);
383 }
384 }
385 }
386
387 static int
pci_iov_parse_config(struct pcicfg_iov * iov,struct pci_iov_arg * arg,nvlist_t ** ret)388 pci_iov_parse_config(struct pcicfg_iov *iov, struct pci_iov_arg *arg,
389 nvlist_t **ret)
390 {
391 void *packed_config;
392 nvlist_t *config;
393 int error;
394
395 config = NULL;
396 packed_config = NULL;
397
398 if (arg->len > pci_iov_max_config) {
399 error = EMSGSIZE;
400 goto out;
401 }
402
403 packed_config = malloc(arg->len, M_SRIOV, M_WAITOK);
404
405 error = copyin(arg->config, packed_config, arg->len);
406 if (error != 0)
407 goto out;
408
409 config = nvlist_unpack(packed_config, arg->len, NV_FLAG_IGNORE_CASE);
410 if (config == NULL) {
411 error = EINVAL;
412 goto out;
413 }
414
415 error = pci_iov_schema_validate_config(iov->iov_schema, config);
416 if (error != 0)
417 goto out;
418
419 error = nvlist_error(config);
420 if (error != 0)
421 goto out;
422
423 *ret = config;
424 config = NULL;
425
426 out:
427 nvlist_destroy(config);
428 free(packed_config, M_SRIOV);
429 return (error);
430 }
431
432 /*
433 * Set the ARI_EN bit in the lowest-numbered PCI function with the SR-IOV
434 * capability. This bit is only writeable on the lowest-numbered PF but
435 * affects all PFs on the device.
436 */
437 static int
pci_iov_set_ari(device_t bus)438 pci_iov_set_ari(device_t bus)
439 {
440 device_t lowest;
441 device_t *devlist;
442 int i, error, devcount, lowest_func, lowest_pos, iov_pos, dev_func;
443 uint16_t iov_ctl;
444
445 /* If ARI is disabled on the downstream port there is nothing to do. */
446 if (!PCIB_ARI_ENABLED(device_get_parent(bus)))
447 return (0);
448
449 error = device_get_children(bus, &devlist, &devcount);
450
451 if (error != 0)
452 return (error);
453
454 lowest = NULL;
455 for (i = 0; i < devcount; i++) {
456 if (pci_find_extcap(devlist[i], PCIZ_SRIOV, &iov_pos) == 0) {
457 dev_func = pci_get_function(devlist[i]);
458 if (lowest == NULL || dev_func < lowest_func) {
459 lowest = devlist[i];
460 lowest_func = dev_func;
461 lowest_pos = iov_pos;
462 }
463 }
464 }
465 free(devlist, M_TEMP);
466
467 /*
468 * If we called this function some device must have the SR-IOV
469 * capability.
470 */
471 KASSERT(lowest != NULL,
472 ("Could not find child of %s with SR-IOV capability",
473 device_get_nameunit(bus)));
474
475 iov_ctl = pci_read_config(lowest, lowest_pos + PCIR_SRIOV_CTL, 2);
476 iov_ctl |= PCIM_SRIOV_ARI_EN;
477 pci_write_config(lowest, lowest_pos + PCIR_SRIOV_CTL, iov_ctl, 2);
478 if ((pci_read_config(lowest, lowest_pos + PCIR_SRIOV_CTL, 2) &
479 PCIM_SRIOV_ARI_EN) == 0) {
480 device_printf(lowest, "failed to enable ARI\n");
481 return (ENXIO);
482 }
483 return (0);
484 }
485
486 static int
pci_iov_config_page_size(struct pci_devinfo * dinfo)487 pci_iov_config_page_size(struct pci_devinfo *dinfo)
488 {
489 uint32_t page_cap, page_size;
490
491 page_cap = IOV_READ(dinfo, PCIR_SRIOV_PAGE_CAP, 4);
492
493 /*
494 * If the system page size is less than the smallest SR-IOV page size
495 * then round up to the smallest SR-IOV page size.
496 */
497 if (PAGE_SHIFT < PCI_SRIOV_BASE_PAGE_SHIFT)
498 page_size = (1 << 0);
499 else
500 page_size = (1 << (PAGE_SHIFT - PCI_SRIOV_BASE_PAGE_SHIFT));
501
502 /* Check that the device supports the system page size. */
503 if (!(page_size & page_cap))
504 return (ENXIO);
505
506 IOV_WRITE(dinfo, PCIR_SRIOV_PAGE_SIZE, page_size, 4);
507 return (0);
508 }
509
510 static int
pci_iov_init(device_t dev,uint16_t num_vfs,const nvlist_t * config)511 pci_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *config)
512 {
513 const nvlist_t *device, *driver_config;
514
515 device = nvlist_get_nvlist(config, PF_CONFIG_NAME);
516 driver_config = nvlist_get_nvlist(device, DRIVER_CONFIG_NAME);
517 return (PCI_IOV_INIT(dev, num_vfs, driver_config));
518 }
519
520 static int
pci_iov_init_rman(device_t pf,struct pcicfg_iov * iov)521 pci_iov_init_rman(device_t pf, struct pcicfg_iov *iov)
522 {
523 int error;
524
525 iov->rman.rm_start = 0;
526 iov->rman.rm_end = ~0;
527 iov->rman.rm_type = RMAN_ARRAY;
528 snprintf(iov->rman_name, sizeof(iov->rman_name), "%s VF I/O memory",
529 device_get_nameunit(pf));
530 iov->rman.rm_descr = iov->rman_name;
531
532 error = rman_init(&iov->rman);
533 if (error != 0)
534 return (error);
535
536 iov->iov_flags |= IOV_RMAN_INITED;
537 return (0);
538 }
539
540 static int
pci_iov_alloc_bar_ea(struct pci_devinfo * dinfo,int bar)541 pci_iov_alloc_bar_ea(struct pci_devinfo *dinfo, int bar)
542 {
543 struct pcicfg_iov *iov;
544 rman_res_t start, end;
545 struct resource *res;
546 struct resource_list *rl;
547 struct resource_list_entry *rle;
548
549 rl = &dinfo->resources;
550 iov = dinfo->cfg.iov;
551
552 rle = resource_list_find(rl, SYS_RES_MEMORY,
553 iov->iov_pos + PCIR_SRIOV_BAR(bar));
554 if (rle == NULL)
555 rle = resource_list_find(rl, SYS_RES_IOPORT,
556 iov->iov_pos + PCIR_SRIOV_BAR(bar));
557 if (rle == NULL)
558 return (ENXIO);
559 res = rle->res;
560
561 iov->iov_bar[bar].res = res;
562 iov->iov_bar[bar].bar_size = rman_get_size(res) / iov->iov_num_vfs;
563 iov->iov_bar[bar].bar_shift = pci_mapsize(iov->iov_bar[bar].bar_size);
564
565 start = rman_get_start(res);
566 end = rman_get_end(res);
567
568 return (rman_manage_region(&iov->rman, start, end));
569 }
570
571 static int
pci_iov_setup_bars(struct pci_devinfo * dinfo)572 pci_iov_setup_bars(struct pci_devinfo *dinfo)
573 {
574 device_t dev;
575 struct pcicfg_iov *iov;
576 pci_addr_t bar_value, testval;
577 int i, last_64, error;
578
579 iov = dinfo->cfg.iov;
580 dev = dinfo->cfg.dev;
581 last_64 = 0;
582
583 pci_add_resources_ea(device_get_parent(dev), dev, 1);
584
585 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
586 /* First, try to use BARs allocated with EA */
587 error = pci_iov_alloc_bar_ea(dinfo, i);
588 if (error == 0)
589 continue;
590
591 /* Allocate legacy-BAR only if EA is not enabled */
592 if (pci_ea_is_enabled(dev, iov->iov_pos + PCIR_SRIOV_BAR(i)))
593 continue;
594
595 /*
596 * If a PCI BAR is a 64-bit wide BAR, then it spans two
597 * consecutive registers. Therefore if the last BAR that
598 * we looked at was a 64-bit BAR, we need to skip this
599 * register as it's the second half of the last BAR.
600 */
601 if (!last_64) {
602 pci_read_bar(dev,
603 iov->iov_pos + PCIR_SRIOV_BAR(i),
604 &bar_value, &testval, &last_64);
605
606 if (testval != 0) {
607 error = pci_iov_alloc_bar(dinfo, i,
608 pci_mapsize(testval));
609 if (error != 0)
610 return (error);
611 }
612 } else
613 last_64 = 0;
614 }
615
616 return (0);
617 }
618
619 static void
pci_iov_enumerate_vfs(struct pci_devinfo * dinfo,const nvlist_t * config,uint16_t first_rid,uint16_t rid_stride)620 pci_iov_enumerate_vfs(struct pci_devinfo *dinfo, const nvlist_t *config,
621 uint16_t first_rid, uint16_t rid_stride)
622 {
623 char device_name[VF_MAX_NAME];
624 const nvlist_t *device, *driver_config, *iov_config;
625 device_t bus, dev, vf;
626 struct pcicfg_iov *iov;
627 struct pci_devinfo *vfinfo;
628 int i, error;
629 uint16_t vid, did, next_rid;
630
631 iov = dinfo->cfg.iov;
632 dev = dinfo->cfg.dev;
633 bus = device_get_parent(dev);
634 next_rid = first_rid;
635 vid = pci_get_vendor(dev);
636 did = IOV_READ(dinfo, PCIR_SRIOV_VF_DID, 2);
637
638 for (i = 0; i < iov->iov_num_vfs; i++, next_rid += rid_stride) {
639 snprintf(device_name, sizeof(device_name), VF_PREFIX"%d", i);
640 device = nvlist_get_nvlist(config, device_name);
641 iov_config = nvlist_get_nvlist(device, IOV_CONFIG_NAME);
642 driver_config = nvlist_get_nvlist(device, DRIVER_CONFIG_NAME);
643
644 vf = PCI_CREATE_IOV_CHILD(bus, dev, next_rid, vid, did);
645 if (vf == NULL)
646 break;
647
648 /*
649 * If we are creating passthrough devices then force the ppt
650 * driver to attach to prevent a VF driver from claiming the
651 * VFs.
652 */
653 if (nvlist_get_bool(iov_config, "passthrough"))
654 device_set_devclass_fixed(vf, "ppt");
655
656 vfinfo = device_get_ivars(vf);
657
658 vfinfo->cfg.iov = iov;
659 vfinfo->cfg.vf.index = i;
660
661 pci_iov_add_bars(iov, vfinfo);
662
663 error = PCI_IOV_ADD_VF(dev, i, driver_config);
664 if (error != 0) {
665 device_printf(dev, "Failed to add VF %d\n", i);
666 device_delete_child(bus, vf);
667 }
668 }
669
670 bus_generic_attach(bus);
671 }
672
673 static int
pci_iov_config(struct cdev * cdev,struct pci_iov_arg * arg)674 pci_iov_config(struct cdev *cdev, struct pci_iov_arg *arg)
675 {
676 device_t bus, dev;
677 struct pci_devinfo *dinfo;
678 struct pcicfg_iov *iov;
679 nvlist_t *config;
680 int i, error;
681 uint16_t rid_off, rid_stride;
682 uint16_t first_rid, last_rid;
683 uint16_t iov_ctl;
684 uint16_t num_vfs, total_vfs;
685 int iov_inited;
686
687 mtx_lock(&Giant);
688 dinfo = cdev->si_drv1;
689 iov = dinfo->cfg.iov;
690 dev = dinfo->cfg.dev;
691 bus = device_get_parent(dev);
692 iov_inited = 0;
693 config = NULL;
694
695 if ((iov->iov_flags & IOV_BUSY) || iov->iov_num_vfs != 0) {
696 mtx_unlock(&Giant);
697 return (EBUSY);
698 }
699 iov->iov_flags |= IOV_BUSY;
700
701 error = pci_iov_parse_config(iov, arg, &config);
702 if (error != 0)
703 goto out;
704
705 num_vfs = pci_iov_config_get_num_vfs(config);
706 total_vfs = IOV_READ(dinfo, PCIR_SRIOV_TOTAL_VFS, 2);
707 if (num_vfs > total_vfs) {
708 error = EINVAL;
709 goto out;
710 }
711
712 error = pci_iov_config_page_size(dinfo);
713 if (error != 0)
714 goto out;
715
716 error = pci_iov_set_ari(bus);
717 if (error != 0)
718 goto out;
719
720 error = pci_iov_init(dev, num_vfs, config);
721 if (error != 0)
722 goto out;
723 iov_inited = 1;
724
725 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, num_vfs, 2);
726
727 rid_off = IOV_READ(dinfo, PCIR_SRIOV_VF_OFF, 2);
728 rid_stride = IOV_READ(dinfo, PCIR_SRIOV_VF_STRIDE, 2);
729
730 first_rid = pci_get_rid(dev) + rid_off;
731 last_rid = first_rid + (num_vfs - 1) * rid_stride;
732
733 /* We don't yet support allocating extra bus numbers for VFs. */
734 if (pci_get_bus(dev) != PCI_RID2BUS(last_rid)) {
735 device_printf(dev, "not enough PCIe bus numbers for VFs\n");
736 error = ENOSPC;
737 goto out;
738 }
739
740 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
741 iov_ctl &= ~(PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE);
742 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2);
743
744 error = pci_iov_init_rman(dev, iov);
745 if (error != 0)
746 goto out;
747
748 iov->iov_num_vfs = num_vfs;
749
750 error = pci_iov_setup_bars(dinfo);
751 if (error != 0)
752 goto out;
753
754 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
755 iov_ctl |= PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE;
756 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2);
757
758 /* Per specification, we must wait 100ms before accessing VFs. */
759 pause("iov", roundup(hz, 10));
760 pci_iov_enumerate_vfs(dinfo, config, first_rid, rid_stride);
761
762 nvlist_destroy(config);
763 iov->iov_flags &= ~IOV_BUSY;
764 mtx_unlock(&Giant);
765
766 return (0);
767 out:
768 if (iov_inited)
769 PCI_IOV_UNINIT(dev);
770
771 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
772 if (iov->iov_bar[i].res != NULL) {
773 pci_release_resource(bus, dev, SYS_RES_MEMORY,
774 iov->iov_pos + PCIR_SRIOV_BAR(i),
775 iov->iov_bar[i].res);
776 pci_delete_resource(bus, dev, SYS_RES_MEMORY,
777 iov->iov_pos + PCIR_SRIOV_BAR(i));
778 iov->iov_bar[i].res = NULL;
779 }
780 }
781
782 if (iov->iov_flags & IOV_RMAN_INITED) {
783 rman_fini(&iov->rman);
784 iov->iov_flags &= ~IOV_RMAN_INITED;
785 }
786
787 nvlist_destroy(config);
788 iov->iov_num_vfs = 0;
789 iov->iov_flags &= ~IOV_BUSY;
790 mtx_unlock(&Giant);
791 return (error);
792 }
793
794 void
pci_iov_cfg_restore(device_t dev,struct pci_devinfo * dinfo)795 pci_iov_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
796 {
797 struct pcicfg_iov *iov;
798
799 iov = dinfo->cfg.iov;
800
801 IOV_WRITE(dinfo, PCIR_SRIOV_PAGE_SIZE, iov->iov_page_size, 4);
802 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, iov->iov_num_vfs, 2);
803 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov->iov_ctl, 2);
804 }
805
806 void
pci_iov_cfg_save(device_t dev,struct pci_devinfo * dinfo)807 pci_iov_cfg_save(device_t dev, struct pci_devinfo *dinfo)
808 {
809 struct pcicfg_iov *iov;
810
811 iov = dinfo->cfg.iov;
812
813 iov->iov_page_size = IOV_READ(dinfo, PCIR_SRIOV_PAGE_SIZE, 4);
814 iov->iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
815 }
816
817 /* Return true if child is a VF of the given PF. */
818 static int
pci_iov_is_child_vf(struct pcicfg_iov * pf,device_t child)819 pci_iov_is_child_vf(struct pcicfg_iov *pf, device_t child)
820 {
821 struct pci_devinfo *vfinfo;
822
823 vfinfo = device_get_ivars(child);
824
825 if (!(vfinfo->cfg.flags & PCICFG_VF))
826 return (0);
827
828 return (pf == vfinfo->cfg.iov);
829 }
830
831 static int
pci_iov_delete_iov_children(struct pci_devinfo * dinfo)832 pci_iov_delete_iov_children(struct pci_devinfo *dinfo)
833 {
834 device_t bus, dev, vf, *devlist;
835 struct pcicfg_iov *iov;
836 int i, error, devcount;
837 uint32_t iov_ctl;
838
839 mtx_assert(&Giant, MA_OWNED);
840
841 iov = dinfo->cfg.iov;
842 dev = dinfo->cfg.dev;
843 bus = device_get_parent(dev);
844 devlist = NULL;
845
846 iov->iov_flags |= IOV_BUSY;
847
848 error = device_get_children(bus, &devlist, &devcount);
849
850 if (error != 0)
851 goto out;
852
853 for (i = 0; i < devcount; i++) {
854 vf = devlist[i];
855
856 if (!pci_iov_is_child_vf(iov, vf))
857 continue;
858
859 error = device_detach(vf);
860 if (error != 0) {
861 device_printf(dev,
862 "Could not disable SR-IOV: failed to detach VF %s\n",
863 device_get_nameunit(vf));
864 goto out;
865 }
866 }
867
868 for (i = 0; i < devcount; i++) {
869 vf = devlist[i];
870
871 if (pci_iov_is_child_vf(iov, vf))
872 device_delete_child(bus, vf);
873 }
874 PCI_IOV_UNINIT(dev);
875
876 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
877 iov_ctl &= ~(PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE);
878 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2);
879 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, 0, 2);
880
881 iov->iov_num_vfs = 0;
882
883 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
884 if (iov->iov_bar[i].res != NULL) {
885 pci_release_resource(bus, dev, SYS_RES_MEMORY,
886 iov->iov_pos + PCIR_SRIOV_BAR(i),
887 iov->iov_bar[i].res);
888 pci_delete_resource(bus, dev, SYS_RES_MEMORY,
889 iov->iov_pos + PCIR_SRIOV_BAR(i));
890 iov->iov_bar[i].res = NULL;
891 }
892 }
893
894 if (iov->iov_flags & IOV_RMAN_INITED) {
895 rman_fini(&iov->rman);
896 iov->iov_flags &= ~IOV_RMAN_INITED;
897 }
898
899 error = 0;
900 out:
901 free(devlist, M_TEMP);
902 iov->iov_flags &= ~IOV_BUSY;
903 return (error);
904 }
905
906 static int
pci_iov_delete(struct cdev * cdev)907 pci_iov_delete(struct cdev *cdev)
908 {
909 struct pci_devinfo *dinfo;
910 struct pcicfg_iov *iov;
911 int error;
912
913 mtx_lock(&Giant);
914 dinfo = cdev->si_drv1;
915 iov = dinfo->cfg.iov;
916
917 if ((iov->iov_flags & IOV_BUSY) != 0) {
918 error = EBUSY;
919 goto out;
920 }
921 if (iov->iov_num_vfs == 0) {
922 error = ECHILD;
923 goto out;
924 }
925
926 error = pci_iov_delete_iov_children(dinfo);
927
928 out:
929 mtx_unlock(&Giant);
930 return (error);
931 }
932
933 static int
pci_iov_get_schema_ioctl(struct cdev * cdev,struct pci_iov_schema * output)934 pci_iov_get_schema_ioctl(struct cdev *cdev, struct pci_iov_schema *output)
935 {
936 struct pci_devinfo *dinfo;
937 void *packed;
938 size_t output_len, size;
939 int error;
940
941 packed = NULL;
942
943 mtx_lock(&Giant);
944 dinfo = cdev->si_drv1;
945 packed = nvlist_pack(dinfo->cfg.iov->iov_schema, &size);
946 mtx_unlock(&Giant);
947
948 if (packed == NULL) {
949 error = ENOMEM;
950 goto fail;
951 }
952
953 output_len = output->len;
954 output->len = size;
955 if (size <= output_len) {
956 error = copyout(packed, output->schema, size);
957
958 if (error != 0)
959 goto fail;
960
961 output->error = 0;
962 } else
963 /*
964 * If we return an error then the ioctl code won't copyout
965 * output back to userland, so we flag the error in the struct
966 * instead.
967 */
968 output->error = EMSGSIZE;
969
970 error = 0;
971
972 fail:
973 free(packed, M_NVLIST);
974
975 return (error);
976 }
977
978 static int
pci_iov_ioctl(struct cdev * dev,u_long cmd,caddr_t data,int fflag,struct thread * td)979 pci_iov_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
980 struct thread *td)
981 {
982
983 switch (cmd) {
984 case IOV_CONFIG:
985 return (pci_iov_config(dev, (struct pci_iov_arg *)data));
986 case IOV_DELETE:
987 return (pci_iov_delete(dev));
988 case IOV_GET_SCHEMA:
989 return (pci_iov_get_schema_ioctl(dev,
990 (struct pci_iov_schema *)data));
991 default:
992 return (EINVAL);
993 }
994 }
995
996 struct resource *
pci_vf_alloc_mem_resource(device_t dev,device_t child,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)997 pci_vf_alloc_mem_resource(device_t dev, device_t child, int *rid,
998 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
999 {
1000 struct pci_devinfo *dinfo;
1001 struct pcicfg_iov *iov;
1002 struct pci_map *map;
1003 struct resource *res;
1004 struct resource_list_entry *rle;
1005 rman_res_t bar_start, bar_end;
1006 pci_addr_t bar_length;
1007 int error;
1008
1009 dinfo = device_get_ivars(child);
1010 iov = dinfo->cfg.iov;
1011
1012 map = pci_find_bar(child, *rid);
1013 if (map == NULL)
1014 return (NULL);
1015
1016 bar_length = 1 << map->pm_size;
1017 bar_start = map->pm_value;
1018 bar_end = bar_start + bar_length - 1;
1019
1020 /* Make sure that the resource fits the constraints. */
1021 if (bar_start >= end || bar_end <= bar_start || count != 1)
1022 return (NULL);
1023
1024 /* Clamp the resource to the constraints if necessary. */
1025 if (bar_start < start)
1026 bar_start = start;
1027 if (bar_end > end)
1028 bar_end = end;
1029 bar_length = bar_end - bar_start + 1;
1030
1031 res = rman_reserve_resource(&iov->rman, bar_start, bar_end,
1032 bar_length, flags, child);
1033 if (res == NULL)
1034 return (NULL);
1035
1036 rle = resource_list_add(&dinfo->resources, SYS_RES_MEMORY, *rid,
1037 bar_start, bar_end, 1);
1038 if (rle == NULL) {
1039 rman_release_resource(res);
1040 return (NULL);
1041 }
1042
1043 rman_set_rid(res, *rid);
1044
1045 if (flags & RF_ACTIVE) {
1046 error = bus_activate_resource(child, SYS_RES_MEMORY, *rid, res);
1047 if (error != 0) {
1048 resource_list_delete(&dinfo->resources, SYS_RES_MEMORY,
1049 *rid);
1050 rman_release_resource(res);
1051 return (NULL);
1052 }
1053 }
1054 rle->res = res;
1055
1056 return (res);
1057 }
1058
1059 int
pci_vf_release_mem_resource(device_t dev,device_t child,int rid,struct resource * r)1060 pci_vf_release_mem_resource(device_t dev, device_t child, int rid,
1061 struct resource *r)
1062 {
1063 struct pci_devinfo *dinfo;
1064 struct resource_list_entry *rle;
1065 int error;
1066
1067 dinfo = device_get_ivars(child);
1068
1069 if (rman_get_flags(r) & RF_ACTIVE) {
1070 error = bus_deactivate_resource(child, SYS_RES_MEMORY, rid, r);
1071 if (error != 0)
1072 return (error);
1073 }
1074
1075 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, rid);
1076 if (rle != NULL) {
1077 rle->res = NULL;
1078 resource_list_delete(&dinfo->resources, SYS_RES_MEMORY,
1079 rid);
1080 }
1081
1082 return (rman_release_resource(r));
1083 }
1084