1 /* $OpenBSD: pci_machdep.c,v 1.29 2005/07/28 17:22:28 brad Exp $ */
2 /* $NetBSD: pci_machdep.c,v 1.28 1997/06/06 23:29:17 thorpej Exp $ */
3
4 /*-
5 * Copyright (c) 1997 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10 * NASA Ames Research Center.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the NetBSD
23 * Foundation, Inc. and its contributors.
24 * 4. Neither the name of The NetBSD Foundation nor the names of its
25 * contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 */
40
41 /*
42 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
43 * Copyright (c) 1994 Charles Hannum. All rights reserved.
44 *
45 * Redistribution and use in source and binary forms, with or without
46 * modification, are permitted provided that the following conditions
47 * are met:
48 * 1. Redistributions of source code must retain the above copyright
49 * notice, this list of conditions and the following disclaimer.
50 * 2. Redistributions in binary form must reproduce the above copyright
51 * notice, this list of conditions and the following disclaimer in the
52 * documentation and/or other materials provided with the distribution.
53 * 3. All advertising materials mentioning features or use of this software
54 * must display the following acknowledgement:
55 * This product includes software developed by Charles Hannum.
56 * 4. The name of the author may not be used to endorse or promote products
57 * derived from this software without specific prior written permission.
58 *
59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
69 */
70
71 /*
72 * Machine-specific functions for PCI autoconfiguration.
73 *
74 * On PCs, there are two methods of generating PCI configuration cycles.
75 * We try to detect the appropriate mechanism for this machine and set
76 * up a few function pointers to access the correct method directly.
77 *
78 * The configuration method can be hard-coded in the config file by
79 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode
80 * as defined section 3.6.4.1, `Generating Configuration Cycles'.
81 */
82
83 #include <sys/types.h>
84 #include <sys/param.h>
85 #include <sys/time.h>
86 #include <sys/systm.h>
87 #include <sys/errno.h>
88 #include <sys/device.h>
89
90 #include <uvm/uvm_extern.h>
91
92 #define _I386_BUS_DMA_PRIVATE
93 #include <machine/bus.h>
94 #include <machine/pio.h>
95
96 #include "bios.h"
97 #if NBIOS > 0
98 #include <machine/biosvar.h>
99 extern bios_pciinfo_t *bios_pciinfo;
100 #endif
101
102 #include <i386/isa/icu.h>
103 #include <dev/isa/isavar.h>
104 #include <dev/pci/pcivar.h>
105 #include <dev/pci/pcireg.h>
106 #include <dev/pci/pcidevs.h>
107
108 #include "pcibios.h"
109 #if NPCIBIOS > 0
110 #include <i386/pci/pcibiosvar.h>
111 #endif
112
113 int pci_mode = -1;
114
115 #define PCI_MODE1_ENABLE 0x80000000UL
116 #define PCI_MODE1_ADDRESS_REG 0x0cf8
117 #define PCI_MODE1_DATA_REG 0x0cfc
118
119 #define PCI_MODE2_ENABLE_REG 0x0cf8
120 #define PCI_MODE2_FORWARD_REG 0x0cfa
121
122 #define _m1tag(b, d, f) \
123 (PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8))
124 #define _qe(bus, dev, fcn, vend, prod) \
125 {_m1tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)}
126 struct {
127 u_int32_t tag;
128 pcireg_t id;
129 } pcim1_quirk_tbl[] = {
130 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1),
131 /* XXX Triflex2 not tested */
132 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2),
133 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4),
134 /* Triton needed for Connectix Virtual PC */
135 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX),
136 /* Connectix Virtual PC 5 has a 440BX */
137 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP),
138 {0, 0xffffffff} /* patchable */
139 };
140 #undef _m1tag
141 #undef _qe
142
143 /*
144 * PCI doesn't have any special needs; just use the generic versions
145 * of these functions.
146 */
147 struct i386_bus_dma_tag pci_bus_dma_tag = {
148 NULL, /* _cookie */
149 _bus_dmamap_create,
150 _bus_dmamap_destroy,
151 _bus_dmamap_load,
152 _bus_dmamap_load_mbuf,
153 _bus_dmamap_load_uio,
154 _bus_dmamap_load_raw,
155 _bus_dmamap_unload,
156 NULL, /* _dmamap_sync */
157 _bus_dmamem_alloc,
158 _bus_dmamem_free,
159 _bus_dmamem_map,
160 _bus_dmamem_unmap,
161 _bus_dmamem_mmap,
162 };
163
164 void
pci_attach_hook(parent,self,pba)165 pci_attach_hook(parent, self, pba)
166 struct device *parent, *self;
167 struct pcibus_attach_args *pba;
168 {
169
170 #if NBIOS > 0
171 if (pba->pba_bus == 0)
172 printf(": configuration mode %d (%s)",
173 pci_mode, (bios_pciinfo?"bios":"no bios"));
174 #else
175 if (pba->pba_bus == 0)
176 printf(": configuration mode %d", pci_mode);
177 #endif
178 }
179
180 int
pci_bus_maxdevs(pc,busno)181 pci_bus_maxdevs(pc, busno)
182 pci_chipset_tag_t pc;
183 int busno;
184 {
185
186 /*
187 * Bus number is irrelevant. If Configuration Mechanism 2 is in
188 * use, can only have devices 0-15 on any bus. If Configuration
189 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal'
190 * range).
191 */
192 if (pci_mode == 2)
193 return (16);
194 else
195 return (32);
196 }
197
198 pcitag_t
pci_make_tag(pc,bus,device,function)199 pci_make_tag(pc, bus, device, function)
200 pci_chipset_tag_t pc;
201 int bus, device, function;
202 {
203 pcitag_t tag;
204
205 #ifndef PCI_CONF_MODE
206 switch (pci_mode) {
207 case 1:
208 goto mode1;
209 case 2:
210 goto mode2;
211 default:
212 panic("pci_make_tag: mode not configured");
213 }
214 #endif
215
216 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1)
217 #ifndef PCI_CONF_MODE
218 mode1:
219 #endif
220 if (bus >= 256 || device >= 32 || function >= 8)
221 panic("pci_make_tag: bad request");
222
223 tag.mode1 = PCI_MODE1_ENABLE |
224 (bus << 16) | (device << 11) | (function << 8);
225 return tag;
226 #endif
227
228 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2)
229 #ifndef PCI_CONF_MODE
230 mode2:
231 #endif
232 if (bus >= 256 || device >= 16 || function >= 8)
233 panic("pci_make_tag: bad request");
234
235 tag.mode2.port = 0xc000 | (device << 8);
236 tag.mode2.enable = 0xf0 | (function << 1);
237 tag.mode2.forward = bus;
238 return tag;
239 #endif
240 }
241
242 void
pci_decompose_tag(pc,tag,bp,dp,fp)243 pci_decompose_tag(pc, tag, bp, dp, fp)
244 pci_chipset_tag_t pc;
245 pcitag_t tag;
246 int *bp, *dp, *fp;
247 {
248
249 #ifndef PCI_CONF_MODE
250 switch (pci_mode) {
251 case 1:
252 goto mode1;
253 case 2:
254 goto mode2;
255 default:
256 panic("pci_decompose_tag: mode not configured");
257 }
258 #endif
259
260 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1)
261 #ifndef PCI_CONF_MODE
262 mode1:
263 #endif
264 if (bp != NULL)
265 *bp = (tag.mode1 >> 16) & 0xff;
266 if (dp != NULL)
267 *dp = (tag.mode1 >> 11) & 0x1f;
268 if (fp != NULL)
269 *fp = (tag.mode1 >> 8) & 0x7;
270 return;
271 #endif
272
273 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2)
274 #ifndef PCI_CONF_MODE
275 mode2:
276 #endif
277 if (bp != NULL)
278 *bp = tag.mode2.forward & 0xff;
279 if (dp != NULL)
280 *dp = (tag.mode2.port >> 8) & 0xf;
281 if (fp != NULL)
282 *fp = (tag.mode2.enable >> 1) & 0x7;
283 #endif
284 }
285
286 pcireg_t
pci_conf_read(pc,tag,reg)287 pci_conf_read(pc, tag, reg)
288 pci_chipset_tag_t pc;
289 pcitag_t tag;
290 int reg;
291 {
292 pcireg_t data;
293
294 #ifndef PCI_CONF_MODE
295 switch (pci_mode) {
296 case 1:
297 goto mode1;
298 case 2:
299 goto mode2;
300 default:
301 panic("pci_conf_read: mode not configured");
302 }
303 #endif
304
305 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1)
306 #ifndef PCI_CONF_MODE
307 mode1:
308 #endif
309 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg);
310 data = inl(PCI_MODE1_DATA_REG);
311 outl(PCI_MODE1_ADDRESS_REG, 0);
312 return data;
313 #endif
314
315 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2)
316 #ifndef PCI_CONF_MODE
317 mode2:
318 #endif
319 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable);
320 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward);
321 data = inl(tag.mode2.port | reg);
322 outb(PCI_MODE2_ENABLE_REG, 0);
323 return data;
324 #endif
325 }
326
327 void
pci_conf_write(pc,tag,reg,data)328 pci_conf_write(pc, tag, reg, data)
329 pci_chipset_tag_t pc;
330 pcitag_t tag;
331 int reg;
332 pcireg_t data;
333 {
334
335 #ifndef PCI_CONF_MODE
336 switch (pci_mode) {
337 case 1:
338 goto mode1;
339 case 2:
340 goto mode2;
341 default:
342 panic("pci_conf_write: mode not configured");
343 }
344 #endif
345
346 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 1)
347 #ifndef PCI_CONF_MODE
348 mode1:
349 #endif
350 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg);
351 outl(PCI_MODE1_DATA_REG, data);
352 outl(PCI_MODE1_ADDRESS_REG, 0);
353 return;
354 #endif
355
356 #if !defined(PCI_CONF_MODE) || (PCI_CONF_MODE == 2)
357 #ifndef PCI_CONF_MODE
358 mode2:
359 #endif
360 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable);
361 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward);
362 outl(tag.mode2.port | reg, data);
363 outb(PCI_MODE2_ENABLE_REG, 0);
364 #endif
365 }
366
367 int
pci_mode_detect()368 pci_mode_detect()
369 {
370
371 #ifdef PCI_CONF_MODE
372 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2)
373 return (pci_mode = PCI_CONF_MODE);
374 #else
375 #error Invalid PCI configuration mode.
376 #endif
377 #else
378 u_int32_t sav, val;
379 int i;
380 pcireg_t idreg;
381
382 if (pci_mode != -1)
383 return (pci_mode);
384
385 #if NBIOS > 0
386 /*
387 * If we have PCI info passed from the BIOS, use the mode given there
388 * for all of this code. If not, pass on through to the previous tests
389 * to try and devine the correct mode.
390 */
391 if (bios_pciinfo != NULL) {
392 if (bios_pciinfo->pci_chars & 0x2)
393 return (pci_mode = 2);
394
395 if (bios_pciinfo->pci_chars & 0x1)
396 return (pci_mode = 1);
397
398 /* We should never get here, but if we do, fall through... */
399 }
400 #endif
401
402 /*
403 * We try to divine which configuration mode the host bridge wants.
404 *
405 * This should really be done using the PCI BIOS. If we get here, the
406 * PCI BIOS does not exist, or the boot blocks did not provide the
407 * information.
408 */
409
410 sav = inl(PCI_MODE1_ADDRESS_REG);
411
412 pci_mode = 1; /* assume this for now */
413 /*
414 * catch some known buggy implementations of mode 1
415 */
416 for (i = 0; i < sizeof(pcim1_quirk_tbl) / sizeof(pcim1_quirk_tbl[0]);
417 i++) {
418 pcitag_t t;
419
420 if (!pcim1_quirk_tbl[i].tag)
421 break;
422 t.mode1 = pcim1_quirk_tbl[i].tag;
423 idreg = pci_conf_read(0, t, PCI_ID_REG); /* needs "pci_mode" */
424 if (idreg == pcim1_quirk_tbl[i].id) {
425 #ifdef DEBUG
426 printf("known mode 1 PCI chipset (%08x)\n",
427 idreg);
428 #endif
429 return (pci_mode);
430 }
431 }
432
433 /*
434 * Strong check for standard compliant mode 1:
435 * 1. bit 31 ("enable") can be set
436 * 2. byte/word access does not affect register
437 */
438 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE);
439 outb(PCI_MODE1_ADDRESS_REG + 3, 0);
440 outw(PCI_MODE1_ADDRESS_REG + 2, 0);
441 val = inl(PCI_MODE1_ADDRESS_REG);
442 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) {
443 #ifdef DEBUG
444 printf("pci_mode_detect: mode 1 enable failed (%x)\n",
445 val);
446 #endif
447 goto not1;
448 }
449 outl(PCI_MODE1_ADDRESS_REG, 0);
450 val = inl(PCI_MODE1_ADDRESS_REG);
451 if ((val & 0x80fffffc) != 0)
452 goto not1;
453 return (pci_mode);
454 not1:
455 outl(PCI_MODE1_ADDRESS_REG, sav);
456
457 /*
458 * This mode 2 check is quite weak (and known to give false
459 * positives on some Compaq machines).
460 * However, this doesn't matter, because this is the
461 * last test, and simply no PCI devices will be found if
462 * this happens.
463 */
464 outb(PCI_MODE2_ENABLE_REG, 0);
465 outb(PCI_MODE2_FORWARD_REG, 0);
466 if (inb(PCI_MODE2_ENABLE_REG) != 0 ||
467 inb(PCI_MODE2_FORWARD_REG) != 0)
468 goto not2;
469 return (pci_mode = 2);
470 not2:
471 return (pci_mode = 0);
472 #endif
473 }
474
475 int
pci_intr_map(pa,ihp)476 pci_intr_map(pa, ihp)
477 struct pci_attach_args *pa;
478 pci_intr_handle_t *ihp;
479 {
480 #if NPCIBIOS > 0
481 pci_chipset_tag_t pc = pa->pa_pc;
482 pcitag_t intrtag = pa->pa_intrtag;
483 #endif
484 int pin = pa->pa_intrpin;
485 int line = pa->pa_intrline;
486
487 if (pin == 0) {
488 /* No IRQ used. */
489 goto bad;
490 }
491
492 if (pin > 4) {
493 printf("pci_intr_map: bad interrupt pin %d\n", pin);
494 goto bad;
495 }
496
497 ihp->line = line;
498 ihp->pin = pin;
499 #if NPCIBIOS > 0
500 pci_intr_header_fixup(pc, intrtag, ihp);
501 line = ihp->line;
502 #endif
503
504 /*
505 * Section 6.2.4, `Miscellaneous Functions', says that 255 means
506 * `unknown' or `no connection' on a PC. We assume that a device with
507 * `no connection' either doesn't have an interrupt (in which case the
508 * pin number should be 0, and would have been noticed above), or
509 * wasn't configured by the BIOS (in which case we punt, since there's
510 * no real way we can know how the interrupt lines are mapped in the
511 * hardware).
512 *
513 * XXX
514 * Since IRQ 0 is only used by the clock, and we can't actually be sure
515 * that the BIOS did its job, we also recognize that as meaning that
516 * the BIOS has not configured the device.
517 */
518 if (line == 0 || line == 255) {
519 printf("pci_intr_map: no mapping for pin %c\n", '@' + pin);
520 goto bad;
521 } else {
522 if (line >= ICU_LEN) {
523 printf("pci_intr_map: bad interrupt line %d\n", line);
524 goto bad;
525 }
526 if (line == 2) {
527 printf("pci_intr_map: changed line 2 to line 9\n");
528 line = 9;
529 }
530 }
531
532 return 0;
533
534 bad:
535 ihp->line = -1;
536 return 1;
537 }
538
539 const char *
pci_intr_string(pc,ih)540 pci_intr_string(pc, ih)
541 pci_chipset_tag_t pc;
542 pci_intr_handle_t ih;
543 {
544 static char irqstr[64];
545
546 if (ih.line == 0 || (ih.line & 0xff) >= ICU_LEN || ih.line == 2)
547 panic("pci_intr_string: bogus handle 0x%x", ih.line);
548
549 #if NIOAPIC > 0
550 if (ih.line & APIC_INT_VIA_APIC) {
551 snprintf(irqstr, sizeof irqstr, "apic %d int %d (irq %d)",
552 APIC_IRQ_APIC(ih.line), APIC_IRQ_PIN(ih.line),
553 ih.line & 0xff);
554 return (irqstr);
555 }
556 #endif
557
558 snprintf(irqstr, sizeof irqstr, "irq %d", ih.line);
559 return (irqstr);
560 }
561
562 void *
pci_intr_establish(pc,ih,level,func,arg,what)563 pci_intr_establish(pc, ih, level, func, arg, what)
564 pci_chipset_tag_t pc;
565 pci_intr_handle_t ih;
566 int level, (*func)(void *);
567 void *arg;
568 char *what;
569 {
570 void *ret;
571
572 #if NIOAPIC > 0
573 if (ih.line != -1 && ih.line & APIC_INT_VIA_APIC)
574 return (apic_intr_establish(ih.line, IST_LEVEL, level, func,
575 arg, what));
576 #endif
577 if (ih.line == 0 || ih.line >= ICU_LEN || ih.line == 2)
578 panic("pci_intr_establish: bogus handle 0x%x", ih.line);
579
580 ret = isa_intr_establish(NULL, ih.line, IST_LEVEL, level, func, arg,
581 what);
582 #if NPCIBIOS > 0
583 if (ret)
584 pci_intr_route_link(pc, &ih);
585 #endif
586 return (ret);
587 }
588
589 void
pci_intr_disestablish(pc,cookie)590 pci_intr_disestablish(pc, cookie)
591 pci_chipset_tag_t pc;
592 void *cookie;
593 {
594 /* XXX oh, unroute the pci int link? */
595 isa_intr_disestablish(NULL, cookie);
596 }
597