1 /*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31
32 #include "opt_bus.h"
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/linker.h>
39 #include <sys/fcntl.h>
40 #include <sys/conf.h>
41 #include <sys/kernel.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <sys/endian.h>
45
46 #include <vm/vm.h>
47 #include <vm/pmap.h>
48 #include <vm/vm_extern.h>
49
50 #include <sys/bus.h>
51 #include <machine/bus.h>
52 #include <sys/rman.h>
53 #include <machine/resource.h>
54 #include <machine/stdarg.h>
55
56 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
57 #include <machine/intr_machdep.h>
58 #endif
59
60 #include <sys/pciio.h>
61 #include <dev/pci/pcireg.h>
62 #include <dev/pci/pcivar.h>
63 #include <dev/pci/pci_private.h>
64
65 #include <dev/usb/controller/xhcireg.h>
66 #include <dev/usb/controller/ehcireg.h>
67 #include <dev/usb/controller/ohcireg.h>
68 #include <dev/usb/controller/uhcireg.h>
69
70 #include "pcib_if.h"
71 #include "pci_if.h"
72
73 #define PCIR_IS_BIOS(cfg, reg) \
74 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \
75 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1))
76
77 static int pci_has_quirk(uint32_t devid, int quirk);
78 static pci_addr_t pci_mapbase(uint64_t mapreg);
79 static const char *pci_maptype(uint64_t mapreg);
80 static int pci_mapsize(uint64_t testval);
81 static int pci_maprange(uint64_t mapreg);
82 static pci_addr_t pci_rombase(uint64_t mapreg);
83 static int pci_romsize(uint64_t testval);
84 static void pci_fixancient(pcicfgregs *cfg);
85 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...);
86
87 static int pci_porten(device_t dev);
88 static int pci_memen(device_t dev);
89 static void pci_assign_interrupt(device_t bus, device_t dev,
90 int force_route);
91 static int pci_add_map(device_t bus, device_t dev, int reg,
92 struct resource_list *rl, int force, int prefetch);
93 static int pci_probe(device_t dev);
94 static int pci_attach(device_t dev);
95 #ifdef PCI_RES_BUS
96 static int pci_detach(device_t dev);
97 #endif
98 static void pci_load_vendor_data(void);
99 static int pci_describe_parse_line(char **ptr, int *vendor,
100 int *device, char **desc);
101 static char *pci_describe_device(device_t dev);
102 static int pci_modevent(module_t mod, int what, void *arg);
103 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
104 pcicfgregs *cfg);
105 static void pci_read_cap(device_t pcib, pcicfgregs *cfg);
106 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
107 int reg, uint32_t *data);
108 #if 0
109 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
110 int reg, uint32_t data);
111 #endif
112 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
113 static void pci_disable_msi(device_t dev);
114 static void pci_enable_msi(device_t dev, uint64_t address,
115 uint16_t data);
116 static void pci_enable_msix(device_t dev, u_int index,
117 uint64_t address, uint32_t data);
118 static void pci_mask_msix(device_t dev, u_int index);
119 static void pci_unmask_msix(device_t dev, u_int index);
120 static int pci_msi_blacklisted(void);
121 static int pci_msix_blacklisted(void);
122 static void pci_resume_msi(device_t dev);
123 static void pci_resume_msix(device_t dev);
124 static int pci_remap_intr_method(device_t bus, device_t dev,
125 u_int irq);
126
127 static uint16_t pci_get_rid_method(device_t dev, device_t child);
128
129 static device_method_t pci_methods[] = {
130 /* Device interface */
131 DEVMETHOD(device_probe, pci_probe),
132 DEVMETHOD(device_attach, pci_attach),
133 #ifdef PCI_RES_BUS
134 DEVMETHOD(device_detach, pci_detach),
135 #else
136 DEVMETHOD(device_detach, bus_generic_detach),
137 #endif
138 DEVMETHOD(device_shutdown, bus_generic_shutdown),
139 DEVMETHOD(device_suspend, pci_suspend),
140 DEVMETHOD(device_resume, pci_resume),
141
142 /* Bus interface */
143 DEVMETHOD(bus_print_child, pci_print_child),
144 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
145 DEVMETHOD(bus_read_ivar, pci_read_ivar),
146 DEVMETHOD(bus_write_ivar, pci_write_ivar),
147 DEVMETHOD(bus_driver_added, pci_driver_added),
148 DEVMETHOD(bus_setup_intr, pci_setup_intr),
149 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
150
151 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag),
152 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
153 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
154 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
155 DEVMETHOD(bus_delete_resource, pci_delete_resource),
156 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
157 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
158 DEVMETHOD(bus_release_resource, pci_release_resource),
159 DEVMETHOD(bus_activate_resource, pci_activate_resource),
160 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
161 DEVMETHOD(bus_child_detached, pci_child_detached),
162 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
163 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
164 DEVMETHOD(bus_remap_intr, pci_remap_intr_method),
165
166 /* PCI interface */
167 DEVMETHOD(pci_read_config, pci_read_config_method),
168 DEVMETHOD(pci_write_config, pci_write_config_method),
169 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
170 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
171 DEVMETHOD(pci_enable_io, pci_enable_io_method),
172 DEVMETHOD(pci_disable_io, pci_disable_io_method),
173 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
174 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
175 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
176 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
177 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
178 DEVMETHOD(pci_find_cap, pci_find_cap_method),
179 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
180 DEVMETHOD(pci_find_htcap, pci_find_htcap_method),
181 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
182 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
183 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
184 DEVMETHOD(pci_release_msi, pci_release_msi_method),
185 DEVMETHOD(pci_msi_count, pci_msi_count_method),
186 DEVMETHOD(pci_msix_count, pci_msix_count_method),
187 DEVMETHOD(pci_get_rid, pci_get_rid_method),
188
189 DEVMETHOD_END
190 };
191
192 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc));
193
194 static devclass_t pci_devclass;
195 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL);
196 MODULE_VERSION(pci, 1);
197
198 static char *pci_vendordata;
199 static size_t pci_vendordata_size;
200
201 struct pci_quirk {
202 uint32_t devid; /* Vendor/device of the card */
203 int type;
204 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
205 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */
206 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */
207 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */
208 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */
209 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */
210 int arg1;
211 int arg2;
212 };
213
214 static const struct pci_quirk pci_quirks[] = {
215 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */
216 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
217 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
218 /* As does the Serverworks OSB4 (the SMBus mapping register) */
219 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
220
221 /*
222 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
223 * or the CMIC-SL (AKA ServerWorks GC_LE).
224 */
225 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
226 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
227
228 /*
229 * MSI doesn't work on earlier Intel chipsets including
230 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
231 */
232 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
233 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
234 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
235 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
236 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
237 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
238 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
239
240 /*
241 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
242 * bridge.
243 */
244 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
245
246 /*
247 * MSI-X allocation doesn't work properly for devices passed through
248 * by VMware up to at least ESXi 5.1.
249 */
250 { 0x079015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCI/PCI-X */
251 { 0x07a015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCIe */
252
253 /*
254 * Some virtualization environments emulate an older chipset
255 * but support MSI just fine. QEMU uses the Intel 82440.
256 */
257 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 },
258
259 /*
260 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus
261 * controller depending on SoftPciRst register (PM_IO 0x55 [7]).
262 * It prevents us from attaching hpet(4) when the bit is unset.
263 * Note this quirk only affects SB600 revision A13 and earlier.
264 * For SB600 A21 and later, firmware must set the bit to hide it.
265 * For SB700 and later, it is unused and hardcoded to zero.
266 */
267 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 },
268
269 /*
270 * Atheros AR8161/AR8162/E2200 Ethernet controllers have a bug that
271 * MSI interrupt does not assert if PCIM_CMD_INTxDIS bit of the
272 * command register is set.
273 */
274 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
275 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
276 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
277
278 /*
279 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't
280 * issue MSI interrupts with PCIM_CMD_INTxDIS set either.
281 */
282 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */
283 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */
284 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */
285 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */
286 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */
287 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */
288
289 { 0 }
290 };
291
292 /* map register information */
293 #define PCI_MAPMEM 0x01 /* memory map */
294 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
295 #define PCI_MAPPORT 0x04 /* port map */
296
297 struct devlist pci_devq;
298 uint32_t pci_generation;
299 uint32_t pci_numdevs = 0;
300 static int pcie_chipset, pcix_chipset;
301
302 /* sysctl vars */
303 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
304
305 static int pci_enable_io_modes = 1;
306 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
307 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
308 &pci_enable_io_modes, 1,
309 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
310 enable these bits correctly. We'd like to do this all the time, but there\n\
311 are some peripherals that this causes problems with.");
312
313 static int pci_do_realloc_bars = 0;
314 TUNABLE_INT("hw.pci.realloc_bars", &pci_do_realloc_bars);
315 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RW,
316 &pci_do_realloc_bars, 0,
317 "Attempt to allocate a new range for any BARs whose original firmware-assigned ranges fail to allocate during the initial device scan.");
318
319 static int pci_do_power_nodriver = 0;
320 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
321 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
322 &pci_do_power_nodriver, 0,
323 "Place a function into D3 state when no driver attaches to it. 0 means\n\
324 disable. 1 means conservatively place devices into D3 state. 2 means\n\
325 agressively place devices into D3 state. 3 means put absolutely everything\n\
326 in D3 state.");
327
328 int pci_do_power_resume = 1;
329 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
330 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
331 &pci_do_power_resume, 1,
332 "Transition from D3 -> D0 on resume.");
333
334 int pci_do_power_suspend = 1;
335 TUNABLE_INT("hw.pci.do_power_suspend", &pci_do_power_suspend);
336 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RW,
337 &pci_do_power_suspend, 1,
338 "Transition from D0 -> D3 on suspend.");
339
340 static int pci_do_msi = 1;
341 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
342 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
343 "Enable support for MSI interrupts");
344
345 static int pci_do_msix = 1;
346 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
347 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
348 "Enable support for MSI-X interrupts");
349
350 static int pci_honor_msi_blacklist = 1;
351 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
352 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
353 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X");
354
355 #if defined(__i386__) || defined(__amd64__)
356 static int pci_usb_takeover = 1;
357 #else
358 static int pci_usb_takeover = 0;
359 #endif
360 TUNABLE_INT("hw.pci.usb_early_takeover", &pci_usb_takeover);
361 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN,
362 &pci_usb_takeover, 1, "Enable early takeover of USB controllers.\n\
363 Disable this if you depend on BIOS emulation of USB devices, that is\n\
364 you use USB devices (like keyboard or mouse) but do not load USB drivers");
365
366 static int pci_clear_bars;
367 TUNABLE_INT("hw.pci.clear_bars", &pci_clear_bars);
368 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0,
369 "Ignore firmware-assigned resources for BARs.");
370
371 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
372 static int pci_clear_buses;
373 TUNABLE_INT("hw.pci.clear_buses", &pci_clear_buses);
374 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0,
375 "Ignore firmware-assigned bus numbers.");
376 #endif
377
378 static int pci_enable_ari = 1;
379 TUNABLE_INT("hw.pci.enable_ari", &pci_enable_ari);
380 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari,
381 0, "Enable support for PCIe Alternative RID Interpretation");
382
383 static int
pci_has_quirk(uint32_t devid,int quirk)384 pci_has_quirk(uint32_t devid, int quirk)
385 {
386 const struct pci_quirk *q;
387
388 for (q = &pci_quirks[0]; q->devid; q++) {
389 if (q->devid == devid && q->type == quirk)
390 return (1);
391 }
392 return (0);
393 }
394
395 /* Find a device_t by bus/slot/function in domain 0 */
396
397 device_t
pci_find_bsf(uint8_t bus,uint8_t slot,uint8_t func)398 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
399 {
400
401 return (pci_find_dbsf(0, bus, slot, func));
402 }
403
404 /* Find a device_t by domain/bus/slot/function */
405
406 device_t
pci_find_dbsf(uint32_t domain,uint8_t bus,uint8_t slot,uint8_t func)407 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
408 {
409 struct pci_devinfo *dinfo;
410
411 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
412 if ((dinfo->cfg.domain == domain) &&
413 (dinfo->cfg.bus == bus) &&
414 (dinfo->cfg.slot == slot) &&
415 (dinfo->cfg.func == func)) {
416 return (dinfo->cfg.dev);
417 }
418 }
419
420 return (NULL);
421 }
422
423 /* Find a device_t by vendor/device ID */
424
425 device_t
pci_find_device(uint16_t vendor,uint16_t device)426 pci_find_device(uint16_t vendor, uint16_t device)
427 {
428 struct pci_devinfo *dinfo;
429
430 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
431 if ((dinfo->cfg.vendor == vendor) &&
432 (dinfo->cfg.device == device)) {
433 return (dinfo->cfg.dev);
434 }
435 }
436
437 return (NULL);
438 }
439
440 device_t
pci_find_class(uint8_t class,uint8_t subclass)441 pci_find_class(uint8_t class, uint8_t subclass)
442 {
443 struct pci_devinfo *dinfo;
444
445 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
446 if (dinfo->cfg.baseclass == class &&
447 dinfo->cfg.subclass == subclass) {
448 return (dinfo->cfg.dev);
449 }
450 }
451
452 return (NULL);
453 }
454
455 static int
pci_printf(pcicfgregs * cfg,const char * fmt,...)456 pci_printf(pcicfgregs *cfg, const char *fmt, ...)
457 {
458 va_list ap;
459 int retval;
460
461 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot,
462 cfg->func);
463 va_start(ap, fmt);
464 retval += vprintf(fmt, ap);
465 va_end(ap);
466 return (retval);
467 }
468
469 /* return base address of memory or port map */
470
471 static pci_addr_t
pci_mapbase(uint64_t mapreg)472 pci_mapbase(uint64_t mapreg)
473 {
474
475 if (PCI_BAR_MEM(mapreg))
476 return (mapreg & PCIM_BAR_MEM_BASE);
477 else
478 return (mapreg & PCIM_BAR_IO_BASE);
479 }
480
481 /* return map type of memory or port map */
482
483 static const char *
pci_maptype(uint64_t mapreg)484 pci_maptype(uint64_t mapreg)
485 {
486
487 if (PCI_BAR_IO(mapreg))
488 return ("I/O Port");
489 if (mapreg & PCIM_BAR_MEM_PREFETCH)
490 return ("Prefetchable Memory");
491 return ("Memory");
492 }
493
494 /* return log2 of map size decoded for memory or port map */
495
496 static int
pci_mapsize(uint64_t testval)497 pci_mapsize(uint64_t testval)
498 {
499 int ln2size;
500
501 testval = pci_mapbase(testval);
502 ln2size = 0;
503 if (testval != 0) {
504 while ((testval & 1) == 0)
505 {
506 ln2size++;
507 testval >>= 1;
508 }
509 }
510 return (ln2size);
511 }
512
513 /* return base address of device ROM */
514
515 static pci_addr_t
pci_rombase(uint64_t mapreg)516 pci_rombase(uint64_t mapreg)
517 {
518
519 return (mapreg & PCIM_BIOS_ADDR_MASK);
520 }
521
522 /* return log2 of map size decided for device ROM */
523
524 static int
pci_romsize(uint64_t testval)525 pci_romsize(uint64_t testval)
526 {
527 int ln2size;
528
529 testval = pci_rombase(testval);
530 ln2size = 0;
531 if (testval != 0) {
532 while ((testval & 1) == 0)
533 {
534 ln2size++;
535 testval >>= 1;
536 }
537 }
538 return (ln2size);
539 }
540
541 /* return log2 of address range supported by map register */
542
543 static int
pci_maprange(uint64_t mapreg)544 pci_maprange(uint64_t mapreg)
545 {
546 int ln2range = 0;
547
548 if (PCI_BAR_IO(mapreg))
549 ln2range = 32;
550 else
551 switch (mapreg & PCIM_BAR_MEM_TYPE) {
552 case PCIM_BAR_MEM_32:
553 ln2range = 32;
554 break;
555 case PCIM_BAR_MEM_1MB:
556 ln2range = 20;
557 break;
558 case PCIM_BAR_MEM_64:
559 ln2range = 64;
560 break;
561 }
562 return (ln2range);
563 }
564
565 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
566
567 static void
pci_fixancient(pcicfgregs * cfg)568 pci_fixancient(pcicfgregs *cfg)
569 {
570 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
571 return;
572
573 /* PCI to PCI bridges use header type 1 */
574 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
575 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
576 }
577
578 /* extract header type specific config data */
579
580 static void
pci_hdrtypedata(device_t pcib,int b,int s,int f,pcicfgregs * cfg)581 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
582 {
583 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
584 switch (cfg->hdrtype & PCIM_HDRTYPE) {
585 case PCIM_HDRTYPE_NORMAL:
586 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
587 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
588 cfg->mingnt = REG(PCIR_MINGNT, 1);
589 cfg->maxlat = REG(PCIR_MAXLAT, 1);
590 cfg->nummaps = PCI_MAXMAPS_0;
591 break;
592 case PCIM_HDRTYPE_BRIDGE:
593 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1);
594 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1);
595 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1);
596 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1);
597 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2);
598 cfg->nummaps = PCI_MAXMAPS_1;
599 break;
600 case PCIM_HDRTYPE_CARDBUS:
601 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1);
602 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1);
603 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1);
604 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1);
605 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2);
606 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
607 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
608 cfg->nummaps = PCI_MAXMAPS_2;
609 break;
610 }
611 #undef REG
612 }
613
614 /* read configuration header into pcicfgregs structure */
615 struct pci_devinfo *
pci_read_device(device_t pcib,int d,int b,int s,int f,size_t size)616 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
617 {
618 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
619 pcicfgregs *cfg = NULL;
620 struct pci_devinfo *devlist_entry;
621 struct devlist *devlist_head;
622
623 devlist_head = &pci_devq;
624
625 devlist_entry = NULL;
626
627 if (REG(PCIR_DEVVENDOR, 4) != 0xfffffffful) {
628 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
629 if (devlist_entry == NULL)
630 return (NULL);
631
632 cfg = &devlist_entry->cfg;
633
634 cfg->domain = d;
635 cfg->bus = b;
636 cfg->slot = s;
637 cfg->func = f;
638 cfg->vendor = REG(PCIR_VENDOR, 2);
639 cfg->device = REG(PCIR_DEVICE, 2);
640 cfg->cmdreg = REG(PCIR_COMMAND, 2);
641 cfg->statreg = REG(PCIR_STATUS, 2);
642 cfg->baseclass = REG(PCIR_CLASS, 1);
643 cfg->subclass = REG(PCIR_SUBCLASS, 1);
644 cfg->progif = REG(PCIR_PROGIF, 1);
645 cfg->revid = REG(PCIR_REVID, 1);
646 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
647 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
648 cfg->lattimer = REG(PCIR_LATTIMER, 1);
649 cfg->intpin = REG(PCIR_INTPIN, 1);
650 cfg->intline = REG(PCIR_INTLINE, 1);
651
652 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
653 cfg->hdrtype &= ~PCIM_MFDEV;
654 STAILQ_INIT(&cfg->maps);
655
656 pci_fixancient(cfg);
657 pci_hdrtypedata(pcib, b, s, f, cfg);
658
659 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
660 pci_read_cap(pcib, cfg);
661
662 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
663
664 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
665 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
666 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
667 devlist_entry->conf.pc_sel.pc_func = cfg->func;
668 devlist_entry->conf.pc_hdr = cfg->hdrtype;
669
670 devlist_entry->conf.pc_subvendor = cfg->subvendor;
671 devlist_entry->conf.pc_subdevice = cfg->subdevice;
672 devlist_entry->conf.pc_vendor = cfg->vendor;
673 devlist_entry->conf.pc_device = cfg->device;
674
675 devlist_entry->conf.pc_class = cfg->baseclass;
676 devlist_entry->conf.pc_subclass = cfg->subclass;
677 devlist_entry->conf.pc_progif = cfg->progif;
678 devlist_entry->conf.pc_revid = cfg->revid;
679
680 pci_numdevs++;
681 pci_generation++;
682 }
683 return (devlist_entry);
684 #undef REG
685 }
686
687 static void
pci_read_cap(device_t pcib,pcicfgregs * cfg)688 pci_read_cap(device_t pcib, pcicfgregs *cfg)
689 {
690 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
691 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
692 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
693 uint64_t addr;
694 #endif
695 uint32_t val;
696 int ptr, nextptr, ptrptr;
697
698 switch (cfg->hdrtype & PCIM_HDRTYPE) {
699 case PCIM_HDRTYPE_NORMAL:
700 case PCIM_HDRTYPE_BRIDGE:
701 ptrptr = PCIR_CAP_PTR;
702 break;
703 case PCIM_HDRTYPE_CARDBUS:
704 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
705 break;
706 default:
707 return; /* no extended capabilities support */
708 }
709 nextptr = REG(ptrptr, 1); /* sanity check? */
710
711 /*
712 * Read capability entries.
713 */
714 while (nextptr != 0) {
715 /* Sanity check */
716 if (nextptr > 255) {
717 printf("illegal PCI extended capability offset %d\n",
718 nextptr);
719 return;
720 }
721 /* Find the next entry */
722 ptr = nextptr;
723 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
724
725 /* Process this entry */
726 switch (REG(ptr + PCICAP_ID, 1)) {
727 case PCIY_PMG: /* PCI power management */
728 if (cfg->pp.pp_cap == 0) {
729 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
730 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
731 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE;
732 if ((nextptr - ptr) > PCIR_POWER_DATA)
733 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
734 }
735 break;
736 case PCIY_HT: /* HyperTransport */
737 /* Determine HT-specific capability type. */
738 val = REG(ptr + PCIR_HT_COMMAND, 2);
739
740 if ((val & 0xe000) == PCIM_HTCAP_SLAVE)
741 cfg->ht.ht_slave = ptr;
742
743 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
744 switch (val & PCIM_HTCMD_CAP_MASK) {
745 case PCIM_HTCAP_MSI_MAPPING:
746 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
747 /* Sanity check the mapping window. */
748 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,
749 4);
750 addr <<= 32;
751 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,
752 4);
753 if (addr != MSI_INTEL_ADDR_BASE)
754 device_printf(pcib,
755 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n",
756 cfg->domain, cfg->bus,
757 cfg->slot, cfg->func,
758 (long long)addr);
759 } else
760 addr = MSI_INTEL_ADDR_BASE;
761
762 cfg->ht.ht_msimap = ptr;
763 cfg->ht.ht_msictrl = val;
764 cfg->ht.ht_msiaddr = addr;
765 break;
766 }
767 #endif
768 break;
769 case PCIY_MSI: /* PCI MSI */
770 cfg->msi.msi_location = ptr;
771 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
772 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
773 PCIM_MSICTRL_MMC_MASK)>>1);
774 break;
775 case PCIY_MSIX: /* PCI MSI-X */
776 cfg->msix.msix_location = ptr;
777 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
778 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
779 PCIM_MSIXCTRL_TABLE_SIZE) + 1;
780 val = REG(ptr + PCIR_MSIX_TABLE, 4);
781 cfg->msix.msix_table_bar = PCIR_BAR(val &
782 PCIM_MSIX_BIR_MASK);
783 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
784 val = REG(ptr + PCIR_MSIX_PBA, 4);
785 cfg->msix.msix_pba_bar = PCIR_BAR(val &
786 PCIM_MSIX_BIR_MASK);
787 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
788 break;
789 case PCIY_VPD: /* PCI Vital Product Data */
790 cfg->vpd.vpd_reg = ptr;
791 break;
792 case PCIY_SUBVENDOR:
793 /* Should always be true. */
794 if ((cfg->hdrtype & PCIM_HDRTYPE) ==
795 PCIM_HDRTYPE_BRIDGE) {
796 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
797 cfg->subvendor = val & 0xffff;
798 cfg->subdevice = val >> 16;
799 }
800 break;
801 case PCIY_PCIX: /* PCI-X */
802 /*
803 * Assume we have a PCI-X chipset if we have
804 * at least one PCI-PCI bridge with a PCI-X
805 * capability. Note that some systems with
806 * PCI-express or HT chipsets might match on
807 * this check as well.
808 */
809 if ((cfg->hdrtype & PCIM_HDRTYPE) ==
810 PCIM_HDRTYPE_BRIDGE)
811 pcix_chipset = 1;
812 cfg->pcix.pcix_location = ptr;
813 break;
814 case PCIY_EXPRESS: /* PCI-express */
815 /*
816 * Assume we have a PCI-express chipset if we have
817 * at least one PCI-express device.
818 */
819 pcie_chipset = 1;
820 cfg->pcie.pcie_location = ptr;
821 val = REG(ptr + PCIER_FLAGS, 2);
822 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE;
823 break;
824 default:
825 break;
826 }
827 }
828
829 #if defined(__powerpc__)
830 /*
831 * Enable the MSI mapping window for all HyperTransport
832 * slaves. PCI-PCI bridges have their windows enabled via
833 * PCIB_MAP_MSI().
834 */
835 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 &&
836 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
837 device_printf(pcib,
838 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n",
839 cfg->domain, cfg->bus, cfg->slot, cfg->func);
840 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
841 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl,
842 2);
843 }
844 #endif
845 /* REG and WREG use carry through to next functions */
846 }
847
848 /*
849 * PCI Vital Product Data
850 */
851
852 #define PCI_VPD_TIMEOUT 1000000
853
854 static int
pci_read_vpd_reg(device_t pcib,pcicfgregs * cfg,int reg,uint32_t * data)855 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
856 {
857 int count = PCI_VPD_TIMEOUT;
858
859 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
860
861 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
862
863 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
864 if (--count < 0)
865 return (ENXIO);
866 DELAY(1); /* limit looping */
867 }
868 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
869
870 return (0);
871 }
872
873 #if 0
874 static int
875 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
876 {
877 int count = PCI_VPD_TIMEOUT;
878
879 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
880
881 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
882 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
883 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
884 if (--count < 0)
885 return (ENXIO);
886 DELAY(1); /* limit looping */
887 }
888
889 return (0);
890 }
891 #endif
892
893 #undef PCI_VPD_TIMEOUT
894
895 struct vpd_readstate {
896 device_t pcib;
897 pcicfgregs *cfg;
898 uint32_t val;
899 int bytesinval;
900 int off;
901 uint8_t cksum;
902 };
903
904 static int
vpd_nextbyte(struct vpd_readstate * vrs,uint8_t * data)905 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
906 {
907 uint32_t reg;
908 uint8_t byte;
909
910 if (vrs->bytesinval == 0) {
911 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
912 return (ENXIO);
913 vrs->val = le32toh(reg);
914 vrs->off += 4;
915 byte = vrs->val & 0xff;
916 vrs->bytesinval = 3;
917 } else {
918 vrs->val = vrs->val >> 8;
919 byte = vrs->val & 0xff;
920 vrs->bytesinval--;
921 }
922
923 vrs->cksum += byte;
924 *data = byte;
925 return (0);
926 }
927
928 static void
pci_read_vpd(device_t pcib,pcicfgregs * cfg)929 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
930 {
931 struct vpd_readstate vrs;
932 int state;
933 int name;
934 int remain;
935 int i;
936 int alloc, off; /* alloc/off for RO/W arrays */
937 int cksumvalid;
938 int dflen;
939 uint8_t byte;
940 uint8_t byte2;
941
942 /* init vpd reader */
943 vrs.bytesinval = 0;
944 vrs.off = 0;
945 vrs.pcib = pcib;
946 vrs.cfg = cfg;
947 vrs.cksum = 0;
948
949 state = 0;
950 name = remain = i = 0; /* shut up stupid gcc */
951 alloc = off = 0; /* shut up stupid gcc */
952 dflen = 0; /* shut up stupid gcc */
953 cksumvalid = -1;
954 while (state >= 0) {
955 if (vpd_nextbyte(&vrs, &byte)) {
956 state = -2;
957 break;
958 }
959 #if 0
960 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
961 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
962 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
963 #endif
964 switch (state) {
965 case 0: /* item name */
966 if (byte & 0x80) {
967 if (vpd_nextbyte(&vrs, &byte2)) {
968 state = -2;
969 break;
970 }
971 remain = byte2;
972 if (vpd_nextbyte(&vrs, &byte2)) {
973 state = -2;
974 break;
975 }
976 remain |= byte2 << 8;
977 if (remain > (0x7f*4 - vrs.off)) {
978 state = -1;
979 pci_printf(cfg,
980 "invalid VPD data, remain %#x\n",
981 remain);
982 }
983 name = byte & 0x7f;
984 } else {
985 remain = byte & 0x7;
986 name = (byte >> 3) & 0xf;
987 }
988 switch (name) {
989 case 0x2: /* String */
990 cfg->vpd.vpd_ident = malloc(remain + 1,
991 M_DEVBUF, M_WAITOK);
992 i = 0;
993 state = 1;
994 break;
995 case 0xf: /* End */
996 state = -1;
997 break;
998 case 0x10: /* VPD-R */
999 alloc = 8;
1000 off = 0;
1001 cfg->vpd.vpd_ros = malloc(alloc *
1002 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
1003 M_WAITOK | M_ZERO);
1004 state = 2;
1005 break;
1006 case 0x11: /* VPD-W */
1007 alloc = 8;
1008 off = 0;
1009 cfg->vpd.vpd_w = malloc(alloc *
1010 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
1011 M_WAITOK | M_ZERO);
1012 state = 5;
1013 break;
1014 default: /* Invalid data, abort */
1015 state = -1;
1016 break;
1017 }
1018 break;
1019
1020 case 1: /* Identifier String */
1021 cfg->vpd.vpd_ident[i++] = byte;
1022 remain--;
1023 if (remain == 0) {
1024 cfg->vpd.vpd_ident[i] = '\0';
1025 state = 0;
1026 }
1027 break;
1028
1029 case 2: /* VPD-R Keyword Header */
1030 if (off == alloc) {
1031 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
1032 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
1033 M_DEVBUF, M_WAITOK | M_ZERO);
1034 }
1035 cfg->vpd.vpd_ros[off].keyword[0] = byte;
1036 if (vpd_nextbyte(&vrs, &byte2)) {
1037 state = -2;
1038 break;
1039 }
1040 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
1041 if (vpd_nextbyte(&vrs, &byte2)) {
1042 state = -2;
1043 break;
1044 }
1045 cfg->vpd.vpd_ros[off].len = dflen = byte2;
1046 if (dflen == 0 &&
1047 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
1048 2) == 0) {
1049 /*
1050 * if this happens, we can't trust the rest
1051 * of the VPD.
1052 */
1053 pci_printf(cfg, "bad keyword length: %d\n",
1054 dflen);
1055 cksumvalid = 0;
1056 state = -1;
1057 break;
1058 } else if (dflen == 0) {
1059 cfg->vpd.vpd_ros[off].value = malloc(1 *
1060 sizeof(*cfg->vpd.vpd_ros[off].value),
1061 M_DEVBUF, M_WAITOK);
1062 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1063 } else
1064 cfg->vpd.vpd_ros[off].value = malloc(
1065 (dflen + 1) *
1066 sizeof(*cfg->vpd.vpd_ros[off].value),
1067 M_DEVBUF, M_WAITOK);
1068 remain -= 3;
1069 i = 0;
1070 /* keep in sync w/ state 3's transistions */
1071 if (dflen == 0 && remain == 0)
1072 state = 0;
1073 else if (dflen == 0)
1074 state = 2;
1075 else
1076 state = 3;
1077 break;
1078
1079 case 3: /* VPD-R Keyword Value */
1080 cfg->vpd.vpd_ros[off].value[i++] = byte;
1081 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1082 "RV", 2) == 0 && cksumvalid == -1) {
1083 if (vrs.cksum == 0)
1084 cksumvalid = 1;
1085 else {
1086 if (bootverbose)
1087 pci_printf(cfg,
1088 "bad VPD cksum, remain %hhu\n",
1089 vrs.cksum);
1090 cksumvalid = 0;
1091 state = -1;
1092 break;
1093 }
1094 }
1095 dflen--;
1096 remain--;
1097 /* keep in sync w/ state 2's transistions */
1098 if (dflen == 0)
1099 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1100 if (dflen == 0 && remain == 0) {
1101 cfg->vpd.vpd_rocnt = off;
1102 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
1103 off * sizeof(*cfg->vpd.vpd_ros),
1104 M_DEVBUF, M_WAITOK | M_ZERO);
1105 state = 0;
1106 } else if (dflen == 0)
1107 state = 2;
1108 break;
1109
1110 case 4:
1111 remain--;
1112 if (remain == 0)
1113 state = 0;
1114 break;
1115
1116 case 5: /* VPD-W Keyword Header */
1117 if (off == alloc) {
1118 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
1119 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1120 M_DEVBUF, M_WAITOK | M_ZERO);
1121 }
1122 cfg->vpd.vpd_w[off].keyword[0] = byte;
1123 if (vpd_nextbyte(&vrs, &byte2)) {
1124 state = -2;
1125 break;
1126 }
1127 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1128 if (vpd_nextbyte(&vrs, &byte2)) {
1129 state = -2;
1130 break;
1131 }
1132 cfg->vpd.vpd_w[off].len = dflen = byte2;
1133 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1134 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) *
1135 sizeof(*cfg->vpd.vpd_w[off].value),
1136 M_DEVBUF, M_WAITOK);
1137 remain -= 3;
1138 i = 0;
1139 /* keep in sync w/ state 6's transistions */
1140 if (dflen == 0 && remain == 0)
1141 state = 0;
1142 else if (dflen == 0)
1143 state = 5;
1144 else
1145 state = 6;
1146 break;
1147
1148 case 6: /* VPD-W Keyword Value */
1149 cfg->vpd.vpd_w[off].value[i++] = byte;
1150 dflen--;
1151 remain--;
1152 /* keep in sync w/ state 5's transistions */
1153 if (dflen == 0)
1154 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1155 if (dflen == 0 && remain == 0) {
1156 cfg->vpd.vpd_wcnt = off;
1157 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
1158 off * sizeof(*cfg->vpd.vpd_w),
1159 M_DEVBUF, M_WAITOK | M_ZERO);
1160 state = 0;
1161 } else if (dflen == 0)
1162 state = 5;
1163 break;
1164
1165 default:
1166 pci_printf(cfg, "invalid state: %d\n", state);
1167 state = -1;
1168 break;
1169 }
1170 }
1171
1172 if (cksumvalid == 0 || state < -1) {
1173 /* read-only data bad, clean up */
1174 if (cfg->vpd.vpd_ros != NULL) {
1175 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1176 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1177 free(cfg->vpd.vpd_ros, M_DEVBUF);
1178 cfg->vpd.vpd_ros = NULL;
1179 }
1180 }
1181 if (state < -1) {
1182 /* I/O error, clean up */
1183 pci_printf(cfg, "failed to read VPD data.\n");
1184 if (cfg->vpd.vpd_ident != NULL) {
1185 free(cfg->vpd.vpd_ident, M_DEVBUF);
1186 cfg->vpd.vpd_ident = NULL;
1187 }
1188 if (cfg->vpd.vpd_w != NULL) {
1189 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1190 free(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1191 free(cfg->vpd.vpd_w, M_DEVBUF);
1192 cfg->vpd.vpd_w = NULL;
1193 }
1194 }
1195 cfg->vpd.vpd_cached = 1;
1196 #undef REG
1197 #undef WREG
1198 }
1199
1200 int
pci_get_vpd_ident_method(device_t dev,device_t child,const char ** identptr)1201 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1202 {
1203 struct pci_devinfo *dinfo = device_get_ivars(child);
1204 pcicfgregs *cfg = &dinfo->cfg;
1205
1206 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1207 pci_read_vpd(device_get_parent(dev), cfg);
1208
1209 *identptr = cfg->vpd.vpd_ident;
1210
1211 if (*identptr == NULL)
1212 return (ENXIO);
1213
1214 return (0);
1215 }
1216
1217 int
pci_get_vpd_readonly_method(device_t dev,device_t child,const char * kw,const char ** vptr)1218 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1219 const char **vptr)
1220 {
1221 struct pci_devinfo *dinfo = device_get_ivars(child);
1222 pcicfgregs *cfg = &dinfo->cfg;
1223 int i;
1224
1225 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1226 pci_read_vpd(device_get_parent(dev), cfg);
1227
1228 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1229 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1230 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1231 *vptr = cfg->vpd.vpd_ros[i].value;
1232 return (0);
1233 }
1234
1235 *vptr = NULL;
1236 return (ENXIO);
1237 }
1238
1239 struct pcicfg_vpd *
pci_fetch_vpd_list(device_t dev)1240 pci_fetch_vpd_list(device_t dev)
1241 {
1242 struct pci_devinfo *dinfo = device_get_ivars(dev);
1243 pcicfgregs *cfg = &dinfo->cfg;
1244
1245 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1246 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg);
1247 return (&cfg->vpd);
1248 }
1249
1250 /*
1251 * Find the requested HyperTransport capability and return the offset
1252 * in configuration space via the pointer provided. The function
1253 * returns 0 on success and an error code otherwise.
1254 */
1255 int
pci_find_htcap_method(device_t dev,device_t child,int capability,int * capreg)1256 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg)
1257 {
1258 int ptr, error;
1259 uint16_t val;
1260
1261 error = pci_find_cap(child, PCIY_HT, &ptr);
1262 if (error)
1263 return (error);
1264
1265 /*
1266 * Traverse the capabilities list checking each HT capability
1267 * to see if it matches the requested HT capability.
1268 */
1269 while (ptr != 0) {
1270 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2);
1271 if (capability == PCIM_HTCAP_SLAVE ||
1272 capability == PCIM_HTCAP_HOST)
1273 val &= 0xe000;
1274 else
1275 val &= PCIM_HTCMD_CAP_MASK;
1276 if (val == capability) {
1277 if (capreg != NULL)
1278 *capreg = ptr;
1279 return (0);
1280 }
1281
1282 /* Skip to the next HT capability. */
1283 while (ptr != 0) {
1284 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1285 if (pci_read_config(child, ptr + PCICAP_ID, 1) ==
1286 PCIY_HT)
1287 break;
1288 }
1289 }
1290 return (ENOENT);
1291 }
1292
1293 /*
1294 * Find the requested capability and return the offset in
1295 * configuration space via the pointer provided. The function returns
1296 * 0 on success and an error code otherwise.
1297 */
1298 int
pci_find_cap_method(device_t dev,device_t child,int capability,int * capreg)1299 pci_find_cap_method(device_t dev, device_t child, int capability,
1300 int *capreg)
1301 {
1302 struct pci_devinfo *dinfo = device_get_ivars(child);
1303 pcicfgregs *cfg = &dinfo->cfg;
1304 u_int32_t status;
1305 u_int8_t ptr;
1306
1307 /*
1308 * Check the CAP_LIST bit of the PCI status register first.
1309 */
1310 status = pci_read_config(child, PCIR_STATUS, 2);
1311 if (!(status & PCIM_STATUS_CAPPRESENT))
1312 return (ENXIO);
1313
1314 /*
1315 * Determine the start pointer of the capabilities list.
1316 */
1317 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1318 case PCIM_HDRTYPE_NORMAL:
1319 case PCIM_HDRTYPE_BRIDGE:
1320 ptr = PCIR_CAP_PTR;
1321 break;
1322 case PCIM_HDRTYPE_CARDBUS:
1323 ptr = PCIR_CAP_PTR_2;
1324 break;
1325 default:
1326 /* XXX: panic? */
1327 return (ENXIO); /* no extended capabilities support */
1328 }
1329 ptr = pci_read_config(child, ptr, 1);
1330
1331 /*
1332 * Traverse the capabilities list.
1333 */
1334 while (ptr != 0) {
1335 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1336 if (capreg != NULL)
1337 *capreg = ptr;
1338 return (0);
1339 }
1340 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1341 }
1342
1343 return (ENOENT);
1344 }
1345
1346 /*
1347 * Find the requested extended capability and return the offset in
1348 * configuration space via the pointer provided. The function returns
1349 * 0 on success and an error code otherwise.
1350 */
1351 int
pci_find_extcap_method(device_t dev,device_t child,int capability,int * capreg)1352 pci_find_extcap_method(device_t dev, device_t child, int capability,
1353 int *capreg)
1354 {
1355 struct pci_devinfo *dinfo = device_get_ivars(child);
1356 pcicfgregs *cfg = &dinfo->cfg;
1357 uint32_t ecap;
1358 uint16_t ptr;
1359
1360 /* Only supported for PCI-express devices. */
1361 if (cfg->pcie.pcie_location == 0)
1362 return (ENXIO);
1363
1364 ptr = PCIR_EXTCAP;
1365 ecap = pci_read_config(child, ptr, 4);
1366 if (ecap == 0xffffffff || ecap == 0)
1367 return (ENOENT);
1368 for (;;) {
1369 if (PCI_EXTCAP_ID(ecap) == capability) {
1370 if (capreg != NULL)
1371 *capreg = ptr;
1372 return (0);
1373 }
1374 ptr = PCI_EXTCAP_NEXTPTR(ecap);
1375 if (ptr == 0)
1376 break;
1377 ecap = pci_read_config(child, ptr, 4);
1378 }
1379
1380 return (ENOENT);
1381 }
1382
1383 /*
1384 * Support for MSI-X message interrupts.
1385 */
1386 void
pci_enable_msix(device_t dev,u_int index,uint64_t address,uint32_t data)1387 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1388 {
1389 struct pci_devinfo *dinfo = device_get_ivars(dev);
1390 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1391 uint32_t offset;
1392
1393 KASSERT(msix->msix_table_len > index, ("bogus index"));
1394 offset = msix->msix_table_offset + index * 16;
1395 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1396 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1397 bus_write_4(msix->msix_table_res, offset + 8, data);
1398
1399 /* Enable MSI -> HT mapping. */
1400 pci_ht_map_msi(dev, address);
1401 }
1402
1403 void
pci_mask_msix(device_t dev,u_int index)1404 pci_mask_msix(device_t dev, u_int index)
1405 {
1406 struct pci_devinfo *dinfo = device_get_ivars(dev);
1407 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1408 uint32_t offset, val;
1409
1410 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1411 offset = msix->msix_table_offset + index * 16 + 12;
1412 val = bus_read_4(msix->msix_table_res, offset);
1413 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1414 val |= PCIM_MSIX_VCTRL_MASK;
1415 bus_write_4(msix->msix_table_res, offset, val);
1416 }
1417 }
1418
1419 void
pci_unmask_msix(device_t dev,u_int index)1420 pci_unmask_msix(device_t dev, u_int index)
1421 {
1422 struct pci_devinfo *dinfo = device_get_ivars(dev);
1423 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1424 uint32_t offset, val;
1425
1426 KASSERT(msix->msix_table_len > index, ("bogus index"));
1427 offset = msix->msix_table_offset + index * 16 + 12;
1428 val = bus_read_4(msix->msix_table_res, offset);
1429 if (val & PCIM_MSIX_VCTRL_MASK) {
1430 val &= ~PCIM_MSIX_VCTRL_MASK;
1431 bus_write_4(msix->msix_table_res, offset, val);
1432 }
1433 }
1434
1435 int
pci_pending_msix(device_t dev,u_int index)1436 pci_pending_msix(device_t dev, u_int index)
1437 {
1438 struct pci_devinfo *dinfo = device_get_ivars(dev);
1439 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1440 uint32_t offset, bit;
1441
1442 KASSERT(msix->msix_table_len > index, ("bogus index"));
1443 offset = msix->msix_pba_offset + (index / 32) * 4;
1444 bit = 1 << index % 32;
1445 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1446 }
1447
1448 /*
1449 * Restore MSI-X registers and table during resume. If MSI-X is
1450 * enabled then walk the virtual table to restore the actual MSI-X
1451 * table.
1452 */
1453 static void
pci_resume_msix(device_t dev)1454 pci_resume_msix(device_t dev)
1455 {
1456 struct pci_devinfo *dinfo = device_get_ivars(dev);
1457 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1458 struct msix_table_entry *mte;
1459 struct msix_vector *mv;
1460 int i;
1461
1462 if (msix->msix_alloc > 0) {
1463 /* First, mask all vectors. */
1464 for (i = 0; i < msix->msix_msgnum; i++)
1465 pci_mask_msix(dev, i);
1466
1467 /* Second, program any messages with at least one handler. */
1468 for (i = 0; i < msix->msix_table_len; i++) {
1469 mte = &msix->msix_table[i];
1470 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1471 continue;
1472 mv = &msix->msix_vectors[mte->mte_vector - 1];
1473 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1474 pci_unmask_msix(dev, i);
1475 }
1476 }
1477 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1478 msix->msix_ctrl, 2);
1479 }
1480
1481 /*
1482 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1483 * returned in *count. After this function returns, each message will be
1484 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1485 */
1486 int
pci_alloc_msix_method(device_t dev,device_t child,int * count)1487 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1488 {
1489 struct pci_devinfo *dinfo = device_get_ivars(child);
1490 pcicfgregs *cfg = &dinfo->cfg;
1491 struct resource_list_entry *rle;
1492 int actual, error, i, irq, max;
1493
1494 /* Don't let count == 0 get us into trouble. */
1495 if (*count == 0)
1496 return (EINVAL);
1497
1498 /* If rid 0 is allocated, then fail. */
1499 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1500 if (rle != NULL && rle->res != NULL)
1501 return (ENXIO);
1502
1503 /* Already have allocated messages? */
1504 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1505 return (ENXIO);
1506
1507 /* If MSI-X is blacklisted for this system, fail. */
1508 if (pci_msix_blacklisted())
1509 return (ENXIO);
1510
1511 /* MSI-X capability present? */
1512 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1513 return (ENODEV);
1514
1515 /* Make sure the appropriate BARs are mapped. */
1516 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1517 cfg->msix.msix_table_bar);
1518 if (rle == NULL || rle->res == NULL ||
1519 !(rman_get_flags(rle->res) & RF_ACTIVE))
1520 return (ENXIO);
1521 cfg->msix.msix_table_res = rle->res;
1522 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1523 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1524 cfg->msix.msix_pba_bar);
1525 if (rle == NULL || rle->res == NULL ||
1526 !(rman_get_flags(rle->res) & RF_ACTIVE))
1527 return (ENXIO);
1528 }
1529 cfg->msix.msix_pba_res = rle->res;
1530
1531 if (bootverbose)
1532 device_printf(child,
1533 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1534 *count, cfg->msix.msix_msgnum);
1535 max = min(*count, cfg->msix.msix_msgnum);
1536 for (i = 0; i < max; i++) {
1537 /* Allocate a message. */
1538 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1539 if (error) {
1540 if (i == 0)
1541 return (error);
1542 break;
1543 }
1544 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1545 irq, 1);
1546 }
1547 actual = i;
1548
1549 if (bootverbose) {
1550 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1551 if (actual == 1)
1552 device_printf(child, "using IRQ %lu for MSI-X\n",
1553 rle->start);
1554 else {
1555 int run;
1556
1557 /*
1558 * Be fancy and try to print contiguous runs of
1559 * IRQ values as ranges. 'irq' is the previous IRQ.
1560 * 'run' is true if we are in a range.
1561 */
1562 device_printf(child, "using IRQs %lu", rle->start);
1563 irq = rle->start;
1564 run = 0;
1565 for (i = 1; i < actual; i++) {
1566 rle = resource_list_find(&dinfo->resources,
1567 SYS_RES_IRQ, i + 1);
1568
1569 /* Still in a run? */
1570 if (rle->start == irq + 1) {
1571 run = 1;
1572 irq++;
1573 continue;
1574 }
1575
1576 /* Finish previous range. */
1577 if (run) {
1578 printf("-%d", irq);
1579 run = 0;
1580 }
1581
1582 /* Start new range. */
1583 printf(",%lu", rle->start);
1584 irq = rle->start;
1585 }
1586
1587 /* Unfinished range? */
1588 if (run)
1589 printf("-%d", irq);
1590 printf(" for MSI-X\n");
1591 }
1592 }
1593
1594 /* Mask all vectors. */
1595 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1596 pci_mask_msix(child, i);
1597
1598 /* Allocate and initialize vector data and virtual table. */
1599 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual,
1600 M_DEVBUF, M_WAITOK | M_ZERO);
1601 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual,
1602 M_DEVBUF, M_WAITOK | M_ZERO);
1603 for (i = 0; i < actual; i++) {
1604 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1605 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1606 cfg->msix.msix_table[i].mte_vector = i + 1;
1607 }
1608
1609 /* Update control register to enable MSI-X. */
1610 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1611 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1612 cfg->msix.msix_ctrl, 2);
1613
1614 /* Update counts of alloc'd messages. */
1615 cfg->msix.msix_alloc = actual;
1616 cfg->msix.msix_table_len = actual;
1617 *count = actual;
1618 return (0);
1619 }
1620
1621 /*
1622 * By default, pci_alloc_msix() will assign the allocated IRQ
1623 * resources consecutively to the first N messages in the MSI-X table.
1624 * However, device drivers may want to use different layouts if they
1625 * either receive fewer messages than they asked for, or they wish to
1626 * populate the MSI-X table sparsely. This method allows the driver
1627 * to specify what layout it wants. It must be called after a
1628 * successful pci_alloc_msix() but before any of the associated
1629 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1630 *
1631 * The 'vectors' array contains 'count' message vectors. The array
1632 * maps directly to the MSI-X table in that index 0 in the array
1633 * specifies the vector for the first message in the MSI-X table, etc.
1634 * The vector value in each array index can either be 0 to indicate
1635 * that no vector should be assigned to a message slot, or it can be a
1636 * number from 1 to N (where N is the count returned from a
1637 * succcessful call to pci_alloc_msix()) to indicate which message
1638 * vector (IRQ) to be used for the corresponding message.
1639 *
1640 * On successful return, each message with a non-zero vector will have
1641 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1642 * 1. Additionally, if any of the IRQs allocated via the previous
1643 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1644 * will be freed back to the system automatically.
1645 *
1646 * For example, suppose a driver has a MSI-X table with 6 messages and
1647 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1648 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1649 * C. After the call to pci_alloc_msix(), the device will be setup to
1650 * have an MSI-X table of ABC--- (where - means no vector assigned).
1651 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 },
1652 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1653 * be freed back to the system. This device will also have valid
1654 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1655 *
1656 * In any case, the SYS_RES_IRQ rid X will always map to the message
1657 * at MSI-X table index X - 1 and will only be valid if a vector is
1658 * assigned to that table entry.
1659 */
1660 int
pci_remap_msix_method(device_t dev,device_t child,int count,const u_int * vectors)1661 pci_remap_msix_method(device_t dev, device_t child, int count,
1662 const u_int *vectors)
1663 {
1664 struct pci_devinfo *dinfo = device_get_ivars(child);
1665 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1666 struct resource_list_entry *rle;
1667 int i, irq, j, *used;
1668
1669 /*
1670 * Have to have at least one message in the table but the
1671 * table can't be bigger than the actual MSI-X table in the
1672 * device.
1673 */
1674 if (count == 0 || count > msix->msix_msgnum)
1675 return (EINVAL);
1676
1677 /* Sanity check the vectors. */
1678 for (i = 0; i < count; i++)
1679 if (vectors[i] > msix->msix_alloc)
1680 return (EINVAL);
1681
1682 /*
1683 * Make sure there aren't any holes in the vectors to be used.
1684 * It's a big pain to support it, and it doesn't really make
1685 * sense anyway. Also, at least one vector must be used.
1686 */
1687 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1688 M_ZERO);
1689 for (i = 0; i < count; i++)
1690 if (vectors[i] != 0)
1691 used[vectors[i] - 1] = 1;
1692 for (i = 0; i < msix->msix_alloc - 1; i++)
1693 if (used[i] == 0 && used[i + 1] == 1) {
1694 free(used, M_DEVBUF);
1695 return (EINVAL);
1696 }
1697 if (used[0] != 1) {
1698 free(used, M_DEVBUF);
1699 return (EINVAL);
1700 }
1701
1702 /* Make sure none of the resources are allocated. */
1703 for (i = 0; i < msix->msix_table_len; i++) {
1704 if (msix->msix_table[i].mte_vector == 0)
1705 continue;
1706 if (msix->msix_table[i].mte_handlers > 0)
1707 return (EBUSY);
1708 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1709 KASSERT(rle != NULL, ("missing resource"));
1710 if (rle->res != NULL)
1711 return (EBUSY);
1712 }
1713
1714 /* Free the existing resource list entries. */
1715 for (i = 0; i < msix->msix_table_len; i++) {
1716 if (msix->msix_table[i].mte_vector == 0)
1717 continue;
1718 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1719 }
1720
1721 /*
1722 * Build the new virtual table keeping track of which vectors are
1723 * used.
1724 */
1725 free(msix->msix_table, M_DEVBUF);
1726 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count,
1727 M_DEVBUF, M_WAITOK | M_ZERO);
1728 for (i = 0; i < count; i++)
1729 msix->msix_table[i].mte_vector = vectors[i];
1730 msix->msix_table_len = count;
1731
1732 /* Free any unused IRQs and resize the vectors array if necessary. */
1733 j = msix->msix_alloc - 1;
1734 if (used[j] == 0) {
1735 struct msix_vector *vec;
1736
1737 while (used[j] == 0) {
1738 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1739 msix->msix_vectors[j].mv_irq);
1740 j--;
1741 }
1742 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1743 M_WAITOK);
1744 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1745 (j + 1));
1746 free(msix->msix_vectors, M_DEVBUF);
1747 msix->msix_vectors = vec;
1748 msix->msix_alloc = j + 1;
1749 }
1750 free(used, M_DEVBUF);
1751
1752 /* Map the IRQs onto the rids. */
1753 for (i = 0; i < count; i++) {
1754 if (vectors[i] == 0)
1755 continue;
1756 irq = msix->msix_vectors[vectors[i]].mv_irq;
1757 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1758 irq, 1);
1759 }
1760
1761 if (bootverbose) {
1762 device_printf(child, "Remapped MSI-X IRQs as: ");
1763 for (i = 0; i < count; i++) {
1764 if (i != 0)
1765 printf(", ");
1766 if (vectors[i] == 0)
1767 printf("---");
1768 else
1769 printf("%d",
1770 msix->msix_vectors[vectors[i]].mv_irq);
1771 }
1772 printf("\n");
1773 }
1774
1775 return (0);
1776 }
1777
1778 static int
pci_release_msix(device_t dev,device_t child)1779 pci_release_msix(device_t dev, device_t child)
1780 {
1781 struct pci_devinfo *dinfo = device_get_ivars(child);
1782 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1783 struct resource_list_entry *rle;
1784 int i;
1785
1786 /* Do we have any messages to release? */
1787 if (msix->msix_alloc == 0)
1788 return (ENODEV);
1789
1790 /* Make sure none of the resources are allocated. */
1791 for (i = 0; i < msix->msix_table_len; i++) {
1792 if (msix->msix_table[i].mte_vector == 0)
1793 continue;
1794 if (msix->msix_table[i].mte_handlers > 0)
1795 return (EBUSY);
1796 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1797 KASSERT(rle != NULL, ("missing resource"));
1798 if (rle->res != NULL)
1799 return (EBUSY);
1800 }
1801
1802 /* Update control register to disable MSI-X. */
1803 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1804 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1805 msix->msix_ctrl, 2);
1806
1807 /* Free the resource list entries. */
1808 for (i = 0; i < msix->msix_table_len; i++) {
1809 if (msix->msix_table[i].mte_vector == 0)
1810 continue;
1811 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1812 }
1813 free(msix->msix_table, M_DEVBUF);
1814 msix->msix_table_len = 0;
1815
1816 /* Release the IRQs. */
1817 for (i = 0; i < msix->msix_alloc; i++)
1818 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1819 msix->msix_vectors[i].mv_irq);
1820 free(msix->msix_vectors, M_DEVBUF);
1821 msix->msix_alloc = 0;
1822 return (0);
1823 }
1824
1825 /*
1826 * Return the max supported MSI-X messages this device supports.
1827 * Basically, assuming the MD code can alloc messages, this function
1828 * should return the maximum value that pci_alloc_msix() can return.
1829 * Thus, it is subject to the tunables, etc.
1830 */
1831 int
pci_msix_count_method(device_t dev,device_t child)1832 pci_msix_count_method(device_t dev, device_t child)
1833 {
1834 struct pci_devinfo *dinfo = device_get_ivars(child);
1835 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1836
1837 if (pci_do_msix && msix->msix_location != 0)
1838 return (msix->msix_msgnum);
1839 return (0);
1840 }
1841
1842 /*
1843 * HyperTransport MSI mapping control
1844 */
1845 void
pci_ht_map_msi(device_t dev,uint64_t addr)1846 pci_ht_map_msi(device_t dev, uint64_t addr)
1847 {
1848 struct pci_devinfo *dinfo = device_get_ivars(dev);
1849 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1850
1851 if (!ht->ht_msimap)
1852 return;
1853
1854 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1855 ht->ht_msiaddr >> 20 == addr >> 20) {
1856 /* Enable MSI -> HT mapping. */
1857 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1858 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1859 ht->ht_msictrl, 2);
1860 }
1861
1862 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1863 /* Disable MSI -> HT mapping. */
1864 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1865 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1866 ht->ht_msictrl, 2);
1867 }
1868 }
1869
1870 int
pci_get_max_read_req(device_t dev)1871 pci_get_max_read_req(device_t dev)
1872 {
1873 struct pci_devinfo *dinfo = device_get_ivars(dev);
1874 int cap;
1875 uint16_t val;
1876
1877 cap = dinfo->cfg.pcie.pcie_location;
1878 if (cap == 0)
1879 return (0);
1880 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
1881 val &= PCIEM_CTL_MAX_READ_REQUEST;
1882 val >>= 12;
1883 return (1 << (val + 7));
1884 }
1885
1886 int
pci_set_max_read_req(device_t dev,int size)1887 pci_set_max_read_req(device_t dev, int size)
1888 {
1889 struct pci_devinfo *dinfo = device_get_ivars(dev);
1890 int cap;
1891 uint16_t val;
1892
1893 cap = dinfo->cfg.pcie.pcie_location;
1894 if (cap == 0)
1895 return (0);
1896 if (size < 128)
1897 size = 128;
1898 if (size > 4096)
1899 size = 4096;
1900 size = (1 << (fls(size) - 1));
1901 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
1902 val &= ~PCIEM_CTL_MAX_READ_REQUEST;
1903 val |= (fls(size) - 8) << 12;
1904 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2);
1905 return (size);
1906 }
1907
1908 /*
1909 * Support for MSI message signalled interrupts.
1910 */
1911 void
pci_enable_msi(device_t dev,uint64_t address,uint16_t data)1912 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1913 {
1914 struct pci_devinfo *dinfo = device_get_ivars(dev);
1915 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1916
1917 /* Write data and address values. */
1918 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1919 address & 0xffffffff, 4);
1920 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1921 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1922 address >> 32, 4);
1923 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1924 data, 2);
1925 } else
1926 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1927 2);
1928
1929 /* Enable MSI in the control register. */
1930 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1931 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1932 2);
1933
1934 /* Enable MSI -> HT mapping. */
1935 pci_ht_map_msi(dev, address);
1936 }
1937
1938 void
pci_disable_msi(device_t dev)1939 pci_disable_msi(device_t dev)
1940 {
1941 struct pci_devinfo *dinfo = device_get_ivars(dev);
1942 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1943
1944 /* Disable MSI -> HT mapping. */
1945 pci_ht_map_msi(dev, 0);
1946
1947 /* Disable MSI in the control register. */
1948 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1949 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1950 2);
1951 }
1952
1953 /*
1954 * Restore MSI registers during resume. If MSI is enabled then
1955 * restore the data and address registers in addition to the control
1956 * register.
1957 */
1958 static void
pci_resume_msi(device_t dev)1959 pci_resume_msi(device_t dev)
1960 {
1961 struct pci_devinfo *dinfo = device_get_ivars(dev);
1962 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1963 uint64_t address;
1964 uint16_t data;
1965
1966 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1967 address = msi->msi_addr;
1968 data = msi->msi_data;
1969 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1970 address & 0xffffffff, 4);
1971 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1972 pci_write_config(dev, msi->msi_location +
1973 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1974 pci_write_config(dev, msi->msi_location +
1975 PCIR_MSI_DATA_64BIT, data, 2);
1976 } else
1977 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1978 data, 2);
1979 }
1980 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1981 2);
1982 }
1983
1984 static int
pci_remap_intr_method(device_t bus,device_t dev,u_int irq)1985 pci_remap_intr_method(device_t bus, device_t dev, u_int irq)
1986 {
1987 struct pci_devinfo *dinfo = device_get_ivars(dev);
1988 pcicfgregs *cfg = &dinfo->cfg;
1989 struct resource_list_entry *rle;
1990 struct msix_table_entry *mte;
1991 struct msix_vector *mv;
1992 uint64_t addr;
1993 uint32_t data;
1994 int error, i, j;
1995
1996 /*
1997 * Handle MSI first. We try to find this IRQ among our list
1998 * of MSI IRQs. If we find it, we request updated address and
1999 * data registers and apply the results.
2000 */
2001 if (cfg->msi.msi_alloc > 0) {
2002
2003 /* If we don't have any active handlers, nothing to do. */
2004 if (cfg->msi.msi_handlers == 0)
2005 return (0);
2006 for (i = 0; i < cfg->msi.msi_alloc; i++) {
2007 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
2008 i + 1);
2009 if (rle->start == irq) {
2010 error = PCIB_MAP_MSI(device_get_parent(bus),
2011 dev, irq, &addr, &data);
2012 if (error)
2013 return (error);
2014 pci_disable_msi(dev);
2015 dinfo->cfg.msi.msi_addr = addr;
2016 dinfo->cfg.msi.msi_data = data;
2017 pci_enable_msi(dev, addr, data);
2018 return (0);
2019 }
2020 }
2021 return (ENOENT);
2022 }
2023
2024 /*
2025 * For MSI-X, we check to see if we have this IRQ. If we do,
2026 * we request the updated mapping info. If that works, we go
2027 * through all the slots that use this IRQ and update them.
2028 */
2029 if (cfg->msix.msix_alloc > 0) {
2030 for (i = 0; i < cfg->msix.msix_alloc; i++) {
2031 mv = &cfg->msix.msix_vectors[i];
2032 if (mv->mv_irq == irq) {
2033 error = PCIB_MAP_MSI(device_get_parent(bus),
2034 dev, irq, &addr, &data);
2035 if (error)
2036 return (error);
2037 mv->mv_address = addr;
2038 mv->mv_data = data;
2039 for (j = 0; j < cfg->msix.msix_table_len; j++) {
2040 mte = &cfg->msix.msix_table[j];
2041 if (mte->mte_vector != i + 1)
2042 continue;
2043 if (mte->mte_handlers == 0)
2044 continue;
2045 pci_mask_msix(dev, j);
2046 pci_enable_msix(dev, j, addr, data);
2047 pci_unmask_msix(dev, j);
2048 }
2049 }
2050 }
2051 return (ENOENT);
2052 }
2053
2054 return (ENOENT);
2055 }
2056
2057 /*
2058 * Returns true if the specified device is blacklisted because MSI
2059 * doesn't work.
2060 */
2061 int
pci_msi_device_blacklisted(device_t dev)2062 pci_msi_device_blacklisted(device_t dev)
2063 {
2064
2065 if (!pci_honor_msi_blacklist)
2066 return (0);
2067
2068 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI));
2069 }
2070
2071 /*
2072 * Determine if MSI is blacklisted globally on this system. Currently,
2073 * we just check for blacklisted chipsets as represented by the
2074 * host-PCI bridge at device 0:0:0. In the future, it may become
2075 * necessary to check other system attributes, such as the kenv values
2076 * that give the motherboard manufacturer and model number.
2077 */
2078 static int
pci_msi_blacklisted(void)2079 pci_msi_blacklisted(void)
2080 {
2081 device_t dev;
2082
2083 if (!pci_honor_msi_blacklist)
2084 return (0);
2085
2086 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
2087 if (!(pcie_chipset || pcix_chipset)) {
2088 if (vm_guest != VM_GUEST_NO) {
2089 /*
2090 * Whitelist older chipsets in virtual
2091 * machines known to support MSI.
2092 */
2093 dev = pci_find_bsf(0, 0, 0);
2094 if (dev != NULL)
2095 return (!pci_has_quirk(pci_get_devid(dev),
2096 PCI_QUIRK_ENABLE_MSI_VM));
2097 }
2098 return (1);
2099 }
2100
2101 dev = pci_find_bsf(0, 0, 0);
2102 if (dev != NULL)
2103 return (pci_msi_device_blacklisted(dev));
2104 return (0);
2105 }
2106
2107 /*
2108 * Returns true if the specified device is blacklisted because MSI-X
2109 * doesn't work. Note that this assumes that if MSI doesn't work,
2110 * MSI-X doesn't either.
2111 */
2112 int
pci_msix_device_blacklisted(device_t dev)2113 pci_msix_device_blacklisted(device_t dev)
2114 {
2115
2116 if (!pci_honor_msi_blacklist)
2117 return (0);
2118
2119 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX))
2120 return (1);
2121
2122 return (pci_msi_device_blacklisted(dev));
2123 }
2124
2125 /*
2126 * Determine if MSI-X is blacklisted globally on this system. If MSI
2127 * is blacklisted, assume that MSI-X is as well. Check for additional
2128 * chipsets where MSI works but MSI-X does not.
2129 */
2130 static int
pci_msix_blacklisted(void)2131 pci_msix_blacklisted(void)
2132 {
2133 device_t dev;
2134
2135 if (!pci_honor_msi_blacklist)
2136 return (0);
2137
2138 dev = pci_find_bsf(0, 0, 0);
2139 if (dev != NULL && pci_has_quirk(pci_get_devid(dev),
2140 PCI_QUIRK_DISABLE_MSIX))
2141 return (1);
2142
2143 return (pci_msi_blacklisted());
2144 }
2145
2146 /*
2147 * Attempt to allocate *count MSI messages. The actual number allocated is
2148 * returned in *count. After this function returns, each message will be
2149 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
2150 */
2151 int
pci_alloc_msi_method(device_t dev,device_t child,int * count)2152 pci_alloc_msi_method(device_t dev, device_t child, int *count)
2153 {
2154 struct pci_devinfo *dinfo = device_get_ivars(child);
2155 pcicfgregs *cfg = &dinfo->cfg;
2156 struct resource_list_entry *rle;
2157 int actual, error, i, irqs[32];
2158 uint16_t ctrl;
2159
2160 /* Don't let count == 0 get us into trouble. */
2161 if (*count == 0)
2162 return (EINVAL);
2163
2164 /* If rid 0 is allocated, then fail. */
2165 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
2166 if (rle != NULL && rle->res != NULL)
2167 return (ENXIO);
2168
2169 /* Already have allocated messages? */
2170 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
2171 return (ENXIO);
2172
2173 /* If MSI is blacklisted for this system, fail. */
2174 if (pci_msi_blacklisted())
2175 return (ENXIO);
2176
2177 /* MSI capability present? */
2178 if (cfg->msi.msi_location == 0 || !pci_do_msi)
2179 return (ENODEV);
2180
2181 if (bootverbose)
2182 device_printf(child,
2183 "attempting to allocate %d MSI vectors (%d supported)\n",
2184 *count, cfg->msi.msi_msgnum);
2185
2186 /* Don't ask for more than the device supports. */
2187 actual = min(*count, cfg->msi.msi_msgnum);
2188
2189 /* Don't ask for more than 32 messages. */
2190 actual = min(actual, 32);
2191
2192 /* MSI requires power of 2 number of messages. */
2193 if (!powerof2(actual))
2194 return (EINVAL);
2195
2196 for (;;) {
2197 /* Try to allocate N messages. */
2198 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
2199 actual, irqs);
2200 if (error == 0)
2201 break;
2202 if (actual == 1)
2203 return (error);
2204
2205 /* Try N / 2. */
2206 actual >>= 1;
2207 }
2208
2209 /*
2210 * We now have N actual messages mapped onto SYS_RES_IRQ
2211 * resources in the irqs[] array, so add new resources
2212 * starting at rid 1.
2213 */
2214 for (i = 0; i < actual; i++)
2215 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2216 irqs[i], irqs[i], 1);
2217
2218 if (bootverbose) {
2219 if (actual == 1)
2220 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
2221 else {
2222 int run;
2223
2224 /*
2225 * Be fancy and try to print contiguous runs
2226 * of IRQ values as ranges. 'run' is true if
2227 * we are in a range.
2228 */
2229 device_printf(child, "using IRQs %d", irqs[0]);
2230 run = 0;
2231 for (i = 1; i < actual; i++) {
2232
2233 /* Still in a run? */
2234 if (irqs[i] == irqs[i - 1] + 1) {
2235 run = 1;
2236 continue;
2237 }
2238
2239 /* Finish previous range. */
2240 if (run) {
2241 printf("-%d", irqs[i - 1]);
2242 run = 0;
2243 }
2244
2245 /* Start new range. */
2246 printf(",%d", irqs[i]);
2247 }
2248
2249 /* Unfinished range? */
2250 if (run)
2251 printf("-%d", irqs[actual - 1]);
2252 printf(" for MSI\n");
2253 }
2254 }
2255
2256 /* Update control register with actual count. */
2257 ctrl = cfg->msi.msi_ctrl;
2258 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2259 ctrl |= (ffs(actual) - 1) << 4;
2260 cfg->msi.msi_ctrl = ctrl;
2261 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2262
2263 /* Update counts of alloc'd messages. */
2264 cfg->msi.msi_alloc = actual;
2265 cfg->msi.msi_handlers = 0;
2266 *count = actual;
2267 return (0);
2268 }
2269
2270 /* Release the MSI messages associated with this device. */
2271 int
pci_release_msi_method(device_t dev,device_t child)2272 pci_release_msi_method(device_t dev, device_t child)
2273 {
2274 struct pci_devinfo *dinfo = device_get_ivars(child);
2275 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2276 struct resource_list_entry *rle;
2277 int error, i, irqs[32];
2278
2279 /* Try MSI-X first. */
2280 error = pci_release_msix(dev, child);
2281 if (error != ENODEV)
2282 return (error);
2283
2284 /* Do we have any messages to release? */
2285 if (msi->msi_alloc == 0)
2286 return (ENODEV);
2287 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2288
2289 /* Make sure none of the resources are allocated. */
2290 if (msi->msi_handlers > 0)
2291 return (EBUSY);
2292 for (i = 0; i < msi->msi_alloc; i++) {
2293 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2294 KASSERT(rle != NULL, ("missing MSI resource"));
2295 if (rle->res != NULL)
2296 return (EBUSY);
2297 irqs[i] = rle->start;
2298 }
2299
2300 /* Update control register with 0 count. */
2301 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2302 ("%s: MSI still enabled", __func__));
2303 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2304 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2305 msi->msi_ctrl, 2);
2306
2307 /* Release the messages. */
2308 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2309 for (i = 0; i < msi->msi_alloc; i++)
2310 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2311
2312 /* Update alloc count. */
2313 msi->msi_alloc = 0;
2314 msi->msi_addr = 0;
2315 msi->msi_data = 0;
2316 return (0);
2317 }
2318
2319 /*
2320 * Return the max supported MSI messages this device supports.
2321 * Basically, assuming the MD code can alloc messages, this function
2322 * should return the maximum value that pci_alloc_msi() can return.
2323 * Thus, it is subject to the tunables, etc.
2324 */
2325 int
pci_msi_count_method(device_t dev,device_t child)2326 pci_msi_count_method(device_t dev, device_t child)
2327 {
2328 struct pci_devinfo *dinfo = device_get_ivars(child);
2329 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2330
2331 if (pci_do_msi && msi->msi_location != 0)
2332 return (msi->msi_msgnum);
2333 return (0);
2334 }
2335
2336 /* free pcicfgregs structure and all depending data structures */
2337
2338 int
pci_freecfg(struct pci_devinfo * dinfo)2339 pci_freecfg(struct pci_devinfo *dinfo)
2340 {
2341 struct devlist *devlist_head;
2342 struct pci_map *pm, *next;
2343 int i;
2344
2345 devlist_head = &pci_devq;
2346
2347 if (dinfo->cfg.vpd.vpd_reg) {
2348 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2349 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2350 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2351 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2352 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2353 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2354 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2355 }
2356 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) {
2357 free(pm, M_DEVBUF);
2358 }
2359 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2360 free(dinfo, M_DEVBUF);
2361
2362 /* increment the generation count */
2363 pci_generation++;
2364
2365 /* we're losing one device */
2366 pci_numdevs--;
2367 return (0);
2368 }
2369
2370 /*
2371 * PCI power manangement
2372 */
2373 int
pci_set_powerstate_method(device_t dev,device_t child,int state)2374 pci_set_powerstate_method(device_t dev, device_t child, int state)
2375 {
2376 struct pci_devinfo *dinfo = device_get_ivars(child);
2377 pcicfgregs *cfg = &dinfo->cfg;
2378 uint16_t status;
2379 int oldstate, highest, delay;
2380
2381 if (cfg->pp.pp_cap == 0)
2382 return (EOPNOTSUPP);
2383
2384 /*
2385 * Optimize a no state change request away. While it would be OK to
2386 * write to the hardware in theory, some devices have shown odd
2387 * behavior when going from D3 -> D3.
2388 */
2389 oldstate = pci_get_powerstate(child);
2390 if (oldstate == state)
2391 return (0);
2392
2393 /*
2394 * The PCI power management specification states that after a state
2395 * transition between PCI power states, system software must
2396 * guarantee a minimal delay before the function accesses the device.
2397 * Compute the worst case delay that we need to guarantee before we
2398 * access the device. Many devices will be responsive much more
2399 * quickly than this delay, but there are some that don't respond
2400 * instantly to state changes. Transitions to/from D3 state require
2401 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2402 * is done below with DELAY rather than a sleeper function because
2403 * this function can be called from contexts where we cannot sleep.
2404 */
2405 highest = (oldstate > state) ? oldstate : state;
2406 if (highest == PCI_POWERSTATE_D3)
2407 delay = 10000;
2408 else if (highest == PCI_POWERSTATE_D2)
2409 delay = 200;
2410 else
2411 delay = 0;
2412 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2413 & ~PCIM_PSTAT_DMASK;
2414 switch (state) {
2415 case PCI_POWERSTATE_D0:
2416 status |= PCIM_PSTAT_D0;
2417 break;
2418 case PCI_POWERSTATE_D1:
2419 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2420 return (EOPNOTSUPP);
2421 status |= PCIM_PSTAT_D1;
2422 break;
2423 case PCI_POWERSTATE_D2:
2424 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2425 return (EOPNOTSUPP);
2426 status |= PCIM_PSTAT_D2;
2427 break;
2428 case PCI_POWERSTATE_D3:
2429 status |= PCIM_PSTAT_D3;
2430 break;
2431 default:
2432 return (EINVAL);
2433 }
2434
2435 if (bootverbose)
2436 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate,
2437 state);
2438
2439 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2440 if (delay)
2441 DELAY(delay);
2442 return (0);
2443 }
2444
2445 int
pci_get_powerstate_method(device_t dev,device_t child)2446 pci_get_powerstate_method(device_t dev, device_t child)
2447 {
2448 struct pci_devinfo *dinfo = device_get_ivars(child);
2449 pcicfgregs *cfg = &dinfo->cfg;
2450 uint16_t status;
2451 int result;
2452
2453 if (cfg->pp.pp_cap != 0) {
2454 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2455 switch (status & PCIM_PSTAT_DMASK) {
2456 case PCIM_PSTAT_D0:
2457 result = PCI_POWERSTATE_D0;
2458 break;
2459 case PCIM_PSTAT_D1:
2460 result = PCI_POWERSTATE_D1;
2461 break;
2462 case PCIM_PSTAT_D2:
2463 result = PCI_POWERSTATE_D2;
2464 break;
2465 case PCIM_PSTAT_D3:
2466 result = PCI_POWERSTATE_D3;
2467 break;
2468 default:
2469 result = PCI_POWERSTATE_UNKNOWN;
2470 break;
2471 }
2472 } else {
2473 /* No support, device is always at D0 */
2474 result = PCI_POWERSTATE_D0;
2475 }
2476 return (result);
2477 }
2478
2479 /*
2480 * Some convenience functions for PCI device drivers.
2481 */
2482
2483 static __inline void
pci_set_command_bit(device_t dev,device_t child,uint16_t bit)2484 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2485 {
2486 uint16_t command;
2487
2488 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2489 command |= bit;
2490 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2491 }
2492
2493 static __inline void
pci_clear_command_bit(device_t dev,device_t child,uint16_t bit)2494 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2495 {
2496 uint16_t command;
2497
2498 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2499 command &= ~bit;
2500 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2501 }
2502
2503 int
pci_enable_busmaster_method(device_t dev,device_t child)2504 pci_enable_busmaster_method(device_t dev, device_t child)
2505 {
2506 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2507 return (0);
2508 }
2509
2510 int
pci_disable_busmaster_method(device_t dev,device_t child)2511 pci_disable_busmaster_method(device_t dev, device_t child)
2512 {
2513 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2514 return (0);
2515 }
2516
2517 int
pci_enable_io_method(device_t dev,device_t child,int space)2518 pci_enable_io_method(device_t dev, device_t child, int space)
2519 {
2520 uint16_t bit;
2521
2522 switch(space) {
2523 case SYS_RES_IOPORT:
2524 bit = PCIM_CMD_PORTEN;
2525 break;
2526 case SYS_RES_MEMORY:
2527 bit = PCIM_CMD_MEMEN;
2528 break;
2529 default:
2530 return (EINVAL);
2531 }
2532 pci_set_command_bit(dev, child, bit);
2533 return (0);
2534 }
2535
2536 int
pci_disable_io_method(device_t dev,device_t child,int space)2537 pci_disable_io_method(device_t dev, device_t child, int space)
2538 {
2539 uint16_t bit;
2540
2541 switch(space) {
2542 case SYS_RES_IOPORT:
2543 bit = PCIM_CMD_PORTEN;
2544 break;
2545 case SYS_RES_MEMORY:
2546 bit = PCIM_CMD_MEMEN;
2547 break;
2548 default:
2549 return (EINVAL);
2550 }
2551 pci_clear_command_bit(dev, child, bit);
2552 return (0);
2553 }
2554
2555 /*
2556 * New style pci driver. Parent device is either a pci-host-bridge or a
2557 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2558 */
2559
2560 void
pci_print_verbose(struct pci_devinfo * dinfo)2561 pci_print_verbose(struct pci_devinfo *dinfo)
2562 {
2563
2564 if (bootverbose) {
2565 pcicfgregs *cfg = &dinfo->cfg;
2566
2567 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2568 cfg->vendor, cfg->device, cfg->revid);
2569 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2570 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2571 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2572 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2573 cfg->mfdev);
2574 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2575 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2576 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2577 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2578 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2579 if (cfg->intpin > 0)
2580 printf("\tintpin=%c, irq=%d\n",
2581 cfg->intpin +'a' -1, cfg->intline);
2582 if (cfg->pp.pp_cap) {
2583 uint16_t status;
2584
2585 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2586 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2587 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2588 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2589 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2590 status & PCIM_PSTAT_DMASK);
2591 }
2592 if (cfg->msi.msi_location) {
2593 int ctrl;
2594
2595 ctrl = cfg->msi.msi_ctrl;
2596 printf("\tMSI supports %d message%s%s%s\n",
2597 cfg->msi.msi_msgnum,
2598 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2599 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2600 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2601 }
2602 if (cfg->msix.msix_location) {
2603 printf("\tMSI-X supports %d message%s ",
2604 cfg->msix.msix_msgnum,
2605 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2606 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2607 printf("in map 0x%x\n",
2608 cfg->msix.msix_table_bar);
2609 else
2610 printf("in maps 0x%x and 0x%x\n",
2611 cfg->msix.msix_table_bar,
2612 cfg->msix.msix_pba_bar);
2613 }
2614 }
2615 }
2616
2617 static int
pci_porten(device_t dev)2618 pci_porten(device_t dev)
2619 {
2620 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0;
2621 }
2622
2623 static int
pci_memen(device_t dev)2624 pci_memen(device_t dev)
2625 {
2626 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0;
2627 }
2628
2629 static void
pci_read_bar(device_t dev,int reg,pci_addr_t * mapp,pci_addr_t * testvalp)2630 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp)
2631 {
2632 struct pci_devinfo *dinfo;
2633 pci_addr_t map, testval;
2634 int ln2range;
2635 uint16_t cmd;
2636
2637 /*
2638 * The device ROM BAR is special. It is always a 32-bit
2639 * memory BAR. Bit 0 is special and should not be set when
2640 * sizing the BAR.
2641 */
2642 dinfo = device_get_ivars(dev);
2643 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) {
2644 map = pci_read_config(dev, reg, 4);
2645 pci_write_config(dev, reg, 0xfffffffe, 4);
2646 testval = pci_read_config(dev, reg, 4);
2647 pci_write_config(dev, reg, map, 4);
2648 *mapp = map;
2649 *testvalp = testval;
2650 return;
2651 }
2652
2653 map = pci_read_config(dev, reg, 4);
2654 ln2range = pci_maprange(map);
2655 if (ln2range == 64)
2656 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2657
2658 /*
2659 * Disable decoding via the command register before
2660 * determining the BAR's length since we will be placing it in
2661 * a weird state.
2662 */
2663 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2664 pci_write_config(dev, PCIR_COMMAND,
2665 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
2666
2667 /*
2668 * Determine the BAR's length by writing all 1's. The bottom
2669 * log_2(size) bits of the BAR will stick as 0 when we read
2670 * the value back.
2671 */
2672 pci_write_config(dev, reg, 0xffffffff, 4);
2673 testval = pci_read_config(dev, reg, 4);
2674 if (ln2range == 64) {
2675 pci_write_config(dev, reg + 4, 0xffffffff, 4);
2676 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2677 }
2678
2679 /*
2680 * Restore the original value of the BAR. We may have reprogrammed
2681 * the BAR of the low-level console device and when booting verbose,
2682 * we need the console device addressable.
2683 */
2684 pci_write_config(dev, reg, map, 4);
2685 if (ln2range == 64)
2686 pci_write_config(dev, reg + 4, map >> 32, 4);
2687 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2688
2689 *mapp = map;
2690 *testvalp = testval;
2691 }
2692
2693 static void
pci_write_bar(device_t dev,struct pci_map * pm,pci_addr_t base)2694 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base)
2695 {
2696 struct pci_devinfo *dinfo;
2697 int ln2range;
2698
2699 /* The device ROM BAR is always a 32-bit memory BAR. */
2700 dinfo = device_get_ivars(dev);
2701 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
2702 ln2range = 32;
2703 else
2704 ln2range = pci_maprange(pm->pm_value);
2705 pci_write_config(dev, pm->pm_reg, base, 4);
2706 if (ln2range == 64)
2707 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4);
2708 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4);
2709 if (ln2range == 64)
2710 pm->pm_value |= (pci_addr_t)pci_read_config(dev,
2711 pm->pm_reg + 4, 4) << 32;
2712 }
2713
2714 struct pci_map *
pci_find_bar(device_t dev,int reg)2715 pci_find_bar(device_t dev, int reg)
2716 {
2717 struct pci_devinfo *dinfo;
2718 struct pci_map *pm;
2719
2720 dinfo = device_get_ivars(dev);
2721 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
2722 if (pm->pm_reg == reg)
2723 return (pm);
2724 }
2725 return (NULL);
2726 }
2727
2728 int
pci_bar_enabled(device_t dev,struct pci_map * pm)2729 pci_bar_enabled(device_t dev, struct pci_map *pm)
2730 {
2731 struct pci_devinfo *dinfo;
2732 uint16_t cmd;
2733
2734 dinfo = device_get_ivars(dev);
2735 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) &&
2736 !(pm->pm_value & PCIM_BIOS_ENABLE))
2737 return (0);
2738 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2739 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value))
2740 return ((cmd & PCIM_CMD_MEMEN) != 0);
2741 else
2742 return ((cmd & PCIM_CMD_PORTEN) != 0);
2743 }
2744
2745 static struct pci_map *
pci_add_bar(device_t dev,int reg,pci_addr_t value,pci_addr_t size)2746 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size)
2747 {
2748 struct pci_devinfo *dinfo;
2749 struct pci_map *pm, *prev;
2750
2751 dinfo = device_get_ivars(dev);
2752 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO);
2753 pm->pm_reg = reg;
2754 pm->pm_value = value;
2755 pm->pm_size = size;
2756 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) {
2757 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x",
2758 reg));
2759 if (STAILQ_NEXT(prev, pm_link) == NULL ||
2760 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg)
2761 break;
2762 }
2763 if (prev != NULL)
2764 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link);
2765 else
2766 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link);
2767 return (pm);
2768 }
2769
2770 static void
pci_restore_bars(device_t dev)2771 pci_restore_bars(device_t dev)
2772 {
2773 struct pci_devinfo *dinfo;
2774 struct pci_map *pm;
2775 int ln2range;
2776
2777 dinfo = device_get_ivars(dev);
2778 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
2779 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
2780 ln2range = 32;
2781 else
2782 ln2range = pci_maprange(pm->pm_value);
2783 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4);
2784 if (ln2range == 64)
2785 pci_write_config(dev, pm->pm_reg + 4,
2786 pm->pm_value >> 32, 4);
2787 }
2788 }
2789
2790 /*
2791 * Add a resource based on a pci map register. Return 1 if the map
2792 * register is a 32bit map register or 2 if it is a 64bit register.
2793 */
2794 static int
pci_add_map(device_t bus,device_t dev,int reg,struct resource_list * rl,int force,int prefetch)2795 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl,
2796 int force, int prefetch)
2797 {
2798 struct pci_map *pm;
2799 pci_addr_t base, map, testval;
2800 pci_addr_t start, end, count;
2801 int barlen, basezero, flags, maprange, mapsize, type;
2802 uint16_t cmd;
2803 struct resource *res;
2804
2805 /*
2806 * The BAR may already exist if the device is a CardBus card
2807 * whose CIS is stored in this BAR.
2808 */
2809 pm = pci_find_bar(dev, reg);
2810 if (pm != NULL) {
2811 maprange = pci_maprange(pm->pm_value);
2812 barlen = maprange == 64 ? 2 : 1;
2813 return (barlen);
2814 }
2815
2816 pci_read_bar(dev, reg, &map, &testval);
2817 if (PCI_BAR_MEM(map)) {
2818 type = SYS_RES_MEMORY;
2819 if (map & PCIM_BAR_MEM_PREFETCH)
2820 prefetch = 1;
2821 } else
2822 type = SYS_RES_IOPORT;
2823 mapsize = pci_mapsize(testval);
2824 base = pci_mapbase(map);
2825 #ifdef __PCI_BAR_ZERO_VALID
2826 basezero = 0;
2827 #else
2828 basezero = base == 0;
2829 #endif
2830 maprange = pci_maprange(map);
2831 barlen = maprange == 64 ? 2 : 1;
2832
2833 /*
2834 * For I/O registers, if bottom bit is set, and the next bit up
2835 * isn't clear, we know we have a BAR that doesn't conform to the
2836 * spec, so ignore it. Also, sanity check the size of the data
2837 * areas to the type of memory involved. Memory must be at least
2838 * 16 bytes in size, while I/O ranges must be at least 4.
2839 */
2840 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2841 return (barlen);
2842 if ((type == SYS_RES_MEMORY && mapsize < 4) ||
2843 (type == SYS_RES_IOPORT && mapsize < 2))
2844 return (barlen);
2845
2846 /* Save a record of this BAR. */
2847 pm = pci_add_bar(dev, reg, map, mapsize);
2848 if (bootverbose) {
2849 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2850 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize);
2851 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2852 printf(", port disabled\n");
2853 else if (type == SYS_RES_MEMORY && !pci_memen(dev))
2854 printf(", memory disabled\n");
2855 else
2856 printf(", enabled\n");
2857 }
2858
2859 /*
2860 * If base is 0, then we have problems if this architecture does
2861 * not allow that. It is best to ignore such entries for the
2862 * moment. These will be allocated later if the driver specifically
2863 * requests them. However, some removable busses look better when
2864 * all resources are allocated, so allow '0' to be overriden.
2865 *
2866 * Similarly treat maps whose values is the same as the test value
2867 * read back. These maps have had all f's written to them by the
2868 * BIOS in an attempt to disable the resources.
2869 */
2870 if (!force && (basezero || map == testval))
2871 return (barlen);
2872 if ((u_long)base != base) {
2873 device_printf(bus,
2874 "pci%d:%d:%d:%d bar %#x too many address bits",
2875 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev),
2876 pci_get_function(dev), reg);
2877 return (barlen);
2878 }
2879
2880 /*
2881 * This code theoretically does the right thing, but has
2882 * undesirable side effects in some cases where peripherals
2883 * respond oddly to having these bits enabled. Let the user
2884 * be able to turn them off (since pci_enable_io_modes is 1 by
2885 * default).
2886 */
2887 if (pci_enable_io_modes) {
2888 /* Turn on resources that have been left off by a lazy BIOS */
2889 if (type == SYS_RES_IOPORT && !pci_porten(dev)) {
2890 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2891 cmd |= PCIM_CMD_PORTEN;
2892 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2893 }
2894 if (type == SYS_RES_MEMORY && !pci_memen(dev)) {
2895 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2896 cmd |= PCIM_CMD_MEMEN;
2897 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2898 }
2899 } else {
2900 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2901 return (barlen);
2902 if (type == SYS_RES_MEMORY && !pci_memen(dev))
2903 return (barlen);
2904 }
2905
2906 count = (pci_addr_t)1 << mapsize;
2907 flags = RF_ALIGNMENT_LOG2(mapsize);
2908 if (prefetch)
2909 flags |= RF_PREFETCHABLE;
2910 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) {
2911 start = 0; /* Let the parent decide. */
2912 end = ~0ul;
2913 } else {
2914 start = base;
2915 end = base + count - 1;
2916 }
2917 resource_list_add(rl, type, reg, start, end, count);
2918
2919 /*
2920 * Try to allocate the resource for this BAR from our parent
2921 * so that this resource range is already reserved. The
2922 * driver for this device will later inherit this resource in
2923 * pci_alloc_resource().
2924 */
2925 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count,
2926 flags);
2927 if (pci_do_realloc_bars && res == NULL && (start != 0 || end != ~0ul)) {
2928 /*
2929 * If the allocation fails, try to allocate a resource for
2930 * this BAR using any available range. The firmware felt
2931 * it was important enough to assign a resource, so don't
2932 * disable decoding if we can help it.
2933 */
2934 resource_list_delete(rl, type, reg);
2935 resource_list_add(rl, type, reg, 0, ~0ul, count);
2936 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0ul,
2937 count, flags);
2938 }
2939 if (res == NULL) {
2940 /*
2941 * If the allocation fails, delete the resource list entry
2942 * and disable decoding for this device.
2943 *
2944 * If the driver requests this resource in the future,
2945 * pci_reserve_map() will try to allocate a fresh
2946 * resource range.
2947 */
2948 resource_list_delete(rl, type, reg);
2949 pci_disable_io(dev, type);
2950 if (bootverbose)
2951 device_printf(bus,
2952 "pci%d:%d:%d:%d bar %#x failed to allocate\n",
2953 pci_get_domain(dev), pci_get_bus(dev),
2954 pci_get_slot(dev), pci_get_function(dev), reg);
2955 } else {
2956 start = rman_get_start(res);
2957 pci_write_bar(dev, pm, start);
2958 }
2959 return (barlen);
2960 }
2961
2962 /*
2963 * For ATA devices we need to decide early what addressing mode to use.
2964 * Legacy demands that the primary and secondary ATA ports sits on the
2965 * same addresses that old ISA hardware did. This dictates that we use
2966 * those addresses and ignore the BAR's if we cannot set PCI native
2967 * addressing mode.
2968 */
2969 static void
pci_ata_maps(device_t bus,device_t dev,struct resource_list * rl,int force,uint32_t prefetchmask)2970 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force,
2971 uint32_t prefetchmask)
2972 {
2973 int rid, type, progif;
2974 #if 0
2975 /* if this device supports PCI native addressing use it */
2976 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2977 if ((progif & 0x8a) == 0x8a) {
2978 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2979 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2980 printf("Trying ATA native PCI addressing mode\n");
2981 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2982 }
2983 }
2984 #endif
2985 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2986 type = SYS_RES_IOPORT;
2987 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2988 pci_add_map(bus, dev, PCIR_BAR(0), rl, force,
2989 prefetchmask & (1 << 0));
2990 pci_add_map(bus, dev, PCIR_BAR(1), rl, force,
2991 prefetchmask & (1 << 1));
2992 } else {
2993 rid = PCIR_BAR(0);
2994 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2995 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0,
2996 0x1f7, 8, 0);
2997 rid = PCIR_BAR(1);
2998 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2999 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6,
3000 0x3f6, 1, 0);
3001 }
3002 if (progif & PCIP_STORAGE_IDE_MODESEC) {
3003 pci_add_map(bus, dev, PCIR_BAR(2), rl, force,
3004 prefetchmask & (1 << 2));
3005 pci_add_map(bus, dev, PCIR_BAR(3), rl, force,
3006 prefetchmask & (1 << 3));
3007 } else {
3008 rid = PCIR_BAR(2);
3009 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
3010 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170,
3011 0x177, 8, 0);
3012 rid = PCIR_BAR(3);
3013 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
3014 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376,
3015 0x376, 1, 0);
3016 }
3017 pci_add_map(bus, dev, PCIR_BAR(4), rl, force,
3018 prefetchmask & (1 << 4));
3019 pci_add_map(bus, dev, PCIR_BAR(5), rl, force,
3020 prefetchmask & (1 << 5));
3021 }
3022
3023 static void
pci_assign_interrupt(device_t bus,device_t dev,int force_route)3024 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
3025 {
3026 struct pci_devinfo *dinfo = device_get_ivars(dev);
3027 pcicfgregs *cfg = &dinfo->cfg;
3028 char tunable_name[64];
3029 int irq;
3030
3031 /* Has to have an intpin to have an interrupt. */
3032 if (cfg->intpin == 0)
3033 return;
3034
3035 /* Let the user override the IRQ with a tunable. */
3036 irq = PCI_INVALID_IRQ;
3037 snprintf(tunable_name, sizeof(tunable_name),
3038 "hw.pci%d.%d.%d.INT%c.irq",
3039 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
3040 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
3041 irq = PCI_INVALID_IRQ;
3042
3043 /*
3044 * If we didn't get an IRQ via the tunable, then we either use the
3045 * IRQ value in the intline register or we ask the bus to route an
3046 * interrupt for us. If force_route is true, then we only use the
3047 * value in the intline register if the bus was unable to assign an
3048 * IRQ.
3049 */
3050 if (!PCI_INTERRUPT_VALID(irq)) {
3051 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
3052 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
3053 if (!PCI_INTERRUPT_VALID(irq))
3054 irq = cfg->intline;
3055 }
3056
3057 /* If after all that we don't have an IRQ, just bail. */
3058 if (!PCI_INTERRUPT_VALID(irq))
3059 return;
3060
3061 /* Update the config register if it changed. */
3062 if (irq != cfg->intline) {
3063 cfg->intline = irq;
3064 pci_write_config(dev, PCIR_INTLINE, irq, 1);
3065 }
3066
3067 /* Add this IRQ as rid 0 interrupt resource. */
3068 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
3069 }
3070
3071 /* Perform early OHCI takeover from SMM. */
3072 static void
ohci_early_takeover(device_t self)3073 ohci_early_takeover(device_t self)
3074 {
3075 struct resource *res;
3076 uint32_t ctl;
3077 int rid;
3078 int i;
3079
3080 rid = PCIR_BAR(0);
3081 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3082 if (res == NULL)
3083 return;
3084
3085 ctl = bus_read_4(res, OHCI_CONTROL);
3086 if (ctl & OHCI_IR) {
3087 if (bootverbose)
3088 printf("ohci early: "
3089 "SMM active, request owner change\n");
3090 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR);
3091 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) {
3092 DELAY(1000);
3093 ctl = bus_read_4(res, OHCI_CONTROL);
3094 }
3095 if (ctl & OHCI_IR) {
3096 if (bootverbose)
3097 printf("ohci early: "
3098 "SMM does not respond, resetting\n");
3099 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET);
3100 }
3101 /* Disable interrupts */
3102 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
3103 }
3104
3105 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3106 }
3107
3108 /* Perform early UHCI takeover from SMM. */
3109 static void
uhci_early_takeover(device_t self)3110 uhci_early_takeover(device_t self)
3111 {
3112 struct resource *res;
3113 int rid;
3114
3115 /*
3116 * Set the PIRQD enable bit and switch off all the others. We don't
3117 * want legacy support to interfere with us XXX Does this also mean
3118 * that the BIOS won't touch the keyboard anymore if it is connected
3119 * to the ports of the root hub?
3120 */
3121 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2);
3122
3123 /* Disable interrupts */
3124 rid = PCI_UHCI_BASE_REG;
3125 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE);
3126 if (res != NULL) {
3127 bus_write_2(res, UHCI_INTR, 0);
3128 bus_release_resource(self, SYS_RES_IOPORT, rid, res);
3129 }
3130 }
3131
3132 /* Perform early EHCI takeover from SMM. */
3133 static void
ehci_early_takeover(device_t self)3134 ehci_early_takeover(device_t self)
3135 {
3136 struct resource *res;
3137 uint32_t cparams;
3138 uint32_t eec;
3139 uint8_t eecp;
3140 uint8_t bios_sem;
3141 uint8_t offs;
3142 int rid;
3143 int i;
3144
3145 rid = PCIR_BAR(0);
3146 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3147 if (res == NULL)
3148 return;
3149
3150 cparams = bus_read_4(res, EHCI_HCCPARAMS);
3151
3152 /* Synchronise with the BIOS if it owns the controller. */
3153 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0;
3154 eecp = EHCI_EECP_NEXT(eec)) {
3155 eec = pci_read_config(self, eecp, 4);
3156 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) {
3157 continue;
3158 }
3159 bios_sem = pci_read_config(self, eecp +
3160 EHCI_LEGSUP_BIOS_SEM, 1);
3161 if (bios_sem == 0) {
3162 continue;
3163 }
3164 if (bootverbose)
3165 printf("ehci early: "
3166 "SMM active, request owner change\n");
3167
3168 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1);
3169
3170 for (i = 0; (i < 100) && (bios_sem != 0); i++) {
3171 DELAY(1000);
3172 bios_sem = pci_read_config(self, eecp +
3173 EHCI_LEGSUP_BIOS_SEM, 1);
3174 }
3175
3176 if (bios_sem != 0) {
3177 if (bootverbose)
3178 printf("ehci early: "
3179 "SMM does not respond\n");
3180 }
3181 /* Disable interrupts */
3182 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION));
3183 bus_write_4(res, offs + EHCI_USBINTR, 0);
3184 }
3185 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3186 }
3187
3188 /* Perform early XHCI takeover from SMM. */
3189 static void
xhci_early_takeover(device_t self)3190 xhci_early_takeover(device_t self)
3191 {
3192 struct resource *res;
3193 uint32_t cparams;
3194 uint32_t eec;
3195 uint8_t eecp;
3196 uint8_t bios_sem;
3197 uint8_t offs;
3198 int rid;
3199 int i;
3200
3201 rid = PCIR_BAR(0);
3202 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3203 if (res == NULL)
3204 return;
3205
3206 cparams = bus_read_4(res, XHCI_HCSPARAMS0);
3207
3208 eec = -1;
3209
3210 /* Synchronise with the BIOS if it owns the controller. */
3211 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
3212 eecp += XHCI_XECP_NEXT(eec) << 2) {
3213 eec = bus_read_4(res, eecp);
3214
3215 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
3216 continue;
3217
3218 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM);
3219 if (bios_sem == 0)
3220 continue;
3221
3222 if (bootverbose)
3223 printf("xhci early: "
3224 "SMM active, request owner change\n");
3225
3226 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1);
3227
3228 /* wait a maximum of 5 second */
3229
3230 for (i = 0; (i < 5000) && (bios_sem != 0); i++) {
3231 DELAY(1000);
3232 bios_sem = bus_read_1(res, eecp +
3233 XHCI_XECP_BIOS_SEM);
3234 }
3235
3236 if (bios_sem != 0) {
3237 if (bootverbose)
3238 printf("xhci early: "
3239 "SMM does not respond\n");
3240 }
3241
3242 /* Disable interrupts */
3243 offs = bus_read_1(res, XHCI_CAPLENGTH);
3244 bus_write_4(res, offs + XHCI_USBCMD, 0);
3245 bus_read_4(res, offs + XHCI_USBSTS);
3246 }
3247 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3248 }
3249
3250 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
3251 static void
pci_reserve_secbus(device_t bus,device_t dev,pcicfgregs * cfg,struct resource_list * rl)3252 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg,
3253 struct resource_list *rl)
3254 {
3255 struct resource *res;
3256 char *cp;
3257 u_long start, end, count;
3258 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus;
3259
3260 switch (cfg->hdrtype & PCIM_HDRTYPE) {
3261 case PCIM_HDRTYPE_BRIDGE:
3262 sec_reg = PCIR_SECBUS_1;
3263 sub_reg = PCIR_SUBBUS_1;
3264 break;
3265 case PCIM_HDRTYPE_CARDBUS:
3266 sec_reg = PCIR_SECBUS_2;
3267 sub_reg = PCIR_SUBBUS_2;
3268 break;
3269 default:
3270 return;
3271 }
3272
3273 /*
3274 * If the existing bus range is valid, attempt to reserve it
3275 * from our parent. If this fails for any reason, clear the
3276 * secbus and subbus registers.
3277 *
3278 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus?
3279 * This would at least preserve the existing sec_bus if it is
3280 * valid.
3281 */
3282 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1);
3283 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1);
3284
3285 /* Quirk handling. */
3286 switch (pci_get_devid(dev)) {
3287 case 0x12258086: /* Intel 82454KX/GX (Orion) */
3288 sup_bus = pci_read_config(dev, 0x41, 1);
3289 if (sup_bus != 0xff) {
3290 sec_bus = sup_bus + 1;
3291 sub_bus = sup_bus + 1;
3292 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1);
3293 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1);
3294 }
3295 break;
3296
3297 case 0x00dd10de:
3298 /* Compaq R3000 BIOS sets wrong subordinate bus number. */
3299 if ((cp = getenv("smbios.planar.maker")) == NULL)
3300 break;
3301 if (strncmp(cp, "Compal", 6) != 0) {
3302 freeenv(cp);
3303 break;
3304 }
3305 freeenv(cp);
3306 if ((cp = getenv("smbios.planar.product")) == NULL)
3307 break;
3308 if (strncmp(cp, "08A0", 4) != 0) {
3309 freeenv(cp);
3310 break;
3311 }
3312 freeenv(cp);
3313 if (sub_bus < 0xa) {
3314 sub_bus = 0xa;
3315 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1);
3316 }
3317 break;
3318 }
3319
3320 if (bootverbose)
3321 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus);
3322 if (sec_bus > 0 && sub_bus >= sec_bus) {
3323 start = sec_bus;
3324 end = sub_bus;
3325 count = end - start + 1;
3326
3327 resource_list_add(rl, PCI_RES_BUS, 0, 0ul, ~0ul, count);
3328
3329 /*
3330 * If requested, clear secondary bus registers in
3331 * bridge devices to force a complete renumbering
3332 * rather than reserving the existing range. However,
3333 * preserve the existing size.
3334 */
3335 if (pci_clear_buses)
3336 goto clear;
3337
3338 rid = 0;
3339 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid,
3340 start, end, count, 0);
3341 if (res != NULL)
3342 return;
3343
3344 if (bootverbose)
3345 device_printf(bus,
3346 "pci%d:%d:%d:%d secbus failed to allocate\n",
3347 pci_get_domain(dev), pci_get_bus(dev),
3348 pci_get_slot(dev), pci_get_function(dev));
3349 }
3350
3351 clear:
3352 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1);
3353 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1);
3354 }
3355
3356 static struct resource *
pci_alloc_secbus(device_t dev,device_t child,int * rid,u_long start,u_long end,u_long count,u_int flags)3357 pci_alloc_secbus(device_t dev, device_t child, int *rid, u_long start,
3358 u_long end, u_long count, u_int flags)
3359 {
3360 struct pci_devinfo *dinfo;
3361 pcicfgregs *cfg;
3362 struct resource_list *rl;
3363 struct resource *res;
3364 int sec_reg, sub_reg;
3365
3366 dinfo = device_get_ivars(child);
3367 cfg = &dinfo->cfg;
3368 rl = &dinfo->resources;
3369 switch (cfg->hdrtype & PCIM_HDRTYPE) {
3370 case PCIM_HDRTYPE_BRIDGE:
3371 sec_reg = PCIR_SECBUS_1;
3372 sub_reg = PCIR_SUBBUS_1;
3373 break;
3374 case PCIM_HDRTYPE_CARDBUS:
3375 sec_reg = PCIR_SECBUS_2;
3376 sub_reg = PCIR_SUBBUS_2;
3377 break;
3378 default:
3379 return (NULL);
3380 }
3381
3382 if (*rid != 0)
3383 return (NULL);
3384
3385 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL)
3386 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count);
3387 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) {
3388 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid,
3389 start, end, count, flags & ~RF_ACTIVE);
3390 if (res == NULL) {
3391 resource_list_delete(rl, PCI_RES_BUS, *rid);
3392 device_printf(child, "allocating %lu bus%s failed\n",
3393 count, count == 1 ? "" : "es");
3394 return (NULL);
3395 }
3396 if (bootverbose)
3397 device_printf(child,
3398 "Lazy allocation of %lu bus%s at %lu\n", count,
3399 count == 1 ? "" : "es", rman_get_start(res));
3400 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1);
3401 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1);
3402 }
3403 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start,
3404 end, count, flags));
3405 }
3406 #endif
3407
3408 void
pci_add_resources(device_t bus,device_t dev,int force,uint32_t prefetchmask)3409 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
3410 {
3411 struct pci_devinfo *dinfo;
3412 pcicfgregs *cfg;
3413 struct resource_list *rl;
3414 const struct pci_quirk *q;
3415 uint32_t devid;
3416 int i;
3417
3418 dinfo = device_get_ivars(dev);
3419 cfg = &dinfo->cfg;
3420 rl = &dinfo->resources;
3421 devid = (cfg->device << 16) | cfg->vendor;
3422
3423 /* ATA devices needs special map treatment */
3424 if ((pci_get_class(dev) == PCIC_STORAGE) &&
3425 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
3426 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
3427 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
3428 !pci_read_config(dev, PCIR_BAR(2), 4))) )
3429 pci_ata_maps(bus, dev, rl, force, prefetchmask);
3430 else
3431 for (i = 0; i < cfg->nummaps;) {
3432 /*
3433 * Skip quirked resources.
3434 */
3435 for (q = &pci_quirks[0]; q->devid != 0; q++)
3436 if (q->devid == devid &&
3437 q->type == PCI_QUIRK_UNMAP_REG &&
3438 q->arg1 == PCIR_BAR(i))
3439 break;
3440 if (q->devid != 0) {
3441 i++;
3442 continue;
3443 }
3444 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force,
3445 prefetchmask & (1 << i));
3446 }
3447
3448 /*
3449 * Add additional, quirked resources.
3450 */
3451 for (q = &pci_quirks[0]; q->devid != 0; q++)
3452 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG)
3453 pci_add_map(bus, dev, q->arg1, rl, force, 0);
3454
3455 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
3456 #ifdef __PCI_REROUTE_INTERRUPT
3457 /*
3458 * Try to re-route interrupts. Sometimes the BIOS or
3459 * firmware may leave bogus values in these registers.
3460 * If the re-route fails, then just stick with what we
3461 * have.
3462 */
3463 pci_assign_interrupt(bus, dev, 1);
3464 #else
3465 pci_assign_interrupt(bus, dev, 0);
3466 #endif
3467 }
3468
3469 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS &&
3470 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) {
3471 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI)
3472 xhci_early_takeover(dev);
3473 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI)
3474 ehci_early_takeover(dev);
3475 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI)
3476 ohci_early_takeover(dev);
3477 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI)
3478 uhci_early_takeover(dev);
3479 }
3480
3481 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
3482 /*
3483 * Reserve resources for secondary bus ranges behind bridge
3484 * devices.
3485 */
3486 pci_reserve_secbus(bus, dev, cfg, rl);
3487 #endif
3488 }
3489
3490 static struct pci_devinfo *
pci_identify_function(device_t pcib,device_t dev,int domain,int busno,int slot,int func,size_t dinfo_size)3491 pci_identify_function(device_t pcib, device_t dev, int domain, int busno,
3492 int slot, int func, size_t dinfo_size)
3493 {
3494 struct pci_devinfo *dinfo;
3495
3496 dinfo = pci_read_device(pcib, domain, busno, slot, func, dinfo_size);
3497 if (dinfo != NULL)
3498 pci_add_child(dev, dinfo);
3499
3500 return (dinfo);
3501 }
3502
3503 void
pci_add_children(device_t dev,int domain,int busno,size_t dinfo_size)3504 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
3505 {
3506 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
3507 device_t pcib = device_get_parent(dev);
3508 struct pci_devinfo *dinfo;
3509 int maxslots;
3510 int s, f, pcifunchigh;
3511 uint8_t hdrtype;
3512 int first_func;
3513
3514 /*
3515 * Try to detect a device at slot 0, function 0. If it exists, try to
3516 * enable ARI. We must enable ARI before detecting the rest of the
3517 * functions on this bus as ARI changes the set of slots and functions
3518 * that are legal on this bus.
3519 */
3520 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0,
3521 dinfo_size);
3522 if (dinfo != NULL && pci_enable_ari)
3523 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev);
3524
3525 /*
3526 * Start looking for new devices on slot 0 at function 1 because we
3527 * just identified the device at slot 0, function 0.
3528 */
3529 first_func = 1;
3530
3531 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
3532 ("dinfo_size too small"));
3533 maxslots = PCIB_MAXSLOTS(pcib);
3534 for (s = 0; s <= maxslots; s++, first_func = 0) {
3535 pcifunchigh = 0;
3536 f = 0;
3537 DELAY(1);
3538 hdrtype = REG(PCIR_HDRTYPE, 1);
3539 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
3540 continue;
3541 if (hdrtype & PCIM_MFDEV)
3542 pcifunchigh = PCIB_MAXFUNCS(pcib);
3543 for (f = first_func; f <= pcifunchigh; f++)
3544 pci_identify_function(pcib, dev, domain, busno, s, f,
3545 dinfo_size);
3546 }
3547 #undef REG
3548 }
3549
3550 void
pci_add_child(device_t bus,struct pci_devinfo * dinfo)3551 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
3552 {
3553 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
3554 device_set_ivars(dinfo->cfg.dev, dinfo);
3555 resource_list_init(&dinfo->resources);
3556 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
3557 pci_cfg_restore(dinfo->cfg.dev, dinfo);
3558 pci_print_verbose(dinfo);
3559 pci_add_resources(bus, dinfo->cfg.dev, 0, 0);
3560 }
3561
3562 static int
pci_probe(device_t dev)3563 pci_probe(device_t dev)
3564 {
3565
3566 device_set_desc(dev, "PCI bus");
3567
3568 /* Allow other subclasses to override this driver. */
3569 return (BUS_PROBE_GENERIC);
3570 }
3571
3572 int
pci_attach_common(device_t dev)3573 pci_attach_common(device_t dev)
3574 {
3575 struct pci_softc *sc;
3576 int busno, domain;
3577 #ifdef PCI_DMA_BOUNDARY
3578 int error, tag_valid;
3579 #endif
3580 #ifdef PCI_RES_BUS
3581 int rid;
3582 #endif
3583
3584 sc = device_get_softc(dev);
3585 domain = pcib_get_domain(dev);
3586 busno = pcib_get_bus(dev);
3587 #ifdef PCI_RES_BUS
3588 rid = 0;
3589 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno,
3590 1, 0);
3591 if (sc->sc_bus == NULL) {
3592 device_printf(dev, "failed to allocate bus number\n");
3593 return (ENXIO);
3594 }
3595 #endif
3596 if (bootverbose)
3597 device_printf(dev, "domain=%d, physical bus=%d\n",
3598 domain, busno);
3599 #ifdef PCI_DMA_BOUNDARY
3600 tag_valid = 0;
3601 if (device_get_devclass(device_get_parent(device_get_parent(dev))) !=
3602 devclass_find("pci")) {
3603 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1,
3604 PCI_DMA_BOUNDARY, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3605 NULL, NULL, BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED,
3606 BUS_SPACE_MAXSIZE, 0, NULL, NULL, &sc->sc_dma_tag);
3607 if (error)
3608 device_printf(dev, "Failed to create DMA tag: %d\n",
3609 error);
3610 else
3611 tag_valid = 1;
3612 }
3613 if (!tag_valid)
3614 #endif
3615 sc->sc_dma_tag = bus_get_dma_tag(dev);
3616 return (0);
3617 }
3618
3619 static int
pci_attach(device_t dev)3620 pci_attach(device_t dev)
3621 {
3622 int busno, domain, error;
3623
3624 error = pci_attach_common(dev);
3625 if (error)
3626 return (error);
3627
3628 /*
3629 * Since there can be multiple independantly numbered PCI
3630 * busses on systems with multiple PCI domains, we can't use
3631 * the unit number to decide which bus we are probing. We ask
3632 * the parent pcib what our domain and bus numbers are.
3633 */
3634 domain = pcib_get_domain(dev);
3635 busno = pcib_get_bus(dev);
3636 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
3637 return (bus_generic_attach(dev));
3638 }
3639
3640 #ifdef PCI_RES_BUS
3641 static int
pci_detach(device_t dev)3642 pci_detach(device_t dev)
3643 {
3644 struct pci_softc *sc;
3645 int error;
3646
3647 error = bus_generic_detach(dev);
3648 if (error)
3649 return (error);
3650 sc = device_get_softc(dev);
3651 return (bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus));
3652 }
3653 #endif
3654
3655 static void
pci_set_power_children(device_t dev,device_t * devlist,int numdevs,int state)3656 pci_set_power_children(device_t dev, device_t *devlist, int numdevs,
3657 int state)
3658 {
3659 device_t child, pcib;
3660 int dstate, i;
3661
3662 /*
3663 * Set the device to the given state. If the firmware suggests
3664 * a different power state, use it instead. If power management
3665 * is not present, the firmware is responsible for managing
3666 * device power. Skip children who aren't attached since they
3667 * are handled separately.
3668 */
3669 pcib = device_get_parent(dev);
3670 for (i = 0; i < numdevs; i++) {
3671 child = devlist[i];
3672 dstate = state;
3673 if (device_is_attached(child) &&
3674 PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0)
3675 pci_set_powerstate(child, dstate);
3676 }
3677 }
3678
3679 int
pci_suspend(device_t dev)3680 pci_suspend(device_t dev)
3681 {
3682 device_t child, *devlist;
3683 struct pci_devinfo *dinfo;
3684 int error, i, numdevs;
3685
3686 /*
3687 * Save the PCI configuration space for each child and set the
3688 * device in the appropriate power state for this sleep state.
3689 */
3690 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
3691 return (error);
3692 for (i = 0; i < numdevs; i++) {
3693 child = devlist[i];
3694 dinfo = device_get_ivars(child);
3695 pci_cfg_save(child, dinfo, 0);
3696 }
3697
3698 /* Suspend devices before potentially powering them down. */
3699 error = bus_generic_suspend(dev);
3700 if (error) {
3701 free(devlist, M_TEMP);
3702 return (error);
3703 }
3704 if (pci_do_power_suspend)
3705 pci_set_power_children(dev, devlist, numdevs,
3706 PCI_POWERSTATE_D3);
3707 free(devlist, M_TEMP);
3708 return (0);
3709 }
3710
3711 int
pci_resume(device_t dev)3712 pci_resume(device_t dev)
3713 {
3714 device_t child, *devlist;
3715 struct pci_devinfo *dinfo;
3716 int error, i, numdevs;
3717
3718 /*
3719 * Set each child to D0 and restore its PCI configuration space.
3720 */
3721 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
3722 return (error);
3723 if (pci_do_power_resume)
3724 pci_set_power_children(dev, devlist, numdevs,
3725 PCI_POWERSTATE_D0);
3726
3727 /* Now the device is powered up, restore its config space. */
3728 for (i = 0; i < numdevs; i++) {
3729 child = devlist[i];
3730 dinfo = device_get_ivars(child);
3731
3732 pci_cfg_restore(child, dinfo);
3733 if (!device_is_attached(child))
3734 pci_cfg_save(child, dinfo, 1);
3735 }
3736
3737 /*
3738 * Resume critical devices first, then everything else later.
3739 */
3740 for (i = 0; i < numdevs; i++) {
3741 child = devlist[i];
3742 switch (pci_get_class(child)) {
3743 case PCIC_DISPLAY:
3744 case PCIC_MEMORY:
3745 case PCIC_BRIDGE:
3746 case PCIC_BASEPERIPH:
3747 DEVICE_RESUME(child);
3748 break;
3749 }
3750 }
3751 for (i = 0; i < numdevs; i++) {
3752 child = devlist[i];
3753 switch (pci_get_class(child)) {
3754 case PCIC_DISPLAY:
3755 case PCIC_MEMORY:
3756 case PCIC_BRIDGE:
3757 case PCIC_BASEPERIPH:
3758 break;
3759 default:
3760 DEVICE_RESUME(child);
3761 }
3762 }
3763 free(devlist, M_TEMP);
3764 return (0);
3765 }
3766
3767 static void
pci_load_vendor_data(void)3768 pci_load_vendor_data(void)
3769 {
3770 caddr_t data;
3771 void *ptr;
3772 size_t sz;
3773
3774 data = preload_search_by_type("pci_vendor_data");
3775 if (data != NULL) {
3776 ptr = preload_fetch_addr(data);
3777 sz = preload_fetch_size(data);
3778 if (ptr != NULL && sz != 0) {
3779 pci_vendordata = ptr;
3780 pci_vendordata_size = sz;
3781 /* terminate the database */
3782 pci_vendordata[pci_vendordata_size] = '\n';
3783 }
3784 }
3785 }
3786
3787 void
pci_driver_added(device_t dev,driver_t * driver)3788 pci_driver_added(device_t dev, driver_t *driver)
3789 {
3790 int numdevs;
3791 device_t *devlist;
3792 device_t child;
3793 struct pci_devinfo *dinfo;
3794 int i;
3795
3796 if (bootverbose)
3797 device_printf(dev, "driver added\n");
3798 DEVICE_IDENTIFY(driver, dev);
3799 if (device_get_children(dev, &devlist, &numdevs) != 0)
3800 return;
3801 for (i = 0; i < numdevs; i++) {
3802 child = devlist[i];
3803 if (device_get_state(child) != DS_NOTPRESENT)
3804 continue;
3805 dinfo = device_get_ivars(child);
3806 pci_print_verbose(dinfo);
3807 if (bootverbose)
3808 pci_printf(&dinfo->cfg, "reprobing on driver added\n");
3809 pci_cfg_restore(child, dinfo);
3810 if (device_probe_and_attach(child) != 0)
3811 pci_child_detached(dev, child);
3812 }
3813 free(devlist, M_TEMP);
3814 }
3815
3816 int
pci_setup_intr(device_t dev,device_t child,struct resource * irq,int flags,driver_filter_t * filter,driver_intr_t * intr,void * arg,void ** cookiep)3817 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
3818 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep)
3819 {
3820 struct pci_devinfo *dinfo;
3821 struct msix_table_entry *mte;
3822 struct msix_vector *mv;
3823 uint64_t addr;
3824 uint32_t data;
3825 void *cookie;
3826 int error, rid;
3827
3828 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr,
3829 arg, &cookie);
3830 if (error)
3831 return (error);
3832
3833 /* If this is not a direct child, just bail out. */
3834 if (device_get_parent(child) != dev) {
3835 *cookiep = cookie;
3836 return(0);
3837 }
3838
3839 rid = rman_get_rid(irq);
3840 if (rid == 0) {
3841 /* Make sure that INTx is enabled */
3842 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3843 } else {
3844 /*
3845 * Check to see if the interrupt is MSI or MSI-X.
3846 * Ask our parent to map the MSI and give
3847 * us the address and data register values.
3848 * If we fail for some reason, teardown the
3849 * interrupt handler.
3850 */
3851 dinfo = device_get_ivars(child);
3852 if (dinfo->cfg.msi.msi_alloc > 0) {
3853 if (dinfo->cfg.msi.msi_addr == 0) {
3854 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3855 ("MSI has handlers, but vectors not mapped"));
3856 error = PCIB_MAP_MSI(device_get_parent(dev),
3857 child, rman_get_start(irq), &addr, &data);
3858 if (error)
3859 goto bad;
3860 dinfo->cfg.msi.msi_addr = addr;
3861 dinfo->cfg.msi.msi_data = data;
3862 }
3863 if (dinfo->cfg.msi.msi_handlers == 0)
3864 pci_enable_msi(child, dinfo->cfg.msi.msi_addr,
3865 dinfo->cfg.msi.msi_data);
3866 dinfo->cfg.msi.msi_handlers++;
3867 } else {
3868 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3869 ("No MSI or MSI-X interrupts allocated"));
3870 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3871 ("MSI-X index too high"));
3872 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3873 KASSERT(mte->mte_vector != 0, ("no message vector"));
3874 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3875 KASSERT(mv->mv_irq == rman_get_start(irq),
3876 ("IRQ mismatch"));
3877 if (mv->mv_address == 0) {
3878 KASSERT(mte->mte_handlers == 0,
3879 ("MSI-X table entry has handlers, but vector not mapped"));
3880 error = PCIB_MAP_MSI(device_get_parent(dev),
3881 child, rman_get_start(irq), &addr, &data);
3882 if (error)
3883 goto bad;
3884 mv->mv_address = addr;
3885 mv->mv_data = data;
3886 }
3887 if (mte->mte_handlers == 0) {
3888 pci_enable_msix(child, rid - 1, mv->mv_address,
3889 mv->mv_data);
3890 pci_unmask_msix(child, rid - 1);
3891 }
3892 mte->mte_handlers++;
3893 }
3894
3895 /*
3896 * Make sure that INTx is disabled if we are using MSI/MSI-X,
3897 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG,
3898 * in which case we "enable" INTx so MSI/MSI-X actually works.
3899 */
3900 if (!pci_has_quirk(pci_get_devid(child),
3901 PCI_QUIRK_MSI_INTX_BUG))
3902 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3903 else
3904 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3905 bad:
3906 if (error) {
3907 (void)bus_generic_teardown_intr(dev, child, irq,
3908 cookie);
3909 return (error);
3910 }
3911 }
3912 *cookiep = cookie;
3913 return (0);
3914 }
3915
3916 int
pci_teardown_intr(device_t dev,device_t child,struct resource * irq,void * cookie)3917 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3918 void *cookie)
3919 {
3920 struct msix_table_entry *mte;
3921 struct resource_list_entry *rle;
3922 struct pci_devinfo *dinfo;
3923 int error, rid;
3924
3925 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3926 return (EINVAL);
3927
3928 /* If this isn't a direct child, just bail out */
3929 if (device_get_parent(child) != dev)
3930 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3931
3932 rid = rman_get_rid(irq);
3933 if (rid == 0) {
3934 /* Mask INTx */
3935 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3936 } else {
3937 /*
3938 * Check to see if the interrupt is MSI or MSI-X. If so,
3939 * decrement the appropriate handlers count and mask the
3940 * MSI-X message, or disable MSI messages if the count
3941 * drops to 0.
3942 */
3943 dinfo = device_get_ivars(child);
3944 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3945 if (rle->res != irq)
3946 return (EINVAL);
3947 if (dinfo->cfg.msi.msi_alloc > 0) {
3948 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3949 ("MSI-X index too high"));
3950 if (dinfo->cfg.msi.msi_handlers == 0)
3951 return (EINVAL);
3952 dinfo->cfg.msi.msi_handlers--;
3953 if (dinfo->cfg.msi.msi_handlers == 0)
3954 pci_disable_msi(child);
3955 } else {
3956 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3957 ("No MSI or MSI-X interrupts allocated"));
3958 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3959 ("MSI-X index too high"));
3960 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3961 if (mte->mte_handlers == 0)
3962 return (EINVAL);
3963 mte->mte_handlers--;
3964 if (mte->mte_handlers == 0)
3965 pci_mask_msix(child, rid - 1);
3966 }
3967 }
3968 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3969 if (rid > 0)
3970 KASSERT(error == 0,
3971 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3972 return (error);
3973 }
3974
3975 int
pci_print_child(device_t dev,device_t child)3976 pci_print_child(device_t dev, device_t child)
3977 {
3978 struct pci_devinfo *dinfo;
3979 struct resource_list *rl;
3980 int retval = 0;
3981
3982 dinfo = device_get_ivars(child);
3983 rl = &dinfo->resources;
3984
3985 retval += bus_print_child_header(dev, child);
3986
3987 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3988 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3989 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3990 if (device_get_flags(dev))
3991 retval += printf(" flags %#x", device_get_flags(dev));
3992
3993 retval += printf(" at device %d.%d", pci_get_slot(child),
3994 pci_get_function(child));
3995
3996 retval += bus_print_child_domain(dev, child);
3997 retval += bus_print_child_footer(dev, child);
3998
3999 return (retval);
4000 }
4001
4002 static const struct
4003 {
4004 int class;
4005 int subclass;
4006 int report; /* 0 = bootverbose, 1 = always */
4007 const char *desc;
4008 } pci_nomatch_tab[] = {
4009 {PCIC_OLD, -1, 1, "old"},
4010 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"},
4011 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"},
4012 {PCIC_STORAGE, -1, 1, "mass storage"},
4013 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"},
4014 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"},
4015 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"},
4016 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"},
4017 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"},
4018 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"},
4019 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"},
4020 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"},
4021 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"},
4022 {PCIC_NETWORK, -1, 1, "network"},
4023 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"},
4024 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"},
4025 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"},
4026 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"},
4027 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"},
4028 {PCIC_DISPLAY, -1, 1, "display"},
4029 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"},
4030 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"},
4031 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"},
4032 {PCIC_MULTIMEDIA, -1, 1, "multimedia"},
4033 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"},
4034 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"},
4035 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"},
4036 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"},
4037 {PCIC_MEMORY, -1, 1, "memory"},
4038 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"},
4039 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"},
4040 {PCIC_BRIDGE, -1, 1, "bridge"},
4041 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"},
4042 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"},
4043 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"},
4044 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"},
4045 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"},
4046 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"},
4047 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"},
4048 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"},
4049 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"},
4050 {PCIC_SIMPLECOMM, -1, 1, "simple comms"},
4051 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */
4052 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"},
4053 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"},
4054 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"},
4055 {PCIC_BASEPERIPH, -1, 0, "base peripheral"},
4056 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"},
4057 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"},
4058 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"},
4059 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"},
4060 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"},
4061 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"},
4062 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"},
4063 {PCIC_INPUTDEV, -1, 1, "input device"},
4064 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"},
4065 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"},
4066 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"},
4067 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"},
4068 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"},
4069 {PCIC_DOCKING, -1, 1, "docking station"},
4070 {PCIC_PROCESSOR, -1, 1, "processor"},
4071 {PCIC_SERIALBUS, -1, 1, "serial bus"},
4072 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"},
4073 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"},
4074 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"},
4075 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"},
4076 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"},
4077 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"},
4078 {PCIC_WIRELESS, -1, 1, "wireless controller"},
4079 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"},
4080 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"},
4081 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"},
4082 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"},
4083 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"},
4084 {PCIC_SATCOM, -1, 1, "satellite communication"},
4085 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"},
4086 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"},
4087 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"},
4088 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"},
4089 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"},
4090 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"},
4091 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"},
4092 {PCIC_DASP, -1, 0, "dasp"},
4093 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"},
4094 {0, 0, 0, NULL}
4095 };
4096
4097 void
pci_probe_nomatch(device_t dev,device_t child)4098 pci_probe_nomatch(device_t dev, device_t child)
4099 {
4100 int i, report;
4101 const char *cp, *scp;
4102 char *device;
4103
4104 /*
4105 * Look for a listing for this device in a loaded device database.
4106 */
4107 report = 1;
4108 if ((device = pci_describe_device(child)) != NULL) {
4109 device_printf(dev, "<%s>", device);
4110 free(device, M_DEVBUF);
4111 } else {
4112 /*
4113 * Scan the class/subclass descriptions for a general
4114 * description.
4115 */
4116 cp = "unknown";
4117 scp = NULL;
4118 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
4119 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
4120 if (pci_nomatch_tab[i].subclass == -1) {
4121 cp = pci_nomatch_tab[i].desc;
4122 report = pci_nomatch_tab[i].report;
4123 } else if (pci_nomatch_tab[i].subclass ==
4124 pci_get_subclass(child)) {
4125 scp = pci_nomatch_tab[i].desc;
4126 report = pci_nomatch_tab[i].report;
4127 }
4128 }
4129 }
4130 if (report || bootverbose) {
4131 device_printf(dev, "<%s%s%s>",
4132 cp ? cp : "",
4133 ((cp != NULL) && (scp != NULL)) ? ", " : "",
4134 scp ? scp : "");
4135 }
4136 }
4137 if (report || bootverbose) {
4138 printf(" at device %d.%d (no driver attached)\n",
4139 pci_get_slot(child), pci_get_function(child));
4140 }
4141 pci_cfg_save(child, device_get_ivars(child), 1);
4142 }
4143
4144 void
pci_child_detached(device_t dev,device_t child)4145 pci_child_detached(device_t dev, device_t child)
4146 {
4147 struct pci_devinfo *dinfo;
4148 struct resource_list *rl;
4149
4150 dinfo = device_get_ivars(child);
4151 rl = &dinfo->resources;
4152
4153 /*
4154 * Have to deallocate IRQs before releasing any MSI messages and
4155 * have to release MSI messages before deallocating any memory
4156 * BARs.
4157 */
4158 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0)
4159 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n");
4160 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) {
4161 pci_printf(&dinfo->cfg, "Device leaked MSI vectors\n");
4162 (void)pci_release_msi(child);
4163 }
4164 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0)
4165 pci_printf(&dinfo->cfg, "Device leaked memory resources\n");
4166 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0)
4167 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n");
4168 #ifdef PCI_RES_BUS
4169 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0)
4170 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n");
4171 #endif
4172
4173 pci_cfg_save(child, dinfo, 1);
4174 }
4175
4176 /*
4177 * Parse the PCI device database, if loaded, and return a pointer to a
4178 * description of the device.
4179 *
4180 * The database is flat text formatted as follows:
4181 *
4182 * Any line not in a valid format is ignored.
4183 * Lines are terminated with newline '\n' characters.
4184 *
4185 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
4186 * the vendor name.
4187 *
4188 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
4189 * - devices cannot be listed without a corresponding VENDOR line.
4190 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
4191 * another TAB, then the device name.
4192 */
4193
4194 /*
4195 * Assuming (ptr) points to the beginning of a line in the database,
4196 * return the vendor or device and description of the next entry.
4197 * The value of (vendor) or (device) inappropriate for the entry type
4198 * is set to -1. Returns nonzero at the end of the database.
4199 *
4200 * Note that this is slightly unrobust in the face of corrupt data;
4201 * we attempt to safeguard against this by spamming the end of the
4202 * database with a newline when we initialise.
4203 */
4204 static int
pci_describe_parse_line(char ** ptr,int * vendor,int * device,char ** desc)4205 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
4206 {
4207 char *cp = *ptr;
4208 int left;
4209
4210 *device = -1;
4211 *vendor = -1;
4212 **desc = '\0';
4213 for (;;) {
4214 left = pci_vendordata_size - (cp - pci_vendordata);
4215 if (left <= 0) {
4216 *ptr = cp;
4217 return(1);
4218 }
4219
4220 /* vendor entry? */
4221 if (*cp != '\t' &&
4222 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
4223 break;
4224 /* device entry? */
4225 if (*cp == '\t' &&
4226 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
4227 break;
4228
4229 /* skip to next line */
4230 while (*cp != '\n' && left > 0) {
4231 cp++;
4232 left--;
4233 }
4234 if (*cp == '\n') {
4235 cp++;
4236 left--;
4237 }
4238 }
4239 /* skip to next line */
4240 while (*cp != '\n' && left > 0) {
4241 cp++;
4242 left--;
4243 }
4244 if (*cp == '\n' && left > 0)
4245 cp++;
4246 *ptr = cp;
4247 return(0);
4248 }
4249
4250 static char *
pci_describe_device(device_t dev)4251 pci_describe_device(device_t dev)
4252 {
4253 int vendor, device;
4254 char *desc, *vp, *dp, *line;
4255
4256 desc = vp = dp = NULL;
4257
4258 /*
4259 * If we have no vendor data, we can't do anything.
4260 */
4261 if (pci_vendordata == NULL)
4262 goto out;
4263
4264 /*
4265 * Scan the vendor data looking for this device
4266 */
4267 line = pci_vendordata;
4268 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
4269 goto out;
4270 for (;;) {
4271 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
4272 goto out;
4273 if (vendor == pci_get_vendor(dev))
4274 break;
4275 }
4276 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
4277 goto out;
4278 for (;;) {
4279 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
4280 *dp = 0;
4281 break;
4282 }
4283 if (vendor != -1) {
4284 *dp = 0;
4285 break;
4286 }
4287 if (device == pci_get_device(dev))
4288 break;
4289 }
4290 if (dp[0] == '\0')
4291 snprintf(dp, 80, "0x%x", pci_get_device(dev));
4292 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
4293 NULL)
4294 sprintf(desc, "%s, %s", vp, dp);
4295 out:
4296 if (vp != NULL)
4297 free(vp, M_DEVBUF);
4298 if (dp != NULL)
4299 free(dp, M_DEVBUF);
4300 return(desc);
4301 }
4302
4303 int
pci_read_ivar(device_t dev,device_t child,int which,uintptr_t * result)4304 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
4305 {
4306 struct pci_devinfo *dinfo;
4307 pcicfgregs *cfg;
4308
4309 dinfo = device_get_ivars(child);
4310 cfg = &dinfo->cfg;
4311
4312 switch (which) {
4313 case PCI_IVAR_ETHADDR:
4314 /*
4315 * The generic accessor doesn't deal with failure, so
4316 * we set the return value, then return an error.
4317 */
4318 *((uint8_t **) result) = NULL;
4319 return (EINVAL);
4320 case PCI_IVAR_SUBVENDOR:
4321 *result = cfg->subvendor;
4322 break;
4323 case PCI_IVAR_SUBDEVICE:
4324 *result = cfg->subdevice;
4325 break;
4326 case PCI_IVAR_VENDOR:
4327 *result = cfg->vendor;
4328 break;
4329 case PCI_IVAR_DEVICE:
4330 *result = cfg->device;
4331 break;
4332 case PCI_IVAR_DEVID:
4333 *result = (cfg->device << 16) | cfg->vendor;
4334 break;
4335 case PCI_IVAR_CLASS:
4336 *result = cfg->baseclass;
4337 break;
4338 case PCI_IVAR_SUBCLASS:
4339 *result = cfg->subclass;
4340 break;
4341 case PCI_IVAR_PROGIF:
4342 *result = cfg->progif;
4343 break;
4344 case PCI_IVAR_REVID:
4345 *result = cfg->revid;
4346 break;
4347 case PCI_IVAR_INTPIN:
4348 *result = cfg->intpin;
4349 break;
4350 case PCI_IVAR_IRQ:
4351 *result = cfg->intline;
4352 break;
4353 case PCI_IVAR_DOMAIN:
4354 *result = cfg->domain;
4355 break;
4356 case PCI_IVAR_BUS:
4357 *result = cfg->bus;
4358 break;
4359 case PCI_IVAR_SLOT:
4360 *result = cfg->slot;
4361 break;
4362 case PCI_IVAR_FUNCTION:
4363 *result = cfg->func;
4364 break;
4365 case PCI_IVAR_CMDREG:
4366 *result = cfg->cmdreg;
4367 break;
4368 case PCI_IVAR_CACHELNSZ:
4369 *result = cfg->cachelnsz;
4370 break;
4371 case PCI_IVAR_MINGNT:
4372 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) {
4373 *result = -1;
4374 return (EINVAL);
4375 }
4376 *result = cfg->mingnt;
4377 break;
4378 case PCI_IVAR_MAXLAT:
4379 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) {
4380 *result = -1;
4381 return (EINVAL);
4382 }
4383 *result = cfg->maxlat;
4384 break;
4385 case PCI_IVAR_LATTIMER:
4386 *result = cfg->lattimer;
4387 break;
4388 default:
4389 return (ENOENT);
4390 }
4391 return (0);
4392 }
4393
4394 int
pci_write_ivar(device_t dev,device_t child,int which,uintptr_t value)4395 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
4396 {
4397 struct pci_devinfo *dinfo;
4398
4399 dinfo = device_get_ivars(child);
4400
4401 switch (which) {
4402 case PCI_IVAR_INTPIN:
4403 dinfo->cfg.intpin = value;
4404 return (0);
4405 case PCI_IVAR_ETHADDR:
4406 case PCI_IVAR_SUBVENDOR:
4407 case PCI_IVAR_SUBDEVICE:
4408 case PCI_IVAR_VENDOR:
4409 case PCI_IVAR_DEVICE:
4410 case PCI_IVAR_DEVID:
4411 case PCI_IVAR_CLASS:
4412 case PCI_IVAR_SUBCLASS:
4413 case PCI_IVAR_PROGIF:
4414 case PCI_IVAR_REVID:
4415 case PCI_IVAR_IRQ:
4416 case PCI_IVAR_DOMAIN:
4417 case PCI_IVAR_BUS:
4418 case PCI_IVAR_SLOT:
4419 case PCI_IVAR_FUNCTION:
4420 return (EINVAL); /* disallow for now */
4421
4422 default:
4423 return (ENOENT);
4424 }
4425 }
4426
4427 #include "opt_ddb.h"
4428 #ifdef DDB
4429 #include <ddb/ddb.h>
4430 #include <sys/cons.h>
4431
4432 /*
4433 * List resources based on pci map registers, used for within ddb
4434 */
4435
DB_SHOW_COMMAND(pciregs,db_pci_dump)4436 DB_SHOW_COMMAND(pciregs, db_pci_dump)
4437 {
4438 struct pci_devinfo *dinfo;
4439 struct devlist *devlist_head;
4440 struct pci_conf *p;
4441 const char *name;
4442 int i, error, none_count;
4443
4444 none_count = 0;
4445 /* get the head of the device queue */
4446 devlist_head = &pci_devq;
4447
4448 /*
4449 * Go through the list of devices and print out devices
4450 */
4451 for (error = 0, i = 0,
4452 dinfo = STAILQ_FIRST(devlist_head);
4453 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
4454 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4455
4456 /* Populate pd_name and pd_unit */
4457 name = NULL;
4458 if (dinfo->cfg.dev)
4459 name = device_get_name(dinfo->cfg.dev);
4460
4461 p = &dinfo->conf;
4462 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
4463 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
4464 (name && *name) ? name : "none",
4465 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
4466 none_count++,
4467 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
4468 p->pc_sel.pc_func, (p->pc_class << 16) |
4469 (p->pc_subclass << 8) | p->pc_progif,
4470 (p->pc_subdevice << 16) | p->pc_subvendor,
4471 (p->pc_device << 16) | p->pc_vendor,
4472 p->pc_revid, p->pc_hdr);
4473 }
4474 }
4475 #endif /* DDB */
4476
4477 static struct resource *
pci_reserve_map(device_t dev,device_t child,int type,int * rid,u_long start,u_long end,u_long count,u_int flags)4478 pci_reserve_map(device_t dev, device_t child, int type, int *rid,
4479 u_long start, u_long end, u_long count, u_int flags)
4480 {
4481 struct pci_devinfo *dinfo = device_get_ivars(child);
4482 struct resource_list *rl = &dinfo->resources;
4483 struct resource *res;
4484 struct pci_map *pm;
4485 pci_addr_t map, testval;
4486 int mapsize;
4487
4488 res = NULL;
4489 pm = pci_find_bar(child, *rid);
4490 if (pm != NULL) {
4491 /* This is a BAR that we failed to allocate earlier. */
4492 mapsize = pm->pm_size;
4493 map = pm->pm_value;
4494 } else {
4495 /*
4496 * Weed out the bogons, and figure out how large the
4497 * BAR/map is. BARs that read back 0 here are bogus
4498 * and unimplemented. Note: atapci in legacy mode are
4499 * special and handled elsewhere in the code. If you
4500 * have a atapci device in legacy mode and it fails
4501 * here, that other code is broken.
4502 */
4503 pci_read_bar(child, *rid, &map, &testval);
4504
4505 /*
4506 * Determine the size of the BAR and ignore BARs with a size
4507 * of 0. Device ROM BARs use a different mask value.
4508 */
4509 if (PCIR_IS_BIOS(&dinfo->cfg, *rid))
4510 mapsize = pci_romsize(testval);
4511 else
4512 mapsize = pci_mapsize(testval);
4513 if (mapsize == 0)
4514 goto out;
4515 pm = pci_add_bar(child, *rid, map, mapsize);
4516 }
4517
4518 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) {
4519 if (type != SYS_RES_MEMORY) {
4520 if (bootverbose)
4521 device_printf(dev,
4522 "child %s requested type %d for rid %#x,"
4523 " but the BAR says it is an memio\n",
4524 device_get_nameunit(child), type, *rid);
4525 goto out;
4526 }
4527 } else {
4528 if (type != SYS_RES_IOPORT) {
4529 if (bootverbose)
4530 device_printf(dev,
4531 "child %s requested type %d for rid %#x,"
4532 " but the BAR says it is an ioport\n",
4533 device_get_nameunit(child), type, *rid);
4534 goto out;
4535 }
4536 }
4537
4538 /*
4539 * For real BARs, we need to override the size that
4540 * the driver requests, because that's what the BAR
4541 * actually uses and we would otherwise have a
4542 * situation where we might allocate the excess to
4543 * another driver, which won't work.
4544 */
4545 count = (pci_addr_t)1 << mapsize;
4546 if (RF_ALIGNMENT(flags) < mapsize)
4547 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
4548 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH))
4549 flags |= RF_PREFETCHABLE;
4550
4551 /*
4552 * Allocate enough resource, and then write back the
4553 * appropriate BAR for that resource.
4554 */
4555 resource_list_add(rl, type, *rid, start, end, count);
4556 res = resource_list_reserve(rl, dev, child, type, rid, start, end,
4557 count, flags & ~RF_ACTIVE);
4558 if (res == NULL) {
4559 resource_list_delete(rl, type, *rid);
4560 device_printf(child,
4561 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
4562 count, *rid, type, start, end);
4563 goto out;
4564 }
4565 if (bootverbose)
4566 device_printf(child,
4567 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
4568 count, *rid, type, rman_get_start(res));
4569 map = rman_get_start(res);
4570 pci_write_bar(child, pm, map);
4571 out:
4572 return (res);
4573 }
4574
4575 struct resource *
pci_alloc_resource(device_t dev,device_t child,int type,int * rid,u_long start,u_long end,u_long count,u_int flags)4576 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
4577 u_long start, u_long end, u_long count, u_int flags)
4578 {
4579 struct pci_devinfo *dinfo;
4580 struct resource_list *rl;
4581 struct resource_list_entry *rle;
4582 struct resource *res;
4583 pcicfgregs *cfg;
4584
4585 if (device_get_parent(child) != dev)
4586 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
4587 type, rid, start, end, count, flags));
4588
4589 /*
4590 * Perform lazy resource allocation
4591 */
4592 dinfo = device_get_ivars(child);
4593 rl = &dinfo->resources;
4594 cfg = &dinfo->cfg;
4595 switch (type) {
4596 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
4597 case PCI_RES_BUS:
4598 return (pci_alloc_secbus(dev, child, rid, start, end, count,
4599 flags));
4600 #endif
4601 case SYS_RES_IRQ:
4602 /*
4603 * Can't alloc legacy interrupt once MSI messages have
4604 * been allocated.
4605 */
4606 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
4607 cfg->msix.msix_alloc > 0))
4608 return (NULL);
4609
4610 /*
4611 * If the child device doesn't have an interrupt
4612 * routed and is deserving of an interrupt, try to
4613 * assign it one.
4614 */
4615 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
4616 (cfg->intpin != 0))
4617 pci_assign_interrupt(dev, child, 0);
4618 break;
4619 case SYS_RES_IOPORT:
4620 case SYS_RES_MEMORY:
4621 #ifdef NEW_PCIB
4622 /*
4623 * PCI-PCI bridge I/O window resources are not BARs.
4624 * For those allocations just pass the request up the
4625 * tree.
4626 */
4627 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) {
4628 switch (*rid) {
4629 case PCIR_IOBASEL_1:
4630 case PCIR_MEMBASE_1:
4631 case PCIR_PMBASEL_1:
4632 /*
4633 * XXX: Should we bother creating a resource
4634 * list entry?
4635 */
4636 return (bus_generic_alloc_resource(dev, child,
4637 type, rid, start, end, count, flags));
4638 }
4639 }
4640 #endif
4641 /* Reserve resources for this BAR if needed. */
4642 rle = resource_list_find(rl, type, *rid);
4643 if (rle == NULL) {
4644 res = pci_reserve_map(dev, child, type, rid, start, end,
4645 count, flags);
4646 if (res == NULL)
4647 return (NULL);
4648 }
4649 }
4650 return (resource_list_alloc(rl, dev, child, type, rid,
4651 start, end, count, flags));
4652 }
4653
4654 int
pci_release_resource(device_t dev,device_t child,int type,int rid,struct resource * r)4655 pci_release_resource(device_t dev, device_t child, int type, int rid,
4656 struct resource *r)
4657 {
4658 struct pci_devinfo *dinfo;
4659 struct resource_list *rl;
4660 pcicfgregs *cfg;
4661
4662 if (device_get_parent(child) != dev)
4663 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
4664 type, rid, r));
4665
4666 dinfo = device_get_ivars(child);
4667 cfg = &dinfo->cfg;
4668 #ifdef NEW_PCIB
4669 /*
4670 * PCI-PCI bridge I/O window resources are not BARs. For
4671 * those allocations just pass the request up the tree.
4672 */
4673 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE &&
4674 (type == SYS_RES_IOPORT || type == SYS_RES_MEMORY)) {
4675 switch (rid) {
4676 case PCIR_IOBASEL_1:
4677 case PCIR_MEMBASE_1:
4678 case PCIR_PMBASEL_1:
4679 return (bus_generic_release_resource(dev, child, type,
4680 rid, r));
4681 }
4682 }
4683 #endif
4684
4685 rl = &dinfo->resources;
4686 return (resource_list_release(rl, dev, child, type, rid, r));
4687 }
4688
4689 int
pci_activate_resource(device_t dev,device_t child,int type,int rid,struct resource * r)4690 pci_activate_resource(device_t dev, device_t child, int type, int rid,
4691 struct resource *r)
4692 {
4693 struct pci_devinfo *dinfo;
4694 int error;
4695
4696 error = bus_generic_activate_resource(dev, child, type, rid, r);
4697 if (error)
4698 return (error);
4699
4700 /* Enable decoding in the command register when activating BARs. */
4701 if (device_get_parent(child) == dev) {
4702 /* Device ROMs need their decoding explicitly enabled. */
4703 dinfo = device_get_ivars(child);
4704 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
4705 pci_write_bar(child, pci_find_bar(child, rid),
4706 rman_get_start(r) | PCIM_BIOS_ENABLE);
4707 switch (type) {
4708 case SYS_RES_IOPORT:
4709 case SYS_RES_MEMORY:
4710 error = PCI_ENABLE_IO(dev, child, type);
4711 break;
4712 }
4713 }
4714 return (error);
4715 }
4716
4717 int
pci_deactivate_resource(device_t dev,device_t child,int type,int rid,struct resource * r)4718 pci_deactivate_resource(device_t dev, device_t child, int type,
4719 int rid, struct resource *r)
4720 {
4721 struct pci_devinfo *dinfo;
4722 int error;
4723
4724 error = bus_generic_deactivate_resource(dev, child, type, rid, r);
4725 if (error)
4726 return (error);
4727
4728 /* Disable decoding for device ROMs. */
4729 if (device_get_parent(child) == dev) {
4730 dinfo = device_get_ivars(child);
4731 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
4732 pci_write_bar(child, pci_find_bar(child, rid),
4733 rman_get_start(r));
4734 }
4735 return (0);
4736 }
4737
4738 void
pci_delete_child(device_t dev,device_t child)4739 pci_delete_child(device_t dev, device_t child)
4740 {
4741 struct resource_list_entry *rle;
4742 struct resource_list *rl;
4743 struct pci_devinfo *dinfo;
4744
4745 dinfo = device_get_ivars(child);
4746 rl = &dinfo->resources;
4747
4748 if (device_is_attached(child))
4749 device_detach(child);
4750
4751 /* Turn off access to resources we're about to free */
4752 pci_write_config(child, PCIR_COMMAND, pci_read_config(child,
4753 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2);
4754
4755 /* Free all allocated resources */
4756 STAILQ_FOREACH(rle, rl, link) {
4757 if (rle->res) {
4758 if (rman_get_flags(rle->res) & RF_ACTIVE ||
4759 resource_list_busy(rl, rle->type, rle->rid)) {
4760 pci_printf(&dinfo->cfg,
4761 "Resource still owned, oops. "
4762 "(type=%d, rid=%d, addr=%lx)\n",
4763 rle->type, rle->rid,
4764 rman_get_start(rle->res));
4765 bus_release_resource(child, rle->type, rle->rid,
4766 rle->res);
4767 }
4768 resource_list_unreserve(rl, dev, child, rle->type,
4769 rle->rid);
4770 }
4771 }
4772 resource_list_free(rl);
4773
4774 device_delete_child(dev, child);
4775 pci_freecfg(dinfo);
4776 }
4777
4778 void
pci_delete_resource(device_t dev,device_t child,int type,int rid)4779 pci_delete_resource(device_t dev, device_t child, int type, int rid)
4780 {
4781 struct pci_devinfo *dinfo;
4782 struct resource_list *rl;
4783 struct resource_list_entry *rle;
4784
4785 if (device_get_parent(child) != dev)
4786 return;
4787
4788 dinfo = device_get_ivars(child);
4789 rl = &dinfo->resources;
4790 rle = resource_list_find(rl, type, rid);
4791 if (rle == NULL)
4792 return;
4793
4794 if (rle->res) {
4795 if (rman_get_flags(rle->res) & RF_ACTIVE ||
4796 resource_list_busy(rl, type, rid)) {
4797 device_printf(dev, "delete_resource: "
4798 "Resource still owned by child, oops. "
4799 "(type=%d, rid=%d, addr=%lx)\n",
4800 type, rid, rman_get_start(rle->res));
4801 return;
4802 }
4803 resource_list_unreserve(rl, dev, child, type, rid);
4804 }
4805 resource_list_delete(rl, type, rid);
4806 }
4807
4808 struct resource_list *
pci_get_resource_list(device_t dev,device_t child)4809 pci_get_resource_list (device_t dev, device_t child)
4810 {
4811 struct pci_devinfo *dinfo = device_get_ivars(child);
4812
4813 return (&dinfo->resources);
4814 }
4815
4816 bus_dma_tag_t
pci_get_dma_tag(device_t bus,device_t dev)4817 pci_get_dma_tag(device_t bus, device_t dev)
4818 {
4819 struct pci_softc *sc = device_get_softc(bus);
4820
4821 return (sc->sc_dma_tag);
4822 }
4823
4824 uint32_t
pci_read_config_method(device_t dev,device_t child,int reg,int width)4825 pci_read_config_method(device_t dev, device_t child, int reg, int width)
4826 {
4827 struct pci_devinfo *dinfo = device_get_ivars(child);
4828 pcicfgregs *cfg = &dinfo->cfg;
4829
4830 return (PCIB_READ_CONFIG(device_get_parent(dev),
4831 cfg->bus, cfg->slot, cfg->func, reg, width));
4832 }
4833
4834 void
pci_write_config_method(device_t dev,device_t child,int reg,uint32_t val,int width)4835 pci_write_config_method(device_t dev, device_t child, int reg,
4836 uint32_t val, int width)
4837 {
4838 struct pci_devinfo *dinfo = device_get_ivars(child);
4839 pcicfgregs *cfg = &dinfo->cfg;
4840
4841 PCIB_WRITE_CONFIG(device_get_parent(dev),
4842 cfg->bus, cfg->slot, cfg->func, reg, val, width);
4843 }
4844
4845 int
pci_child_location_str_method(device_t dev,device_t child,char * buf,size_t buflen)4846 pci_child_location_str_method(device_t dev, device_t child, char *buf,
4847 size_t buflen)
4848 {
4849
4850 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
4851 pci_get_function(child));
4852 return (0);
4853 }
4854
4855 int
pci_child_pnpinfo_str_method(device_t dev,device_t child,char * buf,size_t buflen)4856 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
4857 size_t buflen)
4858 {
4859 struct pci_devinfo *dinfo;
4860 pcicfgregs *cfg;
4861
4862 dinfo = device_get_ivars(child);
4863 cfg = &dinfo->cfg;
4864 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
4865 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
4866 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
4867 cfg->progif);
4868 return (0);
4869 }
4870
4871 int
pci_assign_interrupt_method(device_t dev,device_t child)4872 pci_assign_interrupt_method(device_t dev, device_t child)
4873 {
4874 struct pci_devinfo *dinfo = device_get_ivars(child);
4875 pcicfgregs *cfg = &dinfo->cfg;
4876
4877 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
4878 cfg->intpin));
4879 }
4880
4881 static int
pci_modevent(module_t mod,int what,void * arg)4882 pci_modevent(module_t mod, int what, void *arg)
4883 {
4884 static struct cdev *pci_cdev;
4885
4886 switch (what) {
4887 case MOD_LOAD:
4888 STAILQ_INIT(&pci_devq);
4889 pci_generation = 0;
4890 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644,
4891 "pci");
4892 pci_load_vendor_data();
4893 break;
4894
4895 case MOD_UNLOAD:
4896 destroy_dev(pci_cdev);
4897 break;
4898 }
4899
4900 return (0);
4901 }
4902
4903 static void
pci_cfg_restore_pcie(device_t dev,struct pci_devinfo * dinfo)4904 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo)
4905 {
4906 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2)
4907 struct pcicfg_pcie *cfg;
4908 int version, pos;
4909
4910 cfg = &dinfo->cfg.pcie;
4911 pos = cfg->pcie_location;
4912
4913 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION;
4914
4915 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl);
4916
4917 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4918 cfg->pcie_type == PCIEM_TYPE_ENDPOINT ||
4919 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT)
4920 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl);
4921
4922 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4923 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT &&
4924 (cfg->pcie_flags & PCIEM_FLAGS_SLOT))))
4925 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl);
4926
4927 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4928 cfg->pcie_type == PCIEM_TYPE_ROOT_EC)
4929 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl);
4930
4931 if (version > 1) {
4932 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2);
4933 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2);
4934 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2);
4935 }
4936 #undef WREG
4937 }
4938
4939 static void
pci_cfg_restore_pcix(device_t dev,struct pci_devinfo * dinfo)4940 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo)
4941 {
4942 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND,
4943 dinfo->cfg.pcix.pcix_command, 2);
4944 }
4945
4946 void
pci_cfg_restore(device_t dev,struct pci_devinfo * dinfo)4947 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
4948 {
4949
4950 /*
4951 * Restore the device to full power mode. We must do this
4952 * before we restore the registers because moving from D3 to
4953 * D0 will cause the chip's BARs and some other registers to
4954 * be reset to some unknown power on reset values. Cut down
4955 * the noise on boot by doing nothing if we are already in
4956 * state D0.
4957 */
4958 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0)
4959 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4960 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
4961 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
4962 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
4963 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
4964 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
4965 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
4966 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
4967 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) {
4968 case PCIM_HDRTYPE_NORMAL:
4969 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
4970 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
4971 break;
4972 case PCIM_HDRTYPE_BRIDGE:
4973 pci_write_config(dev, PCIR_SECLAT_1,
4974 dinfo->cfg.bridge.br_seclat, 1);
4975 pci_write_config(dev, PCIR_SUBBUS_1,
4976 dinfo->cfg.bridge.br_subbus, 1);
4977 pci_write_config(dev, PCIR_SECBUS_1,
4978 dinfo->cfg.bridge.br_secbus, 1);
4979 pci_write_config(dev, PCIR_PRIBUS_1,
4980 dinfo->cfg.bridge.br_pribus, 1);
4981 pci_write_config(dev, PCIR_BRIDGECTL_1,
4982 dinfo->cfg.bridge.br_control, 2);
4983 break;
4984 case PCIM_HDRTYPE_CARDBUS:
4985 pci_write_config(dev, PCIR_SECLAT_2,
4986 dinfo->cfg.bridge.br_seclat, 1);
4987 pci_write_config(dev, PCIR_SUBBUS_2,
4988 dinfo->cfg.bridge.br_subbus, 1);
4989 pci_write_config(dev, PCIR_SECBUS_2,
4990 dinfo->cfg.bridge.br_secbus, 1);
4991 pci_write_config(dev, PCIR_PRIBUS_2,
4992 dinfo->cfg.bridge.br_pribus, 1);
4993 pci_write_config(dev, PCIR_BRIDGECTL_2,
4994 dinfo->cfg.bridge.br_control, 2);
4995 break;
4996 }
4997 pci_restore_bars(dev);
4998
4999 /*
5000 * Restore extended capabilities for PCI-Express and PCI-X
5001 */
5002 if (dinfo->cfg.pcie.pcie_location != 0)
5003 pci_cfg_restore_pcie(dev, dinfo);
5004 if (dinfo->cfg.pcix.pcix_location != 0)
5005 pci_cfg_restore_pcix(dev, dinfo);
5006
5007 /* Restore MSI and MSI-X configurations if they are present. */
5008 if (dinfo->cfg.msi.msi_location != 0)
5009 pci_resume_msi(dev);
5010 if (dinfo->cfg.msix.msix_location != 0)
5011 pci_resume_msix(dev);
5012 }
5013
5014 static void
pci_cfg_save_pcie(device_t dev,struct pci_devinfo * dinfo)5015 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo)
5016 {
5017 #define RREG(n) pci_read_config(dev, pos + (n), 2)
5018 struct pcicfg_pcie *cfg;
5019 int version, pos;
5020
5021 cfg = &dinfo->cfg.pcie;
5022 pos = cfg->pcie_location;
5023
5024 cfg->pcie_flags = RREG(PCIER_FLAGS);
5025
5026 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION;
5027
5028 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL);
5029
5030 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
5031 cfg->pcie_type == PCIEM_TYPE_ENDPOINT ||
5032 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT)
5033 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL);
5034
5035 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
5036 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT &&
5037 (cfg->pcie_flags & PCIEM_FLAGS_SLOT))))
5038 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL);
5039
5040 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
5041 cfg->pcie_type == PCIEM_TYPE_ROOT_EC)
5042 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL);
5043
5044 if (version > 1) {
5045 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2);
5046 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2);
5047 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2);
5048 }
5049 #undef RREG
5050 }
5051
5052 static void
pci_cfg_save_pcix(device_t dev,struct pci_devinfo * dinfo)5053 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo)
5054 {
5055 dinfo->cfg.pcix.pcix_command = pci_read_config(dev,
5056 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2);
5057 }
5058
5059 void
pci_cfg_save(device_t dev,struct pci_devinfo * dinfo,int setstate)5060 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
5061 {
5062 uint32_t cls;
5063 int ps;
5064
5065 /*
5066 * Some drivers apparently write to these registers w/o updating our
5067 * cached copy. No harm happens if we update the copy, so do so here
5068 * so we can restore them. The COMMAND register is modified by the
5069 * bus w/o updating the cache. This should represent the normally
5070 * writable portion of the 'defined' part of type 0/1/2 headers.
5071 */
5072 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
5073 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
5074 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
5075 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
5076 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
5077 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
5078 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
5079 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
5080 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
5081 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
5082 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
5083 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) {
5084 case PCIM_HDRTYPE_NORMAL:
5085 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
5086 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
5087 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
5088 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
5089 break;
5090 case PCIM_HDRTYPE_BRIDGE:
5091 dinfo->cfg.bridge.br_seclat = pci_read_config(dev,
5092 PCIR_SECLAT_1, 1);
5093 dinfo->cfg.bridge.br_subbus = pci_read_config(dev,
5094 PCIR_SUBBUS_1, 1);
5095 dinfo->cfg.bridge.br_secbus = pci_read_config(dev,
5096 PCIR_SECBUS_1, 1);
5097 dinfo->cfg.bridge.br_pribus = pci_read_config(dev,
5098 PCIR_PRIBUS_1, 1);
5099 dinfo->cfg.bridge.br_control = pci_read_config(dev,
5100 PCIR_BRIDGECTL_1, 2);
5101 break;
5102 case PCIM_HDRTYPE_CARDBUS:
5103 dinfo->cfg.bridge.br_seclat = pci_read_config(dev,
5104 PCIR_SECLAT_2, 1);
5105 dinfo->cfg.bridge.br_subbus = pci_read_config(dev,
5106 PCIR_SUBBUS_2, 1);
5107 dinfo->cfg.bridge.br_secbus = pci_read_config(dev,
5108 PCIR_SECBUS_2, 1);
5109 dinfo->cfg.bridge.br_pribus = pci_read_config(dev,
5110 PCIR_PRIBUS_2, 1);
5111 dinfo->cfg.bridge.br_control = pci_read_config(dev,
5112 PCIR_BRIDGECTL_2, 2);
5113 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2);
5114 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2);
5115 break;
5116 }
5117
5118 if (dinfo->cfg.pcie.pcie_location != 0)
5119 pci_cfg_save_pcie(dev, dinfo);
5120
5121 if (dinfo->cfg.pcix.pcix_location != 0)
5122 pci_cfg_save_pcix(dev, dinfo);
5123
5124 /*
5125 * don't set the state for display devices, base peripherals and
5126 * memory devices since bad things happen when they are powered down.
5127 * We should (a) have drivers that can easily detach and (b) use
5128 * generic drivers for these devices so that some device actually
5129 * attaches. We need to make sure that when we implement (a) we don't
5130 * power the device down on a reattach.
5131 */
5132 cls = pci_get_class(dev);
5133 if (!setstate)
5134 return;
5135 switch (pci_do_power_nodriver)
5136 {
5137 case 0: /* NO powerdown at all */
5138 return;
5139 case 1: /* Conservative about what to power down */
5140 if (cls == PCIC_STORAGE)
5141 return;
5142 /*FALLTHROUGH*/
5143 case 2: /* Agressive about what to power down */
5144 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
5145 cls == PCIC_BASEPERIPH)
5146 return;
5147 /*FALLTHROUGH*/
5148 case 3: /* Power down everything */
5149 break;
5150 }
5151 /*
5152 * PCI spec says we can only go into D3 state from D0 state.
5153 * Transition from D[12] into D0 before going to D3 state.
5154 */
5155 ps = pci_get_powerstate(dev);
5156 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
5157 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
5158 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
5159 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
5160 }
5161
5162 /* Wrapper APIs suitable for device driver use. */
5163 void
pci_save_state(device_t dev)5164 pci_save_state(device_t dev)
5165 {
5166 struct pci_devinfo *dinfo;
5167
5168 dinfo = device_get_ivars(dev);
5169 pci_cfg_save(dev, dinfo, 0);
5170 }
5171
5172 void
pci_restore_state(device_t dev)5173 pci_restore_state(device_t dev)
5174 {
5175 struct pci_devinfo *dinfo;
5176
5177 dinfo = device_get_ivars(dev);
5178 pci_cfg_restore(dev, dinfo);
5179 }
5180
5181 static uint16_t
pci_get_rid_method(device_t dev,device_t child)5182 pci_get_rid_method(device_t dev, device_t child)
5183 {
5184
5185 return (PCIB_GET_RID(device_get_parent(dev), child));
5186 }
5187