1 /*-
2 * Copyright (c) 2013-2021, Mellanox Technologies, Ltd. All rights reserved.
3 * Copyright (c) 2022 NVIDIA corporation & affiliates.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include "opt_rss.h"
28 #include "opt_ratelimit.h"
29
30 #include <linux/kmod.h>
31 #include <linux/module.h>
32 #include <linux/errno.h>
33 #include <linux/pci.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/slab.h>
36 #include <linux/io-mapping.h>
37 #include <linux/interrupt.h>
38 #include <linux/hardirq.h>
39 #include <dev/mlx5/driver.h>
40 #include <dev/mlx5/cq.h>
41 #include <dev/mlx5/qp.h>
42 #include <dev/mlx5/srq.h>
43 #include <dev/mlx5/mpfs.h>
44 #include <dev/mlx5/vport.h>
45 #include <linux/delay.h>
46 #include <dev/mlx5/mlx5_ifc.h>
47 #include <dev/mlx5/mlx5_fpga/core.h>
48 #include <dev/mlx5/mlx5_lib/mlx5.h>
49 #include <dev/mlx5/mlx5_core/mlx5_core.h>
50 #include <dev/mlx5/mlx5_core/eswitch.h>
51 #include <dev/mlx5/mlx5_core/fs_core.h>
52 #include <dev/mlx5/mlx5_core/diag_cnt.h>
53 #ifdef PCI_IOV
54 #include <sys/nv.h>
55 #include <sys/socket.h>
56 #include <dev/pci/pci_iov.h>
57 #include <sys/iov_schema.h>
58 #include <sys/iov.h>
59 #include <net/if.h>
60 #include <net/if_vlan_var.h>
61 #endif
62
63 static const char mlx5_version[] = "Mellanox Core driver "
64 DRIVER_VERSION " (" DRIVER_RELDATE ")";
65 MODULE_DESCRIPTION("Mellanox ConnectX-4 and onwards core driver");
66 MODULE_LICENSE("Dual BSD/GPL");
67 MODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1);
68 MODULE_DEPEND(mlx5, mlxfw, 1, 1, 1);
69 MODULE_DEPEND(mlx5, firmware, 1, 1, 1);
70 MODULE_VERSION(mlx5, 1);
71
72 SYSCTL_NODE(_hw, OID_AUTO, mlx5, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
73 "mlx5 hardware controls");
74
75 int mlx5_core_debug_mask;
76 SYSCTL_INT(_hw_mlx5, OID_AUTO, debug_mask, CTLFLAG_RWTUN,
77 &mlx5_core_debug_mask, 0,
78 "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
79
80 #define MLX5_DEFAULT_PROF 2
81 static int mlx5_prof_sel = MLX5_DEFAULT_PROF;
82 SYSCTL_INT(_hw_mlx5, OID_AUTO, prof_sel, CTLFLAG_RWTUN,
83 &mlx5_prof_sel, 0,
84 "profile selector. Valid range 0 - 2");
85
86 static int mlx5_fast_unload_enabled = 1;
87 SYSCTL_INT(_hw_mlx5, OID_AUTO, fast_unload_enabled, CTLFLAG_RWTUN,
88 &mlx5_fast_unload_enabled, 0,
89 "Set to enable fast unload. Clear to disable.");
90
91 static int mlx5_core_comp_eq_size = 1024;
92 SYSCTL_INT(_hw_mlx5, OID_AUTO, comp_eq_size, CTLFLAG_RDTUN | CTLFLAG_MPSAFE,
93 &mlx5_core_comp_eq_size, 0,
94 "Set default completion EQ size between 1024 and 16384 inclusivly. Value should be power of two.");
95
96 static LIST_HEAD(intf_list);
97 static LIST_HEAD(dev_list);
98 static DEFINE_MUTEX(intf_mutex);
99
100 struct mlx5_device_context {
101 struct list_head list;
102 struct mlx5_interface *intf;
103 void *context;
104 };
105
106 enum {
107 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
108 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
109 };
110
111 static struct mlx5_profile profiles[] = {
112 [0] = {
113 .mask = 0,
114 },
115 [1] = {
116 .mask = MLX5_PROF_MASK_QP_SIZE,
117 .log_max_qp = 12,
118 },
119 [2] = {
120 .mask = MLX5_PROF_MASK_QP_SIZE |
121 MLX5_PROF_MASK_MR_CACHE,
122 .log_max_qp = 17,
123 .mr_cache[0] = {
124 .size = 500,
125 .limit = 250
126 },
127 .mr_cache[1] = {
128 .size = 500,
129 .limit = 250
130 },
131 .mr_cache[2] = {
132 .size = 500,
133 .limit = 250
134 },
135 .mr_cache[3] = {
136 .size = 500,
137 .limit = 250
138 },
139 .mr_cache[4] = {
140 .size = 500,
141 .limit = 250
142 },
143 .mr_cache[5] = {
144 .size = 500,
145 .limit = 250
146 },
147 .mr_cache[6] = {
148 .size = 500,
149 .limit = 250
150 },
151 .mr_cache[7] = {
152 .size = 500,
153 .limit = 250
154 },
155 .mr_cache[8] = {
156 .size = 500,
157 .limit = 250
158 },
159 .mr_cache[9] = {
160 .size = 500,
161 .limit = 250
162 },
163 .mr_cache[10] = {
164 .size = 500,
165 .limit = 250
166 },
167 .mr_cache[11] = {
168 .size = 500,
169 .limit = 250
170 },
171 .mr_cache[12] = {
172 .size = 64,
173 .limit = 32
174 },
175 .mr_cache[13] = {
176 .size = 32,
177 .limit = 16
178 },
179 .mr_cache[14] = {
180 .size = 16,
181 .limit = 8
182 },
183 },
184 [3] = {
185 .mask = MLX5_PROF_MASK_QP_SIZE,
186 .log_max_qp = 17,
187 },
188 };
189
190 static int
mlx5_core_get_comp_eq_size(void)191 mlx5_core_get_comp_eq_size(void)
192 {
193 int value = mlx5_core_comp_eq_size;
194
195 if (value < 1024)
196 value = 1024;
197 else if (value > 16384)
198 value = 16384;
199
200 /* make value power of two, rounded down */
201 while (value & (value - 1))
202 value &= (value - 1);
203 return (value);
204 }
205
mlx5_set_driver_version(struct mlx5_core_dev * dev)206 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
207 {
208 const size_t driver_ver_sz =
209 MLX5_FLD_SZ_BYTES(set_driver_version_in, driver_version);
210 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
211 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {};
212 char *string;
213
214 if (!MLX5_CAP_GEN(dev, driver_version))
215 return;
216
217 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
218
219 snprintf(string, driver_ver_sz, "FreeBSD,mlx5_core,%u.%u.%u," DRIVER_VERSION,
220 __FreeBSD_version / 100000, (__FreeBSD_version / 1000) % 100,
221 __FreeBSD_version % 1000);
222
223 /* Send the command */
224 MLX5_SET(set_driver_version_in, in, opcode,
225 MLX5_CMD_OP_SET_DRIVER_VERSION);
226
227 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
228 }
229
230 #ifdef PCI_IOV
231 static const char iov_mac_addr_name[] = "mac-addr";
232 static const char iov_vlan_name[] = "vlan";
233 static const char iov_node_guid_name[] = "node-guid";
234 static const char iov_port_guid_name[] = "port-guid";
235 #endif
236
set_dma_caps(struct pci_dev * pdev)237 static int set_dma_caps(struct pci_dev *pdev)
238 {
239 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
240 int err;
241
242 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
243 if (err) {
244 mlx5_core_warn(dev, "couldn't set 64-bit PCI DMA mask\n");
245 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
246 if (err) {
247 mlx5_core_err(dev, "Can't set PCI DMA mask, aborting\n");
248 return err;
249 }
250 }
251
252 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
253 if (err) {
254 mlx5_core_warn(dev, "couldn't set 64-bit consistent PCI DMA mask\n");
255 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
256 if (err) {
257 mlx5_core_err(dev, "Can't set consistent PCI DMA mask, aborting\n");
258 return err;
259 }
260 }
261
262 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
263 return err;
264 }
265
mlx5_pci_read_power_status(struct mlx5_core_dev * dev,u16 * p_power,u8 * p_status)266 int mlx5_pci_read_power_status(struct mlx5_core_dev *dev,
267 u16 *p_power, u8 *p_status)
268 {
269 u32 in[MLX5_ST_SZ_DW(mpein_reg)] = {};
270 u32 out[MLX5_ST_SZ_DW(mpein_reg)] = {};
271 int err;
272
273 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
274 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN, 0, 0);
275
276 *p_status = MLX5_GET(mpein_reg, out, pwr_status);
277 *p_power = MLX5_GET(mpein_reg, out, pci_power);
278 return err;
279 }
280
mlx5_pci_enable_device(struct mlx5_core_dev * dev)281 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
282 {
283 struct pci_dev *pdev = dev->pdev;
284 int err = 0;
285
286 mutex_lock(&dev->pci_status_mutex);
287 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
288 err = pci_enable_device(pdev);
289 if (!err)
290 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
291 }
292 mutex_unlock(&dev->pci_status_mutex);
293
294 return err;
295 }
296
mlx5_pci_disable_device(struct mlx5_core_dev * dev)297 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
298 {
299 struct pci_dev *pdev = dev->pdev;
300
301 mutex_lock(&dev->pci_status_mutex);
302 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
303 pci_disable_device(pdev);
304 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
305 }
306 mutex_unlock(&dev->pci_status_mutex);
307 }
308
request_bar(struct pci_dev * pdev)309 static int request_bar(struct pci_dev *pdev)
310 {
311 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
312 int err = 0;
313
314 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
315 mlx5_core_err(dev, "Missing registers BAR, aborting\n");
316 return -ENODEV;
317 }
318
319 err = pci_request_regions(pdev, DRIVER_NAME);
320 if (err)
321 mlx5_core_err(dev, "Couldn't get PCI resources, aborting\n");
322
323 return err;
324 }
325
release_bar(struct pci_dev * pdev)326 static void release_bar(struct pci_dev *pdev)
327 {
328 pci_release_regions(pdev);
329 }
330
mlx5_enable_msix(struct mlx5_core_dev * dev)331 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
332 {
333 struct mlx5_priv *priv = &dev->priv;
334 struct mlx5_eq_table *table = &priv->eq_table;
335 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
336 int limit = dev->msix_eqvec;
337 int nvec = MLX5_EQ_VEC_COMP_BASE;
338 int i;
339
340 if (limit > 0)
341 nvec += limit;
342 else
343 nvec += MLX5_CAP_GEN(dev, num_ports) * num_online_cpus();
344
345 if (nvec > num_eqs)
346 nvec = num_eqs;
347 if (nvec > 256)
348 nvec = 256; /* limit of firmware API */
349 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
350 return -ENOMEM;
351
352 priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL);
353
354 for (i = 0; i < nvec; i++)
355 priv->msix_arr[i].entry = i;
356
357 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
358 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
359 if (nvec < 0)
360 return nvec;
361
362 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
363 return 0;
364 }
365
mlx5_disable_msix(struct mlx5_core_dev * dev)366 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
367 {
368 struct mlx5_priv *priv = &dev->priv;
369
370 pci_disable_msix(dev->pdev);
371 kfree(priv->msix_arr);
372 }
373
374 struct mlx5_reg_host_endianess {
375 u8 he;
376 u8 rsvd[15];
377 };
378
379
380 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
381
382 enum {
383 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
384 MLX5_DEV_CAP_FLAG_DCT |
385 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR,
386 };
387
to_fw_pkey_sz(struct mlx5_core_dev * dev,u32 size)388 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
389 {
390 switch (size) {
391 case 128:
392 return 0;
393 case 256:
394 return 1;
395 case 512:
396 return 2;
397 case 1024:
398 return 3;
399 case 2048:
400 return 4;
401 case 4096:
402 return 5;
403 default:
404 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
405 return 0;
406 }
407 }
408
mlx5_core_get_caps_mode(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type,enum mlx5_cap_mode cap_mode)409 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
410 enum mlx5_cap_type cap_type,
411 enum mlx5_cap_mode cap_mode)
412 {
413 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
414 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
415 void *out, *hca_caps;
416 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
417 int err;
418
419 memset(in, 0, sizeof(in));
420 out = kzalloc(out_sz, GFP_KERNEL);
421
422 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
423 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
424 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
425 if (err) {
426 mlx5_core_warn(dev,
427 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
428 cap_type, cap_mode, err);
429 goto query_ex;
430 }
431
432 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
433
434 switch (cap_mode) {
435 case HCA_CAP_OPMOD_GET_MAX:
436 memcpy(dev->hca_caps_max[cap_type], hca_caps,
437 MLX5_UN_SZ_BYTES(hca_cap_union));
438 break;
439 case HCA_CAP_OPMOD_GET_CUR:
440 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
441 MLX5_UN_SZ_BYTES(hca_cap_union));
442 break;
443 default:
444 mlx5_core_warn(dev,
445 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
446 cap_type, cap_mode);
447 err = -EINVAL;
448 break;
449 }
450 query_ex:
451 kfree(out);
452 return err;
453 }
454
mlx5_core_get_caps(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type)455 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
456 {
457 int ret;
458
459 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
460 if (ret)
461 return ret;
462
463 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
464 }
465
set_caps(struct mlx5_core_dev * dev,void * in,int in_sz)466 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
467 {
468 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
469
470 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
471
472 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
473 }
474
handle_hca_cap(struct mlx5_core_dev * dev)475 static int handle_hca_cap(struct mlx5_core_dev *dev)
476 {
477 void *set_ctx = NULL;
478 struct mlx5_profile *prof = dev->profile;
479 int err = -ENOMEM;
480 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
481 void *set_hca_cap;
482
483 set_ctx = kzalloc(set_sz, GFP_KERNEL);
484
485 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
486 if (err)
487 goto query_ex;
488
489 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
490 capability);
491 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
492 MLX5_ST_SZ_BYTES(cmd_hca_cap));
493
494 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
495 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
496 128);
497 /* we limit the size of the pkey table to 128 entries for now */
498 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
499 to_fw_pkey_sz(dev, 128));
500
501 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
502 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
503 prof->log_max_qp);
504
505 /* disable cmdif checksum */
506 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
507
508 /* Enable 4K UAR only when HCA supports it and page size is bigger
509 * than 4K.
510 */
511 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
512 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
513
514 /* enable drain sigerr */
515 MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1);
516
517 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
518
519 err = set_caps(dev, set_ctx, set_sz);
520
521 query_ex:
522 kfree(set_ctx);
523 return err;
524 }
525
handle_hca_cap_atomic(struct mlx5_core_dev * dev)526 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
527 {
528 void *set_ctx;
529 void *set_hca_cap;
530 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
531 int req_endianness;
532 int err;
533
534 if (MLX5_CAP_GEN(dev, atomic)) {
535 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
536 if (err)
537 return err;
538 } else {
539 return 0;
540 }
541
542 req_endianness =
543 MLX5_CAP_ATOMIC(dev,
544 supported_atomic_req_8B_endianess_mode_1);
545
546 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
547 return 0;
548
549 set_ctx = kzalloc(set_sz, GFP_KERNEL);
550 if (!set_ctx)
551 return -ENOMEM;
552
553 MLX5_SET(set_hca_cap_in, set_ctx, op_mod,
554 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC << 1);
555 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
556
557 /* Set requestor to host endianness */
558 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
559 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
560
561 err = set_caps(dev, set_ctx, set_sz);
562
563 kfree(set_ctx);
564 return err;
565 }
566
set_hca_ctrl(struct mlx5_core_dev * dev)567 static int set_hca_ctrl(struct mlx5_core_dev *dev)
568 {
569 struct mlx5_reg_host_endianess he_in;
570 struct mlx5_reg_host_endianess he_out;
571 int err;
572
573 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
574 !MLX5_CAP_GEN(dev, roce))
575 return 0;
576
577 memset(&he_in, 0, sizeof(he_in));
578 he_in.he = MLX5_SET_HOST_ENDIANNESS;
579 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
580 &he_out, sizeof(he_out),
581 MLX5_REG_HOST_ENDIANNESS, 0, 1);
582 return err;
583 }
584
mlx5_core_set_hca_defaults(struct mlx5_core_dev * dev)585 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
586 {
587 int ret = 0;
588
589 /* Disable local_lb by default */
590 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
591 ret = mlx5_nic_vport_update_local_lb(dev, false);
592
593 return ret;
594 }
595
mlx5_core_enable_hca(struct mlx5_core_dev * dev,u16 func_id)596 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
597 {
598 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
599 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
600
601 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
602 MLX5_SET(enable_hca_in, in, function_id, func_id);
603 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
604 }
605
mlx5_core_disable_hca(struct mlx5_core_dev * dev)606 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
607 {
608 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
609 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
610
611 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
612 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
613 }
614
mlx5_core_set_issi(struct mlx5_core_dev * dev)615 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
616 {
617 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
618 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
619 u32 sup_issi;
620 int err;
621
622 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
623
624 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), query_out, sizeof(query_out));
625 if (err) {
626 u32 syndrome;
627 u8 status;
628
629 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
630 if (status == MLX5_CMD_STAT_BAD_OP_ERR) {
631 mlx5_core_dbg(dev, "Only ISSI 0 is supported\n");
632 return 0;
633 }
634
635 mlx5_core_err(dev, "failed to query ISSI\n");
636 return err;
637 }
638
639 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
640
641 if (sup_issi & (1 << 1)) {
642 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
643 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
644
645 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
646 MLX5_SET(set_issi_in, set_in, current_issi, 1);
647
648 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), set_out, sizeof(set_out));
649 if (err) {
650 mlx5_core_err(dev, "failed to set ISSI=1 err(%d)\n", err);
651 return err;
652 }
653
654 dev->issi = 1;
655
656 return 0;
657 } else if (sup_issi & (1 << 0)) {
658 return 0;
659 }
660
661 return -ENOTSUPP;
662 }
663
664
mlx5_vector2eqn(struct mlx5_core_dev * dev,int vector,int * eqn,int * irqn)665 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
666 {
667 struct mlx5_eq_table *table = &dev->priv.eq_table;
668 struct mlx5_eq *eq;
669 int err = -ENOENT;
670
671 spin_lock(&table->lock);
672 list_for_each_entry(eq, &table->comp_eqs_list, list) {
673 if (eq->index == vector) {
674 *eqn = eq->eqn;
675 *irqn = eq->irqn;
676 err = 0;
677 break;
678 }
679 }
680 spin_unlock(&table->lock);
681
682 return err;
683 }
684 EXPORT_SYMBOL(mlx5_vector2eqn);
685
free_comp_eqs(struct mlx5_core_dev * dev)686 static void free_comp_eqs(struct mlx5_core_dev *dev)
687 {
688 struct mlx5_eq_table *table = &dev->priv.eq_table;
689 struct mlx5_eq *eq, *n;
690
691 spin_lock(&table->lock);
692 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
693 list_del(&eq->list);
694 spin_unlock(&table->lock);
695 if (mlx5_destroy_unmap_eq(dev, eq))
696 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
697 eq->eqn);
698 kfree(eq);
699 spin_lock(&table->lock);
700 }
701 spin_unlock(&table->lock);
702 }
703
alloc_comp_eqs(struct mlx5_core_dev * dev)704 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
705 {
706 struct mlx5_eq_table *table = &dev->priv.eq_table;
707 struct mlx5_eq *eq;
708 int ncomp_vec;
709 int nent;
710 int err;
711 int i;
712
713 INIT_LIST_HEAD(&table->comp_eqs_list);
714 ncomp_vec = table->num_comp_vectors;
715 nent = mlx5_core_get_comp_eq_size();
716 for (i = 0; i < ncomp_vec; i++) {
717 eq = kzalloc_node(sizeof(*eq), GFP_KERNEL, dev->priv.numa_node);
718
719 err = mlx5_create_map_eq(dev, eq,
720 i + MLX5_EQ_VEC_COMP_BASE, nent, 0);
721 if (err) {
722 kfree(eq);
723 goto clean;
724 }
725 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
726 eq->index = i;
727 spin_lock(&table->lock);
728 list_add_tail(&eq->list, &table->comp_eqs_list);
729 spin_unlock(&table->lock);
730 }
731
732 return 0;
733
734 clean:
735 free_comp_eqs(dev);
736 return err;
737 }
738
fw_initializing(struct mlx5_core_dev * dev)739 static inline int fw_initializing(struct mlx5_core_dev *dev)
740 {
741 return ioread32be(&dev->iseg->initializing) >> 31;
742 }
743
wait_fw_init(struct mlx5_core_dev * dev,u32 max_wait_mili,u32 warn_time_mili)744 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
745 u32 warn_time_mili)
746 {
747 int warn = jiffies + msecs_to_jiffies(warn_time_mili);
748 int end = jiffies + msecs_to_jiffies(max_wait_mili);
749 int err = 0;
750
751 MPASS(max_wait_mili > warn_time_mili);
752
753 while (fw_initializing(dev) == 1) {
754 if (time_after(jiffies, end)) {
755 err = -EBUSY;
756 break;
757 }
758 if (warn_time_mili && time_after(jiffies, warn)) {
759 mlx5_core_warn(dev,
760 "Waiting for FW initialization, timeout abort in %u s\n",
761 (unsigned)(jiffies_to_msecs(end - warn) / 1000));
762 warn = jiffies + msecs_to_jiffies(warn_time_mili);
763 }
764 msleep(FW_INIT_WAIT_MS);
765 }
766
767 if (err != 0)
768 mlx5_core_dbg(dev, "Full initializing bit dword = 0x%x\n",
769 ioread32be(&dev->iseg->initializing));
770
771 return err;
772 }
773
mlx5_add_device(struct mlx5_interface * intf,struct mlx5_priv * priv)774 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
775 {
776 struct mlx5_device_context *dev_ctx;
777 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
778
779 dev_ctx = kzalloc_node(sizeof(*dev_ctx), GFP_KERNEL, priv->numa_node);
780 if (!dev_ctx)
781 return;
782
783 dev_ctx->intf = intf;
784 CURVNET_SET_QUIET(vnet0);
785 dev_ctx->context = intf->add(dev);
786 CURVNET_RESTORE();
787
788 if (dev_ctx->context) {
789 spin_lock_irq(&priv->ctx_lock);
790 list_add_tail(&dev_ctx->list, &priv->ctx_list);
791 spin_unlock_irq(&priv->ctx_lock);
792 } else {
793 kfree(dev_ctx);
794 }
795 }
796
mlx5_remove_device(struct mlx5_interface * intf,struct mlx5_priv * priv)797 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
798 {
799 struct mlx5_device_context *dev_ctx;
800 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
801
802 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
803 if (dev_ctx->intf == intf) {
804 spin_lock_irq(&priv->ctx_lock);
805 list_del(&dev_ctx->list);
806 spin_unlock_irq(&priv->ctx_lock);
807
808 intf->remove(dev, dev_ctx->context);
809 kfree(dev_ctx);
810 return;
811 }
812 }
813
814 int
mlx5_register_device(struct mlx5_core_dev * dev)815 mlx5_register_device(struct mlx5_core_dev *dev)
816 {
817 struct mlx5_priv *priv = &dev->priv;
818 struct mlx5_interface *intf;
819
820 mutex_lock(&intf_mutex);
821 list_add_tail(&priv->dev_list, &dev_list);
822 list_for_each_entry(intf, &intf_list, list)
823 mlx5_add_device(intf, priv);
824 mutex_unlock(&intf_mutex);
825
826 return 0;
827 }
828
829 void
mlx5_unregister_device(struct mlx5_core_dev * dev)830 mlx5_unregister_device(struct mlx5_core_dev *dev)
831 {
832 struct mlx5_priv *priv = &dev->priv;
833 struct mlx5_interface *intf;
834
835 mutex_lock(&intf_mutex);
836 list_for_each_entry(intf, &intf_list, list)
837 mlx5_remove_device(intf, priv);
838 list_del(&priv->dev_list);
839 mutex_unlock(&intf_mutex);
840 }
841
mlx5_register_interface(struct mlx5_interface * intf)842 int mlx5_register_interface(struct mlx5_interface *intf)
843 {
844 struct mlx5_priv *priv;
845
846 if (!intf->add || !intf->remove)
847 return -EINVAL;
848
849 mutex_lock(&intf_mutex);
850 list_add_tail(&intf->list, &intf_list);
851 list_for_each_entry(priv, &dev_list, dev_list)
852 mlx5_add_device(intf, priv);
853 mutex_unlock(&intf_mutex);
854
855 return 0;
856 }
857 EXPORT_SYMBOL(mlx5_register_interface);
858
mlx5_unregister_interface(struct mlx5_interface * intf)859 void mlx5_unregister_interface(struct mlx5_interface *intf)
860 {
861 struct mlx5_priv *priv;
862
863 mutex_lock(&intf_mutex);
864 list_for_each_entry(priv, &dev_list, dev_list)
865 mlx5_remove_device(intf, priv);
866 list_del(&intf->list);
867 mutex_unlock(&intf_mutex);
868 }
869 EXPORT_SYMBOL(mlx5_unregister_interface);
870
mlx5_get_protocol_dev(struct mlx5_core_dev * mdev,int protocol)871 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
872 {
873 struct mlx5_priv *priv = &mdev->priv;
874 struct mlx5_device_context *dev_ctx;
875 unsigned long flags;
876 void *result = NULL;
877
878 spin_lock_irqsave(&priv->ctx_lock, flags);
879
880 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
881 if ((dev_ctx->intf->protocol == protocol) &&
882 dev_ctx->intf->get_dev) {
883 result = dev_ctx->intf->get_dev(dev_ctx->context);
884 break;
885 }
886
887 spin_unlock_irqrestore(&priv->ctx_lock, flags);
888
889 return result;
890 }
891 EXPORT_SYMBOL(mlx5_get_protocol_dev);
892
893 static int mlx5_auto_fw_update;
894 SYSCTL_INT(_hw_mlx5, OID_AUTO, auto_fw_update, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
895 &mlx5_auto_fw_update, 0,
896 "Allow automatic firmware update on driver start");
897 static int
mlx5_firmware_update(struct mlx5_core_dev * dev)898 mlx5_firmware_update(struct mlx5_core_dev *dev)
899 {
900 const struct firmware *fw;
901 int err;
902
903 TUNABLE_INT_FETCH("hw.mlx5.auto_fw_update", &mlx5_auto_fw_update);
904 if (!mlx5_auto_fw_update)
905 return (0);
906 fw = firmware_get("mlx5fw_mfa");
907 if (fw) {
908 err = mlx5_firmware_flash(dev, fw);
909 firmware_put(fw, FIRMWARE_UNLOAD);
910 }
911 else
912 return (-ENOENT);
913
914 return err;
915 }
916
mlx5_pci_init(struct mlx5_core_dev * dev,struct mlx5_priv * priv)917 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
918 {
919 struct pci_dev *pdev = dev->pdev;
920 device_t bsddev;
921 int err;
922
923 pdev = dev->pdev;
924 bsddev = pdev->dev.bsddev;
925 pci_set_drvdata(dev->pdev, dev);
926 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
927 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
928
929 mutex_init(&priv->pgdir_mutex);
930 INIT_LIST_HEAD(&priv->pgdir_list);
931 spin_lock_init(&priv->mkey_lock);
932
933 err = mlx5_pci_enable_device(dev);
934 if (err) {
935 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
936 goto err_dbg;
937 }
938
939 err = request_bar(pdev);
940 if (err) {
941 mlx5_core_err(dev, "error requesting BARs, aborting\n");
942 goto err_disable;
943 }
944
945 pci_set_master(pdev);
946
947 err = set_dma_caps(pdev);
948 if (err) {
949 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
950 goto err_clr_master;
951 }
952
953 dev->iseg_base = pci_resource_start(dev->pdev, 0);
954 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
955 if (!dev->iseg) {
956 err = -ENOMEM;
957 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
958 goto err_clr_master;
959 }
960
961 return 0;
962
963 err_clr_master:
964 release_bar(dev->pdev);
965 err_disable:
966 mlx5_pci_disable_device(dev);
967 err_dbg:
968 return err;
969 }
970
mlx5_pci_close(struct mlx5_core_dev * dev,struct mlx5_priv * priv)971 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
972 {
973 #ifdef PCI_IOV
974 if (MLX5_CAP_GEN(dev, eswitch_flow_table))
975 pci_iov_detach(dev->pdev->dev.bsddev);
976 #endif
977 iounmap(dev->iseg);
978 release_bar(dev->pdev);
979 mlx5_pci_disable_device(dev);
980 }
981
mlx5_init_once(struct mlx5_core_dev * dev,struct mlx5_priv * priv)982 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
983 {
984 int err;
985
986 err = mlx5_vsc_find_cap(dev);
987 if (err)
988 mlx5_core_warn(dev, "Unable to find vendor specific capabilities\n");
989
990 err = mlx5_query_hca_caps(dev);
991 if (err) {
992 mlx5_core_err(dev, "query hca failed\n");
993 goto out;
994 }
995
996 err = mlx5_query_board_id(dev);
997 if (err) {
998 mlx5_core_err(dev, "query board id failed\n");
999 goto out;
1000 }
1001
1002 err = mlx5_eq_init(dev);
1003 if (err) {
1004 mlx5_core_err(dev, "failed to initialize eq\n");
1005 goto out;
1006 }
1007
1008 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
1009
1010 err = mlx5_init_cq_table(dev);
1011 if (err) {
1012 mlx5_core_err(dev, "failed to initialize cq table\n");
1013 goto err_eq_cleanup;
1014 }
1015
1016 mlx5_init_qp_table(dev);
1017 mlx5_init_srq_table(dev);
1018 mlx5_init_mr_table(dev);
1019
1020 mlx5_init_reserved_gids(dev);
1021 mlx5_fpga_init(dev);
1022
1023 #ifdef RATELIMIT
1024 err = mlx5_init_rl_table(dev);
1025 if (err) {
1026 mlx5_core_err(dev, "Failed to init rate limiting\n");
1027 goto err_tables_cleanup;
1028 }
1029 #endif
1030 return 0;
1031
1032 #ifdef RATELIMIT
1033 err_tables_cleanup:
1034 mlx5_cleanup_mr_table(dev);
1035 mlx5_cleanup_srq_table(dev);
1036 mlx5_cleanup_qp_table(dev);
1037 mlx5_cleanup_cq_table(dev);
1038 #endif
1039
1040 err_eq_cleanup:
1041 mlx5_eq_cleanup(dev);
1042
1043 out:
1044 return err;
1045 }
1046
mlx5_cleanup_once(struct mlx5_core_dev * dev)1047 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
1048 {
1049 #ifdef RATELIMIT
1050 mlx5_cleanup_rl_table(dev);
1051 #endif
1052 mlx5_fpga_cleanup(dev);
1053 mlx5_cleanup_reserved_gids(dev);
1054 mlx5_cleanup_mr_table(dev);
1055 mlx5_cleanup_srq_table(dev);
1056 mlx5_cleanup_qp_table(dev);
1057 mlx5_cleanup_cq_table(dev);
1058 mlx5_eq_cleanup(dev);
1059 }
1060
mlx5_load_one(struct mlx5_core_dev * dev,struct mlx5_priv * priv,bool boot)1061 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1062 bool boot)
1063 {
1064 int err;
1065
1066 mutex_lock(&dev->intf_state_mutex);
1067 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1068 mlx5_core_warn(dev, "interface is up, NOP\n");
1069 goto out;
1070 }
1071
1072 mlx5_core_dbg(dev, "firmware version: %d.%d.%d\n",
1073 fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev));
1074
1075 /*
1076 * On load removing any previous indication of internal error,
1077 * device is up
1078 */
1079 dev->state = MLX5_DEVICE_STATE_UP;
1080
1081 /* wait for firmware to accept initialization segments configurations
1082 */
1083 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI,
1084 FW_INIT_WARN_MESSAGE_INTERVAL);
1085 if (err) {
1086 dev_err(&dev->pdev->dev,
1087 "Firmware over %d MS in pre-initializing state, aborting\n",
1088 FW_PRE_INIT_TIMEOUT_MILI);
1089 goto out_err;
1090 }
1091
1092 err = mlx5_cmd_init(dev);
1093 if (err) {
1094 mlx5_core_err(dev,
1095 "Failed initializing command interface, aborting\n");
1096 goto out_err;
1097 }
1098
1099 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0);
1100 if (err) {
1101 mlx5_core_err(dev,
1102 "Firmware over %d MS in initializing state, aborting\n",
1103 FW_INIT_TIMEOUT_MILI);
1104 goto err_cmd_cleanup;
1105 }
1106
1107 err = mlx5_core_enable_hca(dev, 0);
1108 if (err) {
1109 mlx5_core_err(dev, "enable hca failed\n");
1110 goto err_cmd_cleanup;
1111 }
1112
1113 err = mlx5_core_set_issi(dev);
1114 if (err) {
1115 mlx5_core_err(dev, "failed to set issi\n");
1116 goto err_disable_hca;
1117 }
1118
1119 err = mlx5_pagealloc_start(dev);
1120 if (err) {
1121 mlx5_core_err(dev, "mlx5_pagealloc_start failed\n");
1122 goto err_disable_hca;
1123 }
1124
1125 err = mlx5_satisfy_startup_pages(dev, 1);
1126 if (err) {
1127 mlx5_core_err(dev, "failed to allocate boot pages\n");
1128 goto err_pagealloc_stop;
1129 }
1130
1131 err = set_hca_ctrl(dev);
1132 if (err) {
1133 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1134 goto reclaim_boot_pages;
1135 }
1136
1137 err = handle_hca_cap(dev);
1138 if (err) {
1139 mlx5_core_err(dev, "handle_hca_cap failed\n");
1140 goto reclaim_boot_pages;
1141 }
1142
1143 err = handle_hca_cap_atomic(dev);
1144 if (err) {
1145 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
1146 goto reclaim_boot_pages;
1147 }
1148
1149 err = mlx5_satisfy_startup_pages(dev, 0);
1150 if (err) {
1151 mlx5_core_err(dev, "failed to allocate init pages\n");
1152 goto reclaim_boot_pages;
1153 }
1154
1155 err = mlx5_cmd_init_hca(dev);
1156 if (err) {
1157 mlx5_core_err(dev, "init hca failed\n");
1158 goto reclaim_boot_pages;
1159 }
1160
1161 mlx5_set_driver_version(dev);
1162
1163 mlx5_start_health_poll(dev);
1164
1165 if (boot && (err = mlx5_init_once(dev, priv))) {
1166 mlx5_core_err(dev, "sw objs init failed\n");
1167 goto err_stop_poll;
1168 }
1169
1170 dev->priv.uar = mlx5_get_uars_page(dev);
1171 if (IS_ERR(dev->priv.uar)) {
1172 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1173 err = PTR_ERR(dev->priv.uar);
1174 goto err_cleanup_once;
1175 }
1176
1177 err = mlx5_enable_msix(dev);
1178 if (err) {
1179 mlx5_core_err(dev, "enable msix failed\n");
1180 goto err_cleanup_uar;
1181 }
1182
1183 err = mlx5_start_eqs(dev);
1184 if (err) {
1185 mlx5_core_err(dev, "Failed to start pages and async EQs\n");
1186 goto err_disable_msix;
1187 }
1188
1189 err = alloc_comp_eqs(dev);
1190 if (err) {
1191 mlx5_core_err(dev, "Failed to alloc completion EQs\n");
1192 goto err_stop_eqs;
1193 }
1194
1195 err = mlx5_init_fs(dev);
1196 if (err) {
1197 mlx5_core_err(dev, "flow steering init %d\n", err);
1198 goto err_free_comp_eqs;
1199 }
1200
1201 err = mlx5_core_set_hca_defaults(dev);
1202 if (err) {
1203 mlx5_core_err(dev, "Failed to set HCA defaults %d\n", err);
1204 goto err_free_comp_eqs;
1205 }
1206
1207 err = mlx5_mpfs_init(dev);
1208 if (err) {
1209 mlx5_core_err(dev, "mpfs init failed %d\n", err);
1210 goto err_fs;
1211 }
1212
1213 err = mlx5_fpga_device_start(dev);
1214 if (err) {
1215 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1216 goto err_mpfs;
1217 }
1218
1219 err = mlx5_diag_cnt_init(dev);
1220 if (err) {
1221 mlx5_core_err(dev, "diag cnt init failed %d\n", err);
1222 goto err_fpga;
1223 }
1224
1225 err = mlx5_register_device(dev);
1226 if (err) {
1227 mlx5_core_err(dev, "mlx5_register_device failed %d\n", err);
1228 goto err_diag_cnt;
1229 }
1230
1231 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1232
1233 out:
1234 mutex_unlock(&dev->intf_state_mutex);
1235 return 0;
1236
1237 err_diag_cnt:
1238 mlx5_diag_cnt_cleanup(dev);
1239
1240 err_fpga:
1241 mlx5_fpga_device_stop(dev);
1242
1243 err_mpfs:
1244 mlx5_mpfs_destroy(dev);
1245
1246 err_fs:
1247 mlx5_cleanup_fs(dev);
1248
1249 err_free_comp_eqs:
1250 free_comp_eqs(dev);
1251
1252 err_stop_eqs:
1253 mlx5_stop_eqs(dev);
1254
1255 err_disable_msix:
1256 mlx5_disable_msix(dev);
1257
1258 err_cleanup_uar:
1259 mlx5_put_uars_page(dev, dev->priv.uar);
1260
1261 err_cleanup_once:
1262 if (boot)
1263 mlx5_cleanup_once(dev);
1264
1265 err_stop_poll:
1266 mlx5_stop_health_poll(dev, boot);
1267 if (mlx5_cmd_teardown_hca(dev)) {
1268 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1269 goto out_err;
1270 }
1271
1272 reclaim_boot_pages:
1273 mlx5_reclaim_startup_pages(dev);
1274
1275 err_pagealloc_stop:
1276 mlx5_pagealloc_stop(dev);
1277
1278 err_disable_hca:
1279 mlx5_core_disable_hca(dev);
1280
1281 err_cmd_cleanup:
1282 mlx5_cmd_cleanup(dev);
1283
1284 out_err:
1285 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1286 mutex_unlock(&dev->intf_state_mutex);
1287
1288 return err;
1289 }
1290
mlx5_unload_one(struct mlx5_core_dev * dev,struct mlx5_priv * priv,bool cleanup)1291 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1292 bool cleanup)
1293 {
1294 int err = 0;
1295
1296 if (cleanup)
1297 mlx5_drain_health_recovery(dev);
1298
1299 mutex_lock(&dev->intf_state_mutex);
1300 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1301 mlx5_core_warn(dev, "%s: interface is down, NOP\n", __func__);
1302 if (cleanup)
1303 mlx5_cleanup_once(dev);
1304 goto out;
1305 }
1306
1307 mlx5_unregister_device(dev);
1308
1309 mlx5_eswitch_cleanup(dev->priv.eswitch);
1310 mlx5_diag_cnt_cleanup(dev);
1311 mlx5_fpga_device_stop(dev);
1312 mlx5_mpfs_destroy(dev);
1313 mlx5_cleanup_fs(dev);
1314 mlx5_wait_for_reclaim_vfs_pages(dev);
1315 free_comp_eqs(dev);
1316 mlx5_stop_eqs(dev);
1317 mlx5_disable_msix(dev);
1318 mlx5_put_uars_page(dev, dev->priv.uar);
1319 if (cleanup)
1320 mlx5_cleanup_once(dev);
1321 mlx5_stop_health_poll(dev, cleanup);
1322 err = mlx5_cmd_teardown_hca(dev);
1323 if (err) {
1324 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1325 goto out;
1326 }
1327 mlx5_pagealloc_stop(dev);
1328 mlx5_reclaim_startup_pages(dev);
1329 mlx5_core_disable_hca(dev);
1330 mlx5_cmd_cleanup(dev);
1331
1332 out:
1333 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1334 mutex_unlock(&dev->intf_state_mutex);
1335 return err;
1336 }
1337
mlx5_core_event(struct mlx5_core_dev * dev,enum mlx5_dev_event event,unsigned long param)1338 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1339 unsigned long param)
1340 {
1341 struct mlx5_priv *priv = &dev->priv;
1342 struct mlx5_device_context *dev_ctx;
1343 unsigned long flags;
1344
1345 spin_lock_irqsave(&priv->ctx_lock, flags);
1346
1347 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1348 if (dev_ctx->intf->event)
1349 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1350
1351 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1352 }
1353
1354 struct mlx5_core_event_handler {
1355 void (*event)(struct mlx5_core_dev *dev,
1356 enum mlx5_dev_event event,
1357 void *data);
1358 };
1359
1360 #define MLX5_STATS_DESC(a, b, c, d, e, ...) d, e,
1361
1362 #define MLX5_PORT_MODULE_ERROR_STATS(m) \
1363 m(+1, u64, power_budget_exceeded, "power_budget", "Module Power Budget Exceeded") \
1364 m(+1, u64, long_range, "long_range", "Module Long Range for non MLNX cable/module") \
1365 m(+1, u64, bus_stuck, "bus_stuck", "Module Bus stuck(I2C or data shorted)") \
1366 m(+1, u64, no_eeprom, "no_eeprom", "No EEPROM/retry timeout") \
1367 m(+1, u64, enforce_part_number, "enforce_part_number", "Module Enforce part number list") \
1368 m(+1, u64, unknown_id, "unknown_id", "Module Unknown identifier") \
1369 m(+1, u64, high_temp, "high_temp", "Module High Temperature") \
1370 m(+1, u64, cable_shorted, "cable_shorted", "Module Cable is shorted") \
1371 m(+1, u64, pmd_type_not_enabled, "pmd_type_not_enabled", "PMD type is not enabled") \
1372 m(+1, u64, laster_tec_failure, "laster_tec_failure", "Laster TEC failure") \
1373 m(+1, u64, high_current, "high_current", "High current") \
1374 m(+1, u64, high_voltage, "high_voltage", "High voltage") \
1375 m(+1, u64, pcie_sys_power_slot_exceeded, "pcie_sys_power_slot_exceeded", "PCIe system power slot Exceeded") \
1376 m(+1, u64, high_power, "high_power", "High power") \
1377 m(+1, u64, module_state_machine_fault, "module_state_machine_fault", "Module State Machine fault")
1378
1379 static const char *mlx5_pme_err_desc[] = {
1380 MLX5_PORT_MODULE_ERROR_STATS(MLX5_STATS_DESC)
1381 };
1382
init_one(struct pci_dev * pdev,const struct pci_device_id * id)1383 static int init_one(struct pci_dev *pdev,
1384 const struct pci_device_id *id)
1385 {
1386 struct mlx5_core_dev *dev;
1387 struct mlx5_priv *priv;
1388 device_t bsddev = pdev->dev.bsddev;
1389 #ifdef PCI_IOV
1390 nvlist_t *pf_schema, *vf_schema;
1391 int num_vfs, sriov_pos;
1392 #endif
1393 int i,err;
1394 int numa_node;
1395 struct sysctl_oid *pme_sysctl_node;
1396 struct sysctl_oid *pme_err_sysctl_node;
1397 struct sysctl_oid *cap_sysctl_node;
1398 struct sysctl_oid *current_cap_sysctl_node;
1399 struct sysctl_oid *max_cap_sysctl_node;
1400
1401 printk_once("mlx5: %s", mlx5_version);
1402
1403 numa_node = dev_to_node(&pdev->dev);
1404
1405 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, numa_node);
1406
1407 priv = &dev->priv;
1408 priv->numa_node = numa_node;
1409
1410 if (id)
1411 priv->pci_dev_data = id->driver_data;
1412
1413 if (mlx5_prof_sel < 0 || mlx5_prof_sel >= ARRAY_SIZE(profiles)) {
1414 device_printf(bsddev,
1415 "WARN: selected profile out of range, selecting default (%d)\n",
1416 MLX5_DEFAULT_PROF);
1417 mlx5_prof_sel = MLX5_DEFAULT_PROF;
1418 }
1419 dev->profile = &profiles[mlx5_prof_sel];
1420 dev->pdev = pdev;
1421 dev->event = mlx5_core_event;
1422
1423 /* Set desc */
1424 device_set_desc(bsddev, mlx5_version);
1425
1426 sysctl_ctx_init(&dev->sysctl_ctx);
1427 SYSCTL_ADD_INT(&dev->sysctl_ctx,
1428 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1429 OID_AUTO, "msix_eqvec", CTLFLAG_RDTUN, &dev->msix_eqvec, 0,
1430 "Maximum number of MSIX event queue vectors, if set");
1431 SYSCTL_ADD_INT(&dev->sysctl_ctx,
1432 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1433 OID_AUTO, "power_status", CTLFLAG_RD, &dev->pwr_status, 0,
1434 "0:Invalid 1:Sufficient 2:Insufficient");
1435 SYSCTL_ADD_INT(&dev->sysctl_ctx,
1436 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1437 OID_AUTO, "power_value", CTLFLAG_RD, &dev->pwr_value, 0,
1438 "Current power value in Watts");
1439
1440 pme_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx,
1441 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1442 OID_AUTO, "pme_stats", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
1443 "Port module event statistics");
1444 if (pme_sysctl_node == NULL) {
1445 err = -ENOMEM;
1446 goto clean_sysctl_ctx;
1447 }
1448 pme_err_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx,
1449 SYSCTL_CHILDREN(pme_sysctl_node),
1450 OID_AUTO, "errors", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
1451 "Port module event error statistics");
1452 if (pme_err_sysctl_node == NULL) {
1453 err = -ENOMEM;
1454 goto clean_sysctl_ctx;
1455 }
1456 SYSCTL_ADD_U64(&dev->sysctl_ctx,
1457 SYSCTL_CHILDREN(pme_sysctl_node), OID_AUTO,
1458 "module_plug", CTLFLAG_RD | CTLFLAG_MPSAFE,
1459 &dev->priv.pme_stats.status_counters[MLX5_MODULE_STATUS_PLUGGED_ENABLED],
1460 0, "Number of time module plugged");
1461 SYSCTL_ADD_U64(&dev->sysctl_ctx,
1462 SYSCTL_CHILDREN(pme_sysctl_node), OID_AUTO,
1463 "module_unplug", CTLFLAG_RD | CTLFLAG_MPSAFE,
1464 &dev->priv.pme_stats.status_counters[MLX5_MODULE_STATUS_UNPLUGGED],
1465 0, "Number of time module unplugged");
1466 for (i = 0 ; i < MLX5_MODULE_EVENT_ERROR_NUM; i++) {
1467 SYSCTL_ADD_U64(&dev->sysctl_ctx,
1468 SYSCTL_CHILDREN(pme_err_sysctl_node), OID_AUTO,
1469 mlx5_pme_err_desc[2 * i], CTLFLAG_RD | CTLFLAG_MPSAFE,
1470 &dev->priv.pme_stats.error_counters[i],
1471 0, mlx5_pme_err_desc[2 * i + 1]);
1472 }
1473
1474 cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx,
1475 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1476 OID_AUTO, "caps", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
1477 "hardware capabilities raw bitstrings");
1478 if (cap_sysctl_node == NULL) {
1479 err = -ENOMEM;
1480 goto clean_sysctl_ctx;
1481 }
1482 current_cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx,
1483 SYSCTL_CHILDREN(cap_sysctl_node),
1484 OID_AUTO, "current", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
1485 "");
1486 if (current_cap_sysctl_node == NULL) {
1487 err = -ENOMEM;
1488 goto clean_sysctl_ctx;
1489 }
1490 max_cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx,
1491 SYSCTL_CHILDREN(cap_sysctl_node),
1492 OID_AUTO, "max", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
1493 "");
1494 if (max_cap_sysctl_node == NULL) {
1495 err = -ENOMEM;
1496 goto clean_sysctl_ctx;
1497 }
1498 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1499 SYSCTL_CHILDREN(current_cap_sysctl_node),
1500 OID_AUTO, "general", CTLFLAG_RD | CTLFLAG_MPSAFE,
1501 &dev->hca_caps_cur[MLX5_CAP_GENERAL],
1502 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1503 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1504 SYSCTL_CHILDREN(max_cap_sysctl_node),
1505 OID_AUTO, "general", CTLFLAG_RD | CTLFLAG_MPSAFE,
1506 &dev->hca_caps_max[MLX5_CAP_GENERAL],
1507 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1508 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1509 SYSCTL_CHILDREN(current_cap_sysctl_node),
1510 OID_AUTO, "ether", CTLFLAG_RD | CTLFLAG_MPSAFE,
1511 &dev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS],
1512 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1513 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1514 SYSCTL_CHILDREN(max_cap_sysctl_node),
1515 OID_AUTO, "ether", CTLFLAG_RD | CTLFLAG_MPSAFE,
1516 &dev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS],
1517 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1518 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1519 SYSCTL_CHILDREN(current_cap_sysctl_node),
1520 OID_AUTO, "odp", CTLFLAG_RD | CTLFLAG_MPSAFE,
1521 &dev->hca_caps_cur[MLX5_CAP_ODP],
1522 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1523 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1524 SYSCTL_CHILDREN(max_cap_sysctl_node),
1525 OID_AUTO, "odp", CTLFLAG_RD | CTLFLAG_MPSAFE,
1526 &dev->hca_caps_max[MLX5_CAP_ODP],
1527 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1528 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1529 SYSCTL_CHILDREN(current_cap_sysctl_node),
1530 OID_AUTO, "atomic", CTLFLAG_RD | CTLFLAG_MPSAFE,
1531 &dev->hca_caps_cur[MLX5_CAP_ATOMIC],
1532 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1533 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1534 SYSCTL_CHILDREN(max_cap_sysctl_node),
1535 OID_AUTO, "atomic", CTLFLAG_RD | CTLFLAG_MPSAFE,
1536 &dev->hca_caps_max[MLX5_CAP_ATOMIC],
1537 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1538 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1539 SYSCTL_CHILDREN(current_cap_sysctl_node),
1540 OID_AUTO, "roce", CTLFLAG_RD | CTLFLAG_MPSAFE,
1541 &dev->hca_caps_cur[MLX5_CAP_ROCE],
1542 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1543 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1544 SYSCTL_CHILDREN(max_cap_sysctl_node),
1545 OID_AUTO, "roce", CTLFLAG_RD | CTLFLAG_MPSAFE,
1546 &dev->hca_caps_max[MLX5_CAP_ROCE],
1547 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1548 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1549 SYSCTL_CHILDREN(current_cap_sysctl_node),
1550 OID_AUTO, "ipoib", CTLFLAG_RD | CTLFLAG_MPSAFE,
1551 &dev->hca_caps_cur[MLX5_CAP_IPOIB_OFFLOADS],
1552 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1553 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1554 SYSCTL_CHILDREN(max_cap_sysctl_node),
1555 OID_AUTO, "ipoib", CTLFLAG_RD | CTLFLAG_MPSAFE,
1556 &dev->hca_caps_max[MLX5_CAP_IPOIB_OFFLOADS],
1557 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1558 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1559 SYSCTL_CHILDREN(current_cap_sysctl_node),
1560 OID_AUTO, "eoib", CTLFLAG_RD | CTLFLAG_MPSAFE,
1561 &dev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS],
1562 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1563 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1564 SYSCTL_CHILDREN(max_cap_sysctl_node),
1565 OID_AUTO, "eoib", CTLFLAG_RD | CTLFLAG_MPSAFE,
1566 &dev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS],
1567 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1568 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1569 SYSCTL_CHILDREN(current_cap_sysctl_node),
1570 OID_AUTO, "flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE,
1571 &dev->hca_caps_cur[MLX5_CAP_FLOW_TABLE],
1572 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1573 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1574 SYSCTL_CHILDREN(max_cap_sysctl_node),
1575 OID_AUTO, "flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE,
1576 &dev->hca_caps_max[MLX5_CAP_FLOW_TABLE],
1577 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1578 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1579 SYSCTL_CHILDREN(current_cap_sysctl_node),
1580 OID_AUTO, "eswitch_flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE,
1581 &dev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE],
1582 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1583 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1584 SYSCTL_CHILDREN(max_cap_sysctl_node),
1585 OID_AUTO, "eswitch_flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE,
1586 &dev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE],
1587 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1588 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1589 SYSCTL_CHILDREN(current_cap_sysctl_node),
1590 OID_AUTO, "eswitch", CTLFLAG_RD | CTLFLAG_MPSAFE,
1591 &dev->hca_caps_cur[MLX5_CAP_ESWITCH],
1592 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1593 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1594 SYSCTL_CHILDREN(max_cap_sysctl_node),
1595 OID_AUTO, "eswitch", CTLFLAG_RD | CTLFLAG_MPSAFE,
1596 &dev->hca_caps_max[MLX5_CAP_ESWITCH],
1597 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1598 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1599 SYSCTL_CHILDREN(current_cap_sysctl_node),
1600 OID_AUTO, "snapshot", CTLFLAG_RD | CTLFLAG_MPSAFE,
1601 &dev->hca_caps_cur[MLX5_CAP_SNAPSHOT],
1602 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1603 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1604 SYSCTL_CHILDREN(max_cap_sysctl_node),
1605 OID_AUTO, "snapshot", CTLFLAG_RD | CTLFLAG_MPSAFE,
1606 &dev->hca_caps_max[MLX5_CAP_SNAPSHOT],
1607 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1608 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1609 SYSCTL_CHILDREN(current_cap_sysctl_node),
1610 OID_AUTO, "vector_calc", CTLFLAG_RD | CTLFLAG_MPSAFE,
1611 &dev->hca_caps_cur[MLX5_CAP_VECTOR_CALC],
1612 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1613 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1614 SYSCTL_CHILDREN(max_cap_sysctl_node),
1615 OID_AUTO, "vector_calc", CTLFLAG_RD | CTLFLAG_MPSAFE,
1616 &dev->hca_caps_max[MLX5_CAP_VECTOR_CALC],
1617 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1618 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1619 SYSCTL_CHILDREN(current_cap_sysctl_node),
1620 OID_AUTO, "qos", CTLFLAG_RD | CTLFLAG_MPSAFE,
1621 &dev->hca_caps_cur[MLX5_CAP_QOS],
1622 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1623 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1624 SYSCTL_CHILDREN(max_cap_sysctl_node),
1625 OID_AUTO, "qos", CTLFLAG_RD | CTLFLAG_MPSAFE,
1626 &dev->hca_caps_max[MLX5_CAP_QOS],
1627 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1628 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1629 SYSCTL_CHILDREN(current_cap_sysctl_node),
1630 OID_AUTO, "debug", CTLFLAG_RD | CTLFLAG_MPSAFE,
1631 &dev->hca_caps_cur[MLX5_CAP_DEBUG],
1632 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1633 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1634 SYSCTL_CHILDREN(max_cap_sysctl_node),
1635 OID_AUTO, "debug", CTLFLAG_RD | CTLFLAG_MPSAFE,
1636 &dev->hca_caps_max[MLX5_CAP_DEBUG],
1637 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1638 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1639 SYSCTL_CHILDREN(cap_sysctl_node),
1640 OID_AUTO, "pcam", CTLFLAG_RD | CTLFLAG_MPSAFE,
1641 &dev->caps.pcam, sizeof(dev->caps.pcam), "IU", "");
1642 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1643 SYSCTL_CHILDREN(cap_sysctl_node),
1644 OID_AUTO, "mcam", CTLFLAG_RD | CTLFLAG_MPSAFE,
1645 &dev->caps.mcam, sizeof(dev->caps.mcam), "IU", "");
1646 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1647 SYSCTL_CHILDREN(cap_sysctl_node),
1648 OID_AUTO, "qcam", CTLFLAG_RD | CTLFLAG_MPSAFE,
1649 &dev->caps.qcam, sizeof(dev->caps.qcam), "IU", "");
1650 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1651 SYSCTL_CHILDREN(cap_sysctl_node),
1652 OID_AUTO, "fpga", CTLFLAG_RD | CTLFLAG_MPSAFE,
1653 &dev->caps.fpga, sizeof(dev->caps.fpga), "IU", "");
1654
1655 INIT_LIST_HEAD(&priv->ctx_list);
1656 spin_lock_init(&priv->ctx_lock);
1657 mutex_init(&dev->pci_status_mutex);
1658 mutex_init(&dev->intf_state_mutex);
1659
1660 mutex_init(&priv->bfregs.reg_head.lock);
1661 mutex_init(&priv->bfregs.wc_head.lock);
1662 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1663 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1664
1665 mtx_init(&dev->dump_lock, "mlx5dmp", NULL, MTX_DEF | MTX_NEW);
1666 err = mlx5_pci_init(dev, priv);
1667 if (err) {
1668 mlx5_core_err(dev, "mlx5_pci_init failed %d\n", err);
1669 goto clean_dev;
1670 }
1671
1672 err = mlx5_health_init(dev);
1673 if (err) {
1674 mlx5_core_err(dev, "mlx5_health_init failed %d\n", err);
1675 goto close_pci;
1676 }
1677
1678 mlx5_pagealloc_init(dev);
1679
1680 err = mlx5_load_one(dev, priv, true);
1681 if (err) {
1682 mlx5_core_err(dev, "mlx5_load_one failed %d\n", err);
1683 goto clean_health;
1684 }
1685
1686 mlx5_fwdump_prep(dev);
1687
1688 mlx5_firmware_update(dev);
1689
1690 #ifdef PCI_IOV
1691 if (MLX5_CAP_GEN(dev, vport_group_manager)) {
1692 if (pci_find_extcap(bsddev, PCIZ_SRIOV, &sriov_pos) == 0) {
1693 num_vfs = pci_read_config(bsddev, sriov_pos +
1694 PCIR_SRIOV_TOTAL_VFS, 2);
1695 } else {
1696 mlx5_core_info(dev, "cannot find SR-IOV PCIe cap\n");
1697 num_vfs = 0;
1698 }
1699 err = mlx5_eswitch_init(dev, 1 + num_vfs);
1700 if (err == 0) {
1701 pf_schema = pci_iov_schema_alloc_node();
1702 vf_schema = pci_iov_schema_alloc_node();
1703 pci_iov_schema_add_unicast_mac(vf_schema,
1704 iov_mac_addr_name, 0, NULL);
1705 pci_iov_schema_add_vlan(vf_schema,
1706 iov_vlan_name, 0, 0);
1707 pci_iov_schema_add_uint64(vf_schema, iov_node_guid_name,
1708 0, 0);
1709 pci_iov_schema_add_uint64(vf_schema, iov_port_guid_name,
1710 0, 0);
1711 err = pci_iov_attach(bsddev, pf_schema, vf_schema);
1712 if (err == 0) {
1713 dev->iov_pf = true;
1714 } else {
1715 device_printf(bsddev,
1716 "Failed to initialize SR-IOV support, error %d\n",
1717 err);
1718 }
1719 } else {
1720 mlx5_core_err(dev, "eswitch init failed, error %d\n",
1721 err);
1722 }
1723 }
1724 #endif
1725
1726 pci_save_state(pdev);
1727 return 0;
1728
1729 clean_health:
1730 mlx5_pagealloc_cleanup(dev);
1731 mlx5_health_cleanup(dev);
1732 close_pci:
1733 mlx5_pci_close(dev, priv);
1734 clean_dev:
1735 mtx_destroy(&dev->dump_lock);
1736 clean_sysctl_ctx:
1737 sysctl_ctx_free(&dev->sysctl_ctx);
1738 kfree(dev);
1739 return err;
1740 }
1741
remove_one(struct pci_dev * pdev)1742 static void remove_one(struct pci_dev *pdev)
1743 {
1744 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1745 struct mlx5_priv *priv = &dev->priv;
1746
1747 #ifdef PCI_IOV
1748 if (dev->iov_pf) {
1749 pci_iov_detach(pdev->dev.bsddev);
1750 mlx5_eswitch_disable_sriov(priv->eswitch);
1751 dev->iov_pf = false;
1752 }
1753 #endif
1754
1755 if (mlx5_unload_one(dev, priv, true)) {
1756 mlx5_core_err(dev, "mlx5_unload_one() failed, leaked %lld bytes\n",
1757 (long long)(dev->priv.fw_pages * MLX5_ADAPTER_PAGE_SIZE));
1758 }
1759
1760 mlx5_pagealloc_cleanup(dev);
1761 mlx5_health_cleanup(dev);
1762 mlx5_fwdump_clean(dev);
1763 mlx5_pci_close(dev, priv);
1764 mtx_destroy(&dev->dump_lock);
1765 pci_set_drvdata(pdev, NULL);
1766 sysctl_ctx_free(&dev->sysctl_ctx);
1767 kfree(dev);
1768 }
1769
mlx5_pci_err_detected(struct pci_dev * pdev,pci_channel_state_t state)1770 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1771 pci_channel_state_t state)
1772 {
1773 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1774 struct mlx5_priv *priv = &dev->priv;
1775
1776 mlx5_core_info(dev, "%s was called\n", __func__);
1777 mlx5_enter_error_state(dev, false);
1778 mlx5_unload_one(dev, priv, false);
1779
1780 if (state) {
1781 mlx5_drain_health_wq(dev);
1782 mlx5_pci_disable_device(dev);
1783 }
1784
1785 return state == pci_channel_io_perm_failure ?
1786 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1787 }
1788
mlx5_pci_slot_reset(struct pci_dev * pdev)1789 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1790 {
1791 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1792 int err = 0;
1793
1794 mlx5_core_info(dev,"%s was called\n", __func__);
1795
1796 err = mlx5_pci_enable_device(dev);
1797 if (err) {
1798 mlx5_core_err(dev, "mlx5_pci_enable_device failed with error code: %d\n"
1799 ,err);
1800 return PCI_ERS_RESULT_DISCONNECT;
1801 }
1802 pci_set_master(pdev);
1803 pci_set_powerstate(pdev->dev.bsddev, PCI_POWERSTATE_D0);
1804 pci_restore_state(pdev);
1805 pci_save_state(pdev);
1806
1807 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1808 }
1809
1810 /* wait for the device to show vital signs. For now we check
1811 * that we can read the device ID and that the health buffer
1812 * shows a non zero value which is different than 0xffffffff
1813 */
wait_vital(struct pci_dev * pdev)1814 static void wait_vital(struct pci_dev *pdev)
1815 {
1816 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1817 struct mlx5_core_health *health = &dev->priv.health;
1818 const int niter = 100;
1819 u32 count;
1820 u16 did;
1821 int i;
1822
1823 /* Wait for firmware to be ready after reset */
1824 msleep(1000);
1825 for (i = 0; i < niter; i++) {
1826 if (pci_read_config_word(pdev, 2, &did)) {
1827 mlx5_core_warn(dev, "failed reading config word\n");
1828 break;
1829 }
1830 if (did == pdev->device) {
1831 mlx5_core_info(dev,
1832 "device ID correctly read after %d iterations\n", i);
1833 break;
1834 }
1835 msleep(50);
1836 }
1837 if (i == niter)
1838 mlx5_core_warn(dev, "could not read device ID\n");
1839
1840 for (i = 0; i < niter; i++) {
1841 count = ioread32be(health->health_counter);
1842 if (count && count != 0xffffffff) {
1843 mlx5_core_info(dev,
1844 "Counter value 0x%x after %d iterations\n", count, i);
1845 break;
1846 }
1847 msleep(50);
1848 }
1849
1850 if (i == niter)
1851 mlx5_core_warn(dev, "could not read device ID\n");
1852 }
1853
mlx5_pci_resume(struct pci_dev * pdev)1854 static void mlx5_pci_resume(struct pci_dev *pdev)
1855 {
1856 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1857 struct mlx5_priv *priv = &dev->priv;
1858 int err;
1859
1860 mlx5_core_info(dev,"%s was called\n", __func__);
1861
1862 wait_vital(pdev);
1863
1864 err = mlx5_load_one(dev, priv, false);
1865 if (err)
1866 mlx5_core_err(dev,
1867 "mlx5_load_one failed with error code: %d\n" ,err);
1868 else
1869 mlx5_core_info(dev,"device recovered\n");
1870 }
1871
1872 static const struct pci_error_handlers mlx5_err_handler = {
1873 .error_detected = mlx5_pci_err_detected,
1874 .slot_reset = mlx5_pci_slot_reset,
1875 .resume = mlx5_pci_resume
1876 };
1877
1878 #ifdef PCI_IOV
1879 static int
mlx5_iov_init(device_t dev,uint16_t num_vfs,const nvlist_t * pf_config)1880 mlx5_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *pf_config)
1881 {
1882 struct pci_dev *pdev;
1883 struct mlx5_core_dev *core_dev;
1884 struct mlx5_priv *priv;
1885 int err;
1886
1887 pdev = device_get_softc(dev);
1888 core_dev = pci_get_drvdata(pdev);
1889 priv = &core_dev->priv;
1890
1891 if (priv->eswitch == NULL)
1892 return (ENXIO);
1893 if (priv->eswitch->total_vports < num_vfs + 1)
1894 num_vfs = priv->eswitch->total_vports - 1;
1895 err = mlx5_eswitch_enable_sriov(priv->eswitch, num_vfs);
1896 return (-err);
1897 }
1898
1899 static void
mlx5_iov_uninit(device_t dev)1900 mlx5_iov_uninit(device_t dev)
1901 {
1902 struct pci_dev *pdev;
1903 struct mlx5_core_dev *core_dev;
1904 struct mlx5_priv *priv;
1905
1906 pdev = device_get_softc(dev);
1907 core_dev = pci_get_drvdata(pdev);
1908 priv = &core_dev->priv;
1909
1910 mlx5_eswitch_disable_sriov(priv->eswitch);
1911 }
1912
1913 static int
mlx5_iov_add_vf(device_t dev,uint16_t vfnum,const nvlist_t * vf_config)1914 mlx5_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *vf_config)
1915 {
1916 struct pci_dev *pdev;
1917 struct mlx5_core_dev *core_dev;
1918 struct mlx5_priv *priv;
1919 const void *mac;
1920 size_t mac_size;
1921 uint64_t node_guid, port_guid;
1922 int error;
1923
1924 pdev = device_get_softc(dev);
1925 core_dev = pci_get_drvdata(pdev);
1926 priv = &core_dev->priv;
1927
1928 if (vfnum + 1 >= priv->eswitch->total_vports)
1929 return (ENXIO);
1930
1931 if (nvlist_exists_binary(vf_config, iov_mac_addr_name)) {
1932 mac = nvlist_get_binary(vf_config, iov_mac_addr_name,
1933 &mac_size);
1934 error = -mlx5_eswitch_set_vport_mac(priv->eswitch,
1935 vfnum + 1, __DECONST(u8 *, mac));
1936 if (error != 0) {
1937 mlx5_core_err(core_dev,
1938 "setting MAC for VF %d failed, error %d\n",
1939 vfnum + 1, error);
1940 }
1941 }
1942
1943 if (nvlist_exists_number(vf_config, iov_vlan_name)) {
1944 uint16_t vlan = nvlist_get_number(vf_config, iov_vlan_name);
1945
1946 if (vlan == 0)
1947 error = ENOTSUP;
1948 else {
1949 if (vlan == VF_VLAN_TRUNK)
1950 vlan = 0;
1951
1952 error = -mlx5_eswitch_set_vport_vlan(priv->eswitch,
1953 vfnum + 1, vlan, 0);
1954 }
1955 if (error != 0) {
1956 mlx5_core_err(core_dev,
1957 "setting VLAN for VF %d failed, error %d\n",
1958 vfnum + 1, error);
1959 }
1960 }
1961
1962 if (nvlist_exists_number(vf_config, iov_node_guid_name)) {
1963 node_guid = nvlist_get_number(vf_config, iov_node_guid_name);
1964 error = -mlx5_modify_nic_vport_node_guid(core_dev, vfnum + 1,
1965 node_guid);
1966 if (error != 0) {
1967 mlx5_core_err(core_dev,
1968 "modifying node GUID for VF %d failed, error %d\n",
1969 vfnum + 1, error);
1970 }
1971 }
1972
1973 if (nvlist_exists_number(vf_config, iov_port_guid_name)) {
1974 port_guid = nvlist_get_number(vf_config, iov_port_guid_name);
1975 error = -mlx5_modify_nic_vport_port_guid(core_dev, vfnum + 1,
1976 port_guid);
1977 if (error != 0) {
1978 mlx5_core_err(core_dev,
1979 "modifying port GUID for VF %d failed, error %d\n",
1980 vfnum + 1, error);
1981 }
1982 }
1983
1984 error = -mlx5_eswitch_set_vport_state(priv->eswitch, vfnum + 1,
1985 VPORT_STATE_FOLLOW);
1986 if (error != 0) {
1987 mlx5_core_err(core_dev,
1988 "upping vport for VF %d failed, error %d\n",
1989 vfnum + 1, error);
1990 }
1991 error = -mlx5_core_enable_hca(core_dev, vfnum + 1);
1992 if (error != 0) {
1993 mlx5_core_err(core_dev, "enabling VF %d failed, error %d\n",
1994 vfnum + 1, error);
1995 }
1996 return (error);
1997 }
1998 #endif
1999
mlx5_try_fast_unload(struct mlx5_core_dev * dev)2000 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
2001 {
2002 bool fast_teardown, force_teardown;
2003 int err;
2004
2005 if (!mlx5_fast_unload_enabled) {
2006 mlx5_core_dbg(dev, "fast unload is disabled by user\n");
2007 return -EOPNOTSUPP;
2008 }
2009
2010 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
2011 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
2012
2013 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
2014 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
2015
2016 if (!fast_teardown && !force_teardown)
2017 return -EOPNOTSUPP;
2018
2019 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
2020 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
2021 return -EAGAIN;
2022 }
2023
2024 /* Panic tear down fw command will stop the PCI bus communication
2025 * with the HCA, so the health polll is no longer needed.
2026 */
2027 mlx5_drain_health_wq(dev);
2028 mlx5_stop_health_poll(dev, false);
2029
2030 err = mlx5_cmd_fast_teardown_hca(dev);
2031 if (!err)
2032 goto done;
2033
2034 err = mlx5_cmd_force_teardown_hca(dev);
2035 if (!err)
2036 goto done;
2037
2038 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", err);
2039 mlx5_start_health_poll(dev);
2040 return err;
2041 done:
2042 mlx5_enter_error_state(dev, true);
2043 return 0;
2044 }
2045
mlx5_shutdown_disable_interrupts(struct mlx5_core_dev * mdev)2046 static void mlx5_shutdown_disable_interrupts(struct mlx5_core_dev *mdev)
2047 {
2048 int nvec = mdev->priv.eq_table.num_comp_vectors + MLX5_EQ_VEC_COMP_BASE;
2049 int x;
2050
2051 mdev->priv.disable_irqs = 1;
2052
2053 /* wait for all IRQ handlers to finish processing */
2054 for (x = 0; x != nvec; x++)
2055 synchronize_irq(mdev->priv.msix_arr[x].vector);
2056 }
2057
shutdown_one(struct pci_dev * pdev)2058 static void shutdown_one(struct pci_dev *pdev)
2059 {
2060 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2061 struct mlx5_priv *priv = &dev->priv;
2062 int err;
2063
2064 /* enter polling mode */
2065 mlx5_cmd_use_polling(dev);
2066
2067 set_bit(MLX5_INTERFACE_STATE_TEARDOWN, &dev->intf_state);
2068
2069 /* disable all interrupts */
2070 mlx5_shutdown_disable_interrupts(dev);
2071
2072 err = mlx5_try_fast_unload(dev);
2073 if (err)
2074 mlx5_unload_one(dev, priv, false);
2075 mlx5_pci_disable_device(dev);
2076 }
2077
2078 static const struct pci_device_id mlx5_core_pci_table[] = {
2079 { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */
2080 { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */
2081 { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */
2082 { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */
2083 { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */
2084 { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */
2085 { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5, PCIe 3.0 */
2086 { PCI_VDEVICE(MELLANOX, 4120) }, /* ConnectX-5 VF */
2087 { PCI_VDEVICE(MELLANOX, 4121) }, /* ConnectX-5 Ex */
2088 { PCI_VDEVICE(MELLANOX, 4122) }, /* ConnectX-5 Ex VF */
2089 { PCI_VDEVICE(MELLANOX, 4123) }, /* ConnectX-6 */
2090 { PCI_VDEVICE(MELLANOX, 4124) }, /* ConnectX-6 VF */
2091 { PCI_VDEVICE(MELLANOX, 4125) }, /* ConnectX-6 Dx */
2092 { PCI_VDEVICE(MELLANOX, 4126) }, /* ConnectX Family mlx5Gen Virtual Function */
2093 { PCI_VDEVICE(MELLANOX, 4127) }, /* ConnectX-6 LX */
2094 { PCI_VDEVICE(MELLANOX, 4128) },
2095 { PCI_VDEVICE(MELLANOX, 4129) }, /* ConnectX-7 */
2096 { PCI_VDEVICE(MELLANOX, 4130) },
2097 { PCI_VDEVICE(MELLANOX, 4131) }, /* ConnectX-8 */
2098 { PCI_VDEVICE(MELLANOX, 4132) },
2099 { PCI_VDEVICE(MELLANOX, 4133) },
2100 { PCI_VDEVICE(MELLANOX, 4134) },
2101 { PCI_VDEVICE(MELLANOX, 4135) },
2102 { PCI_VDEVICE(MELLANOX, 4136) },
2103 { PCI_VDEVICE(MELLANOX, 4137) },
2104 { PCI_VDEVICE(MELLANOX, 4138) },
2105 { PCI_VDEVICE(MELLANOX, 4139) },
2106 { PCI_VDEVICE(MELLANOX, 4140) },
2107 { PCI_VDEVICE(MELLANOX, 4141) },
2108 { PCI_VDEVICE(MELLANOX, 4142) },
2109 { PCI_VDEVICE(MELLANOX, 4143) },
2110 { PCI_VDEVICE(MELLANOX, 4144) },
2111 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
2112 { PCI_VDEVICE(MELLANOX, 0xa2d3) }, /* BlueField integrated ConnectX-5 network controller VF */
2113 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
2114 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
2115 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */
2116 { }
2117 };
2118
2119 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
2120
mlx5_disable_device(struct mlx5_core_dev * dev)2121 void mlx5_disable_device(struct mlx5_core_dev *dev)
2122 {
2123 mlx5_pci_err_detected(dev->pdev, 0);
2124 }
2125
mlx5_recover_device(struct mlx5_core_dev * dev)2126 void mlx5_recover_device(struct mlx5_core_dev *dev)
2127 {
2128 mlx5_pci_disable_device(dev);
2129 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
2130 mlx5_pci_resume(dev->pdev);
2131 }
2132
2133 struct pci_driver mlx5_core_driver = {
2134 .name = DRIVER_NAME,
2135 .id_table = mlx5_core_pci_table,
2136 .shutdown = shutdown_one,
2137 .probe = init_one,
2138 .remove = remove_one,
2139 .err_handler = &mlx5_err_handler,
2140 #ifdef PCI_IOV
2141 .bsd_iov_init = mlx5_iov_init,
2142 .bsd_iov_uninit = mlx5_iov_uninit,
2143 .bsd_iov_add_vf = mlx5_iov_add_vf,
2144 #endif
2145 };
2146
init(void)2147 static int __init init(void)
2148 {
2149 int err;
2150
2151 err = pci_register_driver(&mlx5_core_driver);
2152 if (err)
2153 goto err_debug;
2154
2155 err = mlx5_ctl_init();
2156 if (err)
2157 goto err_ctl;
2158
2159 return 0;
2160
2161 err_ctl:
2162 pci_unregister_driver(&mlx5_core_driver);
2163
2164 err_debug:
2165 return err;
2166 }
2167
cleanup(void)2168 static void __exit cleanup(void)
2169 {
2170 mlx5_ctl_fini();
2171 pci_unregister_driver(&mlx5_core_driver);
2172 }
2173
2174 module_init_order(init, SI_ORDER_FIRST);
2175 module_exit_order(cleanup, SI_ORDER_FIRST);
2176