1 /*-
2 * Copyright (C) 2013 Emulex
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Emulex Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
39 /* $FreeBSD$ */
40
41 #include "opt_inet6.h"
42 #include "opt_inet.h"
43
44 #include "oce_if.h"
45
46 /* UE Status Low CSR */
47 static char *ue_status_low_desc[] = {
48 "CEV",
49 "CTX",
50 "DBUF",
51 "ERX",
52 "Host",
53 "MPU",
54 "NDMA",
55 "PTC ",
56 "RDMA ",
57 "RXF ",
58 "RXIPS ",
59 "RXULP0 ",
60 "RXULP1 ",
61 "RXULP2 ",
62 "TIM ",
63 "TPOST ",
64 "TPRE ",
65 "TXIPS ",
66 "TXULP0 ",
67 "TXULP1 ",
68 "UC ",
69 "WDMA ",
70 "TXULP2 ",
71 "HOST1 ",
72 "P0_OB_LINK ",
73 "P1_OB_LINK ",
74 "HOST_GPIO ",
75 "MBOX ",
76 "AXGMAC0",
77 "AXGMAC1",
78 "JTAG",
79 "MPU_INTPEND"
80 };
81
82 /* UE Status High CSR */
83 static char *ue_status_hi_desc[] = {
84 "LPCMEMHOST",
85 "MGMT_MAC",
86 "PCS0ONLINE",
87 "MPU_IRAM",
88 "PCS1ONLINE",
89 "PCTL0",
90 "PCTL1",
91 "PMEM",
92 "RR",
93 "TXPB",
94 "RXPP",
95 "XAUI",
96 "TXP",
97 "ARM",
98 "IPC",
99 "HOST2",
100 "HOST3",
101 "HOST4",
102 "HOST5",
103 "HOST6",
104 "HOST7",
105 "HOST8",
106 "HOST9",
107 "NETC",
108 "Unknown",
109 "Unknown",
110 "Unknown",
111 "Unknown",
112 "Unknown",
113 "Unknown",
114 "Unknown",
115 "Unknown"
116 };
117
118
119 /* Driver entry points prototypes */
120 static int oce_probe(device_t dev);
121 static int oce_attach(device_t dev);
122 static int oce_detach(device_t dev);
123 static int oce_shutdown(device_t dev);
124 static int oce_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
125 static void oce_init(void *xsc);
126 static int oce_multiq_start(struct ifnet *ifp, struct mbuf *m);
127 static void oce_multiq_flush(struct ifnet *ifp);
128
129 /* Driver interrupt routines protypes */
130 static void oce_intr(void *arg, int pending);
131 static int oce_setup_intr(POCE_SOFTC sc);
132 static int oce_fast_isr(void *arg);
133 static int oce_alloc_intr(POCE_SOFTC sc, int vector,
134 void (*isr) (void *arg, int pending));
135
136 /* Media callbacks prototypes */
137 static void oce_media_status(struct ifnet *ifp, struct ifmediareq *req);
138 static int oce_media_change(struct ifnet *ifp);
139
140 /* Transmit routines prototypes */
141 static int oce_tx(POCE_SOFTC sc, struct mbuf **mpp, int wq_index);
142 static void oce_tx_restart(POCE_SOFTC sc, struct oce_wq *wq);
143 static void oce_tx_complete(struct oce_wq *wq, uint32_t wqe_idx,
144 uint32_t status);
145 static int oce_multiq_transmit(struct ifnet *ifp, struct mbuf *m,
146 struct oce_wq *wq);
147
148 /* Receive routines prototypes */
149 static void oce_discard_rx_comp(struct oce_rq *rq, struct oce_nic_rx_cqe *cqe);
150 static int oce_cqe_vtp_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe);
151 static int oce_cqe_portid_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe);
152 static void oce_rx(struct oce_rq *rq, uint32_t rqe_idx,
153 struct oce_nic_rx_cqe *cqe);
154
155 /* Helper function prototypes in this file */
156 static int oce_attach_ifp(POCE_SOFTC sc);
157 static void oce_add_vlan(void *arg, struct ifnet *ifp, uint16_t vtag);
158 static void oce_del_vlan(void *arg, struct ifnet *ifp, uint16_t vtag);
159 static int oce_vid_config(POCE_SOFTC sc);
160 static void oce_mac_addr_set(POCE_SOFTC sc);
161 static int oce_handle_passthrough(struct ifnet *ifp, caddr_t data);
162 static void oce_local_timer(void *arg);
163 static void oce_if_deactivate(POCE_SOFTC sc);
164 static void oce_if_activate(POCE_SOFTC sc);
165 static void setup_max_queues_want(POCE_SOFTC sc);
166 static void update_queues_got(POCE_SOFTC sc);
167 static void process_link_state(POCE_SOFTC sc,
168 struct oce_async_cqe_link_state *acqe);
169 static int oce_tx_asic_stall_verify(POCE_SOFTC sc, struct mbuf *m);
170 static void oce_get_config(POCE_SOFTC sc);
171 static struct mbuf *oce_insert_vlan_tag(POCE_SOFTC sc, struct mbuf *m, boolean_t *complete);
172
173 /* IP specific */
174 #if defined(INET6) || defined(INET)
175 static int oce_init_lro(POCE_SOFTC sc);
176 static void oce_rx_flush_lro(struct oce_rq *rq);
177 static struct mbuf * oce_tso_setup(POCE_SOFTC sc, struct mbuf **mpp);
178 #endif
179
180 static device_method_t oce_dispatch[] = {
181 DEVMETHOD(device_probe, oce_probe),
182 DEVMETHOD(device_attach, oce_attach),
183 DEVMETHOD(device_detach, oce_detach),
184 DEVMETHOD(device_shutdown, oce_shutdown),
185
186 DEVMETHOD_END
187 };
188
189 static driver_t oce_driver = {
190 "oce",
191 oce_dispatch,
192 sizeof(OCE_SOFTC)
193 };
194 static devclass_t oce_devclass;
195
196
197 DRIVER_MODULE(oce, pci, oce_driver, oce_devclass, 0, 0);
198 MODULE_DEPEND(oce, pci, 1, 1, 1);
199 MODULE_DEPEND(oce, ether, 1, 1, 1);
200 MODULE_VERSION(oce, 1);
201
202
203 /* global vars */
204 const char component_revision[32] = {"///" COMPONENT_REVISION "///"};
205
206 /* Module capabilites and parameters */
207 uint32_t oce_max_rsp_handled = OCE_MAX_RSP_HANDLED;
208 uint32_t oce_enable_rss = OCE_MODCAP_RSS;
209
210
211 TUNABLE_INT("hw.oce.max_rsp_handled", &oce_max_rsp_handled);
212 TUNABLE_INT("hw.oce.enable_rss", &oce_enable_rss);
213
214
215 /* Supported devices table */
216 static uint32_t supportedDevices[] = {
217 (PCI_VENDOR_SERVERENGINES << 16) | PCI_PRODUCT_BE2,
218 (PCI_VENDOR_SERVERENGINES << 16) | PCI_PRODUCT_BE3,
219 (PCI_VENDOR_EMULEX << 16) | PCI_PRODUCT_BE3,
220 (PCI_VENDOR_EMULEX << 16) | PCI_PRODUCT_XE201,
221 (PCI_VENDOR_EMULEX << 16) | PCI_PRODUCT_XE201_VF,
222 (PCI_VENDOR_EMULEX << 16) | PCI_PRODUCT_SH
223 };
224
225
226
227
228 /*****************************************************************************
229 * Driver entry points functions *
230 *****************************************************************************/
231
232 static int
oce_probe(device_t dev)233 oce_probe(device_t dev)
234 {
235 uint16_t vendor = 0;
236 uint16_t device = 0;
237 int i = 0;
238 char str[256] = {0};
239 POCE_SOFTC sc;
240
241 sc = device_get_softc(dev);
242 bzero(sc, sizeof(OCE_SOFTC));
243 sc->dev = dev;
244
245 vendor = pci_get_vendor(dev);
246 device = pci_get_device(dev);
247
248 for (i = 0; i < (sizeof(supportedDevices) / sizeof(uint32_t)); i++) {
249 if (vendor == ((supportedDevices[i] >> 16) & 0xffff)) {
250 if (device == (supportedDevices[i] & 0xffff)) {
251 sprintf(str, "%s:%s", "Emulex CNA NIC function",
252 component_revision);
253 device_set_desc_copy(dev, str);
254
255 switch (device) {
256 case PCI_PRODUCT_BE2:
257 sc->flags |= OCE_FLAGS_BE2;
258 break;
259 case PCI_PRODUCT_BE3:
260 sc->flags |= OCE_FLAGS_BE3;
261 break;
262 case PCI_PRODUCT_XE201:
263 case PCI_PRODUCT_XE201_VF:
264 sc->flags |= OCE_FLAGS_XE201;
265 break;
266 case PCI_PRODUCT_SH:
267 sc->flags |= OCE_FLAGS_SH;
268 break;
269 default:
270 return ENXIO;
271 }
272 return BUS_PROBE_DEFAULT;
273 }
274 }
275 }
276
277 return ENXIO;
278 }
279
280
281 static int
oce_attach(device_t dev)282 oce_attach(device_t dev)
283 {
284 POCE_SOFTC sc;
285 int rc = 0;
286
287 sc = device_get_softc(dev);
288
289 rc = oce_hw_pci_alloc(sc);
290 if (rc)
291 return rc;
292
293 sc->tx_ring_size = OCE_TX_RING_SIZE;
294 sc->rx_ring_size = OCE_RX_RING_SIZE;
295 sc->rq_frag_size = OCE_RQ_BUF_SIZE;
296 sc->flow_control = OCE_DEFAULT_FLOW_CONTROL;
297 sc->promisc = OCE_DEFAULT_PROMISCUOUS;
298
299 LOCK_CREATE(&sc->bmbx_lock, "Mailbox_lock");
300 LOCK_CREATE(&sc->dev_lock, "Device_lock");
301
302 /* initialise the hardware */
303 rc = oce_hw_init(sc);
304 if (rc)
305 goto pci_res_free;
306
307 oce_get_config(sc);
308
309 setup_max_queues_want(sc);
310
311 rc = oce_setup_intr(sc);
312 if (rc)
313 goto mbox_free;
314
315 rc = oce_queue_init_all(sc);
316 if (rc)
317 goto intr_free;
318
319 rc = oce_attach_ifp(sc);
320 if (rc)
321 goto queues_free;
322
323 #if defined(INET6) || defined(INET)
324 rc = oce_init_lro(sc);
325 if (rc)
326 goto ifp_free;
327 #endif
328
329 rc = oce_hw_start(sc);
330 if (rc)
331 goto lro_free;
332
333 sc->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
334 oce_add_vlan, sc, EVENTHANDLER_PRI_FIRST);
335 sc->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
336 oce_del_vlan, sc, EVENTHANDLER_PRI_FIRST);
337
338 rc = oce_stats_init(sc);
339 if (rc)
340 goto vlan_free;
341
342 oce_add_sysctls(sc);
343
344 callout_init(&sc->timer, CALLOUT_MPSAFE);
345 rc = callout_reset(&sc->timer, 2 * hz, oce_local_timer, sc);
346 if (rc)
347 goto stats_free;
348
349 return 0;
350
351 stats_free:
352 callout_drain(&sc->timer);
353 oce_stats_free(sc);
354 vlan_free:
355 if (sc->vlan_attach)
356 EVENTHANDLER_DEREGISTER(vlan_config, sc->vlan_attach);
357 if (sc->vlan_detach)
358 EVENTHANDLER_DEREGISTER(vlan_unconfig, sc->vlan_detach);
359 oce_hw_intr_disable(sc);
360 lro_free:
361 #if defined(INET6) || defined(INET)
362 oce_free_lro(sc);
363 ifp_free:
364 #endif
365 ether_ifdetach(sc->ifp);
366 if_free(sc->ifp);
367 queues_free:
368 oce_queue_release_all(sc);
369 intr_free:
370 oce_intr_free(sc);
371 mbox_free:
372 oce_dma_free(sc, &sc->bsmbx);
373 pci_res_free:
374 oce_hw_pci_free(sc);
375 LOCK_DESTROY(&sc->dev_lock);
376 LOCK_DESTROY(&sc->bmbx_lock);
377 return rc;
378
379 }
380
381
382 static int
oce_detach(device_t dev)383 oce_detach(device_t dev)
384 {
385 POCE_SOFTC sc = device_get_softc(dev);
386
387 LOCK(&sc->dev_lock);
388 oce_if_deactivate(sc);
389 UNLOCK(&sc->dev_lock);
390
391 callout_drain(&sc->timer);
392
393 if (sc->vlan_attach != NULL)
394 EVENTHANDLER_DEREGISTER(vlan_config, sc->vlan_attach);
395 if (sc->vlan_detach != NULL)
396 EVENTHANDLER_DEREGISTER(vlan_unconfig, sc->vlan_detach);
397
398 ether_ifdetach(sc->ifp);
399
400 if_free(sc->ifp);
401
402 oce_hw_shutdown(sc);
403
404 bus_generic_detach(dev);
405
406 return 0;
407 }
408
409
410 static int
oce_shutdown(device_t dev)411 oce_shutdown(device_t dev)
412 {
413 int rc;
414
415 rc = oce_detach(dev);
416
417 return rc;
418 }
419
420
421 static int
oce_ioctl(struct ifnet * ifp,u_long command,caddr_t data)422 oce_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
423 {
424 struct ifreq *ifr = (struct ifreq *)data;
425 POCE_SOFTC sc = ifp->if_softc;
426 int rc = 0;
427 uint32_t u;
428
429 switch (command) {
430
431 case SIOCGIFMEDIA:
432 rc = ifmedia_ioctl(ifp, ifr, &sc->media, command);
433 break;
434
435 case SIOCSIFMTU:
436 if (ifr->ifr_mtu > OCE_MAX_MTU)
437 rc = EINVAL;
438 else
439 ifp->if_mtu = ifr->ifr_mtu;
440 break;
441
442 case SIOCSIFFLAGS:
443 if (ifp->if_flags & IFF_UP) {
444 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
445 sc->ifp->if_drv_flags |= IFF_DRV_RUNNING;
446 oce_init(sc);
447 }
448 device_printf(sc->dev, "Interface Up\n");
449 } else {
450 LOCK(&sc->dev_lock);
451
452 sc->ifp->if_drv_flags &=
453 ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
454 oce_if_deactivate(sc);
455
456 UNLOCK(&sc->dev_lock);
457
458 device_printf(sc->dev, "Interface Down\n");
459 }
460
461 if ((ifp->if_flags & IFF_PROMISC) && !sc->promisc) {
462 if (!oce_rxf_set_promiscuous(sc, (1 | (1 << 1))))
463 sc->promisc = TRUE;
464 } else if (!(ifp->if_flags & IFF_PROMISC) && sc->promisc) {
465 if (!oce_rxf_set_promiscuous(sc, 0))
466 sc->promisc = FALSE;
467 }
468
469 break;
470
471 case SIOCADDMULTI:
472 case SIOCDELMULTI:
473 rc = oce_hw_update_multicast(sc);
474 if (rc)
475 device_printf(sc->dev,
476 "Update multicast address failed\n");
477 break;
478
479 case SIOCSIFCAP:
480 u = ifr->ifr_reqcap ^ ifp->if_capenable;
481
482 if (u & IFCAP_TXCSUM) {
483 ifp->if_capenable ^= IFCAP_TXCSUM;
484 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
485
486 if (IFCAP_TSO & ifp->if_capenable &&
487 !(IFCAP_TXCSUM & ifp->if_capenable)) {
488 ifp->if_capenable &= ~IFCAP_TSO;
489 ifp->if_hwassist &= ~CSUM_TSO;
490 if_printf(ifp,
491 "TSO disabled due to -txcsum.\n");
492 }
493 }
494
495 if (u & IFCAP_RXCSUM)
496 ifp->if_capenable ^= IFCAP_RXCSUM;
497
498 if (u & IFCAP_TSO4) {
499 ifp->if_capenable ^= IFCAP_TSO4;
500
501 if (IFCAP_TSO & ifp->if_capenable) {
502 if (IFCAP_TXCSUM & ifp->if_capenable)
503 ifp->if_hwassist |= CSUM_TSO;
504 else {
505 ifp->if_capenable &= ~IFCAP_TSO;
506 ifp->if_hwassist &= ~CSUM_TSO;
507 if_printf(ifp,
508 "Enable txcsum first.\n");
509 rc = EAGAIN;
510 }
511 } else
512 ifp->if_hwassist &= ~CSUM_TSO;
513 }
514
515 if (u & IFCAP_VLAN_HWTAGGING)
516 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
517
518 if (u & IFCAP_VLAN_HWFILTER) {
519 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
520 oce_vid_config(sc);
521 }
522 #if defined(INET6) || defined(INET)
523 if (u & IFCAP_LRO)
524 ifp->if_capenable ^= IFCAP_LRO;
525 #endif
526
527 break;
528
529 case SIOCGPRIVATE_0:
530 rc = oce_handle_passthrough(ifp, data);
531 break;
532 default:
533 rc = ether_ioctl(ifp, command, data);
534 break;
535 }
536
537 return rc;
538 }
539
540
541 static void
oce_init(void * arg)542 oce_init(void *arg)
543 {
544 POCE_SOFTC sc = arg;
545
546 LOCK(&sc->dev_lock);
547
548 if (sc->ifp->if_flags & IFF_UP) {
549 oce_if_deactivate(sc);
550 oce_if_activate(sc);
551 }
552
553 UNLOCK(&sc->dev_lock);
554
555 }
556
557
558 static int
oce_multiq_start(struct ifnet * ifp,struct mbuf * m)559 oce_multiq_start(struct ifnet *ifp, struct mbuf *m)
560 {
561 POCE_SOFTC sc = ifp->if_softc;
562 struct oce_wq *wq = NULL;
563 int queue_index = 0;
564 int status = 0;
565
566 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
567 queue_index = m->m_pkthdr.flowid % sc->nwqs;
568
569 wq = sc->wq[queue_index];
570
571 LOCK(&wq->tx_lock);
572 status = oce_multiq_transmit(ifp, m, wq);
573 UNLOCK(&wq->tx_lock);
574
575 return status;
576
577 }
578
579
580 static void
oce_multiq_flush(struct ifnet * ifp)581 oce_multiq_flush(struct ifnet *ifp)
582 {
583 POCE_SOFTC sc = ifp->if_softc;
584 struct mbuf *m;
585 int i = 0;
586
587 for (i = 0; i < sc->nwqs; i++) {
588 while ((m = buf_ring_dequeue_sc(sc->wq[i]->br)) != NULL)
589 m_freem(m);
590 }
591 if_qflush(ifp);
592 }
593
594
595
596 /*****************************************************************************
597 * Driver interrupt routines functions *
598 *****************************************************************************/
599
600 static void
oce_intr(void * arg,int pending)601 oce_intr(void *arg, int pending)
602 {
603
604 POCE_INTR_INFO ii = (POCE_INTR_INFO) arg;
605 POCE_SOFTC sc = ii->sc;
606 struct oce_eq *eq = ii->eq;
607 struct oce_eqe *eqe;
608 struct oce_cq *cq = NULL;
609 int i, num_eqes = 0;
610
611
612 bus_dmamap_sync(eq->ring->dma.tag, eq->ring->dma.map,
613 BUS_DMASYNC_POSTWRITE);
614 do {
615 eqe = RING_GET_CONSUMER_ITEM_VA(eq->ring, struct oce_eqe);
616 if (eqe->evnt == 0)
617 break;
618 eqe->evnt = 0;
619 bus_dmamap_sync(eq->ring->dma.tag, eq->ring->dma.map,
620 BUS_DMASYNC_POSTWRITE);
621 RING_GET(eq->ring, 1);
622 num_eqes++;
623
624 } while (TRUE);
625
626 if (!num_eqes)
627 goto eq_arm; /* Spurious */
628
629 /* Clear EQ entries, but dont arm */
630 oce_arm_eq(sc, eq->eq_id, num_eqes, FALSE, FALSE);
631
632 /* Process TX, RX and MCC. But dont arm CQ*/
633 for (i = 0; i < eq->cq_valid; i++) {
634 cq = eq->cq[i];
635 (*cq->cq_handler)(cq->cb_arg);
636 }
637
638 /* Arm all cqs connected to this EQ */
639 for (i = 0; i < eq->cq_valid; i++) {
640 cq = eq->cq[i];
641 oce_arm_cq(sc, cq->cq_id, 0, TRUE);
642 }
643
644 eq_arm:
645 oce_arm_eq(sc, eq->eq_id, 0, TRUE, FALSE);
646
647 return;
648 }
649
650
651 static int
oce_setup_intr(POCE_SOFTC sc)652 oce_setup_intr(POCE_SOFTC sc)
653 {
654 int rc = 0, use_intx = 0;
655 int vector = 0, req_vectors = 0;
656
657 if (is_rss_enabled(sc))
658 req_vectors = MAX((sc->nrqs - 1), sc->nwqs);
659 else
660 req_vectors = 1;
661
662 if (sc->flags & OCE_FLAGS_MSIX_CAPABLE) {
663 sc->intr_count = req_vectors;
664 rc = pci_alloc_msix(sc->dev, &sc->intr_count);
665 if (rc != 0) {
666 use_intx = 1;
667 pci_release_msi(sc->dev);
668 } else
669 sc->flags |= OCE_FLAGS_USING_MSIX;
670 } else
671 use_intx = 1;
672
673 if (use_intx)
674 sc->intr_count = 1;
675
676 /* Scale number of queues based on intr we got */
677 update_queues_got(sc);
678
679 if (use_intx) {
680 device_printf(sc->dev, "Using legacy interrupt\n");
681 rc = oce_alloc_intr(sc, vector, oce_intr);
682 if (rc)
683 goto error;
684 } else {
685 for (; vector < sc->intr_count; vector++) {
686 rc = oce_alloc_intr(sc, vector, oce_intr);
687 if (rc)
688 goto error;
689 }
690 }
691
692 return 0;
693 error:
694 oce_intr_free(sc);
695 return rc;
696 }
697
698
699 static int
oce_fast_isr(void * arg)700 oce_fast_isr(void *arg)
701 {
702 POCE_INTR_INFO ii = (POCE_INTR_INFO) arg;
703 POCE_SOFTC sc = ii->sc;
704
705 if (ii->eq == NULL)
706 return FILTER_STRAY;
707
708 oce_arm_eq(sc, ii->eq->eq_id, 0, FALSE, TRUE);
709
710 taskqueue_enqueue_fast(ii->tq, &ii->task);
711
712 ii->eq->intr++;
713
714 return FILTER_HANDLED;
715 }
716
717
718 static int
oce_alloc_intr(POCE_SOFTC sc,int vector,void (* isr)(void * arg,int pending))719 oce_alloc_intr(POCE_SOFTC sc, int vector, void (*isr) (void *arg, int pending))
720 {
721 POCE_INTR_INFO ii = &sc->intrs[vector];
722 int rc = 0, rr;
723
724 if (vector >= OCE_MAX_EQ)
725 return (EINVAL);
726
727 /* Set the resource id for the interrupt.
728 * MSIx is vector + 1 for the resource id,
729 * INTx is 0 for the resource id.
730 */
731 if (sc->flags & OCE_FLAGS_USING_MSIX)
732 rr = vector + 1;
733 else
734 rr = 0;
735 ii->intr_res = bus_alloc_resource_any(sc->dev,
736 SYS_RES_IRQ,
737 &rr, RF_ACTIVE|RF_SHAREABLE);
738 ii->irq_rr = rr;
739 if (ii->intr_res == NULL) {
740 device_printf(sc->dev,
741 "Could not allocate interrupt\n");
742 rc = ENXIO;
743 return rc;
744 }
745
746 TASK_INIT(&ii->task, 0, isr, ii);
747 ii->vector = vector;
748 sprintf(ii->task_name, "oce_task[%d]", ii->vector);
749 ii->tq = taskqueue_create_fast(ii->task_name,
750 M_NOWAIT,
751 taskqueue_thread_enqueue,
752 &ii->tq);
753 taskqueue_start_threads(&ii->tq, 1, PI_NET, "%s taskq",
754 device_get_nameunit(sc->dev));
755
756 ii->sc = sc;
757 rc = bus_setup_intr(sc->dev,
758 ii->intr_res,
759 INTR_TYPE_NET,
760 oce_fast_isr, NULL, ii, &ii->tag);
761 return rc;
762
763 }
764
765
766 void
oce_intr_free(POCE_SOFTC sc)767 oce_intr_free(POCE_SOFTC sc)
768 {
769 int i = 0;
770
771 for (i = 0; i < sc->intr_count; i++) {
772
773 if (sc->intrs[i].tag != NULL)
774 bus_teardown_intr(sc->dev, sc->intrs[i].intr_res,
775 sc->intrs[i].tag);
776 if (sc->intrs[i].tq != NULL)
777 taskqueue_free(sc->intrs[i].tq);
778
779 if (sc->intrs[i].intr_res != NULL)
780 bus_release_resource(sc->dev, SYS_RES_IRQ,
781 sc->intrs[i].irq_rr,
782 sc->intrs[i].intr_res);
783 sc->intrs[i].tag = NULL;
784 sc->intrs[i].intr_res = NULL;
785 }
786
787 if (sc->flags & OCE_FLAGS_USING_MSIX)
788 pci_release_msi(sc->dev);
789
790 }
791
792
793
794 /******************************************************************************
795 * Media callbacks functions *
796 ******************************************************************************/
797
798 static void
oce_media_status(struct ifnet * ifp,struct ifmediareq * req)799 oce_media_status(struct ifnet *ifp, struct ifmediareq *req)
800 {
801 POCE_SOFTC sc = (POCE_SOFTC) ifp->if_softc;
802
803
804 req->ifm_status = IFM_AVALID;
805 req->ifm_active = IFM_ETHER;
806
807 if (sc->link_status == 1)
808 req->ifm_status |= IFM_ACTIVE;
809 else
810 return;
811
812 switch (sc->link_speed) {
813 case 1: /* 10 Mbps */
814 req->ifm_active |= IFM_10_T | IFM_FDX;
815 sc->speed = 10;
816 break;
817 case 2: /* 100 Mbps */
818 req->ifm_active |= IFM_100_TX | IFM_FDX;
819 sc->speed = 100;
820 break;
821 case 3: /* 1 Gbps */
822 req->ifm_active |= IFM_1000_T | IFM_FDX;
823 sc->speed = 1000;
824 break;
825 case 4: /* 10 Gbps */
826 req->ifm_active |= IFM_10G_SR | IFM_FDX;
827 sc->speed = 10000;
828 break;
829 case 5: /* 20 Gbps */
830 req->ifm_active |= IFM_10G_SR | IFM_FDX;
831 sc->speed = 20000;
832 break;
833 case 6: /* 25 Gbps */
834 req->ifm_active |= IFM_10G_SR | IFM_FDX;
835 sc->speed = 25000;
836 break;
837 case 7: /* 40 Gbps */
838 req->ifm_active |= IFM_40G_SR4 | IFM_FDX;
839 sc->speed = 40000;
840 break;
841 default:
842 sc->speed = 0;
843 break;
844 }
845
846 return;
847 }
848
849
850 int
oce_media_change(struct ifnet * ifp)851 oce_media_change(struct ifnet *ifp)
852 {
853 return 0;
854 }
855
856
857
858
859 /*****************************************************************************
860 * Transmit routines functions *
861 *****************************************************************************/
862
863 static int
oce_tx(POCE_SOFTC sc,struct mbuf ** mpp,int wq_index)864 oce_tx(POCE_SOFTC sc, struct mbuf **mpp, int wq_index)
865 {
866 int rc = 0, i, retry_cnt = 0;
867 bus_dma_segment_t segs[OCE_MAX_TX_ELEMENTS];
868 struct mbuf *m, *m_temp;
869 struct oce_wq *wq = sc->wq[wq_index];
870 struct oce_packet_desc *pd;
871 struct oce_nic_hdr_wqe *nichdr;
872 struct oce_nic_frag_wqe *nicfrag;
873 int num_wqes;
874 uint32_t reg_value;
875 boolean_t complete = TRUE;
876
877 m = *mpp;
878 if (!m)
879 return EINVAL;
880
881 if (!(m->m_flags & M_PKTHDR)) {
882 rc = ENXIO;
883 goto free_ret;
884 }
885
886 if(oce_tx_asic_stall_verify(sc, m)) {
887 m = oce_insert_vlan_tag(sc, m, &complete);
888 if(!m) {
889 device_printf(sc->dev, "Insertion unsuccessful\n");
890 return 0;
891 }
892
893 }
894
895 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
896 /* consolidate packet buffers for TSO/LSO segment offload */
897 #if defined(INET6) || defined(INET)
898 m = oce_tso_setup(sc, mpp);
899 #else
900 m = NULL;
901 #endif
902 if (m == NULL) {
903 rc = ENXIO;
904 goto free_ret;
905 }
906 }
907
908 pd = &wq->pckts[wq->pkt_desc_head];
909 retry:
910 rc = bus_dmamap_load_mbuf_sg(wq->tag,
911 pd->map,
912 m, segs, &pd->nsegs, BUS_DMA_NOWAIT);
913 if (rc == 0) {
914 num_wqes = pd->nsegs + 1;
915 if (IS_BE(sc) || IS_SH(sc)) {
916 /*Dummy required only for BE3.*/
917 if (num_wqes & 1)
918 num_wqes++;
919 }
920 if (num_wqes >= RING_NUM_FREE(wq->ring)) {
921 bus_dmamap_unload(wq->tag, pd->map);
922 return EBUSY;
923 }
924 atomic_store_rel_int(&wq->pkt_desc_head,
925 (wq->pkt_desc_head + 1) % \
926 OCE_WQ_PACKET_ARRAY_SIZE);
927 bus_dmamap_sync(wq->tag, pd->map, BUS_DMASYNC_PREWRITE);
928 pd->mbuf = m;
929
930 nichdr =
931 RING_GET_PRODUCER_ITEM_VA(wq->ring, struct oce_nic_hdr_wqe);
932 nichdr->u0.dw[0] = 0;
933 nichdr->u0.dw[1] = 0;
934 nichdr->u0.dw[2] = 0;
935 nichdr->u0.dw[3] = 0;
936
937 nichdr->u0.s.complete = complete;
938 nichdr->u0.s.event = 1;
939 nichdr->u0.s.crc = 1;
940 nichdr->u0.s.forward = 0;
941 nichdr->u0.s.ipcs = (m->m_pkthdr.csum_flags & CSUM_IP) ? 1 : 0;
942 nichdr->u0.s.udpcs =
943 (m->m_pkthdr.csum_flags & CSUM_UDP) ? 1 : 0;
944 nichdr->u0.s.tcpcs =
945 (m->m_pkthdr.csum_flags & CSUM_TCP) ? 1 : 0;
946 nichdr->u0.s.num_wqe = num_wqes;
947 nichdr->u0.s.total_length = m->m_pkthdr.len;
948
949 if (m->m_flags & M_VLANTAG) {
950 nichdr->u0.s.vlan = 1; /*Vlan present*/
951 nichdr->u0.s.vlan_tag = m->m_pkthdr.ether_vtag;
952 }
953
954 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
955 if (m->m_pkthdr.tso_segsz) {
956 nichdr->u0.s.lso = 1;
957 nichdr->u0.s.lso_mss = m->m_pkthdr.tso_segsz;
958 }
959 if (!IS_BE(sc) || !IS_SH(sc))
960 nichdr->u0.s.ipcs = 1;
961 }
962
963 RING_PUT(wq->ring, 1);
964 atomic_add_int(&wq->ring->num_used, 1);
965
966 for (i = 0; i < pd->nsegs; i++) {
967 nicfrag =
968 RING_GET_PRODUCER_ITEM_VA(wq->ring,
969 struct oce_nic_frag_wqe);
970 nicfrag->u0.s.rsvd0 = 0;
971 nicfrag->u0.s.frag_pa_hi = ADDR_HI(segs[i].ds_addr);
972 nicfrag->u0.s.frag_pa_lo = ADDR_LO(segs[i].ds_addr);
973 nicfrag->u0.s.frag_len = segs[i].ds_len;
974 pd->wqe_idx = wq->ring->pidx;
975 RING_PUT(wq->ring, 1);
976 atomic_add_int(&wq->ring->num_used, 1);
977 }
978 if (num_wqes > (pd->nsegs + 1)) {
979 nicfrag =
980 RING_GET_PRODUCER_ITEM_VA(wq->ring,
981 struct oce_nic_frag_wqe);
982 nicfrag->u0.dw[0] = 0;
983 nicfrag->u0.dw[1] = 0;
984 nicfrag->u0.dw[2] = 0;
985 nicfrag->u0.dw[3] = 0;
986 pd->wqe_idx = wq->ring->pidx;
987 RING_PUT(wq->ring, 1);
988 atomic_add_int(&wq->ring->num_used, 1);
989 pd->nsegs++;
990 }
991
992 sc->ifp->if_opackets++;
993 wq->tx_stats.tx_reqs++;
994 wq->tx_stats.tx_wrbs += num_wqes;
995 wq->tx_stats.tx_bytes += m->m_pkthdr.len;
996 wq->tx_stats.tx_pkts++;
997
998 bus_dmamap_sync(wq->ring->dma.tag, wq->ring->dma.map,
999 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1000 reg_value = (num_wqes << 16) | wq->wq_id;
1001 OCE_WRITE_REG32(sc, db, wq->db_offset, reg_value);
1002
1003 } else if (rc == EFBIG) {
1004 if (retry_cnt == 0) {
1005 m_temp = m_defrag(m, M_NOWAIT);
1006 if (m_temp == NULL)
1007 goto free_ret;
1008 m = m_temp;
1009 *mpp = m_temp;
1010 retry_cnt = retry_cnt + 1;
1011 goto retry;
1012 } else
1013 goto free_ret;
1014 } else if (rc == ENOMEM)
1015 return rc;
1016 else
1017 goto free_ret;
1018
1019 return 0;
1020
1021 free_ret:
1022 m_freem(*mpp);
1023 *mpp = NULL;
1024 return rc;
1025 }
1026
1027
1028 static void
oce_tx_complete(struct oce_wq * wq,uint32_t wqe_idx,uint32_t status)1029 oce_tx_complete(struct oce_wq *wq, uint32_t wqe_idx, uint32_t status)
1030 {
1031 struct oce_packet_desc *pd;
1032 POCE_SOFTC sc = (POCE_SOFTC) wq->parent;
1033 struct mbuf *m;
1034
1035 pd = &wq->pckts[wq->pkt_desc_tail];
1036 atomic_store_rel_int(&wq->pkt_desc_tail,
1037 (wq->pkt_desc_tail + 1) % OCE_WQ_PACKET_ARRAY_SIZE);
1038 atomic_subtract_int(&wq->ring->num_used, pd->nsegs + 1);
1039 bus_dmamap_sync(wq->tag, pd->map, BUS_DMASYNC_POSTWRITE);
1040 bus_dmamap_unload(wq->tag, pd->map);
1041
1042 m = pd->mbuf;
1043 m_freem(m);
1044 pd->mbuf = NULL;
1045
1046
1047 if (sc->ifp->if_drv_flags & IFF_DRV_OACTIVE) {
1048 if (wq->ring->num_used < (wq->ring->num_items / 2)) {
1049 sc->ifp->if_drv_flags &= ~(IFF_DRV_OACTIVE);
1050 oce_tx_restart(sc, wq);
1051 }
1052 }
1053 }
1054
1055
1056 static void
oce_tx_restart(POCE_SOFTC sc,struct oce_wq * wq)1057 oce_tx_restart(POCE_SOFTC sc, struct oce_wq *wq)
1058 {
1059
1060 if ((sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != IFF_DRV_RUNNING)
1061 return;
1062
1063 #if __FreeBSD_version >= 800000
1064 if (!drbr_empty(sc->ifp, wq->br))
1065 #else
1066 if (!IFQ_DRV_IS_EMPTY(&sc->ifp->if_snd))
1067 #endif
1068 taskqueue_enqueue_fast(taskqueue_swi, &wq->txtask);
1069
1070 }
1071
1072
1073 #if defined(INET6) || defined(INET)
1074 static struct mbuf *
oce_tso_setup(POCE_SOFTC sc,struct mbuf ** mpp)1075 oce_tso_setup(POCE_SOFTC sc, struct mbuf **mpp)
1076 {
1077 struct mbuf *m;
1078 #ifdef INET
1079 struct ip *ip;
1080 #endif
1081 #ifdef INET6
1082 struct ip6_hdr *ip6;
1083 #endif
1084 struct ether_vlan_header *eh;
1085 struct tcphdr *th;
1086 uint16_t etype;
1087 int total_len = 0, ehdrlen = 0;
1088
1089 m = *mpp;
1090
1091 if (M_WRITABLE(m) == 0) {
1092 m = m_dup(*mpp, M_NOWAIT);
1093 if (!m)
1094 return NULL;
1095 m_freem(*mpp);
1096 *mpp = m;
1097 }
1098
1099 eh = mtod(m, struct ether_vlan_header *);
1100 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
1101 etype = ntohs(eh->evl_proto);
1102 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
1103 } else {
1104 etype = ntohs(eh->evl_encap_proto);
1105 ehdrlen = ETHER_HDR_LEN;
1106 }
1107
1108 switch (etype) {
1109 #ifdef INET
1110 case ETHERTYPE_IP:
1111 ip = (struct ip *)(m->m_data + ehdrlen);
1112 if (ip->ip_p != IPPROTO_TCP)
1113 return NULL;
1114 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
1115
1116 total_len = ehdrlen + (ip->ip_hl << 2) + (th->th_off << 2);
1117 break;
1118 #endif
1119 #ifdef INET6
1120 case ETHERTYPE_IPV6:
1121 ip6 = (struct ip6_hdr *)(m->m_data + ehdrlen);
1122 if (ip6->ip6_nxt != IPPROTO_TCP)
1123 return NULL;
1124 th = (struct tcphdr *)((caddr_t)ip6 + sizeof(struct ip6_hdr));
1125
1126 total_len = ehdrlen + sizeof(struct ip6_hdr) + (th->th_off << 2);
1127 break;
1128 #endif
1129 default:
1130 return NULL;
1131 }
1132
1133 m = m_pullup(m, total_len);
1134 if (!m)
1135 return NULL;
1136 *mpp = m;
1137 return m;
1138
1139 }
1140 #endif /* INET6 || INET */
1141
1142 void
oce_tx_task(void * arg,int npending)1143 oce_tx_task(void *arg, int npending)
1144 {
1145 struct oce_wq *wq = arg;
1146 POCE_SOFTC sc = wq->parent;
1147 struct ifnet *ifp = sc->ifp;
1148 int rc = 0;
1149
1150 #if __FreeBSD_version >= 800000
1151 LOCK(&wq->tx_lock);
1152 rc = oce_multiq_transmit(ifp, NULL, wq);
1153 if (rc) {
1154 device_printf(sc->dev,
1155 "TX[%d] restart failed\n", wq->queue_index);
1156 }
1157 UNLOCK(&wq->tx_lock);
1158 #else
1159 oce_start(ifp);
1160 #endif
1161
1162 }
1163
1164
1165 void
oce_start(struct ifnet * ifp)1166 oce_start(struct ifnet *ifp)
1167 {
1168 POCE_SOFTC sc = ifp->if_softc;
1169 struct mbuf *m;
1170 int rc = 0;
1171 int def_q = 0; /* Defualt tx queue is 0*/
1172
1173 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1174 IFF_DRV_RUNNING)
1175 return;
1176
1177 if (!sc->link_status)
1178 return;
1179
1180 do {
1181 IF_DEQUEUE(&sc->ifp->if_snd, m);
1182 if (m == NULL)
1183 break;
1184
1185 LOCK(&sc->wq[def_q]->tx_lock);
1186 rc = oce_tx(sc, &m, def_q);
1187 UNLOCK(&sc->wq[def_q]->tx_lock);
1188 if (rc) {
1189 if (m != NULL) {
1190 sc->wq[def_q]->tx_stats.tx_stops ++;
1191 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1192 IFQ_DRV_PREPEND(&ifp->if_snd, m);
1193 m = NULL;
1194 }
1195 break;
1196 }
1197 if (m != NULL)
1198 ETHER_BPF_MTAP(ifp, m);
1199
1200 } while (TRUE);
1201
1202 return;
1203 }
1204
1205
1206 /* Handle the Completion Queue for transmit */
1207 uint16_t
oce_wq_handler(void * arg)1208 oce_wq_handler(void *arg)
1209 {
1210 struct oce_wq *wq = (struct oce_wq *)arg;
1211 POCE_SOFTC sc = wq->parent;
1212 struct oce_cq *cq = wq->cq;
1213 struct oce_nic_tx_cqe *cqe;
1214 int num_cqes = 0;
1215
1216 bus_dmamap_sync(cq->ring->dma.tag,
1217 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
1218 cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_tx_cqe);
1219 while (cqe->u0.dw[3]) {
1220 DW_SWAP((uint32_t *) cqe, sizeof(oce_wq_cqe));
1221
1222 wq->ring->cidx = cqe->u0.s.wqe_index + 1;
1223 if (wq->ring->cidx >= wq->ring->num_items)
1224 wq->ring->cidx -= wq->ring->num_items;
1225
1226 oce_tx_complete(wq, cqe->u0.s.wqe_index, cqe->u0.s.status);
1227 wq->tx_stats.tx_compl++;
1228 cqe->u0.dw[3] = 0;
1229 RING_GET(cq->ring, 1);
1230 bus_dmamap_sync(cq->ring->dma.tag,
1231 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
1232 cqe =
1233 RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_tx_cqe);
1234 num_cqes++;
1235 }
1236
1237 if (num_cqes)
1238 oce_arm_cq(sc, cq->cq_id, num_cqes, FALSE);
1239
1240 return 0;
1241 }
1242
1243
1244 #if __FreeBSD_version >= 1000000
1245 static __inline void
drbr_stats_update(struct ifnet * ifp,int len,int mflags)1246 drbr_stats_update(struct ifnet *ifp, int len, int mflags)
1247 {
1248 #ifndef NO_SLOW_STATS
1249 ifp->if_obytes += len;
1250 if (mflags & M_MCAST)
1251 ifp->if_omcasts++;
1252 #endif
1253 }
1254 #endif
1255
1256 static int
oce_multiq_transmit(struct ifnet * ifp,struct mbuf * m,struct oce_wq * wq)1257 oce_multiq_transmit(struct ifnet *ifp, struct mbuf *m, struct oce_wq *wq)
1258 {
1259 POCE_SOFTC sc = ifp->if_softc;
1260 int status = 0, queue_index = 0;
1261 struct mbuf *next = NULL;
1262 struct buf_ring *br = NULL;
1263
1264 br = wq->br;
1265 queue_index = wq->queue_index;
1266
1267 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1268 IFF_DRV_RUNNING) {
1269 if (m != NULL)
1270 status = drbr_enqueue(ifp, br, m);
1271 return status;
1272 }
1273
1274 if (m != NULL) {
1275 if ((status = drbr_enqueue(ifp, br, m)) != 0)
1276 return status;
1277 }
1278 while ((next = drbr_peek(ifp, br)) != NULL) {
1279 if (oce_tx(sc, &next, queue_index)) {
1280 if (next == NULL) {
1281 drbr_advance(ifp, br);
1282 } else {
1283 drbr_putback(ifp, br, next);
1284 wq->tx_stats.tx_stops ++;
1285 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1286 }
1287 break;
1288 }
1289 drbr_advance(ifp, br);
1290 ifp->if_obytes += next->m_pkthdr.len;
1291 if (next->m_flags & M_MCAST)
1292 ifp->if_omcasts++;
1293 ETHER_BPF_MTAP(ifp, next);
1294 }
1295
1296 return 0;
1297 }
1298
1299
1300
1301
1302 /*****************************************************************************
1303 * Receive routines functions *
1304 *****************************************************************************/
1305
1306 static void
oce_rx(struct oce_rq * rq,uint32_t rqe_idx,struct oce_nic_rx_cqe * cqe)1307 oce_rx(struct oce_rq *rq, uint32_t rqe_idx, struct oce_nic_rx_cqe *cqe)
1308 {
1309 uint32_t out;
1310 struct oce_packet_desc *pd;
1311 POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
1312 int i, len, frag_len;
1313 struct mbuf *m = NULL, *tail = NULL;
1314 uint16_t vtag;
1315
1316 len = cqe->u0.s.pkt_size;
1317 if (!len) {
1318 /*partial DMA workaround for Lancer*/
1319 oce_discard_rx_comp(rq, cqe);
1320 goto exit;
1321 }
1322
1323 /* Get vlan_tag value */
1324 if(IS_BE(sc) || IS_SH(sc))
1325 vtag = BSWAP_16(cqe->u0.s.vlan_tag);
1326 else
1327 vtag = cqe->u0.s.vlan_tag;
1328
1329
1330 for (i = 0; i < cqe->u0.s.num_fragments; i++) {
1331
1332 if (rq->packets_out == rq->packets_in) {
1333 device_printf(sc->dev,
1334 "RQ transmit descriptor missing\n");
1335 }
1336 out = rq->packets_out + 1;
1337 if (out == OCE_RQ_PACKET_ARRAY_SIZE)
1338 out = 0;
1339 pd = &rq->pckts[rq->packets_out];
1340 rq->packets_out = out;
1341
1342 bus_dmamap_sync(rq->tag, pd->map, BUS_DMASYNC_POSTWRITE);
1343 bus_dmamap_unload(rq->tag, pd->map);
1344 rq->pending--;
1345
1346 frag_len = (len > rq->cfg.frag_size) ? rq->cfg.frag_size : len;
1347 pd->mbuf->m_len = frag_len;
1348
1349 if (tail != NULL) {
1350 /* additional fragments */
1351 pd->mbuf->m_flags &= ~M_PKTHDR;
1352 tail->m_next = pd->mbuf;
1353 tail = pd->mbuf;
1354 } else {
1355 /* first fragment, fill out much of the packet header */
1356 pd->mbuf->m_pkthdr.len = len;
1357 pd->mbuf->m_pkthdr.csum_flags = 0;
1358 if (IF_CSUM_ENABLED(sc)) {
1359 if (cqe->u0.s.l4_cksum_pass) {
1360 pd->mbuf->m_pkthdr.csum_flags |=
1361 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1362 pd->mbuf->m_pkthdr.csum_data = 0xffff;
1363 }
1364 if (cqe->u0.s.ip_cksum_pass) {
1365 if (!cqe->u0.s.ip_ver) { /* IPV4 */
1366 pd->mbuf->m_pkthdr.csum_flags |=
1367 (CSUM_IP_CHECKED|CSUM_IP_VALID);
1368 }
1369 }
1370 }
1371 m = tail = pd->mbuf;
1372 }
1373 pd->mbuf = NULL;
1374 len -= frag_len;
1375 }
1376
1377 if (m) {
1378 if (!oce_cqe_portid_valid(sc, cqe)) {
1379 m_freem(m);
1380 goto exit;
1381 }
1382
1383 m->m_pkthdr.rcvif = sc->ifp;
1384 #if __FreeBSD_version >= 800000
1385 if (rq->queue_index)
1386 m->m_pkthdr.flowid = (rq->queue_index - 1);
1387 else
1388 m->m_pkthdr.flowid = rq->queue_index;
1389 M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE);
1390 #endif
1391 /* This deternies if vlan tag is Valid */
1392 if (oce_cqe_vtp_valid(sc, cqe)) {
1393 if (sc->function_mode & FNM_FLEX10_MODE) {
1394 /* FLEX10. If QnQ is not set, neglect VLAN */
1395 if (cqe->u0.s.qnq) {
1396 m->m_pkthdr.ether_vtag = vtag;
1397 m->m_flags |= M_VLANTAG;
1398 }
1399 } else if (sc->pvid != (vtag & VLAN_VID_MASK)) {
1400 /* In UMC mode generally pvid will be striped by
1401 hw. But in some cases we have seen it comes
1402 with pvid. So if pvid == vlan, neglect vlan.
1403 */
1404 m->m_pkthdr.ether_vtag = vtag;
1405 m->m_flags |= M_VLANTAG;
1406 }
1407 }
1408
1409 sc->ifp->if_ipackets++;
1410 #if defined(INET6) || defined(INET)
1411 /* Try to queue to LRO */
1412 if (IF_LRO_ENABLED(sc) &&
1413 (cqe->u0.s.ip_cksum_pass) &&
1414 (cqe->u0.s.l4_cksum_pass) &&
1415 (!cqe->u0.s.ip_ver) &&
1416 (rq->lro.lro_cnt != 0)) {
1417
1418 if (tcp_lro_rx(&rq->lro, m, 0) == 0) {
1419 rq->lro_pkts_queued ++;
1420 goto post_done;
1421 }
1422 /* If LRO posting fails then try to post to STACK */
1423 }
1424 #endif
1425
1426 (*sc->ifp->if_input) (sc->ifp, m);
1427 #if defined(INET6) || defined(INET)
1428 post_done:
1429 #endif
1430 /* Update rx stats per queue */
1431 rq->rx_stats.rx_pkts++;
1432 rq->rx_stats.rx_bytes += cqe->u0.s.pkt_size;
1433 rq->rx_stats.rx_frags += cqe->u0.s.num_fragments;
1434 if (cqe->u0.s.pkt_type == OCE_MULTICAST_PACKET)
1435 rq->rx_stats.rx_mcast_pkts++;
1436 if (cqe->u0.s.pkt_type == OCE_UNICAST_PACKET)
1437 rq->rx_stats.rx_ucast_pkts++;
1438 }
1439 exit:
1440 return;
1441 }
1442
1443
1444 static void
oce_discard_rx_comp(struct oce_rq * rq,struct oce_nic_rx_cqe * cqe)1445 oce_discard_rx_comp(struct oce_rq *rq, struct oce_nic_rx_cqe *cqe)
1446 {
1447 uint32_t out, i = 0;
1448 struct oce_packet_desc *pd;
1449 POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
1450 int num_frags = cqe->u0.s.num_fragments;
1451
1452 for (i = 0; i < num_frags; i++) {
1453 if (rq->packets_out == rq->packets_in) {
1454 device_printf(sc->dev,
1455 "RQ transmit descriptor missing\n");
1456 }
1457 out = rq->packets_out + 1;
1458 if (out == OCE_RQ_PACKET_ARRAY_SIZE)
1459 out = 0;
1460 pd = &rq->pckts[rq->packets_out];
1461 rq->packets_out = out;
1462
1463 bus_dmamap_sync(rq->tag, pd->map, BUS_DMASYNC_POSTWRITE);
1464 bus_dmamap_unload(rq->tag, pd->map);
1465 rq->pending--;
1466 m_freem(pd->mbuf);
1467 }
1468
1469 }
1470
1471
1472 static int
oce_cqe_vtp_valid(POCE_SOFTC sc,struct oce_nic_rx_cqe * cqe)1473 oce_cqe_vtp_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe)
1474 {
1475 struct oce_nic_rx_cqe_v1 *cqe_v1;
1476 int vtp = 0;
1477
1478 if (sc->be3_native) {
1479 cqe_v1 = (struct oce_nic_rx_cqe_v1 *)cqe;
1480 vtp = cqe_v1->u0.s.vlan_tag_present;
1481 } else
1482 vtp = cqe->u0.s.vlan_tag_present;
1483
1484 return vtp;
1485
1486 }
1487
1488
1489 static int
oce_cqe_portid_valid(POCE_SOFTC sc,struct oce_nic_rx_cqe * cqe)1490 oce_cqe_portid_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe)
1491 {
1492 struct oce_nic_rx_cqe_v1 *cqe_v1;
1493 int port_id = 0;
1494
1495 if (sc->be3_native && (IS_BE(sc) || IS_SH(sc))) {
1496 cqe_v1 = (struct oce_nic_rx_cqe_v1 *)cqe;
1497 port_id = cqe_v1->u0.s.port;
1498 if (sc->port_id != port_id)
1499 return 0;
1500 } else
1501 ;/* For BE3 legacy and Lancer this is dummy */
1502
1503 return 1;
1504
1505 }
1506
1507 #if defined(INET6) || defined(INET)
1508 static void
oce_rx_flush_lro(struct oce_rq * rq)1509 oce_rx_flush_lro(struct oce_rq *rq)
1510 {
1511 struct lro_ctrl *lro = &rq->lro;
1512 struct lro_entry *queued;
1513 POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
1514
1515 if (!IF_LRO_ENABLED(sc))
1516 return;
1517
1518 while ((queued = SLIST_FIRST(&lro->lro_active)) != NULL) {
1519 SLIST_REMOVE_HEAD(&lro->lro_active, next);
1520 tcp_lro_flush(lro, queued);
1521 }
1522 rq->lro_pkts_queued = 0;
1523
1524 return;
1525 }
1526
1527
1528 static int
oce_init_lro(POCE_SOFTC sc)1529 oce_init_lro(POCE_SOFTC sc)
1530 {
1531 struct lro_ctrl *lro = NULL;
1532 int i = 0, rc = 0;
1533
1534 for (i = 0; i < sc->nrqs; i++) {
1535 lro = &sc->rq[i]->lro;
1536 rc = tcp_lro_init(lro);
1537 if (rc != 0) {
1538 device_printf(sc->dev, "LRO init failed\n");
1539 return rc;
1540 }
1541 lro->ifp = sc->ifp;
1542 }
1543
1544 return rc;
1545 }
1546
1547
1548 void
oce_free_lro(POCE_SOFTC sc)1549 oce_free_lro(POCE_SOFTC sc)
1550 {
1551 struct lro_ctrl *lro = NULL;
1552 int i = 0;
1553
1554 for (i = 0; i < sc->nrqs; i++) {
1555 lro = &sc->rq[i]->lro;
1556 if (lro)
1557 tcp_lro_free(lro);
1558 }
1559 }
1560 #endif
1561
1562 int
oce_alloc_rx_bufs(struct oce_rq * rq,int count)1563 oce_alloc_rx_bufs(struct oce_rq *rq, int count)
1564 {
1565 POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
1566 int i, in, rc;
1567 struct oce_packet_desc *pd;
1568 bus_dma_segment_t segs[6];
1569 int nsegs, added = 0;
1570 struct oce_nic_rqe *rqe;
1571 pd_rxulp_db_t rxdb_reg;
1572
1573 bzero(&rxdb_reg, sizeof(pd_rxulp_db_t));
1574 for (i = 0; i < count; i++) {
1575 in = rq->packets_in + 1;
1576 if (in == OCE_RQ_PACKET_ARRAY_SIZE)
1577 in = 0;
1578 if (in == rq->packets_out)
1579 break; /* no more room */
1580
1581 pd = &rq->pckts[rq->packets_in];
1582 pd->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1583 if (pd->mbuf == NULL)
1584 break;
1585
1586 pd->mbuf->m_len = pd->mbuf->m_pkthdr.len = MCLBYTES;
1587 rc = bus_dmamap_load_mbuf_sg(rq->tag,
1588 pd->map,
1589 pd->mbuf,
1590 segs, &nsegs, BUS_DMA_NOWAIT);
1591 if (rc) {
1592 m_free(pd->mbuf);
1593 break;
1594 }
1595
1596 if (nsegs != 1) {
1597 i--;
1598 continue;
1599 }
1600
1601 rq->packets_in = in;
1602 bus_dmamap_sync(rq->tag, pd->map, BUS_DMASYNC_PREREAD);
1603
1604 rqe = RING_GET_PRODUCER_ITEM_VA(rq->ring, struct oce_nic_rqe);
1605 rqe->u0.s.frag_pa_hi = ADDR_HI(segs[0].ds_addr);
1606 rqe->u0.s.frag_pa_lo = ADDR_LO(segs[0].ds_addr);
1607 DW_SWAP(u32ptr(rqe), sizeof(struct oce_nic_rqe));
1608 RING_PUT(rq->ring, 1);
1609 added++;
1610 rq->pending++;
1611 }
1612 if (added != 0) {
1613 for (i = added / OCE_MAX_RQ_POSTS; i > 0; i--) {
1614 rxdb_reg.bits.num_posted = OCE_MAX_RQ_POSTS;
1615 rxdb_reg.bits.qid = rq->rq_id;
1616 OCE_WRITE_REG32(sc, db, PD_RXULP_DB, rxdb_reg.dw0);
1617 added -= OCE_MAX_RQ_POSTS;
1618 }
1619 if (added > 0) {
1620 rxdb_reg.bits.qid = rq->rq_id;
1621 rxdb_reg.bits.num_posted = added;
1622 OCE_WRITE_REG32(sc, db, PD_RXULP_DB, rxdb_reg.dw0);
1623 }
1624 }
1625
1626 return 0;
1627 }
1628
1629
1630 /* Handle the Completion Queue for receive */
1631 uint16_t
oce_rq_handler(void * arg)1632 oce_rq_handler(void *arg)
1633 {
1634 struct oce_rq *rq = (struct oce_rq *)arg;
1635 struct oce_cq *cq = rq->cq;
1636 POCE_SOFTC sc = rq->parent;
1637 struct oce_nic_rx_cqe *cqe;
1638 int num_cqes = 0, rq_buffers_used = 0;
1639
1640
1641 bus_dmamap_sync(cq->ring->dma.tag,
1642 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
1643 cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_rx_cqe);
1644 while (cqe->u0.dw[2]) {
1645 DW_SWAP((uint32_t *) cqe, sizeof(oce_rq_cqe));
1646
1647 RING_GET(rq->ring, 1);
1648 if (cqe->u0.s.error == 0) {
1649 oce_rx(rq, cqe->u0.s.frag_index, cqe);
1650 } else {
1651 rq->rx_stats.rxcp_err++;
1652 sc->ifp->if_ierrors++;
1653 /* Post L3/L4 errors to stack.*/
1654 oce_rx(rq, cqe->u0.s.frag_index, cqe);
1655 }
1656 rq->rx_stats.rx_compl++;
1657 cqe->u0.dw[2] = 0;
1658
1659 #if defined(INET6) || defined(INET)
1660 if (IF_LRO_ENABLED(sc) && rq->lro_pkts_queued >= 16) {
1661 oce_rx_flush_lro(rq);
1662 }
1663 #endif
1664
1665 RING_GET(cq->ring, 1);
1666 bus_dmamap_sync(cq->ring->dma.tag,
1667 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
1668 cqe =
1669 RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_rx_cqe);
1670 num_cqes++;
1671 if (num_cqes >= (IS_XE201(sc) ? 8 : oce_max_rsp_handled))
1672 break;
1673 }
1674
1675 #if defined(INET6) || defined(INET)
1676 if (IF_LRO_ENABLED(sc))
1677 oce_rx_flush_lro(rq);
1678 #endif
1679
1680 if (num_cqes) {
1681 oce_arm_cq(sc, cq->cq_id, num_cqes, FALSE);
1682 rq_buffers_used = OCE_RQ_PACKET_ARRAY_SIZE - rq->pending;
1683 if (rq_buffers_used > 1)
1684 oce_alloc_rx_bufs(rq, (rq_buffers_used - 1));
1685 }
1686
1687 return 0;
1688
1689 }
1690
1691
1692
1693
1694 /*****************************************************************************
1695 * Helper function prototypes in this file *
1696 *****************************************************************************/
1697
1698 static int
oce_attach_ifp(POCE_SOFTC sc)1699 oce_attach_ifp(POCE_SOFTC sc)
1700 {
1701
1702 sc->ifp = if_alloc(IFT_ETHER);
1703 if (!sc->ifp)
1704 return ENOMEM;
1705
1706 ifmedia_init(&sc->media, IFM_IMASK, oce_media_change, oce_media_status);
1707 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1708 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1709
1710 sc->ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST;
1711 sc->ifp->if_ioctl = oce_ioctl;
1712 sc->ifp->if_start = oce_start;
1713 sc->ifp->if_init = oce_init;
1714 sc->ifp->if_mtu = ETHERMTU;
1715 sc->ifp->if_softc = sc;
1716 #if __FreeBSD_version >= 800000
1717 sc->ifp->if_transmit = oce_multiq_start;
1718 sc->ifp->if_qflush = oce_multiq_flush;
1719 #endif
1720
1721 if_initname(sc->ifp,
1722 device_get_name(sc->dev), device_get_unit(sc->dev));
1723
1724 sc->ifp->if_snd.ifq_drv_maxlen = OCE_MAX_TX_DESC - 1;
1725 IFQ_SET_MAXLEN(&sc->ifp->if_snd, sc->ifp->if_snd.ifq_drv_maxlen);
1726 IFQ_SET_READY(&sc->ifp->if_snd);
1727
1728 sc->ifp->if_hwassist = OCE_IF_HWASSIST;
1729 sc->ifp->if_hwassist |= CSUM_TSO;
1730 sc->ifp->if_hwassist |= (CSUM_IP | CSUM_TCP | CSUM_UDP);
1731
1732 sc->ifp->if_capabilities = OCE_IF_CAPABILITIES;
1733 sc->ifp->if_capabilities |= IFCAP_HWCSUM;
1734 sc->ifp->if_capabilities |= IFCAP_VLAN_HWFILTER;
1735
1736 #if defined(INET6) || defined(INET)
1737 sc->ifp->if_capabilities |= IFCAP_TSO;
1738 sc->ifp->if_capabilities |= IFCAP_LRO;
1739 sc->ifp->if_capabilities |= IFCAP_VLAN_HWTSO;
1740 #endif
1741
1742 sc->ifp->if_capenable = sc->ifp->if_capabilities;
1743 if_initbaudrate(sc->ifp, IF_Gbps(10));
1744
1745 #if __FreeBSD_version >= 1000000
1746 sc->ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
1747 sc->ifp->if_hw_tsomaxsegcount = OCE_MAX_TX_ELEMENTS;
1748 sc->ifp->if_hw_tsomaxsegsize = 4096;
1749 #endif
1750
1751 ether_ifattach(sc->ifp, sc->macaddr.mac_addr);
1752
1753 return 0;
1754 }
1755
1756
1757 static void
oce_add_vlan(void * arg,struct ifnet * ifp,uint16_t vtag)1758 oce_add_vlan(void *arg, struct ifnet *ifp, uint16_t vtag)
1759 {
1760 POCE_SOFTC sc = ifp->if_softc;
1761
1762 if (ifp->if_softc != arg)
1763 return;
1764 if ((vtag == 0) || (vtag > 4095))
1765 return;
1766
1767 sc->vlan_tag[vtag] = 1;
1768 sc->vlans_added++;
1769 if (sc->vlans_added <= (sc->max_vlans + 1))
1770 oce_vid_config(sc);
1771 }
1772
1773
1774 static void
oce_del_vlan(void * arg,struct ifnet * ifp,uint16_t vtag)1775 oce_del_vlan(void *arg, struct ifnet *ifp, uint16_t vtag)
1776 {
1777 POCE_SOFTC sc = ifp->if_softc;
1778
1779 if (ifp->if_softc != arg)
1780 return;
1781 if ((vtag == 0) || (vtag > 4095))
1782 return;
1783
1784 sc->vlan_tag[vtag] = 0;
1785 sc->vlans_added--;
1786 oce_vid_config(sc);
1787 }
1788
1789
1790 /*
1791 * A max of 64 vlans can be configured in BE. If the user configures
1792 * more, place the card in vlan promiscuous mode.
1793 */
1794 static int
oce_vid_config(POCE_SOFTC sc)1795 oce_vid_config(POCE_SOFTC sc)
1796 {
1797 struct normal_vlan vtags[MAX_VLANFILTER_SIZE];
1798 uint16_t ntags = 0, i;
1799 int status = 0;
1800
1801 if ((sc->vlans_added <= MAX_VLANFILTER_SIZE) &&
1802 (sc->ifp->if_capenable & IFCAP_VLAN_HWFILTER)) {
1803 for (i = 0; i < MAX_VLANS; i++) {
1804 if (sc->vlan_tag[i]) {
1805 vtags[ntags].vtag = i;
1806 ntags++;
1807 }
1808 }
1809 if (ntags)
1810 status = oce_config_vlan(sc, (uint8_t) sc->if_id,
1811 vtags, ntags, 1, 0);
1812 } else
1813 status = oce_config_vlan(sc, (uint8_t) sc->if_id,
1814 NULL, 0, 1, 1);
1815 return status;
1816 }
1817
1818
1819 static void
oce_mac_addr_set(POCE_SOFTC sc)1820 oce_mac_addr_set(POCE_SOFTC sc)
1821 {
1822 uint32_t old_pmac_id = sc->pmac_id;
1823 int status = 0;
1824
1825
1826 status = bcmp((IF_LLADDR(sc->ifp)), sc->macaddr.mac_addr,
1827 sc->macaddr.size_of_struct);
1828 if (!status)
1829 return;
1830
1831 status = oce_mbox_macaddr_add(sc, (uint8_t *)(IF_LLADDR(sc->ifp)),
1832 sc->if_id, &sc->pmac_id);
1833 if (!status) {
1834 status = oce_mbox_macaddr_del(sc, sc->if_id, old_pmac_id);
1835 bcopy((IF_LLADDR(sc->ifp)), sc->macaddr.mac_addr,
1836 sc->macaddr.size_of_struct);
1837 }
1838 if (status)
1839 device_printf(sc->dev, "Failed update macaddress\n");
1840
1841 }
1842
1843
1844 static int
oce_handle_passthrough(struct ifnet * ifp,caddr_t data)1845 oce_handle_passthrough(struct ifnet *ifp, caddr_t data)
1846 {
1847 POCE_SOFTC sc = ifp->if_softc;
1848 struct ifreq *ifr = (struct ifreq *)data;
1849 int rc = ENXIO;
1850 char cookie[32] = {0};
1851 void *priv_data = (void *)ifr->ifr_data;
1852 void *ioctl_ptr;
1853 uint32_t req_size;
1854 struct mbx_hdr req;
1855 OCE_DMA_MEM dma_mem;
1856 struct mbx_common_get_cntl_attr *fw_cmd;
1857
1858 if (copyin(priv_data, cookie, strlen(IOCTL_COOKIE)))
1859 return EFAULT;
1860
1861 if (memcmp(cookie, IOCTL_COOKIE, strlen(IOCTL_COOKIE)))
1862 return EINVAL;
1863
1864 ioctl_ptr = (char *)priv_data + strlen(IOCTL_COOKIE);
1865 if (copyin(ioctl_ptr, &req, sizeof(struct mbx_hdr)))
1866 return EFAULT;
1867
1868 req_size = le32toh(req.u0.req.request_length);
1869 if (req_size > 65536)
1870 return EINVAL;
1871
1872 req_size += sizeof(struct mbx_hdr);
1873 rc = oce_dma_alloc(sc, req_size, &dma_mem, 0);
1874 if (rc)
1875 return ENOMEM;
1876
1877 if (copyin(ioctl_ptr, OCE_DMAPTR(&dma_mem,char), req_size)) {
1878 rc = EFAULT;
1879 goto dma_free;
1880 }
1881
1882 rc = oce_pass_through_mbox(sc, &dma_mem, req_size);
1883 if (rc) {
1884 rc = EIO;
1885 goto dma_free;
1886 }
1887
1888 if (copyout(OCE_DMAPTR(&dma_mem,char), ioctl_ptr, req_size))
1889 rc = EFAULT;
1890
1891 /*
1892 firmware is filling all the attributes for this ioctl except
1893 the driver version..so fill it
1894 */
1895 if(req.u0.rsp.opcode == OPCODE_COMMON_GET_CNTL_ATTRIBUTES) {
1896 fw_cmd = (struct mbx_common_get_cntl_attr *) ioctl_ptr;
1897 strncpy(fw_cmd->params.rsp.cntl_attr_info.hba_attr.drv_ver_str,
1898 COMPONENT_REVISION, strlen(COMPONENT_REVISION));
1899 }
1900
1901 dma_free:
1902 oce_dma_free(sc, &dma_mem);
1903 return rc;
1904
1905 }
1906
1907 static void
oce_eqd_set_periodic(POCE_SOFTC sc)1908 oce_eqd_set_periodic(POCE_SOFTC sc)
1909 {
1910 struct oce_set_eqd set_eqd[OCE_MAX_EQ];
1911 struct oce_aic_obj *aic;
1912 struct oce_eq *eqo;
1913 uint64_t now = 0, delta;
1914 int eqd, i, num = 0;
1915 uint32_t ips = 0;
1916 int tps;
1917
1918 for (i = 0 ; i < sc->neqs; i++) {
1919 eqo = sc->eq[i];
1920 aic = &sc->aic_obj[i];
1921 /* When setting the static eq delay from the user space */
1922 if (!aic->enable) {
1923 eqd = aic->et_eqd;
1924 goto modify_eqd;
1925 }
1926
1927 now = ticks;
1928
1929 /* Over flow check */
1930 if ((now < aic->ticks) || (eqo->intr < aic->intr_prev))
1931 goto done;
1932
1933 delta = now - aic->ticks;
1934 tps = delta/hz;
1935
1936 /* Interrupt rate based on elapsed ticks */
1937 if(tps)
1938 ips = (uint32_t)(eqo->intr - aic->intr_prev) / tps;
1939
1940 if (ips > INTR_RATE_HWM)
1941 eqd = aic->cur_eqd + 20;
1942 else if (ips < INTR_RATE_LWM)
1943 eqd = aic->cur_eqd / 2;
1944 else
1945 goto done;
1946
1947 if (eqd < 10)
1948 eqd = 0;
1949
1950 /* Make sure that the eq delay is in the known range */
1951 eqd = min(eqd, aic->max_eqd);
1952 eqd = max(eqd, aic->min_eqd);
1953
1954 modify_eqd:
1955 if (eqd != aic->cur_eqd) {
1956 set_eqd[num].delay_multiplier = (eqd * 65)/100;
1957 set_eqd[num].eq_id = eqo->eq_id;
1958 aic->cur_eqd = eqd;
1959 num++;
1960 }
1961 done:
1962 aic->intr_prev = eqo->intr;
1963 aic->ticks = now;
1964 }
1965
1966 /* Is there atleast one eq that needs to be modified? */
1967 if(num)
1968 oce_mbox_eqd_modify_periodic(sc, set_eqd, num);
1969 }
1970
oce_detect_hw_error(POCE_SOFTC sc)1971 static void oce_detect_hw_error(POCE_SOFTC sc)
1972 {
1973
1974 uint32_t ue_low = 0, ue_high = 0, ue_low_mask = 0, ue_high_mask = 0;
1975 uint32_t sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
1976 uint32_t i;
1977
1978 if (sc->hw_error)
1979 return;
1980
1981 if (IS_XE201(sc)) {
1982 sliport_status = OCE_READ_REG32(sc, db, SLIPORT_STATUS_OFFSET);
1983 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
1984 sliport_err1 = OCE_READ_REG32(sc, db, SLIPORT_ERROR1_OFFSET);
1985 sliport_err2 = OCE_READ_REG32(sc, db, SLIPORT_ERROR2_OFFSET);
1986 }
1987 } else {
1988 ue_low = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_LOW);
1989 ue_high = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_HIGH);
1990 ue_low_mask = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_LOW_MASK);
1991 ue_high_mask = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_HI_MASK);
1992
1993 ue_low = (ue_low & ~ue_low_mask);
1994 ue_high = (ue_high & ~ue_high_mask);
1995 }
1996
1997 /* On certain platforms BE hardware can indicate spurious UEs.
1998 * Allow the h/w to stop working completely in case of a real UE.
1999 * Hence not setting the hw_error for UE detection.
2000 */
2001 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
2002 sc->hw_error = TRUE;
2003 device_printf(sc->dev, "Error detected in the card\n");
2004 }
2005
2006 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
2007 device_printf(sc->dev,
2008 "ERR: sliport status 0x%x\n", sliport_status);
2009 device_printf(sc->dev,
2010 "ERR: sliport error1 0x%x\n", sliport_err1);
2011 device_printf(sc->dev,
2012 "ERR: sliport error2 0x%x\n", sliport_err2);
2013 }
2014
2015 if (ue_low) {
2016 for (i = 0; ue_low; ue_low >>= 1, i++) {
2017 if (ue_low & 1)
2018 device_printf(sc->dev, "UE: %s bit set\n",
2019 ue_status_low_desc[i]);
2020 }
2021 }
2022
2023 if (ue_high) {
2024 for (i = 0; ue_high; ue_high >>= 1, i++) {
2025 if (ue_high & 1)
2026 device_printf(sc->dev, "UE: %s bit set\n",
2027 ue_status_hi_desc[i]);
2028 }
2029 }
2030
2031 }
2032
2033
2034 static void
oce_local_timer(void * arg)2035 oce_local_timer(void *arg)
2036 {
2037 POCE_SOFTC sc = arg;
2038 int i = 0;
2039
2040 oce_detect_hw_error(sc);
2041 oce_refresh_nic_stats(sc);
2042 oce_refresh_queue_stats(sc);
2043 oce_mac_addr_set(sc);
2044
2045 /* TX Watch Dog*/
2046 for (i = 0; i < sc->nwqs; i++)
2047 oce_tx_restart(sc, sc->wq[i]);
2048
2049 /* calculate and set the eq delay for optimal interrupt rate */
2050 if (IS_BE(sc) || IS_SH(sc))
2051 oce_eqd_set_periodic(sc);
2052
2053 callout_reset(&sc->timer, hz, oce_local_timer, sc);
2054 }
2055
2056
2057 /* NOTE : This should only be called holding
2058 * DEVICE_LOCK.
2059 */
2060 static void
oce_if_deactivate(POCE_SOFTC sc)2061 oce_if_deactivate(POCE_SOFTC sc)
2062 {
2063 int i, mtime = 0;
2064 int wait_req = 0;
2065 struct oce_rq *rq;
2066 struct oce_wq *wq;
2067 struct oce_eq *eq;
2068
2069 sc->ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2070
2071 /*Wait for max of 400ms for TX completions to be done */
2072 while (mtime < 400) {
2073 wait_req = 0;
2074 for_all_wq_queues(sc, wq, i) {
2075 if (wq->ring->num_used) {
2076 wait_req = 1;
2077 DELAY(1);
2078 break;
2079 }
2080 }
2081 mtime += 1;
2082 if (!wait_req)
2083 break;
2084 }
2085
2086 /* Stop intrs and finish any bottom halves pending */
2087 oce_hw_intr_disable(sc);
2088
2089 /* Since taskqueue_drain takes a Gaint Lock, We should not acquire
2090 any other lock. So unlock device lock and require after
2091 completing taskqueue_drain.
2092 */
2093 UNLOCK(&sc->dev_lock);
2094 for (i = 0; i < sc->intr_count; i++) {
2095 if (sc->intrs[i].tq != NULL) {
2096 taskqueue_drain(sc->intrs[i].tq, &sc->intrs[i].task);
2097 }
2098 }
2099 LOCK(&sc->dev_lock);
2100
2101 /* Delete RX queue in card with flush param */
2102 oce_stop_rx(sc);
2103
2104 /* Invalidate any pending cq and eq entries*/
2105 for_all_evnt_queues(sc, eq, i)
2106 oce_drain_eq(eq);
2107 for_all_rq_queues(sc, rq, i)
2108 oce_drain_rq_cq(rq);
2109 for_all_wq_queues(sc, wq, i)
2110 oce_drain_wq_cq(wq);
2111
2112 /* But still we need to get MCC aync events.
2113 So enable intrs and also arm first EQ
2114 */
2115 oce_hw_intr_enable(sc);
2116 oce_arm_eq(sc, sc->eq[0]->eq_id, 0, TRUE, FALSE);
2117
2118 DELAY(10);
2119 }
2120
2121
2122 static void
oce_if_activate(POCE_SOFTC sc)2123 oce_if_activate(POCE_SOFTC sc)
2124 {
2125 struct oce_eq *eq;
2126 struct oce_rq *rq;
2127 struct oce_wq *wq;
2128 int i, rc = 0;
2129
2130 sc->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2131
2132 oce_hw_intr_disable(sc);
2133
2134 oce_start_rx(sc);
2135
2136 for_all_rq_queues(sc, rq, i) {
2137 rc = oce_start_rq(rq);
2138 if (rc)
2139 device_printf(sc->dev, "Unable to start RX\n");
2140 }
2141
2142 for_all_wq_queues(sc, wq, i) {
2143 rc = oce_start_wq(wq);
2144 if (rc)
2145 device_printf(sc->dev, "Unable to start TX\n");
2146 }
2147
2148
2149 for_all_evnt_queues(sc, eq, i)
2150 oce_arm_eq(sc, eq->eq_id, 0, TRUE, FALSE);
2151
2152 oce_hw_intr_enable(sc);
2153
2154 }
2155
2156 static void
process_link_state(POCE_SOFTC sc,struct oce_async_cqe_link_state * acqe)2157 process_link_state(POCE_SOFTC sc, struct oce_async_cqe_link_state *acqe)
2158 {
2159 /* Update Link status */
2160 if ((acqe->u0.s.link_status & ~ASYNC_EVENT_LOGICAL) ==
2161 ASYNC_EVENT_LINK_UP) {
2162 sc->link_status = ASYNC_EVENT_LINK_UP;
2163 if_link_state_change(sc->ifp, LINK_STATE_UP);
2164 } else {
2165 sc->link_status = ASYNC_EVENT_LINK_DOWN;
2166 if_link_state_change(sc->ifp, LINK_STATE_DOWN);
2167 }
2168 }
2169
2170
2171 /* Handle the Completion Queue for the Mailbox/Async notifications */
2172 uint16_t
oce_mq_handler(void * arg)2173 oce_mq_handler(void *arg)
2174 {
2175 struct oce_mq *mq = (struct oce_mq *)arg;
2176 POCE_SOFTC sc = mq->parent;
2177 struct oce_cq *cq = mq->cq;
2178 int num_cqes = 0, evt_type = 0, optype = 0;
2179 struct oce_mq_cqe *cqe;
2180 struct oce_async_cqe_link_state *acqe;
2181 struct oce_async_event_grp5_pvid_state *gcqe;
2182 struct oce_async_event_qnq *dbgcqe;
2183
2184
2185 bus_dmamap_sync(cq->ring->dma.tag,
2186 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
2187 cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_mq_cqe);
2188
2189 while (cqe->u0.dw[3]) {
2190 DW_SWAP((uint32_t *) cqe, sizeof(oce_mq_cqe));
2191 if (cqe->u0.s.async_event) {
2192 evt_type = cqe->u0.s.event_type;
2193 optype = cqe->u0.s.async_type;
2194 if (evt_type == ASYNC_EVENT_CODE_LINK_STATE) {
2195 /* Link status evt */
2196 acqe = (struct oce_async_cqe_link_state *)cqe;
2197 process_link_state(sc, acqe);
2198 } else if ((evt_type == ASYNC_EVENT_GRP5) &&
2199 (optype == ASYNC_EVENT_PVID_STATE)) {
2200 /* GRP5 PVID */
2201 gcqe =
2202 (struct oce_async_event_grp5_pvid_state *)cqe;
2203 if (gcqe->enabled)
2204 sc->pvid = gcqe->tag & VLAN_VID_MASK;
2205 else
2206 sc->pvid = 0;
2207
2208 }
2209 else if(evt_type == ASYNC_EVENT_CODE_DEBUG &&
2210 optype == ASYNC_EVENT_DEBUG_QNQ) {
2211 dbgcqe =
2212 (struct oce_async_event_qnq *)cqe;
2213 if(dbgcqe->valid)
2214 sc->qnqid = dbgcqe->vlan_tag;
2215 sc->qnq_debug_event = TRUE;
2216 }
2217 }
2218 cqe->u0.dw[3] = 0;
2219 RING_GET(cq->ring, 1);
2220 bus_dmamap_sync(cq->ring->dma.tag,
2221 cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
2222 cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_mq_cqe);
2223 num_cqes++;
2224 }
2225
2226 if (num_cqes)
2227 oce_arm_cq(sc, cq->cq_id, num_cqes, FALSE);
2228
2229 return 0;
2230 }
2231
2232
2233 static void
setup_max_queues_want(POCE_SOFTC sc)2234 setup_max_queues_want(POCE_SOFTC sc)
2235 {
2236 /* Check if it is FLEX machine. Is so dont use RSS */
2237 if ((sc->function_mode & FNM_FLEX10_MODE) ||
2238 (sc->function_mode & FNM_UMC_MODE) ||
2239 (sc->function_mode & FNM_VNIC_MODE) ||
2240 (!is_rss_enabled(sc)) ||
2241 IS_BE2(sc)) {
2242 sc->nrqs = 1;
2243 sc->nwqs = 1;
2244 } else {
2245 sc->nrqs = MIN(OCE_NCPUS, sc->nrssqs) + 1;
2246 sc->nwqs = MIN(OCE_NCPUS, sc->nrssqs);
2247 }
2248
2249 if (IS_BE2(sc) && is_rss_enabled(sc))
2250 sc->nrqs = MIN(OCE_NCPUS, sc->nrssqs) + 1;
2251 }
2252
2253
2254 static void
update_queues_got(POCE_SOFTC sc)2255 update_queues_got(POCE_SOFTC sc)
2256 {
2257 if (is_rss_enabled(sc)) {
2258 sc->nrqs = sc->intr_count + 1;
2259 sc->nwqs = sc->intr_count;
2260 } else {
2261 sc->nrqs = 1;
2262 sc->nwqs = 1;
2263 }
2264
2265 if (IS_BE2(sc))
2266 sc->nwqs = 1;
2267 }
2268
2269 static int
oce_check_ipv6_ext_hdr(struct mbuf * m)2270 oce_check_ipv6_ext_hdr(struct mbuf *m)
2271 {
2272 struct ether_header *eh = mtod(m, struct ether_header *);
2273 caddr_t m_datatemp = m->m_data;
2274
2275 if (eh->ether_type == htons(ETHERTYPE_IPV6)) {
2276 m->m_data += sizeof(struct ether_header);
2277 struct ip6_hdr *ip6 = mtod(m, struct ip6_hdr *);
2278
2279 if((ip6->ip6_nxt != IPPROTO_TCP) && \
2280 (ip6->ip6_nxt != IPPROTO_UDP)){
2281 struct ip6_ext *ip6e = NULL;
2282 m->m_data += sizeof(struct ip6_hdr);
2283
2284 ip6e = (struct ip6_ext *) mtod(m, struct ip6_ext *);
2285 if(ip6e->ip6e_len == 0xff) {
2286 m->m_data = m_datatemp;
2287 return TRUE;
2288 }
2289 }
2290 m->m_data = m_datatemp;
2291 }
2292 return FALSE;
2293 }
2294
2295 static int
is_be3_a1(POCE_SOFTC sc)2296 is_be3_a1(POCE_SOFTC sc)
2297 {
2298 if((sc->flags & OCE_FLAGS_BE3) && ((sc->asic_revision & 0xFF) < 2)) {
2299 return TRUE;
2300 }
2301 return FALSE;
2302 }
2303
2304 static struct mbuf *
oce_insert_vlan_tag(POCE_SOFTC sc,struct mbuf * m,boolean_t * complete)2305 oce_insert_vlan_tag(POCE_SOFTC sc, struct mbuf *m, boolean_t *complete)
2306 {
2307 uint16_t vlan_tag = 0;
2308
2309 if(!M_WRITABLE(m))
2310 return NULL;
2311
2312 /* Embed vlan tag in the packet if it is not part of it */
2313 if(m->m_flags & M_VLANTAG) {
2314 vlan_tag = EVL_VLANOFTAG(m->m_pkthdr.ether_vtag);
2315 m->m_flags &= ~M_VLANTAG;
2316 }
2317
2318 /* if UMC, ignore vlan tag insertion and instead insert pvid */
2319 if(sc->pvid) {
2320 if(!vlan_tag)
2321 vlan_tag = sc->pvid;
2322 *complete = FALSE;
2323 }
2324
2325 if(vlan_tag) {
2326 m = ether_vlanencap(m, vlan_tag);
2327 }
2328
2329 if(sc->qnqid) {
2330 m = ether_vlanencap(m, sc->qnqid);
2331 *complete = FALSE;
2332 }
2333 return m;
2334 }
2335
2336 static int
oce_tx_asic_stall_verify(POCE_SOFTC sc,struct mbuf * m)2337 oce_tx_asic_stall_verify(POCE_SOFTC sc, struct mbuf *m)
2338 {
2339 if(is_be3_a1(sc) && IS_QNQ_OR_UMC(sc) && \
2340 oce_check_ipv6_ext_hdr(m)) {
2341 return TRUE;
2342 }
2343 return FALSE;
2344 }
2345
2346 static void
oce_get_config(POCE_SOFTC sc)2347 oce_get_config(POCE_SOFTC sc)
2348 {
2349 int rc = 0;
2350 uint32_t max_rss = 0;
2351
2352 if ((IS_BE(sc) || IS_SH(sc)) && (!sc->be3_native))
2353 max_rss = OCE_LEGACY_MODE_RSS;
2354 else
2355 max_rss = OCE_MAX_RSS;
2356
2357 if (!IS_BE(sc)) {
2358 rc = oce_get_profile_config(sc, max_rss);
2359 if (rc) {
2360 sc->nwqs = OCE_MAX_WQ;
2361 sc->nrssqs = max_rss;
2362 sc->nrqs = sc->nrssqs + 1;
2363 }
2364 }
2365 else { /* For BE3 don't rely on fw for determining the resources */
2366 sc->nrssqs = max_rss;
2367 sc->nrqs = sc->nrssqs + 1;
2368 sc->nwqs = OCE_MAX_WQ;
2369 sc->max_vlans = MAX_VLANFILTER_SIZE;
2370 }
2371 }
2372