1 /*-
2 * Copyright (C) 2013 Emulex
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Emulex Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
39 /* $FreeBSD$ */
40
41 #include "oce_if.h"
42
43 int
oce_wait_ready(POCE_SOFTC sc)44 oce_wait_ready(POCE_SOFTC sc)
45 {
46 #define SLIPORT_READY_TIMEOUT 30000
47 uint32_t sliport_status, i;
48
49 if (!IS_XE201(sc))
50 return (-1);
51
52 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
53 sliport_status = OCE_READ_REG32(sc, db, SLIPORT_STATUS_OFFSET);
54 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
55 return 0;
56
57 if (sliport_status & SLIPORT_STATUS_ERR_MASK &&
58 !(sliport_status & SLIPORT_STATUS_RN_MASK)) {
59 device_printf(sc->dev, "Error detected in the card\n");
60 return EIO;
61 }
62
63 DELAY(1000);
64 }
65
66 device_printf(sc->dev, "Firmware wait timed out\n");
67
68 return (-1);
69 }
70
71 /**
72 * @brief Reset (firmware) common function
73 * @param sc software handle to the device
74 * @returns 0 on success, ETIMEDOUT on failure
75 */
76 int
oce_reset_fun(POCE_SOFTC sc)77 oce_reset_fun(POCE_SOFTC sc)
78 {
79 struct oce_mbx *mbx;
80 struct oce_bmbx *mb;
81 struct ioctl_common_function_reset *fwcmd;
82 int rc = 0;
83
84 if (IS_XE201(sc)) {
85 OCE_WRITE_REG32(sc, db, SLIPORT_CONTROL_OFFSET,
86 SLI_PORT_CONTROL_IP_MASK);
87
88 rc = oce_wait_ready(sc);
89 if (rc) {
90 device_printf(sc->dev, "Firmware reset Failed\n");
91 }
92
93 return rc;
94 }
95
96 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
97 mbx = &mb->mbx;
98 bzero(mbx, sizeof(struct oce_mbx));
99
100 fwcmd = (struct ioctl_common_function_reset *)&mbx->payload;
101 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
102 MBX_SUBSYSTEM_COMMON,
103 OPCODE_COMMON_FUNCTION_RESET,
104 10, /* MBX_TIMEOUT_SEC */
105 sizeof(struct
106 ioctl_common_function_reset),
107 OCE_MBX_VER_V0);
108
109 mbx->u0.s.embedded = 1;
110 mbx->payload_length =
111 sizeof(struct ioctl_common_function_reset);
112
113 rc = oce_mbox_dispatch(sc, 2);
114
115 return rc;
116 }
117
118
119 /**
120 * @brief This funtions tells firmware we are
121 * done with commands.
122 * @param sc software handle to the device
123 * @returns 0 on success, ETIMEDOUT on failure
124 */
125 int
oce_fw_clean(POCE_SOFTC sc)126 oce_fw_clean(POCE_SOFTC sc)
127 {
128 struct oce_bmbx *mbx;
129 uint8_t *ptr;
130 int ret = 0;
131
132 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
133 ptr = (uint8_t *) &mbx->mbx;
134
135 /* Endian Signature */
136 *ptr++ = 0xff;
137 *ptr++ = 0xaa;
138 *ptr++ = 0xbb;
139 *ptr++ = 0xff;
140 *ptr++ = 0xff;
141 *ptr++ = 0xcc;
142 *ptr++ = 0xdd;
143 *ptr = 0xff;
144
145 ret = oce_mbox_dispatch(sc, 2);
146
147 return ret;
148 }
149
150
151 /**
152 * @brief Mailbox wait
153 * @param sc software handle to the device
154 * @param tmo_sec timeout in seconds
155 */
156 static int
oce_mbox_wait(POCE_SOFTC sc,uint32_t tmo_sec)157 oce_mbox_wait(POCE_SOFTC sc, uint32_t tmo_sec)
158 {
159 tmo_sec *= 10000;
160 pd_mpu_mbox_db_t mbox_db;
161
162 for (;;) {
163 if (tmo_sec != 0) {
164 if (--tmo_sec == 0)
165 break;
166 }
167
168 mbox_db.dw0 = OCE_READ_REG32(sc, db, PD_MPU_MBOX_DB);
169
170 if (mbox_db.bits.ready)
171 return 0;
172
173 DELAY(100);
174 }
175
176 device_printf(sc->dev, "Mailbox timed out\n");
177
178 return ETIMEDOUT;
179 }
180
181
182 /**
183 * @brief Mailbox dispatch
184 * @param sc software handle to the device
185 * @param tmo_sec timeout in seconds
186 */
187 int
oce_mbox_dispatch(POCE_SOFTC sc,uint32_t tmo_sec)188 oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec)
189 {
190 pd_mpu_mbox_db_t mbox_db;
191 uint32_t pa;
192 int rc;
193
194 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_PREWRITE);
195 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 34);
196 bzero(&mbox_db, sizeof(pd_mpu_mbox_db_t));
197 mbox_db.bits.ready = 0;
198 mbox_db.bits.hi = 1;
199 mbox_db.bits.address = pa;
200
201 rc = oce_mbox_wait(sc, tmo_sec);
202 if (rc == 0) {
203 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0);
204
205 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 4) & 0x3fffffff;
206 mbox_db.bits.ready = 0;
207 mbox_db.bits.hi = 0;
208 mbox_db.bits.address = pa;
209
210 rc = oce_mbox_wait(sc, tmo_sec);
211
212 if (rc == 0) {
213 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0);
214
215 rc = oce_mbox_wait(sc, tmo_sec);
216
217 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_POSTWRITE);
218 }
219 }
220
221 return rc;
222 }
223
224
225
226 /**
227 * @brief Mailbox common request header initialization
228 * @param hdr mailbox header
229 * @param dom domain
230 * @param port port
231 * @param subsys subsystem
232 * @param opcode opcode
233 * @param timeout timeout
234 * @param pyld_len payload length
235 */
236 void
mbx_common_req_hdr_init(struct mbx_hdr * hdr,uint8_t dom,uint8_t port,uint8_t subsys,uint8_t opcode,uint32_t timeout,uint32_t pyld_len,uint8_t version)237 mbx_common_req_hdr_init(struct mbx_hdr *hdr,
238 uint8_t dom, uint8_t port,
239 uint8_t subsys, uint8_t opcode,
240 uint32_t timeout, uint32_t pyld_len,
241 uint8_t version)
242 {
243 hdr->u0.req.opcode = opcode;
244 hdr->u0.req.subsystem = subsys;
245 hdr->u0.req.port_number = port;
246 hdr->u0.req.domain = dom;
247
248 hdr->u0.req.timeout = timeout;
249 hdr->u0.req.request_length = pyld_len - sizeof(struct mbx_hdr);
250 hdr->u0.req.version = version;
251 }
252
253
254
255 /**
256 * @brief Function to initialize the hw with host endian information
257 * @param sc software handle to the device
258 * @returns 0 on success, ETIMEDOUT on failure
259 */
260 int
oce_mbox_init(POCE_SOFTC sc)261 oce_mbox_init(POCE_SOFTC sc)
262 {
263 struct oce_bmbx *mbx;
264 uint8_t *ptr;
265 int ret = 0;
266
267 if (sc->flags & OCE_FLAGS_MBOX_ENDIAN_RQD) {
268 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
269 ptr = (uint8_t *) &mbx->mbx;
270
271 /* Endian Signature */
272 *ptr++ = 0xff;
273 *ptr++ = 0x12;
274 *ptr++ = 0x34;
275 *ptr++ = 0xff;
276 *ptr++ = 0xff;
277 *ptr++ = 0x56;
278 *ptr++ = 0x78;
279 *ptr = 0xff;
280
281 ret = oce_mbox_dispatch(sc, 0);
282 }
283
284 return ret;
285 }
286
287
288 /**
289 * @brief Function to get the firmware version
290 * @param sc software handle to the device
291 * @returns 0 on success, EIO on failure
292 */
293 int
oce_get_fw_version(POCE_SOFTC sc)294 oce_get_fw_version(POCE_SOFTC sc)
295 {
296 struct oce_mbx mbx;
297 struct mbx_get_common_fw_version *fwcmd;
298 int ret = 0;
299
300 bzero(&mbx, sizeof(struct oce_mbx));
301
302 fwcmd = (struct mbx_get_common_fw_version *)&mbx.payload;
303 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
304 MBX_SUBSYSTEM_COMMON,
305 OPCODE_COMMON_GET_FW_VERSION,
306 MBX_TIMEOUT_SEC,
307 sizeof(struct mbx_get_common_fw_version),
308 OCE_MBX_VER_V0);
309
310 mbx.u0.s.embedded = 1;
311 mbx.payload_length = sizeof(struct mbx_get_common_fw_version);
312 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
313
314 ret = oce_mbox_post(sc, &mbx, NULL);
315 if (!ret)
316 ret = fwcmd->hdr.u0.rsp.status;
317 if (ret) {
318 device_printf(sc->dev,
319 "%s failed - cmd status: %d addi status: %d\n",
320 __FUNCTION__, ret,
321 fwcmd->hdr.u0.rsp.additional_status);
322 goto error;
323 }
324
325 bcopy(fwcmd->params.rsp.fw_ver_str, sc->fw_version, 32);
326 error:
327 return ret;
328 }
329
330
331 /**
332 * @brief Firmware will send gracious notifications during
333 * attach only after sending first mcc commnad. We
334 * use MCC queue only for getting async and mailbox
335 * for sending cmds. So to get gracious notifications
336 * atleast send one dummy command on mcc.
337 */
338 int
oce_first_mcc_cmd(POCE_SOFTC sc)339 oce_first_mcc_cmd(POCE_SOFTC sc)
340 {
341 struct oce_mbx *mbx;
342 struct oce_mq *mq = sc->mq;
343 struct mbx_get_common_fw_version *fwcmd;
344 uint32_t reg_value;
345
346 mbx = RING_GET_PRODUCER_ITEM_VA(mq->ring, struct oce_mbx);
347 bzero(mbx, sizeof(struct oce_mbx));
348
349 fwcmd = (struct mbx_get_common_fw_version *)&mbx->payload;
350 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
351 MBX_SUBSYSTEM_COMMON,
352 OPCODE_COMMON_GET_FW_VERSION,
353 MBX_TIMEOUT_SEC,
354 sizeof(struct mbx_get_common_fw_version),
355 OCE_MBX_VER_V0);
356 mbx->u0.s.embedded = 1;
357 mbx->payload_length = sizeof(struct mbx_get_common_fw_version);
358 bus_dmamap_sync(mq->ring->dma.tag, mq->ring->dma.map,
359 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
360 RING_PUT(mq->ring, 1);
361 reg_value = (1 << 16) | mq->mq_id;
362 OCE_WRITE_REG32(sc, db, PD_MQ_DB, reg_value);
363
364 return 0;
365 }
366
367 /**
368 * @brief Function to post a MBX to the mbox
369 * @param sc software handle to the device
370 * @param mbx pointer to the MBX to send
371 * @param mbxctx pointer to the mbx context structure
372 * @returns 0 on success, error on failure
373 */
374 int
oce_mbox_post(POCE_SOFTC sc,struct oce_mbx * mbx,struct oce_mbx_ctx * mbxctx)375 oce_mbox_post(POCE_SOFTC sc, struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx)
376 {
377 struct oce_mbx *mb_mbx = NULL;
378 struct oce_mq_cqe *mb_cqe = NULL;
379 struct oce_bmbx *mb = NULL;
380 int rc = 0;
381 uint32_t tmo = 0;
382 uint32_t cstatus = 0;
383 uint32_t xstatus = 0;
384
385 LOCK(&sc->bmbx_lock);
386
387 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
388 mb_mbx = &mb->mbx;
389
390 /* get the tmo */
391 tmo = mbx->tag[0];
392 mbx->tag[0] = 0;
393
394 /* copy mbx into mbox */
395 bcopy(mbx, mb_mbx, sizeof(struct oce_mbx));
396
397 /* now dispatch */
398 rc = oce_mbox_dispatch(sc, tmo);
399 if (rc == 0) {
400 /*
401 * the command completed successfully. Now get the
402 * completion queue entry
403 */
404 mb_cqe = &mb->cqe;
405 DW_SWAP(u32ptr(&mb_cqe->u0.dw[0]), sizeof(struct oce_mq_cqe));
406
407 /* copy mbox mbx back */
408 bcopy(mb_mbx, mbx, sizeof(struct oce_mbx));
409
410 /* pick up the mailbox status */
411 cstatus = mb_cqe->u0.s.completion_status;
412 xstatus = mb_cqe->u0.s.extended_status;
413
414 /*
415 * store the mbx context in the cqe tag section so that
416 * the upper layer handling the cqe can associate the mbx
417 * with the response
418 */
419 if (cstatus == 0 && mbxctx) {
420 /* save context */
421 mbxctx->mbx = mb_mbx;
422 bcopy(&mbxctx, mb_cqe->u0.s.mq_tag,
423 sizeof(struct oce_mbx_ctx *));
424 }
425 }
426
427 UNLOCK(&sc->bmbx_lock);
428
429 return rc;
430 }
431
432 /**
433 * @brief Function to read the mac address associated with an interface
434 * @param sc software handle to the device
435 * @param if_id interface id to read the address from
436 * @param perm set to 1 if reading the factory mac address.
437 * In this case if_id is ignored
438 * @param type type of the mac address, whether network or storage
439 * @param[out] mac [OUTPUT] pointer to a buffer containing the
440 * mac address when the command succeeds.
441 * @returns 0 on success, EIO on failure
442 */
443 int
oce_read_mac_addr(POCE_SOFTC sc,uint32_t if_id,uint8_t perm,uint8_t type,struct mac_address_format * mac)444 oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id,
445 uint8_t perm, uint8_t type, struct mac_address_format *mac)
446 {
447 struct oce_mbx mbx;
448 struct mbx_query_common_iface_mac *fwcmd;
449 int ret = 0;
450
451 bzero(&mbx, sizeof(struct oce_mbx));
452
453 fwcmd = (struct mbx_query_common_iface_mac *)&mbx.payload;
454 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
455 MBX_SUBSYSTEM_COMMON,
456 OPCODE_COMMON_QUERY_IFACE_MAC,
457 MBX_TIMEOUT_SEC,
458 sizeof(struct mbx_query_common_iface_mac),
459 OCE_MBX_VER_V0);
460
461 fwcmd->params.req.permanent = perm;
462 if (!perm)
463 fwcmd->params.req.if_id = (uint16_t) if_id;
464 else
465 fwcmd->params.req.if_id = 0;
466
467 fwcmd->params.req.type = type;
468
469 mbx.u0.s.embedded = 1;
470 mbx.payload_length = sizeof(struct mbx_query_common_iface_mac);
471 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
472
473 ret = oce_mbox_post(sc, &mbx, NULL);
474 if (!ret)
475 ret = fwcmd->hdr.u0.rsp.status;
476 if (ret) {
477 device_printf(sc->dev,
478 "%s failed - cmd status: %d addi status: %d\n",
479 __FUNCTION__, ret,
480 fwcmd->hdr.u0.rsp.additional_status);
481 goto error;
482 }
483
484 /* copy the mac addres in the output parameter */
485 mac->size_of_struct = fwcmd->params.rsp.mac.size_of_struct;
486 bcopy(&fwcmd->params.rsp.mac.mac_addr[0], &mac->mac_addr[0],
487 mac->size_of_struct);
488 error:
489 return ret;
490 }
491
492 /**
493 * @brief Function to query the fw attributes from the hw
494 * @param sc software handle to the device
495 * @returns 0 on success, EIO on failure
496 */
497 int
oce_get_fw_config(POCE_SOFTC sc)498 oce_get_fw_config(POCE_SOFTC sc)
499 {
500 struct oce_mbx mbx;
501 struct mbx_common_query_fw_config *fwcmd;
502 int ret = 0;
503
504 bzero(&mbx, sizeof(struct oce_mbx));
505
506 fwcmd = (struct mbx_common_query_fw_config *)&mbx.payload;
507 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
508 MBX_SUBSYSTEM_COMMON,
509 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
510 MBX_TIMEOUT_SEC,
511 sizeof(struct mbx_common_query_fw_config),
512 OCE_MBX_VER_V0);
513
514 mbx.u0.s.embedded = 1;
515 mbx.payload_length = sizeof(struct mbx_common_query_fw_config);
516 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
517
518 ret = oce_mbox_post(sc, &mbx, NULL);
519 if (!ret)
520 ret = fwcmd->hdr.u0.rsp.status;
521 if (ret) {
522 device_printf(sc->dev,
523 "%s failed - cmd status: %d addi status: %d\n",
524 __FUNCTION__, ret,
525 fwcmd->hdr.u0.rsp.additional_status);
526 goto error;
527 }
528
529 DW_SWAP(u32ptr(fwcmd), sizeof(struct mbx_common_query_fw_config));
530
531 sc->config_number = HOST_32(fwcmd->params.rsp.config_number);
532 sc->asic_revision = HOST_32(fwcmd->params.rsp.asic_revision);
533 sc->port_id = HOST_32(fwcmd->params.rsp.port_id);
534 sc->function_mode = HOST_32(fwcmd->params.rsp.function_mode);
535 if ((sc->function_mode & (ULP_NIC_MODE | ULP_RDMA_MODE)) ==
536 (ULP_NIC_MODE | ULP_RDMA_MODE)) {
537 sc->rdma_flags = OCE_RDMA_FLAG_SUPPORTED;
538 }
539 sc->function_caps = HOST_32(fwcmd->params.rsp.function_caps);
540
541 if (fwcmd->params.rsp.ulp[0].ulp_mode & ULP_NIC_MODE) {
542 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[0].nic_wq_tot);
543 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[0].lro_rqid_tot);
544 } else {
545 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[1].nic_wq_tot);
546 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[1].lro_rqid_tot);
547 }
548
549 error:
550 return ret;
551
552 }
553
554 /**
555 *
556 * @brief function to create a device interface
557 * @param sc software handle to the device
558 * @param cap_flags capability flags
559 * @param en_flags enable capability flags
560 * @param vlan_tag optional vlan tag to associate with the if
561 * @param mac_addr pointer to a buffer containing the mac address
562 * @param[out] if_id [OUTPUT] pointer to an integer to hold the ID of the
563 interface created
564 * @returns 0 on success, EIO on failure
565 */
566 int
oce_if_create(POCE_SOFTC sc,uint32_t cap_flags,uint32_t en_flags,uint16_t vlan_tag,uint8_t * mac_addr,uint32_t * if_id)567 oce_if_create(POCE_SOFTC sc,
568 uint32_t cap_flags,
569 uint32_t en_flags,
570 uint16_t vlan_tag,
571 uint8_t *mac_addr,
572 uint32_t *if_id)
573 {
574 struct oce_mbx mbx;
575 struct mbx_create_common_iface *fwcmd;
576 int rc = 0;
577
578 bzero(&mbx, sizeof(struct oce_mbx));
579
580 fwcmd = (struct mbx_create_common_iface *)&mbx.payload;
581 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
582 MBX_SUBSYSTEM_COMMON,
583 OPCODE_COMMON_CREATE_IFACE,
584 MBX_TIMEOUT_SEC,
585 sizeof(struct mbx_create_common_iface),
586 OCE_MBX_VER_V0);
587 DW_SWAP(u32ptr(&fwcmd->hdr), sizeof(struct mbx_hdr));
588
589 fwcmd->params.req.version = 0;
590 fwcmd->params.req.cap_flags = LE_32(cap_flags);
591 fwcmd->params.req.enable_flags = LE_32(en_flags);
592 if (mac_addr != NULL) {
593 bcopy(mac_addr, &fwcmd->params.req.mac_addr[0], 6);
594 fwcmd->params.req.vlan_tag.u0.normal.vtag = LE_16(vlan_tag);
595 fwcmd->params.req.mac_invalid = 0;
596 } else {
597 fwcmd->params.req.mac_invalid = 1;
598 }
599
600 mbx.u0.s.embedded = 1;
601 mbx.payload_length = sizeof(struct mbx_create_common_iface);
602 DW_SWAP(u32ptr(&mbx), OCE_BMBX_RHDR_SZ);
603
604 rc = oce_mbox_post(sc, &mbx, NULL);
605 if (!rc)
606 rc = fwcmd->hdr.u0.rsp.status;
607 if (rc) {
608 device_printf(sc->dev,
609 "%s failed - cmd status: %d addi status: %d\n",
610 __FUNCTION__, rc,
611 fwcmd->hdr.u0.rsp.additional_status);
612 goto error;
613 }
614
615 *if_id = HOST_32(fwcmd->params.rsp.if_id);
616
617 if (mac_addr != NULL)
618 sc->pmac_id = HOST_32(fwcmd->params.rsp.pmac_id);
619 error:
620 return rc;
621 }
622
623 /**
624 * @brief Function to delete an interface
625 * @param sc software handle to the device
626 * @param if_id ID of the interface to delete
627 * @returns 0 on success, EIO on failure
628 */
629 int
oce_if_del(POCE_SOFTC sc,uint32_t if_id)630 oce_if_del(POCE_SOFTC sc, uint32_t if_id)
631 {
632 struct oce_mbx mbx;
633 struct mbx_destroy_common_iface *fwcmd;
634 int rc = 0;
635
636 bzero(&mbx, sizeof(struct oce_mbx));
637
638 fwcmd = (struct mbx_destroy_common_iface *)&mbx.payload;
639 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
640 MBX_SUBSYSTEM_COMMON,
641 OPCODE_COMMON_DESTROY_IFACE,
642 MBX_TIMEOUT_SEC,
643 sizeof(struct mbx_destroy_common_iface),
644 OCE_MBX_VER_V0);
645
646 fwcmd->params.req.if_id = if_id;
647
648 mbx.u0.s.embedded = 1;
649 mbx.payload_length = sizeof(struct mbx_destroy_common_iface);
650 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
651
652 rc = oce_mbox_post(sc, &mbx, NULL);
653 if (!rc)
654 rc = fwcmd->hdr.u0.rsp.status;
655 if (rc)
656 device_printf(sc->dev,
657 "%s failed - cmd status: %d addi status: %d\n",
658 __FUNCTION__, rc,
659 fwcmd->hdr.u0.rsp.additional_status);
660 return rc;
661 }
662
663 /**
664 * @brief Function to send the mbx command to configure vlan
665 * @param sc software handle to the device
666 * @param if_id interface identifier index
667 * @param vtag_arr array of vlan tags
668 * @param vtag_cnt number of elements in array
669 * @param untagged boolean TRUE/FLASE
670 * @param enable_promisc flag to enable/disable VLAN promiscuous mode
671 * @returns 0 on success, EIO on failure
672 */
673 int
oce_config_vlan(POCE_SOFTC sc,uint32_t if_id,struct normal_vlan * vtag_arr,uint8_t vtag_cnt,uint32_t untagged,uint32_t enable_promisc)674 oce_config_vlan(POCE_SOFTC sc,
675 uint32_t if_id,
676 struct normal_vlan *vtag_arr,
677 uint8_t vtag_cnt, uint32_t untagged, uint32_t enable_promisc)
678 {
679 struct oce_mbx mbx;
680 struct mbx_common_config_vlan *fwcmd;
681 int rc = 0;
682
683 if (sc->vlans_added > sc->max_vlans)
684 goto vlan_promisc;
685
686 bzero(&mbx, sizeof(struct oce_mbx));
687 fwcmd = (struct mbx_common_config_vlan *)&mbx.payload;
688
689 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
690 MBX_SUBSYSTEM_COMMON,
691 OPCODE_COMMON_CONFIG_IFACE_VLAN,
692 MBX_TIMEOUT_SEC,
693 sizeof(struct mbx_common_config_vlan),
694 OCE_MBX_VER_V0);
695
696 fwcmd->params.req.if_id = (uint8_t) if_id;
697 fwcmd->params.req.promisc = (uint8_t) enable_promisc;
698 fwcmd->params.req.untagged = (uint8_t) untagged;
699 fwcmd->params.req.num_vlans = vtag_cnt;
700
701 if (!enable_promisc) {
702 bcopy(vtag_arr, fwcmd->params.req.tags.normal_vlans,
703 vtag_cnt * sizeof(struct normal_vlan));
704 }
705 mbx.u0.s.embedded = 1;
706 mbx.payload_length = sizeof(struct mbx_common_config_vlan);
707 DW_SWAP(u32ptr(&mbx), (OCE_BMBX_RHDR_SZ + mbx.payload_length));
708
709 rc = oce_mbox_post(sc, &mbx, NULL);
710 if (!rc)
711 rc = fwcmd->hdr.u0.rsp.status;
712 if (rc)
713 device_printf(sc->dev,
714 "%s failed - cmd status: %d addi status: %d\n",
715 __FUNCTION__, rc,
716 fwcmd->hdr.u0.rsp.additional_status);
717
718 goto done;
719
720 vlan_promisc:
721 /* Enable Vlan Promis */
722 oce_rxf_set_promiscuous(sc, (1 << 1));
723 device_printf(sc->dev,"Enabling Vlan Promisc Mode\n");
724 done:
725 return rc;
726
727 }
728
729 /**
730 * @brief Function to set flow control capability in the hardware
731 * @param sc software handle to the device
732 * @param flow_control flow control flags to set
733 * @returns 0 on success, EIO on failure
734 */
735 int
oce_set_flow_control(POCE_SOFTC sc,uint32_t flow_control)736 oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control)
737 {
738 struct oce_mbx mbx;
739 struct mbx_common_get_set_flow_control *fwcmd =
740 (struct mbx_common_get_set_flow_control *)&mbx.payload;
741 int rc;
742
743 bzero(&mbx, sizeof(struct oce_mbx));
744
745 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
746 MBX_SUBSYSTEM_COMMON,
747 OPCODE_COMMON_SET_FLOW_CONTROL,
748 MBX_TIMEOUT_SEC,
749 sizeof(struct mbx_common_get_set_flow_control),
750 OCE_MBX_VER_V0);
751
752 if (flow_control & OCE_FC_TX)
753 fwcmd->tx_flow_control = 1;
754
755 if (flow_control & OCE_FC_RX)
756 fwcmd->rx_flow_control = 1;
757
758 mbx.u0.s.embedded = 1;
759 mbx.payload_length = sizeof(struct mbx_common_get_set_flow_control);
760 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
761
762 rc = oce_mbox_post(sc, &mbx, NULL);
763 if (!rc)
764 rc = fwcmd->hdr.u0.rsp.status;
765 if (rc)
766 device_printf(sc->dev,
767 "%s failed - cmd status: %d addi status: %d\n",
768 __FUNCTION__, rc,
769 fwcmd->hdr.u0.rsp.additional_status);
770 return rc;
771 }
772
773 /**
774 * @brief Initialize the RSS CPU indirection table
775 *
776 * The table is used to choose the queue to place the incomming packets.
777 * Incomming packets are hashed. The lowest bits in the hash result
778 * are used as the index into the CPU indirection table.
779 * Each entry in the table contains the RSS CPU-ID returned by the NIC
780 * create. Based on the CPU ID, the receive completion is routed to
781 * the corresponding RSS CQs. (Non-RSS packets are always completed
782 * on the default (0) CQ).
783 *
784 * @param sc software handle to the device
785 * @param *fwcmd pointer to the rss mbox command
786 * @returns none
787 */
788 static int
oce_rss_itbl_init(POCE_SOFTC sc,struct mbx_config_nic_rss * fwcmd)789 oce_rss_itbl_init(POCE_SOFTC sc, struct mbx_config_nic_rss *fwcmd)
790 {
791 int i = 0, j = 0, rc = 0;
792 uint8_t *tbl = fwcmd->params.req.cputable;
793 struct oce_rq *rq = NULL;
794
795
796 for (j = 0; j < INDIRECTION_TABLE_ENTRIES ; j += (sc->nrqs - 1)) {
797 for_all_rss_queues(sc, rq, i) {
798 if ((j + i) >= INDIRECTION_TABLE_ENTRIES)
799 break;
800 tbl[j + i] = rq->rss_cpuid;
801 }
802 }
803 if (i == 0) {
804 device_printf(sc->dev, "error: Invalid number of RSS RQ's\n");
805 rc = ENXIO;
806
807 }
808
809 /* fill log2 value indicating the size of the CPU table */
810 if (rc == 0)
811 fwcmd->params.req.cpu_tbl_sz_log2 = LE_16(OCE_LOG2(INDIRECTION_TABLE_ENTRIES));
812
813 return rc;
814 }
815
816 /**
817 * @brief Function to set flow control capability in the hardware
818 * @param sc software handle to the device
819 * @param if_id interface id to read the address from
820 * @param enable_rss 0=disable, RSS_ENABLE_xxx flags otherwise
821 * @returns 0 on success, EIO on failure
822 */
823 int
oce_config_nic_rss(POCE_SOFTC sc,uint32_t if_id,uint16_t enable_rss)824 oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss)
825 {
826 int rc;
827 struct oce_mbx mbx;
828 struct mbx_config_nic_rss *fwcmd =
829 (struct mbx_config_nic_rss *)&mbx.payload;
830 int version;
831
832 bzero(&mbx, sizeof(struct oce_mbx));
833
834 if (IS_XE201(sc) || IS_SH(sc)) {
835 version = OCE_MBX_VER_V1;
836 fwcmd->params.req.enable_rss = RSS_ENABLE_UDP_IPV4 |
837 RSS_ENABLE_UDP_IPV6;
838 } else
839 version = OCE_MBX_VER_V0;
840
841 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
842 MBX_SUBSYSTEM_NIC,
843 NIC_CONFIG_RSS,
844 MBX_TIMEOUT_SEC,
845 sizeof(struct mbx_config_nic_rss),
846 version);
847 if (enable_rss)
848 fwcmd->params.req.enable_rss |= (RSS_ENABLE_IPV4 |
849 RSS_ENABLE_TCP_IPV4 |
850 RSS_ENABLE_IPV6 |
851 RSS_ENABLE_TCP_IPV6);
852
853 if(!sc->enable_hwlro)
854 fwcmd->params.req.flush = OCE_FLUSH;
855 else
856 fwcmd->params.req.flush = 0;
857
858 fwcmd->params.req.if_id = LE_32(if_id);
859
860 srandom(arc4random()); /* random entropy seed */
861 read_random(fwcmd->params.req.hash, sizeof(fwcmd->params.req.hash));
862
863 rc = oce_rss_itbl_init(sc, fwcmd);
864 if (rc == 0) {
865 mbx.u0.s.embedded = 1;
866 mbx.payload_length = sizeof(struct mbx_config_nic_rss);
867 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
868
869 rc = oce_mbox_post(sc, &mbx, NULL);
870 if (!rc)
871 rc = fwcmd->hdr.u0.rsp.status;
872 if (rc)
873 device_printf(sc->dev,
874 "%s failed - cmd status: %d addi status: %d\n",
875 __FUNCTION__, rc,
876 fwcmd->hdr.u0.rsp.additional_status);
877 }
878 return rc;
879 }
880
881 /**
882 * @brief RXF function to enable/disable device promiscuous mode
883 * @param sc software handle to the device
884 * @param enable enable/disable flag
885 * @returns 0 on success, EIO on failure
886 * @note
887 * The NIC_CONFIG_PROMISCUOUS command deprecated for Lancer.
888 * This function uses the COMMON_SET_IFACE_RX_FILTER command instead.
889 */
890 int
oce_rxf_set_promiscuous(POCE_SOFTC sc,uint8_t enable)891 oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable)
892 {
893 struct mbx_set_common_iface_rx_filter *fwcmd;
894 int sz = sizeof(struct mbx_set_common_iface_rx_filter);
895 iface_rx_filter_ctx_t *req;
896 OCE_DMA_MEM sgl;
897 int rc;
898
899 /* allocate mbx payload's dma scatter/gather memory */
900 rc = oce_dma_alloc(sc, sz, &sgl, 0);
901 if (rc)
902 return rc;
903
904 fwcmd = OCE_DMAPTR(&sgl, struct mbx_set_common_iface_rx_filter);
905
906 req = &fwcmd->params.req;
907 req->iface_flags_mask = MBX_RX_IFACE_FLAGS_PROMISCUOUS |
908 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
909 /* Bit 0 Mac promisc, Bit 1 Vlan promisc */
910 if (enable & 0x01)
911 req->iface_flags = MBX_RX_IFACE_FLAGS_PROMISCUOUS;
912
913 if (enable & 0x02)
914 req->iface_flags |= MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
915
916 req->if_id = sc->if_id;
917
918 rc = oce_set_common_iface_rx_filter(sc, &sgl);
919 oce_dma_free(sc, &sgl);
920
921 return rc;
922 }
923
924
925 /**
926 * @brief Function modify and select rx filter options
927 * @param sc software handle to the device
928 * @param sgl scatter/gather request/response
929 * @returns 0 on success, error code on failure
930 */
931 int
oce_set_common_iface_rx_filter(POCE_SOFTC sc,POCE_DMA_MEM sgl)932 oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl)
933 {
934 struct oce_mbx mbx;
935 int mbx_sz = sizeof(struct mbx_set_common_iface_rx_filter);
936 struct mbx_set_common_iface_rx_filter *fwcmd;
937 int rc;
938
939 bzero(&mbx, sizeof(struct oce_mbx));
940 fwcmd = OCE_DMAPTR(sgl, struct mbx_set_common_iface_rx_filter);
941
942 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
943 MBX_SUBSYSTEM_COMMON,
944 OPCODE_COMMON_SET_IFACE_RX_FILTER,
945 MBX_TIMEOUT_SEC,
946 mbx_sz,
947 OCE_MBX_VER_V0);
948
949 oce_dma_sync(sgl, BUS_DMASYNC_PREWRITE);
950 mbx.u0.s.embedded = 0;
951 mbx.u0.s.sge_count = 1;
952 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(sgl->paddr);
953 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(sgl->paddr);
954 mbx.payload.u0.u1.sgl[0].length = mbx_sz;
955 mbx.payload_length = mbx_sz;
956 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
957
958 rc = oce_mbox_post(sc, &mbx, NULL);
959 if (!rc)
960 rc = fwcmd->hdr.u0.rsp.status;
961 if (rc)
962 device_printf(sc->dev,
963 "%s failed - cmd status: %d addi status: %d\n",
964 __FUNCTION__, rc,
965 fwcmd->hdr.u0.rsp.additional_status);
966 return rc;
967 }
968
969 /**
970 * @brief Function to query the link status from the hardware
971 * @param sc software handle to the device
972 * @param[out] link pointer to the structure returning link attributes
973 * @returns 0 on success, EIO on failure
974 */
975 int
oce_get_link_status(POCE_SOFTC sc,struct link_status * link)976 oce_get_link_status(POCE_SOFTC sc, struct link_status *link)
977 {
978 struct oce_mbx mbx;
979 struct mbx_query_common_link_config *fwcmd;
980 int rc = 0, version;
981
982 bzero(&mbx, sizeof(struct oce_mbx));
983
984 IS_BE2(sc) ? (version = OCE_MBX_VER_V0) : (version = OCE_MBX_VER_V1);
985
986 fwcmd = (struct mbx_query_common_link_config *)&mbx.payload;
987 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
988 MBX_SUBSYSTEM_COMMON,
989 OPCODE_COMMON_QUERY_LINK_CONFIG,
990 MBX_TIMEOUT_SEC,
991 sizeof(struct mbx_query_common_link_config),
992 version);
993
994 mbx.u0.s.embedded = 1;
995 mbx.payload_length = sizeof(struct mbx_query_common_link_config);
996 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
997
998 rc = oce_mbox_post(sc, &mbx, NULL);
999
1000 if (!rc)
1001 rc = fwcmd->hdr.u0.rsp.status;
1002 if (rc) {
1003 device_printf(sc->dev,
1004 "%s failed - cmd status: %d addi status: %d\n",
1005 __FUNCTION__, rc,
1006 fwcmd->hdr.u0.rsp.additional_status);
1007 goto error;
1008 }
1009 /* interpret response */
1010 link->qos_link_speed = HOST_16(fwcmd->params.rsp.qos_link_speed);
1011 link->phys_port_speed = fwcmd->params.rsp.physical_port_speed;
1012 link->logical_link_status = fwcmd->params.rsp.logical_link_status;
1013 error:
1014 return rc;
1015 }
1016
1017
1018 /**
1019 * @brief Function to get NIC statistics
1020 * @param sc software handle to the device
1021 * @param *stats pointer to where to store statistics
1022 * @param reset_stats resets statistics of set
1023 * @returns 0 on success, EIO on failure
1024 * @note command depricated in Lancer
1025 */
1026 #define OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, version) \
1027 int \
1028 oce_mbox_get_nic_stats_v##version(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem) \
1029 { \
1030 struct oce_mbx mbx; \
1031 struct mbx_get_nic_stats_v##version *fwcmd; \
1032 int rc = 0; \
1033 \
1034 bzero(&mbx, sizeof(struct oce_mbx)); \
1035 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats_v##version); \
1036 bzero(fwcmd, sizeof(*fwcmd)); \
1037 \
1038 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, \
1039 MBX_SUBSYSTEM_NIC, \
1040 NIC_GET_STATS, \
1041 MBX_TIMEOUT_SEC, \
1042 sizeof(*fwcmd), \
1043 OCE_MBX_VER_V##version); \
1044 \
1045 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */ \
1046 mbx.u0.s.sge_count = 1; /* using scatter gather instead */ \
1047 \
1048 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE); \
1049 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr); \
1050 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr); \
1051 mbx.payload.u0.u1.sgl[0].length = sizeof(*fwcmd); \
1052 mbx.payload_length = sizeof(*fwcmd); \
1053 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); \
1054 \
1055 rc = oce_mbox_post(sc, &mbx, NULL); \
1056 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE); \
1057 if (!rc) \
1058 rc = fwcmd->hdr.u0.rsp.status; \
1059 if (rc) \
1060 device_printf(sc->dev, \
1061 "%s failed - cmd status: %d addi status: %d\n", \
1062 __FUNCTION__, rc, \
1063 fwcmd->hdr.u0.rsp.additional_status); \
1064 return rc; \
1065 }
1066
1067 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 0);
1068 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 1);
1069 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 2);
1070
1071
1072 /**
1073 * @brief Function to get pport (physical port) statistics
1074 * @param sc software handle to the device
1075 * @param *stats pointer to where to store statistics
1076 * @param reset_stats resets statistics of set
1077 * @returns 0 on success, EIO on failure
1078 */
1079 int
oce_mbox_get_pport_stats(POCE_SOFTC sc,POCE_DMA_MEM pstats_dma_mem,uint32_t reset_stats)1080 oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1081 uint32_t reset_stats)
1082 {
1083 struct oce_mbx mbx;
1084 struct mbx_get_pport_stats *fwcmd;
1085 int rc = 0;
1086
1087 bzero(&mbx, sizeof(struct oce_mbx));
1088 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_pport_stats);
1089 bzero(fwcmd, sizeof(struct mbx_get_pport_stats));
1090
1091 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1092 MBX_SUBSYSTEM_NIC,
1093 NIC_GET_PPORT_STATS,
1094 MBX_TIMEOUT_SEC,
1095 sizeof(struct mbx_get_pport_stats),
1096 OCE_MBX_VER_V0);
1097
1098 fwcmd->params.req.reset_stats = reset_stats;
1099 fwcmd->params.req.port_number = sc->port_id;
1100
1101 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1102 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1103
1104 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1105 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1106 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1107 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_pport_stats);
1108
1109 mbx.payload_length = sizeof(struct mbx_get_pport_stats);
1110 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1111
1112 rc = oce_mbox_post(sc, &mbx, NULL);
1113 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1114
1115 if (!rc)
1116 rc = fwcmd->hdr.u0.rsp.status;
1117 if (rc)
1118 device_printf(sc->dev,
1119 "%s failed - cmd status: %d addi status: %d\n",
1120 __FUNCTION__, rc,
1121 fwcmd->hdr.u0.rsp.additional_status);
1122 return rc;
1123 }
1124
1125
1126 /**
1127 * @brief Function to get vport (virtual port) statistics
1128 * @param sc software handle to the device
1129 * @param *stats pointer to where to store statistics
1130 * @param reset_stats resets statistics of set
1131 * @returns 0 on success, EIO on failure
1132 */
1133 int
oce_mbox_get_vport_stats(POCE_SOFTC sc,POCE_DMA_MEM pstats_dma_mem,uint32_t req_size,uint32_t reset_stats)1134 oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1135 uint32_t req_size, uint32_t reset_stats)
1136 {
1137 struct oce_mbx mbx;
1138 struct mbx_get_vport_stats *fwcmd;
1139 int rc = 0;
1140
1141 bzero(&mbx, sizeof(struct oce_mbx));
1142
1143 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_vport_stats);
1144 bzero(fwcmd, sizeof(struct mbx_get_vport_stats));
1145
1146 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1147 MBX_SUBSYSTEM_NIC,
1148 NIC_GET_VPORT_STATS,
1149 MBX_TIMEOUT_SEC,
1150 sizeof(struct mbx_get_vport_stats),
1151 OCE_MBX_VER_V0);
1152
1153 fwcmd->params.req.reset_stats = reset_stats;
1154 fwcmd->params.req.vport_number = sc->if_id;
1155
1156 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1157 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1158
1159 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1160 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1161 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1162 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_vport_stats);
1163
1164 mbx.payload_length = sizeof(struct mbx_get_vport_stats);
1165 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1166
1167 rc = oce_mbox_post(sc, &mbx, NULL);
1168 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1169
1170 if (!rc)
1171 rc = fwcmd->hdr.u0.rsp.status;
1172 if (rc)
1173 device_printf(sc->dev,
1174 "%s failed - cmd status: %d addi status: %d\n",
1175 __FUNCTION__, rc,
1176 fwcmd->hdr.u0.rsp.additional_status);
1177 return rc;
1178 }
1179
1180
1181 /**
1182 * @brief Function to update the muticast filter with
1183 * values in dma_mem
1184 * @param sc software handle to the device
1185 * @param dma_mem pointer to dma memory region
1186 * @returns 0 on success, EIO on failure
1187 */
1188 int
oce_update_multicast(POCE_SOFTC sc,POCE_DMA_MEM pdma_mem)1189 oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem)
1190 {
1191 struct oce_mbx mbx;
1192 struct oce_mq_sge *sgl;
1193 struct mbx_set_common_iface_multicast *req = NULL;
1194 int rc = 0;
1195
1196 req = OCE_DMAPTR(pdma_mem, struct mbx_set_common_iface_multicast);
1197 mbx_common_req_hdr_init(&req->hdr, 0, 0,
1198 MBX_SUBSYSTEM_COMMON,
1199 OPCODE_COMMON_SET_IFACE_MULTICAST,
1200 MBX_TIMEOUT_SEC,
1201 sizeof(struct mbx_set_common_iface_multicast),
1202 OCE_MBX_VER_V0);
1203
1204 bzero(&mbx, sizeof(struct oce_mbx));
1205
1206 mbx.u0.s.embedded = 0; /*Non embeded*/
1207 mbx.payload_length = sizeof(struct mbx_set_common_iface_multicast);
1208 mbx.u0.s.sge_count = 1;
1209 sgl = &mbx.payload.u0.u1.sgl[0];
1210 sgl->pa_hi = htole32(upper_32_bits(pdma_mem->paddr));
1211 sgl->pa_lo = htole32((pdma_mem->paddr) & 0xFFFFFFFF);
1212 sgl->length = htole32(mbx.payload_length);
1213
1214 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1215
1216 rc = oce_mbox_post(sc, &mbx, NULL);
1217 if (!rc)
1218 rc = req->hdr.u0.rsp.status;
1219 if (rc)
1220 device_printf(sc->dev,
1221 "%s failed - cmd status: %d addi status: %d\n",
1222 __FUNCTION__, rc,
1223 req->hdr.u0.rsp.additional_status);
1224 return rc;
1225 }
1226
1227
1228 /**
1229 * @brief Function to send passthrough Ioctls
1230 * @param sc software handle to the device
1231 * @param dma_mem pointer to dma memory region
1232 * @param req_size size of dma_mem
1233 * @returns 0 on success, EIO on failure
1234 */
1235 int
oce_pass_through_mbox(POCE_SOFTC sc,POCE_DMA_MEM dma_mem,uint32_t req_size)1236 oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size)
1237 {
1238 struct oce_mbx mbx;
1239 struct oce_mq_sge *sgl;
1240 int rc = 0;
1241
1242 bzero(&mbx, sizeof(struct oce_mbx));
1243
1244 mbx.u0.s.embedded = 0; /*Non embeded*/
1245 mbx.payload_length = req_size;
1246 mbx.u0.s.sge_count = 1;
1247 sgl = &mbx.payload.u0.u1.sgl[0];
1248 sgl->pa_hi = htole32(upper_32_bits(dma_mem->paddr));
1249 sgl->pa_lo = htole32((dma_mem->paddr) & 0xFFFFFFFF);
1250 sgl->length = htole32(req_size);
1251
1252 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1253
1254 rc = oce_mbox_post(sc, &mbx, NULL);
1255 return rc;
1256 }
1257
1258
1259 int
oce_mbox_macaddr_add(POCE_SOFTC sc,uint8_t * mac_addr,uint32_t if_id,uint32_t * pmac_id)1260 oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr,
1261 uint32_t if_id, uint32_t *pmac_id)
1262 {
1263 struct oce_mbx mbx;
1264 struct mbx_add_common_iface_mac *fwcmd;
1265 int rc = 0;
1266
1267 bzero(&mbx, sizeof(struct oce_mbx));
1268
1269 fwcmd = (struct mbx_add_common_iface_mac *)&mbx.payload;
1270 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1271 MBX_SUBSYSTEM_COMMON,
1272 OPCODE_COMMON_ADD_IFACE_MAC,
1273 MBX_TIMEOUT_SEC,
1274 sizeof(struct mbx_add_common_iface_mac),
1275 OCE_MBX_VER_V0);
1276
1277 fwcmd->params.req.if_id = (uint16_t) if_id;
1278 bcopy(mac_addr, fwcmd->params.req.mac_address, 6);
1279
1280 mbx.u0.s.embedded = 1;
1281 mbx.payload_length = sizeof(struct mbx_add_common_iface_mac);
1282 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1283 rc = oce_mbox_post(sc, &mbx, NULL);
1284 if (!rc)
1285 rc = fwcmd->hdr.u0.rsp.status;
1286 if (rc) {
1287 device_printf(sc->dev,
1288 "%s failed - cmd status: %d addi status: %d\n",
1289 __FUNCTION__, rc,
1290 fwcmd->hdr.u0.rsp.additional_status);
1291 goto error;
1292 }
1293 *pmac_id = fwcmd->params.rsp.pmac_id;
1294 error:
1295 return rc;
1296 }
1297
1298
1299 int
oce_mbox_macaddr_del(POCE_SOFTC sc,uint32_t if_id,uint32_t pmac_id)1300 oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id)
1301 {
1302 struct oce_mbx mbx;
1303 struct mbx_del_common_iface_mac *fwcmd;
1304 int rc = 0;
1305
1306 bzero(&mbx, sizeof(struct oce_mbx));
1307
1308 fwcmd = (struct mbx_del_common_iface_mac *)&mbx.payload;
1309 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1310 MBX_SUBSYSTEM_COMMON,
1311 OPCODE_COMMON_DEL_IFACE_MAC,
1312 MBX_TIMEOUT_SEC,
1313 sizeof(struct mbx_del_common_iface_mac),
1314 OCE_MBX_VER_V0);
1315
1316 fwcmd->params.req.if_id = (uint16_t)if_id;
1317 fwcmd->params.req.pmac_id = pmac_id;
1318
1319 mbx.u0.s.embedded = 1;
1320 mbx.payload_length = sizeof(struct mbx_del_common_iface_mac);
1321 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1322
1323 rc = oce_mbox_post(sc, &mbx, NULL);
1324 if (!rc)
1325 rc = fwcmd->hdr.u0.rsp.status;
1326 if (rc)
1327 device_printf(sc->dev,
1328 "%s failed - cmd status: %d addi status: %d\n",
1329 __FUNCTION__, rc,
1330 fwcmd->hdr.u0.rsp.additional_status);
1331 return rc;
1332 }
1333
1334
1335
1336 int
oce_mbox_check_native_mode(POCE_SOFTC sc)1337 oce_mbox_check_native_mode(POCE_SOFTC sc)
1338 {
1339 struct oce_mbx mbx;
1340 struct mbx_common_set_function_cap *fwcmd;
1341 int rc = 0;
1342
1343 bzero(&mbx, sizeof(struct oce_mbx));
1344
1345 fwcmd = (struct mbx_common_set_function_cap *)&mbx.payload;
1346 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1347 MBX_SUBSYSTEM_COMMON,
1348 OPCODE_COMMON_SET_FUNCTIONAL_CAPS,
1349 MBX_TIMEOUT_SEC,
1350 sizeof(struct mbx_common_set_function_cap),
1351 OCE_MBX_VER_V0);
1352
1353 fwcmd->params.req.valid_capability_flags = CAP_SW_TIMESTAMPS |
1354 CAP_BE3_NATIVE_ERX_API;
1355
1356 fwcmd->params.req.capability_flags = CAP_BE3_NATIVE_ERX_API;
1357
1358 mbx.u0.s.embedded = 1;
1359 mbx.payload_length = sizeof(struct mbx_common_set_function_cap);
1360 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1361
1362 rc = oce_mbox_post(sc, &mbx, NULL);
1363 if (!rc)
1364 rc = fwcmd->hdr.u0.rsp.status;
1365 if (rc) {
1366 device_printf(sc->dev,
1367 "%s failed - cmd status: %d addi status: %d\n",
1368 __FUNCTION__, rc,
1369 fwcmd->hdr.u0.rsp.additional_status);
1370 goto error;
1371 }
1372 sc->be3_native = HOST_32(fwcmd->params.rsp.capability_flags)
1373 & CAP_BE3_NATIVE_ERX_API;
1374
1375 error:
1376 return 0;
1377 }
1378
1379
1380
1381 int
oce_mbox_cmd_set_loopback(POCE_SOFTC sc,uint8_t port_num,uint8_t loopback_type,uint8_t enable)1382 oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num,
1383 uint8_t loopback_type, uint8_t enable)
1384 {
1385 struct oce_mbx mbx;
1386 struct mbx_lowlevel_set_loopback_mode *fwcmd;
1387 int rc = 0;
1388
1389
1390 bzero(&mbx, sizeof(struct oce_mbx));
1391
1392 fwcmd = (struct mbx_lowlevel_set_loopback_mode *)&mbx.payload;
1393 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1394 MBX_SUBSYSTEM_LOWLEVEL,
1395 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1396 MBX_TIMEOUT_SEC,
1397 sizeof(struct mbx_lowlevel_set_loopback_mode),
1398 OCE_MBX_VER_V0);
1399
1400 fwcmd->params.req.src_port = port_num;
1401 fwcmd->params.req.dest_port = port_num;
1402 fwcmd->params.req.loopback_type = loopback_type;
1403 fwcmd->params.req.loopback_state = enable;
1404
1405 mbx.u0.s.embedded = 1;
1406 mbx.payload_length = sizeof(struct mbx_lowlevel_set_loopback_mode);
1407 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1408
1409 rc = oce_mbox_post(sc, &mbx, NULL);
1410 if (!rc)
1411 rc = fwcmd->hdr.u0.rsp.status;
1412 if (rc)
1413 device_printf(sc->dev,
1414 "%s failed - cmd status: %d addi status: %d\n",
1415 __FUNCTION__, rc,
1416 fwcmd->hdr.u0.rsp.additional_status);
1417
1418 return rc;
1419
1420 }
1421
1422 int
oce_mbox_cmd_test_loopback(POCE_SOFTC sc,uint32_t port_num,uint32_t loopback_type,uint32_t pkt_size,uint32_t num_pkts,uint64_t pattern)1423 oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num,
1424 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts,
1425 uint64_t pattern)
1426 {
1427
1428 struct oce_mbx mbx;
1429 struct mbx_lowlevel_test_loopback_mode *fwcmd;
1430 int rc = 0;
1431
1432
1433 bzero(&mbx, sizeof(struct oce_mbx));
1434
1435 fwcmd = (struct mbx_lowlevel_test_loopback_mode *)&mbx.payload;
1436 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1437 MBX_SUBSYSTEM_LOWLEVEL,
1438 OPCODE_LOWLEVEL_TEST_LOOPBACK,
1439 MBX_TIMEOUT_SEC,
1440 sizeof(struct mbx_lowlevel_test_loopback_mode),
1441 OCE_MBX_VER_V0);
1442
1443 fwcmd->params.req.pattern = pattern;
1444 fwcmd->params.req.src_port = port_num;
1445 fwcmd->params.req.dest_port = port_num;
1446 fwcmd->params.req.pkt_size = pkt_size;
1447 fwcmd->params.req.num_pkts = num_pkts;
1448 fwcmd->params.req.loopback_type = loopback_type;
1449
1450 mbx.u0.s.embedded = 1;
1451 mbx.payload_length = sizeof(struct mbx_lowlevel_test_loopback_mode);
1452 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1453
1454 rc = oce_mbox_post(sc, &mbx, NULL);
1455 if (!rc)
1456 rc = fwcmd->hdr.u0.rsp.status;
1457 if (rc)
1458 device_printf(sc->dev,
1459 "%s failed - cmd status: %d addi status: %d\n",
1460 __FUNCTION__, rc,
1461 fwcmd->hdr.u0.rsp.additional_status);
1462
1463 return rc;
1464 }
1465
1466 int
oce_mbox_write_flashrom(POCE_SOFTC sc,uint32_t optype,uint32_t opcode,POCE_DMA_MEM pdma_mem,uint32_t num_bytes)1467 oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode,
1468 POCE_DMA_MEM pdma_mem, uint32_t num_bytes)
1469 {
1470
1471 struct oce_mbx mbx;
1472 struct oce_mq_sge *sgl = NULL;
1473 struct mbx_common_read_write_flashrom *fwcmd = NULL;
1474 int rc = 0, payload_len = 0;
1475
1476 bzero(&mbx, sizeof(struct oce_mbx));
1477 fwcmd = OCE_DMAPTR(pdma_mem, struct mbx_common_read_write_flashrom);
1478 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 32*1024;
1479
1480 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1481 MBX_SUBSYSTEM_COMMON,
1482 OPCODE_COMMON_WRITE_FLASHROM,
1483 LONG_TIMEOUT,
1484 payload_len,
1485 OCE_MBX_VER_V0);
1486
1487 fwcmd->flash_op_type = LE_32(optype);
1488 fwcmd->flash_op_code = LE_32(opcode);
1489 fwcmd->data_buffer_size = LE_32(num_bytes);
1490
1491 mbx.u0.s.embedded = 0; /*Non embeded*/
1492 mbx.payload_length = payload_len;
1493 mbx.u0.s.sge_count = 1;
1494
1495 sgl = &mbx.payload.u0.u1.sgl[0];
1496 sgl->pa_hi = upper_32_bits(pdma_mem->paddr);
1497 sgl->pa_lo = pdma_mem->paddr & 0xFFFFFFFF;
1498 sgl->length = payload_len;
1499
1500 /* post the command */
1501 rc = oce_mbox_post(sc, &mbx, NULL);
1502 if (!rc)
1503 rc = fwcmd->hdr.u0.rsp.status;
1504 if (rc)
1505 device_printf(sc->dev,
1506 "%s failed - cmd status: %d addi status: %d\n",
1507 __FUNCTION__, rc,
1508 fwcmd->hdr.u0.rsp.additional_status);
1509
1510 return rc;
1511
1512 }
1513
1514 int
oce_mbox_get_flashrom_crc(POCE_SOFTC sc,uint8_t * flash_crc,uint32_t offset,uint32_t optype)1515 oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc,
1516 uint32_t offset, uint32_t optype)
1517 {
1518
1519 int rc = 0, payload_len = 0;
1520 struct oce_mbx mbx;
1521 struct mbx_common_read_write_flashrom *fwcmd;
1522
1523 bzero(&mbx, sizeof(struct oce_mbx));
1524
1525 fwcmd = (struct mbx_common_read_write_flashrom *)&mbx.payload;
1526
1527 /* Firmware requires extra 4 bytes with this ioctl. Since there
1528 is enough room in the mbx payload it should be good enough
1529 Reference: Bug 14853
1530 */
1531 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 4;
1532
1533 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1534 MBX_SUBSYSTEM_COMMON,
1535 OPCODE_COMMON_READ_FLASHROM,
1536 MBX_TIMEOUT_SEC,
1537 payload_len,
1538 OCE_MBX_VER_V0);
1539
1540 fwcmd->flash_op_type = optype;
1541 fwcmd->flash_op_code = FLASHROM_OPER_REPORT;
1542 fwcmd->data_offset = offset;
1543 fwcmd->data_buffer_size = 0x4;
1544
1545 mbx.u0.s.embedded = 1;
1546 mbx.payload_length = payload_len;
1547
1548 /* post the command */
1549 rc = oce_mbox_post(sc, &mbx, NULL);
1550 if (!rc)
1551 rc = fwcmd->hdr.u0.rsp.status;
1552 if (rc) {
1553 device_printf(sc->dev,
1554 "%s failed - cmd status: %d addi status: %d\n",
1555 __FUNCTION__, rc,
1556 fwcmd->hdr.u0.rsp.additional_status);
1557 goto error;
1558 }
1559 bcopy(fwcmd->data_buffer, flash_crc, 4);
1560 error:
1561 return rc;
1562 }
1563
1564 int
oce_mbox_get_phy_info(POCE_SOFTC sc,struct oce_phy_info * phy_info)1565 oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info)
1566 {
1567
1568 struct oce_mbx mbx;
1569 struct mbx_common_phy_info *fwcmd;
1570 int rc = 0;
1571
1572 bzero(&mbx, sizeof(struct oce_mbx));
1573
1574 fwcmd = (struct mbx_common_phy_info *)&mbx.payload;
1575 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1576 MBX_SUBSYSTEM_COMMON,
1577 OPCODE_COMMON_GET_PHY_CONFIG,
1578 MBX_TIMEOUT_SEC,
1579 sizeof(struct mbx_common_phy_info),
1580 OCE_MBX_VER_V0);
1581
1582 mbx.u0.s.embedded = 1;
1583 mbx.payload_length = sizeof(struct mbx_common_phy_info);
1584
1585 /* now post the command */
1586 rc = oce_mbox_post(sc, &mbx, NULL);
1587 if (!rc)
1588 rc = fwcmd->hdr.u0.rsp.status;
1589 if (rc) {
1590 device_printf(sc->dev,
1591 "%s failed - cmd status: %d addi status: %d\n",
1592 __FUNCTION__, rc,
1593 fwcmd->hdr.u0.rsp.additional_status);
1594 goto error;
1595 }
1596 phy_info->phy_type = HOST_16(fwcmd->params.rsp.phy_info.phy_type);
1597 phy_info->interface_type =
1598 HOST_16(fwcmd->params.rsp.phy_info.interface_type);
1599 phy_info->auto_speeds_supported =
1600 HOST_16(fwcmd->params.rsp.phy_info.auto_speeds_supported);
1601 phy_info->fixed_speeds_supported =
1602 HOST_16(fwcmd->params.rsp.phy_info.fixed_speeds_supported);
1603 phy_info->misc_params = HOST_32(fwcmd->params.rsp.phy_info.misc_params);
1604 error:
1605 return rc;
1606
1607 }
1608
1609
1610 int
oce_mbox_lancer_write_flashrom(POCE_SOFTC sc,uint32_t data_size,uint32_t data_offset,POCE_DMA_MEM pdma_mem,uint32_t * written_data,uint32_t * additional_status)1611 oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size,
1612 uint32_t data_offset, POCE_DMA_MEM pdma_mem,
1613 uint32_t *written_data, uint32_t *additional_status)
1614 {
1615
1616 struct oce_mbx mbx;
1617 struct mbx_lancer_common_write_object *fwcmd = NULL;
1618 int rc = 0, payload_len = 0;
1619
1620 bzero(&mbx, sizeof(struct oce_mbx));
1621 payload_len = sizeof(struct mbx_lancer_common_write_object);
1622
1623 mbx.u0.s.embedded = 1;/* Embedded */
1624 mbx.payload_length = payload_len;
1625 fwcmd = (struct mbx_lancer_common_write_object *)&mbx.payload;
1626
1627 /* initialize the ioctl header */
1628 mbx_common_req_hdr_init(&fwcmd->params.req.hdr, 0, 0,
1629 MBX_SUBSYSTEM_COMMON,
1630 OPCODE_COMMON_WRITE_OBJECT,
1631 LONG_TIMEOUT,
1632 payload_len,
1633 OCE_MBX_VER_V0);
1634
1635 fwcmd->params.req.write_length = data_size;
1636 if (data_size == 0)
1637 fwcmd->params.req.eof = 1;
1638 else
1639 fwcmd->params.req.eof = 0;
1640
1641 strcpy(fwcmd->params.req.object_name, "/prg");
1642 fwcmd->params.req.descriptor_count = 1;
1643 fwcmd->params.req.write_offset = data_offset;
1644 fwcmd->params.req.buffer_length = data_size;
1645 fwcmd->params.req.address_lower = pdma_mem->paddr & 0xFFFFFFFF;
1646 fwcmd->params.req.address_upper = upper_32_bits(pdma_mem->paddr);
1647
1648 /* post the command */
1649 rc = oce_mbox_post(sc, &mbx, NULL);
1650 if (!rc)
1651 rc = fwcmd->params.rsp.status;
1652 if (rc) {
1653 device_printf(sc->dev,
1654 "%s failed - cmd status: %d addi status: %d\n",
1655 __FUNCTION__, rc,
1656 fwcmd->params.rsp.additional_status);
1657 goto error;
1658 }
1659 *written_data = HOST_32(fwcmd->params.rsp.actual_write_length);
1660 *additional_status = fwcmd->params.rsp.additional_status;
1661 error:
1662 return rc;
1663
1664 }
1665
1666
1667
1668 int
oce_mbox_create_rq(struct oce_rq * rq)1669 oce_mbox_create_rq(struct oce_rq *rq)
1670 {
1671
1672 struct oce_mbx mbx;
1673 struct mbx_create_nic_rq *fwcmd;
1674 POCE_SOFTC sc = rq->parent;
1675 int rc, num_pages = 0;
1676
1677 if (rq->qstate == QCREATED)
1678 return 0;
1679
1680 bzero(&mbx, sizeof(struct oce_mbx));
1681
1682 fwcmd = (struct mbx_create_nic_rq *)&mbx.payload;
1683 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1684 MBX_SUBSYSTEM_NIC,
1685 NIC_CREATE_RQ, MBX_TIMEOUT_SEC,
1686 sizeof(struct mbx_create_nic_rq),
1687 OCE_MBX_VER_V0);
1688
1689 /* oce_page_list will also prepare pages */
1690 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]);
1691
1692 if (IS_XE201(sc)) {
1693 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048;
1694 fwcmd->params.req.page_size = 1;
1695 fwcmd->hdr.u0.req.version = OCE_MBX_VER_V1;
1696 } else
1697 fwcmd->params.req.frag_size = OCE_LOG2(rq->cfg.frag_size);
1698 fwcmd->params.req.num_pages = num_pages;
1699 fwcmd->params.req.cq_id = rq->cq->cq_id;
1700 fwcmd->params.req.if_id = sc->if_id;
1701 fwcmd->params.req.max_frame_size = rq->cfg.mtu;
1702 fwcmd->params.req.is_rss_queue = rq->cfg.is_rss_queue;
1703
1704 mbx.u0.s.embedded = 1;
1705 mbx.payload_length = sizeof(struct mbx_create_nic_rq);
1706
1707 rc = oce_mbox_post(sc, &mbx, NULL);
1708 if (!rc)
1709 rc = fwcmd->hdr.u0.rsp.status;
1710 if (rc) {
1711 device_printf(sc->dev,
1712 "%s failed - cmd status: %d addi status: %d\n",
1713 __FUNCTION__, rc,
1714 fwcmd->hdr.u0.rsp.additional_status);
1715 goto error;
1716 }
1717 rq->rq_id = HOST_16(fwcmd->params.rsp.rq_id);
1718 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid;
1719 error:
1720 return rc;
1721
1722 }
1723
1724
1725
1726 int
oce_mbox_create_wq(struct oce_wq * wq)1727 oce_mbox_create_wq(struct oce_wq *wq)
1728 {
1729 struct oce_mbx mbx;
1730 struct mbx_create_nic_wq *fwcmd;
1731 POCE_SOFTC sc = wq->parent;
1732 int rc = 0, version, num_pages;
1733
1734 bzero(&mbx, sizeof(struct oce_mbx));
1735
1736 fwcmd = (struct mbx_create_nic_wq *)&mbx.payload;
1737 if (IS_XE201(sc))
1738 version = OCE_MBX_VER_V1;
1739 else if(IS_BE(sc))
1740 IS_PROFILE_SUPER_NIC(sc) ? (version = OCE_MBX_VER_V2)
1741 : (version = OCE_MBX_VER_V0);
1742 else
1743 version = OCE_MBX_VER_V2;
1744
1745 if (version > OCE_MBX_VER_V0)
1746 fwcmd->params.req.if_id = sc->if_id;
1747
1748 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1749 MBX_SUBSYSTEM_NIC,
1750 NIC_CREATE_WQ, MBX_TIMEOUT_SEC,
1751 sizeof(struct mbx_create_nic_wq),
1752 version);
1753
1754 num_pages = oce_page_list(wq->ring, &fwcmd->params.req.pages[0]);
1755
1756 fwcmd->params.req.nic_wq_type = wq->cfg.wq_type;
1757 fwcmd->params.req.num_pages = num_pages;
1758 fwcmd->params.req.wq_size = OCE_LOG2(wq->cfg.q_len) + 1;
1759 fwcmd->params.req.cq_id = wq->cq->cq_id;
1760 fwcmd->params.req.ulp_num = 1;
1761
1762 mbx.u0.s.embedded = 1;
1763 mbx.payload_length = sizeof(struct mbx_create_nic_wq);
1764
1765 rc = oce_mbox_post(sc, &mbx, NULL);
1766 if (!rc)
1767 rc = fwcmd->hdr.u0.rsp.status;
1768 if (rc) {
1769 device_printf(sc->dev,
1770 "%s failed - cmd status: %d addi status: %d\n",
1771 __FUNCTION__, rc,
1772 fwcmd->hdr.u0.rsp.additional_status);
1773 goto error;
1774 }
1775 wq->wq_id = HOST_16(fwcmd->params.rsp.wq_id);
1776 if (version == OCE_MBX_VER_V2)
1777 wq->db_offset = HOST_32(fwcmd->params.rsp.db_offset);
1778 else
1779 wq->db_offset = PD_TXULP_DB;
1780 error:
1781 return rc;
1782
1783 }
1784
1785
1786
1787 int
oce_mbox_create_eq(struct oce_eq * eq)1788 oce_mbox_create_eq(struct oce_eq *eq)
1789 {
1790 struct oce_mbx mbx;
1791 struct mbx_create_common_eq *fwcmd;
1792 POCE_SOFTC sc = eq->parent;
1793 int rc = 0;
1794 uint32_t num_pages;
1795
1796 bzero(&mbx, sizeof(struct oce_mbx));
1797
1798 fwcmd = (struct mbx_create_common_eq *)&mbx.payload;
1799
1800 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1801 MBX_SUBSYSTEM_COMMON,
1802 OPCODE_COMMON_CREATE_EQ, MBX_TIMEOUT_SEC,
1803 sizeof(struct mbx_create_common_eq),
1804 OCE_MBX_VER_V0);
1805
1806 num_pages = oce_page_list(eq->ring, &fwcmd->params.req.pages[0]);
1807 fwcmd->params.req.ctx.num_pages = num_pages;
1808 fwcmd->params.req.ctx.valid = 1;
1809 fwcmd->params.req.ctx.size = (eq->eq_cfg.item_size == 4) ? 0 : 1;
1810 fwcmd->params.req.ctx.count = OCE_LOG2(eq->eq_cfg.q_len / 256);
1811 fwcmd->params.req.ctx.armed = 0;
1812 fwcmd->params.req.ctx.delay_mult = eq->eq_cfg.cur_eqd;
1813
1814
1815 mbx.u0.s.embedded = 1;
1816 mbx.payload_length = sizeof(struct mbx_create_common_eq);
1817
1818 rc = oce_mbox_post(sc, &mbx, NULL);
1819 if (!rc)
1820 rc = fwcmd->hdr.u0.rsp.status;
1821 if (rc) {
1822 device_printf(sc->dev,
1823 "%s failed - cmd status: %d addi status: %d\n",
1824 __FUNCTION__, rc,
1825 fwcmd->hdr.u0.rsp.additional_status);
1826 goto error;
1827 }
1828 eq->eq_id = HOST_16(fwcmd->params.rsp.eq_id);
1829 error:
1830 return rc;
1831 }
1832
1833
1834
1835 int
oce_mbox_cq_create(struct oce_cq * cq,uint32_t ncoalesce,uint32_t is_eventable)1836 oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, uint32_t is_eventable)
1837 {
1838 struct oce_mbx mbx;
1839 struct mbx_create_common_cq *fwcmd;
1840 POCE_SOFTC sc = cq->parent;
1841 uint8_t version;
1842 oce_cq_ctx_t *ctx;
1843 uint32_t num_pages, page_size;
1844 int rc = 0;
1845
1846
1847 bzero(&mbx, sizeof(struct oce_mbx));
1848
1849 fwcmd = (struct mbx_create_common_cq *)&mbx.payload;
1850
1851 if (IS_XE201(sc))
1852 version = OCE_MBX_VER_V2;
1853 else
1854 version = OCE_MBX_VER_V0;
1855
1856 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1857 MBX_SUBSYSTEM_COMMON,
1858 OPCODE_COMMON_CREATE_CQ,
1859 MBX_TIMEOUT_SEC,
1860 sizeof(struct mbx_create_common_cq),
1861 version);
1862
1863 ctx = &fwcmd->params.req.cq_ctx;
1864
1865 num_pages = oce_page_list(cq->ring, &fwcmd->params.req.pages[0]);
1866 page_size = 1; /* 1 for 4K */
1867
1868 if (version == OCE_MBX_VER_V2) {
1869 ctx->v2.num_pages = LE_16(num_pages);
1870 ctx->v2.page_size = page_size;
1871 ctx->v2.eventable = is_eventable;
1872 ctx->v2.valid = 1;
1873 ctx->v2.count = OCE_LOG2(cq->cq_cfg.q_len / 256);
1874 ctx->v2.nodelay = cq->cq_cfg.nodelay;
1875 ctx->v2.coalesce_wm = ncoalesce;
1876 ctx->v2.armed = 0;
1877 ctx->v2.eq_id = cq->eq->eq_id;
1878 if (ctx->v2.count == 3) {
1879 if ((u_int)cq->cq_cfg.q_len > (4*1024)-1)
1880 ctx->v2.cqe_count = (4*1024)-1;
1881 else
1882 ctx->v2.cqe_count = cq->cq_cfg.q_len;
1883 }
1884 } else {
1885 ctx->v0.num_pages = LE_16(num_pages);
1886 ctx->v0.eventable = is_eventable;
1887 ctx->v0.valid = 1;
1888 ctx->v0.count = OCE_LOG2(cq->cq_cfg.q_len / 256);
1889 ctx->v0.nodelay = cq->cq_cfg.nodelay;
1890 ctx->v0.coalesce_wm = ncoalesce;
1891 ctx->v0.armed = 0;
1892 ctx->v0.eq_id = cq->eq->eq_id;
1893 }
1894
1895 mbx.u0.s.embedded = 1;
1896 mbx.payload_length = sizeof(struct mbx_create_common_cq);
1897
1898 rc = oce_mbox_post(sc, &mbx, NULL);
1899 if (!rc)
1900 rc = fwcmd->hdr.u0.rsp.status;
1901 if (rc) {
1902 device_printf(sc->dev,
1903 "%s failed - cmd status: %d addi status: %d\n",
1904 __FUNCTION__, rc,
1905 fwcmd->hdr.u0.rsp.additional_status);
1906 goto error;
1907 }
1908 cq->cq_id = HOST_16(fwcmd->params.rsp.cq_id);
1909 error:
1910 return rc;
1911
1912 }
1913
1914 int
oce_mbox_read_transrecv_data(POCE_SOFTC sc,uint32_t page_num)1915 oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num)
1916 {
1917 int rc = 0;
1918 struct oce_mbx mbx;
1919 struct mbx_read_common_transrecv_data *fwcmd;
1920 struct oce_mq_sge *sgl;
1921 OCE_DMA_MEM dma;
1922
1923 /* Allocate DMA mem*/
1924 if (oce_dma_alloc(sc, sizeof(struct mbx_read_common_transrecv_data),
1925 &dma, 0))
1926 return ENOMEM;
1927
1928 fwcmd = OCE_DMAPTR(&dma, struct mbx_read_common_transrecv_data);
1929 bzero(fwcmd, sizeof(struct mbx_read_common_transrecv_data));
1930
1931 bzero(&mbx, sizeof(struct oce_mbx));
1932 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1933 MBX_SUBSYSTEM_COMMON,
1934 OPCODE_COMMON_READ_TRANSRECEIVER_DATA,
1935 MBX_TIMEOUT_SEC,
1936 sizeof(struct mbx_read_common_transrecv_data),
1937 OCE_MBX_VER_V0);
1938
1939 /* fill rest of mbx */
1940 mbx.u0.s.embedded = 0;
1941 mbx.payload_length = sizeof(struct mbx_read_common_transrecv_data);
1942 mbx.u0.s.sge_count = 1;
1943 sgl = &mbx.payload.u0.u1.sgl[0];
1944 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
1945 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
1946 sgl->length = htole32(mbx.payload_length);
1947 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1948
1949 fwcmd->params.req.port = LE_32(sc->port_id);
1950 fwcmd->params.req.page_num = LE_32(page_num);
1951
1952 /* command post */
1953 rc = oce_mbox_post(sc, &mbx, NULL);
1954 if (!rc)
1955 rc = fwcmd->hdr.u0.rsp.status;
1956 if (rc) {
1957 device_printf(sc->dev,
1958 "%s failed - cmd status: %d addi status: %d\n",
1959 __FUNCTION__, rc,
1960 fwcmd->hdr.u0.rsp.additional_status);
1961 goto error;
1962 }
1963 if(fwcmd->params.rsp.page_num == PAGE_NUM_A0)
1964 {
1965 bcopy((char *)fwcmd->params.rsp.page_data,
1966 &sfp_vpd_dump_buffer[0],
1967 TRANSCEIVER_A0_SIZE);
1968 }
1969
1970 if(fwcmd->params.rsp.page_num == PAGE_NUM_A2)
1971 {
1972 bcopy((char *)fwcmd->params.rsp.page_data,
1973 &sfp_vpd_dump_buffer[TRANSCEIVER_A0_SIZE],
1974 TRANSCEIVER_A2_SIZE);
1975 }
1976 error:
1977 oce_dma_free(sc, &dma);
1978 return rc;
1979 }
1980
1981 void
oce_mbox_eqd_modify_periodic(POCE_SOFTC sc,struct oce_set_eqd * set_eqd,int num)1982 oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd,
1983 int num)
1984 {
1985 struct oce_mbx mbx;
1986 struct mbx_modify_common_eq_delay *fwcmd;
1987 int rc = 0;
1988 int i = 0;
1989
1990 bzero(&mbx, sizeof(struct oce_mbx));
1991
1992 /* Initialize MODIFY_EQ_DELAY ioctl header */
1993 fwcmd = (struct mbx_modify_common_eq_delay *)&mbx.payload;
1994 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1995 MBX_SUBSYSTEM_COMMON,
1996 OPCODE_COMMON_MODIFY_EQ_DELAY,
1997 MBX_TIMEOUT_SEC,
1998 sizeof(struct mbx_modify_common_eq_delay),
1999 OCE_MBX_VER_V0);
2000 /* fill rest of mbx */
2001 mbx.u0.s.embedded = 1;
2002 mbx.payload_length = sizeof(struct mbx_modify_common_eq_delay);
2003 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
2004
2005 fwcmd->params.req.num_eq = num;
2006 for (i = 0; i < num; i++) {
2007 fwcmd->params.req.delay[i].eq_id =
2008 htole32(set_eqd[i].eq_id);
2009 fwcmd->params.req.delay[i].phase = 0;
2010 fwcmd->params.req.delay[i].dm =
2011 htole32(set_eqd[i].delay_multiplier);
2012 }
2013
2014
2015 /* command post */
2016 rc = oce_mbox_post(sc, &mbx, NULL);
2017
2018 if (!rc)
2019 rc = fwcmd->hdr.u0.rsp.status;
2020 if (rc)
2021 device_printf(sc->dev,
2022 "%s failed - cmd status: %d addi status: %d\n",
2023 __FUNCTION__, rc,
2024 fwcmd->hdr.u0.rsp.additional_status);
2025 }
2026
2027 int
oce_get_profile_config(POCE_SOFTC sc,uint32_t max_rss)2028 oce_get_profile_config(POCE_SOFTC sc, uint32_t max_rss)
2029 {
2030 struct oce_mbx mbx;
2031 struct mbx_common_get_profile_config *fwcmd;
2032 int rc = 0;
2033 int version = 0;
2034 struct oce_mq_sge *sgl;
2035 OCE_DMA_MEM dma;
2036 uint32_t desc_count = 0;
2037 struct oce_nic_resc_desc *nic_desc = NULL;
2038 int i;
2039 boolean_t nic_desc_valid = FALSE;
2040
2041 if (IS_BE2(sc))
2042 return -1;
2043
2044 /* Allocate DMA mem*/
2045 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_profile_config),
2046 &dma, 0))
2047 return ENOMEM;
2048
2049 /* Initialize MODIFY_EQ_DELAY ioctl header */
2050 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_profile_config);
2051 bzero(fwcmd, sizeof(struct mbx_common_get_profile_config));
2052
2053 if (!IS_XE201(sc))
2054 version = OCE_MBX_VER_V1;
2055 else
2056 version = OCE_MBX_VER_V0;
2057
2058 bzero(&mbx, sizeof(struct oce_mbx));
2059 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2060 MBX_SUBSYSTEM_COMMON,
2061 OPCODE_COMMON_GET_PROFILE_CONFIG,
2062 MBX_TIMEOUT_SEC,
2063 sizeof(struct mbx_common_get_profile_config),
2064 version);
2065 /* fill rest of mbx */
2066 mbx.u0.s.embedded = 0;
2067 mbx.payload_length = sizeof(struct mbx_common_get_profile_config);
2068 mbx.u0.s.sge_count = 1;
2069 sgl = &mbx.payload.u0.u1.sgl[0];
2070 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
2071 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
2072 sgl->length = htole32(mbx.payload_length);
2073 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
2074
2075 fwcmd->params.req.type = ACTIVE_PROFILE;
2076
2077 /* command post */
2078 rc = oce_mbox_post(sc, &mbx, NULL);
2079 if (!rc)
2080 rc = fwcmd->hdr.u0.rsp.status;
2081 if (rc) {
2082 device_printf(sc->dev,
2083 "%s failed - cmd status: %d addi status: %d\n",
2084 __FUNCTION__, rc,
2085 fwcmd->hdr.u0.rsp.additional_status);
2086 goto error;
2087 }
2088
2089 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources;
2090 desc_count = HOST_32(fwcmd->params.rsp.desc_count);
2091 for (i = 0; i < desc_count; i++) {
2092 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) ||
2093 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) {
2094 nic_desc_valid = TRUE;
2095 break;
2096 }
2097 nic_desc = (struct oce_nic_resc_desc *) \
2098 ((char *)nic_desc + nic_desc->desc_len);
2099 }
2100 if (!nic_desc_valid) {
2101 rc = -1;
2102 goto error;
2103 }
2104 else {
2105 sc->max_vlans = HOST_16(nic_desc->vlan_count);
2106 sc->nwqs = HOST_16(nic_desc->txq_count);
2107 if (sc->nwqs)
2108 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ);
2109 else
2110 sc->nwqs = OCE_MAX_WQ;
2111
2112 sc->nrssqs = HOST_16(nic_desc->rssq_count);
2113 if (sc->nrssqs)
2114 sc->nrssqs = MIN(sc->nrssqs, max_rss);
2115 else
2116 sc->nrssqs = max_rss;
2117 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */
2118
2119 }
2120 error:
2121 oce_dma_free(sc, &dma);
2122 return rc;
2123
2124 }
2125
2126 int
oce_get_func_config(POCE_SOFTC sc)2127 oce_get_func_config(POCE_SOFTC sc)
2128 {
2129 struct oce_mbx mbx;
2130 struct mbx_common_get_func_config *fwcmd;
2131 int rc = 0;
2132 int version = 0;
2133 struct oce_mq_sge *sgl;
2134 OCE_DMA_MEM dma;
2135 uint32_t desc_count = 0;
2136 struct oce_nic_resc_desc *nic_desc = NULL;
2137 int i;
2138 boolean_t nic_desc_valid = FALSE;
2139 uint32_t max_rss = 0;
2140
2141 if ((IS_BE(sc) || IS_SH(sc)) && (!sc->be3_native))
2142 max_rss = OCE_LEGACY_MODE_RSS;
2143 else
2144 max_rss = OCE_MAX_RSS;
2145
2146 /* Allocate DMA mem*/
2147 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_func_config),
2148 &dma, 0))
2149 return ENOMEM;
2150
2151 /* Initialize MODIFY_EQ_DELAY ioctl header */
2152 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_func_config);
2153 bzero(fwcmd, sizeof(struct mbx_common_get_func_config));
2154
2155 if (IS_SH(sc))
2156 version = OCE_MBX_VER_V1;
2157 else
2158 version = OCE_MBX_VER_V0;
2159
2160 bzero(&mbx, sizeof(struct oce_mbx));
2161 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2162 MBX_SUBSYSTEM_COMMON,
2163 OPCODE_COMMON_GET_FUNCTION_CONFIG,
2164 MBX_TIMEOUT_SEC,
2165 sizeof(struct mbx_common_get_func_config),
2166 version);
2167 /* fill rest of mbx */
2168 mbx.u0.s.embedded = 0;
2169 mbx.payload_length = sizeof(struct mbx_common_get_func_config);
2170 mbx.u0.s.sge_count = 1;
2171 sgl = &mbx.payload.u0.u1.sgl[0];
2172 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
2173 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
2174 sgl->length = htole32(mbx.payload_length);
2175 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
2176
2177 /* command post */
2178 rc = oce_mbox_post(sc, &mbx, NULL);
2179 if (!rc)
2180 rc = fwcmd->hdr.u0.rsp.status;
2181 if (rc) {
2182 device_printf(sc->dev,
2183 "%s failed - cmd status: %d addi status: %d\n",
2184 __FUNCTION__, rc,
2185 fwcmd->hdr.u0.rsp.additional_status);
2186 goto error;
2187 }
2188
2189 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources;
2190 desc_count = HOST_32(fwcmd->params.rsp.desc_count);
2191 for (i = 0; i < desc_count; i++) {
2192 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) ||
2193 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) {
2194 nic_desc_valid = TRUE;
2195 break;
2196 }
2197 nic_desc = (struct oce_nic_resc_desc *) \
2198 ((char *)nic_desc + nic_desc->desc_len);
2199 }
2200 if (!nic_desc_valid) {
2201 rc = -1;
2202 goto error;
2203 }
2204 else {
2205 sc->max_vlans = nic_desc->vlan_count;
2206 sc->nwqs = HOST_32(nic_desc->txq_count);
2207 if (sc->nwqs)
2208 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ);
2209 else
2210 sc->nwqs = OCE_MAX_WQ;
2211
2212 sc->nrssqs = HOST_32(nic_desc->rssq_count);
2213 if (sc->nrssqs)
2214 sc->nrssqs = MIN(sc->nrssqs, max_rss);
2215 else
2216 sc->nrssqs = max_rss;
2217 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */
2218 }
2219 error:
2220 oce_dma_free(sc, &dma);
2221 return rc;
2222
2223 }
2224
2225 /* hw lro functions */
2226
2227 int
oce_mbox_nic_query_lro_capabilities(POCE_SOFTC sc,uint32_t * lro_rq_cnt,uint32_t * lro_flags)2228 oce_mbox_nic_query_lro_capabilities(POCE_SOFTC sc, uint32_t *lro_rq_cnt, uint32_t *lro_flags)
2229 {
2230 struct oce_mbx mbx;
2231 struct mbx_nic_query_lro_capabilities *fwcmd;
2232 int rc = 0;
2233
2234 bzero(&mbx, sizeof(struct oce_mbx));
2235
2236 fwcmd = (struct mbx_nic_query_lro_capabilities *)&mbx.payload;
2237 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2238 MBX_SUBSYSTEM_NIC,
2239 0x20,MBX_TIMEOUT_SEC,
2240 sizeof(struct mbx_nic_query_lro_capabilities),
2241 OCE_MBX_VER_V0);
2242
2243 mbx.u0.s.embedded = 1;
2244 mbx.payload_length = sizeof(struct mbx_nic_query_lro_capabilities);
2245
2246 rc = oce_mbox_post(sc, &mbx, NULL);
2247 if (!rc)
2248 rc = fwcmd->hdr.u0.rsp.status;
2249 if (rc) {
2250 device_printf(sc->dev,
2251 "%s failed - cmd status: %d addi status: %d\n",
2252 __FUNCTION__, rc,
2253 fwcmd->hdr.u0.rsp.additional_status);
2254
2255 return rc;
2256 }
2257 if(lro_flags)
2258 *lro_flags = HOST_32(fwcmd->params.rsp.lro_flags);
2259
2260 if(lro_rq_cnt)
2261 *lro_rq_cnt = HOST_16(fwcmd->params.rsp.lro_rq_cnt);
2262
2263 return rc;
2264 }
2265
2266 int
oce_mbox_nic_set_iface_lro_config(POCE_SOFTC sc,int enable)2267 oce_mbox_nic_set_iface_lro_config(POCE_SOFTC sc, int enable)
2268 {
2269 struct oce_mbx mbx;
2270 struct mbx_nic_set_iface_lro_config *fwcmd;
2271 int rc = 0;
2272
2273 bzero(&mbx, sizeof(struct oce_mbx));
2274
2275 fwcmd = (struct mbx_nic_set_iface_lro_config *)&mbx.payload;
2276 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2277 MBX_SUBSYSTEM_NIC,
2278 0x26,MBX_TIMEOUT_SEC,
2279 sizeof(struct mbx_nic_set_iface_lro_config),
2280 OCE_MBX_VER_V0);
2281
2282 mbx.u0.s.embedded = 1;
2283 mbx.payload_length = sizeof(struct mbx_nic_set_iface_lro_config);
2284
2285 fwcmd->params.req.iface_id = sc->if_id;
2286 fwcmd->params.req.lro_flags = 0;
2287
2288 if(enable) {
2289 fwcmd->params.req.lro_flags = LRO_FLAGS_HASH_MODE | LRO_FLAGS_RSS_MODE;
2290 fwcmd->params.req.lro_flags |= LRO_FLAGS_CLSC_IPV4 | LRO_FLAGS_CLSC_IPV6;
2291
2292 fwcmd->params.req.max_clsc_byte_cnt = 64*1024; /* min = 2974, max = 0xfa59 */
2293 fwcmd->params.req.max_clsc_seg_cnt = 43; /* min = 2, max = 64 */
2294 fwcmd->params.req.max_clsc_usec_delay = 18; /* min = 1, max = 256 */
2295 fwcmd->params.req.min_clsc_frame_byte_cnt = 0; /* min = 1, max = 9014 */
2296 }
2297
2298 rc = oce_mbox_post(sc, &mbx, NULL);
2299 if (!rc)
2300 rc = fwcmd->hdr.u0.rsp.status;
2301 if (rc) {
2302 device_printf(sc->dev,
2303 "%s failed - cmd status: %d addi status: %d\n",
2304 __FUNCTION__, rc,
2305 fwcmd->hdr.u0.rsp.additional_status);
2306
2307 return rc;
2308 }
2309 return rc;
2310 }
2311
2312 int
oce_mbox_create_rq_v2(struct oce_rq * rq)2313 oce_mbox_create_rq_v2(struct oce_rq *rq)
2314 {
2315 struct oce_mbx mbx;
2316 struct mbx_create_nic_rq_v2 *fwcmd;
2317 POCE_SOFTC sc = rq->parent;
2318 int rc = 0, num_pages = 0;
2319
2320 if (rq->qstate == QCREATED)
2321 return 0;
2322
2323 bzero(&mbx, sizeof(struct oce_mbx));
2324
2325 fwcmd = (struct mbx_create_nic_rq_v2 *)&mbx.payload;
2326 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2327 MBX_SUBSYSTEM_NIC,
2328 0x08, MBX_TIMEOUT_SEC,
2329 sizeof(struct mbx_create_nic_rq_v2),
2330 OCE_MBX_VER_V2);
2331
2332 /* oce_page_list will also prepare pages */
2333 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]);
2334
2335 fwcmd->params.req.cq_id = rq->cq->cq_id;
2336 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048;
2337 fwcmd->params.req.num_pages = num_pages;
2338
2339 fwcmd->params.req.if_id = sc->if_id;
2340
2341 fwcmd->params.req.max_frame_size = rq->cfg.mtu;
2342 fwcmd->params.req.page_size = 1;
2343 if(rq->cfg.is_rss_queue) {
2344 fwcmd->params.req.rq_flags = (NIC_RQ_FLAGS_RSS | NIC_RQ_FLAGS_LRO);
2345 }else {
2346 device_printf(sc->dev,
2347 "non rss lro queue should not be created \n");
2348 goto error;
2349 }
2350 mbx.u0.s.embedded = 1;
2351 mbx.payload_length = sizeof(struct mbx_create_nic_rq_v2);
2352
2353 rc = oce_mbox_post(sc, &mbx, NULL);
2354 if (!rc)
2355 rc = fwcmd->hdr.u0.rsp.status;
2356 if (rc) {
2357 device_printf(sc->dev,
2358 "%s failed - cmd status: %d addi status: %d\n",
2359 __FUNCTION__, rc,
2360 fwcmd->hdr.u0.rsp.additional_status);
2361 goto error;
2362 }
2363 rq->rq_id = HOST_16(fwcmd->params.rsp.rq_id);
2364 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid;
2365
2366 error:
2367 return rc;
2368 }
2369
2370