1 /*-
2 * Copyright (C) 2013 Emulex
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Emulex Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
39 /* $FreeBSD$ */
40
41 #include "oce_if.h"
42 extern uint32_t sfp_vpd_dump_buffer[TRANSCEIVER_DATA_NUM_ELE];
43
44 /**
45 * @brief Reset (firmware) common function
46 * @param sc software handle to the device
47 * @returns 0 on success, ETIMEDOUT on failure
48 */
49 int
oce_reset_fun(POCE_SOFTC sc)50 oce_reset_fun(POCE_SOFTC sc)
51 {
52 struct oce_mbx *mbx;
53 struct oce_bmbx *mb;
54 struct ioctl_common_function_reset *fwcmd;
55 int rc = 0;
56
57 if (sc->flags & OCE_FLAGS_FUNCRESET_RQD) {
58 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
59 mbx = &mb->mbx;
60 bzero(mbx, sizeof(struct oce_mbx));
61
62 fwcmd = (struct ioctl_common_function_reset *)&mbx->payload;
63 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
64 MBX_SUBSYSTEM_COMMON,
65 OPCODE_COMMON_FUNCTION_RESET,
66 10, /* MBX_TIMEOUT_SEC */
67 sizeof(struct
68 ioctl_common_function_reset),
69 OCE_MBX_VER_V0);
70
71 mbx->u0.s.embedded = 1;
72 mbx->payload_length =
73 sizeof(struct ioctl_common_function_reset);
74
75 rc = oce_mbox_dispatch(sc, 2);
76 }
77
78 return rc;
79 }
80
81
82 /**
83 * @brief This funtions tells firmware we are
84 * done with commands.
85 * @param sc software handle to the device
86 * @returns 0 on success, ETIMEDOUT on failure
87 */
88 int
oce_fw_clean(POCE_SOFTC sc)89 oce_fw_clean(POCE_SOFTC sc)
90 {
91 struct oce_bmbx *mbx;
92 uint8_t *ptr;
93 int ret = 0;
94
95 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
96 ptr = (uint8_t *) &mbx->mbx;
97
98 /* Endian Signature */
99 *ptr++ = 0xff;
100 *ptr++ = 0xaa;
101 *ptr++ = 0xbb;
102 *ptr++ = 0xff;
103 *ptr++ = 0xff;
104 *ptr++ = 0xcc;
105 *ptr++ = 0xdd;
106 *ptr = 0xff;
107
108 ret = oce_mbox_dispatch(sc, 2);
109
110 return ret;
111 }
112
113
114 /**
115 * @brief Mailbox wait
116 * @param sc software handle to the device
117 * @param tmo_sec timeout in seconds
118 */
119 static int
oce_mbox_wait(POCE_SOFTC sc,uint32_t tmo_sec)120 oce_mbox_wait(POCE_SOFTC sc, uint32_t tmo_sec)
121 {
122 tmo_sec *= 10000;
123 pd_mpu_mbox_db_t mbox_db;
124
125 for (;;) {
126 if (tmo_sec != 0) {
127 if (--tmo_sec == 0)
128 break;
129 }
130
131 mbox_db.dw0 = OCE_READ_REG32(sc, db, PD_MPU_MBOX_DB);
132
133 if (mbox_db.bits.ready)
134 return 0;
135
136 DELAY(100);
137 }
138
139 device_printf(sc->dev, "Mailbox timed out\n");
140
141 return ETIMEDOUT;
142 }
143
144
145 /**
146 * @brief Mailbox dispatch
147 * @param sc software handle to the device
148 * @param tmo_sec timeout in seconds
149 */
150 int
oce_mbox_dispatch(POCE_SOFTC sc,uint32_t tmo_sec)151 oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec)
152 {
153 pd_mpu_mbox_db_t mbox_db;
154 uint32_t pa;
155 int rc;
156
157 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_PREWRITE);
158 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 34);
159 bzero(&mbox_db, sizeof(pd_mpu_mbox_db_t));
160 mbox_db.bits.ready = 0;
161 mbox_db.bits.hi = 1;
162 mbox_db.bits.address = pa;
163
164 rc = oce_mbox_wait(sc, tmo_sec);
165 if (rc == 0) {
166 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0);
167
168 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 4) & 0x3fffffff;
169 mbox_db.bits.ready = 0;
170 mbox_db.bits.hi = 0;
171 mbox_db.bits.address = pa;
172
173 rc = oce_mbox_wait(sc, tmo_sec);
174
175 if (rc == 0) {
176 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0);
177
178 rc = oce_mbox_wait(sc, tmo_sec);
179
180 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_POSTWRITE);
181 }
182 }
183
184 return rc;
185 }
186
187
188
189 /**
190 * @brief Mailbox common request header initialization
191 * @param hdr mailbox header
192 * @param dom domain
193 * @param port port
194 * @param subsys subsystem
195 * @param opcode opcode
196 * @param timeout timeout
197 * @param pyld_len payload length
198 */
199 void
mbx_common_req_hdr_init(struct mbx_hdr * hdr,uint8_t dom,uint8_t port,uint8_t subsys,uint8_t opcode,uint32_t timeout,uint32_t pyld_len,uint8_t version)200 mbx_common_req_hdr_init(struct mbx_hdr *hdr,
201 uint8_t dom, uint8_t port,
202 uint8_t subsys, uint8_t opcode,
203 uint32_t timeout, uint32_t pyld_len,
204 uint8_t version)
205 {
206 hdr->u0.req.opcode = opcode;
207 hdr->u0.req.subsystem = subsys;
208 hdr->u0.req.port_number = port;
209 hdr->u0.req.domain = dom;
210
211 hdr->u0.req.timeout = timeout;
212 hdr->u0.req.request_length = pyld_len - sizeof(struct mbx_hdr);
213 hdr->u0.req.version = version;
214 }
215
216
217
218 /**
219 * @brief Function to initialize the hw with host endian information
220 * @param sc software handle to the device
221 * @returns 0 on success, ETIMEDOUT on failure
222 */
223 int
oce_mbox_init(POCE_SOFTC sc)224 oce_mbox_init(POCE_SOFTC sc)
225 {
226 struct oce_bmbx *mbx;
227 uint8_t *ptr;
228 int ret = 0;
229
230 if (sc->flags & OCE_FLAGS_MBOX_ENDIAN_RQD) {
231 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
232 ptr = (uint8_t *) &mbx->mbx;
233
234 /* Endian Signature */
235 *ptr++ = 0xff;
236 *ptr++ = 0x12;
237 *ptr++ = 0x34;
238 *ptr++ = 0xff;
239 *ptr++ = 0xff;
240 *ptr++ = 0x56;
241 *ptr++ = 0x78;
242 *ptr = 0xff;
243
244 ret = oce_mbox_dispatch(sc, 0);
245 }
246
247 return ret;
248 }
249
250
251 /**
252 * @brief Function to get the firmware version
253 * @param sc software handle to the device
254 * @returns 0 on success, EIO on failure
255 */
256 int
oce_get_fw_version(POCE_SOFTC sc)257 oce_get_fw_version(POCE_SOFTC sc)
258 {
259 struct oce_mbx mbx;
260 struct mbx_get_common_fw_version *fwcmd;
261 int ret = 0;
262
263 bzero(&mbx, sizeof(struct oce_mbx));
264
265 fwcmd = (struct mbx_get_common_fw_version *)&mbx.payload;
266 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
267 MBX_SUBSYSTEM_COMMON,
268 OPCODE_COMMON_GET_FW_VERSION,
269 MBX_TIMEOUT_SEC,
270 sizeof(struct mbx_get_common_fw_version),
271 OCE_MBX_VER_V0);
272
273 mbx.u0.s.embedded = 1;
274 mbx.payload_length = sizeof(struct mbx_get_common_fw_version);
275 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
276
277 ret = oce_mbox_post(sc, &mbx, NULL);
278 if (!ret)
279 ret = fwcmd->hdr.u0.rsp.status;
280 if (ret) {
281 device_printf(sc->dev,
282 "%s failed - cmd status: %d addi status: %d\n",
283 __FUNCTION__, ret,
284 fwcmd->hdr.u0.rsp.additional_status);
285 goto error;
286 }
287
288 bcopy(fwcmd->params.rsp.fw_ver_str, sc->fw_version, 32);
289 error:
290 return ret;
291 }
292
293
294 /**
295 * @brief Firmware will send gracious notifications during
296 * attach only after sending first mcc commnad. We
297 * use MCC queue only for getting async and mailbox
298 * for sending cmds. So to get gracious notifications
299 * atleast send one dummy command on mcc.
300 */
301 int
oce_first_mcc_cmd(POCE_SOFTC sc)302 oce_first_mcc_cmd(POCE_SOFTC sc)
303 {
304 struct oce_mbx *mbx;
305 struct oce_mq *mq = sc->mq;
306 struct mbx_get_common_fw_version *fwcmd;
307 uint32_t reg_value;
308
309 mbx = RING_GET_PRODUCER_ITEM_VA(mq->ring, struct oce_mbx);
310 bzero(mbx, sizeof(struct oce_mbx));
311
312 fwcmd = (struct mbx_get_common_fw_version *)&mbx->payload;
313 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
314 MBX_SUBSYSTEM_COMMON,
315 OPCODE_COMMON_GET_FW_VERSION,
316 MBX_TIMEOUT_SEC,
317 sizeof(struct mbx_get_common_fw_version),
318 OCE_MBX_VER_V0);
319 mbx->u0.s.embedded = 1;
320 mbx->payload_length = sizeof(struct mbx_get_common_fw_version);
321 bus_dmamap_sync(mq->ring->dma.tag, mq->ring->dma.map,
322 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
323 RING_PUT(mq->ring, 1);
324 reg_value = (1 << 16) | mq->mq_id;
325 OCE_WRITE_REG32(sc, db, PD_MQ_DB, reg_value);
326
327 return 0;
328 }
329
330 /**
331 * @brief Function to post a MBX to the mbox
332 * @param sc software handle to the device
333 * @param mbx pointer to the MBX to send
334 * @param mbxctx pointer to the mbx context structure
335 * @returns 0 on success, error on failure
336 */
337 int
oce_mbox_post(POCE_SOFTC sc,struct oce_mbx * mbx,struct oce_mbx_ctx * mbxctx)338 oce_mbox_post(POCE_SOFTC sc, struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx)
339 {
340 struct oce_mbx *mb_mbx = NULL;
341 struct oce_mq_cqe *mb_cqe = NULL;
342 struct oce_bmbx *mb = NULL;
343 int rc = 0;
344 uint32_t tmo = 0;
345 uint32_t cstatus = 0;
346 uint32_t xstatus = 0;
347
348 LOCK(&sc->bmbx_lock);
349
350 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
351 mb_mbx = &mb->mbx;
352
353 /* get the tmo */
354 tmo = mbx->tag[0];
355 mbx->tag[0] = 0;
356
357 /* copy mbx into mbox */
358 bcopy(mbx, mb_mbx, sizeof(struct oce_mbx));
359
360 /* now dispatch */
361 rc = oce_mbox_dispatch(sc, tmo);
362 if (rc == 0) {
363 /*
364 * the command completed successfully. Now get the
365 * completion queue entry
366 */
367 mb_cqe = &mb->cqe;
368 DW_SWAP(u32ptr(&mb_cqe->u0.dw[0]), sizeof(struct oce_mq_cqe));
369
370 /* copy mbox mbx back */
371 bcopy(mb_mbx, mbx, sizeof(struct oce_mbx));
372
373 /* pick up the mailbox status */
374 cstatus = mb_cqe->u0.s.completion_status;
375 xstatus = mb_cqe->u0.s.extended_status;
376
377 /*
378 * store the mbx context in the cqe tag section so that
379 * the upper layer handling the cqe can associate the mbx
380 * with the response
381 */
382 if (cstatus == 0 && mbxctx) {
383 /* save context */
384 mbxctx->mbx = mb_mbx;
385 bcopy(&mbxctx, mb_cqe->u0.s.mq_tag,
386 sizeof(struct oce_mbx_ctx *));
387 }
388 }
389
390 UNLOCK(&sc->bmbx_lock);
391
392 return rc;
393 }
394
395 /**
396 * @brief Function to read the mac address associated with an interface
397 * @param sc software handle to the device
398 * @param if_id interface id to read the address from
399 * @param perm set to 1 if reading the factory mac address.
400 * In this case if_id is ignored
401 * @param type type of the mac address, whether network or storage
402 * @param[out] mac [OUTPUT] pointer to a buffer containing the
403 * mac address when the command succeeds.
404 * @returns 0 on success, EIO on failure
405 */
406 int
oce_read_mac_addr(POCE_SOFTC sc,uint32_t if_id,uint8_t perm,uint8_t type,struct mac_address_format * mac)407 oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id,
408 uint8_t perm, uint8_t type, struct mac_address_format *mac)
409 {
410 struct oce_mbx mbx;
411 struct mbx_query_common_iface_mac *fwcmd;
412 int ret = 0;
413
414 bzero(&mbx, sizeof(struct oce_mbx));
415
416 fwcmd = (struct mbx_query_common_iface_mac *)&mbx.payload;
417 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
418 MBX_SUBSYSTEM_COMMON,
419 OPCODE_COMMON_QUERY_IFACE_MAC,
420 MBX_TIMEOUT_SEC,
421 sizeof(struct mbx_query_common_iface_mac),
422 OCE_MBX_VER_V0);
423
424 fwcmd->params.req.permanent = perm;
425 if (!perm)
426 fwcmd->params.req.if_id = (uint16_t) if_id;
427 else
428 fwcmd->params.req.if_id = 0;
429
430 fwcmd->params.req.type = type;
431
432 mbx.u0.s.embedded = 1;
433 mbx.payload_length = sizeof(struct mbx_query_common_iface_mac);
434 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
435
436 ret = oce_mbox_post(sc, &mbx, NULL);
437 if (!ret)
438 ret = fwcmd->hdr.u0.rsp.status;
439 if (ret) {
440 device_printf(sc->dev,
441 "%s failed - cmd status: %d addi status: %d\n",
442 __FUNCTION__, ret,
443 fwcmd->hdr.u0.rsp.additional_status);
444 goto error;
445 }
446
447 /* copy the mac addres in the output parameter */
448 mac->size_of_struct = fwcmd->params.rsp.mac.size_of_struct;
449 bcopy(&fwcmd->params.rsp.mac.mac_addr[0], &mac->mac_addr[0],
450 mac->size_of_struct);
451 error:
452 return ret;
453 }
454
455 /**
456 * @brief Function to query the fw attributes from the hw
457 * @param sc software handle to the device
458 * @returns 0 on success, EIO on failure
459 */
460 int
oce_get_fw_config(POCE_SOFTC sc)461 oce_get_fw_config(POCE_SOFTC sc)
462 {
463 struct oce_mbx mbx;
464 struct mbx_common_query_fw_config *fwcmd;
465 int ret = 0;
466
467 bzero(&mbx, sizeof(struct oce_mbx));
468
469 fwcmd = (struct mbx_common_query_fw_config *)&mbx.payload;
470 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
471 MBX_SUBSYSTEM_COMMON,
472 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
473 MBX_TIMEOUT_SEC,
474 sizeof(struct mbx_common_query_fw_config),
475 OCE_MBX_VER_V0);
476
477 mbx.u0.s.embedded = 1;
478 mbx.payload_length = sizeof(struct mbx_common_query_fw_config);
479 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
480
481 ret = oce_mbox_post(sc, &mbx, NULL);
482 if (!ret)
483 ret = fwcmd->hdr.u0.rsp.status;
484 if (ret) {
485 device_printf(sc->dev,
486 "%s failed - cmd status: %d addi status: %d\n",
487 __FUNCTION__, ret,
488 fwcmd->hdr.u0.rsp.additional_status);
489 goto error;
490 }
491
492 DW_SWAP(u32ptr(fwcmd), sizeof(struct mbx_common_query_fw_config));
493
494 sc->config_number = HOST_32(fwcmd->params.rsp.config_number);
495 sc->asic_revision = HOST_32(fwcmd->params.rsp.asic_revision);
496 sc->port_id = HOST_32(fwcmd->params.rsp.port_id);
497 sc->function_mode = HOST_32(fwcmd->params.rsp.function_mode);
498 sc->function_caps = HOST_32(fwcmd->params.rsp.function_caps);
499
500 if (fwcmd->params.rsp.ulp[0].ulp_mode & ULP_NIC_MODE) {
501 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[0].nic_wq_tot);
502 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[0].lro_rqid_tot);
503 } else {
504 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[1].nic_wq_tot);
505 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[1].lro_rqid_tot);
506 }
507
508 error:
509 return ret;
510
511 }
512
513 /**
514 *
515 * @brief function to create a device interface
516 * @param sc software handle to the device
517 * @param cap_flags capability flags
518 * @param en_flags enable capability flags
519 * @param vlan_tag optional vlan tag to associate with the if
520 * @param mac_addr pointer to a buffer containing the mac address
521 * @param[out] if_id [OUTPUT] pointer to an integer to hold the ID of the
522 interface created
523 * @returns 0 on success, EIO on failure
524 */
525 int
oce_if_create(POCE_SOFTC sc,uint32_t cap_flags,uint32_t en_flags,uint16_t vlan_tag,uint8_t * mac_addr,uint32_t * if_id)526 oce_if_create(POCE_SOFTC sc,
527 uint32_t cap_flags,
528 uint32_t en_flags,
529 uint16_t vlan_tag,
530 uint8_t *mac_addr,
531 uint32_t *if_id)
532 {
533 struct oce_mbx mbx;
534 struct mbx_create_common_iface *fwcmd;
535 int rc = 0;
536
537 bzero(&mbx, sizeof(struct oce_mbx));
538
539 fwcmd = (struct mbx_create_common_iface *)&mbx.payload;
540 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
541 MBX_SUBSYSTEM_COMMON,
542 OPCODE_COMMON_CREATE_IFACE,
543 MBX_TIMEOUT_SEC,
544 sizeof(struct mbx_create_common_iface),
545 OCE_MBX_VER_V0);
546 DW_SWAP(u32ptr(&fwcmd->hdr), sizeof(struct mbx_hdr));
547
548 fwcmd->params.req.version = 0;
549 fwcmd->params.req.cap_flags = LE_32(cap_flags);
550 fwcmd->params.req.enable_flags = LE_32(en_flags);
551 if (mac_addr != NULL) {
552 bcopy(mac_addr, &fwcmd->params.req.mac_addr[0], 6);
553 fwcmd->params.req.vlan_tag.u0.normal.vtag = LE_16(vlan_tag);
554 fwcmd->params.req.mac_invalid = 0;
555 } else {
556 fwcmd->params.req.mac_invalid = 1;
557 }
558
559 mbx.u0.s.embedded = 1;
560 mbx.payload_length = sizeof(struct mbx_create_common_iface);
561 DW_SWAP(u32ptr(&mbx), OCE_BMBX_RHDR_SZ);
562
563 rc = oce_mbox_post(sc, &mbx, NULL);
564 if (!rc)
565 rc = fwcmd->hdr.u0.rsp.status;
566 if (rc) {
567 device_printf(sc->dev,
568 "%s failed - cmd status: %d addi status: %d\n",
569 __FUNCTION__, rc,
570 fwcmd->hdr.u0.rsp.additional_status);
571 goto error;
572 }
573
574 *if_id = HOST_32(fwcmd->params.rsp.if_id);
575
576 if (mac_addr != NULL)
577 sc->pmac_id = HOST_32(fwcmd->params.rsp.pmac_id);
578 error:
579 return rc;
580 }
581
582 /**
583 * @brief Function to delete an interface
584 * @param sc software handle to the device
585 * @param if_id ID of the interface to delete
586 * @returns 0 on success, EIO on failure
587 */
588 int
oce_if_del(POCE_SOFTC sc,uint32_t if_id)589 oce_if_del(POCE_SOFTC sc, uint32_t if_id)
590 {
591 struct oce_mbx mbx;
592 struct mbx_destroy_common_iface *fwcmd;
593 int rc = 0;
594
595 bzero(&mbx, sizeof(struct oce_mbx));
596
597 fwcmd = (struct mbx_destroy_common_iface *)&mbx.payload;
598 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
599 MBX_SUBSYSTEM_COMMON,
600 OPCODE_COMMON_DESTROY_IFACE,
601 MBX_TIMEOUT_SEC,
602 sizeof(struct mbx_destroy_common_iface),
603 OCE_MBX_VER_V0);
604
605 fwcmd->params.req.if_id = if_id;
606
607 mbx.u0.s.embedded = 1;
608 mbx.payload_length = sizeof(struct mbx_destroy_common_iface);
609 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
610
611 rc = oce_mbox_post(sc, &mbx, NULL);
612 if (!rc)
613 rc = fwcmd->hdr.u0.rsp.status;
614 if (rc)
615 device_printf(sc->dev,
616 "%s failed - cmd status: %d addi status: %d\n",
617 __FUNCTION__, rc,
618 fwcmd->hdr.u0.rsp.additional_status);
619 return rc;
620 }
621
622 /**
623 * @brief Function to send the mbx command to configure vlan
624 * @param sc software handle to the device
625 * @param if_id interface identifier index
626 * @param vtag_arr array of vlan tags
627 * @param vtag_cnt number of elements in array
628 * @param untagged boolean TRUE/FLASE
629 * @param enable_promisc flag to enable/disable VLAN promiscuous mode
630 * @returns 0 on success, EIO on failure
631 */
632 int
oce_config_vlan(POCE_SOFTC sc,uint32_t if_id,struct normal_vlan * vtag_arr,uint8_t vtag_cnt,uint32_t untagged,uint32_t enable_promisc)633 oce_config_vlan(POCE_SOFTC sc,
634 uint32_t if_id,
635 struct normal_vlan *vtag_arr,
636 uint8_t vtag_cnt, uint32_t untagged, uint32_t enable_promisc)
637 {
638 struct oce_mbx mbx;
639 struct mbx_common_config_vlan *fwcmd;
640 int rc = 0;
641
642 if (sc->vlans_added > sc->max_vlans)
643 goto vlan_promisc;
644
645 bzero(&mbx, sizeof(struct oce_mbx));
646 fwcmd = (struct mbx_common_config_vlan *)&mbx.payload;
647
648 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
649 MBX_SUBSYSTEM_COMMON,
650 OPCODE_COMMON_CONFIG_IFACE_VLAN,
651 MBX_TIMEOUT_SEC,
652 sizeof(struct mbx_common_config_vlan),
653 OCE_MBX_VER_V0);
654
655 fwcmd->params.req.if_id = (uint8_t) if_id;
656 fwcmd->params.req.promisc = (uint8_t) enable_promisc;
657 fwcmd->params.req.untagged = (uint8_t) untagged;
658 fwcmd->params.req.num_vlans = vtag_cnt;
659
660 if (!enable_promisc) {
661 bcopy(vtag_arr, fwcmd->params.req.tags.normal_vlans,
662 vtag_cnt * sizeof(struct normal_vlan));
663 }
664 mbx.u0.s.embedded = 1;
665 mbx.payload_length = sizeof(struct mbx_common_config_vlan);
666 DW_SWAP(u32ptr(&mbx), (OCE_BMBX_RHDR_SZ + mbx.payload_length));
667
668 rc = oce_mbox_post(sc, &mbx, NULL);
669 if (!rc)
670 rc = fwcmd->hdr.u0.rsp.status;
671 if (rc)
672 device_printf(sc->dev,
673 "%s failed - cmd status: %d addi status: %d\n",
674 __FUNCTION__, rc,
675 fwcmd->hdr.u0.rsp.additional_status);
676
677 goto done;
678
679 vlan_promisc:
680 /* Enable Vlan Promis */
681 oce_rxf_set_promiscuous(sc, (1 << 1));
682 device_printf(sc->dev,"Enabling Vlan Promisc Mode\n");
683 done:
684 return rc;
685
686 }
687
688 /**
689 * @brief Function to set flow control capability in the hardware
690 * @param sc software handle to the device
691 * @param flow_control flow control flags to set
692 * @returns 0 on success, EIO on failure
693 */
694 int
oce_set_flow_control(POCE_SOFTC sc,uint32_t flow_control)695 oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control)
696 {
697 struct oce_mbx mbx;
698 struct mbx_common_get_set_flow_control *fwcmd =
699 (struct mbx_common_get_set_flow_control *)&mbx.payload;
700 int rc;
701
702 bzero(&mbx, sizeof(struct oce_mbx));
703
704 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
705 MBX_SUBSYSTEM_COMMON,
706 OPCODE_COMMON_SET_FLOW_CONTROL,
707 MBX_TIMEOUT_SEC,
708 sizeof(struct mbx_common_get_set_flow_control),
709 OCE_MBX_VER_V0);
710
711 if (flow_control & OCE_FC_TX)
712 fwcmd->tx_flow_control = 1;
713
714 if (flow_control & OCE_FC_RX)
715 fwcmd->rx_flow_control = 1;
716
717 mbx.u0.s.embedded = 1;
718 mbx.payload_length = sizeof(struct mbx_common_get_set_flow_control);
719 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
720
721 rc = oce_mbox_post(sc, &mbx, NULL);
722 if (!rc)
723 rc = fwcmd->hdr.u0.rsp.status;
724 if (rc)
725 device_printf(sc->dev,
726 "%s failed - cmd status: %d addi status: %d\n",
727 __FUNCTION__, rc,
728 fwcmd->hdr.u0.rsp.additional_status);
729 return rc;
730 }
731
732 /**
733 * @brief Initialize the RSS CPU indirection table
734 *
735 * The table is used to choose the queue to place the incomming packets.
736 * Incomming packets are hashed. The lowest bits in the hash result
737 * are used as the index into the CPU indirection table.
738 * Each entry in the table contains the RSS CPU-ID returned by the NIC
739 * create. Based on the CPU ID, the receive completion is routed to
740 * the corresponding RSS CQs. (Non-RSS packets are always completed
741 * on the default (0) CQ).
742 *
743 * @param sc software handle to the device
744 * @param *fwcmd pointer to the rss mbox command
745 * @returns none
746 */
747 static int
oce_rss_itbl_init(POCE_SOFTC sc,struct mbx_config_nic_rss * fwcmd)748 oce_rss_itbl_init(POCE_SOFTC sc, struct mbx_config_nic_rss *fwcmd)
749 {
750 int i = 0, j = 0, rc = 0;
751 uint8_t *tbl = fwcmd->params.req.cputable;
752 struct oce_rq *rq = NULL;
753
754
755 for (j = 0; j < INDIRECTION_TABLE_ENTRIES ; j += (sc->nrqs - 1)) {
756 for_all_rss_queues(sc, rq, i) {
757 if ((j + i) >= INDIRECTION_TABLE_ENTRIES)
758 break;
759 tbl[j + i] = rq->rss_cpuid;
760 }
761 }
762 if (i == 0) {
763 device_printf(sc->dev, "error: Invalid number of RSS RQ's\n");
764 rc = ENXIO;
765
766 }
767
768 /* fill log2 value indicating the size of the CPU table */
769 if (rc == 0)
770 fwcmd->params.req.cpu_tbl_sz_log2 = LE_16(OCE_LOG2(i));
771
772 return rc;
773 }
774
775 /**
776 * @brief Function to set flow control capability in the hardware
777 * @param sc software handle to the device
778 * @param if_id interface id to read the address from
779 * @param enable_rss 0=disable, RSS_ENABLE_xxx flags otherwise
780 * @returns 0 on success, EIO on failure
781 */
782 int
oce_config_nic_rss(POCE_SOFTC sc,uint32_t if_id,uint16_t enable_rss)783 oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss)
784 {
785 int rc;
786 struct oce_mbx mbx;
787 struct mbx_config_nic_rss *fwcmd =
788 (struct mbx_config_nic_rss *)&mbx.payload;
789 int version;
790
791 bzero(&mbx, sizeof(struct oce_mbx));
792
793 if (IS_XE201(sc) || IS_SH(sc)) {
794 version = OCE_MBX_VER_V1;
795 fwcmd->params.req.enable_rss = RSS_ENABLE_UDP_IPV4 |
796 RSS_ENABLE_UDP_IPV6;
797 } else
798 version = OCE_MBX_VER_V0;
799
800 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
801 MBX_SUBSYSTEM_NIC,
802 NIC_CONFIG_RSS,
803 MBX_TIMEOUT_SEC,
804 sizeof(struct mbx_config_nic_rss),
805 version);
806 if (enable_rss)
807 fwcmd->params.req.enable_rss |= (RSS_ENABLE_IPV4 |
808 RSS_ENABLE_TCP_IPV4 |
809 RSS_ENABLE_IPV6 |
810 RSS_ENABLE_TCP_IPV6);
811 fwcmd->params.req.flush = OCE_FLUSH;
812 fwcmd->params.req.if_id = LE_32(if_id);
813
814 read_random(fwcmd->params.req.hash, sizeof(fwcmd->params.req.hash));
815
816 rc = oce_rss_itbl_init(sc, fwcmd);
817 if (rc == 0) {
818 mbx.u0.s.embedded = 1;
819 mbx.payload_length = sizeof(struct mbx_config_nic_rss);
820 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
821
822 rc = oce_mbox_post(sc, &mbx, NULL);
823 if (!rc)
824 rc = fwcmd->hdr.u0.rsp.status;
825 if (rc)
826 device_printf(sc->dev,
827 "%s failed - cmd status: %d addi status: %d\n",
828 __FUNCTION__, rc,
829 fwcmd->hdr.u0.rsp.additional_status);
830 }
831 return rc;
832 }
833
834 /**
835 * @brief RXF function to enable/disable device promiscuous mode
836 * @param sc software handle to the device
837 * @param enable enable/disable flag
838 * @returns 0 on success, EIO on failure
839 * @note
840 * The NIC_CONFIG_PROMISCUOUS command deprecated for Lancer.
841 * This function uses the COMMON_SET_IFACE_RX_FILTER command instead.
842 */
843 int
oce_rxf_set_promiscuous(POCE_SOFTC sc,uint8_t enable)844 oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable)
845 {
846 struct mbx_set_common_iface_rx_filter *fwcmd;
847 int sz = sizeof(struct mbx_set_common_iface_rx_filter);
848 iface_rx_filter_ctx_t *req;
849 OCE_DMA_MEM sgl;
850 int rc;
851
852 /* allocate mbx payload's dma scatter/gather memory */
853 rc = oce_dma_alloc(sc, sz, &sgl, 0);
854 if (rc)
855 return rc;
856
857 fwcmd = OCE_DMAPTR(&sgl, struct mbx_set_common_iface_rx_filter);
858
859 req = &fwcmd->params.req;
860 req->iface_flags_mask = MBX_RX_IFACE_FLAGS_PROMISCUOUS |
861 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
862 /* Bit 0 Mac promisc, Bit 1 Vlan promisc */
863 if (enable & 0x01)
864 req->iface_flags = MBX_RX_IFACE_FLAGS_PROMISCUOUS;
865
866 if (enable & 0x02)
867 req->iface_flags = MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
868
869 req->if_id = sc->if_id;
870
871 rc = oce_set_common_iface_rx_filter(sc, &sgl);
872 oce_dma_free(sc, &sgl);
873
874 return rc;
875 }
876
877
878 /**
879 * @brief Function modify and select rx filter options
880 * @param sc software handle to the device
881 * @param sgl scatter/gather request/response
882 * @returns 0 on success, error code on failure
883 */
884 int
oce_set_common_iface_rx_filter(POCE_SOFTC sc,POCE_DMA_MEM sgl)885 oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl)
886 {
887 struct oce_mbx mbx;
888 int mbx_sz = sizeof(struct mbx_set_common_iface_rx_filter);
889 struct mbx_set_common_iface_rx_filter *fwcmd;
890 int rc;
891
892 bzero(&mbx, sizeof(struct oce_mbx));
893 fwcmd = OCE_DMAPTR(sgl, struct mbx_set_common_iface_rx_filter);
894
895 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
896 MBX_SUBSYSTEM_COMMON,
897 OPCODE_COMMON_SET_IFACE_RX_FILTER,
898 MBX_TIMEOUT_SEC,
899 mbx_sz,
900 OCE_MBX_VER_V0);
901
902 oce_dma_sync(sgl, BUS_DMASYNC_PREWRITE);
903 mbx.u0.s.embedded = 0;
904 mbx.u0.s.sge_count = 1;
905 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(sgl->paddr);
906 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(sgl->paddr);
907 mbx.payload.u0.u1.sgl[0].length = mbx_sz;
908 mbx.payload_length = mbx_sz;
909 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
910
911 rc = oce_mbox_post(sc, &mbx, NULL);
912 if (!rc)
913 rc = fwcmd->hdr.u0.rsp.status;
914 if (rc)
915 device_printf(sc->dev,
916 "%s failed - cmd status: %d addi status: %d\n",
917 __FUNCTION__, rc,
918 fwcmd->hdr.u0.rsp.additional_status);
919 return rc;
920 }
921
922 /**
923 * @brief Function to query the link status from the hardware
924 * @param sc software handle to the device
925 * @param[out] link pointer to the structure returning link attributes
926 * @returns 0 on success, EIO on failure
927 */
928 int
oce_get_link_status(POCE_SOFTC sc,struct link_status * link)929 oce_get_link_status(POCE_SOFTC sc, struct link_status *link)
930 {
931 struct oce_mbx mbx;
932 struct mbx_query_common_link_config *fwcmd;
933 int rc = 0, version;
934
935 bzero(&mbx, sizeof(struct oce_mbx));
936
937 IS_BE2(sc) ? (version = OCE_MBX_VER_V0) : (version = OCE_MBX_VER_V1);
938
939 fwcmd = (struct mbx_query_common_link_config *)&mbx.payload;
940 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
941 MBX_SUBSYSTEM_COMMON,
942 OPCODE_COMMON_QUERY_LINK_CONFIG,
943 MBX_TIMEOUT_SEC,
944 sizeof(struct mbx_query_common_link_config),
945 version);
946
947 mbx.u0.s.embedded = 1;
948 mbx.payload_length = sizeof(struct mbx_query_common_link_config);
949 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
950
951 rc = oce_mbox_post(sc, &mbx, NULL);
952
953 if (!rc)
954 rc = fwcmd->hdr.u0.rsp.status;
955 if (rc) {
956 device_printf(sc->dev,
957 "%s failed - cmd status: %d addi status: %d\n",
958 __FUNCTION__, rc,
959 fwcmd->hdr.u0.rsp.additional_status);
960 goto error;
961 }
962 /* interpret response */
963 link->qos_link_speed = HOST_16(fwcmd->params.rsp.qos_link_speed);
964 link->phys_port_speed = fwcmd->params.rsp.physical_port_speed;
965 link->logical_link_status = fwcmd->params.rsp.logical_link_status;
966 error:
967 return rc;
968 }
969
970
971
972 int
oce_mbox_get_nic_stats_v0(POCE_SOFTC sc,POCE_DMA_MEM pstats_dma_mem)973 oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem)
974 {
975 struct oce_mbx mbx;
976 struct mbx_get_nic_stats_v0 *fwcmd;
977 int rc = 0;
978
979 bzero(&mbx, sizeof(struct oce_mbx));
980
981 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats_v0);
982 bzero(fwcmd, sizeof(struct mbx_get_nic_stats_v0));
983
984 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
985 MBX_SUBSYSTEM_NIC,
986 NIC_GET_STATS,
987 MBX_TIMEOUT_SEC,
988 sizeof(struct mbx_get_nic_stats_v0),
989 OCE_MBX_VER_V0);
990
991 mbx.u0.s.embedded = 0;
992 mbx.u0.s.sge_count = 1;
993
994 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
995
996 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
997 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
998 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_nic_stats_v0);
999
1000 mbx.payload_length = sizeof(struct mbx_get_nic_stats_v0);
1001
1002 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1003
1004 rc = oce_mbox_post(sc, &mbx, NULL);
1005
1006 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1007
1008 if (!rc)
1009 rc = fwcmd->hdr.u0.rsp.status;
1010 if (rc)
1011 device_printf(sc->dev,
1012 "%s failed - cmd status: %d addi status: %d\n",
1013 __FUNCTION__, rc,
1014 fwcmd->hdr.u0.rsp.additional_status);
1015 return rc;
1016 }
1017
1018
1019
1020 /**
1021 * @brief Function to get NIC statistics
1022 * @param sc software handle to the device
1023 * @param *stats pointer to where to store statistics
1024 * @param reset_stats resets statistics of set
1025 * @returns 0 on success, EIO on failure
1026 * @note command depricated in Lancer
1027 */
1028 int
oce_mbox_get_nic_stats(POCE_SOFTC sc,POCE_DMA_MEM pstats_dma_mem)1029 oce_mbox_get_nic_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem)
1030 {
1031 struct oce_mbx mbx;
1032 struct mbx_get_nic_stats *fwcmd;
1033 int rc = 0;
1034
1035 bzero(&mbx, sizeof(struct oce_mbx));
1036 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats);
1037 bzero(fwcmd, sizeof(struct mbx_get_nic_stats));
1038
1039 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1040 MBX_SUBSYSTEM_NIC,
1041 NIC_GET_STATS,
1042 MBX_TIMEOUT_SEC,
1043 sizeof(struct mbx_get_nic_stats),
1044 OCE_MBX_VER_V1);
1045
1046
1047 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1048 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1049
1050 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1051 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1052 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1053 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_nic_stats);
1054
1055 mbx.payload_length = sizeof(struct mbx_get_nic_stats);
1056 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1057
1058 rc = oce_mbox_post(sc, &mbx, NULL);
1059 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1060 if (!rc)
1061 rc = fwcmd->hdr.u0.rsp.status;
1062 if (rc)
1063 device_printf(sc->dev,
1064 "%s failed - cmd status: %d addi status: %d\n",
1065 __FUNCTION__, rc,
1066 fwcmd->hdr.u0.rsp.additional_status);
1067 return rc;
1068 }
1069
1070
1071 /**
1072 * @brief Function to get pport (physical port) statistics
1073 * @param sc software handle to the device
1074 * @param *stats pointer to where to store statistics
1075 * @param reset_stats resets statistics of set
1076 * @returns 0 on success, EIO on failure
1077 */
1078 int
oce_mbox_get_pport_stats(POCE_SOFTC sc,POCE_DMA_MEM pstats_dma_mem,uint32_t reset_stats)1079 oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1080 uint32_t reset_stats)
1081 {
1082 struct oce_mbx mbx;
1083 struct mbx_get_pport_stats *fwcmd;
1084 int rc = 0;
1085
1086 bzero(&mbx, sizeof(struct oce_mbx));
1087 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_pport_stats);
1088 bzero(fwcmd, sizeof(struct mbx_get_pport_stats));
1089
1090 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1091 MBX_SUBSYSTEM_NIC,
1092 NIC_GET_PPORT_STATS,
1093 MBX_TIMEOUT_SEC,
1094 sizeof(struct mbx_get_pport_stats),
1095 OCE_MBX_VER_V0);
1096
1097 fwcmd->params.req.reset_stats = reset_stats;
1098 fwcmd->params.req.port_number = sc->port_id;
1099
1100 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1101 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1102
1103 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1104 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1105 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1106 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_pport_stats);
1107
1108 mbx.payload_length = sizeof(struct mbx_get_pport_stats);
1109 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1110
1111 rc = oce_mbox_post(sc, &mbx, NULL);
1112 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1113
1114 if (!rc)
1115 rc = fwcmd->hdr.u0.rsp.status;
1116 if (rc)
1117 device_printf(sc->dev,
1118 "%s failed - cmd status: %d addi status: %d\n",
1119 __FUNCTION__, rc,
1120 fwcmd->hdr.u0.rsp.additional_status);
1121 return rc;
1122 }
1123
1124
1125 /**
1126 * @brief Function to get vport (virtual port) statistics
1127 * @param sc software handle to the device
1128 * @param *stats pointer to where to store statistics
1129 * @param reset_stats resets statistics of set
1130 * @returns 0 on success, EIO on failure
1131 */
1132 int
oce_mbox_get_vport_stats(POCE_SOFTC sc,POCE_DMA_MEM pstats_dma_mem,uint32_t req_size,uint32_t reset_stats)1133 oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1134 uint32_t req_size, uint32_t reset_stats)
1135 {
1136 struct oce_mbx mbx;
1137 struct mbx_get_vport_stats *fwcmd;
1138 int rc = 0;
1139
1140 bzero(&mbx, sizeof(struct oce_mbx));
1141
1142 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_vport_stats);
1143 bzero(fwcmd, sizeof(struct mbx_get_vport_stats));
1144
1145 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1146 MBX_SUBSYSTEM_NIC,
1147 NIC_GET_VPORT_STATS,
1148 MBX_TIMEOUT_SEC,
1149 sizeof(struct mbx_get_vport_stats),
1150 OCE_MBX_VER_V0);
1151
1152 fwcmd->params.req.reset_stats = reset_stats;
1153 fwcmd->params.req.vport_number = sc->if_id;
1154
1155 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1156 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1157
1158 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1159 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1160 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1161 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_vport_stats);
1162
1163 mbx.payload_length = sizeof(struct mbx_get_vport_stats);
1164 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1165
1166 rc = oce_mbox_post(sc, &mbx, NULL);
1167 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1168
1169 if (!rc)
1170 rc = fwcmd->hdr.u0.rsp.status;
1171 if (rc)
1172 device_printf(sc->dev,
1173 "%s failed - cmd status: %d addi status: %d\n",
1174 __FUNCTION__, rc,
1175 fwcmd->hdr.u0.rsp.additional_status);
1176 return rc;
1177 }
1178
1179
1180 /**
1181 * @brief Function to update the muticast filter with
1182 * values in dma_mem
1183 * @param sc software handle to the device
1184 * @param dma_mem pointer to dma memory region
1185 * @returns 0 on success, EIO on failure
1186 */
1187 int
oce_update_multicast(POCE_SOFTC sc,POCE_DMA_MEM pdma_mem)1188 oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem)
1189 {
1190 struct oce_mbx mbx;
1191 struct oce_mq_sge *sgl;
1192 struct mbx_set_common_iface_multicast *req = NULL;
1193 int rc = 0;
1194
1195 req = OCE_DMAPTR(pdma_mem, struct mbx_set_common_iface_multicast);
1196 mbx_common_req_hdr_init(&req->hdr, 0, 0,
1197 MBX_SUBSYSTEM_COMMON,
1198 OPCODE_COMMON_SET_IFACE_MULTICAST,
1199 MBX_TIMEOUT_SEC,
1200 sizeof(struct mbx_set_common_iface_multicast),
1201 OCE_MBX_VER_V0);
1202
1203 bzero(&mbx, sizeof(struct oce_mbx));
1204
1205 mbx.u0.s.embedded = 0; /*Non embeded*/
1206 mbx.payload_length = sizeof(struct mbx_set_common_iface_multicast);
1207 mbx.u0.s.sge_count = 1;
1208 sgl = &mbx.payload.u0.u1.sgl[0];
1209 sgl->pa_hi = htole32(upper_32_bits(pdma_mem->paddr));
1210 sgl->pa_lo = htole32((pdma_mem->paddr) & 0xFFFFFFFF);
1211 sgl->length = htole32(mbx.payload_length);
1212
1213 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1214
1215 rc = oce_mbox_post(sc, &mbx, NULL);
1216 if (!rc)
1217 rc = req->hdr.u0.rsp.status;
1218 if (rc)
1219 device_printf(sc->dev,
1220 "%s failed - cmd status: %d addi status: %d\n",
1221 __FUNCTION__, rc,
1222 req->hdr.u0.rsp.additional_status);
1223 return rc;
1224 }
1225
1226
1227 /**
1228 * @brief Function to send passthrough Ioctls
1229 * @param sc software handle to the device
1230 * @param dma_mem pointer to dma memory region
1231 * @param req_size size of dma_mem
1232 * @returns 0 on success, EIO on failure
1233 */
1234 int
oce_pass_through_mbox(POCE_SOFTC sc,POCE_DMA_MEM dma_mem,uint32_t req_size)1235 oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size)
1236 {
1237 struct oce_mbx mbx;
1238 struct oce_mq_sge *sgl;
1239 int rc = 0;
1240
1241 bzero(&mbx, sizeof(struct oce_mbx));
1242
1243 mbx.u0.s.embedded = 0; /*Non embeded*/
1244 mbx.payload_length = req_size;
1245 mbx.u0.s.sge_count = 1;
1246 sgl = &mbx.payload.u0.u1.sgl[0];
1247 sgl->pa_hi = htole32(upper_32_bits(dma_mem->paddr));
1248 sgl->pa_lo = htole32((dma_mem->paddr) & 0xFFFFFFFF);
1249 sgl->length = htole32(req_size);
1250
1251 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1252
1253 rc = oce_mbox_post(sc, &mbx, NULL);
1254 return rc;
1255 }
1256
1257
1258 int
oce_mbox_macaddr_add(POCE_SOFTC sc,uint8_t * mac_addr,uint32_t if_id,uint32_t * pmac_id)1259 oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr,
1260 uint32_t if_id, uint32_t *pmac_id)
1261 {
1262 struct oce_mbx mbx;
1263 struct mbx_add_common_iface_mac *fwcmd;
1264 int rc = 0;
1265
1266 bzero(&mbx, sizeof(struct oce_mbx));
1267
1268 fwcmd = (struct mbx_add_common_iface_mac *)&mbx.payload;
1269 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1270 MBX_SUBSYSTEM_COMMON,
1271 OPCODE_COMMON_ADD_IFACE_MAC,
1272 MBX_TIMEOUT_SEC,
1273 sizeof(struct mbx_add_common_iface_mac),
1274 OCE_MBX_VER_V0);
1275
1276 fwcmd->params.req.if_id = (uint16_t) if_id;
1277 bcopy(mac_addr, fwcmd->params.req.mac_address, 6);
1278
1279 mbx.u0.s.embedded = 1;
1280 mbx.payload_length = sizeof(struct mbx_add_common_iface_mac);
1281 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1282 rc = oce_mbox_post(sc, &mbx, NULL);
1283 if (!rc)
1284 rc = fwcmd->hdr.u0.rsp.status;
1285 if (rc) {
1286 device_printf(sc->dev,
1287 "%s failed - cmd status: %d addi status: %d\n",
1288 __FUNCTION__, rc,
1289 fwcmd->hdr.u0.rsp.additional_status);
1290 goto error;
1291 }
1292 *pmac_id = fwcmd->params.rsp.pmac_id;
1293 error:
1294 return rc;
1295 }
1296
1297
1298 int
oce_mbox_macaddr_del(POCE_SOFTC sc,uint32_t if_id,uint32_t pmac_id)1299 oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id)
1300 {
1301 struct oce_mbx mbx;
1302 struct mbx_del_common_iface_mac *fwcmd;
1303 int rc = 0;
1304
1305 bzero(&mbx, sizeof(struct oce_mbx));
1306
1307 fwcmd = (struct mbx_del_common_iface_mac *)&mbx.payload;
1308 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1309 MBX_SUBSYSTEM_COMMON,
1310 OPCODE_COMMON_DEL_IFACE_MAC,
1311 MBX_TIMEOUT_SEC,
1312 sizeof(struct mbx_del_common_iface_mac),
1313 OCE_MBX_VER_V0);
1314
1315 fwcmd->params.req.if_id = (uint16_t)if_id;
1316 fwcmd->params.req.pmac_id = pmac_id;
1317
1318 mbx.u0.s.embedded = 1;
1319 mbx.payload_length = sizeof(struct mbx_del_common_iface_mac);
1320 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1321
1322 rc = oce_mbox_post(sc, &mbx, NULL);
1323 if (!rc)
1324 rc = fwcmd->hdr.u0.rsp.status;
1325 if (rc)
1326 device_printf(sc->dev,
1327 "%s failed - cmd status: %d addi status: %d\n",
1328 __FUNCTION__, rc,
1329 fwcmd->hdr.u0.rsp.additional_status);
1330 return rc;
1331 }
1332
1333
1334
1335 int
oce_mbox_check_native_mode(POCE_SOFTC sc)1336 oce_mbox_check_native_mode(POCE_SOFTC sc)
1337 {
1338 struct oce_mbx mbx;
1339 struct mbx_common_set_function_cap *fwcmd;
1340 int rc = 0;
1341
1342 bzero(&mbx, sizeof(struct oce_mbx));
1343
1344 fwcmd = (struct mbx_common_set_function_cap *)&mbx.payload;
1345 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1346 MBX_SUBSYSTEM_COMMON,
1347 OPCODE_COMMON_SET_FUNCTIONAL_CAPS,
1348 MBX_TIMEOUT_SEC,
1349 sizeof(struct mbx_common_set_function_cap),
1350 OCE_MBX_VER_V0);
1351
1352 fwcmd->params.req.valid_capability_flags = CAP_SW_TIMESTAMPS |
1353 CAP_BE3_NATIVE_ERX_API;
1354
1355 fwcmd->params.req.capability_flags = CAP_BE3_NATIVE_ERX_API;
1356
1357 mbx.u0.s.embedded = 1;
1358 mbx.payload_length = sizeof(struct mbx_common_set_function_cap);
1359 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1360
1361 rc = oce_mbox_post(sc, &mbx, NULL);
1362 if (!rc)
1363 rc = fwcmd->hdr.u0.rsp.status;
1364 if (rc) {
1365 device_printf(sc->dev,
1366 "%s failed - cmd status: %d addi status: %d\n",
1367 __FUNCTION__, rc,
1368 fwcmd->hdr.u0.rsp.additional_status);
1369 goto error;
1370 }
1371 sc->be3_native = HOST_32(fwcmd->params.rsp.capability_flags)
1372 & CAP_BE3_NATIVE_ERX_API;
1373
1374 error:
1375 return 0;
1376 }
1377
1378
1379
1380 int
oce_mbox_cmd_set_loopback(POCE_SOFTC sc,uint8_t port_num,uint8_t loopback_type,uint8_t enable)1381 oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num,
1382 uint8_t loopback_type, uint8_t enable)
1383 {
1384 struct oce_mbx mbx;
1385 struct mbx_lowlevel_set_loopback_mode *fwcmd;
1386 int rc = 0;
1387
1388
1389 bzero(&mbx, sizeof(struct oce_mbx));
1390
1391 fwcmd = (struct mbx_lowlevel_set_loopback_mode *)&mbx.payload;
1392 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1393 MBX_SUBSYSTEM_LOWLEVEL,
1394 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1395 MBX_TIMEOUT_SEC,
1396 sizeof(struct mbx_lowlevel_set_loopback_mode),
1397 OCE_MBX_VER_V0);
1398
1399 fwcmd->params.req.src_port = port_num;
1400 fwcmd->params.req.dest_port = port_num;
1401 fwcmd->params.req.loopback_type = loopback_type;
1402 fwcmd->params.req.loopback_state = enable;
1403
1404 mbx.u0.s.embedded = 1;
1405 mbx.payload_length = sizeof(struct mbx_lowlevel_set_loopback_mode);
1406 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1407
1408 rc = oce_mbox_post(sc, &mbx, NULL);
1409 if (!rc)
1410 rc = fwcmd->hdr.u0.rsp.status;
1411 if (rc)
1412 device_printf(sc->dev,
1413 "%s failed - cmd status: %d addi status: %d\n",
1414 __FUNCTION__, rc,
1415 fwcmd->hdr.u0.rsp.additional_status);
1416
1417 return rc;
1418
1419 }
1420
1421 int
oce_mbox_cmd_test_loopback(POCE_SOFTC sc,uint32_t port_num,uint32_t loopback_type,uint32_t pkt_size,uint32_t num_pkts,uint64_t pattern)1422 oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num,
1423 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts,
1424 uint64_t pattern)
1425 {
1426
1427 struct oce_mbx mbx;
1428 struct mbx_lowlevel_test_loopback_mode *fwcmd;
1429 int rc = 0;
1430
1431
1432 bzero(&mbx, sizeof(struct oce_mbx));
1433
1434 fwcmd = (struct mbx_lowlevel_test_loopback_mode *)&mbx.payload;
1435 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1436 MBX_SUBSYSTEM_LOWLEVEL,
1437 OPCODE_LOWLEVEL_TEST_LOOPBACK,
1438 MBX_TIMEOUT_SEC,
1439 sizeof(struct mbx_lowlevel_test_loopback_mode),
1440 OCE_MBX_VER_V0);
1441
1442 fwcmd->params.req.pattern = pattern;
1443 fwcmd->params.req.src_port = port_num;
1444 fwcmd->params.req.dest_port = port_num;
1445 fwcmd->params.req.pkt_size = pkt_size;
1446 fwcmd->params.req.num_pkts = num_pkts;
1447 fwcmd->params.req.loopback_type = loopback_type;
1448
1449 mbx.u0.s.embedded = 1;
1450 mbx.payload_length = sizeof(struct mbx_lowlevel_test_loopback_mode);
1451 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1452
1453 rc = oce_mbox_post(sc, &mbx, NULL);
1454 if (!rc)
1455 rc = fwcmd->hdr.u0.rsp.status;
1456 if (rc)
1457 device_printf(sc->dev,
1458 "%s failed - cmd status: %d addi status: %d\n",
1459 __FUNCTION__, rc,
1460 fwcmd->hdr.u0.rsp.additional_status);
1461
1462 return rc;
1463 }
1464
1465 int
oce_mbox_write_flashrom(POCE_SOFTC sc,uint32_t optype,uint32_t opcode,POCE_DMA_MEM pdma_mem,uint32_t num_bytes)1466 oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode,
1467 POCE_DMA_MEM pdma_mem, uint32_t num_bytes)
1468 {
1469
1470 struct oce_mbx mbx;
1471 struct oce_mq_sge *sgl = NULL;
1472 struct mbx_common_read_write_flashrom *fwcmd = NULL;
1473 int rc = 0, payload_len = 0;
1474
1475 bzero(&mbx, sizeof(struct oce_mbx));
1476 fwcmd = OCE_DMAPTR(pdma_mem, struct mbx_common_read_write_flashrom);
1477 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 32*1024;
1478
1479 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1480 MBX_SUBSYSTEM_COMMON,
1481 OPCODE_COMMON_WRITE_FLASHROM,
1482 LONG_TIMEOUT,
1483 payload_len,
1484 OCE_MBX_VER_V0);
1485
1486 fwcmd->flash_op_type = LE_32(optype);
1487 fwcmd->flash_op_code = LE_32(opcode);
1488 fwcmd->data_buffer_size = LE_32(num_bytes);
1489
1490 mbx.u0.s.embedded = 0; /*Non embeded*/
1491 mbx.payload_length = payload_len;
1492 mbx.u0.s.sge_count = 1;
1493
1494 sgl = &mbx.payload.u0.u1.sgl[0];
1495 sgl->pa_hi = upper_32_bits(pdma_mem->paddr);
1496 sgl->pa_lo = pdma_mem->paddr & 0xFFFFFFFF;
1497 sgl->length = payload_len;
1498
1499 /* post the command */
1500 rc = oce_mbox_post(sc, &mbx, NULL);
1501 if (!rc)
1502 rc = fwcmd->hdr.u0.rsp.status;
1503 if (rc)
1504 device_printf(sc->dev,
1505 "%s failed - cmd status: %d addi status: %d\n",
1506 __FUNCTION__, rc,
1507 fwcmd->hdr.u0.rsp.additional_status);
1508
1509 return rc;
1510
1511 }
1512
1513 int
oce_mbox_get_flashrom_crc(POCE_SOFTC sc,uint8_t * flash_crc,uint32_t offset,uint32_t optype)1514 oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc,
1515 uint32_t offset, uint32_t optype)
1516 {
1517
1518 int rc = 0, payload_len = 0;
1519 struct oce_mbx mbx;
1520 struct mbx_common_read_write_flashrom *fwcmd;
1521
1522 bzero(&mbx, sizeof(struct oce_mbx));
1523
1524 fwcmd = (struct mbx_common_read_write_flashrom *)&mbx.payload;
1525
1526 /* Firmware requires extra 4 bytes with this ioctl. Since there
1527 is enough room in the mbx payload it should be good enough
1528 Reference: Bug 14853
1529 */
1530 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 4;
1531
1532 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1533 MBX_SUBSYSTEM_COMMON,
1534 OPCODE_COMMON_READ_FLASHROM,
1535 MBX_TIMEOUT_SEC,
1536 payload_len,
1537 OCE_MBX_VER_V0);
1538
1539 fwcmd->flash_op_type = optype;
1540 fwcmd->flash_op_code = FLASHROM_OPER_REPORT;
1541 fwcmd->data_offset = offset;
1542 fwcmd->data_buffer_size = 0x4;
1543
1544 mbx.u0.s.embedded = 1;
1545 mbx.payload_length = payload_len;
1546
1547 /* post the command */
1548 rc = oce_mbox_post(sc, &mbx, NULL);
1549 if (!rc)
1550 rc = fwcmd->hdr.u0.rsp.status;
1551 if (rc) {
1552 device_printf(sc->dev,
1553 "%s failed - cmd status: %d addi status: %d\n",
1554 __FUNCTION__, rc,
1555 fwcmd->hdr.u0.rsp.additional_status);
1556 goto error;
1557 }
1558 bcopy(fwcmd->data_buffer, flash_crc, 4);
1559 error:
1560 return rc;
1561 }
1562
1563 int
oce_mbox_get_phy_info(POCE_SOFTC sc,struct oce_phy_info * phy_info)1564 oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info)
1565 {
1566
1567 struct oce_mbx mbx;
1568 struct mbx_common_phy_info *fwcmd;
1569 int rc = 0;
1570
1571 bzero(&mbx, sizeof(struct oce_mbx));
1572
1573 fwcmd = (struct mbx_common_phy_info *)&mbx.payload;
1574 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1575 MBX_SUBSYSTEM_COMMON,
1576 OPCODE_COMMON_GET_PHY_CONFIG,
1577 MBX_TIMEOUT_SEC,
1578 sizeof(struct mbx_common_phy_info),
1579 OCE_MBX_VER_V0);
1580
1581 mbx.u0.s.embedded = 1;
1582 mbx.payload_length = sizeof(struct mbx_common_phy_info);
1583
1584 /* now post the command */
1585 rc = oce_mbox_post(sc, &mbx, NULL);
1586 if (!rc)
1587 rc = fwcmd->hdr.u0.rsp.status;
1588 if (rc) {
1589 device_printf(sc->dev,
1590 "%s failed - cmd status: %d addi status: %d\n",
1591 __FUNCTION__, rc,
1592 fwcmd->hdr.u0.rsp.additional_status);
1593 goto error;
1594 }
1595 phy_info->phy_type = HOST_16(fwcmd->params.rsp.phy_info.phy_type);
1596 phy_info->interface_type =
1597 HOST_16(fwcmd->params.rsp.phy_info.interface_type);
1598 phy_info->auto_speeds_supported =
1599 HOST_16(fwcmd->params.rsp.phy_info.auto_speeds_supported);
1600 phy_info->fixed_speeds_supported =
1601 HOST_16(fwcmd->params.rsp.phy_info.fixed_speeds_supported);
1602 phy_info->misc_params = HOST_32(fwcmd->params.rsp.phy_info.misc_params);
1603 error:
1604 return rc;
1605
1606 }
1607
1608
1609 int
oce_mbox_lancer_write_flashrom(POCE_SOFTC sc,uint32_t data_size,uint32_t data_offset,POCE_DMA_MEM pdma_mem,uint32_t * written_data,uint32_t * additional_status)1610 oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size,
1611 uint32_t data_offset, POCE_DMA_MEM pdma_mem,
1612 uint32_t *written_data, uint32_t *additional_status)
1613 {
1614
1615 struct oce_mbx mbx;
1616 struct mbx_lancer_common_write_object *fwcmd = NULL;
1617 int rc = 0, payload_len = 0;
1618
1619 bzero(&mbx, sizeof(struct oce_mbx));
1620 payload_len = sizeof(struct mbx_lancer_common_write_object);
1621
1622 mbx.u0.s.embedded = 1;/* Embedded */
1623 mbx.payload_length = payload_len;
1624 fwcmd = (struct mbx_lancer_common_write_object *)&mbx.payload;
1625
1626 /* initialize the ioctl header */
1627 mbx_common_req_hdr_init(&fwcmd->params.req.hdr, 0, 0,
1628 MBX_SUBSYSTEM_COMMON,
1629 OPCODE_COMMON_WRITE_OBJECT,
1630 LONG_TIMEOUT,
1631 payload_len,
1632 OCE_MBX_VER_V0);
1633
1634 fwcmd->params.req.write_length = data_size;
1635 if (data_size == 0)
1636 fwcmd->params.req.eof = 1;
1637 else
1638 fwcmd->params.req.eof = 0;
1639
1640 strcpy(fwcmd->params.req.object_name, "/prg");
1641 fwcmd->params.req.descriptor_count = 1;
1642 fwcmd->params.req.write_offset = data_offset;
1643 fwcmd->params.req.buffer_length = data_size;
1644 fwcmd->params.req.address_lower = pdma_mem->paddr & 0xFFFFFFFF;
1645 fwcmd->params.req.address_upper = upper_32_bits(pdma_mem->paddr);
1646
1647 /* post the command */
1648 rc = oce_mbox_post(sc, &mbx, NULL);
1649 if (!rc)
1650 rc = fwcmd->params.rsp.status;
1651 if (rc) {
1652 device_printf(sc->dev,
1653 "%s failed - cmd status: %d addi status: %d\n",
1654 __FUNCTION__, rc,
1655 fwcmd->params.rsp.additional_status);
1656 goto error;
1657 }
1658 *written_data = HOST_32(fwcmd->params.rsp.actual_write_length);
1659 *additional_status = fwcmd->params.rsp.additional_status;
1660 error:
1661 return rc;
1662
1663 }
1664
1665
1666
1667 int
oce_mbox_create_rq(struct oce_rq * rq)1668 oce_mbox_create_rq(struct oce_rq *rq)
1669 {
1670
1671 struct oce_mbx mbx;
1672 struct mbx_create_nic_rq *fwcmd;
1673 POCE_SOFTC sc = rq->parent;
1674 int rc, num_pages = 0;
1675
1676 if (rq->qstate == QCREATED)
1677 return 0;
1678
1679 bzero(&mbx, sizeof(struct oce_mbx));
1680
1681 fwcmd = (struct mbx_create_nic_rq *)&mbx.payload;
1682 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1683 MBX_SUBSYSTEM_NIC,
1684 NIC_CREATE_RQ, MBX_TIMEOUT_SEC,
1685 sizeof(struct mbx_create_nic_rq),
1686 OCE_MBX_VER_V0);
1687
1688 /* oce_page_list will also prepare pages */
1689 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]);
1690
1691 if (IS_XE201(sc)) {
1692 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048;
1693 fwcmd->params.req.page_size = 1;
1694 fwcmd->hdr.u0.req.version = OCE_MBX_VER_V1;
1695 } else
1696 fwcmd->params.req.frag_size = OCE_LOG2(rq->cfg.frag_size);
1697 fwcmd->params.req.num_pages = num_pages;
1698 fwcmd->params.req.cq_id = rq->cq->cq_id;
1699 fwcmd->params.req.if_id = sc->if_id;
1700 fwcmd->params.req.max_frame_size = rq->cfg.mtu;
1701 fwcmd->params.req.is_rss_queue = rq->cfg.is_rss_queue;
1702
1703 mbx.u0.s.embedded = 1;
1704 mbx.payload_length = sizeof(struct mbx_create_nic_rq);
1705
1706 rc = oce_mbox_post(sc, &mbx, NULL);
1707 if (!rc)
1708 rc = fwcmd->hdr.u0.rsp.status;
1709 if (rc) {
1710 device_printf(sc->dev,
1711 "%s failed - cmd status: %d addi status: %d\n",
1712 __FUNCTION__, rc,
1713 fwcmd->hdr.u0.rsp.additional_status);
1714 goto error;
1715 }
1716 rq->rq_id = HOST_16(fwcmd->params.rsp.rq_id);
1717 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid;
1718 error:
1719 return rc;
1720
1721 }
1722
1723
1724
1725 int
oce_mbox_create_wq(struct oce_wq * wq)1726 oce_mbox_create_wq(struct oce_wq *wq)
1727 {
1728 struct oce_mbx mbx;
1729 struct mbx_create_nic_wq *fwcmd;
1730 POCE_SOFTC sc = wq->parent;
1731 int rc = 0, version, num_pages;
1732
1733 bzero(&mbx, sizeof(struct oce_mbx));
1734
1735 fwcmd = (struct mbx_create_nic_wq *)&mbx.payload;
1736 if (IS_XE201(sc))
1737 version = OCE_MBX_VER_V1;
1738 else if(IS_BE(sc))
1739 IS_PROFILE_SUPER_NIC(sc) ? (version = OCE_MBX_VER_V2)
1740 : (version = OCE_MBX_VER_V0);
1741 else
1742 version = OCE_MBX_VER_V2;
1743
1744 if (version > OCE_MBX_VER_V0)
1745 fwcmd->params.req.if_id = sc->if_id;
1746
1747 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1748 MBX_SUBSYSTEM_NIC,
1749 NIC_CREATE_WQ, MBX_TIMEOUT_SEC,
1750 sizeof(struct mbx_create_nic_wq),
1751 version);
1752
1753 num_pages = oce_page_list(wq->ring, &fwcmd->params.req.pages[0]);
1754
1755 fwcmd->params.req.nic_wq_type = wq->cfg.wq_type;
1756 fwcmd->params.req.num_pages = num_pages;
1757 fwcmd->params.req.wq_size = OCE_LOG2(wq->cfg.q_len) + 1;
1758 fwcmd->params.req.cq_id = wq->cq->cq_id;
1759 fwcmd->params.req.ulp_num = 1;
1760
1761 mbx.u0.s.embedded = 1;
1762 mbx.payload_length = sizeof(struct mbx_create_nic_wq);
1763
1764 rc = oce_mbox_post(sc, &mbx, NULL);
1765 if (!rc)
1766 rc = fwcmd->hdr.u0.rsp.status;
1767 if (rc) {
1768 device_printf(sc->dev,
1769 "%s failed - cmd status: %d addi status: %d\n",
1770 __FUNCTION__, rc,
1771 fwcmd->hdr.u0.rsp.additional_status);
1772 goto error;
1773 }
1774 wq->wq_id = HOST_16(fwcmd->params.rsp.wq_id);
1775 if (version == OCE_MBX_VER_V2)
1776 wq->db_offset = HOST_32(fwcmd->params.rsp.db_offset);
1777 else
1778 wq->db_offset = PD_TXULP_DB;
1779 error:
1780 return rc;
1781
1782 }
1783
1784
1785
1786 int
oce_mbox_create_eq(struct oce_eq * eq)1787 oce_mbox_create_eq(struct oce_eq *eq)
1788 {
1789 struct oce_mbx mbx;
1790 struct mbx_create_common_eq *fwcmd;
1791 POCE_SOFTC sc = eq->parent;
1792 int rc = 0;
1793 uint32_t num_pages;
1794
1795 bzero(&mbx, sizeof(struct oce_mbx));
1796
1797 fwcmd = (struct mbx_create_common_eq *)&mbx.payload;
1798
1799 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1800 MBX_SUBSYSTEM_COMMON,
1801 OPCODE_COMMON_CREATE_EQ, MBX_TIMEOUT_SEC,
1802 sizeof(struct mbx_create_common_eq),
1803 OCE_MBX_VER_V0);
1804
1805 num_pages = oce_page_list(eq->ring, &fwcmd->params.req.pages[0]);
1806 fwcmd->params.req.ctx.num_pages = num_pages;
1807 fwcmd->params.req.ctx.valid = 1;
1808 fwcmd->params.req.ctx.size = (eq->eq_cfg.item_size == 4) ? 0 : 1;
1809 fwcmd->params.req.ctx.count = OCE_LOG2(eq->eq_cfg.q_len / 256);
1810 fwcmd->params.req.ctx.armed = 0;
1811 fwcmd->params.req.ctx.delay_mult = eq->eq_cfg.cur_eqd;
1812
1813
1814 mbx.u0.s.embedded = 1;
1815 mbx.payload_length = sizeof(struct mbx_create_common_eq);
1816
1817 rc = oce_mbox_post(sc, &mbx, NULL);
1818 if (!rc)
1819 rc = fwcmd->hdr.u0.rsp.status;
1820 if (rc) {
1821 device_printf(sc->dev,
1822 "%s failed - cmd status: %d addi status: %d\n",
1823 __FUNCTION__, rc,
1824 fwcmd->hdr.u0.rsp.additional_status);
1825 goto error;
1826 }
1827 eq->eq_id = HOST_16(fwcmd->params.rsp.eq_id);
1828 error:
1829 return rc;
1830 }
1831
1832
1833
1834 int
oce_mbox_cq_create(struct oce_cq * cq,uint32_t ncoalesce,uint32_t is_eventable)1835 oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, uint32_t is_eventable)
1836 {
1837 struct oce_mbx mbx;
1838 struct mbx_create_common_cq *fwcmd;
1839 POCE_SOFTC sc = cq->parent;
1840 uint8_t version;
1841 oce_cq_ctx_t *ctx;
1842 uint32_t num_pages, page_size;
1843 int rc = 0;
1844
1845
1846 bzero(&mbx, sizeof(struct oce_mbx));
1847
1848 fwcmd = (struct mbx_create_common_cq *)&mbx.payload;
1849
1850 if (IS_XE201(sc))
1851 version = OCE_MBX_VER_V2;
1852 else
1853 version = OCE_MBX_VER_V0;
1854
1855 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1856 MBX_SUBSYSTEM_COMMON,
1857 OPCODE_COMMON_CREATE_CQ,
1858 MBX_TIMEOUT_SEC,
1859 sizeof(struct mbx_create_common_cq),
1860 version);
1861
1862 ctx = &fwcmd->params.req.cq_ctx;
1863
1864 num_pages = oce_page_list(cq->ring, &fwcmd->params.req.pages[0]);
1865 page_size = 1; /* 1 for 4K */
1866
1867 if (version == OCE_MBX_VER_V2) {
1868 ctx->v2.num_pages = LE_16(num_pages);
1869 ctx->v2.page_size = page_size;
1870 ctx->v2.eventable = is_eventable;
1871 ctx->v2.valid = 1;
1872 ctx->v2.count = OCE_LOG2(cq->cq_cfg.q_len / 256);
1873 ctx->v2.nodelay = cq->cq_cfg.nodelay;
1874 ctx->v2.coalesce_wm = ncoalesce;
1875 ctx->v2.armed = 0;
1876 ctx->v2.eq_id = cq->eq->eq_id;
1877 if (ctx->v2.count == 3) {
1878 if ((u_int)cq->cq_cfg.q_len > (4*1024)-1)
1879 ctx->v2.cqe_count = (4*1024)-1;
1880 else
1881 ctx->v2.cqe_count = cq->cq_cfg.q_len;
1882 }
1883 } else {
1884 ctx->v0.num_pages = LE_16(num_pages);
1885 ctx->v0.eventable = is_eventable;
1886 ctx->v0.valid = 1;
1887 ctx->v0.count = OCE_LOG2(cq->cq_cfg.q_len / 256);
1888 ctx->v0.nodelay = cq->cq_cfg.nodelay;
1889 ctx->v0.coalesce_wm = ncoalesce;
1890 ctx->v0.armed = 0;
1891 ctx->v0.eq_id = cq->eq->eq_id;
1892 }
1893
1894 mbx.u0.s.embedded = 1;
1895 mbx.payload_length = sizeof(struct mbx_create_common_cq);
1896
1897 rc = oce_mbox_post(sc, &mbx, NULL);
1898 if (!rc)
1899 rc = fwcmd->hdr.u0.rsp.status;
1900 if (rc) {
1901 device_printf(sc->dev,
1902 "%s failed - cmd status: %d addi status: %d\n",
1903 __FUNCTION__, rc,
1904 fwcmd->hdr.u0.rsp.additional_status);
1905 goto error;
1906 }
1907 cq->cq_id = HOST_16(fwcmd->params.rsp.cq_id);
1908 error:
1909 return rc;
1910
1911 }
1912
1913 int
oce_mbox_read_transrecv_data(POCE_SOFTC sc,uint32_t page_num)1914 oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num)
1915 {
1916 int rc = 0;
1917 struct oce_mbx mbx;
1918 struct mbx_read_common_transrecv_data *fwcmd;
1919 struct oce_mq_sge *sgl;
1920 OCE_DMA_MEM dma;
1921
1922 /* Allocate DMA mem*/
1923 if (oce_dma_alloc(sc, sizeof(struct mbx_read_common_transrecv_data),
1924 &dma, 0))
1925 return ENOMEM;
1926
1927 fwcmd = OCE_DMAPTR(&dma, struct mbx_read_common_transrecv_data);
1928 bzero(fwcmd, sizeof(struct mbx_read_common_transrecv_data));
1929
1930 bzero(&mbx, sizeof(struct oce_mbx));
1931 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1932 MBX_SUBSYSTEM_COMMON,
1933 OPCODE_COMMON_READ_TRANSRECEIVER_DATA,
1934 MBX_TIMEOUT_SEC,
1935 sizeof(struct mbx_read_common_transrecv_data),
1936 OCE_MBX_VER_V0);
1937
1938 /* fill rest of mbx */
1939 mbx.u0.s.embedded = 0;
1940 mbx.payload_length = sizeof(struct mbx_read_common_transrecv_data);
1941 mbx.u0.s.sge_count = 1;
1942 sgl = &mbx.payload.u0.u1.sgl[0];
1943 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
1944 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
1945 sgl->length = htole32(mbx.payload_length);
1946 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1947
1948 fwcmd->params.req.port = LE_32(sc->port_id);
1949 fwcmd->params.req.page_num = LE_32(page_num);
1950
1951 /* command post */
1952 rc = oce_mbox_post(sc, &mbx, NULL);
1953 if (!rc)
1954 rc = fwcmd->hdr.u0.rsp.status;
1955 if (rc) {
1956 device_printf(sc->dev,
1957 "%s failed - cmd status: %d addi status: %d\n",
1958 __FUNCTION__, rc,
1959 fwcmd->hdr.u0.rsp.additional_status);
1960 goto error;
1961 }
1962 if(fwcmd->params.rsp.page_num == PAGE_NUM_A0)
1963 {
1964 bcopy((char *)fwcmd->params.rsp.page_data,
1965 (char *)&sfp_vpd_dump_buffer[0],
1966 TRANSCEIVER_A0_SIZE);
1967 }
1968
1969 if(fwcmd->params.rsp.page_num == PAGE_NUM_A2)
1970 {
1971 bcopy((char *)fwcmd->params.rsp.page_data,
1972 (char *)&sfp_vpd_dump_buffer[32],
1973 TRANSCEIVER_A2_SIZE);
1974 }
1975 error:
1976 oce_dma_free(sc, &dma);
1977 return rc;
1978 }
1979
1980 void
oce_mbox_eqd_modify_periodic(POCE_SOFTC sc,struct oce_set_eqd * set_eqd,int num)1981 oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd,
1982 int num)
1983 {
1984 struct oce_mbx mbx;
1985 struct mbx_modify_common_eq_delay *fwcmd;
1986 int rc = 0;
1987 int i = 0;
1988
1989 bzero(&mbx, sizeof(struct oce_mbx));
1990
1991 /* Initialize MODIFY_EQ_DELAY ioctl header */
1992 fwcmd = (struct mbx_modify_common_eq_delay *)&mbx.payload;
1993 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1994 MBX_SUBSYSTEM_COMMON,
1995 OPCODE_COMMON_MODIFY_EQ_DELAY,
1996 MBX_TIMEOUT_SEC,
1997 sizeof(struct mbx_modify_common_eq_delay),
1998 OCE_MBX_VER_V0);
1999 /* fill rest of mbx */
2000 mbx.u0.s.embedded = 1;
2001 mbx.payload_length = sizeof(struct mbx_modify_common_eq_delay);
2002 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
2003
2004 fwcmd->params.req.num_eq = num;
2005 for (i = 0; i < num; i++) {
2006 fwcmd->params.req.delay[i].eq_id =
2007 htole32(set_eqd[i].eq_id);
2008 fwcmd->params.req.delay[i].phase = 0;
2009 fwcmd->params.req.delay[i].dm =
2010 htole32(set_eqd[i].delay_multiplier);
2011 }
2012
2013
2014 /* command post */
2015 rc = oce_mbox_post(sc, &mbx, NULL);
2016
2017 if (!rc)
2018 rc = fwcmd->hdr.u0.rsp.status;
2019 if (rc)
2020 device_printf(sc->dev,
2021 "%s failed - cmd status: %d addi status: %d\n",
2022 __FUNCTION__, rc,
2023 fwcmd->hdr.u0.rsp.additional_status);
2024 }
2025
2026 int
oce_get_profile_config(POCE_SOFTC sc,uint32_t max_rss)2027 oce_get_profile_config(POCE_SOFTC sc, uint32_t max_rss)
2028 {
2029 struct oce_mbx mbx;
2030 struct mbx_common_get_profile_config *fwcmd;
2031 int rc = 0;
2032 int version = 0;
2033 struct oce_mq_sge *sgl;
2034 OCE_DMA_MEM dma;
2035 uint32_t desc_count = 0;
2036 struct oce_nic_resc_desc *nic_desc = NULL;
2037 int i;
2038 boolean_t nic_desc_valid = FALSE;
2039
2040 if (IS_BE2(sc))
2041 return -1;
2042
2043 /* Allocate DMA mem*/
2044 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_profile_config),
2045 &dma, 0))
2046 return ENOMEM;
2047
2048 /* Initialize MODIFY_EQ_DELAY ioctl header */
2049 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_profile_config);
2050 bzero(fwcmd, sizeof(struct mbx_common_get_profile_config));
2051
2052 if (!IS_XE201(sc))
2053 version = OCE_MBX_VER_V1;
2054 else
2055 version = OCE_MBX_VER_V0;
2056
2057 bzero(&mbx, sizeof(struct oce_mbx));
2058 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2059 MBX_SUBSYSTEM_COMMON,
2060 OPCODE_COMMON_GET_PROFILE_CONFIG,
2061 MBX_TIMEOUT_SEC,
2062 sizeof(struct mbx_common_get_profile_config),
2063 version);
2064 /* fill rest of mbx */
2065 mbx.u0.s.embedded = 0;
2066 mbx.payload_length = sizeof(struct mbx_common_get_profile_config);
2067 mbx.u0.s.sge_count = 1;
2068 sgl = &mbx.payload.u0.u1.sgl[0];
2069 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
2070 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
2071 sgl->length = htole32(mbx.payload_length);
2072 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
2073
2074 fwcmd->params.req.type = ACTIVE_PROFILE;
2075
2076 /* command post */
2077 rc = oce_mbox_post(sc, &mbx, NULL);
2078 if (!rc)
2079 rc = fwcmd->hdr.u0.rsp.status;
2080 if (rc) {
2081 device_printf(sc->dev,
2082 "%s failed - cmd status: %d addi status: %d\n",
2083 __FUNCTION__, rc,
2084 fwcmd->hdr.u0.rsp.additional_status);
2085 goto error;
2086 }
2087
2088 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources;
2089 desc_count = HOST_32(fwcmd->params.rsp.desc_count);
2090 for (i = 0; i < desc_count; i++) {
2091 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) ||
2092 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) {
2093 nic_desc_valid = TRUE;
2094 break;
2095 }
2096 nic_desc = (struct oce_nic_resc_desc *) \
2097 ((char *)nic_desc + nic_desc->desc_len);
2098 }
2099 if (!nic_desc_valid) {
2100 rc = -1;
2101 goto error;
2102 }
2103 else {
2104 sc->max_vlans = HOST_16(nic_desc->vlan_count);
2105 sc->nwqs = HOST_16(nic_desc->txq_count);
2106 if (sc->nwqs)
2107 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ);
2108 else
2109 sc->nwqs = OCE_MAX_WQ;
2110
2111 sc->nrssqs = HOST_16(nic_desc->rssq_count);
2112 if (sc->nrssqs)
2113 sc->nrssqs = MIN(sc->nrssqs, max_rss);
2114 else
2115 sc->nrssqs = max_rss;
2116 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */;
2117
2118 }
2119 error:
2120 oce_dma_free(sc, &dma);
2121 return rc;
2122
2123 }
2124
2125 int
oce_get_func_config(POCE_SOFTC sc)2126 oce_get_func_config(POCE_SOFTC sc)
2127 {
2128 struct oce_mbx mbx;
2129 struct mbx_common_get_func_config *fwcmd;
2130 int rc = 0;
2131 int version = 0;
2132 struct oce_mq_sge *sgl;
2133 OCE_DMA_MEM dma;
2134 uint32_t desc_count = 0;
2135 struct oce_nic_resc_desc *nic_desc = NULL;
2136 int i;
2137 boolean_t nic_desc_valid = FALSE;
2138 uint32_t max_rss = 0;
2139
2140 if ((IS_BE(sc) || IS_SH(sc)) && (!sc->be3_native))
2141 max_rss = OCE_LEGACY_MODE_RSS;
2142 else
2143 max_rss = OCE_MAX_RSS;
2144
2145 /* Allocate DMA mem*/
2146 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_func_config),
2147 &dma, 0))
2148 return ENOMEM;
2149
2150 /* Initialize MODIFY_EQ_DELAY ioctl header */
2151 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_func_config);
2152 bzero(fwcmd, sizeof(struct mbx_common_get_func_config));
2153
2154 if (IS_SH(sc))
2155 version = OCE_MBX_VER_V1;
2156 else
2157 version = OCE_MBX_VER_V0;
2158
2159 bzero(&mbx, sizeof(struct oce_mbx));
2160 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2161 MBX_SUBSYSTEM_COMMON,
2162 OPCODE_COMMON_GET_FUNCTION_CONFIG,
2163 MBX_TIMEOUT_SEC,
2164 sizeof(struct mbx_common_get_func_config),
2165 version);
2166 /* fill rest of mbx */
2167 mbx.u0.s.embedded = 0;
2168 mbx.payload_length = sizeof(struct mbx_common_get_func_config);
2169 mbx.u0.s.sge_count = 1;
2170 sgl = &mbx.payload.u0.u1.sgl[0];
2171 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
2172 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
2173 sgl->length = htole32(mbx.payload_length);
2174 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
2175
2176 /* command post */
2177 rc = oce_mbox_post(sc, &mbx, NULL);
2178 if (!rc)
2179 rc = fwcmd->hdr.u0.rsp.status;
2180 if (rc) {
2181 device_printf(sc->dev,
2182 "%s failed - cmd status: %d addi status: %d\n",
2183 __FUNCTION__, rc,
2184 fwcmd->hdr.u0.rsp.additional_status);
2185 goto error;
2186 }
2187
2188 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources;
2189 desc_count = HOST_32(fwcmd->params.rsp.desc_count);
2190 for (i = 0; i < desc_count; i++) {
2191 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) ||
2192 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) {
2193 nic_desc_valid = TRUE;
2194 break;
2195 }
2196 nic_desc = (struct oce_nic_resc_desc *) \
2197 ((char *)nic_desc + nic_desc->desc_len);
2198 }
2199 if (!nic_desc_valid) {
2200 rc = -1;
2201 goto error;
2202 }
2203 else {
2204 sc->max_vlans = nic_desc->vlan_count;
2205 sc->nwqs = HOST_32(nic_desc->txq_count);
2206 if (sc->nwqs)
2207 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ);
2208 else
2209 sc->nwqs = OCE_MAX_WQ;
2210
2211 sc->nrssqs = HOST_32(nic_desc->rssq_count);
2212 if (sc->nrssqs)
2213 sc->nrssqs = MIN(sc->nrssqs, max_rss);
2214 else
2215 sc->nrssqs = max_rss;
2216 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */;
2217 }
2218 error:
2219 oce_dma_free(sc, &dma);
2220 return rc;
2221
2222 }
2223