1 /* $FreeBSD$ */
2 /*-
3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 /*
28 * Thanks to Mentor Graphics for providing a reference driver for this USB chip
29 * at their homepage.
30 */
31
32 /*
33 * This file contains the driver for the Mentor Graphics Inventra USB
34 * 2.0 High Speed Dual-Role controller.
35 *
36 * NOTE: The current implementation only supports Device Side Mode!
37 */
38
39 #ifdef USB_GLOBAL_INCLUDE_FILE
40 #include USB_GLOBAL_INCLUDE_FILE
41 #else
42 #include <sys/stdint.h>
43 #include <sys/stddef.h>
44 #include <sys/param.h>
45 #include <sys/queue.h>
46 #include <sys/types.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/bus.h>
50 #include <sys/module.h>
51 #include <sys/lock.h>
52 #include <sys/mutex.h>
53 #include <sys/condvar.h>
54 #include <sys/sysctl.h>
55 #include <sys/sx.h>
56 #include <sys/unistd.h>
57 #include <sys/callout.h>
58 #include <sys/malloc.h>
59 #include <sys/priv.h>
60
61 #include <dev/usb/usb.h>
62 #include <dev/usb/usbdi.h>
63
64 #define USB_DEBUG_VAR musbotgdebug
65
66 #include <dev/usb/usb_core.h>
67 #include <dev/usb/usb_debug.h>
68 #include <dev/usb/usb_busdma.h>
69 #include <dev/usb/usb_process.h>
70 #include <dev/usb/usb_transfer.h>
71 #include <dev/usb/usb_device.h>
72 #include <dev/usb/usb_hub.h>
73 #include <dev/usb/usb_util.h>
74
75 #include <dev/usb/usb_controller.h>
76 #include <dev/usb/usb_bus.h>
77 #endif /* USB_GLOBAL_INCLUDE_FILE */
78
79 #include <dev/usb/controller/musb_otg.h>
80
81 #define MUSBOTG_INTR_ENDPT 1
82
83 #define MUSBOTG_BUS2SC(bus) \
84 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \
85 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus))))
86
87 #define MUSBOTG_PC2SC(pc) \
88 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
89
90 #ifdef USB_DEBUG
91 static int musbotgdebug = 0;
92
93 static SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg");
94 SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RWTUN,
95 &musbotgdebug, 0, "Debug level");
96 #endif
97
98 #define MAX_NAK_TO 16
99
100 /* prototypes */
101
102 static const struct usb_bus_methods musbotg_bus_methods;
103 static const struct usb_pipe_methods musbotg_device_bulk_methods;
104 static const struct usb_pipe_methods musbotg_device_ctrl_methods;
105 static const struct usb_pipe_methods musbotg_device_intr_methods;
106 static const struct usb_pipe_methods musbotg_device_isoc_methods;
107
108 /* Control transfers: Device mode */
109 static musbotg_cmd_t musbotg_dev_ctrl_setup_rx;
110 static musbotg_cmd_t musbotg_dev_ctrl_data_rx;
111 static musbotg_cmd_t musbotg_dev_ctrl_data_tx;
112 static musbotg_cmd_t musbotg_dev_ctrl_status;
113
114 /* Control transfers: Host mode */
115 static musbotg_cmd_t musbotg_host_ctrl_setup_tx;
116 static musbotg_cmd_t musbotg_host_ctrl_data_rx;
117 static musbotg_cmd_t musbotg_host_ctrl_data_tx;
118 static musbotg_cmd_t musbotg_host_ctrl_status_rx;
119 static musbotg_cmd_t musbotg_host_ctrl_status_tx;
120
121 /* Bulk, Interrupt, Isochronous: Device mode */
122 static musbotg_cmd_t musbotg_dev_data_rx;
123 static musbotg_cmd_t musbotg_dev_data_tx;
124
125 /* Bulk, Interrupt, Isochronous: Host mode */
126 static musbotg_cmd_t musbotg_host_data_rx;
127 static musbotg_cmd_t musbotg_host_data_tx;
128
129 static void musbotg_device_done(struct usb_xfer *, usb_error_t);
130 static void musbotg_do_poll(struct usb_bus *);
131 static void musbotg_standard_done(struct usb_xfer *);
132 static void musbotg_interrupt_poll(struct musbotg_softc *);
133 static void musbotg_root_intr(struct musbotg_softc *);
134 static int musbotg_channel_alloc(struct musbotg_softc *, struct musbotg_td *td, uint8_t);
135 static void musbotg_channel_free(struct musbotg_softc *, struct musbotg_td *td);
136 static void musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on);
137
138 /*
139 * Here is a configuration that the chip supports.
140 */
141 static const struct usb_hw_ep_profile musbotg_ep_profile[1] = {
142
143 [0] = {
144 .max_in_frame_size = 64,/* fixed */
145 .max_out_frame_size = 64, /* fixed */
146 .is_simplex = 1,
147 .support_control = 1,
148 }
149 };
150
151 static int
musbotg_channel_alloc(struct musbotg_softc * sc,struct musbotg_td * td,uint8_t is_tx)152 musbotg_channel_alloc(struct musbotg_softc *sc, struct musbotg_td *td, uint8_t is_tx)
153 {
154 int ch;
155 int ep;
156
157 ep = td->ep_no;
158
159 /* In device mode each EP got its own channel */
160 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
161 musbotg_ep_int_set(sc, ep, 1);
162 return (ep);
163 }
164
165 /*
166 * All control transactions go through EP0
167 */
168 if (ep == 0) {
169 if (sc->sc_channel_mask & (1 << 0))
170 return (-1);
171 sc->sc_channel_mask |= (1 << 0);
172 musbotg_ep_int_set(sc, ep, 1);
173 return (0);
174 }
175
176 for (ch = sc->sc_ep_max; ch != 0; ch--) {
177 if (sc->sc_channel_mask & (1 << ch))
178 continue;
179
180 /* check FIFO size requirement */
181 if (is_tx) {
182 if (td->max_frame_size >
183 sc->sc_hw_ep_profile[ch].max_in_frame_size)
184 continue;
185 } else {
186 if (td->max_frame_size >
187 sc->sc_hw_ep_profile[ch].max_out_frame_size)
188 continue;
189 }
190 sc->sc_channel_mask |= (1 << ch);
191 musbotg_ep_int_set(sc, ch, 1);
192 return (ch);
193 }
194
195 DPRINTFN(-1, "No available channels. Mask: %04x\n", sc->sc_channel_mask);
196
197 return (-1);
198 }
199
200 static void
musbotg_channel_free(struct musbotg_softc * sc,struct musbotg_td * td)201 musbotg_channel_free(struct musbotg_softc *sc, struct musbotg_td *td)
202 {
203
204 DPRINTFN(1, "ep_no=%d\n", td->channel);
205
206 if (sc->sc_mode == MUSB2_DEVICE_MODE)
207 return;
208
209 if (td == NULL)
210 return;
211 if (td->channel == -1)
212 return;
213
214 musbotg_ep_int_set(sc, td->channel, 0);
215 sc->sc_channel_mask &= ~(1 << td->channel);
216
217 td->channel = -1;
218 }
219
220 static void
musbotg_get_hw_ep_profile(struct usb_device * udev,const struct usb_hw_ep_profile ** ppf,uint8_t ep_addr)221 musbotg_get_hw_ep_profile(struct usb_device *udev,
222 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
223 {
224 struct musbotg_softc *sc;
225
226 sc = MUSBOTG_BUS2SC(udev->bus);
227
228 if (ep_addr == 0) {
229 /* control endpoint */
230 *ppf = musbotg_ep_profile;
231 } else if (ep_addr <= sc->sc_ep_max) {
232 /* other endpoints */
233 *ppf = sc->sc_hw_ep_profile + ep_addr;
234 } else {
235 *ppf = NULL;
236 }
237 }
238
239 static void
musbotg_clocks_on(struct musbotg_softc * sc)240 musbotg_clocks_on(struct musbotg_softc *sc)
241 {
242 if (sc->sc_flags.clocks_off &&
243 sc->sc_flags.port_powered) {
244
245 DPRINTFN(4, "\n");
246
247 if (sc->sc_clocks_on) {
248 (sc->sc_clocks_on) (sc->sc_clocks_arg);
249 }
250 sc->sc_flags.clocks_off = 0;
251
252 /* XXX enable Transceiver */
253 }
254 }
255
256 static void
musbotg_clocks_off(struct musbotg_softc * sc)257 musbotg_clocks_off(struct musbotg_softc *sc)
258 {
259 if (!sc->sc_flags.clocks_off) {
260
261 DPRINTFN(4, "\n");
262
263 /* XXX disable Transceiver */
264
265 if (sc->sc_clocks_off) {
266 (sc->sc_clocks_off) (sc->sc_clocks_arg);
267 }
268 sc->sc_flags.clocks_off = 1;
269 }
270 }
271
272 static void
musbotg_pull_common(struct musbotg_softc * sc,uint8_t on)273 musbotg_pull_common(struct musbotg_softc *sc, uint8_t on)
274 {
275 uint8_t temp;
276
277 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
278 if (on)
279 temp |= MUSB2_MASK_SOFTC;
280 else
281 temp &= ~MUSB2_MASK_SOFTC;
282
283 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
284 }
285
286 static void
musbotg_pull_up(struct musbotg_softc * sc)287 musbotg_pull_up(struct musbotg_softc *sc)
288 {
289 /* pullup D+, if possible */
290
291 if (!sc->sc_flags.d_pulled_up &&
292 sc->sc_flags.port_powered) {
293 sc->sc_flags.d_pulled_up = 1;
294 musbotg_pull_common(sc, 1);
295 }
296 }
297
298 static void
musbotg_pull_down(struct musbotg_softc * sc)299 musbotg_pull_down(struct musbotg_softc *sc)
300 {
301 /* pulldown D+, if possible */
302
303 if (sc->sc_flags.d_pulled_up) {
304 sc->sc_flags.d_pulled_up = 0;
305 musbotg_pull_common(sc, 0);
306 }
307 }
308
309 static void
musbotg_suspend_host(struct musbotg_softc * sc)310 musbotg_suspend_host(struct musbotg_softc *sc)
311 {
312 uint8_t temp;
313
314 if (sc->sc_flags.status_suspend) {
315 return;
316 }
317
318 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
319 temp |= MUSB2_MASK_SUSPMODE;
320 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
321 sc->sc_flags.status_suspend = 1;
322 }
323
324 static void
musbotg_wakeup_host(struct musbotg_softc * sc)325 musbotg_wakeup_host(struct musbotg_softc *sc)
326 {
327 uint8_t temp;
328
329 if (!(sc->sc_flags.status_suspend)) {
330 return;
331 }
332
333 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
334 temp &= ~MUSB2_MASK_SUSPMODE;
335 temp |= MUSB2_MASK_RESUME;
336 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
337
338 /* wait 20 milliseconds */
339 /* Wait for reset to complete. */
340 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
341
342 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
343 temp &= ~MUSB2_MASK_RESUME;
344 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
345
346 sc->sc_flags.status_suspend = 0;
347 }
348
349 static void
musbotg_wakeup_peer(struct musbotg_softc * sc)350 musbotg_wakeup_peer(struct musbotg_softc *sc)
351 {
352 uint8_t temp;
353
354 if (!(sc->sc_flags.status_suspend)) {
355 return;
356 }
357
358 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
359 temp |= MUSB2_MASK_RESUME;
360 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
361
362 /* wait 8 milliseconds */
363 /* Wait for reset to complete. */
364 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
365
366 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
367 temp &= ~MUSB2_MASK_RESUME;
368 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
369 }
370
371 static void
musbotg_set_address(struct musbotg_softc * sc,uint8_t addr)372 musbotg_set_address(struct musbotg_softc *sc, uint8_t addr)
373 {
374 DPRINTFN(4, "addr=%d\n", addr);
375 addr &= 0x7F;
376 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr);
377 }
378
379 static uint8_t
musbotg_dev_ctrl_setup_rx(struct musbotg_td * td)380 musbotg_dev_ctrl_setup_rx(struct musbotg_td *td)
381 {
382 struct musbotg_softc *sc;
383 struct usb_device_request req;
384 uint16_t count;
385 uint8_t csr;
386
387 /* get pointer to softc */
388 sc = MUSBOTG_PC2SC(td->pc);
389
390 if (td->channel == -1)
391 td->channel = musbotg_channel_alloc(sc, td, 0);
392
393 /* EP0 is busy, wait */
394 if (td->channel == -1)
395 return (1);
396
397 DPRINTFN(1, "ep_no=%d\n", td->channel);
398
399 /* select endpoint 0 */
400 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
401
402 /* read out FIFO status */
403 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
404
405 DPRINTFN(4, "csr=0x%02x\n", csr);
406
407 /*
408 * NOTE: If DATAEND is set we should not call the
409 * callback, hence the status stage is not complete.
410 */
411 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
412 /* do not stall at this point */
413 td->did_stall = 1;
414 /* wait for interrupt */
415 DPRINTFN(1, "CSR0 DATAEND\n");
416 goto not_complete;
417 }
418
419 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) {
420 /* clear SENTSTALL */
421 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
422 /* get latest status */
423 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
424 /* update EP0 state */
425 sc->sc_ep0_busy = 0;
426 }
427 if (csr & MUSB2_MASK_CSR0L_SETUPEND) {
428 /* clear SETUPEND */
429 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
430 MUSB2_MASK_CSR0L_SETUPEND_CLR);
431 /* get latest status */
432 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
433 /* update EP0 state */
434 sc->sc_ep0_busy = 0;
435 }
436 if (sc->sc_ep0_busy) {
437 DPRINTFN(1, "EP0 BUSY\n");
438 goto not_complete;
439 }
440 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
441 goto not_complete;
442 }
443 /* get the packet byte count */
444 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
445
446 /* verify data length */
447 if (count != td->remainder) {
448 DPRINTFN(1, "Invalid SETUP packet "
449 "length, %d bytes\n", count);
450 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
451 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
452 /* don't clear stall */
453 td->did_stall = 1;
454 goto not_complete;
455 }
456 if (count != sizeof(req)) {
457 DPRINTFN(1, "Unsupported SETUP packet "
458 "length, %d bytes\n", count);
459 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
460 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
461 /* don't clear stall */
462 td->did_stall = 1;
463 goto not_complete;
464 }
465 /* clear did stall flag */
466 td->did_stall = 0;
467
468 /* receive data */
469 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
470 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
471
472 /* copy data into real buffer */
473 usbd_copy_in(td->pc, 0, &req, sizeof(req));
474
475 td->offset = sizeof(req);
476 td->remainder = 0;
477
478 /* set pending command */
479 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
480
481 /* we need set stall or dataend after this */
482 sc->sc_ep0_busy = 1;
483
484 /* sneak peek the set address */
485 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
486 (req.bRequest == UR_SET_ADDRESS)) {
487 sc->sc_dv_addr = req.wValue[0] & 0x7F;
488 } else {
489 sc->sc_dv_addr = 0xFF;
490 }
491
492 musbotg_channel_free(sc, td);
493 return (0); /* complete */
494
495 not_complete:
496 /* abort any ongoing transfer */
497 if (!td->did_stall) {
498 DPRINTFN(4, "stalling\n");
499 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
500 MUSB2_MASK_CSR0L_SENDSTALL);
501 td->did_stall = 1;
502 }
503 return (1); /* not complete */
504 }
505
506 static uint8_t
musbotg_host_ctrl_setup_tx(struct musbotg_td * td)507 musbotg_host_ctrl_setup_tx(struct musbotg_td *td)
508 {
509 struct musbotg_softc *sc;
510 struct usb_device_request req;
511 uint8_t csr, csrh;
512
513 /* get pointer to softc */
514 sc = MUSBOTG_PC2SC(td->pc);
515
516 if (td->channel == -1)
517 td->channel = musbotg_channel_alloc(sc, td, 1);
518
519 /* EP0 is busy, wait */
520 if (td->channel == -1)
521 return (1);
522
523 DPRINTFN(1, "ep_no=%d\n", td->channel);
524
525 /* select endpoint 0 */
526 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
527
528 /* read out FIFO status */
529 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
530 DPRINTFN(4, "csr=0x%02x\n", csr);
531
532 /* Not ready yet yet */
533 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
534 return (1);
535
536 /* Failed */
537 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
538 MUSB2_MASK_CSR0L_ERROR))
539 {
540 /* Clear status bit */
541 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
542 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
543 td->error = 1;
544 }
545
546 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
547 DPRINTFN(1, "NAK timeout\n");
548
549 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
550 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
551 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
552 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
553 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
554 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
555 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
556 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
557 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
558 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
559 }
560 }
561
562 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
563 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
564
565 td->error = 1;
566 }
567
568 if (td->error) {
569 musbotg_channel_free(sc, td);
570 return (0);
571 }
572
573 /* Fifo is not empty and there is no NAK timeout */
574 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
575 return (1);
576
577 /* check if we are complete */
578 if (td->remainder == 0) {
579 /* we are complete */
580 musbotg_channel_free(sc, td);
581 return (0);
582 }
583
584 /* copy data into real buffer */
585 usbd_copy_out(td->pc, 0, &req, sizeof(req));
586
587 /* send data */
588 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
589 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
590
591 /* update offset and remainder */
592 td->offset += sizeof(req);
593 td->remainder -= sizeof(req);
594
595
596 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
597 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
598 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
599 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
600 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
601
602 /* write command */
603 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
604 MUSB2_MASK_CSR0L_TXPKTRDY |
605 MUSB2_MASK_CSR0L_SETUPPKT);
606
607 /* Just to be consistent, not used above */
608 td->transaction_started = 1;
609
610 return (1); /* in progress */
611 }
612
613 /* Control endpoint only data handling functions (RX/TX/SYNC) */
614
615 static uint8_t
musbotg_dev_ctrl_data_rx(struct musbotg_td * td)616 musbotg_dev_ctrl_data_rx(struct musbotg_td *td)
617 {
618 struct usb_page_search buf_res;
619 struct musbotg_softc *sc;
620 uint16_t count;
621 uint8_t csr;
622 uint8_t got_short;
623
624 /* get pointer to softc */
625 sc = MUSBOTG_PC2SC(td->pc);
626
627 /* select endpoint 0 */
628 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
629
630 /* check if a command is pending */
631 if (sc->sc_ep0_cmd) {
632 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
633 sc->sc_ep0_cmd = 0;
634 }
635 /* read out FIFO status */
636 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
637
638 DPRINTFN(4, "csr=0x%02x\n", csr);
639
640 got_short = 0;
641
642 if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
643 MUSB2_MASK_CSR0L_SENTSTALL)) {
644 if (td->remainder == 0) {
645 /*
646 * We are actually complete and have
647 * received the next SETUP
648 */
649 DPRINTFN(4, "faking complete\n");
650 return (0); /* complete */
651 }
652 /*
653 * USB Host Aborted the transfer.
654 */
655 td->error = 1;
656 return (0); /* complete */
657 }
658 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
659 return (1); /* not complete */
660 }
661 /* get the packet byte count */
662 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
663
664 /* verify the packet byte count */
665 if (count != td->max_frame_size) {
666 if (count < td->max_frame_size) {
667 /* we have a short packet */
668 td->short_pkt = 1;
669 got_short = 1;
670 } else {
671 /* invalid USB packet */
672 td->error = 1;
673 return (0); /* we are complete */
674 }
675 }
676 /* verify the packet byte count */
677 if (count > td->remainder) {
678 /* invalid USB packet */
679 td->error = 1;
680 return (0); /* we are complete */
681 }
682 while (count > 0) {
683 uint32_t temp;
684
685 usbd_get_page(td->pc, td->offset, &buf_res);
686
687 /* get correct length */
688 if (buf_res.length > count) {
689 buf_res.length = count;
690 }
691 /* check for unaligned memory address */
692 if (USB_P2U(buf_res.buffer) & 3) {
693
694 temp = count & ~3;
695
696 if (temp) {
697 /* receive data 4 bytes at a time */
698 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
699 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
700 temp / 4);
701 }
702 temp = count & 3;
703 if (temp) {
704 /* receive data 1 byte at a time */
705 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
706 MUSB2_REG_EPFIFO(0),
707 (void *)(&sc->sc_bounce_buf[count / 4]), temp);
708 }
709 usbd_copy_in(td->pc, td->offset,
710 sc->sc_bounce_buf, count);
711
712 /* update offset and remainder */
713 td->offset += count;
714 td->remainder -= count;
715 break;
716 }
717 /* check if we can optimise */
718 if (buf_res.length >= 4) {
719
720 /* receive data 4 bytes at a time */
721 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
722 MUSB2_REG_EPFIFO(0), buf_res.buffer,
723 buf_res.length / 4);
724
725 temp = buf_res.length & ~3;
726
727 /* update counters */
728 count -= temp;
729 td->offset += temp;
730 td->remainder -= temp;
731 continue;
732 }
733 /* receive data */
734 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
735 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
736
737 /* update counters */
738 count -= buf_res.length;
739 td->offset += buf_res.length;
740 td->remainder -= buf_res.length;
741 }
742
743 /* check if we are complete */
744 if ((td->remainder == 0) || got_short) {
745 if (td->short_pkt) {
746 /* we are complete */
747 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
748 return (0);
749 }
750 /* else need to receive a zero length packet */
751 }
752 /* write command - need more data */
753 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
754 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
755 return (1); /* not complete */
756 }
757
758 static uint8_t
musbotg_dev_ctrl_data_tx(struct musbotg_td * td)759 musbotg_dev_ctrl_data_tx(struct musbotg_td *td)
760 {
761 struct usb_page_search buf_res;
762 struct musbotg_softc *sc;
763 uint16_t count;
764 uint8_t csr;
765
766 /* get pointer to softc */
767 sc = MUSBOTG_PC2SC(td->pc);
768
769 /* select endpoint 0 */
770 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
771
772 /* check if a command is pending */
773 if (sc->sc_ep0_cmd) {
774 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
775 sc->sc_ep0_cmd = 0;
776 }
777 /* read out FIFO status */
778 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
779
780 DPRINTFN(4, "csr=0x%02x\n", csr);
781
782 if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
783 MUSB2_MASK_CSR0L_SENTSTALL)) {
784 /*
785 * The current transfer was aborted
786 * by the USB Host
787 */
788 td->error = 1;
789 return (0); /* complete */
790 }
791 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) {
792 return (1); /* not complete */
793 }
794 count = td->max_frame_size;
795 if (td->remainder < count) {
796 /* we have a short packet */
797 td->short_pkt = 1;
798 count = td->remainder;
799 }
800 while (count > 0) {
801 uint32_t temp;
802
803 usbd_get_page(td->pc, td->offset, &buf_res);
804
805 /* get correct length */
806 if (buf_res.length > count) {
807 buf_res.length = count;
808 }
809 /* check for unaligned memory address */
810 if (USB_P2U(buf_res.buffer) & 3) {
811
812 usbd_copy_out(td->pc, td->offset,
813 sc->sc_bounce_buf, count);
814
815 temp = count & ~3;
816
817 if (temp) {
818 /* transmit data 4 bytes at a time */
819 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
820 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
821 temp / 4);
822 }
823 temp = count & 3;
824 if (temp) {
825 /* receive data 1 byte at a time */
826 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
827 MUSB2_REG_EPFIFO(0),
828 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
829 }
830 /* update offset and remainder */
831 td->offset += count;
832 td->remainder -= count;
833 break;
834 }
835 /* check if we can optimise */
836 if (buf_res.length >= 4) {
837
838 /* transmit data 4 bytes at a time */
839 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
840 MUSB2_REG_EPFIFO(0), buf_res.buffer,
841 buf_res.length / 4);
842
843 temp = buf_res.length & ~3;
844
845 /* update counters */
846 count -= temp;
847 td->offset += temp;
848 td->remainder -= temp;
849 continue;
850 }
851 /* transmit data */
852 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
853 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
854
855 /* update counters */
856 count -= buf_res.length;
857 td->offset += buf_res.length;
858 td->remainder -= buf_res.length;
859 }
860
861 /* check remainder */
862 if (td->remainder == 0) {
863 if (td->short_pkt) {
864 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY;
865 return (0); /* complete */
866 }
867 /* else we need to transmit a short packet */
868 }
869 /* write command */
870 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
871 MUSB2_MASK_CSR0L_TXPKTRDY);
872
873 return (1); /* not complete */
874 }
875
876 static uint8_t
musbotg_host_ctrl_data_rx(struct musbotg_td * td)877 musbotg_host_ctrl_data_rx(struct musbotg_td *td)
878 {
879 struct usb_page_search buf_res;
880 struct musbotg_softc *sc;
881 uint16_t count;
882 uint8_t csr;
883 uint8_t got_short;
884
885 /* get pointer to softc */
886 sc = MUSBOTG_PC2SC(td->pc);
887
888 if (td->channel == -1)
889 td->channel = musbotg_channel_alloc(sc, td, 0);
890
891 /* EP0 is busy, wait */
892 if (td->channel == -1)
893 return (1);
894
895 DPRINTFN(1, "ep_no=%d\n", td->channel);
896
897 /* select endpoint 0 */
898 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
899
900 /* read out FIFO status */
901 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
902
903 DPRINTFN(4, "csr=0x%02x\n", csr);
904
905 got_short = 0;
906 if (!td->transaction_started) {
907 td->transaction_started = 1;
908
909 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
910
911 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
912 td->dev_addr);
913 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
914 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
915 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
916
917 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
918 MUSB2_MASK_CSR0L_REQPKT);
919
920 return (1);
921 }
922
923 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
924 csr &= ~MUSB2_MASK_CSR0L_REQPKT;
925 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
926
927 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
928 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
929
930 td->error = 1;
931 }
932
933 /* Failed */
934 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
935 MUSB2_MASK_CSR0L_ERROR))
936 {
937 /* Clear status bit */
938 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
939 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
940 td->error = 1;
941 }
942
943 if (td->error) {
944 musbotg_channel_free(sc, td);
945 return (0); /* we are complete */
946 }
947
948 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY))
949 return (1); /* not yet */
950
951 /* get the packet byte count */
952 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
953
954 /* verify the packet byte count */
955 if (count != td->max_frame_size) {
956 if (count < td->max_frame_size) {
957 /* we have a short packet */
958 td->short_pkt = 1;
959 got_short = 1;
960 } else {
961 /* invalid USB packet */
962 td->error = 1;
963 musbotg_channel_free(sc, td);
964 return (0); /* we are complete */
965 }
966 }
967 /* verify the packet byte count */
968 if (count > td->remainder) {
969 /* invalid USB packet */
970 td->error = 1;
971 musbotg_channel_free(sc, td);
972 return (0); /* we are complete */
973 }
974 while (count > 0) {
975 uint32_t temp;
976
977 usbd_get_page(td->pc, td->offset, &buf_res);
978
979 /* get correct length */
980 if (buf_res.length > count) {
981 buf_res.length = count;
982 }
983 /* check for unaligned memory address */
984 if (USB_P2U(buf_res.buffer) & 3) {
985
986 temp = count & ~3;
987
988 if (temp) {
989 /* receive data 4 bytes at a time */
990 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
991 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
992 temp / 4);
993 }
994 temp = count & 3;
995 if (temp) {
996 /* receive data 1 byte at a time */
997 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
998 MUSB2_REG_EPFIFO(0),
999 (void *)(&sc->sc_bounce_buf[count / 4]), temp);
1000 }
1001 usbd_copy_in(td->pc, td->offset,
1002 sc->sc_bounce_buf, count);
1003
1004 /* update offset and remainder */
1005 td->offset += count;
1006 td->remainder -= count;
1007 break;
1008 }
1009 /* check if we can optimise */
1010 if (buf_res.length >= 4) {
1011
1012 /* receive data 4 bytes at a time */
1013 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1014 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1015 buf_res.length / 4);
1016
1017 temp = buf_res.length & ~3;
1018
1019 /* update counters */
1020 count -= temp;
1021 td->offset += temp;
1022 td->remainder -= temp;
1023 continue;
1024 }
1025 /* receive data */
1026 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1027 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
1028
1029 /* update counters */
1030 count -= buf_res.length;
1031 td->offset += buf_res.length;
1032 td->remainder -= buf_res.length;
1033 }
1034
1035 csr &= ~MUSB2_MASK_CSR0L_RXPKTRDY;
1036 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1037
1038 /* check if we are complete */
1039 if ((td->remainder == 0) || got_short) {
1040 if (td->short_pkt) {
1041 /* we are complete */
1042
1043 musbotg_channel_free(sc, td);
1044 return (0);
1045 }
1046 /* else need to receive a zero length packet */
1047 }
1048
1049 td->transaction_started = 1;
1050 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1051 MUSB2_MASK_CSR0L_REQPKT);
1052
1053 return (1); /* not complete */
1054 }
1055
1056 static uint8_t
musbotg_host_ctrl_data_tx(struct musbotg_td * td)1057 musbotg_host_ctrl_data_tx(struct musbotg_td *td)
1058 {
1059 struct usb_page_search buf_res;
1060 struct musbotg_softc *sc;
1061 uint16_t count;
1062 uint8_t csr, csrh;
1063
1064 /* get pointer to softc */
1065 sc = MUSBOTG_PC2SC(td->pc);
1066
1067 if (td->channel == -1)
1068 td->channel = musbotg_channel_alloc(sc, td, 1);
1069
1070 /* No free EPs */
1071 if (td->channel == -1)
1072 return (1);
1073
1074 DPRINTFN(1, "ep_no=%d\n", td->channel);
1075
1076 /* select endpoint */
1077 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1078
1079 /* read out FIFO status */
1080 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1081 DPRINTFN(4, "csr=0x%02x\n", csr);
1082
1083 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1084 MUSB2_MASK_CSR0L_ERROR)) {
1085 /* clear status bits */
1086 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1087 td->error = 1;
1088 }
1089
1090 if (csr & MUSB2_MASK_CSR0L_NAKTIMO ) {
1091
1092 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1093 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
1094 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
1095 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
1096 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1097 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1098 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
1099 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
1100 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
1101 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1102 }
1103 }
1104
1105 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1106 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1107
1108 td->error = 1;
1109 }
1110
1111
1112 if (td->error) {
1113 musbotg_channel_free(sc, td);
1114 return (0); /* complete */
1115 }
1116
1117 /*
1118 * Wait while FIFO is empty.
1119 * Do not flush it because it will cause transactions
1120 * with size more then packet size. It might upset
1121 * some devices
1122 */
1123 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY)
1124 return (1);
1125
1126 /* Packet still being processed */
1127 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
1128 return (1);
1129
1130 if (td->transaction_started) {
1131 /* check remainder */
1132 if (td->remainder == 0) {
1133 if (td->short_pkt) {
1134 musbotg_channel_free(sc, td);
1135 return (0); /* complete */
1136 }
1137 /* else we need to transmit a short packet */
1138 }
1139
1140 /* We're not complete - more transactions required */
1141 td->transaction_started = 0;
1142 }
1143
1144 /* check for short packet */
1145 count = td->max_frame_size;
1146 if (td->remainder < count) {
1147 /* we have a short packet */
1148 td->short_pkt = 1;
1149 count = td->remainder;
1150 }
1151
1152 while (count > 0) {
1153 uint32_t temp;
1154
1155 usbd_get_page(td->pc, td->offset, &buf_res);
1156
1157 /* get correct length */
1158 if (buf_res.length > count) {
1159 buf_res.length = count;
1160 }
1161 /* check for unaligned memory address */
1162 if (USB_P2U(buf_res.buffer) & 3) {
1163
1164 usbd_copy_out(td->pc, td->offset,
1165 sc->sc_bounce_buf, count);
1166
1167 temp = count & ~3;
1168
1169 if (temp) {
1170 /* transmit data 4 bytes at a time */
1171 bus_space_write_multi_4(sc->sc_io_tag,
1172 sc->sc_io_hdl, MUSB2_REG_EPFIFO(0),
1173 sc->sc_bounce_buf, temp / 4);
1174 }
1175 temp = count & 3;
1176 if (temp) {
1177 /* receive data 1 byte at a time */
1178 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1179 MUSB2_REG_EPFIFO(0),
1180 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1181 }
1182 /* update offset and remainder */
1183 td->offset += count;
1184 td->remainder -= count;
1185 break;
1186 }
1187 /* check if we can optimise */
1188 if (buf_res.length >= 4) {
1189
1190 /* transmit data 4 bytes at a time */
1191 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1192 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1193 buf_res.length / 4);
1194
1195 temp = buf_res.length & ~3;
1196
1197 /* update counters */
1198 count -= temp;
1199 td->offset += temp;
1200 td->remainder -= temp;
1201 continue;
1202 }
1203 /* transmit data */
1204 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1205 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1206 buf_res.length);
1207
1208 /* update counters */
1209 count -= buf_res.length;
1210 td->offset += buf_res.length;
1211 td->remainder -= buf_res.length;
1212 }
1213
1214 /* Function address */
1215 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
1216 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
1217 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
1218 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
1219
1220 /* TX NAK timeout */
1221 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
1222
1223 /* write command */
1224 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1225 MUSB2_MASK_CSR0L_TXPKTRDY);
1226
1227 td->transaction_started = 1;
1228
1229 return (1); /* not complete */
1230 }
1231
1232 static uint8_t
musbotg_dev_ctrl_status(struct musbotg_td * td)1233 musbotg_dev_ctrl_status(struct musbotg_td *td)
1234 {
1235 struct musbotg_softc *sc;
1236 uint8_t csr;
1237
1238 /* get pointer to softc */
1239 sc = MUSBOTG_PC2SC(td->pc);
1240
1241 /* select endpoint 0 */
1242 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1243
1244 if (sc->sc_ep0_busy) {
1245 sc->sc_ep0_busy = 0;
1246 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND;
1247 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
1248 sc->sc_ep0_cmd = 0;
1249 }
1250 /* read out FIFO status */
1251 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1252
1253 DPRINTFN(4, "csr=0x%02x\n", csr);
1254
1255 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
1256 /* wait for interrupt */
1257 return (1); /* not complete */
1258 }
1259 if (sc->sc_dv_addr != 0xFF) {
1260 /* write function address */
1261 musbotg_set_address(sc, sc->sc_dv_addr);
1262 }
1263
1264 musbotg_channel_free(sc, td);
1265 return (0); /* complete */
1266 }
1267
1268 static uint8_t
musbotg_host_ctrl_status_rx(struct musbotg_td * td)1269 musbotg_host_ctrl_status_rx(struct musbotg_td *td)
1270 {
1271 struct musbotg_softc *sc;
1272 uint8_t csr, csrh;
1273
1274 /* get pointer to softc */
1275 sc = MUSBOTG_PC2SC(td->pc);
1276
1277 if (td->channel == -1)
1278 td->channel = musbotg_channel_alloc(sc, td, 0);
1279
1280 /* EP0 is busy, wait */
1281 if (td->channel == -1)
1282 return (1);
1283
1284 DPRINTFN(1, "ep_no=%d\n", td->channel);
1285
1286 /* select endpoint 0 */
1287 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1288
1289 if (!td->transaction_started) {
1290 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
1291 td->dev_addr);
1292
1293 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
1294 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
1295 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
1296
1297 /* RX NAK timeout */
1298 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
1299
1300 td->transaction_started = 1;
1301
1302 /* Disable PING */
1303 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH);
1304 csrh |= MUSB2_MASK_CSR0H_PING_DIS;
1305 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh);
1306
1307 /* write command */
1308 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1309 MUSB2_MASK_CSR0L_STATUSPKT |
1310 MUSB2_MASK_CSR0L_REQPKT);
1311
1312 return (1); /* Just started */
1313
1314 }
1315
1316 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1317
1318 DPRINTFN(4, "IN STATUS csr=0x%02x\n", csr);
1319
1320 if (csr & MUSB2_MASK_CSR0L_RXPKTRDY) {
1321 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1322 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
1323 musbotg_channel_free(sc, td);
1324 return (0); /* complete */
1325 }
1326
1327 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
1328 csr &= ~ (MUSB2_MASK_CSR0L_STATUSPKT |
1329 MUSB2_MASK_CSR0L_REQPKT);
1330 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1331
1332 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1333 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1334 td->error = 1;
1335 }
1336
1337 /* Failed */
1338 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1339 MUSB2_MASK_CSR0L_ERROR))
1340 {
1341 /* Clear status bit */
1342 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1343 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
1344 td->error = 1;
1345 }
1346
1347 if (td->error) {
1348 musbotg_channel_free(sc, td);
1349 return (0);
1350 }
1351
1352 return (1); /* Not ready yet */
1353 }
1354
1355 static uint8_t
musbotg_host_ctrl_status_tx(struct musbotg_td * td)1356 musbotg_host_ctrl_status_tx(struct musbotg_td *td)
1357 {
1358 struct musbotg_softc *sc;
1359 uint8_t csr;
1360
1361 /* get pointer to softc */
1362 sc = MUSBOTG_PC2SC(td->pc);
1363
1364 if (td->channel == -1)
1365 td->channel = musbotg_channel_alloc(sc, td, 1);
1366
1367 /* EP0 is busy, wait */
1368 if (td->channel == -1)
1369 return (1);
1370
1371 DPRINTFN(1, "ep_no=%d/%d [%d@%d.%d/%02x]\n", td->channel, td->transaction_started,
1372 td->dev_addr,td->haddr,td->hport, td->transfer_type);
1373
1374 /* select endpoint 0 */
1375 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1376
1377 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1378 DPRINTFN(4, "csr=0x%02x\n", csr);
1379
1380 /* Not yet */
1381 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
1382 return (1);
1383
1384 /* Failed */
1385 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1386 MUSB2_MASK_CSR0L_ERROR))
1387 {
1388 /* Clear status bit */
1389 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1390 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
1391 td->error = 1;
1392 musbotg_channel_free(sc, td);
1393 return (0); /* complete */
1394 }
1395
1396 if (td->transaction_started) {
1397 musbotg_channel_free(sc, td);
1398 return (0); /* complete */
1399 }
1400
1401 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, MUSB2_MASK_CSR0H_PING_DIS);
1402
1403 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
1404 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
1405 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
1406 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
1407
1408 /* TX NAK timeout */
1409 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
1410
1411 td->transaction_started = 1;
1412
1413 /* write command */
1414 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1415 MUSB2_MASK_CSR0L_STATUSPKT |
1416 MUSB2_MASK_CSR0L_TXPKTRDY);
1417
1418 return (1); /* wait for interrupt */
1419 }
1420
1421 static uint8_t
musbotg_dev_data_rx(struct musbotg_td * td)1422 musbotg_dev_data_rx(struct musbotg_td *td)
1423 {
1424 struct usb_page_search buf_res;
1425 struct musbotg_softc *sc;
1426 uint16_t count;
1427 uint8_t csr;
1428 uint8_t to;
1429 uint8_t got_short;
1430
1431 to = 8; /* don't loop forever! */
1432 got_short = 0;
1433
1434 /* get pointer to softc */
1435 sc = MUSBOTG_PC2SC(td->pc);
1436
1437 if (td->channel == -1)
1438 td->channel = musbotg_channel_alloc(sc, td, 0);
1439
1440 /* EP0 is busy, wait */
1441 if (td->channel == -1)
1442 return (1);
1443
1444 /* select endpoint */
1445 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1446
1447 repeat:
1448 /* read out FIFO status */
1449 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1450
1451 DPRINTFN(4, "csr=0x%02x\n", csr);
1452
1453 /* clear overrun */
1454 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) {
1455 /* make sure we don't clear "RXPKTRDY" */
1456 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1457 MUSB2_MASK_CSRL_RXPKTRDY);
1458 }
1459
1460 /* check status */
1461 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY))
1462 return (1); /* not complete */
1463
1464 /* get the packet byte count */
1465 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
1466
1467 DPRINTFN(4, "count=0x%04x\n", count);
1468
1469 /*
1470 * Check for short or invalid packet:
1471 */
1472 if (count != td->max_frame_size) {
1473 if (count < td->max_frame_size) {
1474 /* we have a short packet */
1475 td->short_pkt = 1;
1476 got_short = 1;
1477 } else {
1478 /* invalid USB packet */
1479 td->error = 1;
1480 musbotg_channel_free(sc, td);
1481 return (0); /* we are complete */
1482 }
1483 }
1484 /* verify the packet byte count */
1485 if (count > td->remainder) {
1486 /* invalid USB packet */
1487 td->error = 1;
1488 musbotg_channel_free(sc, td);
1489 return (0); /* we are complete */
1490 }
1491 while (count > 0) {
1492 uint32_t temp;
1493
1494 usbd_get_page(td->pc, td->offset, &buf_res);
1495
1496 /* get correct length */
1497 if (buf_res.length > count) {
1498 buf_res.length = count;
1499 }
1500 /* check for unaligned memory address */
1501 if (USB_P2U(buf_res.buffer) & 3) {
1502
1503 temp = count & ~3;
1504
1505 if (temp) {
1506 /* receive data 4 bytes at a time */
1507 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1508 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf,
1509 temp / 4);
1510 }
1511 temp = count & 3;
1512 if (temp) {
1513 /* receive data 1 byte at a time */
1514 bus_space_read_multi_1(sc->sc_io_tag,
1515 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1516 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1517 }
1518 usbd_copy_in(td->pc, td->offset,
1519 sc->sc_bounce_buf, count);
1520
1521 /* update offset and remainder */
1522 td->offset += count;
1523 td->remainder -= count;
1524 break;
1525 }
1526 /* check if we can optimise */
1527 if (buf_res.length >= 4) {
1528
1529 /* receive data 4 bytes at a time */
1530 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1531 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1532 buf_res.length / 4);
1533
1534 temp = buf_res.length & ~3;
1535
1536 /* update counters */
1537 count -= temp;
1538 td->offset += temp;
1539 td->remainder -= temp;
1540 continue;
1541 }
1542 /* receive data */
1543 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1544 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1545 buf_res.length);
1546
1547 /* update counters */
1548 count -= buf_res.length;
1549 td->offset += buf_res.length;
1550 td->remainder -= buf_res.length;
1551 }
1552
1553 /* clear status bits */
1554 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1555
1556 /* check if we are complete */
1557 if ((td->remainder == 0) || got_short) {
1558 if (td->short_pkt) {
1559 /* we are complete */
1560 musbotg_channel_free(sc, td);
1561 return (0);
1562 }
1563 /* else need to receive a zero length packet */
1564 }
1565 if (--to) {
1566 goto repeat;
1567 }
1568 return (1); /* not complete */
1569 }
1570
1571 static uint8_t
musbotg_dev_data_tx(struct musbotg_td * td)1572 musbotg_dev_data_tx(struct musbotg_td *td)
1573 {
1574 struct usb_page_search buf_res;
1575 struct musbotg_softc *sc;
1576 uint16_t count;
1577 uint8_t csr;
1578 uint8_t to;
1579
1580 to = 8; /* don't loop forever! */
1581
1582 /* get pointer to softc */
1583 sc = MUSBOTG_PC2SC(td->pc);
1584
1585 if (td->channel == -1)
1586 td->channel = musbotg_channel_alloc(sc, td, 1);
1587
1588 /* EP0 is busy, wait */
1589 if (td->channel == -1)
1590 return (1);
1591
1592 /* select endpoint */
1593 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1594
1595 repeat:
1596
1597 /* read out FIFO status */
1598 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1599
1600 DPRINTFN(4, "csr=0x%02x\n", csr);
1601
1602 if (csr & (MUSB2_MASK_CSRL_TXINCOMP |
1603 MUSB2_MASK_CSRL_TXUNDERRUN)) {
1604 /* clear status bits */
1605 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1606 }
1607 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) {
1608 return (1); /* not complete */
1609 }
1610 /* check for short packet */
1611 count = td->max_frame_size;
1612 if (td->remainder < count) {
1613 /* we have a short packet */
1614 td->short_pkt = 1;
1615 count = td->remainder;
1616 }
1617 while (count > 0) {
1618 uint32_t temp;
1619
1620 usbd_get_page(td->pc, td->offset, &buf_res);
1621
1622 /* get correct length */
1623 if (buf_res.length > count) {
1624 buf_res.length = count;
1625 }
1626 /* check for unaligned memory address */
1627 if (USB_P2U(buf_res.buffer) & 3) {
1628
1629 usbd_copy_out(td->pc, td->offset,
1630 sc->sc_bounce_buf, count);
1631
1632 temp = count & ~3;
1633
1634 if (temp) {
1635 /* transmit data 4 bytes at a time */
1636 bus_space_write_multi_4(sc->sc_io_tag,
1637 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1638 sc->sc_bounce_buf, temp / 4);
1639 }
1640 temp = count & 3;
1641 if (temp) {
1642 /* receive data 1 byte at a time */
1643 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1644 MUSB2_REG_EPFIFO(td->channel),
1645 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1646 }
1647 /* update offset and remainder */
1648 td->offset += count;
1649 td->remainder -= count;
1650 break;
1651 }
1652 /* check if we can optimise */
1653 if (buf_res.length >= 4) {
1654
1655 /* transmit data 4 bytes at a time */
1656 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1657 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1658 buf_res.length / 4);
1659
1660 temp = buf_res.length & ~3;
1661
1662 /* update counters */
1663 count -= temp;
1664 td->offset += temp;
1665 td->remainder -= temp;
1666 continue;
1667 }
1668 /* transmit data */
1669 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1670 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1671 buf_res.length);
1672
1673 /* update counters */
1674 count -= buf_res.length;
1675 td->offset += buf_res.length;
1676 td->remainder -= buf_res.length;
1677 }
1678
1679 /* Max packet size */
1680 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet);
1681
1682 /* write command */
1683 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1684 MUSB2_MASK_CSRL_TXPKTRDY);
1685
1686 /* check remainder */
1687 if (td->remainder == 0) {
1688 if (td->short_pkt) {
1689 musbotg_channel_free(sc, td);
1690 return (0); /* complete */
1691 }
1692 /* else we need to transmit a short packet */
1693 }
1694 if (--to) {
1695 goto repeat;
1696 }
1697 return (1); /* not complete */
1698 }
1699
1700 static uint8_t
musbotg_host_data_rx(struct musbotg_td * td)1701 musbotg_host_data_rx(struct musbotg_td *td)
1702 {
1703 struct usb_page_search buf_res;
1704 struct musbotg_softc *sc;
1705 uint16_t count;
1706 uint8_t csr, csrh;
1707 uint8_t to;
1708 uint8_t got_short;
1709
1710 /* get pointer to softc */
1711 sc = MUSBOTG_PC2SC(td->pc);
1712
1713 if (td->channel == -1)
1714 td->channel = musbotg_channel_alloc(sc, td, 0);
1715
1716 /* No free EPs */
1717 if (td->channel == -1)
1718 return (1);
1719
1720 DPRINTFN(1, "ep_no=%d\n", td->channel);
1721
1722 to = 8; /* don't loop forever! */
1723 got_short = 0;
1724
1725 /* select endpoint */
1726 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1727
1728 repeat:
1729 /* read out FIFO status */
1730 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1731 DPRINTFN(4, "csr=0x%02x\n", csr);
1732
1733 if (!td->transaction_started) {
1734 /* Function address */
1735 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(td->channel),
1736 td->dev_addr);
1737
1738 /* SPLIT transaction */
1739 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(td->channel),
1740 td->haddr);
1741 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(td->channel),
1742 td->hport);
1743
1744 /* RX NAK timeout */
1745 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC)
1746 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, 0);
1747 else
1748 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
1749
1750 /* Protocol, speed, device endpoint */
1751 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
1752
1753 /* Max packet size */
1754 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, td->reg_max_packet);
1755
1756 /* Data Toggle */
1757 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH);
1758 DPRINTFN(4, "csrh=0x%02x\n", csrh);
1759
1760 csrh |= MUSB2_MASK_CSRH_RXDT_WREN;
1761 if (td->toggle)
1762 csrh |= MUSB2_MASK_CSRH_RXDT_VAL;
1763 else
1764 csrh &= ~MUSB2_MASK_CSRH_RXDT_VAL;
1765
1766 /* Set data toggle */
1767 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh);
1768
1769 /* write command */
1770 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1771 MUSB2_MASK_CSRL_RXREQPKT);
1772
1773 td->transaction_started = 1;
1774 return (1);
1775 }
1776
1777 /* clear NAK timeout */
1778 if (csr & MUSB2_MASK_CSRL_RXNAKTO) {
1779 DPRINTFN(4, "NAK Timeout\n");
1780 if (csr & MUSB2_MASK_CSRL_RXREQPKT) {
1781 csr &= ~MUSB2_MASK_CSRL_RXREQPKT;
1782 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
1783
1784 csr &= ~MUSB2_MASK_CSRL_RXNAKTO;
1785 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
1786 }
1787
1788 td->error = 1;
1789 }
1790
1791 if (csr & MUSB2_MASK_CSRL_RXERROR) {
1792 DPRINTFN(4, "RXERROR\n");
1793 td->error = 1;
1794 }
1795
1796 if (csr & MUSB2_MASK_CSRL_RXSTALL) {
1797 DPRINTFN(4, "RXSTALL\n");
1798 td->error = 1;
1799 }
1800
1801 if (td->error) {
1802 musbotg_channel_free(sc, td);
1803 return (0); /* we are complete */
1804 }
1805
1806 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) {
1807 /* No data available yet */
1808 return (1);
1809 }
1810
1811 td->toggle ^= 1;
1812 /* get the packet byte count */
1813 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
1814 DPRINTFN(4, "count=0x%04x\n", count);
1815
1816 /*
1817 * Check for short or invalid packet:
1818 */
1819 if (count != td->max_frame_size) {
1820 if (count < td->max_frame_size) {
1821 /* we have a short packet */
1822 td->short_pkt = 1;
1823 got_short = 1;
1824 } else {
1825 /* invalid USB packet */
1826 td->error = 1;
1827 musbotg_channel_free(sc, td);
1828 return (0); /* we are complete */
1829 }
1830 }
1831
1832 /* verify the packet byte count */
1833 if (count > td->remainder) {
1834 /* invalid USB packet */
1835 td->error = 1;
1836 musbotg_channel_free(sc, td);
1837 return (0); /* we are complete */
1838 }
1839
1840 while (count > 0) {
1841 uint32_t temp;
1842
1843 usbd_get_page(td->pc, td->offset, &buf_res);
1844
1845 /* get correct length */
1846 if (buf_res.length > count) {
1847 buf_res.length = count;
1848 }
1849 /* check for unaligned memory address */
1850 if (USB_P2U(buf_res.buffer) & 3) {
1851
1852 temp = count & ~3;
1853
1854 if (temp) {
1855 /* receive data 4 bytes at a time */
1856 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1857 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf,
1858 temp / 4);
1859 }
1860 temp = count & 3;
1861 if (temp) {
1862 /* receive data 1 byte at a time */
1863 bus_space_read_multi_1(sc->sc_io_tag,
1864 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1865 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1866 }
1867 usbd_copy_in(td->pc, td->offset,
1868 sc->sc_bounce_buf, count);
1869
1870 /* update offset and remainder */
1871 td->offset += count;
1872 td->remainder -= count;
1873 break;
1874 }
1875 /* check if we can optimise */
1876 if (buf_res.length >= 4) {
1877
1878 /* receive data 4 bytes at a time */
1879 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1880 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1881 buf_res.length / 4);
1882
1883 temp = buf_res.length & ~3;
1884
1885 /* update counters */
1886 count -= temp;
1887 td->offset += temp;
1888 td->remainder -= temp;
1889 continue;
1890 }
1891 /* receive data */
1892 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1893 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1894 buf_res.length);
1895
1896 /* update counters */
1897 count -= buf_res.length;
1898 td->offset += buf_res.length;
1899 td->remainder -= buf_res.length;
1900 }
1901
1902 /* clear status bits */
1903 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1904
1905 /* check if we are complete */
1906 if ((td->remainder == 0) || got_short) {
1907 if (td->short_pkt) {
1908 /* we are complete */
1909 musbotg_channel_free(sc, td);
1910 return (0);
1911 }
1912 /* else need to receive a zero length packet */
1913 }
1914
1915 /* Reset transaction state and restart */
1916 td->transaction_started = 0;
1917
1918 if (--to)
1919 goto repeat;
1920
1921 return (1); /* not complete */
1922 }
1923
1924 static uint8_t
musbotg_host_data_tx(struct musbotg_td * td)1925 musbotg_host_data_tx(struct musbotg_td *td)
1926 {
1927 struct usb_page_search buf_res;
1928 struct musbotg_softc *sc;
1929 uint16_t count;
1930 uint8_t csr, csrh;
1931
1932 /* get pointer to softc */
1933 sc = MUSBOTG_PC2SC(td->pc);
1934
1935 if (td->channel == -1)
1936 td->channel = musbotg_channel_alloc(sc, td, 1);
1937
1938 /* No free EPs */
1939 if (td->channel == -1)
1940 return (1);
1941
1942 DPRINTFN(1, "ep_no=%d\n", td->channel);
1943
1944 /* select endpoint */
1945 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1946
1947 /* read out FIFO status */
1948 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1949 DPRINTFN(4, "csr=0x%02x\n", csr);
1950
1951 if (csr & (MUSB2_MASK_CSRL_TXSTALLED |
1952 MUSB2_MASK_CSRL_TXERROR)) {
1953 /* clear status bits */
1954 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1955 td->error = 1;
1956 musbotg_channel_free(sc, td);
1957 return (0); /* complete */
1958 }
1959
1960 if (csr & MUSB2_MASK_CSRL_TXNAKTO) {
1961 /*
1962 * Flush TX FIFO before clearing NAK TO
1963 */
1964 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1965 csr |= MUSB2_MASK_CSRL_TXFFLUSH;
1966 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1967 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1968 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1969 csr |= MUSB2_MASK_CSRL_TXFFLUSH;
1970 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1971 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1972 }
1973 }
1974
1975 csr &= ~MUSB2_MASK_CSRL_TXNAKTO;
1976 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1977
1978 td->error = 1;
1979 musbotg_channel_free(sc, td);
1980 return (0); /* complete */
1981 }
1982
1983 /*
1984 * Wait while FIFO is empty.
1985 * Do not flush it because it will cause transactions
1986 * with size more then packet size. It might upset
1987 * some devices
1988 */
1989 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY)
1990 return (1);
1991
1992 /* Packet still being processed */
1993 if (csr & MUSB2_MASK_CSRL_TXPKTRDY)
1994 return (1);
1995
1996 if (td->transaction_started) {
1997 /* check remainder */
1998 if (td->remainder == 0) {
1999 if (td->short_pkt) {
2000 musbotg_channel_free(sc, td);
2001 return (0); /* complete */
2002 }
2003 /* else we need to transmit a short packet */
2004 }
2005
2006 /* We're not complete - more transactions required */
2007 td->transaction_started = 0;
2008 }
2009
2010 /* check for short packet */
2011 count = td->max_frame_size;
2012 if (td->remainder < count) {
2013 /* we have a short packet */
2014 td->short_pkt = 1;
2015 count = td->remainder;
2016 }
2017
2018 while (count > 0) {
2019 uint32_t temp;
2020
2021 usbd_get_page(td->pc, td->offset, &buf_res);
2022
2023 /* get correct length */
2024 if (buf_res.length > count) {
2025 buf_res.length = count;
2026 }
2027 /* check for unaligned memory address */
2028 if (USB_P2U(buf_res.buffer) & 3) {
2029
2030 usbd_copy_out(td->pc, td->offset,
2031 sc->sc_bounce_buf, count);
2032
2033 temp = count & ~3;
2034
2035 if (temp) {
2036 /* transmit data 4 bytes at a time */
2037 bus_space_write_multi_4(sc->sc_io_tag,
2038 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
2039 sc->sc_bounce_buf, temp / 4);
2040 }
2041 temp = count & 3;
2042 if (temp) {
2043 /* receive data 1 byte at a time */
2044 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
2045 MUSB2_REG_EPFIFO(td->channel),
2046 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
2047 }
2048 /* update offset and remainder */
2049 td->offset += count;
2050 td->remainder -= count;
2051 break;
2052 }
2053 /* check if we can optimise */
2054 if (buf_res.length >= 4) {
2055
2056 /* transmit data 4 bytes at a time */
2057 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
2058 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
2059 buf_res.length / 4);
2060
2061 temp = buf_res.length & ~3;
2062
2063 /* update counters */
2064 count -= temp;
2065 td->offset += temp;
2066 td->remainder -= temp;
2067 continue;
2068 }
2069 /* transmit data */
2070 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
2071 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
2072 buf_res.length);
2073
2074 /* update counters */
2075 count -= buf_res.length;
2076 td->offset += buf_res.length;
2077 td->remainder -= buf_res.length;
2078 }
2079
2080 /* Function address */
2081 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(td->channel),
2082 td->dev_addr);
2083
2084 /* SPLIT transaction */
2085 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(td->channel),
2086 td->haddr);
2087 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(td->channel),
2088 td->hport);
2089
2090 /* TX NAK timeout */
2091 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC)
2092 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, 0);
2093 else
2094 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
2095
2096 /* Protocol, speed, device endpoint */
2097 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
2098
2099 /* Max packet size */
2100 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet);
2101
2102 if (!td->transaction_started) {
2103 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
2104 DPRINTFN(4, "csrh=0x%02x\n", csrh);
2105
2106 csrh |= MUSB2_MASK_CSRH_TXDT_WREN;
2107 if (td->toggle)
2108 csrh |= MUSB2_MASK_CSRH_TXDT_VAL;
2109 else
2110 csrh &= ~MUSB2_MASK_CSRH_TXDT_VAL;
2111
2112 /* Set data toggle */
2113 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
2114 }
2115
2116 /* write command */
2117 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2118 MUSB2_MASK_CSRL_TXPKTRDY);
2119
2120 /* Update Data Toggle */
2121 td->toggle ^= 1;
2122 td->transaction_started = 1;
2123
2124 return (1); /* not complete */
2125 }
2126
2127 static uint8_t
musbotg_xfer_do_fifo(struct usb_xfer * xfer)2128 musbotg_xfer_do_fifo(struct usb_xfer *xfer)
2129 {
2130 struct musbotg_softc *sc;
2131 struct musbotg_td *td;
2132
2133 DPRINTFN(8, "\n");
2134 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2135
2136 td = xfer->td_transfer_cache;
2137 while (1) {
2138
2139 if ((td->func) (td)) {
2140 /* operation in progress */
2141 break;
2142 }
2143
2144 if (((void *)td) == xfer->td_transfer_last) {
2145 goto done;
2146 }
2147 if (td->error) {
2148 goto done;
2149 } else if (td->remainder > 0) {
2150 /*
2151 * We had a short transfer. If there is no alternate
2152 * next, stop processing !
2153 */
2154 if (!td->alt_next) {
2155 goto done;
2156 }
2157 }
2158 /*
2159 * Fetch the next transfer descriptor and transfer
2160 * some flags to the next transfer descriptor
2161 */
2162 td = td->obj_next;
2163 xfer->td_transfer_cache = td;
2164 }
2165
2166 return (1); /* not complete */
2167 done:
2168 /* compute all actual lengths */
2169 musbotg_standard_done(xfer);
2170
2171 return (0); /* complete */
2172 }
2173
2174 static void
musbotg_interrupt_poll(struct musbotg_softc * sc)2175 musbotg_interrupt_poll(struct musbotg_softc *sc)
2176 {
2177 struct usb_xfer *xfer;
2178
2179 repeat:
2180 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
2181 if (!musbotg_xfer_do_fifo(xfer)) {
2182 /* queue has been modified */
2183 goto repeat;
2184 }
2185 }
2186 }
2187
2188 void
musbotg_vbus_interrupt(struct musbotg_softc * sc,uint8_t is_on)2189 musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on)
2190 {
2191 DPRINTFN(4, "vbus = %u\n", is_on);
2192
2193 USB_BUS_LOCK(&sc->sc_bus);
2194 if (is_on) {
2195 if (!sc->sc_flags.status_vbus) {
2196 sc->sc_flags.status_vbus = 1;
2197
2198 /* complete root HUB interrupt endpoint */
2199 musbotg_root_intr(sc);
2200 }
2201 } else {
2202 if (sc->sc_flags.status_vbus) {
2203 sc->sc_flags.status_vbus = 0;
2204 sc->sc_flags.status_bus_reset = 0;
2205 sc->sc_flags.status_suspend = 0;
2206 sc->sc_flags.change_suspend = 0;
2207 sc->sc_flags.change_connect = 1;
2208
2209 /* complete root HUB interrupt endpoint */
2210 musbotg_root_intr(sc);
2211 }
2212 }
2213
2214 USB_BUS_UNLOCK(&sc->sc_bus);
2215 }
2216
2217 void
musbotg_connect_interrupt(struct musbotg_softc * sc)2218 musbotg_connect_interrupt(struct musbotg_softc *sc)
2219 {
2220 USB_BUS_LOCK(&sc->sc_bus);
2221 sc->sc_flags.change_connect = 1;
2222
2223 /* complete root HUB interrupt endpoint */
2224 musbotg_root_intr(sc);
2225 USB_BUS_UNLOCK(&sc->sc_bus);
2226 }
2227
2228 void
musbotg_interrupt(struct musbotg_softc * sc,uint16_t rxstat,uint16_t txstat,uint8_t stat)2229 musbotg_interrupt(struct musbotg_softc *sc,
2230 uint16_t rxstat, uint16_t txstat, uint8_t stat)
2231 {
2232 uint16_t rx_status;
2233 uint16_t tx_status;
2234 uint8_t usb_status;
2235 uint8_t temp;
2236 uint8_t to = 2;
2237
2238 USB_BUS_LOCK(&sc->sc_bus);
2239
2240 repeat:
2241
2242 /* read all interrupt registers */
2243 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB);
2244
2245 /* read all FIFO interrupts */
2246 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX);
2247 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX);
2248 rx_status |= rxstat;
2249 tx_status |= txstat;
2250 usb_status |= stat;
2251
2252 /* Clear platform flags after first time */
2253 rxstat = 0;
2254 txstat = 0;
2255 stat = 0;
2256
2257 /* check for any bus state change interrupts */
2258
2259 if (usb_status & (MUSB2_MASK_IRESET |
2260 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP |
2261 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC |
2262 MUSB2_MASK_IVBUSERR)) {
2263
2264 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status);
2265
2266 if (usb_status & MUSB2_MASK_IRESET) {
2267
2268 /* set correct state */
2269 sc->sc_flags.status_bus_reset = 1;
2270 sc->sc_flags.status_suspend = 0;
2271 sc->sc_flags.change_suspend = 0;
2272 sc->sc_flags.change_connect = 1;
2273
2274 /* determine line speed */
2275 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
2276 if (temp & MUSB2_MASK_HSMODE)
2277 sc->sc_flags.status_high_speed = 1;
2278 else
2279 sc->sc_flags.status_high_speed = 0;
2280
2281 /*
2282 * After reset all interrupts are on and we need to
2283 * turn them off!
2284 */
2285 temp = MUSB2_MASK_IRESET;
2286 /* disable resume interrupt */
2287 temp &= ~MUSB2_MASK_IRESUME;
2288 /* enable suspend interrupt */
2289 temp |= MUSB2_MASK_ISUSP;
2290 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2291 /* disable TX and RX interrupts */
2292 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
2293 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
2294 }
2295 /*
2296 * If RXRSM and RXSUSP is set at the same time we interpret
2297 * that like RESUME. Resume is set when there is at least 3
2298 * milliseconds of inactivity on the USB BUS.
2299 */
2300 if (usb_status & MUSB2_MASK_IRESUME) {
2301 if (sc->sc_flags.status_suspend) {
2302 sc->sc_flags.status_suspend = 0;
2303 sc->sc_flags.change_suspend = 1;
2304
2305 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
2306 /* disable resume interrupt */
2307 temp &= ~MUSB2_MASK_IRESUME;
2308 /* enable suspend interrupt */
2309 temp |= MUSB2_MASK_ISUSP;
2310 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2311 }
2312 } else if (usb_status & MUSB2_MASK_ISUSP) {
2313 if (!sc->sc_flags.status_suspend) {
2314 sc->sc_flags.status_suspend = 1;
2315 sc->sc_flags.change_suspend = 1;
2316
2317 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
2318 /* disable suspend interrupt */
2319 temp &= ~MUSB2_MASK_ISUSP;
2320 /* enable resume interrupt */
2321 temp |= MUSB2_MASK_IRESUME;
2322 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2323 }
2324 }
2325 if (usb_status &
2326 (MUSB2_MASK_ICONN | MUSB2_MASK_IDISC))
2327 sc->sc_flags.change_connect = 1;
2328
2329 /*
2330 * Host Mode: There is no IRESET so assume bus is
2331 * always in reset state once device is connected.
2332 */
2333 if (sc->sc_mode == MUSB2_HOST_MODE) {
2334 /* check for VBUS error in USB host mode */
2335 if (usb_status & MUSB2_MASK_IVBUSERR) {
2336 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
2337 temp |= MUSB2_MASK_SESS;
2338 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
2339 }
2340 if (usb_status & MUSB2_MASK_ICONN)
2341 sc->sc_flags.status_bus_reset = 1;
2342 if (usb_status & MUSB2_MASK_IDISC)
2343 sc->sc_flags.status_bus_reset = 0;
2344 }
2345
2346 /* complete root HUB interrupt endpoint */
2347 musbotg_root_intr(sc);
2348 }
2349 /* check for any endpoint interrupts */
2350
2351 if (rx_status || tx_status) {
2352 DPRINTFN(4, "real endpoint interrupt "
2353 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status);
2354 }
2355 /* poll one time regardless of FIFO status */
2356
2357 musbotg_interrupt_poll(sc);
2358
2359 if (--to)
2360 goto repeat;
2361
2362 USB_BUS_UNLOCK(&sc->sc_bus);
2363 }
2364
2365 static void
musbotg_setup_standard_chain_sub(struct musbotg_std_temp * temp)2366 musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp)
2367 {
2368 struct musbotg_td *td;
2369
2370 /* get current Transfer Descriptor */
2371 td = temp->td_next;
2372 temp->td = td;
2373
2374 /* prepare for next TD */
2375 temp->td_next = td->obj_next;
2376
2377 /* fill out the Transfer Descriptor */
2378 td->func = temp->func;
2379 td->pc = temp->pc;
2380 td->offset = temp->offset;
2381 td->remainder = temp->len;
2382 td->error = 0;
2383 td->transaction_started = 0;
2384 td->did_stall = temp->did_stall;
2385 td->short_pkt = temp->short_pkt;
2386 td->alt_next = temp->setup_alt_next;
2387 td->channel = temp->channel;
2388 td->dev_addr = temp->dev_addr;
2389 td->haddr = temp->haddr;
2390 td->hport = temp->hport;
2391 td->transfer_type = temp->transfer_type;
2392 }
2393
2394 static void
musbotg_setup_standard_chain(struct usb_xfer * xfer)2395 musbotg_setup_standard_chain(struct usb_xfer *xfer)
2396 {
2397 struct musbotg_std_temp temp;
2398 struct musbotg_softc *sc;
2399 struct musbotg_td *td;
2400 uint32_t x;
2401 uint8_t ep_no;
2402 uint8_t xfer_type;
2403 enum usb_dev_speed speed;
2404 int tx;
2405 int dev_addr;
2406
2407 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n",
2408 xfer->address, UE_GET_ADDR(xfer->endpointno),
2409 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
2410
2411 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2412 ep_no = (xfer->endpointno & UE_ADDR);
2413
2414 temp.max_frame_size = xfer->max_frame_size;
2415
2416 td = xfer->td_start[0];
2417 xfer->td_transfer_first = td;
2418 xfer->td_transfer_cache = td;
2419
2420 /* setup temp */
2421 dev_addr = xfer->address;
2422
2423 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE;
2424
2425 temp.pc = NULL;
2426 temp.td = NULL;
2427 temp.td_next = xfer->td_start[0];
2428 temp.offset = 0;
2429 temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
2430 xfer->flags_int.isochronous_xfr;
2431 temp.did_stall = !xfer->flags_int.control_stall;
2432 temp.channel = -1;
2433 temp.dev_addr = dev_addr;
2434 temp.haddr = xfer->xroot->udev->hs_hub_addr;
2435 temp.hport = xfer->xroot->udev->hs_port_no;
2436
2437 if (xfer->flags_int.usb_mode == USB_MODE_HOST) {
2438 speed = usbd_get_speed(xfer->xroot->udev);
2439
2440 switch (speed) {
2441 case USB_SPEED_LOW:
2442 temp.transfer_type = MUSB2_MASK_TI_SPEED_LO;
2443 break;
2444 case USB_SPEED_FULL:
2445 temp.transfer_type = MUSB2_MASK_TI_SPEED_FS;
2446 break;
2447 case USB_SPEED_HIGH:
2448 temp.transfer_type = MUSB2_MASK_TI_SPEED_HS;
2449 break;
2450 default:
2451 temp.transfer_type = 0;
2452 DPRINTFN(-1, "Invalid USB speed: %d\n", speed);
2453 break;
2454 }
2455
2456 switch (xfer_type) {
2457 case UE_CONTROL:
2458 temp.transfer_type |= MUSB2_MASK_TI_PROTO_CTRL;
2459 break;
2460 case UE_ISOCHRONOUS:
2461 temp.transfer_type |= MUSB2_MASK_TI_PROTO_ISOC;
2462 break;
2463 case UE_BULK:
2464 temp.transfer_type |= MUSB2_MASK_TI_PROTO_BULK;
2465 break;
2466 case UE_INTERRUPT:
2467 temp.transfer_type |= MUSB2_MASK_TI_PROTO_INTR;
2468 break;
2469 default:
2470 DPRINTFN(-1, "Invalid USB transfer type: %d\n",
2471 xfer_type);
2472 break;
2473 }
2474
2475 temp.transfer_type |= ep_no;
2476 td->toggle = xfer->endpoint->toggle_next;
2477 }
2478
2479 /* check if we should prepend a setup message */
2480
2481 if (xfer->flags_int.control_xfr) {
2482 if (xfer->flags_int.control_hdr) {
2483
2484 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE)
2485 temp.func = &musbotg_dev_ctrl_setup_rx;
2486 else
2487 temp.func = &musbotg_host_ctrl_setup_tx;
2488
2489 temp.len = xfer->frlengths[0];
2490 temp.pc = xfer->frbuffers + 0;
2491 temp.short_pkt = temp.len ? 1 : 0;
2492
2493 musbotg_setup_standard_chain_sub(&temp);
2494 }
2495 x = 1;
2496 } else {
2497 x = 0;
2498 }
2499
2500 tx = 0;
2501
2502 if (x != xfer->nframes) {
2503 if (xfer->endpointno & UE_DIR_IN)
2504 tx = 1;
2505
2506 if (xfer->flags_int.usb_mode == USB_MODE_HOST) {
2507 tx = !tx;
2508
2509 if (tx) {
2510 if (xfer->flags_int.control_xfr)
2511 temp.func = &musbotg_host_ctrl_data_tx;
2512 else
2513 temp.func = &musbotg_host_data_tx;
2514 } else {
2515 if (xfer->flags_int.control_xfr)
2516 temp.func = &musbotg_host_ctrl_data_rx;
2517 else
2518 temp.func = &musbotg_host_data_rx;
2519 }
2520
2521 } else {
2522 if (tx) {
2523 if (xfer->flags_int.control_xfr)
2524 temp.func = &musbotg_dev_ctrl_data_tx;
2525 else
2526 temp.func = &musbotg_dev_data_tx;
2527 } else {
2528 if (xfer->flags_int.control_xfr)
2529 temp.func = &musbotg_dev_ctrl_data_rx;
2530 else
2531 temp.func = &musbotg_dev_data_rx;
2532 }
2533 }
2534
2535 /* setup "pc" pointer */
2536 temp.pc = xfer->frbuffers + x;
2537 }
2538 while (x != xfer->nframes) {
2539
2540 /* DATA0 / DATA1 message */
2541
2542 temp.len = xfer->frlengths[x];
2543
2544 x++;
2545
2546 if (x == xfer->nframes) {
2547 if (xfer->flags_int.control_xfr) {
2548 if (xfer->flags_int.control_act) {
2549 temp.setup_alt_next = 0;
2550 }
2551 } else {
2552 temp.setup_alt_next = 0;
2553 }
2554 }
2555 if (temp.len == 0) {
2556
2557 /* make sure that we send an USB packet */
2558
2559 temp.short_pkt = 0;
2560
2561 } else {
2562
2563 if (xfer->flags_int.isochronous_xfr) {
2564 /* isochronous data transfer */
2565 /* don't force short */
2566 temp.short_pkt = 1;
2567 } else {
2568 /* regular data transfer */
2569 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1);
2570 }
2571 }
2572
2573 musbotg_setup_standard_chain_sub(&temp);
2574
2575 if (xfer->flags_int.isochronous_xfr) {
2576 temp.offset += temp.len;
2577 } else {
2578 /* get next Page Cache pointer */
2579 temp.pc = xfer->frbuffers + x;
2580 }
2581 }
2582
2583 /* check for control transfer */
2584 if (xfer->flags_int.control_xfr) {
2585
2586 /* always setup a valid "pc" pointer for status and sync */
2587 temp.pc = xfer->frbuffers + 0;
2588 temp.len = 0;
2589 temp.short_pkt = 0;
2590 temp.setup_alt_next = 0;
2591
2592 /* check if we should append a status stage */
2593 if (!xfer->flags_int.control_act) {
2594 /*
2595 * Send a DATA1 message and invert the current
2596 * endpoint direction.
2597 */
2598 if (sc->sc_mode == MUSB2_DEVICE_MODE)
2599 temp.func = &musbotg_dev_ctrl_status;
2600 else {
2601 if (xfer->endpointno & UE_DIR_IN)
2602 temp.func = musbotg_host_ctrl_status_tx;
2603 else
2604 temp.func = musbotg_host_ctrl_status_rx;
2605 }
2606 musbotg_setup_standard_chain_sub(&temp);
2607 }
2608 }
2609 /* must have at least one frame! */
2610 td = temp.td;
2611 xfer->td_transfer_last = td;
2612 }
2613
2614 static void
musbotg_timeout(void * arg)2615 musbotg_timeout(void *arg)
2616 {
2617 struct usb_xfer *xfer = arg;
2618
2619 DPRINTFN(1, "xfer=%p\n", xfer);
2620
2621 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2622
2623 /* transfer is transferred */
2624 musbotg_device_done(xfer, USB_ERR_TIMEOUT);
2625 }
2626
2627 static void
musbotg_ep_int_set(struct musbotg_softc * sc,int channel,int on)2628 musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on)
2629 {
2630 uint16_t temp;
2631
2632 /*
2633 * Only enable the endpoint interrupt when we are
2634 * actually waiting for data, hence we are dealing
2635 * with level triggered interrupts !
2636 */
2637 DPRINTFN(1, "ep_no=%d, on=%d\n", channel, on);
2638
2639 if (channel == -1)
2640 return;
2641
2642 if (channel == 0) {
2643 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
2644 if (on)
2645 temp |= MUSB2_MASK_EPINT(0);
2646 else
2647 temp &= ~MUSB2_MASK_EPINT(0);
2648
2649 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
2650 } else {
2651 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE);
2652 if (on)
2653 temp |= MUSB2_MASK_EPINT(channel);
2654 else
2655 temp &= ~MUSB2_MASK_EPINT(channel);
2656 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp);
2657
2658 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
2659 if (on)
2660 temp |= MUSB2_MASK_EPINT(channel);
2661 else
2662 temp &= ~MUSB2_MASK_EPINT(channel);
2663 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
2664 }
2665
2666 if (sc->sc_ep_int_set)
2667 sc->sc_ep_int_set(sc, channel, on);
2668 }
2669
2670 static void
musbotg_start_standard_chain(struct usb_xfer * xfer)2671 musbotg_start_standard_chain(struct usb_xfer *xfer)
2672 {
2673 DPRINTFN(8, "\n");
2674
2675 /* poll one time */
2676 if (musbotg_xfer_do_fifo(xfer)) {
2677
2678 DPRINTFN(14, "enabled interrupts on endpoint\n");
2679
2680 /* put transfer on interrupt queue */
2681 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2682
2683 /* start timeout, if any */
2684 if (xfer->timeout != 0) {
2685 usbd_transfer_timeout_ms(xfer,
2686 &musbotg_timeout, xfer->timeout);
2687 }
2688 }
2689 }
2690
2691 static void
musbotg_root_intr(struct musbotg_softc * sc)2692 musbotg_root_intr(struct musbotg_softc *sc)
2693 {
2694 DPRINTFN(8, "\n");
2695
2696 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2697
2698 /* set port bit */
2699 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
2700
2701 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2702 sizeof(sc->sc_hub_idata));
2703 }
2704
2705 static usb_error_t
musbotg_standard_done_sub(struct usb_xfer * xfer)2706 musbotg_standard_done_sub(struct usb_xfer *xfer)
2707 {
2708 struct musbotg_td *td;
2709 uint32_t len;
2710 uint8_t error;
2711
2712 DPRINTFN(8, "\n");
2713
2714 td = xfer->td_transfer_cache;
2715
2716 do {
2717 len = td->remainder;
2718
2719 xfer->endpoint->toggle_next = td->toggle;
2720
2721 if (xfer->aframes != xfer->nframes) {
2722 /*
2723 * Verify the length and subtract
2724 * the remainder from "frlengths[]":
2725 */
2726 if (len > xfer->frlengths[xfer->aframes]) {
2727 td->error = 1;
2728 } else {
2729 xfer->frlengths[xfer->aframes] -= len;
2730 }
2731 }
2732 /* Check for transfer error */
2733 if (td->error) {
2734 /* the transfer is finished */
2735 error = 1;
2736 td = NULL;
2737 break;
2738 }
2739 /* Check for short transfer */
2740 if (len > 0) {
2741 if (xfer->flags_int.short_frames_ok ||
2742 xfer->flags_int.isochronous_xfr) {
2743 /* follow alt next */
2744 if (td->alt_next) {
2745 td = td->obj_next;
2746 } else {
2747 td = NULL;
2748 }
2749 } else {
2750 /* the transfer is finished */
2751 td = NULL;
2752 }
2753 error = 0;
2754 break;
2755 }
2756 td = td->obj_next;
2757
2758 /* this USB frame is complete */
2759 error = 0;
2760 break;
2761
2762 } while (0);
2763
2764 /* update transfer cache */
2765
2766 xfer->td_transfer_cache = td;
2767
2768 return (error ?
2769 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
2770 }
2771
2772 static void
musbotg_standard_done(struct usb_xfer * xfer)2773 musbotg_standard_done(struct usb_xfer *xfer)
2774 {
2775 usb_error_t err = 0;
2776
2777 DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n",
2778 xfer, xfer->endpoint);
2779
2780 /* reset scanner */
2781
2782 xfer->td_transfer_cache = xfer->td_transfer_first;
2783
2784 if (xfer->flags_int.control_xfr) {
2785
2786 if (xfer->flags_int.control_hdr) {
2787
2788 err = musbotg_standard_done_sub(xfer);
2789 }
2790 xfer->aframes = 1;
2791
2792 if (xfer->td_transfer_cache == NULL) {
2793 goto done;
2794 }
2795 }
2796 while (xfer->aframes != xfer->nframes) {
2797
2798 err = musbotg_standard_done_sub(xfer);
2799 xfer->aframes++;
2800
2801 if (xfer->td_transfer_cache == NULL) {
2802 goto done;
2803 }
2804 }
2805
2806 if (xfer->flags_int.control_xfr &&
2807 !xfer->flags_int.control_act) {
2808
2809 err = musbotg_standard_done_sub(xfer);
2810 }
2811 done:
2812 musbotg_device_done(xfer, err);
2813 }
2814
2815 /*------------------------------------------------------------------------*
2816 * musbotg_device_done
2817 *
2818 * NOTE: this function can be called more than one time on the
2819 * same USB transfer!
2820 *------------------------------------------------------------------------*/
2821 static void
musbotg_device_done(struct usb_xfer * xfer,usb_error_t error)2822 musbotg_device_done(struct usb_xfer *xfer, usb_error_t error)
2823 {
2824 struct musbotg_td *td;
2825 struct musbotg_softc *sc;
2826
2827 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2828
2829 DPRINTFN(1, "xfer=%p, endpoint=%p, error=%d\n",
2830 xfer, xfer->endpoint, error);
2831
2832 DPRINTFN(14, "disabled interrupts on endpoint\n");
2833
2834 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2835 td = xfer->td_transfer_cache;
2836
2837 if (td && (td->channel != -1))
2838 musbotg_channel_free(sc, td);
2839
2840 /* dequeue transfer and start next transfer */
2841 usbd_transfer_done(xfer, error);
2842 }
2843
2844 static void
musbotg_xfer_stall(struct usb_xfer * xfer)2845 musbotg_xfer_stall(struct usb_xfer *xfer)
2846 {
2847 musbotg_device_done(xfer, USB_ERR_STALLED);
2848 }
2849
2850 static void
musbotg_set_stall(struct usb_device * udev,struct usb_endpoint * ep,uint8_t * did_stall)2851 musbotg_set_stall(struct usb_device *udev,
2852 struct usb_endpoint *ep, uint8_t *did_stall)
2853 {
2854 struct musbotg_softc *sc;
2855 uint8_t ep_no;
2856
2857 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2858
2859 DPRINTFN(4, "endpoint=%p\n", ep);
2860
2861 /* set FORCESTALL */
2862 sc = MUSBOTG_BUS2SC(udev->bus);
2863
2864 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
2865
2866 /* select endpoint */
2867 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
2868
2869 if (ep->edesc->bEndpointAddress & UE_DIR_IN) {
2870 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2871 MUSB2_MASK_CSRL_TXSENDSTALL);
2872 } else {
2873 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2874 MUSB2_MASK_CSRL_RXSENDSTALL);
2875 }
2876 }
2877
2878 static void
musbotg_clear_stall_sub(struct musbotg_softc * sc,uint16_t wMaxPacket,uint8_t ep_no,uint8_t ep_type,uint8_t ep_dir)2879 musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket,
2880 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
2881 {
2882 uint16_t mps;
2883 uint16_t temp;
2884 uint8_t csr;
2885
2886 if (ep_type == UE_CONTROL) {
2887 /* clearing stall is not needed */
2888 return;
2889 }
2890 /* select endpoint */
2891 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
2892
2893 /* compute max frame size */
2894 mps = wMaxPacket & 0x7FF;
2895 switch ((wMaxPacket >> 11) & 3) {
2896 case 1:
2897 mps *= 2;
2898 break;
2899 case 2:
2900 mps *= 3;
2901 break;
2902 default:
2903 break;
2904 }
2905
2906 if (ep_dir == UE_DIR_IN) {
2907
2908 temp = 0;
2909
2910 /* Configure endpoint */
2911 switch (ep_type) {
2912 case UE_INTERRUPT:
2913 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2914 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2915 MUSB2_MASK_CSRH_TXMODE | temp);
2916 break;
2917 case UE_ISOCHRONOUS:
2918 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2919 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2920 MUSB2_MASK_CSRH_TXMODE |
2921 MUSB2_MASK_CSRH_TXISO | temp);
2922 break;
2923 case UE_BULK:
2924 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2925 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2926 MUSB2_MASK_CSRH_TXMODE | temp);
2927 break;
2928 default:
2929 break;
2930 }
2931
2932 /* Need to flush twice in case of double bufring */
2933 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2934 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2935 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2936 MUSB2_MASK_CSRL_TXFFLUSH);
2937 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2938 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2939 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2940 MUSB2_MASK_CSRL_TXFFLUSH);
2941 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2942 }
2943 }
2944 /* reset data toggle */
2945 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2946 MUSB2_MASK_CSRL_TXDT_CLR);
2947 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
2948 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2949
2950 /* set double/single buffering */
2951 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS);
2952 if (mps <= (sc->sc_hw_ep_profile[ep_no].
2953 max_in_frame_size / 2)) {
2954 /* double buffer */
2955 temp &= ~(1 << ep_no);
2956 } else {
2957 /* single buffer */
2958 temp |= (1 << ep_no);
2959 }
2960 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp);
2961
2962 /* clear sent stall */
2963 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) {
2964 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
2965 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2966 }
2967 } else {
2968
2969 temp = 0;
2970
2971 /* Configure endpoint */
2972 switch (ep_type) {
2973 case UE_INTERRUPT:
2974 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2975 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
2976 MUSB2_MASK_CSRH_RXNYET | temp);
2977 break;
2978 case UE_ISOCHRONOUS:
2979 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2980 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
2981 MUSB2_MASK_CSRH_RXNYET |
2982 MUSB2_MASK_CSRH_RXISO | temp);
2983 break;
2984 case UE_BULK:
2985 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2986 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp);
2987 break;
2988 default:
2989 break;
2990 }
2991
2992 /* Need to flush twice in case of double bufring */
2993 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2994 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
2995 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2996 MUSB2_MASK_CSRL_RXFFLUSH);
2997 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2998 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
2999 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
3000 MUSB2_MASK_CSRL_RXFFLUSH);
3001 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
3002 }
3003 }
3004 /* reset data toggle */
3005 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
3006 MUSB2_MASK_CSRL_RXDT_CLR);
3007 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
3008 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
3009
3010 /* set double/single buffering */
3011 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS);
3012 if (mps <= (sc->sc_hw_ep_profile[ep_no].
3013 max_out_frame_size / 2)) {
3014 /* double buffer */
3015 temp &= ~(1 << ep_no);
3016 } else {
3017 /* single buffer */
3018 temp |= (1 << ep_no);
3019 }
3020 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp);
3021
3022 /* clear sent stall */
3023 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) {
3024 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
3025 }
3026 }
3027 }
3028
3029 static void
musbotg_clear_stall(struct usb_device * udev,struct usb_endpoint * ep)3030 musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3031 {
3032 struct musbotg_softc *sc;
3033 struct usb_endpoint_descriptor *ed;
3034
3035 DPRINTFN(4, "endpoint=%p\n", ep);
3036
3037 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3038
3039 /* check mode */
3040 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3041 /* not supported */
3042 return;
3043 }
3044 /* get softc */
3045 sc = MUSBOTG_BUS2SC(udev->bus);
3046
3047 /* get endpoint descriptor */
3048 ed = ep->edesc;
3049
3050 /* reset endpoint */
3051 musbotg_clear_stall_sub(sc,
3052 UGETW(ed->wMaxPacketSize),
3053 (ed->bEndpointAddress & UE_ADDR),
3054 (ed->bmAttributes & UE_XFERTYPE),
3055 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
3056 }
3057
3058 usb_error_t
musbotg_init(struct musbotg_softc * sc)3059 musbotg_init(struct musbotg_softc *sc)
3060 {
3061 struct usb_hw_ep_profile *pf;
3062 uint16_t offset;
3063 uint8_t nrx;
3064 uint8_t ntx;
3065 uint8_t temp;
3066 uint8_t fsize;
3067 uint8_t frx;
3068 uint8_t ftx;
3069 uint8_t dynfifo;
3070
3071 DPRINTFN(1, "start\n");
3072
3073 /* set up the bus structure */
3074 sc->sc_bus.usbrev = USB_REV_2_0;
3075 sc->sc_bus.methods = &musbotg_bus_methods;
3076
3077 USB_BUS_LOCK(&sc->sc_bus);
3078
3079 /* turn on clocks */
3080
3081 if (sc->sc_clocks_on) {
3082 (sc->sc_clocks_on) (sc->sc_clocks_arg);
3083 }
3084
3085 /* wait a little for things to stabilise */
3086 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
3087
3088 /* disable all interrupts */
3089
3090 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3091 DPRINTF("pre-DEVCTL=0x%02x\n", temp);
3092
3093 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
3094 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
3095 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
3096
3097 /* disable pullup */
3098
3099 musbotg_pull_common(sc, 0);
3100
3101 /* wait a little bit (10ms) */
3102 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3103
3104
3105 /* disable double packet buffering */
3106 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF);
3107 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF);
3108
3109 /* enable HighSpeed and ISO Update flags */
3110
3111 MUSB2_WRITE_1(sc, MUSB2_REG_POWER,
3112 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD);
3113
3114 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
3115 /* clear Session bit, if set */
3116 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3117 temp &= ~MUSB2_MASK_SESS;
3118 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
3119 } else {
3120 /* Enter session for Host mode */
3121 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3122 temp |= MUSB2_MASK_SESS;
3123 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
3124 }
3125
3126 /* wait a little for things to stabilise */
3127 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
3128
3129 DPRINTF("DEVCTL=0x%02x\n", temp);
3130
3131 /* disable testmode */
3132
3133 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0);
3134
3135 /* set default value */
3136
3137 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0);
3138
3139 /* select endpoint index 0 */
3140
3141 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
3142
3143 /* read out number of endpoints */
3144
3145 nrx =
3146 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16);
3147
3148 ntx =
3149 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16);
3150
3151 /* these numbers exclude the control endpoint */
3152
3153 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx);
3154
3155 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx;
3156 if (sc->sc_ep_max == 0) {
3157 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n");
3158 }
3159 /* read out configuration data */
3160
3161 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA);
3162
3163 DPRINTFN(2, "Config Data: 0x%02x\n",
3164 sc->sc_conf_data);
3165
3166 dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0;
3167
3168 if (dynfifo) {
3169 device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, "
3170 "assuming 16Kbytes of FIFO RAM\n");
3171 }
3172
3173 DPRINTFN(2, "HW version: 0x%04x\n",
3174 MUSB2_READ_1(sc, MUSB2_REG_HWVERS));
3175
3176 /* initialise endpoint profiles */
3177
3178 offset = 0;
3179
3180 for (temp = 1; temp <= sc->sc_ep_max; temp++) {
3181 pf = sc->sc_hw_ep_profile + temp;
3182
3183 /* select endpoint */
3184 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp);
3185
3186 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE);
3187 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16;
3188 ftx = (fsize & MUSB2_MASK_TX_FSIZE);
3189
3190 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n",
3191 temp, ftx, frx, dynfifo);
3192
3193 if (dynfifo) {
3194 if (frx && (temp <= nrx)) {
3195 if (temp == 1) {
3196 frx = 12; /* 4K */
3197 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3198 MUSB2_VAL_FIFOSZ_4096 |
3199 MUSB2_MASK_FIFODB);
3200 } else if (temp < 8) {
3201 frx = 10; /* 1K */
3202 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3203 MUSB2_VAL_FIFOSZ_512 |
3204 MUSB2_MASK_FIFODB);
3205 } else {
3206 frx = 7; /* 128 bytes */
3207 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3208 MUSB2_VAL_FIFOSZ_128);
3209 }
3210
3211 MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD,
3212 offset >> 3);
3213
3214 offset += (1 << frx);
3215 }
3216 if (ftx && (temp <= ntx)) {
3217 if (temp == 1) {
3218 ftx = 12; /* 4K */
3219 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3220 MUSB2_VAL_FIFOSZ_4096 |
3221 MUSB2_MASK_FIFODB);
3222 } else if (temp < 8) {
3223 ftx = 10; /* 1K */
3224 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3225 MUSB2_VAL_FIFOSZ_512 |
3226 MUSB2_MASK_FIFODB);
3227 } else {
3228 ftx = 7; /* 128 bytes */
3229 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3230 MUSB2_VAL_FIFOSZ_128);
3231 }
3232
3233 MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD,
3234 offset >> 3);
3235
3236 offset += (1 << ftx);
3237 }
3238 }
3239
3240 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) {
3241 pf->max_in_frame_size = 1 << ftx;
3242 pf->max_out_frame_size = 1 << frx;
3243 pf->is_simplex = 0; /* duplex */
3244 pf->support_multi_buffer = 1;
3245 pf->support_bulk = 1;
3246 pf->support_interrupt = 1;
3247 pf->support_isochronous = 1;
3248 pf->support_in = 1;
3249 pf->support_out = 1;
3250 } else if (frx && (temp <= nrx)) {
3251 pf->max_out_frame_size = 1 << frx;
3252 pf->max_in_frame_size = 0;
3253 pf->is_simplex = 1; /* simplex */
3254 pf->support_multi_buffer = 1;
3255 pf->support_bulk = 1;
3256 pf->support_interrupt = 1;
3257 pf->support_isochronous = 1;
3258 pf->support_out = 1;
3259 } else if (ftx && (temp <= ntx)) {
3260 pf->max_in_frame_size = 1 << ftx;
3261 pf->max_out_frame_size = 0;
3262 pf->is_simplex = 1; /* simplex */
3263 pf->support_multi_buffer = 1;
3264 pf->support_bulk = 1;
3265 pf->support_interrupt = 1;
3266 pf->support_isochronous = 1;
3267 pf->support_in = 1;
3268 }
3269 }
3270
3271 DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset);
3272
3273 /* turn on default interrupts */
3274
3275 if (sc->sc_mode == MUSB2_HOST_MODE)
3276 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0xff);
3277 else
3278 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE,
3279 MUSB2_MASK_IRESET);
3280
3281 musbotg_clocks_off(sc);
3282
3283 USB_BUS_UNLOCK(&sc->sc_bus);
3284
3285 /* catch any lost interrupts */
3286
3287 musbotg_do_poll(&sc->sc_bus);
3288
3289 return (0); /* success */
3290 }
3291
3292 void
musbotg_uninit(struct musbotg_softc * sc)3293 musbotg_uninit(struct musbotg_softc *sc)
3294 {
3295 USB_BUS_LOCK(&sc->sc_bus);
3296
3297 /* disable all interrupts */
3298 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
3299 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
3300 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
3301
3302 sc->sc_flags.port_powered = 0;
3303 sc->sc_flags.status_vbus = 0;
3304 sc->sc_flags.status_bus_reset = 0;
3305 sc->sc_flags.status_suspend = 0;
3306 sc->sc_flags.change_suspend = 0;
3307 sc->sc_flags.change_connect = 1;
3308
3309 musbotg_pull_down(sc);
3310 musbotg_clocks_off(sc);
3311 USB_BUS_UNLOCK(&sc->sc_bus);
3312 }
3313
3314 static void
musbotg_do_poll(struct usb_bus * bus)3315 musbotg_do_poll(struct usb_bus *bus)
3316 {
3317 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
3318
3319 USB_BUS_LOCK(&sc->sc_bus);
3320 musbotg_interrupt_poll(sc);
3321 USB_BUS_UNLOCK(&sc->sc_bus);
3322 }
3323
3324 /*------------------------------------------------------------------------*
3325 * musbotg bulk support
3326 *------------------------------------------------------------------------*/
3327 static void
musbotg_device_bulk_open(struct usb_xfer * xfer)3328 musbotg_device_bulk_open(struct usb_xfer *xfer)
3329 {
3330 return;
3331 }
3332
3333 static void
musbotg_device_bulk_close(struct usb_xfer * xfer)3334 musbotg_device_bulk_close(struct usb_xfer *xfer)
3335 {
3336 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3337 }
3338
3339 static void
musbotg_device_bulk_enter(struct usb_xfer * xfer)3340 musbotg_device_bulk_enter(struct usb_xfer *xfer)
3341 {
3342 return;
3343 }
3344
3345 static void
musbotg_device_bulk_start(struct usb_xfer * xfer)3346 musbotg_device_bulk_start(struct usb_xfer *xfer)
3347 {
3348 /* setup TDs */
3349 musbotg_setup_standard_chain(xfer);
3350 musbotg_start_standard_chain(xfer);
3351 }
3352
3353 static const struct usb_pipe_methods musbotg_device_bulk_methods =
3354 {
3355 .open = musbotg_device_bulk_open,
3356 .close = musbotg_device_bulk_close,
3357 .enter = musbotg_device_bulk_enter,
3358 .start = musbotg_device_bulk_start,
3359 };
3360
3361 /*------------------------------------------------------------------------*
3362 * musbotg control support
3363 *------------------------------------------------------------------------*/
3364 static void
musbotg_device_ctrl_open(struct usb_xfer * xfer)3365 musbotg_device_ctrl_open(struct usb_xfer *xfer)
3366 {
3367 return;
3368 }
3369
3370 static void
musbotg_device_ctrl_close(struct usb_xfer * xfer)3371 musbotg_device_ctrl_close(struct usb_xfer *xfer)
3372 {
3373 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3374 }
3375
3376 static void
musbotg_device_ctrl_enter(struct usb_xfer * xfer)3377 musbotg_device_ctrl_enter(struct usb_xfer *xfer)
3378 {
3379 return;
3380 }
3381
3382 static void
musbotg_device_ctrl_start(struct usb_xfer * xfer)3383 musbotg_device_ctrl_start(struct usb_xfer *xfer)
3384 {
3385 /* setup TDs */
3386 musbotg_setup_standard_chain(xfer);
3387 musbotg_start_standard_chain(xfer);
3388 }
3389
3390 static const struct usb_pipe_methods musbotg_device_ctrl_methods =
3391 {
3392 .open = musbotg_device_ctrl_open,
3393 .close = musbotg_device_ctrl_close,
3394 .enter = musbotg_device_ctrl_enter,
3395 .start = musbotg_device_ctrl_start,
3396 };
3397
3398 /*------------------------------------------------------------------------*
3399 * musbotg interrupt support
3400 *------------------------------------------------------------------------*/
3401 static void
musbotg_device_intr_open(struct usb_xfer * xfer)3402 musbotg_device_intr_open(struct usb_xfer *xfer)
3403 {
3404 return;
3405 }
3406
3407 static void
musbotg_device_intr_close(struct usb_xfer * xfer)3408 musbotg_device_intr_close(struct usb_xfer *xfer)
3409 {
3410 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3411 }
3412
3413 static void
musbotg_device_intr_enter(struct usb_xfer * xfer)3414 musbotg_device_intr_enter(struct usb_xfer *xfer)
3415 {
3416 return;
3417 }
3418
3419 static void
musbotg_device_intr_start(struct usb_xfer * xfer)3420 musbotg_device_intr_start(struct usb_xfer *xfer)
3421 {
3422 /* setup TDs */
3423 musbotg_setup_standard_chain(xfer);
3424 musbotg_start_standard_chain(xfer);
3425 }
3426
3427 static const struct usb_pipe_methods musbotg_device_intr_methods =
3428 {
3429 .open = musbotg_device_intr_open,
3430 .close = musbotg_device_intr_close,
3431 .enter = musbotg_device_intr_enter,
3432 .start = musbotg_device_intr_start,
3433 };
3434
3435 /*------------------------------------------------------------------------*
3436 * musbotg full speed isochronous support
3437 *------------------------------------------------------------------------*/
3438 static void
musbotg_device_isoc_open(struct usb_xfer * xfer)3439 musbotg_device_isoc_open(struct usb_xfer *xfer)
3440 {
3441 return;
3442 }
3443
3444 static void
musbotg_device_isoc_close(struct usb_xfer * xfer)3445 musbotg_device_isoc_close(struct usb_xfer *xfer)
3446 {
3447 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3448 }
3449
3450 static void
musbotg_device_isoc_enter(struct usb_xfer * xfer)3451 musbotg_device_isoc_enter(struct usb_xfer *xfer)
3452 {
3453 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
3454 uint32_t temp;
3455 uint32_t nframes;
3456 uint32_t fs_frames;
3457
3458 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n",
3459 xfer, xfer->endpoint->isoc_next, xfer->nframes);
3460
3461 /* get the current frame index */
3462
3463 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME);
3464
3465 /*
3466 * check if the frame index is within the window where the frames
3467 * will be inserted
3468 */
3469 temp = (nframes - xfer->endpoint->isoc_next) & MUSB2_MASK_FRAME;
3470
3471 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
3472 fs_frames = (xfer->nframes + 7) / 8;
3473 } else {
3474 fs_frames = xfer->nframes;
3475 }
3476
3477 if ((xfer->endpoint->is_synced == 0) ||
3478 (temp < fs_frames)) {
3479 /*
3480 * If there is data underflow or the pipe queue is
3481 * empty we schedule the transfer a few frames ahead
3482 * of the current frame position. Else two isochronous
3483 * transfers might overlap.
3484 */
3485 xfer->endpoint->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME;
3486 xfer->endpoint->is_synced = 1;
3487 DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next);
3488 }
3489 /*
3490 * compute how many milliseconds the insertion is ahead of the
3491 * current frame position:
3492 */
3493 temp = (xfer->endpoint->isoc_next - nframes) & MUSB2_MASK_FRAME;
3494
3495 /*
3496 * pre-compute when the isochronous transfer will be finished:
3497 */
3498 xfer->isoc_time_complete =
3499 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
3500 fs_frames;
3501
3502 /* compute frame number for next insertion */
3503 xfer->endpoint->isoc_next += fs_frames;
3504
3505 /* setup TDs */
3506 musbotg_setup_standard_chain(xfer);
3507 }
3508
3509 static void
musbotg_device_isoc_start(struct usb_xfer * xfer)3510 musbotg_device_isoc_start(struct usb_xfer *xfer)
3511 {
3512 /* start TD chain */
3513 musbotg_start_standard_chain(xfer);
3514 }
3515
3516 static const struct usb_pipe_methods musbotg_device_isoc_methods =
3517 {
3518 .open = musbotg_device_isoc_open,
3519 .close = musbotg_device_isoc_close,
3520 .enter = musbotg_device_isoc_enter,
3521 .start = musbotg_device_isoc_start,
3522 };
3523
3524 /*------------------------------------------------------------------------*
3525 * musbotg root control support
3526 *------------------------------------------------------------------------*
3527 * Simulate a hardware HUB by handling all the necessary requests.
3528 *------------------------------------------------------------------------*/
3529
3530 static const struct usb_device_descriptor musbotg_devd = {
3531 .bLength = sizeof(struct usb_device_descriptor),
3532 .bDescriptorType = UDESC_DEVICE,
3533 .bcdUSB = {0x00, 0x02},
3534 .bDeviceClass = UDCLASS_HUB,
3535 .bDeviceSubClass = UDSUBCLASS_HUB,
3536 .bDeviceProtocol = UDPROTO_HSHUBSTT,
3537 .bMaxPacketSize = 64,
3538 .bcdDevice = {0x00, 0x01},
3539 .iManufacturer = 1,
3540 .iProduct = 2,
3541 .bNumConfigurations = 1,
3542 };
3543
3544 static const struct usb_device_qualifier musbotg_odevd = {
3545 .bLength = sizeof(struct usb_device_qualifier),
3546 .bDescriptorType = UDESC_DEVICE_QUALIFIER,
3547 .bcdUSB = {0x00, 0x02},
3548 .bDeviceClass = UDCLASS_HUB,
3549 .bDeviceSubClass = UDSUBCLASS_HUB,
3550 .bDeviceProtocol = UDPROTO_FSHUB,
3551 .bMaxPacketSize0 = 0,
3552 .bNumConfigurations = 0,
3553 };
3554
3555 static const struct musbotg_config_desc musbotg_confd = {
3556 .confd = {
3557 .bLength = sizeof(struct usb_config_descriptor),
3558 .bDescriptorType = UDESC_CONFIG,
3559 .wTotalLength[0] = sizeof(musbotg_confd),
3560 .bNumInterface = 1,
3561 .bConfigurationValue = 1,
3562 .iConfiguration = 0,
3563 .bmAttributes = UC_SELF_POWERED,
3564 .bMaxPower = 0,
3565 },
3566 .ifcd = {
3567 .bLength = sizeof(struct usb_interface_descriptor),
3568 .bDescriptorType = UDESC_INTERFACE,
3569 .bNumEndpoints = 1,
3570 .bInterfaceClass = UICLASS_HUB,
3571 .bInterfaceSubClass = UISUBCLASS_HUB,
3572 .bInterfaceProtocol = 0,
3573 },
3574 .endpd = {
3575 .bLength = sizeof(struct usb_endpoint_descriptor),
3576 .bDescriptorType = UDESC_ENDPOINT,
3577 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT),
3578 .bmAttributes = UE_INTERRUPT,
3579 .wMaxPacketSize[0] = 8,
3580 .bInterval = 255,
3581 },
3582 };
3583
3584 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3585
3586 static const struct usb_hub_descriptor_min musbotg_hubd = {
3587 .bDescLength = sizeof(musbotg_hubd),
3588 .bDescriptorType = UDESC_HUB,
3589 .bNbrPorts = 1,
3590 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
3591 .bPwrOn2PwrGood = 50,
3592 .bHubContrCurrent = 0,
3593 .DeviceRemovable = {0}, /* port is removable */
3594 };
3595
3596 #define STRING_VENDOR \
3597 "M\0e\0n\0t\0o\0r\0 \0G\0r\0a\0p\0h\0i\0c\0s"
3598
3599 #define STRING_PRODUCT \
3600 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B"
3601
3602 USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor);
3603 USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product);
3604
3605 static usb_error_t
musbotg_roothub_exec(struct usb_device * udev,struct usb_device_request * req,const void ** pptr,uint16_t * plength)3606 musbotg_roothub_exec(struct usb_device *udev,
3607 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3608 {
3609 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
3610 const void *ptr;
3611 uint16_t len;
3612 uint16_t value;
3613 uint16_t index;
3614 uint8_t reg;
3615 usb_error_t err;
3616
3617 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3618
3619 /* buffer reset */
3620 ptr = (const void *)&sc->sc_hub_temp;
3621 len = 0;
3622 err = 0;
3623
3624 value = UGETW(req->wValue);
3625 index = UGETW(req->wIndex);
3626
3627 /* demultiplex the control request */
3628
3629 switch (req->bmRequestType) {
3630 case UT_READ_DEVICE:
3631 switch (req->bRequest) {
3632 case UR_GET_DESCRIPTOR:
3633 goto tr_handle_get_descriptor;
3634 case UR_GET_CONFIG:
3635 goto tr_handle_get_config;
3636 case UR_GET_STATUS:
3637 goto tr_handle_get_status;
3638 default:
3639 goto tr_stalled;
3640 }
3641 break;
3642
3643 case UT_WRITE_DEVICE:
3644 switch (req->bRequest) {
3645 case UR_SET_ADDRESS:
3646 goto tr_handle_set_address;
3647 case UR_SET_CONFIG:
3648 goto tr_handle_set_config;
3649 case UR_CLEAR_FEATURE:
3650 goto tr_valid; /* nop */
3651 case UR_SET_DESCRIPTOR:
3652 goto tr_valid; /* nop */
3653 case UR_SET_FEATURE:
3654 default:
3655 goto tr_stalled;
3656 }
3657 break;
3658
3659 case UT_WRITE_ENDPOINT:
3660 switch (req->bRequest) {
3661 case UR_CLEAR_FEATURE:
3662 switch (UGETW(req->wValue)) {
3663 case UF_ENDPOINT_HALT:
3664 goto tr_handle_clear_halt;
3665 case UF_DEVICE_REMOTE_WAKEUP:
3666 goto tr_handle_clear_wakeup;
3667 default:
3668 goto tr_stalled;
3669 }
3670 break;
3671 case UR_SET_FEATURE:
3672 switch (UGETW(req->wValue)) {
3673 case UF_ENDPOINT_HALT:
3674 goto tr_handle_set_halt;
3675 case UF_DEVICE_REMOTE_WAKEUP:
3676 goto tr_handle_set_wakeup;
3677 default:
3678 goto tr_stalled;
3679 }
3680 break;
3681 case UR_SYNCH_FRAME:
3682 goto tr_valid; /* nop */
3683 default:
3684 goto tr_stalled;
3685 }
3686 break;
3687
3688 case UT_READ_ENDPOINT:
3689 switch (req->bRequest) {
3690 case UR_GET_STATUS:
3691 goto tr_handle_get_ep_status;
3692 default:
3693 goto tr_stalled;
3694 }
3695 break;
3696
3697 case UT_WRITE_INTERFACE:
3698 switch (req->bRequest) {
3699 case UR_SET_INTERFACE:
3700 goto tr_handle_set_interface;
3701 case UR_CLEAR_FEATURE:
3702 goto tr_valid; /* nop */
3703 case UR_SET_FEATURE:
3704 default:
3705 goto tr_stalled;
3706 }
3707 break;
3708
3709 case UT_READ_INTERFACE:
3710 switch (req->bRequest) {
3711 case UR_GET_INTERFACE:
3712 goto tr_handle_get_interface;
3713 case UR_GET_STATUS:
3714 goto tr_handle_get_iface_status;
3715 default:
3716 goto tr_stalled;
3717 }
3718 break;
3719
3720 case UT_WRITE_CLASS_INTERFACE:
3721 case UT_WRITE_VENDOR_INTERFACE:
3722 /* XXX forward */
3723 break;
3724
3725 case UT_READ_CLASS_INTERFACE:
3726 case UT_READ_VENDOR_INTERFACE:
3727 /* XXX forward */
3728 break;
3729
3730 case UT_WRITE_CLASS_DEVICE:
3731 switch (req->bRequest) {
3732 case UR_CLEAR_FEATURE:
3733 goto tr_valid;
3734 case UR_SET_DESCRIPTOR:
3735 case UR_SET_FEATURE:
3736 break;
3737 default:
3738 goto tr_stalled;
3739 }
3740 break;
3741
3742 case UT_WRITE_CLASS_OTHER:
3743 switch (req->bRequest) {
3744 case UR_CLEAR_FEATURE:
3745 goto tr_handle_clear_port_feature;
3746 case UR_SET_FEATURE:
3747 goto tr_handle_set_port_feature;
3748 case UR_CLEAR_TT_BUFFER:
3749 case UR_RESET_TT:
3750 case UR_STOP_TT:
3751 goto tr_valid;
3752
3753 default:
3754 goto tr_stalled;
3755 }
3756 break;
3757
3758 case UT_READ_CLASS_OTHER:
3759 switch (req->bRequest) {
3760 case UR_GET_TT_STATE:
3761 goto tr_handle_get_tt_state;
3762 case UR_GET_STATUS:
3763 goto tr_handle_get_port_status;
3764 default:
3765 goto tr_stalled;
3766 }
3767 break;
3768
3769 case UT_READ_CLASS_DEVICE:
3770 switch (req->bRequest) {
3771 case UR_GET_DESCRIPTOR:
3772 goto tr_handle_get_class_descriptor;
3773 case UR_GET_STATUS:
3774 goto tr_handle_get_class_status;
3775
3776 default:
3777 goto tr_stalled;
3778 }
3779 break;
3780 default:
3781 goto tr_stalled;
3782 }
3783 goto tr_valid;
3784
3785 tr_handle_get_descriptor:
3786 switch (value >> 8) {
3787 case UDESC_DEVICE:
3788 if (value & 0xff) {
3789 goto tr_stalled;
3790 }
3791 len = sizeof(musbotg_devd);
3792 ptr = (const void *)&musbotg_devd;
3793 goto tr_valid;
3794 case UDESC_DEVICE_QUALIFIER:
3795 if (value & 0xff) {
3796 goto tr_stalled;
3797 }
3798 len = sizeof(musbotg_odevd);
3799 ptr = (const void *)&musbotg_odevd;
3800 goto tr_valid;
3801 case UDESC_CONFIG:
3802 if (value & 0xff) {
3803 goto tr_stalled;
3804 }
3805 len = sizeof(musbotg_confd);
3806 ptr = (const void *)&musbotg_confd;
3807 goto tr_valid;
3808 case UDESC_STRING:
3809 switch (value & 0xff) {
3810 case 0: /* Language table */
3811 len = sizeof(usb_string_lang_en);
3812 ptr = (const void *)&usb_string_lang_en;
3813 goto tr_valid;
3814
3815 case 1: /* Vendor */
3816 len = sizeof(musbotg_vendor);
3817 ptr = (const void *)&musbotg_vendor;
3818 goto tr_valid;
3819
3820 case 2: /* Product */
3821 len = sizeof(musbotg_product);
3822 ptr = (const void *)&musbotg_product;
3823 goto tr_valid;
3824 default:
3825 break;
3826 }
3827 break;
3828 default:
3829 goto tr_stalled;
3830 }
3831 goto tr_stalled;
3832
3833 tr_handle_get_config:
3834 len = 1;
3835 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
3836 goto tr_valid;
3837
3838 tr_handle_get_status:
3839 len = 2;
3840 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
3841 goto tr_valid;
3842
3843 tr_handle_set_address:
3844 if (value & 0xFF00) {
3845 goto tr_stalled;
3846 }
3847 sc->sc_rt_addr = value;
3848 goto tr_valid;
3849
3850 tr_handle_set_config:
3851 if (value >= 2) {
3852 goto tr_stalled;
3853 }
3854 sc->sc_conf = value;
3855 goto tr_valid;
3856
3857 tr_handle_get_interface:
3858 len = 1;
3859 sc->sc_hub_temp.wValue[0] = 0;
3860 goto tr_valid;
3861
3862 tr_handle_get_tt_state:
3863 tr_handle_get_class_status:
3864 tr_handle_get_iface_status:
3865 tr_handle_get_ep_status:
3866 len = 2;
3867 USETW(sc->sc_hub_temp.wValue, 0);
3868 goto tr_valid;
3869
3870 tr_handle_set_halt:
3871 tr_handle_set_interface:
3872 tr_handle_set_wakeup:
3873 tr_handle_clear_wakeup:
3874 tr_handle_clear_halt:
3875 goto tr_valid;
3876
3877 tr_handle_clear_port_feature:
3878 if (index != 1) {
3879 goto tr_stalled;
3880 }
3881 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
3882
3883 switch (value) {
3884 case UHF_PORT_SUSPEND:
3885 if (sc->sc_mode == MUSB2_HOST_MODE)
3886 musbotg_wakeup_host(sc);
3887 else
3888 musbotg_wakeup_peer(sc);
3889 break;
3890
3891 case UHF_PORT_ENABLE:
3892 sc->sc_flags.port_enabled = 0;
3893 break;
3894
3895 case UHF_C_PORT_ENABLE:
3896 sc->sc_flags.change_enabled = 0;
3897 break;
3898
3899 case UHF_C_PORT_OVER_CURRENT:
3900 sc->sc_flags.change_over_current = 0;
3901 break;
3902
3903 case UHF_C_PORT_RESET:
3904 sc->sc_flags.change_reset = 0;
3905 break;
3906
3907 case UHF_PORT_TEST:
3908 case UHF_PORT_INDICATOR:
3909 /* nops */
3910 break;
3911
3912 case UHF_PORT_POWER:
3913 sc->sc_flags.port_powered = 0;
3914 musbotg_pull_down(sc);
3915 musbotg_clocks_off(sc);
3916 break;
3917 case UHF_C_PORT_CONNECTION:
3918 sc->sc_flags.change_connect = 0;
3919 break;
3920 case UHF_C_PORT_SUSPEND:
3921 sc->sc_flags.change_suspend = 0;
3922 break;
3923 default:
3924 err = USB_ERR_IOERROR;
3925 goto done;
3926 }
3927 goto tr_valid;
3928
3929 tr_handle_set_port_feature:
3930 if (index != 1) {
3931 goto tr_stalled;
3932 }
3933 DPRINTFN(8, "UR_SET_PORT_FEATURE\n");
3934
3935 switch (value) {
3936 case UHF_PORT_ENABLE:
3937 sc->sc_flags.port_enabled = 1;
3938 break;
3939 case UHF_PORT_SUSPEND:
3940 if (sc->sc_mode == MUSB2_HOST_MODE)
3941 musbotg_suspend_host(sc);
3942 break;
3943
3944 case UHF_PORT_RESET:
3945 if (sc->sc_mode == MUSB2_HOST_MODE) {
3946 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3947 reg |= MUSB2_MASK_RESET;
3948 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);
3949
3950 /* Wait for 20 msec */
3951 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 5);
3952
3953 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3954 reg &= ~MUSB2_MASK_RESET;
3955 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);
3956
3957 /* determine line speed */
3958 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3959 if (reg & MUSB2_MASK_HSMODE)
3960 sc->sc_flags.status_high_speed = 1;
3961 else
3962 sc->sc_flags.status_high_speed = 0;
3963
3964 sc->sc_flags.change_reset = 1;
3965 } else
3966 err = USB_ERR_IOERROR;
3967 break;
3968
3969 case UHF_PORT_TEST:
3970 case UHF_PORT_INDICATOR:
3971 /* nops */
3972 break;
3973 case UHF_PORT_POWER:
3974 sc->sc_flags.port_powered = 1;
3975 break;
3976 default:
3977 err = USB_ERR_IOERROR;
3978 goto done;
3979 }
3980 goto tr_valid;
3981
3982 tr_handle_get_port_status:
3983
3984 DPRINTFN(8, "UR_GET_PORT_STATUS\n");
3985
3986 if (index != 1) {
3987 goto tr_stalled;
3988 }
3989 if (sc->sc_flags.status_vbus) {
3990 musbotg_clocks_on(sc);
3991 musbotg_pull_up(sc);
3992 } else {
3993 musbotg_pull_down(sc);
3994 musbotg_clocks_off(sc);
3995 }
3996
3997 /* Select Device Side Mode */
3998 if (sc->sc_mode == MUSB2_DEVICE_MODE)
3999 value = UPS_PORT_MODE_DEVICE;
4000 else
4001 value = 0;
4002
4003 if (sc->sc_flags.status_high_speed) {
4004 value |= UPS_HIGH_SPEED;
4005 }
4006 if (sc->sc_flags.port_powered) {
4007 value |= UPS_PORT_POWER;
4008 }
4009 if (sc->sc_flags.port_enabled) {
4010 value |= UPS_PORT_ENABLED;
4011 }
4012
4013 if (sc->sc_flags.port_over_current)
4014 value |= UPS_OVERCURRENT_INDICATOR;
4015
4016 if (sc->sc_flags.status_vbus &&
4017 sc->sc_flags.status_bus_reset) {
4018 value |= UPS_CURRENT_CONNECT_STATUS;
4019 }
4020 if (sc->sc_flags.status_suspend) {
4021 value |= UPS_SUSPEND;
4022 }
4023 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
4024
4025 value = 0;
4026
4027 if (sc->sc_flags.change_connect) {
4028 value |= UPS_C_CONNECT_STATUS;
4029
4030 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
4031 if (sc->sc_flags.status_vbus &&
4032 sc->sc_flags.status_bus_reset) {
4033 /* reset EP0 state */
4034 sc->sc_ep0_busy = 0;
4035 sc->sc_ep0_cmd = 0;
4036 }
4037 }
4038 }
4039 if (sc->sc_flags.change_suspend)
4040 value |= UPS_C_SUSPEND;
4041 if (sc->sc_flags.change_reset)
4042 value |= UPS_C_PORT_RESET;
4043 if (sc->sc_flags.change_over_current)
4044 value |= UPS_C_OVERCURRENT_INDICATOR;
4045
4046 USETW(sc->sc_hub_temp.ps.wPortChange, value);
4047 len = sizeof(sc->sc_hub_temp.ps);
4048 goto tr_valid;
4049
4050 tr_handle_get_class_descriptor:
4051 if (value & 0xFF) {
4052 goto tr_stalled;
4053 }
4054 ptr = (const void *)&musbotg_hubd;
4055 len = sizeof(musbotg_hubd);
4056 goto tr_valid;
4057
4058 tr_stalled:
4059 err = USB_ERR_STALLED;
4060 tr_valid:
4061 done:
4062 *plength = len;
4063 *pptr = ptr;
4064 return (err);
4065 }
4066
4067 static void
musbotg_xfer_setup(struct usb_setup_params * parm)4068 musbotg_xfer_setup(struct usb_setup_params *parm)
4069 {
4070 struct musbotg_softc *sc;
4071 struct usb_xfer *xfer;
4072 void *last_obj;
4073 uint32_t ntd;
4074 uint32_t n;
4075 uint8_t ep_no;
4076
4077 sc = MUSBOTG_BUS2SC(parm->udev->bus);
4078 xfer = parm->curr_xfer;
4079
4080 /*
4081 * NOTE: This driver does not use any of the parameters that
4082 * are computed from the following values. Just set some
4083 * reasonable dummies:
4084 */
4085 parm->hc_max_packet_size = 0x400;
4086 parm->hc_max_frame_size = 0xc00;
4087
4088 if ((parm->methods == &musbotg_device_isoc_methods) ||
4089 (parm->methods == &musbotg_device_intr_methods))
4090 parm->hc_max_packet_count = 3;
4091 else
4092 parm->hc_max_packet_count = 1;
4093
4094 usbd_transfer_setup_sub(parm);
4095
4096 /*
4097 * compute maximum number of TDs
4098 */
4099 if (parm->methods == &musbotg_device_ctrl_methods) {
4100
4101 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ;
4102
4103 } else if (parm->methods == &musbotg_device_bulk_methods) {
4104
4105 ntd = xfer->nframes + 1 /* SYNC */ ;
4106
4107 } else if (parm->methods == &musbotg_device_intr_methods) {
4108
4109 ntd = xfer->nframes + 1 /* SYNC */ ;
4110
4111 } else if (parm->methods == &musbotg_device_isoc_methods) {
4112
4113 ntd = xfer->nframes + 1 /* SYNC */ ;
4114
4115 } else {
4116
4117 ntd = 0;
4118 }
4119
4120 /*
4121 * check if "usbd_transfer_setup_sub" set an error
4122 */
4123 if (parm->err) {
4124 return;
4125 }
4126 /*
4127 * allocate transfer descriptors
4128 */
4129 last_obj = NULL;
4130
4131 ep_no = xfer->endpointno & UE_ADDR;
4132
4133 /*
4134 * Check for a valid endpoint profile in USB device mode:
4135 */
4136 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
4137 const struct usb_hw_ep_profile *pf;
4138
4139 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no);
4140
4141 if (pf == NULL) {
4142 /* should not happen */
4143 parm->err = USB_ERR_INVAL;
4144 return;
4145 }
4146 }
4147
4148 /* align data */
4149 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
4150
4151 for (n = 0; n != ntd; n++) {
4152
4153 struct musbotg_td *td;
4154
4155 if (parm->buf) {
4156
4157 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
4158
4159 /* init TD */
4160 td->max_frame_size = xfer->max_frame_size;
4161 td->reg_max_packet = xfer->max_packet_size |
4162 ((xfer->max_packet_count - 1) << 11);
4163 td->ep_no = ep_no;
4164 td->obj_next = last_obj;
4165
4166 last_obj = td;
4167 }
4168 parm->size[0] += sizeof(*td);
4169 }
4170
4171 xfer->td_start[0] = last_obj;
4172 }
4173
4174 static void
musbotg_xfer_unsetup(struct usb_xfer * xfer)4175 musbotg_xfer_unsetup(struct usb_xfer *xfer)
4176 {
4177 return;
4178 }
4179
4180 static void
musbotg_get_dma_delay(struct usb_device * udev,uint32_t * pus)4181 musbotg_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4182 {
4183 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
4184
4185 if (sc->sc_mode == MUSB2_HOST_MODE)
4186 *pus = 2000; /* microseconds */
4187 else
4188 *pus = 0;
4189 }
4190
4191 static void
musbotg_ep_init(struct usb_device * udev,struct usb_endpoint_descriptor * edesc,struct usb_endpoint * ep)4192 musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4193 struct usb_endpoint *ep)
4194 {
4195 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
4196
4197 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
4198 ep, udev->address,
4199 edesc->bEndpointAddress, udev->flags.usb_mode,
4200 sc->sc_rt_addr);
4201
4202 if (udev->device_index != sc->sc_rt_addr) {
4203 switch (edesc->bmAttributes & UE_XFERTYPE) {
4204 case UE_CONTROL:
4205 ep->methods = &musbotg_device_ctrl_methods;
4206 break;
4207 case UE_INTERRUPT:
4208 ep->methods = &musbotg_device_intr_methods;
4209 break;
4210 case UE_ISOCHRONOUS:
4211 ep->methods = &musbotg_device_isoc_methods;
4212 break;
4213 case UE_BULK:
4214 ep->methods = &musbotg_device_bulk_methods;
4215 break;
4216 default:
4217 /* do nothing */
4218 break;
4219 }
4220 }
4221 }
4222
4223 static void
musbotg_set_hw_power_sleep(struct usb_bus * bus,uint32_t state)4224 musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
4225 {
4226 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
4227
4228 switch (state) {
4229 case USB_HW_POWER_SUSPEND:
4230 musbotg_uninit(sc);
4231 break;
4232 case USB_HW_POWER_SHUTDOWN:
4233 musbotg_uninit(sc);
4234 break;
4235 case USB_HW_POWER_RESUME:
4236 musbotg_init(sc);
4237 break;
4238 default:
4239 break;
4240 }
4241 }
4242
4243 static const struct usb_bus_methods musbotg_bus_methods =
4244 {
4245 .endpoint_init = &musbotg_ep_init,
4246 .get_dma_delay = &musbotg_get_dma_delay,
4247 .xfer_setup = &musbotg_xfer_setup,
4248 .xfer_unsetup = &musbotg_xfer_unsetup,
4249 .get_hw_ep_profile = &musbotg_get_hw_ep_profile,
4250 .xfer_stall = &musbotg_xfer_stall,
4251 .set_stall = &musbotg_set_stall,
4252 .clear_stall = &musbotg_clear_stall,
4253 .roothub_exec = &musbotg_roothub_exec,
4254 .xfer_poll = &musbotg_do_poll,
4255 .set_hw_power_sleep = &musbotg_set_hw_power_sleep,
4256 };
4257