1 /* $NetBSD: magma.c,v 1.64 2021/08/07 16:19:15 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 1998 Iain Hibbert
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 /*
29 * Driver for Magma SBus Serial/Parallel cards using the Cirrus Logic
30 * CD1400 & CD1190 chips
31 */
32
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: magma.c,v 1.64 2021/08/07 16:19:15 thorpej Exp $");
35
36 #if 0
37 #define MAGMA_DEBUG
38 #endif
39
40 #include "magma.h"
41 #if NMAGMA > 0
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/proc.h>
46 #include <sys/device.h>
47 #include <sys/file.h>
48 #include <sys/ioctl.h>
49 #include <sys/malloc.h>
50 #include <sys/tty.h>
51 #include <sys/time.h>
52 #include <sys/kernel.h>
53 #include <sys/syslog.h>
54 #include <sys/conf.h>
55 #include <sys/errno.h>
56 #include <sys/kauth.h>
57 #include <sys/intr.h>
58
59 #include <sys/bus.h>
60 #include <machine/autoconf.h>
61
62 #include <dev/sbus/sbusvar.h>
63
64 #include <dev/ic/cd1400reg.h>
65 #include <dev/ic/cd1190reg.h>
66
67 #include <dev/sbus/mbppio.h>
68 #include <dev/sbus/magmareg.h>
69
70 #include "ioconf.h"
71
72 /* supported cards
73 *
74 * The table below lists the cards that this driver is likely to
75 * be able to support.
76 *
77 * Cards with parallel ports: except for the LC2+1Sp, they all use
78 * the CD1190 chip which I know nothing about. I've tried to leave
79 * hooks for it so it shouldn't be too hard to add support later.
80 * (I think somebody is working on this separately)
81 *
82 * Thanks to Bruce at Magma for telling me the hardware offsets.
83 */
84 static struct magma_board_info supported_cards[] = {
85 {
86 "MAGMA_Sp", "MAGMA,4_Sp", "Magma 4 Sp", 4, 0,
87 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 },
88 0, { 0, 0 }
89 },
90 {
91 "MAGMA_Sp", "MAGMA,8_Sp", "Magma 8 Sp", 8, 0,
92 2, 0xa000, 0xc000, 0xe000, { 0x4000, 0x6000, 0, 0 },
93 0, { 0, 0 }
94 },
95 {
96 "MAGMA_Sp", "MAGMA,_8HS_Sp", "Magma Fast 8 Sp", 8, 0,
97 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 },
98 0, { 0, 0 }
99 },
100 {
101 "MAGMA_Sp", "MAGMA,_8SP_422", "Magma 8 Sp - 422", 8, 0,
102 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 },
103 0, { 0, 0 }
104 },
105 {
106 "MAGMA_Sp", "MAGMA,12_Sp", "Magma 12 Sp", 12, 0,
107 3, 0xa000, 0xc000, 0xe000, { 0x2000, 0x4000, 0x6000, 0 },
108 0, { 0, 0 }
109 },
110 {
111 "MAGMA_Sp", "MAGMA,16_Sp", "Magma 16 Sp", 16, 0,
112 4, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0xa000, 0xb000 },
113 0, { 0, 0 }
114 },
115 {
116 "MAGMA_Sp", "MAGMA,16_Sp_2", "Magma 16 Sp", 16, 0,
117 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 },
118 0, { 0, 0 }
119 },
120 {
121 "MAGMA_Sp", "MAGMA,16HS_Sp", "Magma Fast 16 Sp", 16, 0,
122 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 },
123 0, { 0, 0 }
124 },
125 {
126 "MAGMA_Sp", "MAGMA,21_Sp", "Magma LC 2+1 Sp", 2, 1,
127 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 },
128 0, { 0, 0 }
129 },
130 {
131 "MAGMA_Sp", "MAGMA,21HS_Sp", "Magma 2+1 Sp", 2, 1,
132 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 },
133 1, { 0x6000, 0 }
134 },
135 {
136 "MAGMA_Sp", "MAGMA,41_Sp", "Magma 4+1 Sp", 4, 1,
137 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 },
138 1, { 0x6000, 0 }
139 },
140 {
141 "MAGMA_Sp", "MAGMA,82_Sp", "Magma 8+2 Sp", 8, 2,
142 2, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0, 0 },
143 2, { 0xa000, 0xb000 }
144 },
145 {
146 "MAGMA_Sp", "MAGMA,P1_Sp", "Magma P1 Sp", 0, 1,
147 0, 0, 0, 0, { 0, 0, 0, 0 },
148 1, { 0x8000, 0 }
149 },
150 {
151 "MAGMA_Sp", "MAGMA,P2_Sp", "Magma P2 Sp", 0, 2,
152 0, 0, 0, 0, { 0, 0, 0, 0 },
153 2, { 0x4000, 0x8000 }
154 },
155 {
156 "MAGMA 2+1HS Sp", "", "Magma 2+1HS Sp", 2, 0,
157 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 },
158 1, { 0x8000, 0 }
159 },
160 {
161 NULL, NULL, NULL, 0, 0,
162 0, 0, 0, 0, { 0, 0, 0, 0 },
163 0, { 0, 0 }
164 }
165 };
166
167 /************************************************************************
168 *
169 * Autoconfig Stuff
170 */
171
172 CFATTACH_DECL_NEW(magma, sizeof(struct magma_softc),
173 magma_match, magma_attach, NULL, NULL);
174
175 CFATTACH_DECL_NEW(mtty, sizeof(struct mtty_softc),
176 mtty_match, mtty_attach, NULL, NULL);
177
178 CFATTACH_DECL_NEW(mbpp, sizeof(struct mbpp_softc),
179 mbpp_match, mbpp_attach, NULL, NULL);
180
181 dev_type_open(mttyopen);
182 dev_type_close(mttyclose);
183 dev_type_read(mttyread);
184 dev_type_write(mttywrite);
185 dev_type_ioctl(mttyioctl);
186 dev_type_stop(mttystop);
187 dev_type_tty(mttytty);
188 dev_type_poll(mttypoll);
189
190 const struct cdevsw mtty_cdevsw = {
191 .d_open = mttyopen,
192 .d_close = mttyclose,
193 .d_read = mttyread,
194 .d_write = mttywrite,
195 .d_ioctl = mttyioctl,
196 .d_stop = mttystop,
197 .d_tty = mttytty,
198 .d_poll = mttypoll,
199 .d_mmap = nommap,
200 .d_kqfilter = ttykqfilter,
201 .d_discard = nodiscard,
202 .d_flag = D_TTY
203 };
204
205 dev_type_open(mbppopen);
206 dev_type_close(mbppclose);
207 dev_type_read(mbpp_rw);
208 dev_type_ioctl(mbppioctl);
209
210 const struct cdevsw mbpp_cdevsw = {
211 .d_open = mbppopen,
212 .d_close = mbppclose,
213 .d_read = mbpp_rw,
214 .d_write = mbpp_rw,
215 .d_ioctl = mbppioctl,
216 .d_stop = nostop,
217 .d_tty = notty,
218 .d_poll = nopoll,
219 .d_mmap = nommap,
220 .d_kqfilter = nokqfilter,
221 .d_discard = nodiscard,
222 .d_flag = D_OTHER
223 };
224
225 /************************************************************************
226 *
227 * CD1400 Routines
228 *
229 * cd1400_compute_baud calculate COR/BPR register values
230 * cd1400_write_ccr write a value to CD1400 ccr
231 * cd1400_read_reg read from a CD1400 register
232 * cd1400_write_reg write to a CD1400 register
233 * cd1400_enable_transmitter enable transmitting on CD1400 channel
234 */
235
236 /*
237 * compute the bpr/cor pair for any baud rate
238 * returns 0 for success, 1 for failure
239 */
240 int
cd1400_compute_baud(speed_t speed,int clock,int * cor,int * bpr)241 cd1400_compute_baud(speed_t speed, int clock, int *cor, int *bpr)
242 {
243 int c, co, br;
244
245 if( speed < 50 || speed > 150000 )
246 return(1);
247
248 for( c = 0, co = 8 ; co <= 2048 ; co <<= 2, c++ ) {
249 br = ((clock * 1000000) + (co * speed) / 2) / (co * speed);
250 if( br < 0x100 ) {
251 *bpr = br;
252 *cor = c;
253 return(0);
254 }
255 }
256
257 return(1);
258 }
259
260 /*
261 * Write a CD1400 channel command, should have a timeout?
262 */
263 inline void
cd1400_write_ccr(struct cd1400 * cd,u_char cmd)264 cd1400_write_ccr(struct cd1400 *cd, u_char cmd)
265 {
266 while( cd1400_read_reg(cd, CD1400_CCR) )
267 ;
268
269 cd1400_write_reg(cd, CD1400_CCR, cmd);
270 }
271
272 /*
273 * read a value from a cd1400 register
274 */
275 inline u_char
cd1400_read_reg(struct cd1400 * cd,int reg)276 cd1400_read_reg(struct cd1400 *cd, int reg)
277 {
278 return(cd->cd_reg[reg]);
279 }
280
281 /*
282 * write a value to a cd1400 register
283 */
284 inline void
cd1400_write_reg(struct cd1400 * cd,int reg,u_char value)285 cd1400_write_reg(struct cd1400 *cd, int reg, u_char value)
286 {
287 cd->cd_reg[reg] = value;
288 }
289
290 /*
291 * enable transmit service requests for cd1400 channel
292 */
293 void
cd1400_enable_transmitter(struct cd1400 * cd,int channel)294 cd1400_enable_transmitter(struct cd1400 *cd, int channel)
295 {
296 int s, srer;
297
298 s = spltty();
299 cd1400_write_reg(cd, CD1400_CAR, channel);
300 srer = cd1400_read_reg(cd, CD1400_SRER);
301 SET(srer, CD1400_SRER_TXRDY);
302 cd1400_write_reg(cd, CD1400_SRER, srer);
303 splx(s);
304 }
305
306 /************************************************************************
307 *
308 * CD1190 Routines
309 */
310
311 /* well, there are none yet */
312
313 /************************************************************************
314 *
315 * Magma Routines
316 *
317 * magma_match reports if we have a magma board available
318 * magma_attach attaches magma boards to the sbus
319 * magma_hard hardware level interrupt routine
320 * magma_soft software level interrupt routine
321 */
322
323 int
magma_match(device_t parent,cfdata_t cf,void * aux)324 magma_match(device_t parent, cfdata_t cf, void *aux)
325 {
326 struct sbus_attach_args *sa = aux;
327 struct magma_board_info *card;
328
329 /* See if we support this device */
330 for (card = supported_cards; ; card++) {
331 if (card->mb_sbusname == NULL)
332 /* End of table: no match */
333 return (0);
334 if (strcmp(sa->sa_name, card->mb_sbusname) == 0)
335 break;
336 }
337
338 dprintf(("magma: matched `%s'\n", sa->sa_name));
339 dprintf(("magma: magma_prom `%s'\n",
340 prom_getpropstring(sa->sa_node, "magma_prom")));
341 dprintf(("magma: intlevels `%s'\n",
342 prom_getpropstring(sa->sa_node, "intlevels")));
343 dprintf(("magma: chiprev `%s'\n",
344 prom_getpropstring(sa->sa_node, "chiprev")));
345 dprintf(("magma: clock `%s'\n",
346 prom_getpropstring(sa->sa_node, "clock")));
347
348 return (1);
349 }
350
351 void
magma_attach(device_t parent,device_t self,void * aux)352 magma_attach(device_t parent, device_t self, void *aux)
353 {
354 struct sbus_attach_args *sa = aux;
355 struct magma_softc *sc = device_private(self);
356 struct magma_board_info *card;
357 bus_space_handle_t bh;
358 char *magma_prom, *clockstr;
359 int cd_clock;
360 int node, chip;
361
362 sc->ms_dev = self;
363 node = sa->sa_node;
364
365 /*
366 * Find the card model.
367 * Older models all have sbus node name `MAGMA_Sp' (see
368 * `supported_cards[]' above), and must be distinguished
369 * by the `magma_prom' property.
370 */
371 magma_prom = prom_getpropstring(node, "magma_prom");
372
373 for (card = supported_cards; card->mb_name != NULL; card++) {
374 if (strcmp(sa->sa_name, card->mb_sbusname) != 0)
375 /* Sbus node name doesn't match */
376 continue;
377 if (strcmp(magma_prom, card->mb_name) == 0)
378 /* Model name match */
379 break;
380 }
381
382 if( card->mb_name == NULL ) {
383 printf(": %s (unsupported)\n", magma_prom);
384 return;
385 }
386
387 dprintf((" addr %p", sc));
388 printf(": %s\n", card->mb_realname);
389
390 sc->ms_board = card;
391 sc->ms_ncd1400 = card->mb_ncd1400;
392 sc->ms_ncd1190 = card->mb_ncd1190;
393
394 if (sbus_bus_map(sa->sa_bustag,
395 sa->sa_slot, sa->sa_offset, sa->sa_size,
396 BUS_SPACE_MAP_LINEAR, &bh) != 0) {
397 aprint_error("%s @ sbus: cannot map registers\n",
398 device_xname(self));
399 return;
400 }
401
402 /* the SVCACK* lines are daisychained */
403 sc->ms_svcackr = (char *)bus_space_vaddr(sa->sa_bustag, bh)
404 + card->mb_svcackr;
405 sc->ms_svcackt = (char *)bus_space_vaddr(sa->sa_bustag, bh)
406 + card->mb_svcackt;
407 sc->ms_svcackm = (char *)bus_space_vaddr(sa->sa_bustag, bh)
408 + card->mb_svcackm;
409
410 /*
411 * Find the clock speed; it's the same for all CD1400 chips
412 * on the board.
413 */
414 clockstr = prom_getpropstring(node, "clock");
415 if (*clockstr == '\0')
416 /* Default to 25MHz */
417 cd_clock = 25;
418 else {
419 cd_clock = 0;
420 while (*clockstr != '\0')
421 cd_clock = (cd_clock * 10) + (*clockstr++ - '0');
422 }
423
424 /* init the cd1400 chips */
425 for( chip = 0 ; chip < card->mb_ncd1400 ; chip++ ) {
426 struct cd1400 *cd = &sc->ms_cd1400[chip];
427
428 cd->cd_clock = cd_clock;
429 cd->cd_reg = (char *)bus_space_vaddr(sa->sa_bustag, bh) +
430 card->mb_cd1400[chip];
431
432 /* prom_getpropstring(node, "chiprev"); */
433 /* seemingly the Magma drivers just ignore the propstring */
434 cd->cd_chiprev = cd1400_read_reg(cd, CD1400_GFRCR);
435
436 dprintf(("%s attach CD1400 %d addr %p rev %x clock %dMHz\n",
437 device_xname(sc->ms_dev), chip,
438 cd->cd_reg, cd->cd_chiprev, cd->cd_clock));
439
440 /* clear GFRCR */
441 cd1400_write_reg(cd, CD1400_GFRCR, 0x00);
442
443 /* reset whole chip */
444 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FULLRESET);
445
446 /* wait for revision code to be restored */
447 while( cd1400_read_reg(cd, CD1400_GFRCR) != cd->cd_chiprev )
448 ;
449
450 /* set the Prescaler Period Register to tick at 1ms */
451 cd1400_write_reg(cd, CD1400_PPR,
452 ((cd->cd_clock * 1000000 / CD1400_PPR_PRESCALER + 500) / 1000));
453
454 /* The LC2+1Sp card is the only card that doesn't have
455 * a CD1190 for the parallel port, but uses channel 0 of
456 * the CD1400, so we make a note of it for later and set up
457 * the CD1400 for parallel mode operation.
458 */
459 if( card->mb_npar && card->mb_ncd1190 == 0 ) {
460 cd1400_write_reg(cd, CD1400_GCR, CD1400_GCR_PARALLEL);
461 cd->cd_parmode = 1;
462 }
463 }
464
465 /* init the cd1190 chips */
466 for( chip = 0 ; chip < card->mb_ncd1190 ; chip++ ) {
467 struct cd1190 *cd = &sc->ms_cd1190[chip];
468
469 cd->cd_reg = (char *)bus_space_vaddr(sa->sa_bustag, bh) +
470 card->mb_cd1190[chip];
471
472 /* XXX don't know anything about these chips yet */
473 printf("%s: CD1190 %d addr %p (unsupported)\n",
474 device_xname(self), chip, cd->cd_reg);
475 }
476
477 /* configure the children */
478 (void)config_found(self, mtty_match, NULL, CFARGS_NONE);
479 (void)config_found(self, mbpp_match, NULL, CFARGS_NONE);
480
481 /*
482 * Establish the interrupt handlers.
483 */
484 if (sa->sa_nintr == 0)
485 return; /* No interrupts to service!? */
486
487 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_SERIAL,
488 magma_hard, sc);
489 sc->ms_sicookie = softint_establish(SOFTINT_SERIAL, magma_soft, sc);
490 if (sc->ms_sicookie == NULL) {
491 aprint_normal("\n");
492 aprint_error_dev(sc->ms_dev, "cannot establish soft int handler\n");
493 return;
494 }
495 evcnt_attach_dynamic(&sc->ms_intrcnt, EVCNT_TYPE_INTR, NULL,
496 device_xname(sc->ms_dev), "intr");
497 }
498
499 /*
500 * hard interrupt routine
501 *
502 * returns 1 if it handled it, otherwise 0
503 *
504 * runs at IPL_SERIAL
505 */
506 int
magma_hard(void * arg)507 magma_hard(void *arg)
508 {
509 struct magma_softc *sc = arg;
510 struct cd1400 *cd;
511 int chip, status = 0;
512 int serviced = 0;
513 int needsoftint = 0;
514
515 /*
516 * check status of all the CD1400 chips
517 */
518 for( chip = 0 ; chip < sc->ms_ncd1400 ; chip++ )
519 status |= cd1400_read_reg(&sc->ms_cd1400[chip], CD1400_SVRR);
520
521 if( ISSET(status, CD1400_SVRR_RXRDY) ) {
522 u_char rivr = *sc->ms_svcackr; /* enter rx service context */
523 int port = rivr >> 4;
524
525 if( rivr & (1<<3) ) { /* parallel port */
526 struct mbpp_port *mbpp;
527 int n_chars;
528
529 mbpp = &sc->ms_mbpp->ms_port[port];
530 cd = mbpp->mp_cd1400;
531
532 /* don't think we have to handle exceptions */
533 n_chars = cd1400_read_reg(cd, CD1400_RDCR);
534 while (n_chars--) {
535 if( mbpp->mp_cnt == 0 ) {
536 SET(mbpp->mp_flags, MBPPF_WAKEUP);
537 needsoftint = 1;
538 break;
539 }
540 *mbpp->mp_ptr = cd1400_read_reg(cd,CD1400_RDSR);
541 mbpp->mp_ptr++;
542 mbpp->mp_cnt--;
543 }
544 } else { /* serial port */
545 struct mtty_port *mtty;
546 u_char *ptr, n_chars, line_stat;
547
548 mtty = &sc->ms_mtty->ms_port[port];
549 cd = mtty->mp_cd1400;
550
551 if( ISSET(rivr, CD1400_RIVR_EXCEPTION) ) {
552 line_stat = cd1400_read_reg(cd, CD1400_RDSR);
553 n_chars = 1;
554 } else { /* no exception, received data OK */
555 line_stat = 0;
556 n_chars = cd1400_read_reg(cd, CD1400_RDCR);
557 }
558
559 ptr = mtty->mp_rput;
560 while( n_chars-- ) {
561 *ptr++ = line_stat;
562 *ptr++ = cd1400_read_reg(cd, CD1400_RDSR);
563 if( ptr == mtty->mp_rend ) ptr = mtty->mp_rbuf;
564 if( ptr == mtty->mp_rget ) {
565 if( ptr == mtty->mp_rbuf )
566 ptr = mtty->mp_rend;
567 ptr -= 2;
568 SET(mtty->mp_flags, MTTYF_RING_OVERFLOW);
569 break;
570 }
571 }
572 mtty->mp_rput = ptr;
573
574 needsoftint = 1;
575 }
576
577 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */
578 serviced = 1;
579 } /* if(rx_service...) */
580
581 if( ISSET(status, CD1400_SVRR_MDMCH) ) {
582 u_char mivr = *sc->ms_svcackm; /* enter mdm service context */
583 int port = mivr >> 4;
584 struct mtty_port *mtty;
585 int carrier;
586 u_char msvr;
587
588 /*
589 * Handle CD (LC2+1Sp = DSR) changes.
590 */
591 mtty = &sc->ms_mtty->ms_port[port];
592 cd = mtty->mp_cd1400;
593 msvr = cd1400_read_reg(cd, CD1400_MSVR2);
594 carrier = ISSET(msvr, cd->cd_parmode ? CD1400_MSVR2_DSR : CD1400_MSVR2_CD);
595
596 if( mtty->mp_carrier != carrier ) {
597 SET(mtty->mp_flags, MTTYF_CARRIER_CHANGED);
598 mtty->mp_carrier = carrier;
599 needsoftint = 1;
600 }
601
602 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */
603 serviced = 1;
604 } /* if(mdm_service...) */
605
606 if( ISSET(status, CD1400_SVRR_TXRDY) ) {
607 u_char tivr = *sc->ms_svcackt; /* enter tx service context */
608 int port = tivr >> 4;
609
610 if( tivr & (1<<3) ) { /* parallel port */
611 struct mbpp_port *mbpp;
612
613 mbpp = &sc->ms_mbpp->ms_port[port];
614 cd = mbpp->mp_cd1400;
615
616 if( mbpp->mp_cnt ) {
617 int count = 0;
618
619 /* fill the fifo */
620 while (mbpp->mp_cnt &&
621 count++ < CD1400_PAR_FIFO_SIZE) {
622 cd1400_write_reg(cd, CD1400_TDR,
623 *mbpp->mp_ptr);
624 mbpp->mp_ptr++;
625 mbpp->mp_cnt--;
626 }
627 } else {
628 /*
629 * fifo is empty and we got no more data
630 * to send, so shut off interrupts and
631 * signal for a wakeup, which can't be
632 * done here in case we beat mbpp_send to
633 * the tsleep call (we are running at >spltty)
634 */
635 cd1400_write_reg(cd, CD1400_SRER, 0);
636 SET(mbpp->mp_flags, MBPPF_WAKEUP);
637 needsoftint = 1;
638 }
639 } else { /* serial port */
640 struct mtty_port *mtty;
641
642 mtty = &sc->ms_mtty->ms_port[port];
643 cd = mtty->mp_cd1400;
644
645 if( !ISSET(mtty->mp_flags, MTTYF_STOP) ) {
646 int count = 0;
647
648 /* check if we should start/stop a break */
649 if( ISSET(mtty->mp_flags, MTTYF_SET_BREAK) ) {
650 cd1400_write_reg(cd, CD1400_TDR, 0);
651 cd1400_write_reg(cd, CD1400_TDR, 0x81);
652 /* should we delay too? */
653 CLR(mtty->mp_flags, MTTYF_SET_BREAK);
654 count += 2;
655 }
656
657 if( ISSET(mtty->mp_flags, MTTYF_CLR_BREAK) ) {
658 cd1400_write_reg(cd, CD1400_TDR, 0);
659 cd1400_write_reg(cd, CD1400_TDR, 0x83);
660 CLR(mtty->mp_flags, MTTYF_CLR_BREAK);
661 count += 2;
662 }
663
664 /* I don't quite fill the fifo in case the last one is a
665 * NULL which I have to double up because its the escape
666 * code for embedded transmit characters.
667 */
668 while( mtty->mp_txc > 0 && count < CD1400_TX_FIFO_SIZE - 1 ) {
669 u_char ch;
670
671 ch = *mtty->mp_txp;
672
673 mtty->mp_txc--;
674 mtty->mp_txp++;
675
676 if( ch == 0 ) {
677 cd1400_write_reg(cd, CD1400_TDR, ch);
678 count++;
679 }
680
681 cd1400_write_reg(cd, CD1400_TDR, ch);
682 count++;
683 }
684 }
685
686 /* if we ran out of work or are requested to STOP then
687 * shut off the txrdy interrupts and signal DONE to flush
688 * out the chars we have sent.
689 */
690 if( mtty->mp_txc == 0 || ISSET(mtty->mp_flags, MTTYF_STOP) ) {
691 register int srer;
692
693 srer = cd1400_read_reg(cd, CD1400_SRER);
694 CLR(srer, CD1400_SRER_TXRDY);
695 cd1400_write_reg(cd, CD1400_SRER, srer);
696 CLR(mtty->mp_flags, MTTYF_STOP);
697
698 SET(mtty->mp_flags, MTTYF_DONE);
699 needsoftint = 1;
700 }
701 }
702
703 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */
704 serviced = 1;
705 } /* if(tx_service...) */
706
707 /* XXX service CD1190 interrupts too
708 for( chip = 0 ; chip < sc->ms_ncd1190 ; chip++ ) {
709 }
710 */
711
712 if (needsoftint)
713 /* trigger the soft interrupt */
714 softint_schedule(sc->ms_sicookie);
715
716 return(serviced);
717 }
718
719 /*
720 * magma soft interrupt handler
721 *
722 * runs at IPL_SOFTSERIAL
723 */
724 void
magma_soft(void * arg)725 magma_soft(void *arg)
726 {
727 struct magma_softc *sc = arg;
728 struct mtty_softc *mtty = sc->ms_mtty;
729 struct mbpp_softc *mbpp = sc->ms_mbpp;
730 int port;
731 int s, flags;
732
733 if (mtty == NULL)
734 goto chkbpp;
735
736 /*
737 * check the tty ports to see what needs doing
738 */
739 for( port = 0 ; port < mtty->ms_nports ; port++ ) {
740 struct mtty_port *mp = &mtty->ms_port[port];
741 struct tty *tp = mp->mp_tty;
742
743 if( !ISSET(tp->t_state, TS_ISOPEN) )
744 continue;
745
746 /*
747 * handle any received data
748 */
749 while( mp->mp_rget != mp->mp_rput ) {
750 u_char stat;
751 int data;
752
753 stat = mp->mp_rget[0];
754 data = mp->mp_rget[1];
755 mp->mp_rget = ((mp->mp_rget + 2) == mp->mp_rend)
756 ? mp->mp_rbuf : (mp->mp_rget + 2);
757
758 if( stat & (CD1400_RDSR_BREAK | CD1400_RDSR_FE) )
759 data |= TTY_FE;
760 if( stat & CD1400_RDSR_PE )
761 data |= TTY_PE;
762
763 if( stat & CD1400_RDSR_OE )
764 log(LOG_WARNING, "%s%x: fifo overflow\n",
765 device_xname(mtty->ms_dev), port);
766
767 (*tp->t_linesw->l_rint)(data, tp);
768 }
769
770 s = splserial(); /* block out hard interrupt routine */
771 flags = mp->mp_flags;
772 CLR(mp->mp_flags, MTTYF_DONE | MTTYF_CARRIER_CHANGED | MTTYF_RING_OVERFLOW);
773 splx(s); /* ok */
774
775 if( ISSET(flags, MTTYF_CARRIER_CHANGED) ) {
776 dprintf(("%s%x: cd %s\n", device_xname(mtty->ms_dev),
777 port, mp->mp_carrier ? "on" : "off"));
778 (*tp->t_linesw->l_modem)(tp, mp->mp_carrier);
779 }
780
781 if( ISSET(flags, MTTYF_RING_OVERFLOW) ) {
782 log(LOG_WARNING, "%s%x: ring buffer overflow\n",
783 device_xname(mtty->ms_dev), port);
784 }
785
786 if( ISSET(flags, MTTYF_DONE) ) {
787 ndflush(&tp->t_outq, mp->mp_txp - tp->t_outq.c_cf);
788 CLR(tp->t_state, TS_BUSY);
789 (*tp->t_linesw->l_start)(tp); /* might be some more */
790 }
791 } /* for(each mtty...) */
792
793
794 chkbpp:
795 /*
796 * Check the bpp ports (if any) to see what needs doing
797 */
798 if (mbpp == NULL)
799 return;
800
801 for( port = 0 ; port < mbpp->ms_nports ; port++ ) {
802 struct mbpp_port *mp = &mbpp->ms_port[port];
803
804 if( !ISSET(mp->mp_flags, MBPPF_OPEN) )
805 continue;
806
807 s = splserial();
808 flags = mp->mp_flags;
809 CLR(mp->mp_flags, MBPPF_WAKEUP);
810 splx(s);
811
812 if( ISSET(flags, MBPPF_WAKEUP) ) {
813 wakeup(mp);
814 }
815
816 } /* for(each mbpp...) */
817 }
818
819 /************************************************************************
820 *
821 * MTTY Routines
822 *
823 * mtty_match match one mtty device
824 * mtty_attach attach mtty devices
825 * mttyopen open mtty device
826 * mttyclose close mtty device
827 * mttyread read from mtty
828 * mttywrite write to mtty
829 * mttyioctl do ioctl on mtty
830 * mttytty return tty pointer for mtty
831 * mttystop stop mtty device
832 * mtty_start start mtty device
833 * mtty_param set mtty parameters
834 * mtty_modem_control set modem control lines
835 */
836
837 int
mtty_match(device_t parent,cfdata_t cf,void * args)838 mtty_match(device_t parent, cfdata_t cf, void *args)
839 {
840 struct magma_softc *sc = device_private(parent);
841
842 return( args == mtty_match && sc->ms_board->mb_nser && sc->ms_mtty == NULL );
843 }
844
845 void
mtty_attach(device_t parent,device_t self,void * args)846 mtty_attach(device_t parent, device_t self, void *args)
847 {
848 struct magma_softc *sc = device_private(parent);
849 struct mtty_softc *ms = device_private(self);
850 int port, chip, chan;
851
852 sc->ms_dev = self;
853 sc->ms_mtty = ms;
854 dprintf((" addr %p", ms));
855
856 for( port = 0, chip = 0, chan = 0 ; port < sc->ms_board->mb_nser ; port++ ) {
857 struct mtty_port *mp = &ms->ms_port[port];
858 struct tty *tp;
859
860 mp->mp_cd1400 = &sc->ms_cd1400[chip];
861 if (mp->mp_cd1400->cd_parmode && chan == 0)
862 chan = 1; /* skip channel 0 if parmode */
863 mp->mp_channel = chan;
864
865 tp = tty_alloc();
866 if (tp == NULL) {
867 break;
868 }
869 tty_attach(tp);
870 tp->t_oproc = mtty_start;
871 tp->t_param = mtty_param;
872
873 mp->mp_tty = tp;
874
875 mp->mp_rbuf = malloc(MTTY_RBUF_SIZE, M_DEVBUF, M_WAITOK);
876 mp->mp_rend = mp->mp_rbuf + MTTY_RBUF_SIZE;
877
878 chan = (chan + 1) % CD1400_NO_OF_CHANNELS;
879 if (chan == 0)
880 chip++;
881 }
882
883 ms->ms_nports = port;
884 printf(": %d tty%s\n", port, port == 1 ? "" : "s");
885 }
886
887 /*
888 * open routine. returns zero if successful, else error code
889 */
890 int
mttyopen(dev_t dev,int flags,int mode,struct lwp * l)891 mttyopen(dev_t dev, int flags, int mode, struct lwp *l)
892 {
893 int card = MAGMA_CARD(dev);
894 int port = MAGMA_PORT(dev);
895 struct mtty_softc *ms;
896 struct mtty_port *mp;
897 struct tty *tp;
898 struct cd1400 *cd;
899 int error, s;
900
901 if ((ms = device_lookup_private(&mtty_cd, card)) == NULL
902 || port >= ms->ms_nports )
903 return(ENXIO); /* device not configured */
904
905 mp = &ms->ms_port[port];
906 tp = mp->mp_tty;
907 tp->t_dev = dev;
908
909 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp))
910 return (EBUSY);
911
912 s = spltty();
913
914 if( !ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
915
916 /* set defaults */
917 ttychars(tp);
918 tp->t_iflag = TTYDEF_IFLAG;
919 tp->t_oflag = TTYDEF_OFLAG;
920 tp->t_cflag = TTYDEF_CFLAG;
921 if( ISSET(mp->mp_openflags, TIOCFLAG_CLOCAL) )
922 SET(tp->t_cflag, CLOCAL);
923 if( ISSET(mp->mp_openflags, TIOCFLAG_CRTSCTS) )
924 SET(tp->t_cflag, CRTSCTS);
925 if( ISSET(mp->mp_openflags, TIOCFLAG_MDMBUF) )
926 SET(tp->t_cflag, MDMBUF);
927 tp->t_lflag = TTYDEF_LFLAG;
928 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
929
930 /* init ring buffer */
931 mp->mp_rput = mp->mp_rget = mp->mp_rbuf;
932
933 /* reset CD1400 channel */
934 cd = mp->mp_cd1400;
935 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel);
936 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET);
937
938 /* encode the port number in top half of LIVR */
939 cd1400_write_reg(cd, CD1400_LIVR, port << 4 );
940
941 /* sets parameters and raises DTR */
942 (void)mtty_param(tp, &tp->t_termios);
943
944 /* set tty watermarks */
945 ttsetwater(tp);
946
947 /* enable service requests */
948 cd1400_write_reg(cd, CD1400_SRER,
949 CD1400_SRER_RXDATA | CD1400_SRER_MDMCH);
950
951 /* tell the tty about the carrier status */
952 if( ISSET(mp->mp_openflags, TIOCFLAG_SOFTCAR) ||
953 mp->mp_carrier )
954 SET(tp->t_state, TS_CARR_ON);
955 else
956 CLR(tp->t_state, TS_CARR_ON);
957 }
958 splx(s);
959
960 error = ttyopen(tp, MTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK));
961 if (error != 0)
962 goto bad;
963
964 error = (*tp->t_linesw->l_open)(dev, tp);
965 if (error != 0)
966 goto bad;
967
968 bad:
969 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
970 /*
971 * We failed to open the device, and nobody else had it opened.
972 * Clean up the state as appropriate.
973 */
974 /* XXX - do that here */
975 }
976
977 return (error);
978 }
979
980 /*
981 * close routine. returns zero if successful, else error code
982 */
983 int
mttyclose(dev_t dev,int flag,int mode,struct lwp * l)984 mttyclose(dev_t dev, int flag, int mode, struct lwp *l)
985 {
986 struct mtty_softc *ms = device_lookup_private(&mtty_cd,
987 MAGMA_CARD(dev));
988 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
989 struct tty *tp = mp->mp_tty;
990 int s;
991
992 (*tp->t_linesw->l_close)(tp, flag);
993 ttyclose(tp);
994
995 s = spltty();
996
997 /* if HUPCL is set, and the tty is no longer open
998 * shut down the port
999 */
1000 if( ISSET(tp->t_cflag, HUPCL) || !ISSET(tp->t_state, TS_ISOPEN) ) {
1001 /* XXX wait until FIFO is empty before turning off the channel
1002 struct cd1400 *cd = mp->mp_cd1400;
1003 */
1004
1005 /* drop DTR and RTS */
1006 (void)mtty_modem_control(mp, 0, DMSET);
1007
1008 /* turn off the channel
1009 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel);
1010 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET);
1011 */
1012 }
1013
1014 splx(s);
1015
1016 return(0);
1017 }
1018
1019 /*
1020 * Read routine
1021 */
1022 int
mttyread(dev_t dev,struct uio * uio,int flags)1023 mttyread(dev_t dev, struct uio *uio, int flags)
1024 {
1025 struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1026 MAGMA_CARD(dev));
1027 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
1028 struct tty *tp = mp->mp_tty;
1029
1030 return( (*tp->t_linesw->l_read)(tp, uio, flags) );
1031 }
1032
1033 /*
1034 * Write routine
1035 */
1036 int
mttywrite(dev_t dev,struct uio * uio,int flags)1037 mttywrite(dev_t dev, struct uio *uio, int flags)
1038 {
1039 struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1040 MAGMA_CARD(dev));
1041 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
1042 struct tty *tp = mp->mp_tty;
1043
1044 return( (*tp->t_linesw->l_write)(tp, uio, flags) );
1045 }
1046
1047 /*
1048 * Poll routine
1049 */
1050 int
mttypoll(dev_t dev,int events,struct lwp * l)1051 mttypoll(dev_t dev, int events, struct lwp *l)
1052 {
1053 struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1054 MAGMA_CARD(dev));
1055 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
1056 struct tty *tp = mp->mp_tty;
1057
1058 return ((*tp->t_linesw->l_poll)(tp, events, l));
1059 }
1060
1061 /*
1062 * return tty pointer
1063 */
1064 struct tty *
mttytty(dev_t dev)1065 mttytty(dev_t dev)
1066 {
1067 struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1068 MAGMA_CARD(dev));
1069 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
1070
1071 return(mp->mp_tty);
1072 }
1073
1074 /*
1075 * ioctl routine
1076 */
1077 int
mttyioctl(dev_t dev,u_long cmd,void * data,int flags,struct lwp * l)1078 mttyioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l)
1079 {
1080 struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1081 MAGMA_CARD(dev));
1082 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
1083 struct tty *tp = mp->mp_tty;
1084 int error;
1085
1086 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flags, l);
1087 if( error != EPASSTHROUGH ) return(error);
1088
1089 error = ttioctl(tp, cmd, data, flags, l);
1090 if( error != EPASSTHROUGH ) return(error);
1091
1092 error = 0;
1093
1094 switch(cmd) {
1095 case TIOCSBRK: /* set break */
1096 SET(mp->mp_flags, MTTYF_SET_BREAK);
1097 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel);
1098 break;
1099
1100 case TIOCCBRK: /* clear break */
1101 SET(mp->mp_flags, MTTYF_CLR_BREAK);
1102 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel);
1103 break;
1104
1105 case TIOCSDTR: /* set DTR */
1106 mtty_modem_control(mp, TIOCM_DTR, DMBIS);
1107 break;
1108
1109 case TIOCCDTR: /* clear DTR */
1110 mtty_modem_control(mp, TIOCM_DTR, DMBIC);
1111 break;
1112
1113 case TIOCMSET: /* set modem lines */
1114 mtty_modem_control(mp, *((int *)data), DMSET);
1115 break;
1116
1117 case TIOCMBIS: /* bit set modem lines */
1118 mtty_modem_control(mp, *((int *)data), DMBIS);
1119 break;
1120
1121 case TIOCMBIC: /* bit clear modem lines */
1122 mtty_modem_control(mp, *((int *)data), DMBIC);
1123 break;
1124
1125 case TIOCMGET: /* get modem lines */
1126 *((int *)data) = mtty_modem_control(mp, 0, DMGET);
1127 break;
1128
1129 case TIOCGFLAGS:
1130 *((int *)data) = mp->mp_openflags;
1131 break;
1132
1133 case TIOCSFLAGS:
1134 if (kauth_authorize_device_tty(l->l_cred,
1135 KAUTH_DEVICE_TTY_PRIVSET, tp))
1136 error = EPERM;
1137 else
1138 mp->mp_openflags = *((int *)data) &
1139 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL |
1140 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF);
1141 break;
1142
1143 default:
1144 error = EPASSTHROUGH;
1145 }
1146
1147 return(error);
1148 }
1149
1150 /*
1151 * Stop output, e.g., for ^S or output flush.
1152 */
1153 void
mttystop(struct tty * tp,int flags)1154 mttystop(struct tty *tp, int flags)
1155 {
1156 struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1157 MAGMA_CARD(tp->t_dev));
1158 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)];
1159 int s;
1160
1161 s = spltty();
1162
1163 if( ISSET(tp->t_state, TS_BUSY) ) {
1164 if( !ISSET(tp->t_state, TS_TTSTOP) )
1165 SET(tp->t_state, TS_FLUSH);
1166
1167 /*
1168 * the transmit interrupt routine will disable transmit when it
1169 * notices that MTTYF_STOP has been set.
1170 */
1171 SET(mp->mp_flags, MTTYF_STOP);
1172 }
1173
1174 splx(s);
1175 }
1176
1177 /*
1178 * Start output, after a stop.
1179 */
1180 void
mtty_start(struct tty * tp)1181 mtty_start(struct tty *tp)
1182 {
1183 struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1184 MAGMA_CARD(tp->t_dev));
1185 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)];
1186 int s;
1187
1188 s = spltty();
1189
1190 /* we only need to do something if we are not already busy
1191 * or delaying or stopped
1192 */
1193 if( !ISSET(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) {
1194 if (ttypull(tp)) {
1195 mp->mp_txc = ndqb(&tp->t_outq, 0);
1196 mp->mp_txp = tp->t_outq.c_cf;
1197 SET(tp->t_state, TS_BUSY);
1198 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel);
1199 }
1200 }
1201
1202 splx(s);
1203 }
1204
1205 /*
1206 * set/get modem line status
1207 *
1208 * bits can be: TIOCM_DTR, TIOCM_RTS, TIOCM_CTS, TIOCM_CD, TIOCM_RI, TIOCM_DSR
1209 *
1210 * note that DTR and RTS lines are exchanged, and that DSR is
1211 * not available on the LC2+1Sp card (used as CD)
1212 *
1213 * only let them fiddle with RTS if CRTSCTS is not enabled
1214 */
1215 int
mtty_modem_control(struct mtty_port * mp,int bits,int howto)1216 mtty_modem_control(struct mtty_port *mp, int bits, int howto)
1217 {
1218 struct cd1400 *cd = mp->mp_cd1400;
1219 struct tty *tp = mp->mp_tty;
1220 int s, msvr;
1221
1222 s = spltty();
1223
1224 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel);
1225
1226 switch(howto) {
1227 case DMGET: /* get bits */
1228 bits = 0;
1229
1230 bits |= TIOCM_LE;
1231
1232 msvr = cd1400_read_reg(cd, CD1400_MSVR1);
1233 if( msvr & CD1400_MSVR1_RTS ) bits |= TIOCM_DTR;
1234
1235 msvr = cd1400_read_reg(cd, CD1400_MSVR2);
1236 if( msvr & CD1400_MSVR2_DTR ) bits |= TIOCM_RTS;
1237 if( msvr & CD1400_MSVR2_CTS ) bits |= TIOCM_CTS;
1238 if( msvr & CD1400_MSVR2_RI ) bits |= TIOCM_RI;
1239 if( msvr & CD1400_MSVR2_DSR ) bits |= (cd->cd_parmode ? TIOCM_CD : TIOCM_DSR);
1240 if( msvr & CD1400_MSVR2_CD ) bits |= (cd->cd_parmode ? 0 : TIOCM_CD);
1241
1242 break;
1243
1244 case DMSET: /* reset bits */
1245 if( !ISSET(tp->t_cflag, CRTSCTS) )
1246 cd1400_write_reg(cd, CD1400_MSVR2, ((bits & TIOCM_RTS) ? CD1400_MSVR2_DTR : 0));
1247
1248 cd1400_write_reg(cd, CD1400_MSVR1, ((bits & TIOCM_DTR) ? CD1400_MSVR1_RTS : 0));
1249
1250 break;
1251
1252 case DMBIS: /* set bits */
1253 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) )
1254 cd1400_write_reg(cd, CD1400_MSVR2, CD1400_MSVR2_DTR);
1255
1256 if( bits & TIOCM_DTR )
1257 cd1400_write_reg(cd, CD1400_MSVR1, CD1400_MSVR1_RTS);
1258
1259 break;
1260
1261 case DMBIC: /* clear bits */
1262 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) )
1263 cd1400_write_reg(cd, CD1400_MSVR2, 0);
1264
1265 if( bits & TIOCM_DTR )
1266 cd1400_write_reg(cd, CD1400_MSVR1, 0);
1267
1268 break;
1269 }
1270
1271 splx(s);
1272 return(bits);
1273 }
1274
1275 /*
1276 * Set tty parameters, returns error or 0 on success
1277 */
1278 int
mtty_param(struct tty * tp,struct termios * t)1279 mtty_param(struct tty *tp, struct termios *t)
1280 {
1281 struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1282 MAGMA_CARD(tp->t_dev));
1283 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)];
1284 struct cd1400 *cd = mp->mp_cd1400;
1285 int rbpr, tbpr, rcor, tcor;
1286 u_char mcor1 = 0, mcor2 = 0;
1287 int s, opt;
1288
1289 if( t->c_ospeed && cd1400_compute_baud(t->c_ospeed, cd->cd_clock, &tcor, &tbpr) )
1290 return(EINVAL);
1291
1292 if( t->c_ispeed && cd1400_compute_baud(t->c_ispeed, cd->cd_clock, &rcor, &rbpr) )
1293 return(EINVAL);
1294
1295 s = spltty();
1296
1297 /* hang up the line if ospeed is zero, else raise DTR */
1298 (void)mtty_modem_control(mp, TIOCM_DTR, (t->c_ospeed == 0 ? DMBIC : DMBIS));
1299
1300 /* select channel, done in mtty_modem_control() */
1301 /* cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); */
1302
1303 /* set transmit speed */
1304 if( t->c_ospeed ) {
1305 cd1400_write_reg(cd, CD1400_TCOR, tcor);
1306 cd1400_write_reg(cd, CD1400_TBPR, tbpr);
1307 }
1308
1309 /* set receive speed */
1310 if( t->c_ispeed ) {
1311 cd1400_write_reg(cd, CD1400_RCOR, rcor);
1312 cd1400_write_reg(cd, CD1400_RBPR, rbpr);
1313 }
1314
1315 /* enable transmitting and receiving on this channel */
1316 opt = CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN | CD1400_CCR_RCVEN;
1317 cd1400_write_ccr(cd, opt);
1318
1319 /* set parity, data and stop bits */
1320 opt = 0;
1321 if( ISSET(t->c_cflag, PARENB) )
1322 opt |= (ISSET(t->c_cflag, PARODD) ? CD1400_COR1_PARODD : CD1400_COR1_PARNORMAL);
1323
1324 if( !ISSET(t->c_iflag, INPCK) )
1325 opt |= CD1400_COR1_NOINPCK; /* no parity checking */
1326
1327 if( ISSET(t->c_cflag, CSTOPB) )
1328 opt |= CD1400_COR1_STOP2;
1329
1330 switch( t->c_cflag & CSIZE ) {
1331 case CS5:
1332 opt |= CD1400_COR1_CS5;
1333 break;
1334
1335 case CS6:
1336 opt |= CD1400_COR1_CS6;
1337 break;
1338
1339 case CS7:
1340 opt |= CD1400_COR1_CS7;
1341 break;
1342
1343 default:
1344 opt |= CD1400_COR1_CS8;
1345 break;
1346 }
1347
1348 cd1400_write_reg(cd, CD1400_COR1, opt);
1349
1350 /*
1351 * enable Embedded Transmit Commands (for breaks)
1352 * use the CD1400 automatic CTS flow control if CRTSCTS is set
1353 */
1354 opt = CD1400_COR2_ETC;
1355 if( ISSET(t->c_cflag, CRTSCTS) ) opt |= CD1400_COR2_CCTS_OFLOW;
1356 cd1400_write_reg(cd, CD1400_COR2, opt);
1357
1358 cd1400_write_reg(cd, CD1400_COR3, MTTY_RX_FIFO_THRESHOLD);
1359
1360 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR1 | CD1400_CCR_COR2 | CD1400_CCR_COR3);
1361
1362 cd1400_write_reg(cd, CD1400_COR4, CD1400_COR4_PFO_EXCEPTION);
1363 cd1400_write_reg(cd, CD1400_COR5, 0);
1364
1365 /*
1366 * if automatic RTS handshaking enabled, set DTR threshold
1367 * (RTS and DTR lines are switched, CD1400 thinks its DTR)
1368 */
1369 if( ISSET(t->c_cflag, CRTSCTS) )
1370 mcor1 = MTTY_RX_DTR_THRESHOLD;
1371
1372 /* set up `carrier detect' interrupts */
1373 if( cd->cd_parmode ) {
1374 SET(mcor1, CD1400_MCOR1_DSRzd);
1375 SET(mcor2, CD1400_MCOR2_DSRod);
1376 } else {
1377 SET(mcor1, CD1400_MCOR1_CDzd);
1378 SET(mcor2, CD1400_MCOR2_CDod);
1379 }
1380
1381 cd1400_write_reg(cd, CD1400_MCOR1, mcor1);
1382 cd1400_write_reg(cd, CD1400_MCOR2, mcor2);
1383
1384 /* receive timeout 2ms */
1385 cd1400_write_reg(cd, CD1400_RTPR, 2);
1386
1387 splx(s);
1388 return(0);
1389 }
1390
1391 /************************************************************************
1392 *
1393 * MBPP Routines
1394 *
1395 * mbpp_match match one mbpp device
1396 * mbpp_attach attach mbpp devices
1397 * mbppopen open mbpp device
1398 * mbppclose close mbpp device
1399 * mbppioctl do ioctl on mbpp
1400 * mbpp_rw general rw routine
1401 * mbpp_timeout rw timeout
1402 * mbpp_start rw start after delay
1403 * mbpp_send send data
1404 * mbpp_recv recv data
1405 */
1406
1407 int
mbpp_match(device_t parent,cfdata_t cf,void * args)1408 mbpp_match(device_t parent, cfdata_t cf, void *args)
1409 {
1410 struct magma_softc *sc = device_private(parent);
1411
1412 return( args == mbpp_match && sc->ms_board->mb_npar && sc->ms_mbpp == NULL );
1413 }
1414
1415 void
mbpp_attach(device_t parent,device_t dev,void * args)1416 mbpp_attach(device_t parent, device_t dev, void *args)
1417 {
1418 struct magma_softc *sc = device_private(parent);
1419 struct mbpp_softc *ms = device_private(dev);
1420 struct mbpp_port *mp;
1421 int port;
1422
1423 sc->ms_mbpp = ms;
1424 dprintf((" addr %p", ms));
1425
1426 for( port = 0 ; port < sc->ms_board->mb_npar ; port++ ) {
1427 mp = &ms->ms_port[port];
1428
1429 callout_init(&mp->mp_timeout_ch, 0);
1430 callout_init(&mp->mp_start_ch, 0);
1431
1432 if( sc->ms_ncd1190 )
1433 mp->mp_cd1190 = &sc->ms_cd1190[port];
1434 else
1435 mp->mp_cd1400 = &sc->ms_cd1400[0];
1436 }
1437
1438 ms->ms_nports = port;
1439 printf(": %d port%s\n", port, port == 1 ? "" : "s");
1440 }
1441
1442 /*
1443 * open routine. returns zero if successful, else error code
1444 */
1445 int
mbppopen(dev_t dev,int flags,int mode,struct lwp * l)1446 mbppopen(dev_t dev, int flags, int mode, struct lwp *l)
1447 {
1448 int card = MAGMA_CARD(dev);
1449 int port = MAGMA_PORT(dev);
1450 struct mbpp_softc *ms;
1451 struct mbpp_port *mp;
1452 int s;
1453
1454 if ((ms = device_lookup_private(&mbpp_cd, card)) == NULL
1455 || port >= ms->ms_nports )
1456 return(ENXIO);
1457
1458 mp = &ms->ms_port[port];
1459
1460 s = spltty();
1461 if( ISSET(mp->mp_flags, MBPPF_OPEN) ) {
1462 splx(s);
1463 return(EBUSY);
1464 }
1465 SET(mp->mp_flags, MBPPF_OPEN);
1466 splx(s);
1467
1468 /* set defaults */
1469 mp->mp_burst = MBPP_BURST;
1470 mp->mp_timeout = mbpp_mstohz(MBPP_TIMEOUT);
1471 mp->mp_delay = mbpp_mstohz(MBPP_DELAY);
1472
1473 /* init chips */
1474 if( mp->mp_cd1400 ) { /* CD1400 */
1475 struct cd1400 *cd = mp->mp_cd1400;
1476
1477 /* set up CD1400 channel */
1478 s = spltty();
1479 cd1400_write_reg(cd, CD1400_CAR, 0);
1480 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET);
1481 cd1400_write_reg(cd, CD1400_LIVR, (1<<3));
1482 splx(s);
1483 } else { /* CD1190 */
1484 mp->mp_flags = 0;
1485 return (ENXIO);
1486 }
1487
1488 return (0);
1489 }
1490
1491 /*
1492 * close routine. returns zero if successful, else error code
1493 */
1494 int
mbppclose(dev_t dev,int flag,int mode,struct lwp * l)1495 mbppclose(dev_t dev, int flag, int mode, struct lwp *l)
1496 {
1497 struct mbpp_softc *ms = device_lookup_private(&mbpp_cd,
1498 MAGMA_CARD(dev));
1499 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
1500
1501 mp->mp_flags = 0;
1502 return(0);
1503 }
1504
1505 /*
1506 * ioctl routine
1507 */
1508 int
mbppioctl(dev_t dev,u_long cmd,void * data,int flags,struct lwp * l)1509 mbppioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l)
1510 {
1511 struct mbpp_softc *ms = device_lookup_private(&mbpp_cd,
1512 MAGMA_CARD(dev));
1513 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
1514 struct mbpp_param *bp;
1515 int error = 0;
1516 int s;
1517
1518 switch(cmd) {
1519 case MBPPIOCSPARAM:
1520 bp = (struct mbpp_param *)data;
1521 if( bp->bp_burst < MBPP_BURST_MIN || bp->bp_burst > MBPP_BURST_MAX ||
1522 bp->bp_delay < MBPP_DELAY_MIN || bp->bp_delay > MBPP_DELAY_MIN ) {
1523 error = EINVAL;
1524 } else {
1525 mp->mp_burst = bp->bp_burst;
1526 mp->mp_timeout = mbpp_mstohz(bp->bp_timeout);
1527 mp->mp_delay = mbpp_mstohz(bp->bp_delay);
1528 }
1529 break;
1530 case MBPPIOCGPARAM:
1531 bp = (struct mbpp_param *)data;
1532 bp->bp_burst = mp->mp_burst;
1533 bp->bp_timeout = mbpp_hztoms(mp->mp_timeout);
1534 bp->bp_delay = mbpp_hztoms(mp->mp_delay);
1535 break;
1536 case MBPPIOCGSTAT:
1537 /* XXX make this more generic */
1538 s = spltty();
1539 cd1400_write_reg(mp->mp_cd1400, CD1400_CAR, 0);
1540 *(int *)data = cd1400_read_reg(mp->mp_cd1400, CD1400_PSVR);
1541 splx(s);
1542 break;
1543 default:
1544 error = ENOTTY;
1545 }
1546
1547 return(error);
1548 }
1549
1550 int
mbpp_rw(dev_t dev,struct uio * uio,int flag)1551 mbpp_rw(dev_t dev, struct uio *uio, int flag)
1552 {
1553 int card = MAGMA_CARD(dev);
1554 int port = MAGMA_PORT(dev);
1555 struct mbpp_softc *ms = device_lookup_private(&mbpp_cd, card);
1556 struct mbpp_port *mp = &ms->ms_port[port];
1557 char *buffer, *ptr;
1558 int buflen, cnt, len;
1559 int s, error = 0;
1560 int gotdata = 0;
1561
1562 if( uio->uio_resid == 0 )
1563 return(0);
1564
1565 buflen = uimin(uio->uio_resid, mp->mp_burst);
1566 buffer = malloc(buflen, M_DEVBUF, M_WAITOK);
1567 if( buffer == NULL )
1568 return(ENOMEM);
1569
1570 SET(mp->mp_flags, MBPPF_UIO);
1571
1572 /*
1573 * start timeout, if needed
1574 */
1575 if( mp->mp_timeout > 0 ) {
1576 SET(mp->mp_flags, MBPPF_TIMEOUT);
1577 callout_reset(&mp->mp_timeout_ch, mp->mp_timeout,
1578 mbpp_timeout, mp);
1579 }
1580
1581 len = cnt = 0;
1582 while( uio->uio_resid > 0 ) {
1583 len = uimin(buflen, uio->uio_resid);
1584 ptr = buffer;
1585
1586 if( uio->uio_rw == UIO_WRITE ) {
1587 error = uiomove(ptr, len, uio);
1588 if( error ) break;
1589 }
1590 again: /* goto bad */
1591 /* timed out? */
1592 if( !ISSET(mp->mp_flags, MBPPF_UIO) )
1593 break;
1594
1595 /*
1596 * perform the operation
1597 */
1598 if( uio->uio_rw == UIO_WRITE ) {
1599 cnt = mbpp_send(mp, ptr, len);
1600 } else {
1601 cnt = mbpp_recv(mp, ptr, len);
1602 }
1603
1604 if( uio->uio_rw == UIO_READ ) {
1605 if( cnt ) {
1606 error = uiomove(ptr, cnt, uio);
1607 if( error ) break;
1608 gotdata++;
1609 }
1610 else if( gotdata ) /* consider us done */
1611 break;
1612 }
1613
1614 /* timed out? */
1615 if( !ISSET(mp->mp_flags, MBPPF_UIO) )
1616 break;
1617
1618 /*
1619 * poll delay?
1620 */
1621 if( mp->mp_delay > 0 ) {
1622 s = splsoftclock();
1623 SET(mp->mp_flags, MBPPF_DELAY);
1624 callout_reset(&mp->mp_start_ch, mp->mp_delay,
1625 mbpp_start, mp);
1626 error = tsleep(mp, PCATCH | PZERO, "mbppdelay", 0);
1627 splx(s);
1628 if( error ) break;
1629 }
1630
1631 /*
1632 * don't call uiomove again until we used all the data we grabbed
1633 */
1634 if( uio->uio_rw == UIO_WRITE && cnt != len ) {
1635 ptr += cnt;
1636 len -= cnt;
1637 cnt = 0;
1638 goto again;
1639 }
1640 }
1641
1642 /*
1643 * clear timeouts
1644 */
1645 s = splsoftclock();
1646 if( ISSET(mp->mp_flags, MBPPF_TIMEOUT) ) {
1647 callout_stop(&mp->mp_timeout_ch);
1648 CLR(mp->mp_flags, MBPPF_TIMEOUT);
1649 }
1650 if( ISSET(mp->mp_flags, MBPPF_DELAY) ) {
1651 callout_stop(&mp->mp_start_ch);
1652 CLR(mp->mp_flags, MBPPF_DELAY);
1653 }
1654 splx(s);
1655
1656 /*
1657 * adjust for those chars that we uiomoved but never actually wrote
1658 */
1659 if( uio->uio_rw == UIO_WRITE && cnt != len ) {
1660 uio->uio_resid += (len - cnt);
1661 }
1662
1663 free(buffer, M_DEVBUF);
1664 return(error);
1665 }
1666
1667 void
mbpp_timeout(void * arg)1668 mbpp_timeout(void *arg)
1669 {
1670 struct mbpp_port *mp = arg;
1671
1672 CLR(mp->mp_flags, MBPPF_UIO | MBPPF_TIMEOUT);
1673 wakeup(mp);
1674 }
1675
1676 void
mbpp_start(void * arg)1677 mbpp_start(void *arg)
1678 {
1679 struct mbpp_port *mp = arg;
1680
1681 CLR(mp->mp_flags, MBPPF_DELAY);
1682 wakeup(mp);
1683 }
1684
1685 int
mbpp_send(struct mbpp_port * mp,void * ptr,int len)1686 mbpp_send(struct mbpp_port *mp, void *ptr, int len)
1687 {
1688 int s;
1689 struct cd1400 *cd = mp->mp_cd1400;
1690
1691 /* set up io information */
1692 mp->mp_ptr = ptr;
1693 mp->mp_cnt = len;
1694
1695 /* start transmitting */
1696 s = spltty();
1697 if( cd ) {
1698 cd1400_write_reg(cd, CD1400_CAR, 0);
1699
1700 /* output strobe width ~1microsecond */
1701 cd1400_write_reg(cd, CD1400_TBPR, 10);
1702
1703 /* enable channel */
1704 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN);
1705 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_TXRDY);
1706 }
1707
1708 /* ZZzzz... */
1709 tsleep(mp, PCATCH | PZERO, "mbpp_send", 0);
1710
1711 /* stop transmitting */
1712 if( cd ) {
1713 cd1400_write_reg(cd, CD1400_CAR, 0);
1714
1715 /* disable transmitter */
1716 cd1400_write_reg(cd, CD1400_SRER, 0);
1717 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTDIS);
1718
1719 /* flush fifo */
1720 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FTF);
1721 }
1722 splx(s);
1723
1724 /* return number of chars sent */
1725 return(len - mp->mp_cnt);
1726 }
1727
1728 int
mbpp_recv(struct mbpp_port * mp,void * ptr,int len)1729 mbpp_recv(struct mbpp_port *mp, void *ptr, int len)
1730 {
1731 int s;
1732 struct cd1400 *cd = mp->mp_cd1400;
1733
1734 /* set up io information */
1735 mp->mp_ptr = ptr;
1736 mp->mp_cnt = len;
1737
1738 /* start receiving */
1739 s = spltty();
1740 if( cd ) {
1741 int rcor, rbpr;
1742
1743 cd1400_write_reg(cd, CD1400_CAR, 0);
1744
1745 /* input strobe at 100kbaud (10microseconds) */
1746 if (cd1400_compute_baud(100000, cd->cd_clock, &rcor, &rbpr)) {
1747 splx(s);
1748 return 0;
1749 }
1750 cd1400_write_reg(cd, CD1400_RCOR, rcor);
1751 cd1400_write_reg(cd, CD1400_RBPR, rbpr);
1752
1753 /* rx threshold */
1754 cd1400_write_reg(cd, CD1400_COR3, MBPP_RX_FIFO_THRESHOLD);
1755 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR3);
1756
1757 /* enable channel */
1758 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVEN);
1759 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_RXDATA);
1760 }
1761
1762 /* ZZzzz... */
1763 tsleep(mp, PCATCH | PZERO, "mbpp_recv", 0);
1764
1765 /* stop receiving */
1766 if( cd ) {
1767 cd1400_write_reg(cd, CD1400_CAR, 0);
1768
1769 /* disable receiving */
1770 cd1400_write_reg(cd, CD1400_SRER, 0);
1771 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVDIS);
1772 }
1773 splx(s);
1774
1775 /* return number of chars received */
1776 return(len - mp->mp_cnt);
1777 }
1778
1779 int
mbpp_hztoms(int h)1780 mbpp_hztoms(int h)
1781 {
1782 int m = h;
1783
1784 if( m > 0 )
1785 m = m * 1000 / hz;
1786 return(m);
1787 }
1788
1789 int
mbpp_mstohz(int m)1790 mbpp_mstohz(int m)
1791 {
1792 int h = m;
1793
1794 if( h > 0 ) {
1795 h = h * hz / 1000;
1796 if( h == 0 )
1797 h = 1000 / hz;
1798 }
1799 return(h);
1800 }
1801
1802 #endif /* NMAGMA */
1803