1 /*
2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Cisco Systems. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36 #include <linux/string.h>
37 #include <linux/slab.h>
38 #include <linux/sched.h>
39
40 #include <asm/io.h>
41
42 #include <rdma/ib_verbs.h>
43 #include <rdma/ib_cache.h>
44 #include <rdma/ib_pack.h>
45
46 #include "mthca_dev.h"
47 #include "mthca_cmd.h"
48 #include "mthca_memfree.h"
49 #include "mthca_wqe.h"
50
51 enum {
52 MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
53 MTHCA_ACK_REQ_FREQ = 10,
54 MTHCA_FLIGHT_LIMIT = 9,
55 MTHCA_UD_HEADER_SIZE = 72, /* largest UD header possible */
56 MTHCA_INLINE_HEADER_SIZE = 4, /* data segment overhead for inline */
57 MTHCA_INLINE_CHUNK_SIZE = 16 /* inline data segment chunk */
58 };
59
60 enum {
61 MTHCA_QP_STATE_RST = 0,
62 MTHCA_QP_STATE_INIT = 1,
63 MTHCA_QP_STATE_RTR = 2,
64 MTHCA_QP_STATE_RTS = 3,
65 MTHCA_QP_STATE_SQE = 4,
66 MTHCA_QP_STATE_SQD = 5,
67 MTHCA_QP_STATE_ERR = 6,
68 MTHCA_QP_STATE_DRAINING = 7
69 };
70
71 enum {
72 MTHCA_QP_ST_RC = 0x0,
73 MTHCA_QP_ST_UC = 0x1,
74 MTHCA_QP_ST_RD = 0x2,
75 MTHCA_QP_ST_UD = 0x3,
76 MTHCA_QP_ST_MLX = 0x7
77 };
78
79 enum {
80 MTHCA_QP_PM_MIGRATED = 0x3,
81 MTHCA_QP_PM_ARMED = 0x0,
82 MTHCA_QP_PM_REARM = 0x1
83 };
84
85 enum {
86 /* qp_context flags */
87 MTHCA_QP_BIT_DE = 1 << 8,
88 /* params1 */
89 MTHCA_QP_BIT_SRE = 1 << 15,
90 MTHCA_QP_BIT_SWE = 1 << 14,
91 MTHCA_QP_BIT_SAE = 1 << 13,
92 MTHCA_QP_BIT_SIC = 1 << 4,
93 MTHCA_QP_BIT_SSC = 1 << 3,
94 /* params2 */
95 MTHCA_QP_BIT_RRE = 1 << 15,
96 MTHCA_QP_BIT_RWE = 1 << 14,
97 MTHCA_QP_BIT_RAE = 1 << 13,
98 MTHCA_QP_BIT_RIC = 1 << 4,
99 MTHCA_QP_BIT_RSC = 1 << 3
100 };
101
102 enum {
103 MTHCA_SEND_DOORBELL_FENCE = 1 << 5
104 };
105
106 struct mthca_qp_path {
107 __be32 port_pkey;
108 u8 rnr_retry;
109 u8 g_mylmc;
110 __be16 rlid;
111 u8 ackto;
112 u8 mgid_index;
113 u8 static_rate;
114 u8 hop_limit;
115 __be32 sl_tclass_flowlabel;
116 u8 rgid[16];
117 } __attribute__((packed));
118
119 struct mthca_qp_context {
120 __be32 flags;
121 __be32 tavor_sched_queue; /* Reserved on Arbel */
122 u8 mtu_msgmax;
123 u8 rq_size_stride; /* Reserved on Tavor */
124 u8 sq_size_stride; /* Reserved on Tavor */
125 u8 rlkey_arbel_sched_queue; /* Reserved on Tavor */
126 __be32 usr_page;
127 __be32 local_qpn;
128 __be32 remote_qpn;
129 u32 reserved1[2];
130 struct mthca_qp_path pri_path;
131 struct mthca_qp_path alt_path;
132 __be32 rdd;
133 __be32 pd;
134 __be32 wqe_base;
135 __be32 wqe_lkey;
136 __be32 params1;
137 __be32 reserved2;
138 __be32 next_send_psn;
139 __be32 cqn_snd;
140 __be32 snd_wqe_base_l; /* Next send WQE on Tavor */
141 __be32 snd_db_index; /* (debugging only entries) */
142 __be32 last_acked_psn;
143 __be32 ssn;
144 __be32 params2;
145 __be32 rnr_nextrecvpsn;
146 __be32 ra_buff_indx;
147 __be32 cqn_rcv;
148 __be32 rcv_wqe_base_l; /* Next recv WQE on Tavor */
149 __be32 rcv_db_index; /* (debugging only entries) */
150 __be32 qkey;
151 __be32 srqn;
152 __be32 rmsn;
153 __be16 rq_wqe_counter; /* reserved on Tavor */
154 __be16 sq_wqe_counter; /* reserved on Tavor */
155 u32 reserved3[18];
156 } __attribute__((packed));
157
158 struct mthca_qp_param {
159 __be32 opt_param_mask;
160 u32 reserved1;
161 struct mthca_qp_context context;
162 u32 reserved2[62];
163 } __attribute__((packed));
164
165 enum {
166 MTHCA_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
167 MTHCA_QP_OPTPAR_RRE = 1 << 1,
168 MTHCA_QP_OPTPAR_RAE = 1 << 2,
169 MTHCA_QP_OPTPAR_RWE = 1 << 3,
170 MTHCA_QP_OPTPAR_PKEY_INDEX = 1 << 4,
171 MTHCA_QP_OPTPAR_Q_KEY = 1 << 5,
172 MTHCA_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
173 MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
174 MTHCA_QP_OPTPAR_SRA_MAX = 1 << 8,
175 MTHCA_QP_OPTPAR_RRA_MAX = 1 << 9,
176 MTHCA_QP_OPTPAR_PM_STATE = 1 << 10,
177 MTHCA_QP_OPTPAR_PORT_NUM = 1 << 11,
178 MTHCA_QP_OPTPAR_RETRY_COUNT = 1 << 12,
179 MTHCA_QP_OPTPAR_ALT_RNR_RETRY = 1 << 13,
180 MTHCA_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
181 MTHCA_QP_OPTPAR_RNR_RETRY = 1 << 15,
182 MTHCA_QP_OPTPAR_SCHED_QUEUE = 1 << 16
183 };
184
185 static const u8 mthca_opcode[] = {
186 [IB_WR_SEND] = MTHCA_OPCODE_SEND,
187 [IB_WR_SEND_WITH_IMM] = MTHCA_OPCODE_SEND_IMM,
188 [IB_WR_RDMA_WRITE] = MTHCA_OPCODE_RDMA_WRITE,
189 [IB_WR_RDMA_WRITE_WITH_IMM] = MTHCA_OPCODE_RDMA_WRITE_IMM,
190 [IB_WR_RDMA_READ] = MTHCA_OPCODE_RDMA_READ,
191 [IB_WR_ATOMIC_CMP_AND_SWP] = MTHCA_OPCODE_ATOMIC_CS,
192 [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
193 };
194
is_sqp(struct mthca_dev * dev,struct mthca_qp * qp)195 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
196 {
197 return qp->qpn >= dev->qp_table.sqp_start &&
198 qp->qpn <= dev->qp_table.sqp_start + 3;
199 }
200
is_qp0(struct mthca_dev * dev,struct mthca_qp * qp)201 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
202 {
203 return qp->qpn >= dev->qp_table.sqp_start &&
204 qp->qpn <= dev->qp_table.sqp_start + 1;
205 }
206
get_recv_wqe(struct mthca_qp * qp,int n)207 static void *get_recv_wqe(struct mthca_qp *qp, int n)
208 {
209 if (qp->is_direct)
210 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
211 else
212 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
213 ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
214 }
215
get_send_wqe(struct mthca_qp * qp,int n)216 static void *get_send_wqe(struct mthca_qp *qp, int n)
217 {
218 if (qp->is_direct)
219 return qp->queue.direct.buf + qp->send_wqe_offset +
220 (n << qp->sq.wqe_shift);
221 else
222 return qp->queue.page_list[(qp->send_wqe_offset +
223 (n << qp->sq.wqe_shift)) >>
224 PAGE_SHIFT].buf +
225 ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
226 (PAGE_SIZE - 1));
227 }
228
mthca_wq_reset(struct mthca_wq * wq)229 static void mthca_wq_reset(struct mthca_wq *wq)
230 {
231 wq->next_ind = 0;
232 wq->last_comp = wq->max - 1;
233 wq->head = 0;
234 wq->tail = 0;
235 }
236
mthca_qp_event(struct mthca_dev * dev,u32 qpn,enum ib_event_type event_type)237 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
238 enum ib_event_type event_type)
239 {
240 struct mthca_qp *qp;
241 struct ib_event event;
242
243 spin_lock(&dev->qp_table.lock);
244 qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
245 if (qp)
246 ++qp->refcount;
247 spin_unlock(&dev->qp_table.lock);
248
249 if (!qp) {
250 mthca_warn(dev, "Async event %d for bogus QP %08x\n",
251 (int) event_type, qpn);
252 return;
253 }
254
255 if (event_type == IB_EVENT_PATH_MIG)
256 qp->port = qp->alt_port;
257
258 event.device = &dev->ib_dev;
259 event.event = event_type;
260 event.element.qp = &qp->ibqp;
261 if (qp->ibqp.event_handler)
262 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
263
264 spin_lock(&dev->qp_table.lock);
265 if (!--qp->refcount)
266 wake_up(&qp->wait);
267 spin_unlock(&dev->qp_table.lock);
268 }
269
to_mthca_state(enum ib_qp_state ib_state)270 static int to_mthca_state(enum ib_qp_state ib_state)
271 {
272 switch (ib_state) {
273 case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
274 case IB_QPS_INIT: return MTHCA_QP_STATE_INIT;
275 case IB_QPS_RTR: return MTHCA_QP_STATE_RTR;
276 case IB_QPS_RTS: return MTHCA_QP_STATE_RTS;
277 case IB_QPS_SQD: return MTHCA_QP_STATE_SQD;
278 case IB_QPS_SQE: return MTHCA_QP_STATE_SQE;
279 case IB_QPS_ERR: return MTHCA_QP_STATE_ERR;
280 default: return -1;
281 }
282 }
283
284 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
285
to_mthca_st(int transport)286 static int to_mthca_st(int transport)
287 {
288 switch (transport) {
289 case RC: return MTHCA_QP_ST_RC;
290 case UC: return MTHCA_QP_ST_UC;
291 case UD: return MTHCA_QP_ST_UD;
292 case RD: return MTHCA_QP_ST_RD;
293 case MLX: return MTHCA_QP_ST_MLX;
294 default: return -1;
295 }
296 }
297
store_attrs(struct mthca_sqp * sqp,const struct ib_qp_attr * attr,int attr_mask)298 static void store_attrs(struct mthca_sqp *sqp, const struct ib_qp_attr *attr,
299 int attr_mask)
300 {
301 if (attr_mask & IB_QP_PKEY_INDEX)
302 sqp->pkey_index = attr->pkey_index;
303 if (attr_mask & IB_QP_QKEY)
304 sqp->qkey = attr->qkey;
305 if (attr_mask & IB_QP_SQ_PSN)
306 sqp->send_psn = attr->sq_psn;
307 }
308
init_port(struct mthca_dev * dev,int port)309 static void init_port(struct mthca_dev *dev, int port)
310 {
311 int err;
312 u8 status;
313 struct mthca_init_ib_param param;
314
315 memset(¶m, 0, sizeof param);
316
317 param.port_width = dev->limits.port_width_cap;
318 param.vl_cap = dev->limits.vl_cap;
319 param.mtu_cap = dev->limits.mtu_cap;
320 param.gid_cap = dev->limits.gid_table_len;
321 param.pkey_cap = dev->limits.pkey_table_len;
322
323 err = mthca_INIT_IB(dev, ¶m, port, &status);
324 if (err)
325 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
326 if (status)
327 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
328 }
329
get_hw_access_flags(struct mthca_qp * qp,const struct ib_qp_attr * attr,int attr_mask)330 static __be32 get_hw_access_flags(struct mthca_qp *qp, const struct ib_qp_attr *attr,
331 int attr_mask)
332 {
333 u8 dest_rd_atomic;
334 u32 access_flags;
335 u32 hw_access_flags = 0;
336
337 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
338 dest_rd_atomic = attr->max_dest_rd_atomic;
339 else
340 dest_rd_atomic = qp->resp_depth;
341
342 if (attr_mask & IB_QP_ACCESS_FLAGS)
343 access_flags = attr->qp_access_flags;
344 else
345 access_flags = qp->atomic_rd_en;
346
347 if (!dest_rd_atomic)
348 access_flags &= IB_ACCESS_REMOTE_WRITE;
349
350 if (access_flags & IB_ACCESS_REMOTE_READ)
351 hw_access_flags |= MTHCA_QP_BIT_RRE;
352 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
353 hw_access_flags |= MTHCA_QP_BIT_RAE;
354 if (access_flags & IB_ACCESS_REMOTE_WRITE)
355 hw_access_flags |= MTHCA_QP_BIT_RWE;
356
357 return cpu_to_be32(hw_access_flags);
358 }
359
to_ib_qp_state(int mthca_state)360 static inline enum ib_qp_state to_ib_qp_state(int mthca_state)
361 {
362 switch (mthca_state) {
363 case MTHCA_QP_STATE_RST: return IB_QPS_RESET;
364 case MTHCA_QP_STATE_INIT: return IB_QPS_INIT;
365 case MTHCA_QP_STATE_RTR: return IB_QPS_RTR;
366 case MTHCA_QP_STATE_RTS: return IB_QPS_RTS;
367 case MTHCA_QP_STATE_DRAINING:
368 case MTHCA_QP_STATE_SQD: return IB_QPS_SQD;
369 case MTHCA_QP_STATE_SQE: return IB_QPS_SQE;
370 case MTHCA_QP_STATE_ERR: return IB_QPS_ERR;
371 default: return -1;
372 }
373 }
374
to_ib_mig_state(int mthca_mig_state)375 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state)
376 {
377 switch (mthca_mig_state) {
378 case 0: return IB_MIG_ARMED;
379 case 1: return IB_MIG_REARM;
380 case 3: return IB_MIG_MIGRATED;
381 default: return -1;
382 }
383 }
384
to_ib_qp_access_flags(int mthca_flags)385 static int to_ib_qp_access_flags(int mthca_flags)
386 {
387 int ib_flags = 0;
388
389 if (mthca_flags & MTHCA_QP_BIT_RRE)
390 ib_flags |= IB_ACCESS_REMOTE_READ;
391 if (mthca_flags & MTHCA_QP_BIT_RWE)
392 ib_flags |= IB_ACCESS_REMOTE_WRITE;
393 if (mthca_flags & MTHCA_QP_BIT_RAE)
394 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
395
396 return ib_flags;
397 }
398
to_ib_ah_attr(struct mthca_dev * dev,struct ib_ah_attr * ib_ah_attr,struct mthca_qp_path * path)399 static void to_ib_ah_attr(struct mthca_dev *dev, struct ib_ah_attr *ib_ah_attr,
400 struct mthca_qp_path *path)
401 {
402 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
403 ib_ah_attr->port_num = (be32_to_cpu(path->port_pkey) >> 24) & 0x3;
404
405 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->limits.num_ports)
406 return;
407
408 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
409 ib_ah_attr->sl = be32_to_cpu(path->sl_tclass_flowlabel) >> 28;
410 ib_ah_attr->src_path_bits = path->g_mylmc & 0x7f;
411 ib_ah_attr->static_rate = mthca_rate_to_ib(dev,
412 path->static_rate & 0xf,
413 ib_ah_attr->port_num);
414 ib_ah_attr->ah_flags = (path->g_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
415 if (ib_ah_attr->ah_flags) {
416 ib_ah_attr->grh.sgid_index = path->mgid_index & (dev->limits.gid_table_len - 1);
417 ib_ah_attr->grh.hop_limit = path->hop_limit;
418 ib_ah_attr->grh.traffic_class =
419 (be32_to_cpu(path->sl_tclass_flowlabel) >> 20) & 0xff;
420 ib_ah_attr->grh.flow_label =
421 be32_to_cpu(path->sl_tclass_flowlabel) & 0xfffff;
422 memcpy(ib_ah_attr->grh.dgid.raw,
423 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
424 }
425 }
426
mthca_query_qp(struct ib_qp * ibqp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)427 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
428 struct ib_qp_init_attr *qp_init_attr)
429 {
430 struct mthca_dev *dev = to_mdev(ibqp->device);
431 struct mthca_qp *qp = to_mqp(ibqp);
432 int err = 0;
433 struct mthca_mailbox *mailbox = NULL;
434 struct mthca_qp_param *qp_param;
435 struct mthca_qp_context *context;
436 int mthca_state;
437 u8 status;
438
439 mutex_lock(&qp->mutex);
440
441 if (qp->state == IB_QPS_RESET) {
442 qp_attr->qp_state = IB_QPS_RESET;
443 goto done;
444 }
445
446 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
447 if (IS_ERR(mailbox)) {
448 err = PTR_ERR(mailbox);
449 goto out;
450 }
451
452 err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox, &status);
453 if (err)
454 goto out_mailbox;
455 if (status) {
456 mthca_warn(dev, "QUERY_QP returned status %02x\n", status);
457 err = -EINVAL;
458 goto out_mailbox;
459 }
460
461 qp_param = mailbox->buf;
462 context = &qp_param->context;
463 mthca_state = be32_to_cpu(context->flags) >> 28;
464
465 qp->state = to_ib_qp_state(mthca_state);
466 qp_attr->qp_state = qp->state;
467 qp_attr->path_mtu = context->mtu_msgmax >> 5;
468 qp_attr->path_mig_state =
469 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
470 qp_attr->qkey = be32_to_cpu(context->qkey);
471 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
472 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
473 qp_attr->dest_qp_num = be32_to_cpu(context->remote_qpn) & 0xffffff;
474 qp_attr->qp_access_flags =
475 to_ib_qp_access_flags(be32_to_cpu(context->params2));
476
477 if (qp->transport == RC || qp->transport == UC) {
478 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
479 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
480 qp_attr->alt_pkey_index =
481 be32_to_cpu(context->alt_path.port_pkey) & 0x7f;
482 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
483 }
484
485 qp_attr->pkey_index = be32_to_cpu(context->pri_path.port_pkey) & 0x7f;
486 qp_attr->port_num =
487 (be32_to_cpu(context->pri_path.port_pkey) >> 24) & 0x3;
488
489 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
490 qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING;
491
492 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
493
494 qp_attr->max_dest_rd_atomic =
495 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
496 qp_attr->min_rnr_timer =
497 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
498 qp_attr->timeout = context->pri_path.ackto >> 3;
499 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
500 qp_attr->rnr_retry = context->pri_path.rnr_retry >> 5;
501 qp_attr->alt_timeout = context->alt_path.ackto >> 3;
502
503 done:
504 qp_attr->cur_qp_state = qp_attr->qp_state;
505 qp_attr->cap.max_send_wr = qp->sq.max;
506 qp_attr->cap.max_recv_wr = qp->rq.max;
507 qp_attr->cap.max_send_sge = qp->sq.max_gs;
508 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
509 qp_attr->cap.max_inline_data = qp->max_inline_data;
510
511 qp_init_attr->cap = qp_attr->cap;
512
513 out_mailbox:
514 mthca_free_mailbox(dev, mailbox);
515
516 out:
517 mutex_unlock(&qp->mutex);
518 return err;
519 }
520
mthca_path_set(struct mthca_dev * dev,const struct ib_ah_attr * ah,struct mthca_qp_path * path,u8 port)521 static int mthca_path_set(struct mthca_dev *dev, const struct ib_ah_attr *ah,
522 struct mthca_qp_path *path, u8 port)
523 {
524 path->g_mylmc = ah->src_path_bits & 0x7f;
525 path->rlid = cpu_to_be16(ah->dlid);
526 path->static_rate = mthca_get_rate(dev, ah->static_rate, port);
527
528 if (ah->ah_flags & IB_AH_GRH) {
529 if (ah->grh.sgid_index >= dev->limits.gid_table_len) {
530 mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n",
531 ah->grh.sgid_index, dev->limits.gid_table_len-1);
532 return -1;
533 }
534
535 path->g_mylmc |= 1 << 7;
536 path->mgid_index = ah->grh.sgid_index;
537 path->hop_limit = ah->grh.hop_limit;
538 path->sl_tclass_flowlabel =
539 cpu_to_be32((ah->sl << 28) |
540 (ah->grh.traffic_class << 20) |
541 (ah->grh.flow_label));
542 memcpy(path->rgid, ah->grh.dgid.raw, 16);
543 } else
544 path->sl_tclass_flowlabel = cpu_to_be32(ah->sl << 28);
545
546 return 0;
547 }
548
__mthca_modify_qp(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state)549 static int __mthca_modify_qp(struct ib_qp *ibqp,
550 const struct ib_qp_attr *attr, int attr_mask,
551 enum ib_qp_state cur_state, enum ib_qp_state new_state)
552 {
553 struct mthca_dev *dev = to_mdev(ibqp->device);
554 struct mthca_qp *qp = to_mqp(ibqp);
555 struct mthca_mailbox *mailbox;
556 struct mthca_qp_param *qp_param;
557 struct mthca_qp_context *qp_context;
558 u32 sqd_event = 0;
559 u8 status;
560 int err = -EINVAL;
561
562 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
563 if (IS_ERR(mailbox)) {
564 err = PTR_ERR(mailbox);
565 goto out;
566 }
567 qp_param = mailbox->buf;
568 qp_context = &qp_param->context;
569 memset(qp_param, 0, sizeof *qp_param);
570
571 qp_context->flags = cpu_to_be32((to_mthca_state(new_state) << 28) |
572 (to_mthca_st(qp->transport) << 16));
573 qp_context->flags |= cpu_to_be32(MTHCA_QP_BIT_DE);
574 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
575 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
576 else {
577 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
578 switch (attr->path_mig_state) {
579 case IB_MIG_MIGRATED:
580 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
581 break;
582 case IB_MIG_REARM:
583 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
584 break;
585 case IB_MIG_ARMED:
586 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
587 break;
588 }
589 }
590
591 /* leave tavor_sched_queue as 0 */
592
593 if (qp->transport == MLX || qp->transport == UD)
594 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
595 else if (attr_mask & IB_QP_PATH_MTU) {
596 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) {
597 mthca_dbg(dev, "path MTU (%u) is invalid\n",
598 attr->path_mtu);
599 goto out_mailbox;
600 }
601 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
602 }
603
604 if (mthca_is_memfree(dev)) {
605 if (qp->rq.max)
606 qp_context->rq_size_stride = ilog2(qp->rq.max) << 3;
607 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
608
609 if (qp->sq.max)
610 qp_context->sq_size_stride = ilog2(qp->sq.max) << 3;
611 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
612 }
613
614 /* leave arbel_sched_queue as 0 */
615
616 if (qp->ibqp.uobject)
617 qp_context->usr_page =
618 cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
619 else
620 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
621 qp_context->local_qpn = cpu_to_be32(qp->qpn);
622 if (attr_mask & IB_QP_DEST_QPN) {
623 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
624 }
625
626 if (qp->transport == MLX)
627 qp_context->pri_path.port_pkey |=
628 cpu_to_be32(qp->port << 24);
629 else {
630 if (attr_mask & IB_QP_PORT) {
631 qp_context->pri_path.port_pkey |=
632 cpu_to_be32(attr->port_num << 24);
633 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
634 }
635 }
636
637 if (attr_mask & IB_QP_PKEY_INDEX) {
638 qp_context->pri_path.port_pkey |=
639 cpu_to_be32(attr->pkey_index);
640 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
641 }
642
643 if (attr_mask & IB_QP_RNR_RETRY) {
644 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry =
645 attr->rnr_retry << 5;
646 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY |
647 MTHCA_QP_OPTPAR_ALT_RNR_RETRY);
648 }
649
650 if (attr_mask & IB_QP_AV) {
651 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path,
652 attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
653 goto out_mailbox;
654
655 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
656 }
657
658 if (ibqp->qp_type == IB_QPT_RC &&
659 cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
660 u8 sched_queue = ibqp->uobject ? 0x2 : 0x1;
661
662 if (mthca_is_memfree(dev))
663 qp_context->rlkey_arbel_sched_queue |= sched_queue;
664 else
665 qp_context->tavor_sched_queue |= cpu_to_be32(sched_queue);
666
667 qp_param->opt_param_mask |=
668 cpu_to_be32(MTHCA_QP_OPTPAR_SCHED_QUEUE);
669 }
670
671 if (attr_mask & IB_QP_TIMEOUT) {
672 qp_context->pri_path.ackto = attr->timeout << 3;
673 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
674 }
675
676 if (attr_mask & IB_QP_ALT_PATH) {
677 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) {
678 mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n",
679 attr->alt_pkey_index, dev->limits.pkey_table_len-1);
680 goto out_mailbox;
681 }
682
683 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) {
684 mthca_dbg(dev, "Alternate port number (%u) is invalid\n",
685 attr->alt_port_num);
686 goto out_mailbox;
687 }
688
689 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path,
690 attr->alt_ah_attr.port_num))
691 goto out_mailbox;
692
693 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index |
694 attr->alt_port_num << 24);
695 qp_context->alt_path.ackto = attr->alt_timeout << 3;
696 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH);
697 }
698
699 /* leave rdd as 0 */
700 qp_context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
701 /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
702 qp_context->wqe_lkey = cpu_to_be32(qp->mr.ibmr.lkey);
703 qp_context->params1 = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
704 (MTHCA_FLIGHT_LIMIT << 24) |
705 MTHCA_QP_BIT_SWE);
706 if (qp->sq_policy == IB_SIGNAL_ALL_WR)
707 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
708 if (attr_mask & IB_QP_RETRY_CNT) {
709 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
710 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
711 }
712
713 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
714 if (attr->max_rd_atomic) {
715 qp_context->params1 |=
716 cpu_to_be32(MTHCA_QP_BIT_SRE |
717 MTHCA_QP_BIT_SAE);
718 qp_context->params1 |=
719 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
720 }
721 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
722 }
723
724 if (attr_mask & IB_QP_SQ_PSN)
725 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
726 qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
727
728 if (mthca_is_memfree(dev)) {
729 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
730 qp_context->snd_db_index = cpu_to_be32(qp->sq.db_index);
731 }
732
733 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
734 if (attr->max_dest_rd_atomic)
735 qp_context->params2 |=
736 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
737
738 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
739 }
740
741 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
742 qp_context->params2 |= get_hw_access_flags(qp, attr, attr_mask);
743 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
744 MTHCA_QP_OPTPAR_RRE |
745 MTHCA_QP_OPTPAR_RAE);
746 }
747
748 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
749
750 if (ibqp->srq)
751 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
752
753 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
754 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
755 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
756 }
757 if (attr_mask & IB_QP_RQ_PSN)
758 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
759
760 qp_context->ra_buff_indx =
761 cpu_to_be32(dev->qp_table.rdb_base +
762 ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
763 dev->qp_table.rdb_shift));
764
765 qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
766
767 if (mthca_is_memfree(dev))
768 qp_context->rcv_db_index = cpu_to_be32(qp->rq.db_index);
769
770 if (attr_mask & IB_QP_QKEY) {
771 qp_context->qkey = cpu_to_be32(attr->qkey);
772 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
773 }
774
775 if (ibqp->srq)
776 qp_context->srqn = cpu_to_be32(1 << 24 |
777 to_msrq(ibqp->srq)->srqn);
778
779 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
780 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY &&
781 attr->en_sqd_async_notify)
782 sqd_event = 1 << 31;
783
784 err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0,
785 mailbox, sqd_event, &status);
786 if (err)
787 goto out_mailbox;
788 if (status) {
789 mthca_warn(dev, "modify QP %d->%d returned status %02x.\n",
790 cur_state, new_state, status);
791 err = -EINVAL;
792 goto out_mailbox;
793 }
794
795 qp->state = new_state;
796 if (attr_mask & IB_QP_ACCESS_FLAGS)
797 qp->atomic_rd_en = attr->qp_access_flags;
798 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
799 qp->resp_depth = attr->max_dest_rd_atomic;
800 if (attr_mask & IB_QP_PORT)
801 qp->port = attr->port_num;
802 if (attr_mask & IB_QP_ALT_PATH)
803 qp->alt_port = attr->alt_port_num;
804
805 if (is_sqp(dev, qp))
806 store_attrs(to_msqp(qp), attr, attr_mask);
807
808 /*
809 * If we moved QP0 to RTR, bring the IB link up; if we moved
810 * QP0 to RESET or ERROR, bring the link back down.
811 */
812 if (is_qp0(dev, qp)) {
813 if (cur_state != IB_QPS_RTR &&
814 new_state == IB_QPS_RTR)
815 init_port(dev, qp->port);
816
817 if (cur_state != IB_QPS_RESET &&
818 cur_state != IB_QPS_ERR &&
819 (new_state == IB_QPS_RESET ||
820 new_state == IB_QPS_ERR))
821 mthca_CLOSE_IB(dev, qp->port, &status);
822 }
823
824 /*
825 * If we moved a kernel QP to RESET, clean up all old CQ
826 * entries and reinitialize the QP.
827 */
828 if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
829 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
830 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
831 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
832 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn, NULL);
833
834 mthca_wq_reset(&qp->sq);
835 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
836
837 mthca_wq_reset(&qp->rq);
838 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
839
840 if (mthca_is_memfree(dev)) {
841 *qp->sq.db = 0;
842 *qp->rq.db = 0;
843 }
844 }
845
846 out_mailbox:
847 mthca_free_mailbox(dev, mailbox);
848 out:
849 return err;
850 }
851
mthca_modify_qp(struct ib_qp * ibqp,struct ib_qp_attr * attr,int attr_mask,struct ib_udata * udata)852 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
853 struct ib_udata *udata)
854 {
855 struct mthca_dev *dev = to_mdev(ibqp->device);
856 struct mthca_qp *qp = to_mqp(ibqp);
857 enum ib_qp_state cur_state, new_state;
858 int err = -EINVAL;
859
860 mutex_lock(&qp->mutex);
861 if (attr_mask & IB_QP_CUR_STATE) {
862 cur_state = attr->cur_qp_state;
863 } else {
864 spin_lock_irq(&qp->sq.lock);
865 spin_lock(&qp->rq.lock);
866 cur_state = qp->state;
867 spin_unlock(&qp->rq.lock);
868 spin_unlock_irq(&qp->sq.lock);
869 }
870
871 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
872
873 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
874 attr_mask, IB_LINK_LAYER_UNSPECIFIED)) {
875 mthca_dbg(dev, "Bad QP transition (transport %d) "
876 "%d->%d with attr 0x%08x\n",
877 qp->transport, cur_state, new_state,
878 attr_mask);
879 goto out;
880 }
881
882 if ((attr_mask & IB_QP_PKEY_INDEX) &&
883 attr->pkey_index >= dev->limits.pkey_table_len) {
884 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n",
885 attr->pkey_index, dev->limits.pkey_table_len-1);
886 goto out;
887 }
888
889 if ((attr_mask & IB_QP_PORT) &&
890 (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
891 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
892 goto out;
893 }
894
895 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
896 attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
897 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
898 attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
899 goto out;
900 }
901
902 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
903 attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
904 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
905 attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
906 goto out;
907 }
908
909 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
910 err = 0;
911 goto out;
912 }
913
914 err = __mthca_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
915
916 out:
917 mutex_unlock(&qp->mutex);
918 return err;
919 }
920
mthca_max_data_size(struct mthca_dev * dev,struct mthca_qp * qp,int desc_sz)921 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
922 {
923 /*
924 * Calculate the maximum size of WQE s/g segments, excluding
925 * the next segment and other non-data segments.
926 */
927 int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
928
929 switch (qp->transport) {
930 case MLX:
931 max_data_size -= 2 * sizeof (struct mthca_data_seg);
932 break;
933
934 case UD:
935 if (mthca_is_memfree(dev))
936 max_data_size -= sizeof (struct mthca_arbel_ud_seg);
937 else
938 max_data_size -= sizeof (struct mthca_tavor_ud_seg);
939 break;
940
941 default:
942 max_data_size -= sizeof (struct mthca_raddr_seg);
943 break;
944 }
945
946 return max_data_size;
947 }
948
mthca_max_inline_data(struct mthca_pd * pd,int max_data_size)949 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
950 {
951 /* We don't support inline data for kernel QPs (yet). */
952 return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
953 }
954
mthca_adjust_qp_caps(struct mthca_dev * dev,struct mthca_pd * pd,struct mthca_qp * qp)955 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
956 struct mthca_pd *pd,
957 struct mthca_qp *qp)
958 {
959 int max_data_size = mthca_max_data_size(dev, qp,
960 min(dev->limits.max_desc_sz,
961 1 << qp->sq.wqe_shift));
962
963 qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
964
965 qp->sq.max_gs = min_t(int, dev->limits.max_sg,
966 max_data_size / sizeof (struct mthca_data_seg));
967 qp->rq.max_gs = min_t(int, dev->limits.max_sg,
968 (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
969 sizeof (struct mthca_next_seg)) /
970 sizeof (struct mthca_data_seg));
971 }
972
973 /*
974 * Allocate and register buffer for WQEs. qp->rq.max, sq.max,
975 * rq.max_gs and sq.max_gs must all be assigned.
976 * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
977 * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
978 * queue)
979 */
mthca_alloc_wqe_buf(struct mthca_dev * dev,struct mthca_pd * pd,struct mthca_qp * qp)980 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
981 struct mthca_pd *pd,
982 struct mthca_qp *qp)
983 {
984 int size;
985 int err = -ENOMEM;
986
987 size = sizeof (struct mthca_next_seg) +
988 qp->rq.max_gs * sizeof (struct mthca_data_seg);
989
990 if (size > dev->limits.max_desc_sz)
991 return -EINVAL;
992
993 for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
994 qp->rq.wqe_shift++)
995 ; /* nothing */
996
997 size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
998 switch (qp->transport) {
999 case MLX:
1000 size += 2 * sizeof (struct mthca_data_seg);
1001 break;
1002
1003 case UD:
1004 size += mthca_is_memfree(dev) ?
1005 sizeof (struct mthca_arbel_ud_seg) :
1006 sizeof (struct mthca_tavor_ud_seg);
1007 break;
1008
1009 case UC:
1010 size += sizeof (struct mthca_raddr_seg);
1011 break;
1012
1013 case RC:
1014 size += sizeof (struct mthca_raddr_seg);
1015 /*
1016 * An atomic op will require an atomic segment, a
1017 * remote address segment and one scatter entry.
1018 */
1019 size = max_t(int, size,
1020 sizeof (struct mthca_atomic_seg) +
1021 sizeof (struct mthca_raddr_seg) +
1022 sizeof (struct mthca_data_seg));
1023 break;
1024
1025 default:
1026 break;
1027 }
1028
1029 /* Make sure that we have enough space for a bind request */
1030 size = max_t(int, size, sizeof (struct mthca_bind_seg));
1031
1032 size += sizeof (struct mthca_next_seg);
1033
1034 if (size > dev->limits.max_desc_sz)
1035 return -EINVAL;
1036
1037 for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
1038 qp->sq.wqe_shift++)
1039 ; /* nothing */
1040
1041 qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
1042 1 << qp->sq.wqe_shift);
1043
1044 /*
1045 * If this is a userspace QP, we don't actually have to
1046 * allocate anything. All we need is to calculate the WQE
1047 * sizes and the send_wqe_offset, so we're done now.
1048 */
1049 if (pd->ibpd.uobject)
1050 return 0;
1051
1052 size = PAGE_ALIGN(qp->send_wqe_offset +
1053 (qp->sq.max << qp->sq.wqe_shift));
1054
1055 qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1056 GFP_KERNEL);
1057 if (!qp->wrid)
1058 goto err_out;
1059
1060 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1061 &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1062 if (err)
1063 goto err_out;
1064
1065 return 0;
1066
1067 err_out:
1068 kfree(qp->wrid);
1069 return err;
1070 }
1071
mthca_free_wqe_buf(struct mthca_dev * dev,struct mthca_qp * qp)1072 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1073 struct mthca_qp *qp)
1074 {
1075 mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1076 (qp->sq.max << qp->sq.wqe_shift)),
1077 &qp->queue, qp->is_direct, &qp->mr);
1078 kfree(qp->wrid);
1079 }
1080
mthca_map_memfree(struct mthca_dev * dev,struct mthca_qp * qp)1081 static int mthca_map_memfree(struct mthca_dev *dev,
1082 struct mthca_qp *qp)
1083 {
1084 int ret;
1085
1086 if (mthca_is_memfree(dev)) {
1087 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1088 if (ret)
1089 return ret;
1090
1091 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1092 if (ret)
1093 goto err_qpc;
1094
1095 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1096 qp->qpn << dev->qp_table.rdb_shift);
1097 if (ret)
1098 goto err_eqpc;
1099
1100 }
1101
1102 return 0;
1103
1104 err_eqpc:
1105 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1106
1107 err_qpc:
1108 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1109
1110 return ret;
1111 }
1112
mthca_unmap_memfree(struct mthca_dev * dev,struct mthca_qp * qp)1113 static void mthca_unmap_memfree(struct mthca_dev *dev,
1114 struct mthca_qp *qp)
1115 {
1116 mthca_table_put(dev, dev->qp_table.rdb_table,
1117 qp->qpn << dev->qp_table.rdb_shift);
1118 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1119 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1120 }
1121
mthca_alloc_memfree(struct mthca_dev * dev,struct mthca_qp * qp)1122 static int mthca_alloc_memfree(struct mthca_dev *dev,
1123 struct mthca_qp *qp)
1124 {
1125 if (mthca_is_memfree(dev)) {
1126 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1127 qp->qpn, &qp->rq.db);
1128 if (qp->rq.db_index < 0)
1129 return -ENOMEM;
1130
1131 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1132 qp->qpn, &qp->sq.db);
1133 if (qp->sq.db_index < 0) {
1134 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1135 return -ENOMEM;
1136 }
1137 }
1138
1139 return 0;
1140 }
1141
mthca_free_memfree(struct mthca_dev * dev,struct mthca_qp * qp)1142 static void mthca_free_memfree(struct mthca_dev *dev,
1143 struct mthca_qp *qp)
1144 {
1145 if (mthca_is_memfree(dev)) {
1146 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1147 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1148 }
1149 }
1150
mthca_alloc_qp_common(struct mthca_dev * dev,struct mthca_pd * pd,struct mthca_cq * send_cq,struct mthca_cq * recv_cq,enum ib_sig_type send_policy,struct mthca_qp * qp)1151 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1152 struct mthca_pd *pd,
1153 struct mthca_cq *send_cq,
1154 struct mthca_cq *recv_cq,
1155 enum ib_sig_type send_policy,
1156 struct mthca_qp *qp)
1157 {
1158 int ret;
1159 int i;
1160 struct mthca_next_seg *next;
1161
1162 qp->refcount = 1;
1163 init_waitqueue_head(&qp->wait);
1164 mutex_init(&qp->mutex);
1165 qp->state = IB_QPS_RESET;
1166 qp->atomic_rd_en = 0;
1167 qp->resp_depth = 0;
1168 qp->sq_policy = send_policy;
1169 mthca_wq_reset(&qp->sq);
1170 mthca_wq_reset(&qp->rq);
1171
1172 spin_lock_init(&qp->sq.lock);
1173 spin_lock_init(&qp->rq.lock);
1174
1175 ret = mthca_map_memfree(dev, qp);
1176 if (ret)
1177 return ret;
1178
1179 ret = mthca_alloc_wqe_buf(dev, pd, qp);
1180 if (ret) {
1181 mthca_unmap_memfree(dev, qp);
1182 return ret;
1183 }
1184
1185 mthca_adjust_qp_caps(dev, pd, qp);
1186
1187 /*
1188 * If this is a userspace QP, we're done now. The doorbells
1189 * will be allocated and buffers will be initialized in
1190 * userspace.
1191 */
1192 if (pd->ibpd.uobject)
1193 return 0;
1194
1195 ret = mthca_alloc_memfree(dev, qp);
1196 if (ret) {
1197 mthca_free_wqe_buf(dev, qp);
1198 mthca_unmap_memfree(dev, qp);
1199 return ret;
1200 }
1201
1202 if (mthca_is_memfree(dev)) {
1203 struct mthca_data_seg *scatter;
1204 int size = (sizeof (struct mthca_next_seg) +
1205 qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1206
1207 for (i = 0; i < qp->rq.max; ++i) {
1208 next = get_recv_wqe(qp, i);
1209 next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1210 qp->rq.wqe_shift);
1211 next->ee_nds = cpu_to_be32(size);
1212
1213 for (scatter = (void *) (next + 1);
1214 (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1215 ++scatter)
1216 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1217 }
1218
1219 for (i = 0; i < qp->sq.max; ++i) {
1220 next = get_send_wqe(qp, i);
1221 next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1222 qp->sq.wqe_shift) +
1223 qp->send_wqe_offset);
1224 }
1225 } else {
1226 for (i = 0; i < qp->rq.max; ++i) {
1227 next = get_recv_wqe(qp, i);
1228 next->nda_op = htonl((((i + 1) % qp->rq.max) <<
1229 qp->rq.wqe_shift) | 1);
1230 }
1231
1232 }
1233
1234 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1235 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1236
1237 return 0;
1238 }
1239
mthca_set_qp_size(struct mthca_dev * dev,struct ib_qp_cap * cap,struct mthca_pd * pd,struct mthca_qp * qp)1240 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1241 struct mthca_pd *pd, struct mthca_qp *qp)
1242 {
1243 int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1244 u32 max_inline_data;
1245
1246 /* Sanity check QP size before proceeding */
1247 if (cap->max_send_wr > dev->limits.max_wqes ||
1248 cap->max_recv_wr > dev->limits.max_wqes ||
1249 cap->max_send_sge > dev->limits.max_sg ||
1250 cap->max_recv_sge > dev->limits.max_sg)
1251 return -EINVAL;
1252
1253 if (pd->ibpd.uobject &&
1254 cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1255 return -EINVAL;
1256
1257 max_inline_data = pd->ibpd.uobject ? cap->max_inline_data : 0;
1258
1259 /*
1260 * For MLX transport we need 2 extra send gather entries:
1261 * one for the header and one for the checksum at the end
1262 */
1263 if (qp->transport == MLX && cap->max_send_sge + 2 > dev->limits.max_sg)
1264 return -EINVAL;
1265
1266 if (mthca_is_memfree(dev)) {
1267 qp->rq.max = cap->max_recv_wr ?
1268 roundup_pow_of_two(cap->max_recv_wr) : 0;
1269 qp->sq.max = cap->max_send_wr ?
1270 roundup_pow_of_two(cap->max_send_wr) : 0;
1271 } else {
1272 qp->rq.max = cap->max_recv_wr;
1273 qp->sq.max = cap->max_send_wr;
1274 }
1275
1276 qp->rq.max_gs = cap->max_recv_sge;
1277 qp->sq.max_gs = max_t(int, cap->max_send_sge,
1278 ALIGN(max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1279 MTHCA_INLINE_CHUNK_SIZE) /
1280 sizeof (struct mthca_data_seg));
1281
1282 return 0;
1283 }
1284
mthca_alloc_qp(struct mthca_dev * dev,struct mthca_pd * pd,struct mthca_cq * send_cq,struct mthca_cq * recv_cq,enum ib_qp_type type,enum ib_sig_type send_policy,struct ib_qp_cap * cap,struct mthca_qp * qp)1285 int mthca_alloc_qp(struct mthca_dev *dev,
1286 struct mthca_pd *pd,
1287 struct mthca_cq *send_cq,
1288 struct mthca_cq *recv_cq,
1289 enum ib_qp_type type,
1290 enum ib_sig_type send_policy,
1291 struct ib_qp_cap *cap,
1292 struct mthca_qp *qp)
1293 {
1294 int err;
1295
1296 switch (type) {
1297 case IB_QPT_RC: qp->transport = RC; break;
1298 case IB_QPT_UC: qp->transport = UC; break;
1299 case IB_QPT_UD: qp->transport = UD; break;
1300 default: return -EINVAL;
1301 }
1302
1303 err = mthca_set_qp_size(dev, cap, pd, qp);
1304 if (err)
1305 return err;
1306
1307 qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1308 if (qp->qpn == -1)
1309 return -ENOMEM;
1310
1311 /* initialize port to zero for error-catching. */
1312 qp->port = 0;
1313
1314 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1315 send_policy, qp);
1316 if (err) {
1317 mthca_free(&dev->qp_table.alloc, qp->qpn);
1318 return err;
1319 }
1320
1321 spin_lock_irq(&dev->qp_table.lock);
1322 mthca_array_set(&dev->qp_table.qp,
1323 qp->qpn & (dev->limits.num_qps - 1), qp);
1324 spin_unlock_irq(&dev->qp_table.lock);
1325
1326 return 0;
1327 }
1328
mthca_lock_cqs(struct mthca_cq * send_cq,struct mthca_cq * recv_cq)1329 static void mthca_lock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1330 {
1331 if (send_cq == recv_cq)
1332 spin_lock_irq(&send_cq->lock);
1333 else if (send_cq->cqn < recv_cq->cqn) {
1334 spin_lock_irq(&send_cq->lock);
1335 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1336 } else {
1337 spin_lock_irq(&recv_cq->lock);
1338 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1339 }
1340 }
1341
mthca_unlock_cqs(struct mthca_cq * send_cq,struct mthca_cq * recv_cq)1342 static void mthca_unlock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1343 {
1344 if (send_cq == recv_cq)
1345 spin_unlock_irq(&send_cq->lock);
1346 else if (send_cq->cqn < recv_cq->cqn) {
1347 spin_unlock(&recv_cq->lock);
1348 spin_unlock_irq(&send_cq->lock);
1349 } else {
1350 spin_unlock(&send_cq->lock);
1351 spin_unlock_irq(&recv_cq->lock);
1352 }
1353 }
1354
mthca_alloc_sqp(struct mthca_dev * dev,struct mthca_pd * pd,struct mthca_cq * send_cq,struct mthca_cq * recv_cq,enum ib_sig_type send_policy,struct ib_qp_cap * cap,int qpn,int port,struct mthca_sqp * sqp)1355 int mthca_alloc_sqp(struct mthca_dev *dev,
1356 struct mthca_pd *pd,
1357 struct mthca_cq *send_cq,
1358 struct mthca_cq *recv_cq,
1359 enum ib_sig_type send_policy,
1360 struct ib_qp_cap *cap,
1361 int qpn,
1362 int port,
1363 struct mthca_sqp *sqp)
1364 {
1365 u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1366 int err;
1367
1368 sqp->qp.transport = MLX;
1369 err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1370 if (err)
1371 return err;
1372
1373 sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1374 sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1375 &sqp->header_dma, GFP_KERNEL);
1376 if (!sqp->header_buf)
1377 return -ENOMEM;
1378
1379 spin_lock_irq(&dev->qp_table.lock);
1380 if (mthca_array_get(&dev->qp_table.qp, mqpn))
1381 err = -EBUSY;
1382 else
1383 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1384 spin_unlock_irq(&dev->qp_table.lock);
1385
1386 if (err)
1387 goto err_out;
1388
1389 sqp->qp.port = port;
1390 sqp->qp.qpn = mqpn;
1391 sqp->qp.transport = MLX;
1392
1393 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1394 send_policy, &sqp->qp);
1395 if (err)
1396 goto err_out_free;
1397
1398 atomic_inc(&pd->sqp_count);
1399
1400 return 0;
1401
1402 err_out_free:
1403 /*
1404 * Lock CQs here, so that CQ polling code can do QP lookup
1405 * without taking a lock.
1406 */
1407 mthca_lock_cqs(send_cq, recv_cq);
1408
1409 spin_lock(&dev->qp_table.lock);
1410 mthca_array_clear(&dev->qp_table.qp, mqpn);
1411 spin_unlock(&dev->qp_table.lock);
1412
1413 mthca_unlock_cqs(send_cq, recv_cq);
1414
1415 err_out:
1416 dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1417 sqp->header_buf, sqp->header_dma);
1418
1419 return err;
1420 }
1421
get_qp_refcount(struct mthca_dev * dev,struct mthca_qp * qp)1422 static inline int get_qp_refcount(struct mthca_dev *dev, struct mthca_qp *qp)
1423 {
1424 int c;
1425
1426 spin_lock_irq(&dev->qp_table.lock);
1427 c = qp->refcount;
1428 spin_unlock_irq(&dev->qp_table.lock);
1429
1430 return c;
1431 }
1432
mthca_free_qp(struct mthca_dev * dev,struct mthca_qp * qp)1433 void mthca_free_qp(struct mthca_dev *dev,
1434 struct mthca_qp *qp)
1435 {
1436 u8 status;
1437 struct mthca_cq *send_cq;
1438 struct mthca_cq *recv_cq;
1439
1440 send_cq = to_mcq(qp->ibqp.send_cq);
1441 recv_cq = to_mcq(qp->ibqp.recv_cq);
1442
1443 /*
1444 * Lock CQs here, so that CQ polling code can do QP lookup
1445 * without taking a lock.
1446 */
1447 mthca_lock_cqs(send_cq, recv_cq);
1448
1449 spin_lock(&dev->qp_table.lock);
1450 mthca_array_clear(&dev->qp_table.qp,
1451 qp->qpn & (dev->limits.num_qps - 1));
1452 --qp->refcount;
1453 spin_unlock(&dev->qp_table.lock);
1454
1455 mthca_unlock_cqs(send_cq, recv_cq);
1456
1457 wait_event(qp->wait, !get_qp_refcount(dev, qp));
1458
1459 if (qp->state != IB_QPS_RESET)
1460 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0,
1461 NULL, 0, &status);
1462
1463 /*
1464 * If this is a userspace QP, the buffers, MR, CQs and so on
1465 * will be cleaned up in userspace, so all we have to do is
1466 * unref the mem-free tables and free the QPN in our table.
1467 */
1468 if (!qp->ibqp.uobject) {
1469 mthca_cq_clean(dev, recv_cq, qp->qpn,
1470 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1471 if (send_cq != recv_cq)
1472 mthca_cq_clean(dev, send_cq, qp->qpn, NULL);
1473
1474 mthca_free_memfree(dev, qp);
1475 mthca_free_wqe_buf(dev, qp);
1476 }
1477
1478 mthca_unmap_memfree(dev, qp);
1479
1480 if (is_sqp(dev, qp)) {
1481 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1482 dma_free_coherent(&dev->pdev->dev,
1483 to_msqp(qp)->header_buf_size,
1484 to_msqp(qp)->header_buf,
1485 to_msqp(qp)->header_dma);
1486 } else
1487 mthca_free(&dev->qp_table.alloc, qp->qpn);
1488 }
1489
1490 /* Create UD header for an MLX send and build a data segment for it */
build_mlx_header(struct mthca_dev * dev,struct mthca_sqp * sqp,int ind,struct ib_send_wr * wr,struct mthca_mlx_seg * mlx,struct mthca_data_seg * data)1491 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1492 int ind, struct ib_send_wr *wr,
1493 struct mthca_mlx_seg *mlx,
1494 struct mthca_data_seg *data)
1495 {
1496 int header_size;
1497 int err;
1498 u16 pkey;
1499
1500 ib_ud_header_init(256, /* assume a MAD */
1501 1, 0, 0,
1502 mthca_ah_grh_present(to_mah(wr->wr.ud.ah)),
1503 0,
1504 &sqp->ud_header);
1505
1506 err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1507 if (err)
1508 return err;
1509 mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1510 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1511 (sqp->ud_header.lrh.destination_lid ==
1512 IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1513 (sqp->ud_header.lrh.service_level << 8));
1514 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1515 mlx->vcrc = 0;
1516
1517 switch (wr->opcode) {
1518 case IB_WR_SEND:
1519 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1520 sqp->ud_header.immediate_present = 0;
1521 break;
1522 case IB_WR_SEND_WITH_IMM:
1523 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1524 sqp->ud_header.immediate_present = 1;
1525 sqp->ud_header.immediate_data = wr->ex.imm_data;
1526 break;
1527 default:
1528 return -EINVAL;
1529 }
1530
1531 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
1532 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1533 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1534 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1535 if (!sqp->qp.ibqp.qp_num)
1536 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1537 sqp->pkey_index, &pkey);
1538 else
1539 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1540 wr->wr.ud.pkey_index, &pkey);
1541 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1542 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1543 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1544 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1545 sqp->qkey : wr->wr.ud.remote_qkey);
1546 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1547
1548 header_size = ib_ud_header_pack(&sqp->ud_header,
1549 sqp->header_buf +
1550 ind * MTHCA_UD_HEADER_SIZE);
1551
1552 data->byte_count = cpu_to_be32(header_size);
1553 data->lkey = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1554 data->addr = cpu_to_be64(sqp->header_dma +
1555 ind * MTHCA_UD_HEADER_SIZE);
1556
1557 return 0;
1558 }
1559
mthca_wq_overflow(struct mthca_wq * wq,int nreq,struct ib_cq * ib_cq)1560 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1561 struct ib_cq *ib_cq)
1562 {
1563 unsigned cur;
1564 struct mthca_cq *cq;
1565
1566 cur = wq->head - wq->tail;
1567 if (likely(cur + nreq < wq->max))
1568 return 0;
1569
1570 cq = to_mcq(ib_cq);
1571 spin_lock(&cq->lock);
1572 cur = wq->head - wq->tail;
1573 spin_unlock(&cq->lock);
1574
1575 return cur + nreq >= wq->max;
1576 }
1577
set_raddr_seg(struct mthca_raddr_seg * rseg,u64 remote_addr,u32 rkey)1578 static __always_inline void set_raddr_seg(struct mthca_raddr_seg *rseg,
1579 u64 remote_addr, u32 rkey)
1580 {
1581 rseg->raddr = cpu_to_be64(remote_addr);
1582 rseg->rkey = cpu_to_be32(rkey);
1583 rseg->reserved = 0;
1584 }
1585
set_atomic_seg(struct mthca_atomic_seg * aseg,struct ib_send_wr * wr)1586 static __always_inline void set_atomic_seg(struct mthca_atomic_seg *aseg,
1587 struct ib_send_wr *wr)
1588 {
1589 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1590 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
1591 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
1592 } else {
1593 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1594 aseg->compare = 0;
1595 }
1596
1597 }
1598
set_tavor_ud_seg(struct mthca_tavor_ud_seg * useg,struct ib_send_wr * wr)1599 static void set_tavor_ud_seg(struct mthca_tavor_ud_seg *useg,
1600 struct ib_send_wr *wr)
1601 {
1602 useg->lkey = cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1603 useg->av_addr = cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1604 useg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1605 useg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1606
1607 }
1608
set_arbel_ud_seg(struct mthca_arbel_ud_seg * useg,struct ib_send_wr * wr)1609 static void set_arbel_ud_seg(struct mthca_arbel_ud_seg *useg,
1610 struct ib_send_wr *wr)
1611 {
1612 memcpy(useg->av, to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1613 useg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1614 useg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1615 }
1616
mthca_tavor_post_send(struct ib_qp * ibqp,struct ib_send_wr * wr,struct ib_send_wr ** bad_wr)1617 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1618 struct ib_send_wr **bad_wr)
1619 {
1620 struct mthca_dev *dev = to_mdev(ibqp->device);
1621 struct mthca_qp *qp = to_mqp(ibqp);
1622 void *wqe;
1623 void *prev_wqe;
1624 unsigned long flags;
1625 int err = 0;
1626 int nreq;
1627 int i;
1628 int size;
1629 /*
1630 * f0 and size0 are only used if nreq != 0, and they will
1631 * always be initialized the first time through the main loop
1632 * before nreq is incremented. So nreq cannot become non-zero
1633 * without initializing f0 and size0, and they are in fact
1634 * never used uninitialized.
1635 */
1636 int uninitialized_var(size0);
1637 u32 uninitialized_var(f0);
1638 int ind;
1639 u8 op0 = 0;
1640
1641 spin_lock_irqsave(&qp->sq.lock, flags);
1642
1643 /* XXX check that state is OK to post send */
1644
1645 ind = qp->sq.next_ind;
1646
1647 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1648 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1649 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1650 " %d max, %d nreq)\n", qp->qpn,
1651 qp->sq.head, qp->sq.tail,
1652 qp->sq.max, nreq);
1653 err = -ENOMEM;
1654 *bad_wr = wr;
1655 goto out;
1656 }
1657
1658 wqe = get_send_wqe(qp, ind);
1659 prev_wqe = qp->sq.last;
1660 qp->sq.last = wqe;
1661
1662 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1663 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1664 ((struct mthca_next_seg *) wqe)->flags =
1665 ((wr->send_flags & IB_SEND_SIGNALED) ?
1666 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1667 ((wr->send_flags & IB_SEND_SOLICITED) ?
1668 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
1669 cpu_to_be32(1);
1670 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1671 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1672 ((struct mthca_next_seg *) wqe)->imm = wr->ex.imm_data;
1673
1674 wqe += sizeof (struct mthca_next_seg);
1675 size = sizeof (struct mthca_next_seg) / 16;
1676
1677 switch (qp->transport) {
1678 case RC:
1679 switch (wr->opcode) {
1680 case IB_WR_ATOMIC_CMP_AND_SWP:
1681 case IB_WR_ATOMIC_FETCH_AND_ADD:
1682 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
1683 wr->wr.atomic.rkey);
1684 wqe += sizeof (struct mthca_raddr_seg);
1685
1686 set_atomic_seg(wqe, wr);
1687 wqe += sizeof (struct mthca_atomic_seg);
1688 size += (sizeof (struct mthca_raddr_seg) +
1689 sizeof (struct mthca_atomic_seg)) / 16;
1690 break;
1691
1692 case IB_WR_RDMA_WRITE:
1693 case IB_WR_RDMA_WRITE_WITH_IMM:
1694 case IB_WR_RDMA_READ:
1695 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
1696 wr->wr.rdma.rkey);
1697 wqe += sizeof (struct mthca_raddr_seg);
1698 size += sizeof (struct mthca_raddr_seg) / 16;
1699 break;
1700
1701 default:
1702 /* No extra segments required for sends */
1703 break;
1704 }
1705
1706 break;
1707
1708 case UC:
1709 switch (wr->opcode) {
1710 case IB_WR_RDMA_WRITE:
1711 case IB_WR_RDMA_WRITE_WITH_IMM:
1712 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
1713 wr->wr.rdma.rkey);
1714 wqe += sizeof (struct mthca_raddr_seg);
1715 size += sizeof (struct mthca_raddr_seg) / 16;
1716 break;
1717
1718 default:
1719 /* No extra segments required for sends */
1720 break;
1721 }
1722
1723 break;
1724
1725 case UD:
1726 set_tavor_ud_seg(wqe, wr);
1727 wqe += sizeof (struct mthca_tavor_ud_seg);
1728 size += sizeof (struct mthca_tavor_ud_seg) / 16;
1729 break;
1730
1731 case MLX:
1732 err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1733 wqe - sizeof (struct mthca_next_seg),
1734 wqe);
1735 if (err) {
1736 *bad_wr = wr;
1737 goto out;
1738 }
1739 wqe += sizeof (struct mthca_data_seg);
1740 size += sizeof (struct mthca_data_seg) / 16;
1741 break;
1742 }
1743
1744 if (wr->num_sge > qp->sq.max_gs) {
1745 mthca_err(dev, "too many gathers\n");
1746 err = -EINVAL;
1747 *bad_wr = wr;
1748 goto out;
1749 }
1750
1751 for (i = 0; i < wr->num_sge; ++i) {
1752 mthca_set_data_seg(wqe, wr->sg_list + i);
1753 wqe += sizeof (struct mthca_data_seg);
1754 size += sizeof (struct mthca_data_seg) / 16;
1755 }
1756
1757 /* Add one more inline data segment for ICRC */
1758 if (qp->transport == MLX) {
1759 ((struct mthca_data_seg *) wqe)->byte_count =
1760 cpu_to_be32((1U << 31) | 4);
1761 ((u32 *) wqe)[1] = 0;
1762 wqe += sizeof (struct mthca_data_seg);
1763 size += sizeof (struct mthca_data_seg) / 16;
1764 }
1765
1766 qp->wrid[ind] = wr->wr_id;
1767
1768 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1769 mthca_err(dev, "opcode invalid\n");
1770 err = -EINVAL;
1771 *bad_wr = wr;
1772 goto out;
1773 }
1774
1775 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1776 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1777 qp->send_wqe_offset) |
1778 mthca_opcode[wr->opcode]);
1779 wmb();
1780 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1781 cpu_to_be32((nreq ? 0 : MTHCA_NEXT_DBD) | size |
1782 ((wr->send_flags & IB_SEND_FENCE) ?
1783 MTHCA_NEXT_FENCE : 0));
1784
1785 if (!nreq) {
1786 size0 = size;
1787 op0 = mthca_opcode[wr->opcode];
1788 f0 = wr->send_flags & IB_SEND_FENCE ?
1789 MTHCA_SEND_DOORBELL_FENCE : 0;
1790 }
1791
1792 ++ind;
1793 if (unlikely(ind >= qp->sq.max))
1794 ind -= qp->sq.max;
1795 }
1796
1797 out:
1798 if (likely(nreq)) {
1799 wmb();
1800
1801 mthca_write64(((qp->sq.next_ind << qp->sq.wqe_shift) +
1802 qp->send_wqe_offset) | f0 | op0,
1803 (qp->qpn << 8) | size0,
1804 dev->kar + MTHCA_SEND_DOORBELL,
1805 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1806 /*
1807 * Make sure doorbells don't leak out of SQ spinlock
1808 * and reach the HCA out of order:
1809 */
1810 mmiowb();
1811 }
1812
1813 qp->sq.next_ind = ind;
1814 qp->sq.head += nreq;
1815
1816 spin_unlock_irqrestore(&qp->sq.lock, flags);
1817 return err;
1818 }
1819
mthca_tavor_post_receive(struct ib_qp * ibqp,struct ib_recv_wr * wr,struct ib_recv_wr ** bad_wr)1820 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1821 struct ib_recv_wr **bad_wr)
1822 {
1823 struct mthca_dev *dev = to_mdev(ibqp->device);
1824 struct mthca_qp *qp = to_mqp(ibqp);
1825 unsigned long flags;
1826 int err = 0;
1827 int nreq;
1828 int i;
1829 int size;
1830 /*
1831 * size0 is only used if nreq != 0, and it will always be
1832 * initialized the first time through the main loop before
1833 * nreq is incremented. So nreq cannot become non-zero
1834 * without initializing size0, and it is in fact never used
1835 * uninitialized.
1836 */
1837 int uninitialized_var(size0);
1838 int ind;
1839 void *wqe;
1840 void *prev_wqe;
1841
1842 spin_lock_irqsave(&qp->rq.lock, flags);
1843
1844 /* XXX check that state is OK to post receive */
1845
1846 ind = qp->rq.next_ind;
1847
1848 for (nreq = 0; wr; wr = wr->next) {
1849 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1850 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1851 " %d max, %d nreq)\n", qp->qpn,
1852 qp->rq.head, qp->rq.tail,
1853 qp->rq.max, nreq);
1854 err = -ENOMEM;
1855 *bad_wr = wr;
1856 goto out;
1857 }
1858
1859 wqe = get_recv_wqe(qp, ind);
1860 prev_wqe = qp->rq.last;
1861 qp->rq.last = wqe;
1862
1863 ((struct mthca_next_seg *) wqe)->ee_nds =
1864 cpu_to_be32(MTHCA_NEXT_DBD);
1865 ((struct mthca_next_seg *) wqe)->flags = 0;
1866
1867 wqe += sizeof (struct mthca_next_seg);
1868 size = sizeof (struct mthca_next_seg) / 16;
1869
1870 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1871 err = -EINVAL;
1872 *bad_wr = wr;
1873 goto out;
1874 }
1875
1876 for (i = 0; i < wr->num_sge; ++i) {
1877 mthca_set_data_seg(wqe, wr->sg_list + i);
1878 wqe += sizeof (struct mthca_data_seg);
1879 size += sizeof (struct mthca_data_seg) / 16;
1880 }
1881
1882 qp->wrid[ind + qp->sq.max] = wr->wr_id;
1883
1884 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1885 cpu_to_be32(MTHCA_NEXT_DBD | size);
1886
1887 if (!nreq)
1888 size0 = size;
1889
1890 ++ind;
1891 if (unlikely(ind >= qp->rq.max))
1892 ind -= qp->rq.max;
1893
1894 ++nreq;
1895 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1896 nreq = 0;
1897
1898 wmb();
1899
1900 mthca_write64((qp->rq.next_ind << qp->rq.wqe_shift) | size0,
1901 qp->qpn << 8, dev->kar + MTHCA_RECEIVE_DOORBELL,
1902 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1903
1904 qp->rq.next_ind = ind;
1905 qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1906 }
1907 }
1908
1909 out:
1910 if (likely(nreq)) {
1911 wmb();
1912
1913 mthca_write64((qp->rq.next_ind << qp->rq.wqe_shift) | size0,
1914 qp->qpn << 8 | nreq, dev->kar + MTHCA_RECEIVE_DOORBELL,
1915 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1916 }
1917
1918 qp->rq.next_ind = ind;
1919 qp->rq.head += nreq;
1920
1921 /*
1922 * Make sure doorbells don't leak out of RQ spinlock and reach
1923 * the HCA out of order:
1924 */
1925 mmiowb();
1926
1927 spin_unlock_irqrestore(&qp->rq.lock, flags);
1928 return err;
1929 }
1930
mthca_arbel_post_send(struct ib_qp * ibqp,struct ib_send_wr * wr,struct ib_send_wr ** bad_wr)1931 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1932 struct ib_send_wr **bad_wr)
1933 {
1934 struct mthca_dev *dev = to_mdev(ibqp->device);
1935 struct mthca_qp *qp = to_mqp(ibqp);
1936 u32 dbhi;
1937 void *wqe;
1938 void *prev_wqe;
1939 unsigned long flags;
1940 int err = 0;
1941 int nreq;
1942 int i;
1943 int size;
1944 /*
1945 * f0 and size0 are only used if nreq != 0, and they will
1946 * always be initialized the first time through the main loop
1947 * before nreq is incremented. So nreq cannot become non-zero
1948 * without initializing f0 and size0, and they are in fact
1949 * never used uninitialized.
1950 */
1951 int uninitialized_var(size0);
1952 u32 uninitialized_var(f0);
1953 int ind;
1954 u8 op0 = 0;
1955
1956 spin_lock_irqsave(&qp->sq.lock, flags);
1957
1958 /* XXX check that state is OK to post send */
1959
1960 ind = qp->sq.head & (qp->sq.max - 1);
1961
1962 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1963 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1964 nreq = 0;
1965
1966 dbhi = (MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1967 ((qp->sq.head & 0xffff) << 8) | f0 | op0;
1968
1969 qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1970
1971 /*
1972 * Make sure that descriptors are written before
1973 * doorbell record.
1974 */
1975 wmb();
1976 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1977
1978 /*
1979 * Make sure doorbell record is written before we
1980 * write MMIO send doorbell.
1981 */
1982 wmb();
1983
1984 mthca_write64(dbhi, (qp->qpn << 8) | size0,
1985 dev->kar + MTHCA_SEND_DOORBELL,
1986 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1987 }
1988
1989 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1990 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1991 " %d max, %d nreq)\n", qp->qpn,
1992 qp->sq.head, qp->sq.tail,
1993 qp->sq.max, nreq);
1994 err = -ENOMEM;
1995 *bad_wr = wr;
1996 goto out;
1997 }
1998
1999 wqe = get_send_wqe(qp, ind);
2000 prev_wqe = qp->sq.last;
2001 qp->sq.last = wqe;
2002
2003 ((struct mthca_next_seg *) wqe)->flags =
2004 ((wr->send_flags & IB_SEND_SIGNALED) ?
2005 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
2006 ((wr->send_flags & IB_SEND_SOLICITED) ?
2007 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
2008 ((wr->send_flags & IB_SEND_IP_CSUM) ?
2009 cpu_to_be32(MTHCA_NEXT_IP_CSUM | MTHCA_NEXT_TCP_UDP_CSUM) : 0) |
2010 cpu_to_be32(1);
2011 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
2012 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
2013 ((struct mthca_next_seg *) wqe)->imm = wr->ex.imm_data;
2014
2015 wqe += sizeof (struct mthca_next_seg);
2016 size = sizeof (struct mthca_next_seg) / 16;
2017
2018 switch (qp->transport) {
2019 case RC:
2020 switch (wr->opcode) {
2021 case IB_WR_ATOMIC_CMP_AND_SWP:
2022 case IB_WR_ATOMIC_FETCH_AND_ADD:
2023 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2024 wr->wr.atomic.rkey);
2025 wqe += sizeof (struct mthca_raddr_seg);
2026
2027 set_atomic_seg(wqe, wr);
2028 wqe += sizeof (struct mthca_atomic_seg);
2029 size += (sizeof (struct mthca_raddr_seg) +
2030 sizeof (struct mthca_atomic_seg)) / 16;
2031 break;
2032
2033 case IB_WR_RDMA_READ:
2034 case IB_WR_RDMA_WRITE:
2035 case IB_WR_RDMA_WRITE_WITH_IMM:
2036 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
2037 wr->wr.rdma.rkey);
2038 wqe += sizeof (struct mthca_raddr_seg);
2039 size += sizeof (struct mthca_raddr_seg) / 16;
2040 break;
2041
2042 default:
2043 /* No extra segments required for sends */
2044 break;
2045 }
2046
2047 break;
2048
2049 case UC:
2050 switch (wr->opcode) {
2051 case IB_WR_RDMA_WRITE:
2052 case IB_WR_RDMA_WRITE_WITH_IMM:
2053 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
2054 wr->wr.rdma.rkey);
2055 wqe += sizeof (struct mthca_raddr_seg);
2056 size += sizeof (struct mthca_raddr_seg) / 16;
2057 break;
2058
2059 default:
2060 /* No extra segments required for sends */
2061 break;
2062 }
2063
2064 break;
2065
2066 case UD:
2067 set_arbel_ud_seg(wqe, wr);
2068 wqe += sizeof (struct mthca_arbel_ud_seg);
2069 size += sizeof (struct mthca_arbel_ud_seg) / 16;
2070 break;
2071
2072 case MLX:
2073 err = build_mlx_header(dev, to_msqp(qp), ind, wr,
2074 wqe - sizeof (struct mthca_next_seg),
2075 wqe);
2076 if (err) {
2077 *bad_wr = wr;
2078 goto out;
2079 }
2080 wqe += sizeof (struct mthca_data_seg);
2081 size += sizeof (struct mthca_data_seg) / 16;
2082 break;
2083 }
2084
2085 if (wr->num_sge > qp->sq.max_gs) {
2086 mthca_err(dev, "too many gathers\n");
2087 err = -EINVAL;
2088 *bad_wr = wr;
2089 goto out;
2090 }
2091
2092 for (i = 0; i < wr->num_sge; ++i) {
2093 mthca_set_data_seg(wqe, wr->sg_list + i);
2094 wqe += sizeof (struct mthca_data_seg);
2095 size += sizeof (struct mthca_data_seg) / 16;
2096 }
2097
2098 /* Add one more inline data segment for ICRC */
2099 if (qp->transport == MLX) {
2100 ((struct mthca_data_seg *) wqe)->byte_count =
2101 cpu_to_be32((1U << 31) | 4);
2102 ((u32 *) wqe)[1] = 0;
2103 wqe += sizeof (struct mthca_data_seg);
2104 size += sizeof (struct mthca_data_seg) / 16;
2105 }
2106
2107 qp->wrid[ind] = wr->wr_id;
2108
2109 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2110 mthca_err(dev, "opcode invalid\n");
2111 err = -EINVAL;
2112 *bad_wr = wr;
2113 goto out;
2114 }
2115
2116 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2117 cpu_to_be32(((ind << qp->sq.wqe_shift) +
2118 qp->send_wqe_offset) |
2119 mthca_opcode[wr->opcode]);
2120 wmb();
2121 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2122 cpu_to_be32(MTHCA_NEXT_DBD | size |
2123 ((wr->send_flags & IB_SEND_FENCE) ?
2124 MTHCA_NEXT_FENCE : 0));
2125
2126 if (!nreq) {
2127 size0 = size;
2128 op0 = mthca_opcode[wr->opcode];
2129 f0 = wr->send_flags & IB_SEND_FENCE ?
2130 MTHCA_SEND_DOORBELL_FENCE : 0;
2131 }
2132
2133 ++ind;
2134 if (unlikely(ind >= qp->sq.max))
2135 ind -= qp->sq.max;
2136 }
2137
2138 out:
2139 if (likely(nreq)) {
2140 dbhi = (nreq << 24) | ((qp->sq.head & 0xffff) << 8) | f0 | op0;
2141
2142 qp->sq.head += nreq;
2143
2144 /*
2145 * Make sure that descriptors are written before
2146 * doorbell record.
2147 */
2148 wmb();
2149 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2150
2151 /*
2152 * Make sure doorbell record is written before we
2153 * write MMIO send doorbell.
2154 */
2155 wmb();
2156
2157 mthca_write64(dbhi, (qp->qpn << 8) | size0, dev->kar + MTHCA_SEND_DOORBELL,
2158 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2159 }
2160
2161 /*
2162 * Make sure doorbells don't leak out of SQ spinlock and reach
2163 * the HCA out of order:
2164 */
2165 mmiowb();
2166
2167 spin_unlock_irqrestore(&qp->sq.lock, flags);
2168 return err;
2169 }
2170
mthca_arbel_post_receive(struct ib_qp * ibqp,struct ib_recv_wr * wr,struct ib_recv_wr ** bad_wr)2171 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2172 struct ib_recv_wr **bad_wr)
2173 {
2174 struct mthca_dev *dev = to_mdev(ibqp->device);
2175 struct mthca_qp *qp = to_mqp(ibqp);
2176 unsigned long flags;
2177 int err = 0;
2178 int nreq;
2179 int ind;
2180 int i;
2181 void *wqe;
2182
2183 spin_lock_irqsave(&qp->rq.lock, flags);
2184
2185 /* XXX check that state is OK to post receive */
2186
2187 ind = qp->rq.head & (qp->rq.max - 1);
2188
2189 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2190 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2191 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2192 " %d max, %d nreq)\n", qp->qpn,
2193 qp->rq.head, qp->rq.tail,
2194 qp->rq.max, nreq);
2195 err = -ENOMEM;
2196 *bad_wr = wr;
2197 goto out;
2198 }
2199
2200 wqe = get_recv_wqe(qp, ind);
2201
2202 ((struct mthca_next_seg *) wqe)->flags = 0;
2203
2204 wqe += sizeof (struct mthca_next_seg);
2205
2206 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2207 err = -EINVAL;
2208 *bad_wr = wr;
2209 goto out;
2210 }
2211
2212 for (i = 0; i < wr->num_sge; ++i) {
2213 mthca_set_data_seg(wqe, wr->sg_list + i);
2214 wqe += sizeof (struct mthca_data_seg);
2215 }
2216
2217 if (i < qp->rq.max_gs)
2218 mthca_set_data_seg_inval(wqe);
2219
2220 qp->wrid[ind + qp->sq.max] = wr->wr_id;
2221
2222 ++ind;
2223 if (unlikely(ind >= qp->rq.max))
2224 ind -= qp->rq.max;
2225 }
2226 out:
2227 if (likely(nreq)) {
2228 qp->rq.head += nreq;
2229
2230 /*
2231 * Make sure that descriptors are written before
2232 * doorbell record.
2233 */
2234 wmb();
2235 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2236 }
2237
2238 spin_unlock_irqrestore(&qp->rq.lock, flags);
2239 return err;
2240 }
2241
mthca_free_err_wqe(struct mthca_dev * dev,struct mthca_qp * qp,int is_send,int index,int * dbd,__be32 * new_wqe)2242 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2243 int index, int *dbd, __be32 *new_wqe)
2244 {
2245 struct mthca_next_seg *next;
2246
2247 /*
2248 * For SRQs, all receive WQEs generate a CQE, so we're always
2249 * at the end of the doorbell chain.
2250 */
2251 if (qp->ibqp.srq && !is_send) {
2252 *new_wqe = 0;
2253 return;
2254 }
2255
2256 if (is_send)
2257 next = get_send_wqe(qp, index);
2258 else
2259 next = get_recv_wqe(qp, index);
2260
2261 *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2262 if (next->ee_nds & cpu_to_be32(0x3f))
2263 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2264 (next->ee_nds & cpu_to_be32(0x3f));
2265 else
2266 *new_wqe = 0;
2267 }
2268
mthca_init_qp_table(struct mthca_dev * dev)2269 int mthca_init_qp_table(struct mthca_dev *dev)
2270 {
2271 int err;
2272 u8 status;
2273 int i;
2274
2275 spin_lock_init(&dev->qp_table.lock);
2276
2277 /*
2278 * We reserve 2 extra QPs per port for the special QPs. The
2279 * special QP for port 1 has to be even, so round up.
2280 */
2281 dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2282 err = mthca_alloc_init(&dev->qp_table.alloc,
2283 dev->limits.num_qps,
2284 (1 << 24) - 1,
2285 dev->qp_table.sqp_start +
2286 MTHCA_MAX_PORTS * 2);
2287 if (err)
2288 return err;
2289
2290 err = mthca_array_init(&dev->qp_table.qp,
2291 dev->limits.num_qps);
2292 if (err) {
2293 mthca_alloc_cleanup(&dev->qp_table.alloc);
2294 return err;
2295 }
2296
2297 for (i = 0; i < 2; ++i) {
2298 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2299 dev->qp_table.sqp_start + i * 2,
2300 &status);
2301 if (err)
2302 goto err_out;
2303 if (status) {
2304 mthca_warn(dev, "CONF_SPECIAL_QP returned "
2305 "status %02x, aborting.\n",
2306 status);
2307 err = -EINVAL;
2308 goto err_out;
2309 }
2310 }
2311 return 0;
2312
2313 err_out:
2314 for (i = 0; i < 2; ++i)
2315 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2316
2317 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2318 mthca_alloc_cleanup(&dev->qp_table.alloc);
2319
2320 return err;
2321 }
2322
mthca_cleanup_qp_table(struct mthca_dev * dev)2323 void mthca_cleanup_qp_table(struct mthca_dev *dev)
2324 {
2325 int i;
2326 u8 status;
2327
2328 for (i = 0; i < 2; ++i)
2329 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2330
2331 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2332 mthca_alloc_cleanup(&dev->qp_table.alloc);
2333 }
2334