1 /*-
2 * Copyright (C) 2008 Semihalf, Rafal Jaworowski
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include "opt_platform.h"
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/lock.h>
34 #include <sys/mutex.h>
35 #include <sys/reboot.h>
36 #include <sys/rman.h>
37
38 #include <vm/vm.h>
39 #include <vm/vm_param.h>
40 #include <vm/pmap.h>
41
42 #include <machine/cpu.h>
43 #include <machine/cpufunc.h>
44 #include <machine/machdep.h>
45 #include <machine/pio.h>
46 #include <machine/spr.h>
47
48 #include <dev/fdt/fdt_common.h>
49
50 #include <dev/fdt/fdt_common.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
53 #include <dev/ofw/openfirm.h>
54
55 #include <powerpc/mpc85xx/mpc85xx.h>
56
57
58 /*
59 * MPC85xx system specific routines
60 */
61
62 uint32_t
ccsr_read4(uintptr_t addr)63 ccsr_read4(uintptr_t addr)
64 {
65 volatile uint32_t *ptr = (void *)addr;
66
67 return (*ptr);
68 }
69
70 void
ccsr_write4(uintptr_t addr,uint32_t val)71 ccsr_write4(uintptr_t addr, uint32_t val)
72 {
73 volatile uint32_t *ptr = (void *)addr;
74
75 *ptr = val;
76 powerpc_iomb();
77 }
78
79 int
law_getmax(void)80 law_getmax(void)
81 {
82 uint32_t ver;
83 int law_max;
84
85 ver = SVR_VER(mfspr(SPR_SVR));
86 switch (ver) {
87 case SVR_MPC8555:
88 case SVR_MPC8555E:
89 law_max = 8;
90 break;
91 case SVR_MPC8533:
92 case SVR_MPC8533E:
93 case SVR_MPC8548:
94 case SVR_MPC8548E:
95 law_max = 10;
96 break;
97 case SVR_P5020:
98 case SVR_P5020E:
99 law_max = 32;
100 break;
101 default:
102 law_max = 8;
103 }
104
105 return (law_max);
106 }
107
108 static inline void
law_write(uint32_t n,uint64_t bar,uint32_t sr)109 law_write(uint32_t n, uint64_t bar, uint32_t sr)
110 {
111 #if defined(QORIQ_DPAA)
112 ccsr_write4(OCP85XX_LAWBARH(n), bar >> 32);
113 ccsr_write4(OCP85XX_LAWBARL(n), bar);
114 #else
115 ccsr_write4(OCP85XX_LAWBAR(n), bar >> 12);
116 #endif
117 ccsr_write4(OCP85XX_LAWSR(n), sr);
118
119 /*
120 * The last write to LAWAR should be followed by a read
121 * of LAWAR before any device try to use any of windows.
122 * What more the read of LAWAR should be followed by isync
123 * instruction.
124 */
125
126 ccsr_read4(OCP85XX_LAWSR(n));
127 isync();
128 }
129
130 static inline void
law_read(uint32_t n,uint64_t * bar,uint32_t * sr)131 law_read(uint32_t n, uint64_t *bar, uint32_t *sr)
132 {
133 #if defined(QORIQ_DPAA)
134 *bar = (uint64_t)ccsr_read4(OCP85XX_LAWBARH(n)) << 32 |
135 ccsr_read4(OCP85XX_LAWBARL(n));
136 #else
137 *bar = (uint64_t)ccsr_read4(OCP85XX_LAWBAR(n)) << 12;
138 #endif
139 *sr = ccsr_read4(OCP85XX_LAWSR(n));
140 }
141
142 static int
law_find_free(void)143 law_find_free(void)
144 {
145 uint32_t i,sr;
146 uint64_t bar;
147 int law_max;
148
149 law_max = law_getmax();
150 /* Find free LAW */
151 for (i = 0; i < law_max; i++) {
152 law_read(i, &bar, &sr);
153 if ((sr & 0x80000000) == 0)
154 break;
155 }
156
157 return (i);
158 }
159
160 #define _LAW_SR(trgt,size) (0x80000000 | (trgt << 20) | (ffsl(size) - 2))
161
162 int
law_enable(int trgt,uint64_t bar,uint32_t size)163 law_enable(int trgt, uint64_t bar, uint32_t size)
164 {
165 uint64_t bar_tmp;
166 uint32_t sr, sr_tmp;
167 int i, law_max;
168
169 if (size == 0)
170 return (0);
171
172 law_max = law_getmax();
173 sr = _LAW_SR(trgt, size);
174
175 /* Bail if already programmed. */
176 for (i = 0; i < law_max; i++) {
177 law_read(i, &bar_tmp, &sr_tmp);
178 if (sr == sr_tmp && bar == bar_tmp)
179 return (0);
180 }
181
182 /* Find an unused access window. */
183 i = law_find_free();
184
185 if (i == law_max)
186 return (ENOSPC);
187
188 law_write(i, bar, sr);
189 return (0);
190 }
191
192 int
law_disable(int trgt,uint64_t bar,uint32_t size)193 law_disable(int trgt, uint64_t bar, uint32_t size)
194 {
195 uint64_t bar_tmp;
196 uint32_t sr, sr_tmp;
197 int i, law_max;
198
199 law_max = law_getmax();
200 sr = _LAW_SR(trgt, size);
201
202 /* Find and disable requested LAW. */
203 for (i = 0; i < law_max; i++) {
204 law_read(i, &bar_tmp, &sr_tmp);
205 if (sr == sr_tmp && bar == bar_tmp) {
206 law_write(i, 0, 0);
207 return (0);
208 }
209 }
210
211 return (ENOENT);
212 }
213
214 int
law_pci_target(struct resource * res,int * trgt_mem,int * trgt_io)215 law_pci_target(struct resource *res, int *trgt_mem, int *trgt_io)
216 {
217 u_long start;
218 uint32_t ver;
219 int trgt, rv;
220
221 ver = SVR_VER(mfspr(SPR_SVR));
222
223 start = rman_get_start(res) & 0xf000;
224
225 rv = 0;
226 trgt = -1;
227 switch (start) {
228 case 0x0000:
229 case 0x8000:
230 trgt = 0;
231 break;
232 case 0x1000:
233 case 0x9000:
234 trgt = 1;
235 break;
236 case 0x2000:
237 case 0xa000:
238 if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
239 trgt = 3;
240 else
241 trgt = 2;
242 break;
243 case 0x3000:
244 case 0xb000:
245 if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
246 rv = EINVAL;
247 else
248 trgt = 3;
249 break;
250 default:
251 rv = ENXIO;
252 }
253 if (rv == 0) {
254 *trgt_mem = trgt;
255 *trgt_io = trgt;
256 }
257 return (rv);
258 }
259
260 static void
l3cache_inval(void)261 l3cache_inval(void)
262 {
263
264 /* Flash invalidate the CPC and clear all the locks */
265 ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_FI |
266 OCP85XX_CPC_CSR0_LFC);
267 while (ccsr_read4(OCP85XX_CPC_CSR0) & (OCP85XX_CPC_CSR0_FI |
268 OCP85XX_CPC_CSR0_LFC))
269 ;
270 }
271
272 static void
l3cache_enable(void)273 l3cache_enable(void)
274 {
275
276 ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_CE |
277 OCP85XX_CPC_CSR0_PE);
278 /* Read back to sync write */
279 ccsr_read4(OCP85XX_CPC_CSR0);
280 }
281
282 void
mpc85xx_enable_l3_cache(void)283 mpc85xx_enable_l3_cache(void)
284 {
285 uint32_t csr, size, ver;
286
287 /* Enable L3 CoreNet Platform Cache (CPC) */
288 ver = SVR_VER(mfspr(SPR_SVR));
289 if (ver == SVR_P2041 || ver == SVR_P2041E || ver == SVR_P3041 ||
290 ver == SVR_P3041E || ver == SVR_P5020 || ver == SVR_P5020E) {
291 csr = ccsr_read4(OCP85XX_CPC_CSR0);
292 if ((csr & OCP85XX_CPC_CSR0_CE) == 0) {
293 l3cache_inval();
294 l3cache_enable();
295 }
296
297 csr = ccsr_read4(OCP85XX_CPC_CSR0);
298 if ((boothowto & RB_VERBOSE) != 0 ||
299 (csr & OCP85XX_CPC_CSR0_CE) == 0) {
300 size = OCP85XX_CPC_CFG0_SZ_K(ccsr_read4(OCP85XX_CPC_CFG0));
301 printf("L3 Corenet Platform Cache: %d KB %sabled\n",
302 size, (csr & OCP85XX_CPC_CSR0_CE) == 0 ?
303 "dis" : "en");
304 }
305 }
306 }
307
308 static void
mpc85xx_dataloss_erratum_spr976(void)309 mpc85xx_dataloss_erratum_spr976(void)
310 {
311 uint32_t svr = SVR_VER(mfspr(SPR_SVR));
312
313 /* Ignore whether it's the E variant */
314 svr &= ~0x8;
315
316 if (svr != SVR_P3041 && svr != SVR_P4040 &&
317 svr != SVR_P4080 && svr != SVR_P5020)
318 return;
319
320 mb();
321 isync();
322 mtspr(976, (mfspr(976) & ~0x1f8) | 0x48);
323 isync();
324 }
325
326 static vm_offset_t
mpc85xx_map_dcsr(void)327 mpc85xx_map_dcsr(void)
328 {
329 phandle_t node;
330 u_long b, s;
331 int err;
332
333 /*
334 * Try to access the dcsr node directly i.e. through /aliases/.
335 */
336 if ((node = OF_finddevice("dcsr")) != -1)
337 if (fdt_is_compatible_strict(node, "fsl,dcsr"))
338 goto moveon;
339 /*
340 * Find the node the long way.
341 */
342 if ((node = OF_finddevice("/")) == -1)
343 return (ENXIO);
344
345 if ((node = ofw_bus_find_compatible(node, "fsl,dcsr")) == 0)
346 return (ENXIO);
347
348 moveon:
349 err = fdt_get_range(node, 0, &b, &s);
350
351 if (err != 0)
352 return (err);
353
354 #ifdef QORIQ_DPAA
355 law_enable(OCP85XX_TGTIF_DCSR, b, 0x400000);
356 #endif
357 return pmap_early_io_map(b, 0x400000);
358 }
359
360
361
362 void
mpc85xx_fix_errata(vm_offset_t va_ccsr)363 mpc85xx_fix_errata(vm_offset_t va_ccsr)
364 {
365 uint32_t svr = SVR_VER(mfspr(SPR_SVR));
366 vm_offset_t va_dcsr;
367
368 /* Ignore whether it's the E variant */
369 svr &= ~0x8;
370
371 if (svr != SVR_P3041 && svr != SVR_P4040 &&
372 svr != SVR_P4080 && svr != SVR_P5020)
373 return;
374
375 if (mfmsr() & PSL_EE)
376 return;
377
378 /*
379 * dcsr region need to be mapped thus patch can refer to.
380 * Align dcsr right after ccsbar.
381 */
382 va_dcsr = mpc85xx_map_dcsr();
383 if (va_dcsr == 0)
384 goto err;
385
386 /*
387 * As A004510 errata specify, special purpose register 976
388 * SPR976[56:60] = 6'b001001 must be set. e500mc core reference manual
389 * does not document SPR976 register.
390 */
391 mpc85xx_dataloss_erratum_spr976();
392
393 /*
394 * Specific settings in the CCF and core platform cache (CPC)
395 * are required to reconfigure the CoreNet coherency fabric.
396 * The register settings that should be updated are described
397 * in errata and relay on base address, offset and updated value.
398 * Special conditions must be used to update these registers correctly.
399 */
400 dataloss_erratum_access(va_dcsr + 0xb0e08, 0xe0201800);
401 dataloss_erratum_access(va_dcsr + 0xb0e18, 0xe0201800);
402 dataloss_erratum_access(va_dcsr + 0xb0e38, 0xe0400000);
403 dataloss_erratum_access(va_dcsr + 0xb0008, 0x00900000);
404 dataloss_erratum_access(va_dcsr + 0xb0e40, 0xe00a0000);
405
406 switch (svr) {
407 case SVR_P5020:
408 dataloss_erratum_access(va_ccsr + 0x18600, 0xc0000000);
409 break;
410 case SVR_P4040:
411 case SVR_P4080:
412 dataloss_erratum_access(va_ccsr + 0x18600, 0xff000000);
413 break;
414 case SVR_P3041:
415 dataloss_erratum_access(va_ccsr + 0x18600, 0xf0000000);
416 }
417 dataloss_erratum_access(va_ccsr + 0x10f00, 0x415e5000);
418 dataloss_erratum_access(va_ccsr + 0x11f00, 0x415e5000);
419
420 err:
421 return;
422 }
423