1 /*-
2 * Copyright (c) 2010 Isilon Systems, Inc.
3 * Copyright (c) 2010 iX Systems, Inc.
4 * Copyright (c) 2010 Panasas, Inc.
5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd.
6 * All rights reserved.
7 * Copyright (c) 2020-2022 The FreeBSD Foundation
8 *
9 * Portions of this software were developed by Björn Zeeb
10 * under sponsorship from the FreeBSD Foundation.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice unmodified, this list of conditions, and the following
17 * disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33 #ifndef _LINUXKPI_LINUX_PCI_H_
34 #define _LINUXKPI_LINUX_PCI_H_
35
36 #define CONFIG_PCI_MSI
37
38 #include <linux/types.h>
39
40 #include <sys/param.h>
41 #include <sys/bus.h>
42 #include <sys/module.h>
43 #include <sys/nv.h>
44 #include <sys/pciio.h>
45 #include <sys/rman.h>
46 #include <dev/pci/pcivar.h>
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pci_private.h>
49
50 #include <machine/resource.h>
51
52 #include <linux/list.h>
53 #include <linux/dmapool.h>
54 #include <linux/dma-mapping.h>
55 #include <linux/compiler.h>
56 #include <linux/errno.h>
57 #include <asm/atomic.h>
58 #include <linux/device.h>
59 #include <linux/pci_ids.h>
60 #include <linux/pm.h>
61
62 struct pci_device_id {
63 uint32_t vendor;
64 uint32_t device;
65 uint32_t subvendor;
66 uint32_t subdevice;
67 uint32_t class;
68 uint32_t class_mask;
69 uintptr_t driver_data;
70 };
71
72 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */
73 #define MODULE_DEVICE_TABLE(_bus, _table) \
74 \
75 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \
76 DEVMETHOD_END \
77 }; \
78 \
79 static driver_t _ ## _bus ## _ ## _table ## _driver = { \
80 "lkpi_" #_bus #_table, \
81 _ ## _bus ## _ ## _table ## _methods, \
82 0 \
83 }; \
84 \
85 static devclass_t _ ## _bus ## _ ## _table ## _devclass; \
86 \
87 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\
88 _ ## _bus ## _ ## _table ## _devclass, 0, 0); \
89 \
90 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \
91 _bus, lkpi_ ## _table, _table, nitems(_table) - 1)
92
93 #define PCI_ANY_ID -1U
94
95 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
96 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
97 #define PCI_FUNC(devfn) ((devfn) & 0x07)
98 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff)
99
100 #define PCI_VDEVICE(_vendor, _device) \
101 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \
102 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
103 #define PCI_DEVICE(_vendor, _device) \
104 .vendor = (_vendor), .device = (_device), \
105 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
106
107 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
108
109 #define PCI_STD_NUM_BARS 6
110 #define PCI_BASE_ADDRESS_0 PCIR_BARS
111 #define PCI_BASE_ADDRESS_MEM_TYPE_64 PCIM_BAR_MEM_64
112 #define PCI_VENDOR_ID PCIR_VENDOR
113 #define PCI_DEVICE_ID PCIR_DEVICE
114 #define PCI_COMMAND PCIR_COMMAND
115 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS
116 #define PCI_COMMAND_MEMORY PCIM_CMD_MEMEN
117 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */
118 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */
119 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S
120 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1
121 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC
122 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */
123 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD
124 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */
125 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */
126 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */
127 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */
128 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */
129 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */
130 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */
131 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */
132 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */
133 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */
134 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */
135 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */
136 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */
137 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE
138 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE
139 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */
140 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */
141 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */
142 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */
143 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */
144 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */
145 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */
146 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */
147 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */
148 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */
149 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */
150 #define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED
151 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
152 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */
153 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */
154 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */
155 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */
156 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */
157 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */
158 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */
159 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */
160 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */
161 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */
162 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */
163 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */
164 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */
165 #define PCI_EXP_LNKCTL2_TLS 0x000f
166 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */
167 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
168 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
169 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
170 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
171 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */
172 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
173 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
174
175 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR
176 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH
177 #define PCI_MSI_FLAGS PCIR_MSI_CTRL
178 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE
179 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL
180 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE
181
182 #define PCI_EXP_LNKCAP_CLKPM 0x00040000
183 #define PCI_EXP_DEVSTA_TRPND 0x0020
184
185 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY)
186 #define IORESOURCE_IO (1 << SYS_RES_IOPORT)
187 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ)
188
189 enum pci_bus_speed {
190 PCI_SPEED_UNKNOWN = -1,
191 PCIE_SPEED_2_5GT,
192 PCIE_SPEED_5_0GT,
193 PCIE_SPEED_8_0GT,
194 PCIE_SPEED_16_0GT,
195 PCIE_SPEED_32_0GT,
196 PCIE_SPEED_64_0GT,
197 };
198
199 enum pcie_link_width {
200 PCIE_LNK_WIDTH_RESRV = 0x00,
201 PCIE_LNK_X1 = 0x01,
202 PCIE_LNK_X2 = 0x02,
203 PCIE_LNK_X4 = 0x04,
204 PCIE_LNK_X8 = 0x08,
205 PCIE_LNK_X12 = 0x0c,
206 PCIE_LNK_X16 = 0x10,
207 PCIE_LNK_X32 = 0x20,
208 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
209 };
210
211 #define PCIE_LINK_STATE_L0S 0x00000001
212 #define PCIE_LINK_STATE_L1 0x00000002
213 #define PCIE_LINK_STATE_CLKPM 0x00000004
214
215 typedef int pci_power_t;
216
217 #define PCI_D0 PCI_POWERSTATE_D0
218 #define PCI_D1 PCI_POWERSTATE_D1
219 #define PCI_D2 PCI_POWERSTATE_D2
220 #define PCI_D3hot PCI_POWERSTATE_D3
221 #define PCI_D3cold 4
222
223 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN
224
225 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD
226 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID
227
228 #define PCI_EXT_CAP_ID_ERR PCIZ_AER
229 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM
230
231 #define PCI_L1SS_CTL1 0x8
232 #define PCI_L1SS_CTL1_L1SS_MASK 0xf
233
234 #define PCI_IRQ_LEGACY 0x01
235 #define PCI_IRQ_MSI 0x02
236 #define PCI_IRQ_MSIX 0x04
237 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_LEGACY)
238
239 struct pci_dev;
240
241 struct pci_driver {
242 struct list_head node;
243 char *name;
244 const struct pci_device_id *id_table;
245 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
246 void (*remove)(struct pci_dev *dev);
247 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
248 int (*resume) (struct pci_dev *dev); /* Device woken up */
249 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */
250 driver_t bsddriver;
251 devclass_t bsdclass;
252 struct device_driver driver;
253 const struct pci_error_handlers *err_handler;
254 int bsd_probe_return;
255 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs,
256 const nvlist_t *pf_config);
257 void (*bsd_iov_uninit)(device_t dev);
258 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum,
259 const nvlist_t *vf_config);
260 uintptr_t _spare[8];
261 };
262
263 /*
264 * Pseudo-stable KPI. In 13.0 we neglected to include any spare fields to allow
265 * for growth in struct pci_driver. Those were added in 13.1, but can't be used
266 * until 13.1 is the oldest supported release so that packages built in 13.0
267 * will continue to work on stable/13 and 13.1 release. The 13.0 driver was 92
268 * or 182 bytes on 32 or 64 bit systems (respectively). We added 64 or 32 bytes
269 * of padding, hence the math below (which shouldn't be changed as spare fields
270 * are used up).
271 */
272 #ifdef __LP64__
273 #define __PCI_DRIVER_SIZE (184 + 64)
274 #else
275 #define __PCI_DRIVER_SIZE (92 + 32)
276 #endif
277 _Static_assert(sizeof(struct pci_driver) == __PCI_DRIVER_SIZE,
278 "linuxkpi struct pci_driver: Bad size");
279 #undef __PCI_DRIVER_SIZE
280
281 struct pci_bus {
282 struct pci_dev *self;
283 /* struct pci_bus *parent */
284 int domain;
285 int number;
286 };
287
288 extern struct list_head pci_drivers;
289 extern struct list_head pci_devices;
290 extern spinlock_t pci_lock;
291
292 #define __devexit_p(x) x
293
294 #define module_pci_driver(_driver) \
295 \
296 static inline int \
297 _pci_init(void) \
298 { \
299 \
300 return (linux_pci_register_driver(&_driver)); \
301 } \
302 \
303 static inline void \
304 _pci_exit(void) \
305 { \
306 \
307 linux_pci_unregister_driver(&_driver); \
308 } \
309 \
310 module_init(_pci_init); \
311 module_exit(_pci_exit)
312
313 struct msi_msg {
314 uint32_t data;
315 };
316
317 struct pci_msi_desc {
318 struct {
319 bool is_64;
320 } msi_attrib;
321 };
322
323 struct msi_desc {
324 struct msi_msg msg;
325 struct pci_msi_desc pci;
326 };
327
328 /*
329 * If we find drivers accessing this from multiple KPIs we may have to
330 * refcount objects of this structure.
331 */
332 struct pci_mmio_region {
333 TAILQ_ENTRY(pci_mmio_region) next;
334 struct resource *res;
335 int rid;
336 int type;
337 };
338
339 struct pci_dev {
340 struct device dev;
341 struct list_head links;
342 struct pci_driver *pdrv;
343 struct pci_bus *bus;
344 uint16_t device;
345 uint16_t vendor;
346 uint16_t subsystem_vendor;
347 uint16_t subsystem_device;
348 unsigned int irq;
349 unsigned int devfn;
350 uint32_t class;
351 uint8_t revision;
352 uint8_t msix_cap;
353 bool msi_enabled;
354
355 TAILQ_HEAD(, pci_mmio_region) mmio;
356
357 /* Add all new items at the end of the list in 13 */
358 struct pci_dev *root;
359 phys_addr_t rom;
360 size_t romlen;
361 bool managed; /* devres "pcim_*(). */
362 bool want_iomap_res;
363 bool msix_enabled;
364 uint8_t msi_cap;
365 struct msi_desc **msi_desc;
366 char *path_name;
367 };
368
369 /* XXX add kassert here on the mmio offset */
370
371 /* We need some meta-struct to keep track of these for devres. */
372 struct pci_devres {
373 bool enable_io;
374 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */
375 uint8_t region_mask;
376 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */
377 };
378 struct pcim_iomap_devres {
379 void *mmio_table[PCIR_MAX_BAR_0 + 1];
380 struct resource *res_table[PCIR_MAX_BAR_0 + 1];
381 };
382
383 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name);
384 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv,
385 unsigned int flags);
386 bool pci_device_is_present(struct pci_dev *pdev);
387
388 /* Internal helper function(s). */
389 struct pci_dev *lkpinew_pci_dev(device_t);
390 struct pci_devres *lkpi_pci_devres_get_alloc(struct pci_dev *pdev);
391 void lkpi_pci_devres_release(struct device *, void *);
392 struct resource *_lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size);
393 struct pcim_iomap_devres *lkpi_pcim_iomap_devres_find(struct pci_dev *pdev);
394 void lkpi_pcim_iomap_table_release(struct device *, void *);
395 struct pci_dev *lkpi_pci_get_device(uint16_t, uint16_t, struct pci_dev *);
396 struct msi_desc *lkpi_pci_msi_desc_alloc(int);
397
398 static inline bool
dev_is_pci(struct device * dev)399 dev_is_pci(struct device *dev)
400 {
401
402 return (device_get_devclass(dev->bsddev) == devclass_find("pci"));
403 }
404
405 static inline int
pci_resource_type(struct pci_dev * pdev,int bar)406 pci_resource_type(struct pci_dev *pdev, int bar)
407 {
408 struct pci_map *pm;
409
410 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar));
411 if (!pm)
412 return (-1);
413
414 if (PCI_BAR_IO(pm->pm_value))
415 return (SYS_RES_IOPORT);
416 else
417 return (SYS_RES_MEMORY);
418 }
419
420 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev,
421 struct resource_list *rl, int type, int rid);
422
423 static inline struct resource_list_entry *
linux_pci_get_rle(struct pci_dev * pdev,int type,int rid,bool reserve_bar)424 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar)
425 {
426 struct pci_devinfo *dinfo;
427 struct resource_list *rl;
428 struct resource_list_entry *rle;
429
430 dinfo = device_get_ivars(pdev->dev.bsddev);
431 rl = &dinfo->resources;
432 rle = resource_list_find(rl, type, rid);
433 /* Reserve resources for this BAR if needed. */
434 if (rle == NULL && reserve_bar)
435 rle = linux_pci_reserve_bar(pdev, rl, type, rid);
436 return (rle);
437 }
438
439 static inline struct resource_list_entry *
linux_pci_get_bar(struct pci_dev * pdev,int bar,bool reserve)440 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve)
441 {
442 int type;
443
444 type = pci_resource_type(pdev, bar);
445 if (type < 0)
446 return (NULL);
447 bar = PCIR_BAR(bar);
448 return (linux_pci_get_rle(pdev, type, bar, reserve));
449 }
450
451 static inline struct device *
linux_pci_find_irq_dev(unsigned int irq)452 linux_pci_find_irq_dev(unsigned int irq)
453 {
454 struct pci_dev *pdev;
455 struct device *found;
456
457 found = NULL;
458 spin_lock(&pci_lock);
459 list_for_each_entry(pdev, &pci_devices, links) {
460 if (irq == pdev->dev.irq ||
461 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) {
462 found = &pdev->dev;
463 break;
464 }
465 }
466 spin_unlock(&pci_lock);
467 return (found);
468 }
469
470 /*
471 * All drivers just seem to want to inspect the type not flags.
472 */
473 static inline int
pci_resource_flags(struct pci_dev * pdev,int bar)474 pci_resource_flags(struct pci_dev *pdev, int bar)
475 {
476 int type;
477
478 type = pci_resource_type(pdev, bar);
479 if (type < 0)
480 return (0);
481 return (1 << type);
482 }
483
484 static inline const char *
pci_name(struct pci_dev * d)485 pci_name(struct pci_dev *d)
486 {
487 return d->path_name;
488 }
489
490 static inline void *
pci_get_drvdata(struct pci_dev * pdev)491 pci_get_drvdata(struct pci_dev *pdev)
492 {
493
494 return dev_get_drvdata(&pdev->dev);
495 }
496
497 static inline void
pci_set_drvdata(struct pci_dev * pdev,void * data)498 pci_set_drvdata(struct pci_dev *pdev, void *data)
499 {
500
501 dev_set_drvdata(&pdev->dev, data);
502 }
503
504 static inline struct pci_dev *
pci_dev_get(struct pci_dev * pdev)505 pci_dev_get(struct pci_dev *pdev)
506 {
507
508 if (pdev != NULL)
509 get_device(&pdev->dev);
510 return (pdev);
511 }
512
513 static __inline void
pci_dev_put(struct pci_dev * pdev)514 pci_dev_put(struct pci_dev *pdev)
515 {
516
517 if (pdev != NULL)
518 put_device(&pdev->dev);
519 }
520
521 static inline int
pci_enable_device(struct pci_dev * pdev)522 pci_enable_device(struct pci_dev *pdev)
523 {
524
525 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT);
526 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY);
527 return (0);
528 }
529
530 static inline void
pci_disable_device(struct pci_dev * pdev)531 pci_disable_device(struct pci_dev *pdev)
532 {
533
534 pci_disable_busmaster(pdev->dev.bsddev);
535 }
536
537 static inline int
pci_set_master(struct pci_dev * pdev)538 pci_set_master(struct pci_dev *pdev)
539 {
540
541 pci_enable_busmaster(pdev->dev.bsddev);
542 return (0);
543 }
544
545 static inline int
pci_set_power_state(struct pci_dev * pdev,int state)546 pci_set_power_state(struct pci_dev *pdev, int state)
547 {
548
549 pci_set_powerstate(pdev->dev.bsddev, state);
550 return (0);
551 }
552
553 static inline int
pci_clear_master(struct pci_dev * pdev)554 pci_clear_master(struct pci_dev *pdev)
555 {
556
557 pci_disable_busmaster(pdev->dev.bsddev);
558 return (0);
559 }
560
561 static inline bool
pci_is_root_bus(struct pci_bus * pbus)562 pci_is_root_bus(struct pci_bus *pbus)
563 {
564
565 return (pbus->self == NULL);
566 }
567
568 static inline struct pci_dev *
pci_upstream_bridge(struct pci_dev * pdev)569 pci_upstream_bridge(struct pci_dev *pdev)
570 {
571
572 if (pci_is_root_bus(pdev->bus))
573 return (NULL);
574
575 /*
576 * If we do not have a (proper) "upstream bridge" set, e.g., we point
577 * to ourselves, try to handle this case on the fly like we do
578 * for pcie_find_root_port().
579 */
580 if (pdev == pdev->bus->self) {
581 device_t bridge;
582
583 bridge = device_get_parent(pdev->dev.bsddev);
584 if (bridge == NULL)
585 goto done;
586 bridge = device_get_parent(bridge);
587 if (bridge == NULL)
588 goto done;
589 if (device_get_devclass(device_get_parent(bridge)) !=
590 devclass_find("pci"))
591 goto done;
592
593 /*
594 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev
595 * for it so it can be returned.
596 */
597 pdev->bus->self = lkpinew_pci_dev(bridge);
598 }
599 done:
600 return (pdev->bus->self);
601 }
602
603 static inline struct pci_devres *
lkpi_pci_devres_find(struct pci_dev * pdev)604 lkpi_pci_devres_find(struct pci_dev *pdev)
605 {
606
607 if (!pdev->managed)
608 return (NULL);
609
610 return (lkpi_pci_devres_get_alloc(pdev));
611 }
612
613 static inline void
pci_release_region(struct pci_dev * pdev,int bar)614 pci_release_region(struct pci_dev *pdev, int bar)
615 {
616 struct resource_list_entry *rle;
617 struct pci_devres *dr;
618 struct pci_mmio_region *mmio, *p;
619
620 if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL)
621 return;
622
623 /*
624 * As we implicitly track the requests we also need to clear them on
625 * release. Do clear before resource release.
626 */
627 dr = lkpi_pci_devres_find(pdev);
628 if (dr != NULL) {
629 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d"
630 " region_table res %p != rel->res %p\n", __func__, pdev,
631 bar, dr->region_table[bar], rle->res));
632 dr->region_table[bar] = NULL;
633 dr->region_mask &= ~(1 << bar);
634 }
635
636 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) {
637 if (rle->res != (void *)rman_get_bushandle(mmio->res))
638 continue;
639 TAILQ_REMOVE(&pdev->mmio, mmio, next);
640 free(mmio, M_DEVBUF);
641 }
642
643 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res);
644 }
645
646 static inline void
pci_release_regions(struct pci_dev * pdev)647 pci_release_regions(struct pci_dev *pdev)
648 {
649 int i;
650
651 for (i = 0; i <= PCIR_MAX_BAR_0; i++)
652 pci_release_region(pdev, i);
653 }
654
655 static inline int
pci_request_regions(struct pci_dev * pdev,const char * res_name)656 pci_request_regions(struct pci_dev *pdev, const char *res_name)
657 {
658 int error;
659 int i;
660
661 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
662 error = pci_request_region(pdev, i, res_name);
663 if (error && error != -ENODEV) {
664 pci_release_regions(pdev);
665 return (error);
666 }
667 }
668 return (0);
669 }
670
671 static inline void
lkpi_pci_disable_msix(struct pci_dev * pdev)672 lkpi_pci_disable_msix(struct pci_dev *pdev)
673 {
674
675 pci_release_msi(pdev->dev.bsddev);
676
677 /*
678 * The MSIX IRQ numbers associated with this PCI device are no
679 * longer valid and might be re-assigned. Make sure
680 * linux_pci_find_irq_dev() does no longer see them by
681 * resetting their references to zero:
682 */
683 pdev->dev.irq_start = 0;
684 pdev->dev.irq_end = 0;
685 pdev->msix_enabled = false;
686 }
687 /* Only for consistency. No conflict on that one. */
688 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev)
689
690 static inline void
lkpi_pci_disable_msi(struct pci_dev * pdev)691 lkpi_pci_disable_msi(struct pci_dev *pdev)
692 {
693
694 pci_release_msi(pdev->dev.bsddev);
695
696 pdev->dev.irq_start = 0;
697 pdev->dev.irq_end = 0;
698 pdev->irq = pdev->dev.irq;
699 pdev->msi_enabled = false;
700 }
701 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev)
702 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev)
703
704 unsigned long pci_resource_start(struct pci_dev *pdev, int bar);
705 unsigned long pci_resource_len(struct pci_dev *pdev, int bar);
706
707 static inline bus_addr_t
pci_bus_address(struct pci_dev * pdev,int bar)708 pci_bus_address(struct pci_dev *pdev, int bar)
709 {
710
711 return (pci_resource_start(pdev, bar));
712 }
713
714 #define PCI_CAP_ID_EXP PCIY_EXPRESS
715 #define PCI_CAP_ID_PCIX PCIY_PCIX
716 #define PCI_CAP_ID_AGP PCIY_AGP
717 #define PCI_CAP_ID_PM PCIY_PMG
718
719 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL
720 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD
721 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST
722 #define PCI_EXP_LNKCTL PCIER_LINK_CTL
723 #define PCI_EXP_LNKSTA PCIER_LINK_STA
724
725 static inline int
pci_find_capability(struct pci_dev * pdev,int capid)726 pci_find_capability(struct pci_dev *pdev, int capid)
727 {
728 int reg;
729
730 if (pci_find_cap(pdev->dev.bsddev, capid, ®))
731 return (0);
732 return (reg);
733 }
734
pci_pcie_cap(struct pci_dev * dev)735 static inline int pci_pcie_cap(struct pci_dev *dev)
736 {
737 return pci_find_capability(dev, PCI_CAP_ID_EXP);
738 }
739
740 static inline int
pci_find_ext_capability(struct pci_dev * pdev,int capid)741 pci_find_ext_capability(struct pci_dev *pdev, int capid)
742 {
743 int reg;
744
745 if (pci_find_extcap(pdev->dev.bsddev, capid, ®))
746 return (0);
747 return (reg);
748 }
749
750 #define PCIM_PCAP_PME_SHIFT 11
751 static __inline bool
pci_pme_capable(struct pci_dev * pdev,uint32_t flag)752 pci_pme_capable(struct pci_dev *pdev, uint32_t flag)
753 {
754 struct pci_devinfo *dinfo;
755 pcicfgregs *cfg;
756
757 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT))
758 return (false);
759
760 dinfo = device_get_ivars(pdev->dev.bsddev);
761 cfg = &dinfo->cfg;
762
763 if (cfg->pp.pp_cap == 0)
764 return (false);
765
766 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0)
767 return (true);
768
769 return (false);
770 }
771
772 static inline int
pci_disable_link_state(struct pci_dev * pdev,uint32_t flags)773 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags)
774 {
775
776 if (!pci_enable_aspm)
777 return (-EPERM);
778
779 return (-ENXIO);
780 }
781
782 static inline int
pci_read_config_byte(const struct pci_dev * pdev,int where,u8 * val)783 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val)
784 {
785
786 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1);
787 return (0);
788 }
789
790 static inline int
pci_read_config_word(const struct pci_dev * pdev,int where,u16 * val)791 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val)
792 {
793
794 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2);
795 return (0);
796 }
797
798 static inline int
pci_read_config_dword(const struct pci_dev * pdev,int where,u32 * val)799 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val)
800 {
801
802 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4);
803 return (0);
804 }
805
806 static inline int
pci_write_config_byte(const struct pci_dev * pdev,int where,u8 val)807 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val)
808 {
809
810 pci_write_config(pdev->dev.bsddev, where, val, 1);
811 return (0);
812 }
813
814 static inline int
pci_write_config_word(const struct pci_dev * pdev,int where,u16 val)815 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val)
816 {
817
818 pci_write_config(pdev->dev.bsddev, where, val, 2);
819 return (0);
820 }
821
822 static inline int
pci_write_config_dword(const struct pci_dev * pdev,int where,u32 val)823 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val)
824 {
825
826 pci_write_config(pdev->dev.bsddev, where, val, 4);
827 return (0);
828 }
829
830 int linux_pci_register_driver(struct pci_driver *pdrv);
831 int linux_pci_register_drm_driver(struct pci_driver *pdrv);
832 void linux_pci_unregister_driver(struct pci_driver *pdrv);
833 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv);
834
835 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv)
836 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv)
837
838 struct msix_entry {
839 int entry;
840 int vector;
841 };
842
843 /*
844 * Enable msix, positive errors indicate actual number of available
845 * vectors. Negative errors are failures.
846 *
847 * NB: define added to prevent this definition of pci_enable_msix from
848 * clashing with the native FreeBSD version.
849 */
850 #define pci_enable_msix(...) \
851 linux_pci_enable_msix(__VA_ARGS__)
852
853 static inline int
pci_enable_msix(struct pci_dev * pdev,struct msix_entry * entries,int nreq)854 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq)
855 {
856 struct resource_list_entry *rle;
857 int error;
858 int avail;
859 int i;
860
861 avail = pci_msix_count(pdev->dev.bsddev);
862 if (avail < nreq) {
863 if (avail == 0)
864 return -EINVAL;
865 return avail;
866 }
867 avail = nreq;
868 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0)
869 return error;
870 /*
871 * Handle case where "pci_alloc_msix()" may allocate less
872 * interrupts than available and return with no error:
873 */
874 if (avail < nreq) {
875 pci_release_msi(pdev->dev.bsddev);
876 return avail;
877 }
878 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false);
879 pdev->dev.irq_start = rle->start;
880 pdev->dev.irq_end = rle->start + avail;
881 for (i = 0; i < nreq; i++)
882 entries[i].vector = pdev->dev.irq_start + i;
883 pdev->msix_enabled = true;
884 return (0);
885 }
886
887 #define pci_enable_msix_range(...) \
888 linux_pci_enable_msix_range(__VA_ARGS__)
889
890 static inline int
pci_enable_msix_range(struct pci_dev * dev,struct msix_entry * entries,int minvec,int maxvec)891 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
892 int minvec, int maxvec)
893 {
894 int nvec = maxvec;
895 int rc;
896
897 if (maxvec < minvec)
898 return (-ERANGE);
899
900 do {
901 rc = pci_enable_msix(dev, entries, nvec);
902 if (rc < 0) {
903 return (rc);
904 } else if (rc > 0) {
905 if (rc < minvec)
906 return (-ENOSPC);
907 nvec = rc;
908 }
909 } while (rc);
910 return (nvec);
911 }
912
913 #define pci_enable_msi(pdev) \
914 linux_pci_enable_msi(pdev)
915
916 static inline int
_lkpi_pci_enable_msi_range(struct pci_dev * pdev,int minvec,int maxvec)917 _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec)
918 {
919 struct resource_list_entry *rle;
920 int error;
921 int nvec;
922
923 if (maxvec < minvec)
924 return (-EINVAL);
925
926 nvec = pci_msi_count(pdev->dev.bsddev);
927 if (nvec < 1 || nvec < minvec)
928 return (-ENOSPC);
929
930 nvec = min(nvec, maxvec);
931 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &nvec)) != 0)
932 return error;
933
934 /* Native PCI might only ever ask for 32 vectors. */
935 if (nvec < minvec) {
936 pci_release_msi(pdev->dev.bsddev);
937 return (-ENOSPC);
938 }
939
940 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false);
941 pdev->dev.irq_start = rle->start;
942 pdev->dev.irq_end = rle->start + nvec;
943 pdev->irq = rle->start;
944 pdev->msi_enabled = true;
945 return (0);
946 }
947
948 static inline int
pci_enable_msi(struct pci_dev * pdev)949 pci_enable_msi(struct pci_dev *pdev)
950 {
951
952 return (_lkpi_pci_enable_msi_range(pdev, 1, 1));
953 }
954
955 static inline int
pci_channel_offline(struct pci_dev * pdev)956 pci_channel_offline(struct pci_dev *pdev)
957 {
958
959 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID);
960 }
961
pci_enable_sriov(struct pci_dev * dev,int nr_virtfn)962 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
963 {
964 return -ENODEV;
965 }
966
pci_disable_sriov(struct pci_dev * dev)967 static inline void pci_disable_sriov(struct pci_dev *dev)
968 {
969 }
970
971 static inline void *
pci_iomap(struct pci_dev * pdev,int mmio_bar,int mmio_size)972 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size)
973 {
974 struct resource *res;
975
976 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size);
977 if (res == NULL)
978 return (NULL);
979 /* This is a FreeBSD extension so we can use bus_*(). */
980 if (pdev->want_iomap_res)
981 return (res);
982 return ((void *)rman_get_bushandle(res));
983 }
984
985 static inline void
pci_iounmap(struct pci_dev * pdev,void * res)986 pci_iounmap(struct pci_dev *pdev, void *res)
987 {
988 struct pci_mmio_region *mmio, *p;
989
990 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) {
991 if (res != (void *)rman_get_bushandle(mmio->res))
992 continue;
993 bus_release_resource(pdev->dev.bsddev,
994 mmio->type, mmio->rid, mmio->res);
995 TAILQ_REMOVE(&pdev->mmio, mmio, next);
996 free(mmio, M_DEVBUF);
997 return;
998 }
999 }
1000
1001 static inline void
lkpi_pci_save_state(struct pci_dev * pdev)1002 lkpi_pci_save_state(struct pci_dev *pdev)
1003 {
1004
1005 pci_save_state(pdev->dev.bsddev);
1006 }
1007
1008 static inline void
lkpi_pci_restore_state(struct pci_dev * pdev)1009 lkpi_pci_restore_state(struct pci_dev *pdev)
1010 {
1011
1012 pci_restore_state(pdev->dev.bsddev);
1013 }
1014
1015 #define pci_save_state(dev) lkpi_pci_save_state(dev)
1016 #define pci_restore_state(dev) lkpi_pci_restore_state(dev)
1017
1018 static inline int
pci_reset_function(struct pci_dev * pdev)1019 pci_reset_function(struct pci_dev *pdev)
1020 {
1021
1022 return (-ENOSYS);
1023 }
1024
1025 #define DEFINE_PCI_DEVICE_TABLE(_table) \
1026 const struct pci_device_id _table[] __devinitdata
1027
1028 /* XXX This should not be necessary. */
1029 #define pcix_set_mmrbc(d, v) 0
1030 #define pcix_get_max_mmrbc(d) 0
1031 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v))
1032
1033 #define PCI_DMA_BIDIRECTIONAL 0
1034 #define PCI_DMA_TODEVICE 1
1035 #define PCI_DMA_FROMDEVICE 2
1036 #define PCI_DMA_NONE 3
1037
1038 #define pci_pool dma_pool
1039 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__)
1040 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__)
1041 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__)
1042 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \
1043 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc)
1044 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \
1045 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
1046 _size, _vaddr, _dma_handle)
1047 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \
1048 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \
1049 _sg, _nents, (enum dma_data_direction)_dir)
1050 #define pci_map_single(_hwdev, _ptr, _size, _dir) \
1051 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \
1052 (_ptr), (_size), (enum dma_data_direction)_dir)
1053 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \
1054 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
1055 _addr, _size, (enum dma_data_direction)_dir)
1056 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \
1057 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
1058 _sg, _nents, (enum dma_data_direction)_dir)
1059 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \
1060 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\
1061 _offset, _size, (enum dma_data_direction)_dir)
1062 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \
1063 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
1064 _dma_address, _size, (enum dma_data_direction)_dir)
1065 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask))
1066 #define pci_dma_mapping_error(_pdev, _dma_addr) \
1067 dma_mapping_error(&(_pdev)->dev, _dma_addr)
1068 #define pci_set_consistent_dma_mask(_pdev, _mask) \
1069 dma_set_coherent_mask(&(_pdev)->dev, (_mask))
1070 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x);
1071 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x);
1072 #define pci_unmap_addr dma_unmap_addr
1073 #define pci_unmap_addr_set dma_unmap_addr_set
1074 #define pci_unmap_len dma_unmap_len
1075 #define pci_unmap_len_set dma_unmap_len_set
1076
1077 typedef unsigned int __bitwise pci_channel_state_t;
1078 typedef unsigned int __bitwise pci_ers_result_t;
1079
1080 enum pci_channel_state {
1081 pci_channel_io_normal = 1,
1082 pci_channel_io_frozen = 2,
1083 pci_channel_io_perm_failure = 3,
1084 };
1085
1086 enum pci_ers_result {
1087 PCI_ERS_RESULT_NONE = 1,
1088 PCI_ERS_RESULT_CAN_RECOVER = 2,
1089 PCI_ERS_RESULT_NEED_RESET = 3,
1090 PCI_ERS_RESULT_DISCONNECT = 4,
1091 PCI_ERS_RESULT_RECOVERED = 5,
1092 };
1093
1094 /* PCI bus error event callbacks */
1095 struct pci_error_handlers {
1096 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
1097 enum pci_channel_state error);
1098 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
1099 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
1100 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
1101 void (*resume)(struct pci_dev *dev);
1102 };
1103
1104 /* FreeBSD does not support SRIOV - yet */
pci_physfn(struct pci_dev * dev)1105 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
1106 {
1107 return dev;
1108 }
1109
pci_is_pcie(struct pci_dev * dev)1110 static inline bool pci_is_pcie(struct pci_dev *dev)
1111 {
1112 return !!pci_pcie_cap(dev);
1113 }
1114
pcie_flags_reg(struct pci_dev * dev)1115 static inline u16 pcie_flags_reg(struct pci_dev *dev)
1116 {
1117 int pos;
1118 u16 reg16;
1119
1120 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
1121 if (!pos)
1122 return 0;
1123
1124 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16);
1125
1126 return reg16;
1127 }
1128
pci_pcie_type(struct pci_dev * dev)1129 static inline int pci_pcie_type(struct pci_dev *dev)
1130 {
1131 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1132 }
1133
pcie_cap_version(struct pci_dev * dev)1134 static inline int pcie_cap_version(struct pci_dev *dev)
1135 {
1136 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS;
1137 }
1138
pcie_cap_has_lnkctl(struct pci_dev * dev)1139 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev)
1140 {
1141 int type = pci_pcie_type(dev);
1142
1143 return pcie_cap_version(dev) > 1 ||
1144 type == PCI_EXP_TYPE_ROOT_PORT ||
1145 type == PCI_EXP_TYPE_ENDPOINT ||
1146 type == PCI_EXP_TYPE_LEG_END;
1147 }
1148
pcie_cap_has_devctl(const struct pci_dev * dev)1149 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
1150 {
1151 return true;
1152 }
1153
pcie_cap_has_sltctl(struct pci_dev * dev)1154 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev)
1155 {
1156 int type = pci_pcie_type(dev);
1157
1158 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT ||
1159 (type == PCI_EXP_TYPE_DOWNSTREAM &&
1160 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT);
1161 }
1162
pcie_cap_has_rtctl(struct pci_dev * dev)1163 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev)
1164 {
1165 int type = pci_pcie_type(dev);
1166
1167 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT ||
1168 type == PCI_EXP_TYPE_RC_EC;
1169 }
1170
pcie_capability_reg_implemented(struct pci_dev * dev,int pos)1171 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
1172 {
1173 if (!pci_is_pcie(dev))
1174 return false;
1175
1176 switch (pos) {
1177 case PCI_EXP_FLAGS_TYPE:
1178 return true;
1179 case PCI_EXP_DEVCAP:
1180 case PCI_EXP_DEVCTL:
1181 case PCI_EXP_DEVSTA:
1182 return pcie_cap_has_devctl(dev);
1183 case PCI_EXP_LNKCAP:
1184 case PCI_EXP_LNKCTL:
1185 case PCI_EXP_LNKSTA:
1186 return pcie_cap_has_lnkctl(dev);
1187 case PCI_EXP_SLTCAP:
1188 case PCI_EXP_SLTCTL:
1189 case PCI_EXP_SLTSTA:
1190 return pcie_cap_has_sltctl(dev);
1191 case PCI_EXP_RTCTL:
1192 case PCI_EXP_RTCAP:
1193 case PCI_EXP_RTSTA:
1194 return pcie_cap_has_rtctl(dev);
1195 case PCI_EXP_DEVCAP2:
1196 case PCI_EXP_DEVCTL2:
1197 case PCI_EXP_LNKCAP2:
1198 case PCI_EXP_LNKCTL2:
1199 case PCI_EXP_LNKSTA2:
1200 return pcie_cap_version(dev) > 1;
1201 default:
1202 return false;
1203 }
1204 }
1205
1206 static inline int
pcie_capability_read_dword(struct pci_dev * dev,int pos,u32 * dst)1207 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst)
1208 {
1209 *dst = 0;
1210 if (pos & 3)
1211 return -EINVAL;
1212
1213 if (!pcie_capability_reg_implemented(dev, pos))
1214 return -EINVAL;
1215
1216 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst);
1217 }
1218
1219 static inline int
pcie_capability_read_word(struct pci_dev * dev,int pos,u16 * dst)1220 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst)
1221 {
1222 *dst = 0;
1223 if (pos & 3)
1224 return -EINVAL;
1225
1226 if (!pcie_capability_reg_implemented(dev, pos))
1227 return -EINVAL;
1228
1229 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst);
1230 }
1231
1232 static inline int
pcie_capability_write_word(struct pci_dev * dev,int pos,u16 val)1233 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
1234 {
1235 if (pos & 1)
1236 return -EINVAL;
1237
1238 if (!pcie_capability_reg_implemented(dev, pos))
1239 return 0;
1240
1241 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
1242 }
1243
1244 static inline int
pcie_capability_set_word(struct pci_dev * dev,int pos,uint16_t val)1245 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val)
1246 {
1247 int error;
1248 uint16_t v;
1249
1250 error = pcie_capability_read_word(dev, pos, &v);
1251 if (error != 0)
1252 return (error);
1253
1254 v |= val;
1255
1256 error = pcie_capability_write_word(dev, pos, v);
1257 return (error);
1258 }
1259
1260 static inline int
pcie_capability_clear_word(struct pci_dev * dev,int pos,uint16_t val)1261 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val)
1262 {
1263 int error;
1264 uint16_t v;
1265
1266 error = pcie_capability_read_word(dev, pos, &v);
1267 if (error != 0)
1268 return (error);
1269
1270 v &= ~val;
1271
1272 error = pcie_capability_write_word(dev, pos, v);
1273 return (error);
1274 }
1275
pcie_get_minimum_link(struct pci_dev * dev,enum pci_bus_speed * speed,enum pcie_link_width * width)1276 static inline int pcie_get_minimum_link(struct pci_dev *dev,
1277 enum pci_bus_speed *speed, enum pcie_link_width *width)
1278 {
1279 *speed = PCI_SPEED_UNKNOWN;
1280 *width = PCIE_LNK_WIDTH_UNKNOWN;
1281 return (0);
1282 }
1283
1284 static inline int
pci_num_vf(struct pci_dev * dev)1285 pci_num_vf(struct pci_dev *dev)
1286 {
1287 return (0);
1288 }
1289
1290 static inline enum pci_bus_speed
pcie_get_speed_cap(struct pci_dev * dev)1291 pcie_get_speed_cap(struct pci_dev *dev)
1292 {
1293 device_t root;
1294 uint32_t lnkcap, lnkcap2;
1295 int error, pos;
1296
1297 root = device_get_parent(dev->dev.bsddev);
1298 if (root == NULL)
1299 return (PCI_SPEED_UNKNOWN);
1300 root = device_get_parent(root);
1301 if (root == NULL)
1302 return (PCI_SPEED_UNKNOWN);
1303 root = device_get_parent(root);
1304 if (root == NULL)
1305 return (PCI_SPEED_UNKNOWN);
1306
1307 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA ||
1308 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS)
1309 return (PCI_SPEED_UNKNOWN);
1310
1311 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0)
1312 return (PCI_SPEED_UNKNOWN);
1313
1314 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4);
1315
1316 if (lnkcap2) { /* PCIe r3.0-compliant */
1317 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
1318 return (PCIE_SPEED_2_5GT);
1319 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
1320 return (PCIE_SPEED_5_0GT);
1321 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
1322 return (PCIE_SPEED_8_0GT);
1323 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
1324 return (PCIE_SPEED_16_0GT);
1325 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB)
1326 return (PCIE_SPEED_32_0GT);
1327 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB)
1328 return (PCIE_SPEED_64_0GT);
1329 } else { /* pre-r3.0 */
1330 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4);
1331 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
1332 return (PCIE_SPEED_2_5GT);
1333 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
1334 return (PCIE_SPEED_5_0GT);
1335 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
1336 return (PCIE_SPEED_8_0GT);
1337 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
1338 return (PCIE_SPEED_16_0GT);
1339 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB)
1340 return (PCIE_SPEED_32_0GT);
1341 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB)
1342 return (PCIE_SPEED_64_0GT);
1343 }
1344 return (PCI_SPEED_UNKNOWN);
1345 }
1346
1347 static inline enum pcie_link_width
pcie_get_width_cap(struct pci_dev * dev)1348 pcie_get_width_cap(struct pci_dev *dev)
1349 {
1350 uint32_t lnkcap;
1351
1352 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
1353 if (lnkcap)
1354 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4);
1355
1356 return (PCIE_LNK_WIDTH_UNKNOWN);
1357 }
1358
1359 static inline int
pcie_get_mps(struct pci_dev * dev)1360 pcie_get_mps(struct pci_dev *dev)
1361 {
1362 return (pci_get_max_payload(dev->dev.bsddev));
1363 }
1364
1365 static inline uint32_t
PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd)1366 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd)
1367 {
1368
1369 switch(spd) {
1370 case PCIE_SPEED_64_0GT:
1371 return (64000 * 128 / 130);
1372 case PCIE_SPEED_32_0GT:
1373 return (32000 * 128 / 130);
1374 case PCIE_SPEED_16_0GT:
1375 return (16000 * 128 / 130);
1376 case PCIE_SPEED_8_0GT:
1377 return (8000 * 128 / 130);
1378 case PCIE_SPEED_5_0GT:
1379 return (5000 * 8 / 10);
1380 case PCIE_SPEED_2_5GT:
1381 return (2500 * 8 / 10);
1382 default:
1383 return (0);
1384 }
1385 }
1386
1387 static inline uint32_t
pcie_bandwidth_available(struct pci_dev * pdev,struct pci_dev ** limiting,enum pci_bus_speed * speed,enum pcie_link_width * width)1388 pcie_bandwidth_available(struct pci_dev *pdev,
1389 struct pci_dev **limiting,
1390 enum pci_bus_speed *speed,
1391 enum pcie_link_width *width)
1392 {
1393 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev);
1394 enum pcie_link_width nwidth = pcie_get_width_cap(pdev);
1395
1396 if (speed)
1397 *speed = nspeed;
1398 if (width)
1399 *width = nwidth;
1400
1401 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed));
1402 }
1403
1404 static inline struct pci_dev *
pcie_find_root_port(struct pci_dev * pdev)1405 pcie_find_root_port(struct pci_dev *pdev)
1406 {
1407 device_t root;
1408
1409 if (pdev->root != NULL)
1410 return (pdev->root);
1411
1412 root = pci_find_pcie_root_port(pdev->dev.bsddev);
1413 if (root == NULL)
1414 return (NULL);
1415
1416 pdev->root = lkpinew_pci_dev(root);
1417 return (pdev->root);
1418 }
1419
1420 /* This is needed when people rip out the device "HotPlug". */
1421 static inline void
pci_lock_rescan_remove(void)1422 pci_lock_rescan_remove(void)
1423 {
1424 }
1425
1426 static inline void
pci_unlock_rescan_remove(void)1427 pci_unlock_rescan_remove(void)
1428 {
1429 }
1430
1431 static __inline void
pci_stop_and_remove_bus_device(struct pci_dev * pdev)1432 pci_stop_and_remove_bus_device(struct pci_dev *pdev)
1433 {
1434 }
1435
1436 static inline int
pci_rescan_bus(struct pci_bus * pbus)1437 pci_rescan_bus(struct pci_bus *pbus)
1438 {
1439 device_t *devlist, parent;
1440 int devcount, error;
1441
1442 if (!device_is_attached(pbus->self->dev.bsddev))
1443 return (0);
1444 /* pci_rescan_method() will work on the pcib (parent). */
1445 error = BUS_RESCAN(pbus->self->dev.bsddev);
1446 if (error != 0)
1447 return (0);
1448
1449 parent = device_get_parent(pbus->self->dev.bsddev);
1450 error = device_get_children(parent, &devlist, &devcount);
1451 if (error != 0)
1452 return (0);
1453 if (devcount != 0)
1454 free(devlist, M_TEMP);
1455
1456 return (devcount);
1457 }
1458
1459 /*
1460 * The following functions can be used to attach/detach the LinuxKPI's
1461 * PCI device runtime. The pci_driver and pci_device_id pointer is
1462 * allowed to be NULL. Other pointers must be all valid.
1463 * The pci_dev structure should be zero-initialized before passed
1464 * to the linux_pci_attach_device function.
1465 */
1466 extern int linux_pci_attach_device(device_t, struct pci_driver *,
1467 const struct pci_device_id *, struct pci_dev *);
1468 extern int linux_pci_detach_device(struct pci_dev *);
1469
1470 static inline int
pci_dev_present(const struct pci_device_id * cur)1471 pci_dev_present(const struct pci_device_id *cur)
1472 {
1473 while (cur != NULL && (cur->vendor || cur->device)) {
1474 if (pci_find_device(cur->vendor, cur->device) != NULL) {
1475 return (1);
1476 }
1477 cur++;
1478 }
1479 return (0);
1480 }
1481
1482 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain,
1483 unsigned int bus, unsigned int devfn);
1484 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \
1485 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn)
1486
1487 static inline int
pci_domain_nr(struct pci_bus * pbus)1488 pci_domain_nr(struct pci_bus *pbus)
1489 {
1490
1491 return (pbus->domain);
1492 }
1493
1494 static inline int
pci_bus_read_config(struct pci_bus * bus,unsigned int devfn,int pos,uint32_t * val,int len)1495 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn,
1496 int pos, uint32_t *val, int len)
1497 {
1498
1499 *val = pci_read_config(bus->self->dev.bsddev, pos, len);
1500 return (0);
1501 }
1502
1503 static inline int
pci_bus_read_config_word(struct pci_bus * bus,unsigned int devfn,int pos,u16 * val)1504 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val)
1505 {
1506 uint32_t tmp;
1507 int ret;
1508
1509 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2);
1510 *val = (u16)tmp;
1511 return (ret);
1512 }
1513
1514 static inline int
pci_bus_read_config_byte(struct pci_bus * bus,unsigned int devfn,int pos,u8 * val)1515 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val)
1516 {
1517 uint32_t tmp;
1518 int ret;
1519
1520 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1);
1521 *val = (u8)tmp;
1522 return (ret);
1523 }
1524
1525 static inline int
pci_bus_write_config(struct pci_bus * bus,unsigned int devfn,int pos,uint32_t val,int size)1526 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos,
1527 uint32_t val, int size)
1528 {
1529
1530 pci_write_config(bus->self->dev.bsddev, pos, val, size);
1531 return (0);
1532 }
1533
1534 static inline int
pci_bus_write_config_byte(struct pci_bus * bus,unsigned int devfn,int pos,uint8_t val)1535 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos,
1536 uint8_t val)
1537 {
1538 return (pci_bus_write_config(bus, devfn, pos, val, 1));
1539 }
1540
1541 static inline int
pci_bus_write_config_word(struct pci_bus * bus,unsigned int devfn,int pos,uint16_t val)1542 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos,
1543 uint16_t val)
1544 {
1545 return (pci_bus_write_config(bus, devfn, pos, val, 2));
1546 }
1547
1548 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from);
1549 #define pci_get_class(class, from) lkpi_pci_get_class(class, from)
1550
1551 /* -------------------------------------------------------------------------- */
1552
1553 static inline int
pcim_enable_device(struct pci_dev * pdev)1554 pcim_enable_device(struct pci_dev *pdev)
1555 {
1556 struct pci_devres *dr;
1557 int error;
1558
1559 /* Here we cannot run through the pdev->managed check. */
1560 dr = lkpi_pci_devres_get_alloc(pdev);
1561 if (dr == NULL)
1562 return (-ENOMEM);
1563
1564 /* If resources were enabled before do not do it again. */
1565 if (dr->enable_io)
1566 return (0);
1567
1568 error = pci_enable_device(pdev);
1569 if (error == 0)
1570 dr->enable_io = true;
1571
1572 /* This device is not managed. */
1573 pdev->managed = true;
1574
1575 return (error);
1576 }
1577
1578 static inline void __iomem **
pcim_iomap_table(struct pci_dev * pdev)1579 pcim_iomap_table(struct pci_dev *pdev)
1580 {
1581 struct pcim_iomap_devres *dr;
1582
1583 dr = lkpi_pcim_iomap_devres_find(pdev);
1584 if (dr == NULL)
1585 return (NULL);
1586
1587 /*
1588 * If the driver has manually set a flag to be able to request the
1589 * resource to use bus_read/write_<n>, return the shadow table.
1590 */
1591 if (pdev->want_iomap_res)
1592 return ((void **)dr->res_table);
1593
1594 /* This is the Linux default. */
1595 return (dr->mmio_table);
1596 }
1597
1598 static inline int
pcim_iomap_regions(struct pci_dev * pdev,uint32_t mask,const char * name)1599 pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, const char *name)
1600 {
1601 struct pcim_iomap_devres *dr;
1602 void *res;
1603 uint32_t mappings;
1604 int bar;
1605
1606 dr = lkpi_pcim_iomap_devres_find(pdev);
1607 if (dr == NULL)
1608 return (-ENOMEM);
1609
1610 /* Now iomap all the requested (by "mask") ones. */
1611 for (bar = mappings = 0; mappings != mask; bar++) {
1612 if ((mask & (1 << bar)) == 0)
1613 continue;
1614
1615 /* Request double is not allowed. */
1616 if (dr->mmio_table[bar] != NULL) {
1617 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n",
1618 __func__, bar, dr->mmio_table[bar]);
1619 goto err;
1620 }
1621
1622 res = _lkpi_pci_iomap(pdev, bar, 0);
1623 if (res == NULL)
1624 goto err;
1625 dr->mmio_table[bar] = (void *)rman_get_bushandle(res);
1626 dr->res_table[bar] = res;
1627
1628 mappings |= (1 << bar);
1629 }
1630
1631 return (0);
1632 err:
1633 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) {
1634 if ((mappings & (1 << bar)) != 0) {
1635 res = dr->mmio_table[bar];
1636 if (res == NULL)
1637 continue;
1638 pci_iounmap(pdev, res);
1639 }
1640 }
1641
1642 return (-EINVAL);
1643 }
1644
1645 static inline int
pcim_iomap_regions_request_all(struct pci_dev * pdev,uint32_t mask,char * name)1646 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name)
1647 {
1648 uint32_t requests, req_mask;
1649 int bar, error;
1650
1651 /* Request all the BARs ("regions") we do not iomap. */
1652 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask;
1653 for (bar = requests = 0; requests != req_mask; bar++) {
1654 if ((req_mask & (1 << bar)) == 0)
1655 continue;
1656 error = pci_request_region(pdev, bar, name);
1657 if (error != 0 && error != -ENODEV)
1658 goto err;
1659 requests |= (1 << bar);
1660 }
1661
1662 error = pcim_iomap_regions(pdev, mask, name);
1663 if (error != 0)
1664 goto err;
1665
1666 return (0);
1667
1668 err:
1669 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) {
1670 if ((requests & (1 << bar)) != 0)
1671 pci_release_region(pdev, bar);
1672 }
1673
1674 return (-EINVAL);
1675 }
1676
1677 /*
1678 * We cannot simply re-define pci_get_device() as we would normally do
1679 * and then hide it in linux_pci.c as too many semi-native drivers still
1680 * include linux/pci.h and run into the conflict with native PCI. Linux drivers
1681 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device().
1682 */
1683 static inline struct pci_dev *
linuxkpi_pci_get_device(uint16_t vendor,uint16_t device,struct pci_dev * odev)1684 linuxkpi_pci_get_device(uint16_t vendor, uint16_t device, struct pci_dev *odev)
1685 {
1686
1687 return (lkpi_pci_get_device(vendor, device, odev));
1688 }
1689
1690 /* This is a FreeBSD extension so we can use bus_*(). */
1691 static inline void
linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev * pdev)1692 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev)
1693 {
1694 pdev->want_iomap_res = true;
1695 }
1696
1697 static inline bool
pci_is_thunderbolt_attached(struct pci_dev * pdev)1698 pci_is_thunderbolt_attached(struct pci_dev *pdev)
1699 {
1700
1701 return (false);
1702 }
1703
1704 static inline void *
pci_platform_rom(struct pci_dev * pdev,size_t * size)1705 pci_platform_rom(struct pci_dev *pdev, size_t *size)
1706 {
1707
1708 return (NULL);
1709 }
1710
1711 static inline void
pci_ignore_hotplug(struct pci_dev * pdev)1712 pci_ignore_hotplug(struct pci_dev *pdev)
1713 {
1714 }
1715
1716 static inline int
pcie_get_readrq(struct pci_dev * dev)1717 pcie_get_readrq(struct pci_dev *dev)
1718 {
1719 u16 ctl;
1720
1721 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl))
1722 return (-EINVAL);
1723
1724 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12));
1725 }
1726
1727 static inline bool
pci_is_enabled(struct pci_dev * pdev)1728 pci_is_enabled(struct pci_dev *pdev)
1729 {
1730
1731 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) &
1732 PCIM_CMD_BUSMASTEREN) != 0);
1733 }
1734
1735 static inline int
pci_wait_for_pending_transaction(struct pci_dev * pdev)1736 pci_wait_for_pending_transaction(struct pci_dev *pdev)
1737 {
1738
1739 return (0);
1740 }
1741
1742 static inline int
pci_assign_resource(struct pci_dev * pdev,int bar)1743 pci_assign_resource(struct pci_dev *pdev, int bar)
1744 {
1745
1746 return (0);
1747 }
1748
1749 static inline int
pci_irq_vector(struct pci_dev * pdev,unsigned int vector)1750 pci_irq_vector(struct pci_dev *pdev, unsigned int vector)
1751 {
1752
1753 if (!pdev->msix_enabled && !pdev->msi_enabled) {
1754 if (vector != 0)
1755 return (-EINVAL);
1756 return (pdev->irq);
1757 }
1758
1759 if (pdev->msix_enabled || pdev->msi_enabled) {
1760 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end)
1761 return (-EINVAL);
1762 return (pdev->dev.irq_start + vector);
1763 }
1764
1765 return (-ENXIO);
1766 }
1767
1768 #endif /* _LINUXKPI_LINUX_PCI_H_ */
1769