1 /*-
2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD$
26 */
27
28 #include <linux/interrupt.h>
29 #include <linux/module.h>
30 #include <dev/mlx5/driver.h>
31 #include <dev/mlx5/mlx5_ifc.h>
32 #include "mlx5_core.h"
33
34 #include "opt_rss.h"
35
36 #ifdef RSS
37 #include <net/rss_config.h>
38 #include <netinet/in_rss.h>
39 #endif
40
41 enum {
42 MLX5_EQE_SIZE = sizeof(struct mlx5_eqe),
43 MLX5_EQE_OWNER_INIT_VAL = 0x1,
44 };
45
46 enum {
47 MLX5_NUM_SPARE_EQE = 0x80,
48 MLX5_NUM_ASYNC_EQE = 0x100,
49 MLX5_NUM_CMD_EQE = 32,
50 };
51
52 enum {
53 MLX5_EQ_DOORBEL_OFFSET = 0x40,
54 };
55
56 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \
57 (1ull << MLX5_EVENT_TYPE_COMM_EST) | \
58 (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \
59 (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \
60 (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \
61 (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \
62 (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
63 (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \
64 (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \
65 (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \
66 (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \
67 (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT))
68
69 struct map_eq_in {
70 u64 mask;
71 u32 reserved;
72 u32 unmap_eqn;
73 };
74
75 struct cre_des_eq {
76 u8 reserved[15];
77 u8 eqn;
78 };
79
80 /*Function prototype*/
81 static void mlx5_port_module_event(struct mlx5_core_dev *dev,
82 struct mlx5_eqe *eqe);
83
mlx5_cmd_destroy_eq(struct mlx5_core_dev * dev,u8 eqn)84 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn)
85 {
86 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)];
87 u32 out[MLX5_ST_SZ_DW(destroy_eq_out)];
88
89 memset(in, 0, sizeof(in));
90
91 MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ);
92 MLX5_SET(destroy_eq_in, in, eq_number, eqn);
93
94 memset(out, 0, sizeof(out));
95 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
96 out, sizeof(out));
97 }
98
get_eqe(struct mlx5_eq * eq,u32 entry)99 static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry)
100 {
101 return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE);
102 }
103
next_eqe_sw(struct mlx5_eq * eq)104 static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq)
105 {
106 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1));
107
108 return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe;
109 }
110
eqe_type_str(u8 type)111 static const char *eqe_type_str(u8 type)
112 {
113 switch (type) {
114 case MLX5_EVENT_TYPE_COMP:
115 return "MLX5_EVENT_TYPE_COMP";
116 case MLX5_EVENT_TYPE_PATH_MIG:
117 return "MLX5_EVENT_TYPE_PATH_MIG";
118 case MLX5_EVENT_TYPE_COMM_EST:
119 return "MLX5_EVENT_TYPE_COMM_EST";
120 case MLX5_EVENT_TYPE_SQ_DRAINED:
121 return "MLX5_EVENT_TYPE_SQ_DRAINED";
122 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
123 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE";
124 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
125 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT";
126 case MLX5_EVENT_TYPE_CQ_ERROR:
127 return "MLX5_EVENT_TYPE_CQ_ERROR";
128 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
129 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR";
130 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
131 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED";
132 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
133 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR";
134 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
135 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR";
136 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
137 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR";
138 case MLX5_EVENT_TYPE_INTERNAL_ERROR:
139 return "MLX5_EVENT_TYPE_INTERNAL_ERROR";
140 case MLX5_EVENT_TYPE_PORT_CHANGE:
141 return "MLX5_EVENT_TYPE_PORT_CHANGE";
142 case MLX5_EVENT_TYPE_GPIO_EVENT:
143 return "MLX5_EVENT_TYPE_GPIO_EVENT";
144 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT:
145 return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT";
146 case MLX5_EVENT_TYPE_REMOTE_CONFIG:
147 return "MLX5_EVENT_TYPE_REMOTE_CONFIG";
148 case MLX5_EVENT_TYPE_DB_BF_CONGESTION:
149 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION";
150 case MLX5_EVENT_TYPE_STALL_EVENT:
151 return "MLX5_EVENT_TYPE_STALL_EVENT";
152 case MLX5_EVENT_TYPE_CMD:
153 return "MLX5_EVENT_TYPE_CMD";
154 case MLX5_EVENT_TYPE_PAGE_REQUEST:
155 return "MLX5_EVENT_TYPE_PAGE_REQUEST";
156 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
157 return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE";
158 default:
159 return "Unrecognized event";
160 }
161 }
162
port_subtype_event(u8 subtype)163 static enum mlx5_dev_event port_subtype_event(u8 subtype)
164 {
165 switch (subtype) {
166 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
167 return MLX5_DEV_EVENT_PORT_DOWN;
168 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
169 return MLX5_DEV_EVENT_PORT_UP;
170 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
171 return MLX5_DEV_EVENT_PORT_INITIALIZED;
172 case MLX5_PORT_CHANGE_SUBTYPE_LID:
173 return MLX5_DEV_EVENT_LID_CHANGE;
174 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
175 return MLX5_DEV_EVENT_PKEY_CHANGE;
176 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
177 return MLX5_DEV_EVENT_GUID_CHANGE;
178 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
179 return MLX5_DEV_EVENT_CLIENT_REREG;
180 }
181 return -1;
182 }
183
eq_update_ci(struct mlx5_eq * eq,int arm)184 static void eq_update_ci(struct mlx5_eq *eq, int arm)
185 {
186 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
187 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
188 __raw_writel((__force u32) cpu_to_be32(val), addr);
189 /* We still want ordering, just not swabbing, so add a barrier */
190 mb();
191 }
192
mlx5_eq_int(struct mlx5_core_dev * dev,struct mlx5_eq * eq)193 static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
194 {
195 struct mlx5_eqe *eqe;
196 int eqes_found = 0;
197 int set_ci = 0;
198 u32 cqn;
199 u32 rsn;
200 u8 port;
201
202 while ((eqe = next_eqe_sw(eq))) {
203 /*
204 * Make sure we read EQ entry contents after we've
205 * checked the ownership bit.
206 */
207 rmb();
208
209 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n",
210 eq->eqn, eqe_type_str(eqe->type));
211 switch (eqe->type) {
212 case MLX5_EVENT_TYPE_COMP:
213 cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff;
214 mlx5_cq_completion(dev, cqn);
215 break;
216
217 case MLX5_EVENT_TYPE_PATH_MIG:
218 case MLX5_EVENT_TYPE_COMM_EST:
219 case MLX5_EVENT_TYPE_SQ_DRAINED:
220 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
221 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
222 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
223 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
224 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
225 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
226 mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n",
227 eqe_type_str(eqe->type), eqe->type, rsn);
228 mlx5_rsc_event(dev, rsn, eqe->type);
229 break;
230
231 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
232 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
233 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
234 mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n",
235 eqe_type_str(eqe->type), eqe->type, rsn);
236 mlx5_srq_event(dev, rsn, eqe->type);
237 break;
238
239 case MLX5_EVENT_TYPE_CMD:
240 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector));
241 break;
242
243 case MLX5_EVENT_TYPE_PORT_CHANGE:
244 port = (eqe->data.port.port >> 4) & 0xf;
245 switch (eqe->sub_type) {
246 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
247 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
248 case MLX5_PORT_CHANGE_SUBTYPE_LID:
249 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
250 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
251 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
252 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
253 if (dev->event)
254 dev->event(dev, port_subtype_event(eqe->sub_type),
255 (unsigned long)port);
256 break;
257 default:
258 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n",
259 port, eqe->sub_type);
260 }
261 break;
262 case MLX5_EVENT_TYPE_CQ_ERROR:
263 cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
264 mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n",
265 cqn, eqe->data.cq_err.syndrome);
266 mlx5_cq_event(dev, cqn, eqe->type);
267 break;
268
269 case MLX5_EVENT_TYPE_PAGE_REQUEST:
270 {
271 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id);
272 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages);
273
274 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n",
275 func_id, npages);
276 mlx5_core_req_pages_handler(dev, func_id, npages);
277 }
278 break;
279
280 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT:
281 mlx5_port_module_event(dev, eqe);
282 break;
283
284 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
285 {
286 struct mlx5_eqe_vport_change *vc_eqe =
287 &eqe->data.vport_change;
288 u16 vport_num = be16_to_cpu(vc_eqe->vport_num);
289
290 if (dev->event)
291 dev->event(dev,
292 MLX5_DEV_EVENT_VPORT_CHANGE,
293 (unsigned long)vport_num);
294 }
295 break;
296
297 default:
298 mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",
299 eqe->type, eq->eqn);
300 break;
301 }
302
303 ++eq->cons_index;
304 eqes_found = 1;
305 ++set_ci;
306
307 /* The HCA will think the queue has overflowed if we
308 * don't tell it we've been processing events. We
309 * create our EQs with MLX5_NUM_SPARE_EQE extra
310 * entries, so we must update our consumer index at
311 * least that often.
312 */
313 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
314 eq_update_ci(eq, 0);
315 set_ci = 0;
316 }
317 }
318
319 eq_update_ci(eq, 1);
320
321 return eqes_found;
322 }
323
mlx5_msix_handler(int irq,void * eq_ptr)324 static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr)
325 {
326 struct mlx5_eq *eq = eq_ptr;
327 struct mlx5_core_dev *dev = eq->dev;
328
329 mlx5_eq_int(dev, eq);
330
331 /* MSI-X vectors always belong to us */
332 return IRQ_HANDLED;
333 }
334
init_eq_buf(struct mlx5_eq * eq)335 static void init_eq_buf(struct mlx5_eq *eq)
336 {
337 struct mlx5_eqe *eqe;
338 int i;
339
340 for (i = 0; i < eq->nent; i++) {
341 eqe = get_eqe(eq, i);
342 eqe->owner = MLX5_EQE_OWNER_INIT_VAL;
343 }
344 }
345
mlx5_create_map_eq(struct mlx5_core_dev * dev,struct mlx5_eq * eq,u8 vecidx,int nent,u64 mask,const char * name,struct mlx5_uar * uar)346 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
347 int nent, u64 mask, const char *name, struct mlx5_uar *uar)
348 {
349 struct mlx5_priv *priv = &dev->priv;
350 struct mlx5_create_eq_mbox_in *in;
351 struct mlx5_create_eq_mbox_out out;
352 int err;
353 int inlen;
354
355 eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE);
356 err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, 2 * PAGE_SIZE,
357 &eq->buf);
358 if (err)
359 return err;
360
361 init_eq_buf(eq);
362
363 inlen = sizeof(*in) + sizeof(in->pas[0]) * eq->buf.npages;
364 in = mlx5_vzalloc(inlen);
365 if (!in) {
366 err = -ENOMEM;
367 goto err_buf;
368 }
369 memset(&out, 0, sizeof(out));
370
371 mlx5_fill_page_array(&eq->buf, in->pas);
372
373 in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_CREATE_EQ);
374 in->ctx.log_sz_usr_page = cpu_to_be32(ilog2(eq->nent) << 24 | uar->index);
375 in->ctx.intr = vecidx;
376 in->ctx.log_page_size = eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT;
377 in->events_mask = cpu_to_be64(mask);
378
379 err = mlx5_cmd_exec(dev, in, inlen, &out, sizeof(out));
380 if (err)
381 goto err_in;
382
383 if (out.hdr.status) {
384 err = mlx5_cmd_status_to_err(&out.hdr);
385 goto err_in;
386 }
387
388 eq->eqn = out.eq_number;
389 eq->irqn = vecidx;
390 eq->dev = dev;
391 eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET;
392 snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s",
393 name, pci_name(dev->pdev));
394 err = request_irq(priv->msix_arr[vecidx].vector, mlx5_msix_handler, 0,
395 priv->irq_info[vecidx].name, eq);
396 if (err)
397 goto err_eq;
398 #ifdef RSS
399 if (vecidx >= MLX5_EQ_VEC_COMP_BASE) {
400 u8 bucket = vecidx - MLX5_EQ_VEC_COMP_BASE;
401 err = bind_irq_to_cpu(priv->msix_arr[vecidx].vector,
402 rss_getcpu(bucket % rss_getnumbuckets()));
403 if (err)
404 goto err_irq;
405 }
406 #else
407 if (0)
408 goto err_irq;
409 #endif
410
411
412 /* EQs are created in ARMED state
413 */
414 eq_update_ci(eq, 1);
415
416 kvfree(in);
417 return 0;
418
419 err_irq:
420 free_irq(priv->msix_arr[vecidx].vector, eq);
421
422 err_eq:
423 mlx5_cmd_destroy_eq(dev, eq->eqn);
424
425 err_in:
426 kvfree(in);
427
428 err_buf:
429 mlx5_buf_free(dev, &eq->buf);
430 return err;
431 }
432 EXPORT_SYMBOL_GPL(mlx5_create_map_eq);
433
mlx5_destroy_unmap_eq(struct mlx5_core_dev * dev,struct mlx5_eq * eq)434 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
435 {
436 int err;
437
438 free_irq(dev->priv.msix_arr[eq->irqn].vector, eq);
439 err = mlx5_cmd_destroy_eq(dev, eq->eqn);
440 if (err)
441 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
442 eq->eqn);
443 mlx5_buf_free(dev, &eq->buf);
444
445 return err;
446 }
447 EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq);
448
mlx5_eq_init(struct mlx5_core_dev * dev)449 int mlx5_eq_init(struct mlx5_core_dev *dev)
450 {
451 int err;
452
453 spin_lock_init(&dev->priv.eq_table.lock);
454
455 err = 0;
456
457 return err;
458 }
459
460
mlx5_eq_cleanup(struct mlx5_core_dev * dev)461 void mlx5_eq_cleanup(struct mlx5_core_dev *dev)
462 {
463 }
464
mlx5_start_eqs(struct mlx5_core_dev * dev)465 int mlx5_start_eqs(struct mlx5_core_dev *dev)
466 {
467 struct mlx5_eq_table *table = &dev->priv.eq_table;
468 u32 async_event_mask = MLX5_ASYNC_EVENT_MASK;
469 int err;
470
471 if (MLX5_CAP_GEN(dev, port_module_event))
472 async_event_mask |= (1ull <<
473 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT);
474
475 if (MLX5_CAP_GEN(dev, nic_vport_change_event))
476 async_event_mask |= (1ull <<
477 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE);
478
479 err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,
480 MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD,
481 "mlx5_cmd_eq", &dev->priv.uuari.uars[0]);
482 if (err) {
483 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err);
484 return err;
485 }
486
487 mlx5_cmd_use_events(dev);
488
489 err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC,
490 MLX5_NUM_ASYNC_EQE, async_event_mask,
491 "mlx5_async_eq", &dev->priv.uuari.uars[0]);
492 if (err) {
493 mlx5_core_warn(dev, "failed to create async EQ %d\n", err);
494 goto err1;
495 }
496
497 err = mlx5_create_map_eq(dev, &table->pages_eq,
498 MLX5_EQ_VEC_PAGES,
499 /* TODO: sriov max_vf + */ 1,
500 1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq",
501 &dev->priv.uuari.uars[0]);
502 if (err) {
503 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err);
504 goto err2;
505 }
506
507 return err;
508
509 err2:
510 mlx5_destroy_unmap_eq(dev, &table->async_eq);
511
512 err1:
513 mlx5_cmd_use_polling(dev);
514 mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
515 return err;
516 }
517
mlx5_stop_eqs(struct mlx5_core_dev * dev)518 int mlx5_stop_eqs(struct mlx5_core_dev *dev)
519 {
520 struct mlx5_eq_table *table = &dev->priv.eq_table;
521 int err;
522
523 err = mlx5_destroy_unmap_eq(dev, &table->pages_eq);
524 if (err)
525 return err;
526
527 mlx5_destroy_unmap_eq(dev, &table->async_eq);
528 mlx5_cmd_use_polling(dev);
529
530 err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
531 if (err)
532 mlx5_cmd_use_events(dev);
533
534 return err;
535 }
536
mlx5_core_eq_query(struct mlx5_core_dev * dev,struct mlx5_eq * eq,struct mlx5_query_eq_mbox_out * out,int outlen)537 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
538 struct mlx5_query_eq_mbox_out *out, int outlen)
539 {
540 struct mlx5_query_eq_mbox_in in;
541 int err;
542
543 memset(&in, 0, sizeof(in));
544 memset(out, 0, outlen);
545 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_EQ);
546 in.eqn = eq->eqn;
547 err = mlx5_cmd_exec(dev, &in, sizeof(in), out, outlen);
548 if (err)
549 return err;
550
551 if (out->hdr.status)
552 err = mlx5_cmd_status_to_err(&out->hdr);
553
554 return err;
555 }
556
557 EXPORT_SYMBOL_GPL(mlx5_core_eq_query);
558
mlx5_port_module_event_error_type_to_string(u8 error_type)559 static const char *mlx5_port_module_event_error_type_to_string(u8 error_type)
560 {
561 switch (error_type) {
562 case MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED:
563 return "Power Budget Exceeded";
564 case MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE:
565 return "Long Range for non MLNX cable/module";
566 case MLX5_MODULE_EVENT_ERROR_BUS_STUCK:
567 return "Bus stuck(I2C or data shorted)";
568 case MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT:
569 return "No EEPROM/retry timeout";
570 case MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST:
571 return "Enforce part number list";
572 case MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER:
573 return "Unknown identifier";
574 case MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE:
575 return "High Temperature";
576
577 default:
578 return "Unknown error type";
579 }
580 }
581
mlx5_port_module_event(struct mlx5_core_dev * dev,struct mlx5_eqe * eqe)582 static void mlx5_port_module_event(struct mlx5_core_dev *dev,
583 struct mlx5_eqe *eqe)
584 {
585 unsigned int module_num;
586 unsigned int module_status;
587 unsigned int error_type;
588 struct mlx5_eqe_port_module_event *module_event_eqe;
589 struct pci_dev *pdev = dev->pdev;
590
591 module_event_eqe = &eqe->data.port_module_event;
592
593 module_num = (unsigned int)module_event_eqe->module;
594 module_status = (unsigned int)module_event_eqe->module_status &
595 PORT_MODULE_EVENT_MODULE_STATUS_MASK;
596 error_type = (unsigned int)module_event_eqe->error_type &
597 PORT_MODULE_EVENT_ERROR_TYPE_MASK;
598
599 switch (module_status) {
600 case MLX5_MODULE_STATUS_PLUGGED:
601 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: plugged", module_num);
602 break;
603
604 case MLX5_MODULE_STATUS_UNPLUGGED:
605 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: unplugged", module_num);
606 break;
607
608 case MLX5_MODULE_STATUS_ERROR:
609 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: error, %s", module_num, mlx5_port_module_event_error_type_to_string(error_type));
610 break;
611
612 default:
613 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, unknown status", module_num);
614 }
615 }
616
617