1 /*-
2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD$
26 */
27
28 #ifndef MLX5_IB_H
29 #define MLX5_IB_H
30
31 #include <linux/kernel.h>
32 #include <linux/sched.h>
33 #include <linux/printk.h>
34 #include <rdma/ib_verbs.h>
35 #include <rdma/ib_smi.h>
36 #include <dev/mlx5/cq.h>
37 #include <dev/mlx5/qp.h>
38 #include <dev/mlx5/srq.h>
39 #include <linux/types.h>
40 #include <dev/mlx5/mlx5_core/transobj.h>
41 #include <rdma/ib_user_verbs.h>
42 #include <rdma/mlx5-abi.h>
43
44 #define mlx5_ib_dbg(dev, format, arg...) \
45 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
46 __LINE__, current->pid, ##arg)
47
48 #define mlx5_ib_err(dev, format, arg...) \
49 pr_err("%s: ERR: %s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
50 __LINE__, current->pid, ##arg)
51
52 #define mlx5_ib_warn(dev, format, arg...) \
53 pr_warn("%s: WARN: %s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
54 __LINE__, current->pid, ##arg)
55
56 #define field_avail(type, fld, sz) (offsetof(type, fld) + \
57 sizeof(((type *)0)->fld) <= (sz))
58 #define MLX5_IB_DEFAULT_UIDX 0xffffff
59 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
60
61 enum {
62 MLX5_IB_MMAP_CMD_SHIFT = 8,
63 MLX5_IB_MMAP_CMD_MASK = 0xff,
64 };
65
66 enum mlx5_ib_mmap_cmd {
67 MLX5_IB_MMAP_REGULAR_PAGE = 0,
68 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1,
69 MLX5_IB_MMAP_WC_PAGE = 2,
70 MLX5_IB_MMAP_NC_PAGE = 3,
71 /* 5 is chosen in order to be compatible with old versions of libmlx5 */
72 MLX5_IB_MMAP_CORE_CLOCK = 5,
73 };
74
75 enum {
76 MLX5_RES_SCAT_DATA32_CQE = 0x1,
77 MLX5_RES_SCAT_DATA64_CQE = 0x2,
78 MLX5_REQ_SCAT_DATA32_CQE = 0x11,
79 MLX5_REQ_SCAT_DATA64_CQE = 0x22,
80 };
81
82 enum mlx5_ib_latency_class {
83 MLX5_IB_LATENCY_CLASS_LOW,
84 MLX5_IB_LATENCY_CLASS_MEDIUM,
85 MLX5_IB_LATENCY_CLASS_HIGH,
86 MLX5_IB_LATENCY_CLASS_FAST_PATH
87 };
88
89 enum mlx5_ib_mad_ifc_flags {
90 MLX5_MAD_IFC_IGNORE_MKEY = 1,
91 MLX5_MAD_IFC_IGNORE_BKEY = 2,
92 MLX5_MAD_IFC_NET_VIEW = 4,
93 };
94
95 enum {
96 MLX5_CROSS_CHANNEL_UUAR = 0,
97 };
98
99 enum {
100 MLX5_CQE_VERSION_V0,
101 MLX5_CQE_VERSION_V1,
102 };
103
104 struct mlx5_ib_vma_private_data {
105 struct list_head list;
106 struct vm_area_struct *vma;
107 };
108
109 struct mlx5_ib_ucontext {
110 struct ib_ucontext ibucontext;
111 struct list_head db_page_list;
112
113 /* protect doorbell record alloc/free
114 */
115 struct mutex db_page_mutex;
116 struct mlx5_uuar_info uuari;
117 u8 cqe_version;
118 /* Transport Domain number */
119 u32 tdn;
120 struct list_head vma_private_list;
121 };
122
to_mucontext(struct ib_ucontext * ibucontext)123 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
124 {
125 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext);
126 }
127
128 struct mlx5_ib_pd {
129 struct ib_pd ibpd;
130 u32 pdn;
131 };
132
133 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1)
134 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1)
135 #if (MLX5_IB_FLOW_LAST_PRIO <= 0)
136 #error "Invalid number of bypass priorities"
137 #endif
138 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1)
139
140 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1)
141 #define MLX5_IB_NUM_SNIFFER_FTS 2
142 struct mlx5_ib_flow_prio {
143 struct mlx5_flow_table *flow_table;
144 unsigned int refcount;
145 };
146
147 struct mlx5_ib_flow_handler {
148 struct list_head list;
149 struct ib_flow ibflow;
150 struct mlx5_ib_flow_prio *prio;
151 struct mlx5_flow_rule *rule;
152 };
153
154 struct mlx5_ib_flow_db {
155 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT];
156 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS];
157 struct mlx5_flow_table *lag_demux_ft;
158 /* Protect flow steering bypass flow tables
159 * when add/del flow rules.
160 * only single add/removal of flow steering rule could be done
161 * simultaneously.
162 */
163 struct mutex lock;
164 };
165
166 /* Use macros here so that don't have to duplicate
167 * enum ib_send_flags and enum ib_qp_type for low-level driver
168 */
169
170 #define MLX5_IB_SEND_UMR_UNREG IB_SEND_RESERVED_START
171 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 1)
172 #define MLX5_IB_SEND_UMR_UPDATE_MTT (IB_SEND_RESERVED_START << 2)
173
174 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 3)
175 #define MLX5_IB_SEND_UMR_UPDATE_PD (IB_SEND_RESERVED_START << 4)
176 #define MLX5_IB_SEND_UMR_UPDATE_ACCESS IB_SEND_RESERVED_END
177
178 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1
179 /*
180 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI
181 * creates the actual hardware QP.
182 */
183 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2
184 #define MLX5_IB_WR_UMR IB_WR_RESERVED1
185
186 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags.
187 *
188 * These flags are intended for internal use by the mlx5_ib driver, and they
189 * rely on the range reserved for that use in the ib_qp_create_flags enum.
190 */
191
192 /* Create a UD QP whose source QP number is 1 */
mlx5_ib_create_qp_sqpn_qp1(void)193 static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void)
194 {
195 return IB_QP_CREATE_RESERVED_START;
196 }
197
198 struct wr_list {
199 u16 opcode;
200 u16 next;
201 };
202
203 struct mlx5_ib_wq {
204 u64 *wrid;
205 u32 *wr_data;
206 struct wr_list *w_list;
207 unsigned *wqe_head;
208 u16 unsig_count;
209
210 /* serialize post to the work queue
211 */
212 spinlock_t lock;
213 int wqe_cnt;
214 int max_post;
215 int max_gs;
216 int offset;
217 int wqe_shift;
218 unsigned head;
219 unsigned tail;
220 u16 cur_post;
221 u16 last_poll;
222 void *qend;
223 };
224
225 struct mlx5_ib_rwq {
226 struct ib_wq ibwq;
227 struct mlx5_core_qp core_qp;
228 u32 rq_num_pas;
229 u32 log_rq_stride;
230 u32 log_rq_size;
231 u32 rq_page_offset;
232 u32 log_page_size;
233 struct ib_umem *umem;
234 size_t buf_size;
235 unsigned int page_shift;
236 int create_type;
237 struct mlx5_db db;
238 u32 user_index;
239 u32 wqe_count;
240 u32 wqe_shift;
241 int wq_sig;
242 };
243
244 enum {
245 MLX5_QP_USER,
246 MLX5_QP_KERNEL,
247 MLX5_QP_EMPTY
248 };
249
250 enum {
251 MLX5_WQ_USER,
252 MLX5_WQ_KERNEL
253 };
254
255 struct mlx5_ib_rwq_ind_table {
256 struct ib_rwq_ind_table ib_rwq_ind_tbl;
257 u32 rqtn;
258 };
259
260 /*
261 * Connect-IB can trigger up to four concurrent pagefaults
262 * per-QP.
263 */
264 enum mlx5_ib_pagefault_context {
265 MLX5_IB_PAGEFAULT_RESPONDER_READ,
266 MLX5_IB_PAGEFAULT_REQUESTOR_READ,
267 MLX5_IB_PAGEFAULT_RESPONDER_WRITE,
268 MLX5_IB_PAGEFAULT_REQUESTOR_WRITE,
269 MLX5_IB_PAGEFAULT_CONTEXTS
270 };
271
272 static inline enum mlx5_ib_pagefault_context
mlx5_ib_get_pagefault_context(struct mlx5_pagefault * pagefault)273 mlx5_ib_get_pagefault_context(struct mlx5_pagefault *pagefault)
274 {
275 return pagefault->flags & (MLX5_PFAULT_REQUESTOR | MLX5_PFAULT_WRITE);
276 }
277
278 struct mlx5_ib_pfault {
279 struct work_struct work;
280 struct mlx5_pagefault mpfault;
281 };
282
283 struct mlx5_ib_ubuffer {
284 struct ib_umem *umem;
285 int buf_size;
286 u64 buf_addr;
287 };
288
289 struct mlx5_ib_qp_base {
290 struct mlx5_ib_qp *container_mibqp;
291 struct mlx5_core_qp mqp;
292 struct mlx5_ib_ubuffer ubuffer;
293 };
294
295 struct mlx5_ib_qp_trans {
296 struct mlx5_ib_qp_base base;
297 u16 xrcdn;
298 u8 alt_port;
299 u8 atomic_rd_en;
300 u8 resp_depth;
301 };
302
303 struct mlx5_ib_rss_qp {
304 u32 tirn;
305 };
306
307 struct mlx5_ib_rq {
308 struct mlx5_ib_qp_base base;
309 struct mlx5_ib_wq *rq;
310 struct mlx5_ib_ubuffer ubuffer;
311 struct mlx5_db *doorbell;
312 u32 tirn;
313 u8 state;
314 };
315
316 struct mlx5_ib_sq {
317 struct mlx5_ib_qp_base base;
318 struct mlx5_ib_wq *sq;
319 struct mlx5_ib_ubuffer ubuffer;
320 struct mlx5_db *doorbell;
321 u32 tisn;
322 u8 state;
323 };
324
325 struct mlx5_ib_raw_packet_qp {
326 struct mlx5_ib_sq sq;
327 struct mlx5_ib_rq rq;
328 };
329
330 struct mlx5_ib_qp {
331 struct ib_qp ibqp;
332 union {
333 struct mlx5_ib_qp_trans trans_qp;
334 struct mlx5_ib_raw_packet_qp raw_packet_qp;
335 struct mlx5_ib_rss_qp rss_qp;
336 };
337 struct mlx5_buf buf;
338
339 struct mlx5_db db;
340 struct mlx5_ib_wq rq;
341
342 u8 sq_signal_bits;
343 u8 fm_cache;
344 struct mlx5_ib_wq sq;
345
346 /* serialize qp state modifications
347 */
348 struct mutex mutex;
349 u32 flags;
350 u8 port;
351 u8 state;
352 int wq_sig;
353 int scat_cqe;
354 int max_inline_data;
355 struct mlx5_bf *bf;
356 int has_rq;
357
358 /* only for user space QPs. For kernel
359 * we have it from the bf object
360 */
361 int uuarn;
362
363 int create_type;
364
365 /* Store signature errors */
366 bool signature_en;
367
368 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
369 /*
370 * A flag that is true for QP's that are in a state that doesn't
371 * allow page faults, and shouldn't schedule any more faults.
372 */
373 int disable_page_faults;
374 /*
375 * The disable_page_faults_lock protects a QP's disable_page_faults
376 * field, allowing for a thread to atomically check whether the QP
377 * allows page faults, and if so schedule a page fault.
378 */
379 spinlock_t disable_page_faults_lock;
380 struct mlx5_ib_pfault pagefaults[MLX5_IB_PAGEFAULT_CONTEXTS];
381 #endif
382 struct list_head qps_list;
383 struct list_head cq_recv_list;
384 struct list_head cq_send_list;
385 };
386
387 struct mlx5_ib_cq_buf {
388 struct mlx5_buf buf;
389 struct ib_umem *umem;
390 int cqe_size;
391 int nent;
392 };
393
394 enum mlx5_ib_qp_flags {
395 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO,
396 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK,
397 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL,
398 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND,
399 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV,
400 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5,
401 /* QP uses 1 as its source QP number */
402 MLX5_IB_QP_SQPN_QP1 = 1 << 6,
403 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7,
404 MLX5_IB_QP_RSS = 1 << 8,
405 };
406
407 struct mlx5_umr_wr {
408 struct ib_send_wr wr;
409 union {
410 u64 virt_addr;
411 u64 offset;
412 } target;
413 struct ib_pd *pd;
414 unsigned int page_shift;
415 unsigned int npages;
416 u32 length;
417 int access_flags;
418 u32 mkey;
419 };
420
umr_wr(struct ib_send_wr * wr)421 static inline struct mlx5_umr_wr *umr_wr(struct ib_send_wr *wr)
422 {
423 return container_of(wr, struct mlx5_umr_wr, wr);
424 }
425
426 struct mlx5_shared_mr_info {
427 int mr_id;
428 struct ib_umem *umem;
429 };
430
431 struct mlx5_ib_cq {
432 struct ib_cq ibcq;
433 struct mlx5_core_cq mcq;
434 struct mlx5_ib_cq_buf buf;
435 struct mlx5_db db;
436
437 /* serialize access to the CQ
438 */
439 spinlock_t lock;
440
441 /* protect resize cq
442 */
443 struct mutex resize_mutex;
444 struct mlx5_ib_cq_buf *resize_buf;
445 struct ib_umem *resize_umem;
446 int cqe_size;
447 struct list_head list_send_qp;
448 struct list_head list_recv_qp;
449 u32 create_flags;
450 struct list_head wc_list;
451 enum ib_cq_notify_flags notify_flags;
452 struct work_struct notify_work;
453 };
454
455 struct mlx5_ib_wc {
456 struct ib_wc wc;
457 struct list_head list;
458 };
459
460 struct mlx5_ib_srq {
461 struct ib_srq ibsrq;
462 struct mlx5_core_srq msrq;
463 struct mlx5_buf buf;
464 struct mlx5_db db;
465 u64 *wrid;
466 /* protect SRQ hanlding
467 */
468 spinlock_t lock;
469 int head;
470 int tail;
471 u16 wqe_ctr;
472 struct ib_umem *umem;
473 /* serialize arming a SRQ
474 */
475 struct mutex mutex;
476 int wq_sig;
477 };
478
479 struct mlx5_ib_xrcd {
480 struct ib_xrcd ibxrcd;
481 u32 xrcdn;
482 };
483
484 enum mlx5_ib_mtt_access_flags {
485 MLX5_IB_MTT_READ = (1 << 0),
486 MLX5_IB_MTT_WRITE = (1 << 1),
487 };
488
489 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
490
491 struct mlx5_ib_mr {
492 struct ib_mr ibmr;
493 void *descs;
494 dma_addr_t desc_map;
495 int ndescs;
496 int max_descs;
497 int desc_size;
498 int access_mode;
499 struct mlx5_core_mr mmkey;
500 struct ib_umem *umem;
501 struct mlx5_shared_mr_info *smr_info;
502 struct list_head list;
503 int order;
504 int umred;
505 int npages;
506 struct mlx5_ib_dev *dev;
507 u32 out[MLX5_ST_SZ_DW(create_mkey_out)];
508 struct mlx5_core_sig_ctx *sig;
509 int live;
510 void *descs_alloc;
511 int access_flags; /* Needed for rereg MR */
512 struct mlx5_async_work cb_work;
513 };
514
515 struct mlx5_ib_mw {
516 struct ib_mw ibmw;
517 struct mlx5_core_mr mmkey;
518 };
519
520 struct mlx5_ib_umr_context {
521 struct ib_cqe cqe;
522 enum ib_wc_status status;
523 struct completion done;
524 };
525
526 struct umr_common {
527 struct ib_pd *pd;
528 struct ib_cq *cq;
529 struct ib_qp *qp;
530 /* control access to UMR QP
531 */
532 struct semaphore sem;
533 };
534
535 enum {
536 MLX5_FMR_INVALID,
537 MLX5_FMR_VALID,
538 MLX5_FMR_BUSY,
539 };
540
541 struct mlx5_cache_ent {
542 struct list_head head;
543 /* sync access to the cahce entry
544 */
545 spinlock_t lock;
546
547
548 struct dentry *dir;
549 char name[4];
550 u32 order;
551 u32 size;
552 u32 cur;
553 u32 miss;
554 u32 limit;
555
556 struct dentry *fsize;
557 struct dentry *fcur;
558 struct dentry *fmiss;
559 struct dentry *flimit;
560
561 struct mlx5_ib_dev *dev;
562 struct work_struct work;
563 struct delayed_work dwork;
564 int pending;
565 };
566
567 struct mlx5_mr_cache {
568 struct workqueue_struct *wq;
569 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES];
570 int stopped;
571 struct dentry *root;
572 unsigned long last_add;
573 };
574
575 struct mlx5_ib_gsi_qp;
576
577 struct mlx5_ib_port_resources {
578 struct mlx5_ib_resources *devr;
579 struct mlx5_ib_gsi_qp *gsi;
580 struct work_struct pkey_change_work;
581 };
582
583 struct mlx5_ib_resources {
584 struct ib_cq *c0;
585 struct ib_xrcd *x0;
586 struct ib_xrcd *x1;
587 struct ib_pd *p0;
588 struct ib_srq *s0;
589 struct ib_srq *s1;
590 struct mlx5_ib_port_resources ports[2];
591 /* Protects changes to the port resources */
592 struct mutex mutex;
593 };
594
595 struct mlx5_ib_port {
596 u16 q_cnt_id;
597 };
598
599 struct mlx5_roce {
600 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL
601 * netdev pointer
602 */
603 rwlock_t netdev_lock;
604 struct net_device *netdev;
605 struct notifier_block nb;
606 atomic_t next_port;
607 };
608
609 #define MLX5_IB_STATS_COUNT(a,b,c,d) a
610 #define MLX5_IB_STATS_VAR(a,b,c,d) b;
611 #define MLX5_IB_STATS_DESC(a,b,c,d) c, d,
612
613 #define MLX5_IB_CONG_PARAMS(m) \
614 /* ECN RP */ \
615 m(+1, u64 rp_clamp_tgt_rate, "rp_clamp_tgt_rate", "If set, whenever a CNP is processed, the target rate is updated to be the current rate") \
616 m(+1, u64 rp_clamp_tgt_rate_ati, "rp_clamp_tgt_rate_ati", "If set, when receiving a CNP, the target rate should be updated if the transission rate was increased due to the timer, and not only due to the byte counter") \
617 m(+1, u64 rp_time_reset, "rp_time_reset", "Time in microseconds between rate increases if no CNPs are received") \
618 m(+1, u64 rp_byte_reset, "rp_byte_reset", "Transmitted data in bytes between rate increases if no CNP's are received. A value of zero means disabled.") \
619 m(+1, u64 rp_threshold, "rp_threshold", "The number of times rpByteStage or rpTimeStage can count before the RP rate control state machine advances states") \
620 m(+1, u64 rp_ai_rate, "rp_ai_rate", "The rate, in Mbits per second, used to increase rpTargetRate in the active increase state") \
621 m(+1, u64 rp_hai_rate, "rp_hai_rate", "The rate, in Mbits per second, used to increase rpTargetRate in the hyper increase state") \
622 m(+1, u64 rp_min_dec_fac, "rp_min_dec_fac", "The minimum factor by which the current transmit rate can be changed when processing a CNP. Value is given as a percentage, [1 .. 100]") \
623 m(+1, u64 rp_min_rate, "rp_min_rate", "The minimum value, in Mbps per second, for rate to limit") \
624 m(+1, u64 rp_rate_to_set_on_first_cnp, "rp_rate_to_set_on_first_cnp", "The rate that is set for the flow when a rate limiter is allocated to it upon first CNP received, in Mbps. A value of zero means use full port speed") \
625 m(+1, u64 rp_dce_tcp_g, "rp_dce_tcp_g", "Used to update the congestion estimator, alpha, once every dce_tcp_rtt once every dce_tcp_rtt microseconds") \
626 m(+1, u64 rp_dce_tcp_rtt, "rp_dce_tcp_rtt", "The time between updates of the aolpha value, in microseconds") \
627 m(+1, u64 rp_rate_reduce_monitor_period, "rp_rate_reduce_monitor_period", "The minimum time between two consecutive rate reductions for a single flow") \
628 m(+1, u64 rp_initial_alpha_value, "rp_initial_alpha_value", "The initial value of alpha to use when receiving the first CNP for a flow") \
629 m(+1, u64 rp_gd, "rp_gd", "If a CNP is received, the flow rate is reduced at the beginning of the next rate_reduce_monitor_period interval") \
630 /* ECN NP */ \
631 m(+1, u64 np_cnp_dscp, "np_cnp_dscp", "The DiffServ Code Point of the generated CNP for this port") \
632 m(+1, u64 np_cnp_prio_mode, "np_cnp_prio_mode", "The 802.1p priority value of the generated CNP for this port") \
633 m(+1, u64 np_cnp_prio, "np_cnp_prio", "The 802.1p priority value of the generated CNP for this port")
634
635 #define MLX5_IB_CONG_PARAMS_NUM (0 MLX5_IB_CONG_PARAMS(MLX5_IB_STATS_COUNT))
636
637 #define MLX5_IB_CONG_STATS(m) \
638 m(+1, u64 syndrome, "syndrome", "Syndrome number") \
639 m(+1, u64 rp_cur_flows, "rp_cur_flows", "Number of flows limited") \
640 m(+1, u64 sum_flows, "sum_flows", "Sum of the number of flows limited over time") \
641 m(+1, u64 rp_cnp_ignored, "rp_cnp_ignored", "Number of CNPs and CNMs ignored") \
642 m(+1, u64 rp_cnp_handled, "rp_cnp_handled", "Number of CNPs and CNMs successfully handled") \
643 m(+1, u64 time_stamp, "time_stamp", "Time stamp in microseconds") \
644 m(+1, u64 accumulators_period, "accumulators_period", "The value of X variable for accumulating counters") \
645 m(+1, u64 np_ecn_marked_roce_packets, "np_ecn_marked_roce_packets", "Number of ECN marked packets seen") \
646 m(+1, u64 np_cnp_sent, "np_cnp_sent", "Number of CNPs sent")
647
648 #define MLX5_IB_CONG_STATS_NUM (0 MLX5_IB_CONG_STATS(MLX5_IB_STATS_COUNT))
649
650 struct mlx5_ib_congestion {
651 struct sysctl_ctx_list ctx;
652 struct sx lock;
653 struct delayed_work dwork;
654 union {
655 u64 arg[1];
656 struct {
657 MLX5_IB_CONG_PARAMS(MLX5_IB_STATS_VAR)
658 MLX5_IB_CONG_STATS(MLX5_IB_STATS_VAR)
659 };
660 };
661 };
662
663 struct mlx5_ib_dev {
664 struct ib_device ib_dev;
665 struct mlx5_core_dev *mdev;
666 struct mlx5_roce roce;
667 MLX5_DECLARE_DOORBELL_LOCK(uar_lock);
668 int num_ports;
669 /* serialize update of capability mask
670 */
671 struct mutex cap_mask_mutex;
672 bool ib_active;
673 struct umr_common umrc;
674 /* sync used page count stats
675 */
676 struct mlx5_ib_resources devr;
677 struct mlx5_mr_cache cache;
678 struct timer_list delay_timer;
679 /* Prevents soft lock on massive reg MRs */
680 struct mutex slow_path_mutex;
681 int fill_delay;
682 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
683 struct ib_odp_caps odp_caps;
684 /*
685 * Sleepable RCU that prevents destruction of MRs while they are still
686 * being used by a page fault handler.
687 */
688 struct srcu_struct mr_srcu;
689 #endif
690 struct mlx5_ib_flow_db flow_db;
691 /* protect resources needed as part of reset flow */
692 spinlock_t reset_flow_resource_lock;
693 struct list_head qp_list;
694 /* Array with num_ports elements */
695 struct mlx5_ib_port *port;
696 struct mlx5_ib_congestion congestion;
697
698 struct mlx5_async_ctx async_ctx;
699 };
700
to_mibcq(struct mlx5_core_cq * mcq)701 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
702 {
703 return container_of(mcq, struct mlx5_ib_cq, mcq);
704 }
705
to_mxrcd(struct ib_xrcd * ibxrcd)706 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
707 {
708 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd);
709 }
710
to_mdev(struct ib_device * ibdev)711 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev)
712 {
713 return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
714 }
715
to_mcq(struct ib_cq * ibcq)716 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
717 {
718 return container_of(ibcq, struct mlx5_ib_cq, ibcq);
719 }
720
to_mibqp(struct mlx5_core_qp * mqp)721 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
722 {
723 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp;
724 }
725
to_mibrwq(struct mlx5_core_qp * core_qp)726 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp)
727 {
728 return container_of(core_qp, struct mlx5_ib_rwq, core_qp);
729 }
730
to_mibmr(struct mlx5_core_mr * mmkey)731 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mr *mmkey)
732 {
733 return container_of(mmkey, struct mlx5_ib_mr, mmkey);
734 }
735
to_mpd(struct ib_pd * ibpd)736 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
737 {
738 return container_of(ibpd, struct mlx5_ib_pd, ibpd);
739 }
740
to_msrq(struct ib_srq * ibsrq)741 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq)
742 {
743 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq);
744 }
745
to_mqp(struct ib_qp * ibqp)746 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp)
747 {
748 return container_of(ibqp, struct mlx5_ib_qp, ibqp);
749 }
750
to_mrwq(struct ib_wq * ibwq)751 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq)
752 {
753 return container_of(ibwq, struct mlx5_ib_rwq, ibwq);
754 }
755
to_mrwq_ind_table(struct ib_rwq_ind_table * ib_rwq_ind_tbl)756 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
757 {
758 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl);
759 }
760
to_mibsrq(struct mlx5_core_srq * msrq)761 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
762 {
763 return container_of(msrq, struct mlx5_ib_srq, msrq);
764 }
765
to_mmr(struct ib_mr * ibmr)766 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
767 {
768 return container_of(ibmr, struct mlx5_ib_mr, ibmr);
769 }
770
to_mmw(struct ib_mw * ibmw)771 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw)
772 {
773 return container_of(ibmw, struct mlx5_ib_mw, ibmw);
774 }
775
776 struct mlx5_ib_ah {
777 struct ib_ah ibah;
778 struct mlx5_av av;
779 };
780
to_mah(struct ib_ah * ibah)781 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah)
782 {
783 return container_of(ibah, struct mlx5_ib_ah, ibah);
784 }
785
786 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt,
787 struct mlx5_db *db);
788 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
789 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
790 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
791 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
792 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey,
793 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh,
794 const void *in_mad, void *response_mad);
795 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr,
796 struct ib_udata *udata);
797 int mlx5_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr);
798 int mlx5_ib_destroy_ah(struct ib_ah *ah);
799 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd,
800 struct ib_srq_init_attr *init_attr,
801 struct ib_udata *udata);
802 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
803 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
804 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr);
805 int mlx5_ib_destroy_srq(struct ib_srq *srq);
806 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
807 struct ib_recv_wr **bad_wr);
808 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
809 struct ib_qp_init_attr *init_attr,
810 struct ib_udata *udata);
811 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
812 int attr_mask, struct ib_udata *udata);
813 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
814 struct ib_qp_init_attr *qp_init_attr);
815 int mlx5_ib_destroy_qp(struct ib_qp *qp);
816 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
817 struct ib_send_wr **bad_wr);
818 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
819 struct ib_recv_wr **bad_wr);
820 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n);
821 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
822 void *buffer, u32 length,
823 struct mlx5_ib_qp_base *base);
824 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
825 const struct ib_cq_init_attr *attr,
826 struct ib_ucontext *context,
827 struct ib_udata *udata);
828 int mlx5_ib_destroy_cq(struct ib_cq *cq);
829 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
830 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
831 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
832 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
833 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
834 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
835 u64 virt_addr, int access_flags,
836 struct ib_udata *udata);
837 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
838 struct ib_udata *udata);
839 int mlx5_ib_dealloc_mw(struct ib_mw *mw);
840 int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index,
841 int npages, int zap);
842 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
843 u64 length, u64 virt_addr, int access_flags,
844 struct ib_pd *pd, struct ib_udata *udata);
845 struct ib_mr *mlx5_ib_reg_phys_mr(struct ib_pd *pd,
846 struct ib_phys_buf *buffer_list,
847 int num_phys_buf,
848 int access_flags,
849 u64 *virt_addr);
850 int mlx5_ib_dereg_mr(struct ib_mr *ibmr);
851 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd,
852 enum ib_mr_type mr_type,
853 u32 max_num_sg);
854 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
855 unsigned int *sg_offset);
856 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
857 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
858 const struct ib_mad_hdr *in, size_t in_mad_size,
859 struct ib_mad_hdr *out, size_t *out_mad_size,
860 u16 *out_mad_pkey_index);
861 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
862 struct ib_ucontext *context,
863 struct ib_udata *udata);
864 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd);
865 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset);
866 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port);
867 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev,
868 struct ib_smp *out_mad);
869 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev,
870 __be64 *sys_image_guid);
871 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev,
872 u16 *max_pkeys);
873 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev,
874 u32 *vendor_id);
875 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc);
876 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid);
877 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index,
878 u16 *pkey);
879 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index,
880 union ib_gid *gid);
881 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port,
882 struct ib_port_attr *props);
883 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
884 struct ib_port_attr *props);
885 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev);
886 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev);
887 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift,
888 int *ncont, int *order);
889 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
890 int page_shift, size_t offset, size_t num_pages,
891 __be64 *pas, int access_flags);
892 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
893 int page_shift, __be64 *pas, int access_flags);
894 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
895 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq);
896 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev);
897 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev);
898 int mlx5_mr_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift);
899 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
900 struct ib_mr_status *mr_status);
901 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
902 struct ib_wq_init_attr *init_attr,
903 struct ib_udata *udata);
904 int mlx5_ib_destroy_wq(struct ib_wq *wq);
905 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
906 u32 wq_attr_mask, struct ib_udata *udata);
907 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
908 struct ib_rwq_ind_table_init_attr *init_attr,
909 struct ib_udata *udata);
910 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table);
911
912 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
913 extern struct workqueue_struct *mlx5_ib_page_fault_wq;
914
915 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev);
916 void mlx5_ib_mr_pfault_handler(struct mlx5_ib_qp *qp,
917 struct mlx5_ib_pfault *pfault);
918 void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp);
919 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev);
920 void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev);
921 int __init mlx5_ib_odp_init(void);
922 void mlx5_ib_odp_cleanup(void);
923 void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp);
924 void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp);
925 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start,
926 unsigned long end);
927 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev * dev)928 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev)
929 {
930 return;
931 }
932
mlx5_ib_odp_create_qp(struct mlx5_ib_qp * qp)933 static inline void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp) {}
mlx5_ib_odp_init_one(struct mlx5_ib_dev * ibdev)934 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; }
mlx5_ib_odp_remove_one(struct mlx5_ib_dev * ibdev)935 static inline void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev) {}
mlx5_ib_odp_init(void)936 static inline int mlx5_ib_odp_init(void) { return 0; }
mlx5_ib_odp_cleanup(void)937 static inline void mlx5_ib_odp_cleanup(void) {}
mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp * qp)938 static inline void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp) {}
mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp * qp)939 static inline void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp) {}
940
941 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
942
943 int mlx5_ib_get_vf_config(struct ib_device *device, int vf,
944 u8 port, struct ifla_vf_info *info);
945 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf,
946 u8 port, int state);
947 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf,
948 u8 port, struct ifla_vf_stats *stats);
949 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port,
950 u64 guid, int type);
951
952 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
953 int index);
954 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
955 int index, enum ib_gid_type *gid_type);
956
957 /* GSI QP helper functions */
958 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd,
959 struct ib_qp_init_attr *init_attr);
960 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp);
961 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr,
962 int attr_mask);
963 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr,
964 int qp_attr_mask,
965 struct ib_qp_init_attr *qp_init_attr);
966 int mlx5_ib_gsi_post_send(struct ib_qp *qp, struct ib_send_wr *wr,
967 struct ib_send_wr **bad_wr);
968 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, struct ib_recv_wr *wr,
969 struct ib_recv_wr **bad_wr);
970 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi);
971
972 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc);
973
init_query_mad(struct ib_smp * mad)974 static inline void init_query_mad(struct ib_smp *mad)
975 {
976 mad->base_version = 1;
977 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
978 mad->class_version = 1;
979 mad->method = IB_MGMT_METHOD_GET;
980 }
981
convert_access(int acc)982 static inline u8 convert_access(int acc)
983 {
984 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
985 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
986 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
987 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
988 MLX5_PERM_LOCAL_READ;
989 }
990
is_qp1(enum ib_qp_type qp_type)991 static inline int is_qp1(enum ib_qp_type qp_type)
992 {
993 return qp_type == MLX5_IB_QPT_HW_GSI;
994 }
995
996 #define MLX5_MAX_UMR_SHIFT 16
997 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT)
998
check_cq_create_flags(u32 flags)999 static inline u32 check_cq_create_flags(u32 flags)
1000 {
1001 /*
1002 * It returns non-zero value for unsupported CQ
1003 * create flags, otherwise it returns zero.
1004 */
1005 return (flags & ~(IB_CQ_FLAGS_IGNORE_OVERRUN |
1006 IB_CQ_FLAGS_TIMESTAMP_COMPLETION));
1007 }
1008
verify_assign_uidx(u8 cqe_version,u32 cmd_uidx,u32 * user_index)1009 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx,
1010 u32 *user_index)
1011 {
1012 if (cqe_version) {
1013 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) ||
1014 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK))
1015 return -EINVAL;
1016 *user_index = cmd_uidx;
1017 } else {
1018 *user_index = MLX5_IB_DEFAULT_UIDX;
1019 }
1020
1021 return 0;
1022 }
1023
get_qp_user_index(struct mlx5_ib_ucontext * ucontext,struct mlx5_ib_create_qp * ucmd,int inlen,u32 * user_index)1024 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext,
1025 struct mlx5_ib_create_qp *ucmd,
1026 int inlen,
1027 u32 *user_index)
1028 {
1029 u8 cqe_version = ucontext->cqe_version;
1030
1031 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) &&
1032 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1033 return 0;
1034
1035 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) !=
1036 !!cqe_version))
1037 return -EINVAL;
1038
1039 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1040 }
1041
get_srq_user_index(struct mlx5_ib_ucontext * ucontext,struct mlx5_ib_create_srq * ucmd,int inlen,u32 * user_index)1042 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext,
1043 struct mlx5_ib_create_srq *ucmd,
1044 int inlen,
1045 u32 *user_index)
1046 {
1047 u8 cqe_version = ucontext->cqe_version;
1048
1049 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) &&
1050 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1051 return 0;
1052
1053 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) !=
1054 !!cqe_version))
1055 return -EINVAL;
1056
1057 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1058 }
1059
1060 void mlx5_ib_cleanup_congestion(struct mlx5_ib_dev *);
1061 int mlx5_ib_init_congestion(struct mlx5_ib_dev *);
1062
1063 #endif /* MLX5_IB_H */
1064