1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
39 #include <linux/types.h>
40 #include <linux/bitops.h>
41 #include <linux/workqueue.h>
42 #include <asm/atomic.h>
43
44 #include <linux/clocksource.h>
45
46 #define MAX_MSIX_P_PORT 17
47 #define MAX_MSIX 64
48 #define MSIX_LEGACY_SZ 4
49 #define MIN_MSIX_P_PORT 5
50
51 #define MLX4_ROCE_MAX_GIDS 128
52 #define MLX4_ROCE_PF_GIDS 16
53
54 #define MLX4_NUM_UP 8
55 #define MLX4_NUM_TC 8
56 #define MLX4_MAX_100M_UNITS_VAL 255 /*
57 * work around: can't set values
58 * greater then this value when
59 * using 100 Mbps units.
60 */
61 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
62 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
63 #define MLX4_RATELIMIT_DEFAULT 0x00ff
64
65 #define CORE_CLOCK_MASK 0xffffffffffffULL
66
67 enum {
68 MLX4_FLAG_MSI_X = 1 << 0,
69 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
70 MLX4_FLAG_MASTER = 1 << 2,
71 MLX4_FLAG_SLAVE = 1 << 3,
72 MLX4_FLAG_SRIOV = 1 << 4,
73 MLX4_FLAG_DEV_NUM_STR = 1 << 5,
74 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
75 };
76
77 enum {
78 MLX4_PORT_CAP_IS_SM = 1 << 1,
79 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
80 };
81
82 enum {
83 MLX4_MAX_PORTS = 2,
84 MLX4_MAX_PORT_PKEYS = 128
85 };
86
87 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
88 * These qkeys must not be allowed for general use. This is a 64k range,
89 * and to test for violation, we use the mask (protect against future chg).
90 */
91 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
92 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
93
94 enum {
95 MLX4_BOARD_ID_LEN = 64,
96 MLX4_VSD_LEN = 208
97 };
98
99 enum {
100 MLX4_MAX_NUM_PF = 16,
101 MLX4_MAX_NUM_VF = 64,
102 MLX4_MFUNC_MAX = 80,
103 MLX4_MAX_EQ_NUM = 1024,
104 MLX4_MFUNC_EQ_NUM = 4,
105 MLX4_MFUNC_MAX_EQES = 8,
106 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
107 };
108
109 /* Driver supports 3 diffrent device methods to manage traffic steering:
110 * -device managed - High level API for ib and eth flow steering. FW is
111 * managing flow steering tables.
112 * - B0 steering mode - Common low level API for ib and (if supported) eth.
113 * - A0 steering mode - Limited low level API for eth. In case of IB,
114 * B0 mode is in use.
115 */
116 enum {
117 MLX4_STEERING_MODE_A0,
118 MLX4_STEERING_MODE_B0,
119 MLX4_STEERING_MODE_DEVICE_MANAGED
120 };
121
mlx4_steering_mode_str(int steering_mode)122 static inline const char *mlx4_steering_mode_str(int steering_mode)
123 {
124 switch (steering_mode) {
125 case MLX4_STEERING_MODE_A0:
126 return "A0 steering";
127
128 case MLX4_STEERING_MODE_B0:
129 return "B0 steering";
130
131 case MLX4_STEERING_MODE_DEVICE_MANAGED:
132 return "Device managed flow steering";
133
134 default:
135 return "Unrecognize steering mode";
136 }
137 }
138
139 enum {
140 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
141 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
142 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
143 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
144 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
145 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
146 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
147 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
148 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
149 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
150 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
151 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
152 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
153 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
154 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
155 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
156 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
157 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
158 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
159 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
160 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
161 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
162 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
163 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
164 MLX4_DEV_CAP_FLAG_CROSS_CHANNEL = 1LL << 44,
165 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
166 MLX4_DEV_CAP_FLAG_COUNTERS_EXT = 1LL << 49,
167 MLX4_DEV_CAP_FLAG_SET_PORT_ETH_SCHED = 1LL << 53,
168 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
169 MLX4_DEV_CAP_FLAG_FAST_DROP = 1LL << 57,
170 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
171 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
172 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
173 };
174
175 enum {
176 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
177 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
178 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
179 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
180 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 4,
181 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 5,
182 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 6,
183 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1LL << 7,
184 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 8,
185 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 9,
186 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 10,
187 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 11,
188 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 12,
189 MLX4_DEV_CAP_FLAG2_TS = 1LL << 13,
190 MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW = 1LL << 14,
191 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 15,
192 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 16,
193 MLX4_DEV_CAP_FLAG2_FS_EN_NCSI = 1LL << 17,
194 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
195 MLX4_DEV_CAP_FLAG2_DMFS_TAG_MODE = 1LL << 19,
196 MLX4_DEV_CAP_FLAG2_ROCEV2 = 1LL << 20,
197 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 21,
198 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 22,
199 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 23,
200 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1LL << 24,
201 MLX4_DEV_CAP_FLAG2_RX_CSUM_MODE = 1LL << 25,
202 };
203
204 /* bit enums for an 8-bit flags field indicating special use
205 * QPs which require special handling in qp_reserve_range.
206 * Currently, this only includes QPs used by the ETH interface,
207 * where we expect to use blueflame. These QPs must not have
208 * bits 6 and 7 set in their qp number.
209 *
210 * This enum may use only bits 0..7.
211 */
212 enum {
213 MLX4_RESERVE_BF_QP = 1 << 7,
214 };
215
216 enum {
217 MLX4_DEV_CAP_CQ_FLAG_IO = 1 << 0
218 };
219
220 enum {
221 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
222 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1
223 };
224
225 enum {
226 MLX4_USER_DEV_CAP_64B_CQE = 1L << 0
227 };
228
229 enum {
230 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0
231 };
232
233
234 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
235
236 enum {
237 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
238 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
239 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
240 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
241 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
242 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
243 };
244
245 enum mlx4_event {
246 MLX4_EVENT_TYPE_COMP = 0x00,
247 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
248 MLX4_EVENT_TYPE_COMM_EST = 0x02,
249 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
250 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
251 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
252 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
253 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
254 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
255 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
256 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
257 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
258 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
259 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
260 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
261 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
262 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
263 MLX4_EVENT_TYPE_CMD = 0x0a,
264 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
265 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
266 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
267 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
268 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
269 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
270 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e,
271 MLX4_EVENT_TYPE_NONE = 0xff,
272 };
273
274 enum {
275 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
276 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
277 };
278
279 enum {
280 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1,
281 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2,
282 };
283
284 enum {
285 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
286 };
287
288 enum slave_port_state {
289 SLAVE_PORT_DOWN = 0,
290 SLAVE_PENDING_UP,
291 SLAVE_PORT_UP,
292 };
293
294 enum slave_port_gen_event {
295 SLAVE_PORT_GEN_EVENT_DOWN = 0,
296 SLAVE_PORT_GEN_EVENT_UP,
297 SLAVE_PORT_GEN_EVENT_NONE,
298 };
299
300 enum slave_port_state_event {
301 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
302 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
303 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
304 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
305 };
306
307 enum {
308 MLX4_PERM_LOCAL_READ = 1 << 10,
309 MLX4_PERM_LOCAL_WRITE = 1 << 11,
310 MLX4_PERM_REMOTE_READ = 1 << 12,
311 MLX4_PERM_REMOTE_WRITE = 1 << 13,
312 MLX4_PERM_ATOMIC = 1 << 14,
313 MLX4_PERM_BIND_MW = 1 << 15,
314 };
315
316 enum {
317 MLX4_OPCODE_NOP = 0x00,
318 MLX4_OPCODE_SEND_INVAL = 0x01,
319 MLX4_OPCODE_RDMA_WRITE = 0x08,
320 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
321 MLX4_OPCODE_SEND = 0x0a,
322 MLX4_OPCODE_SEND_IMM = 0x0b,
323 MLX4_OPCODE_LSO = 0x0e,
324 MLX4_OPCODE_RDMA_READ = 0x10,
325 MLX4_OPCODE_ATOMIC_CS = 0x11,
326 MLX4_OPCODE_ATOMIC_FA = 0x12,
327 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
328 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
329 MLX4_OPCODE_BIND_MW = 0x18,
330 MLX4_OPCODE_FMR = 0x19,
331 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
332 MLX4_OPCODE_CONFIG_CMD = 0x1f,
333
334 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
335 MLX4_RECV_OPCODE_SEND = 0x01,
336 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
337 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
338
339 MLX4_CQE_OPCODE_ERROR = 0x1e,
340 MLX4_CQE_OPCODE_RESIZE = 0x16,
341 };
342
343 enum {
344 MLX4_STAT_RATE_OFFSET = 5
345 };
346
347 enum mlx4_protocol {
348 MLX4_PROT_IB_IPV6 = 0,
349 MLX4_PROT_ETH,
350 MLX4_PROT_IB_IPV4,
351 MLX4_PROT_FCOE
352 };
353
354 enum {
355 MLX4_MTT_FLAG_PRESENT = 1
356 };
357
358 enum {
359 MLX4_MAX_MTT_SHIFT = 31
360 };
361
362 enum mlx4_qp_region {
363 MLX4_QP_REGION_FW = 0,
364 MLX4_QP_REGION_ETH_ADDR,
365 MLX4_QP_REGION_FC_ADDR,
366 MLX4_QP_REGION_FC_EXCH,
367 MLX4_NUM_QP_REGION
368 };
369
370 enum mlx4_port_type {
371 MLX4_PORT_TYPE_NONE = 0,
372 MLX4_PORT_TYPE_IB = 1,
373 MLX4_PORT_TYPE_ETH = 2,
374 MLX4_PORT_TYPE_AUTO = 3,
375 MLX4_PORT_TYPE_NA = 4
376 };
377
378 enum mlx4_special_vlan_idx {
379 MLX4_NO_VLAN_IDX = 0,
380 MLX4_VLAN_MISS_IDX,
381 MLX4_VLAN_REGULAR
382 };
383
384 enum mlx4_steer_type {
385 MLX4_MC_STEER = 0,
386 MLX4_UC_STEER,
387 MLX4_NUM_STEERS
388 };
389
390 enum {
391 MLX4_NUM_FEXCH = 64 * 1024,
392 };
393
394 enum {
395 MLX4_MAX_FAST_REG_PAGES = 511,
396 };
397
398 enum {
399 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
400 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
401 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
402 };
403
404 /* Port mgmt change event handling */
405 enum {
406 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
407 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
408 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
409 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
410 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
411 };
412
413 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
414 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
415
416 enum mlx4_module_id {
417 MLX4_MODULE_ID_SFP = 0x3,
418 MLX4_MODULE_ID_QSFP = 0xC,
419 MLX4_MODULE_ID_QSFP_PLUS = 0xD,
420 MLX4_MODULE_ID_QSFP28 = 0x11,
421 };
422
mlx4_fw_ver(u64 major,u64 minor,u64 subminor)423 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
424 {
425 return (major << 32) | (minor << 16) | subminor;
426 }
427
428 struct mlx4_phys_caps {
429 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
430 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
431 u32 num_phys_eqs;
432 u32 base_sqpn;
433 u32 base_proxy_sqpn;
434 u32 base_tunnel_sqpn;
435 };
436
437 struct mlx4_caps {
438 u64 fw_ver;
439 u32 function;
440 int num_ports;
441 int vl_cap[MLX4_MAX_PORTS + 1];
442 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
443 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
444 u64 def_mac[MLX4_MAX_PORTS + 1];
445 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
446 int gid_table_len[MLX4_MAX_PORTS + 1];
447 int pkey_table_len[MLX4_MAX_PORTS + 1];
448 int trans_type[MLX4_MAX_PORTS + 1];
449 int vendor_oui[MLX4_MAX_PORTS + 1];
450 int wavelength[MLX4_MAX_PORTS + 1];
451 u64 trans_code[MLX4_MAX_PORTS + 1];
452 int local_ca_ack_delay;
453 int num_uars;
454 u32 uar_page_size;
455 int bf_reg_size;
456 int bf_regs_per_page;
457 int max_sq_sg;
458 int max_rq_sg;
459 int num_qps;
460 int max_wqes;
461 int max_sq_desc_sz;
462 int max_rq_desc_sz;
463 int max_qp_init_rdma;
464 int max_qp_dest_rdma;
465 u32 *qp0_proxy;
466 u32 *qp1_proxy;
467 u32 *qp0_tunnel;
468 u32 *qp1_tunnel;
469 int num_srqs;
470 int max_srq_wqes;
471 int max_srq_sge;
472 int reserved_srqs;
473 int num_cqs;
474 int max_cqes;
475 int reserved_cqs;
476 int num_eqs;
477 int reserved_eqs;
478 int num_comp_vectors;
479 int comp_pool;
480 int num_mpts;
481 int max_fmr_maps;
482 u64 num_mtts;
483 int fmr_reserved_mtts;
484 int reserved_mtts;
485 int reserved_mrws;
486 int reserved_uars;
487 int num_mgms;
488 int num_amgms;
489 int reserved_mcgs;
490 int num_qp_per_mgm;
491 int steering_mode;
492 int num_pds;
493 int reserved_pds;
494 int max_xrcds;
495 int reserved_xrcds;
496 int mtt_entry_sz;
497 u32 max_msg_sz;
498 u32 page_size_cap;
499 u64 flags;
500 u64 flags2;
501 u32 bmme_flags;
502 u32 reserved_lkey;
503 u16 stat_rate_support;
504 u8 cq_timestamp;
505 u8 port_width_cap[MLX4_MAX_PORTS + 1];
506 int max_gso_sz;
507 int max_rss_tbl_sz;
508 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
509 int reserved_qps;
510 int reserved_qps_base[MLX4_NUM_QP_REGION];
511 int log_num_macs;
512 int log_num_vlans;
513 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
514 u8 supported_type[MLX4_MAX_PORTS + 1];
515 u8 suggested_type[MLX4_MAX_PORTS + 1];
516 u8 default_sense[MLX4_MAX_PORTS + 1];
517 u32 port_mask[MLX4_MAX_PORTS + 1];
518 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
519 u32 max_counters;
520 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
521 u16 sqp_demux;
522 u32 sync_qp;
523 u32 cq_flags;
524 u32 eqe_size;
525 u32 cqe_size;
526 u8 eqe_factor;
527 u32 userspace_caps; /* userspace must be aware to */
528 u32 function_caps; /* functions must be aware to */
529 u8 fast_drop;
530 u16 hca_core_clock;
531 u32 max_basic_counters;
532 u32 max_extended_counters;
533 u8 def_counter_index[MLX4_MAX_PORTS + 1];
534 };
535
536 struct mlx4_buf_list {
537 void *buf;
538 dma_addr_t map;
539 };
540
541 struct mlx4_buf {
542 struct mlx4_buf_list direct;
543 struct mlx4_buf_list *page_list;
544 int nbufs;
545 int npages;
546 int page_shift;
547 };
548
549 struct mlx4_mtt {
550 u32 offset;
551 int order;
552 int page_shift;
553 };
554
555 enum {
556 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
557 };
558
559 struct mlx4_db_pgdir {
560 struct list_head list;
561 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
562 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
563 unsigned long *bits[2];
564 __be32 *db_page;
565 dma_addr_t db_dma;
566 };
567
568 struct mlx4_ib_user_db_page;
569
570 struct mlx4_db {
571 __be32 *db;
572 union {
573 struct mlx4_db_pgdir *pgdir;
574 struct mlx4_ib_user_db_page *user_page;
575 } u;
576 dma_addr_t dma;
577 int index;
578 int order;
579 };
580
581 struct mlx4_hwq_resources {
582 struct mlx4_db db;
583 struct mlx4_mtt mtt;
584 struct mlx4_buf buf;
585 };
586
587 struct mlx4_mr {
588 struct mlx4_mtt mtt;
589 u64 iova;
590 u64 size;
591 u32 key;
592 u32 pd;
593 u32 access;
594 int enabled;
595 };
596
597 enum mlx4_mw_type {
598 MLX4_MW_TYPE_1 = 1,
599 MLX4_MW_TYPE_2 = 2,
600 };
601
602 struct mlx4_mw {
603 u32 key;
604 u32 pd;
605 enum mlx4_mw_type type;
606 int enabled;
607 };
608
609 struct mlx4_fmr {
610 struct mlx4_mr mr;
611 struct mlx4_mpt_entry *mpt;
612 __be64 *mtts;
613 dma_addr_t dma_handle;
614 int max_pages;
615 int max_maps;
616 int maps;
617 u8 page_shift;
618 };
619
620 struct mlx4_uar {
621 unsigned long pfn;
622 int index;
623 struct list_head bf_list;
624 unsigned free_bf_bmap;
625 void __iomem *map;
626 void __iomem *bf_map;
627 };
628
629 struct mlx4_bf {
630 unsigned long offset;
631 int buf_size;
632 struct mlx4_uar *uar;
633 void __iomem *reg;
634 };
635
636 struct mlx4_cq {
637 void (*comp) (struct mlx4_cq *);
638 void (*event) (struct mlx4_cq *, enum mlx4_event);
639
640 struct mlx4_uar *uar;
641
642 u32 cons_index;
643
644 __be32 *set_ci_db;
645 __be32 *arm_db;
646 int arm_sn;
647
648 int cqn;
649 unsigned vector;
650
651 atomic_t refcount;
652 struct completion free;
653 int eqn;
654 u16 irq;
655 };
656
657 struct mlx4_qp {
658 void (*event) (struct mlx4_qp *, enum mlx4_event);
659
660 int qpn;
661
662 atomic_t refcount;
663 struct completion free;
664 };
665
666 struct mlx4_srq {
667 void (*event) (struct mlx4_srq *, enum mlx4_event);
668
669 int srqn;
670 int max;
671 int max_gs;
672 int wqe_shift;
673
674 atomic_t refcount;
675 struct completion free;
676 };
677
678 struct mlx4_av {
679 __be32 port_pd;
680 u8 reserved1;
681 u8 g_slid;
682 __be16 dlid;
683 u8 reserved2;
684 u8 gid_index;
685 u8 stat_rate;
686 u8 hop_limit;
687 __be32 sl_tclass_flowlabel;
688 u8 dgid[16];
689 };
690
691 struct mlx4_eth_av {
692 __be32 port_pd;
693 u8 reserved1;
694 u8 smac_idx;
695 u16 reserved2;
696 u8 reserved3;
697 u8 gid_index;
698 u8 stat_rate;
699 u8 hop_limit;
700 __be32 sl_tclass_flowlabel;
701 u8 dgid[16];
702 u8 s_mac[6];
703 u8 reserved4[2];
704 __be16 vlan;
705 u8 mac[6];
706 };
707
708 union mlx4_ext_av {
709 struct mlx4_av ib;
710 struct mlx4_eth_av eth;
711 };
712
713 struct mlx4_if_stat_control {
714 u8 reserved1[3];
715 /* Extended counters enabled */
716 u8 cnt_mode;
717 /* Number of interfaces */
718 __be32 num_of_if;
719 __be32 reserved[2];
720 };
721
722 struct mlx4_if_stat_basic {
723 struct mlx4_if_stat_control control;
724 struct {
725 __be64 IfRxFrames;
726 __be64 IfRxOctets;
727 __be64 IfTxFrames;
728 __be64 IfTxOctets;
729 } counters[];
730 };
731 #define MLX4_IF_STAT_BSC_SZ(ports)(sizeof(struct mlx4_if_stat_extended) +\
732 sizeof(((struct mlx4_if_stat_extended *)0)->\
733 counters[0]) * ports)
734
735 struct mlx4_if_stat_extended {
736 struct mlx4_if_stat_control control;
737 struct {
738 __be64 IfRxUnicastFrames;
739 __be64 IfRxUnicastOctets;
740 __be64 IfRxMulticastFrames;
741 __be64 IfRxMulticastOctets;
742 __be64 IfRxBroadcastFrames;
743 __be64 IfRxBroadcastOctets;
744 __be64 IfRxNoBufferFrames;
745 __be64 IfRxNoBufferOctets;
746 __be64 IfRxErrorFrames;
747 __be64 IfRxErrorOctets;
748 __be32 reserved[39];
749 __be64 IfTxUnicastFrames;
750 __be64 IfTxUnicastOctets;
751 __be64 IfTxMulticastFrames;
752 __be64 IfTxMulticastOctets;
753 __be64 IfTxBroadcastFrames;
754 __be64 IfTxBroadcastOctets;
755 __be64 IfTxDroppedFrames;
756 __be64 IfTxDroppedOctets;
757 __be64 IfTxRequestedFramesSent;
758 __be64 IfTxGeneratedFramesSent;
759 __be64 IfTxTsoOctets;
760 } __packed counters[];
761 };
762 #define MLX4_IF_STAT_EXT_SZ(ports) (sizeof(struct mlx4_if_stat_extended) +\
763 sizeof(((struct mlx4_if_stat_extended *)\
764 0)->counters[0]) * ports)
765
766 union mlx4_counter {
767 struct mlx4_if_stat_control control;
768 struct mlx4_if_stat_basic basic;
769 struct mlx4_if_stat_extended ext;
770 };
771 #define MLX4_IF_STAT_SZ(ports) MLX4_IF_STAT_EXT_SZ(ports)
772
773 struct mlx4_quotas {
774 int qp;
775 int cq;
776 int srq;
777 int mpt;
778 int mtt;
779 int counter;
780 int xrcd;
781 };
782
783 struct mlx4_dev {
784 struct pci_dev *pdev;
785 unsigned long flags;
786 unsigned long num_slaves;
787 struct mlx4_caps caps;
788 struct mlx4_phys_caps phys_caps;
789 struct mlx4_quotas quotas;
790 struct radix_tree_root qp_table_tree;
791 u8 rev_id;
792 char board_id[MLX4_BOARD_ID_LEN];
793 u16 vsd_vendor_id;
794 char vsd[MLX4_VSD_LEN];
795 int num_vfs;
796 int numa_node;
797 int oper_log_mgm_entry_size;
798 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
799 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
800 };
801
802 struct mlx4_clock_params {
803 u64 offset;
804 u8 bar;
805 u8 size;
806 };
807
808 struct mlx4_eqe {
809 u8 reserved1;
810 u8 type;
811 u8 reserved2;
812 u8 subtype;
813 union {
814 u32 raw[6];
815 struct {
816 __be32 cqn;
817 } __packed comp;
818 struct {
819 u16 reserved1;
820 __be16 token;
821 u32 reserved2;
822 u8 reserved3[3];
823 u8 status;
824 __be64 out_param;
825 } __packed cmd;
826 struct {
827 __be32 qpn;
828 } __packed qp;
829 struct {
830 __be32 srqn;
831 } __packed srq;
832 struct {
833 __be32 cqn;
834 u32 reserved1;
835 u8 reserved2[3];
836 u8 syndrome;
837 } __packed cq_err;
838 struct {
839 u32 reserved1[2];
840 __be32 port;
841 } __packed port_change;
842 struct {
843 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
844 u32 reserved;
845 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
846 } __packed comm_channel_arm;
847 struct {
848 u8 port;
849 u8 reserved[3];
850 __be64 mac;
851 } __packed mac_update;
852 struct {
853 __be32 slave_id;
854 } __packed flr_event;
855 struct {
856 __be16 current_temperature;
857 __be16 warning_threshold;
858 } __packed warming;
859 struct {
860 u8 reserved[3];
861 u8 port;
862 union {
863 struct {
864 __be16 mstr_sm_lid;
865 __be16 port_lid;
866 __be32 changed_attr;
867 u8 reserved[3];
868 u8 mstr_sm_sl;
869 __be64 gid_prefix;
870 } __packed port_info;
871 struct {
872 __be32 block_ptr;
873 __be32 tbl_entries_mask;
874 } __packed tbl_change_info;
875 } params;
876 } __packed port_mgmt_change;
877 struct {
878 u8 reserved[3];
879 u8 port;
880 u32 reserved1[5];
881 } __packed bad_cable;
882 } event;
883 u8 slave_id;
884 u8 reserved3[2];
885 u8 owner;
886 } __packed;
887
888 struct mlx4_init_port_param {
889 int set_guid0;
890 int set_node_guid;
891 int set_si_guid;
892 u16 mtu;
893 int port_width_cap;
894 u16 vl_cap;
895 u16 max_gid;
896 u16 max_pkey;
897 u64 guid0;
898 u64 node_guid;
899 u64 si_guid;
900 };
901
902 #define MAD_IFC_DATA_SZ 192
903 /* MAD IFC Mailbox */
904 struct mlx4_mad_ifc {
905 u8 base_version;
906 u8 mgmt_class;
907 u8 class_version;
908 u8 method;
909 __be16 status;
910 __be16 class_specific;
911 __be64 tid;
912 __be16 attr_id;
913 __be16 resv;
914 __be32 attr_mod;
915 __be64 mkey;
916 __be16 dr_slid;
917 __be16 dr_dlid;
918 u8 reserved[28];
919 u8 data[MAD_IFC_DATA_SZ];
920 } __packed;
921
922 #define mlx4_foreach_port(port, dev, type) \
923 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
924 if ((type) == (dev)->caps.port_mask[(port)])
925
926 #define mlx4_foreach_non_ib_transport_port(port, dev) \
927 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
928 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
929
930 #define mlx4_foreach_ib_transport_port(port, dev) \
931 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
932 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
933 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
934
935 #define MLX4_INVALID_SLAVE_ID 0xFF
936
937 #define MLX4_SINK_COUNTER_INDEX 0xff
938
939 void handle_port_mgmt_change_event(struct work_struct *work);
940
mlx4_master_func_num(struct mlx4_dev * dev)941 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
942 {
943 return dev->caps.function;
944 }
945
mlx4_is_master(struct mlx4_dev * dev)946 static inline int mlx4_is_master(struct mlx4_dev *dev)
947 {
948 return dev->flags & MLX4_FLAG_MASTER;
949 }
950
mlx4_num_reserved_sqps(struct mlx4_dev * dev)951 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
952 {
953 return dev->phys_caps.base_sqpn + 8 +
954 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
955 }
956
mlx4_is_qp_reserved(struct mlx4_dev * dev,u32 qpn)957 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
958 {
959 return (qpn < dev->phys_caps.base_sqpn + 8 +
960 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev));
961 }
962
mlx4_is_guest_proxy(struct mlx4_dev * dev,int slave,u32 qpn)963 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
964 {
965 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
966
967 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
968 return 1;
969
970 return 0;
971 }
972
mlx4_is_mfunc(struct mlx4_dev * dev)973 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
974 {
975 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
976 }
977
mlx4_is_slave(struct mlx4_dev * dev)978 static inline int mlx4_is_slave(struct mlx4_dev *dev)
979 {
980 return dev->flags & MLX4_FLAG_SLAVE;
981 }
982
983 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
984 struct mlx4_buf *buf);
985 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
mlx4_buf_offset(struct mlx4_buf * buf,int offset)986 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
987 {
988 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
989 return (u8 *)buf->direct.buf + offset;
990 else
991 return (u8 *)buf->page_list[offset >> PAGE_SHIFT].buf +
992 (offset & (PAGE_SIZE - 1));
993 }
994
995 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
996 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
997 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
998 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
999
1000 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
1001 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
1002 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
1003 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
1004
1005 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
1006 struct mlx4_mtt *mtt);
1007 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1008 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1009
1010 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
1011 int npages, int page_shift, struct mlx4_mr *mr);
1012 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
1013 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
1014 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
1015 struct mlx4_mw *mw);
1016 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
1017 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
1018 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1019 int start_index, int npages, u64 *page_list);
1020 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1021 struct mlx4_buf *buf);
1022
1023 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
1024 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
1025
1026 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
1027 int size, int max_direct);
1028 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
1029 int size);
1030
1031 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
1032 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
1033 unsigned vector, int collapsed, int timestamp_en);
1034 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
1035
1036 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1037 int *base, u8 flags);
1038 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1039
1040 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
1041 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
1042
1043 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
1044 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
1045 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
1046 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
1047 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
1048
1049 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
1050 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
1051
1052 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1053 int block_mcast_loopback, enum mlx4_protocol prot);
1054 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1055 enum mlx4_protocol prot);
1056 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1057 u8 port, int block_mcast_loopback,
1058 enum mlx4_protocol protocol, u64 *reg_id);
1059 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1060 enum mlx4_protocol protocol, u64 reg_id);
1061
1062 enum {
1063 MLX4_DOMAIN_UVERBS = 0x1000,
1064 MLX4_DOMAIN_ETHTOOL = 0x2000,
1065 MLX4_DOMAIN_RFS = 0x3000,
1066 MLX4_DOMAIN_NIC = 0x5000,
1067 };
1068
1069 enum mlx4_net_trans_rule_id {
1070 MLX4_NET_TRANS_RULE_ID_ETH = 0,
1071 MLX4_NET_TRANS_RULE_ID_IB,
1072 MLX4_NET_TRANS_RULE_ID_IPV6,
1073 MLX4_NET_TRANS_RULE_ID_IPV4,
1074 MLX4_NET_TRANS_RULE_ID_TCP,
1075 MLX4_NET_TRANS_RULE_ID_UDP,
1076 MLX4_NET_TRANS_RULE_NUM, /* should be last */
1077 MLX4_NET_TRANS_RULE_DUMMY = -1, /* force enum to be signed */
1078 };
1079
1080 extern const u16 __sw_id_hw[];
1081
map_hw_to_sw_id(u16 header_id)1082 static inline int map_hw_to_sw_id(u16 header_id)
1083 {
1084
1085 int i;
1086 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
1087 if (header_id == __sw_id_hw[i])
1088 return i;
1089 }
1090 return -EINVAL;
1091 }
1092
1093 enum mlx4_net_trans_promisc_mode {
1094 MLX4_FS_REGULAR = 1,
1095 MLX4_FS_ALL_DEFAULT,
1096 MLX4_FS_MC_DEFAULT,
1097 MLX4_FS_UC_SNIFFER,
1098 MLX4_FS_MC_SNIFFER,
1099 MLX4_FS_MODE_NUM, /* should be last */
1100 MLX4_FS_MODE_DUMMY = -1, /* force enum to be signed */
1101 };
1102
1103 struct mlx4_spec_eth {
1104 u8 dst_mac[6];
1105 u8 dst_mac_msk[6];
1106 u8 src_mac[6];
1107 u8 src_mac_msk[6];
1108 u8 ether_type_enable;
1109 __be16 ether_type;
1110 __be16 vlan_id_msk;
1111 __be16 vlan_id;
1112 };
1113
1114 struct mlx4_spec_tcp_udp {
1115 __be16 dst_port;
1116 __be16 dst_port_msk;
1117 __be16 src_port;
1118 __be16 src_port_msk;
1119 };
1120
1121 struct mlx4_spec_ipv4 {
1122 __be32 dst_ip;
1123 __be32 dst_ip_msk;
1124 __be32 src_ip;
1125 __be32 src_ip_msk;
1126 };
1127
1128 struct mlx4_spec_ib {
1129 __be32 l3_qpn;
1130 __be32 qpn_msk;
1131 u8 dst_gid[16];
1132 u8 dst_gid_msk[16];
1133 };
1134
1135 struct mlx4_spec_list {
1136 struct list_head list;
1137 enum mlx4_net_trans_rule_id id;
1138 union {
1139 struct mlx4_spec_eth eth;
1140 struct mlx4_spec_ib ib;
1141 struct mlx4_spec_ipv4 ipv4;
1142 struct mlx4_spec_tcp_udp tcp_udp;
1143 };
1144 };
1145
1146 enum mlx4_net_trans_hw_rule_queue {
1147 MLX4_NET_TRANS_Q_FIFO,
1148 MLX4_NET_TRANS_Q_LIFO,
1149 };
1150
1151 struct mlx4_net_trans_rule {
1152 struct list_head list;
1153 enum mlx4_net_trans_hw_rule_queue queue_mode;
1154 bool exclusive;
1155 bool allow_loopback;
1156 enum mlx4_net_trans_promisc_mode promisc_mode;
1157 u8 port;
1158 u16 priority;
1159 u32 qpn;
1160 };
1161
1162 struct mlx4_net_trans_rule_hw_ctrl {
1163 __be16 prio;
1164 u8 type;
1165 u8 flags;
1166 u8 rsvd1;
1167 u8 funcid;
1168 u8 vep;
1169 u8 port;
1170 __be32 qpn;
1171 __be32 rsvd2;
1172 };
1173
1174 struct mlx4_net_trans_rule_hw_ib {
1175 u8 size;
1176 u8 rsvd1;
1177 __be16 id;
1178 u32 rsvd2;
1179 __be32 l3_qpn;
1180 __be32 qpn_mask;
1181 u8 dst_gid[16];
1182 u8 dst_gid_msk[16];
1183 } __packed;
1184
1185 struct mlx4_net_trans_rule_hw_eth {
1186 u8 size;
1187 u8 rsvd;
1188 __be16 id;
1189 u8 rsvd1[6];
1190 u8 dst_mac[6];
1191 u16 rsvd2;
1192 u8 dst_mac_msk[6];
1193 u16 rsvd3;
1194 u8 src_mac[6];
1195 u16 rsvd4;
1196 u8 src_mac_msk[6];
1197 u8 rsvd5;
1198 u8 ether_type_enable;
1199 __be16 ether_type;
1200 __be16 vlan_tag_msk;
1201 __be16 vlan_tag;
1202 } __packed;
1203
1204 struct mlx4_net_trans_rule_hw_tcp_udp {
1205 u8 size;
1206 u8 rsvd;
1207 __be16 id;
1208 __be16 rsvd1[3];
1209 __be16 dst_port;
1210 __be16 rsvd2;
1211 __be16 dst_port_msk;
1212 __be16 rsvd3;
1213 __be16 src_port;
1214 __be16 rsvd4;
1215 __be16 src_port_msk;
1216 } __packed;
1217
1218 struct mlx4_net_trans_rule_hw_ipv4 {
1219 u8 size;
1220 u8 rsvd;
1221 __be16 id;
1222 __be32 rsvd1;
1223 __be32 dst_ip;
1224 __be32 dst_ip_msk;
1225 __be32 src_ip;
1226 __be32 src_ip_msk;
1227 } __packed;
1228
1229 struct _rule_hw {
1230 union {
1231 struct {
1232 u8 size;
1233 u8 rsvd;
1234 __be16 id;
1235 };
1236 struct mlx4_net_trans_rule_hw_eth eth;
1237 struct mlx4_net_trans_rule_hw_ib ib;
1238 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1239 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1240 };
1241 };
1242
1243 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1244 enum mlx4_net_trans_promisc_mode mode);
1245 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1246 enum mlx4_net_trans_promisc_mode mode);
1247 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1248 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1249 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1250 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1251
1252 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1253 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1254 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1255 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1256 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, unsigned long *stats_bitmap);
1257 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1258 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1259 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1260 u8 promisc);
1261 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
1262 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
1263 u8 *pg, u16 *ratelimit);
1264 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1265 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1266 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1267
1268 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1269 int npages, u64 iova, u32 *lkey, u32 *rkey);
1270 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1271 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1272 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1273 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1274 u32 *lkey, u32 *rkey);
1275 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1276 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1277 int mlx4_query_diag_counters(struct mlx4_dev *mlx4_dev, int array_length,
1278 u8 op_modifier, u32 in_offset[],
1279 u32 counter_out[]);
1280
1281 int mlx4_test_interrupts(struct mlx4_dev *dev);
1282 int mlx4_assign_eq(struct mlx4_dev *dev, char* name, int * vector);
1283 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1284
1285 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1286 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1287
1288 int mlx4_counter_alloc(struct mlx4_dev *dev, u8 port, u32 *idx);
1289 void mlx4_counter_free(struct mlx4_dev *dev, u8 port, u32 idx);
1290
1291 int mlx4_flow_attach(struct mlx4_dev *dev,
1292 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1293 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1294 int map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1295 enum mlx4_net_trans_promisc_mode flow_type);
1296 int map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1297 enum mlx4_net_trans_rule_id id);
1298 int hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1299
1300 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1301 int i, int val);
1302
1303 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1304
1305 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1306 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1307 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1308 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr, u16 lid, u8 sl);
1309 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1310 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1311 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1312
1313 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1314 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1315 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, int *slave_id);
1316 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, u8 *gid);
1317
1318 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, u32 max_range_qpn);
1319
1320 int mlx4_read_clock(struct mlx4_dev *dev);
1321 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1322 struct mlx4_clock_params *params);
1323
1324 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
1325 u16 offset, u16 size, u8 *data);
1326
1327 #endif /* MLX4_DEVICE_H */
1328