1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DM_SERVICES_TYPES_H__ 27 #define __DM_SERVICES_TYPES_H__ 28 29 #include "os_types.h" 30 #include "dc_types.h" 31 32 struct pp_smu_funcs_rv; 33 34 struct dm_pp_clock_range { 35 int min_khz; 36 int max_khz; 37 }; 38 39 enum dm_pp_clocks_state { 40 DM_PP_CLOCKS_STATE_INVALID, 41 DM_PP_CLOCKS_STATE_ULTRA_LOW, 42 DM_PP_CLOCKS_STATE_LOW, 43 DM_PP_CLOCKS_STATE_NOMINAL, 44 DM_PP_CLOCKS_STATE_PERFORMANCE, 45 46 /* Starting from DCE11, Max 8 levels of DPM state supported. */ 47 DM_PP_CLOCKS_DPM_STATE_LEVEL_INVALID = DM_PP_CLOCKS_STATE_INVALID, 48 DM_PP_CLOCKS_DPM_STATE_LEVEL_0, 49 DM_PP_CLOCKS_DPM_STATE_LEVEL_1, 50 DM_PP_CLOCKS_DPM_STATE_LEVEL_2, 51 /* to be backward compatible */ 52 DM_PP_CLOCKS_DPM_STATE_LEVEL_3, 53 DM_PP_CLOCKS_DPM_STATE_LEVEL_4, 54 DM_PP_CLOCKS_DPM_STATE_LEVEL_5, 55 DM_PP_CLOCKS_DPM_STATE_LEVEL_6, 56 DM_PP_CLOCKS_DPM_STATE_LEVEL_7, 57 58 DM_PP_CLOCKS_MAX_STATES 59 }; 60 61 struct dm_pp_gpu_clock_range { 62 enum dm_pp_clocks_state clock_state; 63 struct dm_pp_clock_range sclk; 64 struct dm_pp_clock_range mclk; 65 struct dm_pp_clock_range eclk; 66 struct dm_pp_clock_range dclk; 67 }; 68 69 enum dm_pp_clock_type { 70 DM_PP_CLOCK_TYPE_DISPLAY_CLK = 1, 71 DM_PP_CLOCK_TYPE_ENGINE_CLK, /* System clock */ 72 DM_PP_CLOCK_TYPE_MEMORY_CLK, 73 DM_PP_CLOCK_TYPE_DCFCLK, 74 DM_PP_CLOCK_TYPE_DCEFCLK, 75 DM_PP_CLOCK_TYPE_SOCCLK, 76 DM_PP_CLOCK_TYPE_PIXELCLK, 77 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, 78 DM_PP_CLOCK_TYPE_DPPCLK, 79 DM_PP_CLOCK_TYPE_FCLK, 80 }; 81 82 #define DC_DECODE_PP_CLOCK_TYPE(clk_type) \ 83 (clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \ 84 (clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \ 85 (clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : "Invalid" 86 87 #define DM_PP_MAX_CLOCK_LEVELS 8 88 89 struct dm_pp_clock_levels { 90 uint32_t num_levels; 91 uint32_t clocks_in_khz[DM_PP_MAX_CLOCK_LEVELS]; 92 }; 93 94 struct dm_pp_clock_with_latency { 95 uint32_t clocks_in_khz; 96 uint32_t latency_in_us; 97 }; 98 99 struct dm_pp_clock_levels_with_latency { 100 uint32_t num_levels; 101 struct dm_pp_clock_with_latency data[DM_PP_MAX_CLOCK_LEVELS]; 102 }; 103 104 struct dm_pp_clock_with_voltage { 105 uint32_t clocks_in_khz; 106 uint32_t voltage_in_mv; 107 }; 108 109 struct dm_pp_clock_levels_with_voltage { 110 uint32_t num_levels; 111 struct dm_pp_clock_with_voltage data[DM_PP_MAX_CLOCK_LEVELS]; 112 }; 113 114 struct dm_pp_single_disp_config { 115 enum signal_type signal; 116 uint8_t transmitter; 117 uint8_t ddi_channel_mapping; 118 uint8_t pipe_idx; 119 uint32_t src_height; 120 uint32_t src_width; 121 uint32_t v_refresh; 122 uint32_t sym_clock; /* HDMI only */ 123 struct dc_link_settings link_settings; /* DP only */ 124 }; 125 126 #define MAX_WM_SETS 4 127 128 enum dm_pp_wm_set_id { 129 WM_SET_A = 0, 130 WM_SET_B, 131 WM_SET_C, 132 WM_SET_D, 133 WM_SET_INVALID = 0xffff, 134 }; 135 136 struct dm_pp_clock_range_for_wm_set { 137 enum dm_pp_wm_set_id wm_set_id; 138 uint32_t wm_min_eng_clk_in_khz; 139 uint32_t wm_max_eng_clk_in_khz; 140 uint32_t wm_min_mem_clk_in_khz; 141 uint32_t wm_max_mem_clk_in_khz; 142 }; 143 144 struct dm_pp_wm_sets_with_clock_ranges { 145 uint32_t num_wm_sets; 146 struct dm_pp_clock_range_for_wm_set wm_clk_ranges[MAX_WM_SETS]; 147 }; 148 149 struct dm_pp_clock_range_for_dmif_wm_set_soc15 { 150 enum dm_pp_wm_set_id wm_set_id; 151 uint32_t wm_min_dcfclk_clk_in_khz; 152 uint32_t wm_max_dcfclk_clk_in_khz; 153 uint32_t wm_min_mem_clk_in_khz; 154 uint32_t wm_max_mem_clk_in_khz; 155 }; 156 157 struct dm_pp_clock_range_for_mcif_wm_set_soc15 { 158 enum dm_pp_wm_set_id wm_set_id; 159 uint32_t wm_min_socclk_clk_in_khz; 160 uint32_t wm_max_socclk_clk_in_khz; 161 uint32_t wm_min_mem_clk_in_khz; 162 uint32_t wm_max_mem_clk_in_khz; 163 }; 164 165 struct dm_pp_wm_sets_with_clock_ranges_soc15 { 166 uint32_t num_wm_dmif_sets; 167 uint32_t num_wm_mcif_sets; 168 struct dm_pp_clock_range_for_dmif_wm_set_soc15 169 wm_dmif_clocks_ranges[MAX_WM_SETS]; 170 struct dm_pp_clock_range_for_mcif_wm_set_soc15 171 wm_mcif_clocks_ranges[MAX_WM_SETS]; 172 }; 173 174 #define MAX_DISPLAY_CONFIGS 6 175 176 struct dm_pp_display_configuration { 177 bool nb_pstate_switch_disable;/* controls NB PState switch */ 178 bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */ 179 bool cpu_pstate_disable; 180 uint32_t cpu_pstate_separation_time; 181 182 uint32_t min_memory_clock_khz; 183 uint32_t min_engine_clock_khz; 184 uint32_t min_engine_clock_deep_sleep_khz; 185 186 uint32_t avail_mclk_switch_time_us; 187 uint32_t avail_mclk_switch_time_in_disp_active_us; 188 uint32_t min_dcfclock_khz; 189 uint32_t min_dcfc_deep_sleep_clock_khz; 190 191 uint32_t disp_clk_khz; 192 193 bool all_displays_in_sync; 194 195 uint8_t display_count; 196 struct dm_pp_single_disp_config disp_configs[MAX_DISPLAY_CONFIGS]; 197 198 /*Controller Index of primary display - used in MCLK SMC switching hang 199 * SW Workaround*/ 200 uint8_t crtc_index; 201 /*htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/ 202 uint32_t line_time_in_us; 203 }; 204 205 struct dm_bl_data_point { 206 /* Brightness level in percentage */ 207 uint8_t luminance; 208 /* Brightness level as effective value in range 0-255, 209 * corresponding to above percentage 210 */ 211 uint8_t signalLevel; 212 }; 213 214 /* Total size of the structure should not exceed 256 bytes */ 215 struct dm_acpi_atif_backlight_caps { 216 217 218 uint16_t size; /* Bytes 0-1 (2 bytes) */ 219 uint16_t flags; /* Byted 2-3 (2 bytes) */ 220 uint8_t errorCode; /* Byte 4 */ 221 uint8_t acLevelPercentage; /* Byte 5 */ 222 uint8_t dcLevelPercentage; /* Byte 6 */ 223 uint8_t minInputSignal; /* Byte 7 */ 224 uint8_t maxInputSignal; /* Byte 8 */ 225 uint8_t numOfDataPoints; /* Byte 9 */ 226 struct dm_bl_data_point dataPoints[99]; /* Bytes 10-207 (198 bytes)*/ 227 }; 228 229 enum dm_acpi_display_type { 230 AcpiDisplayType_LCD1 = 0, 231 AcpiDisplayType_CRT1 = 1, 232 AcpiDisplayType_DFP1 = 3, 233 AcpiDisplayType_CRT2 = 4, 234 AcpiDisplayType_LCD2 = 5, 235 AcpiDisplayType_DFP2 = 7, 236 AcpiDisplayType_DFP3 = 9, 237 AcpiDisplayType_DFP4 = 10, 238 AcpiDisplayType_DFP5 = 11, 239 AcpiDisplayType_DFP6 = 12 240 }; 241 242 struct dm_pp_power_level_change_request { 243 enum dm_pp_clocks_state power_level; 244 }; 245 246 struct dm_pp_clock_for_voltage_req { 247 enum dm_pp_clock_type clk_type; 248 uint32_t clocks_in_khz; 249 }; 250 251 struct dm_pp_static_clock_info { 252 uint32_t max_sclk_khz; 253 uint32_t max_mclk_khz; 254 255 /* max possible display block clocks state */ 256 enum dm_pp_clocks_state max_clocks_state; 257 }; 258 259 struct dtn_min_clk_info { 260 uint32_t disp_clk_khz; 261 uint32_t min_engine_clock_khz; 262 uint32_t min_memory_clock_khz; 263 }; 264 265 #endif 266