1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Copyright 1994-2009 The FreeBSD Project.
9 * All rights reserved.
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE FREEBSD PROJECT``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
19 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FREEBSD PROJECT OR
21 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
22 * EXEMPLARY,OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
23 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
24 * PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY THEORY
25 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
26 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * The views and conclusions contained in the software and documentation
30 * are those of the authors and should not be interpreted as representing
31 * official policies,either expressed or implied, of the FreeBSD Project.
32 */
33
34 #include <sys/cdefs.h>
35 #include "opt_mfi.h"
36
37 #include <sys/param.h>
38 #include <sys/types.h>
39 #include <sys/kernel.h>
40 #include <sys/selinfo.h>
41 #include <sys/bus.h>
42 #include <sys/conf.h>
43 #include <sys/bio.h>
44 #include <sys/ioccom.h>
45 #include <sys/eventhandler.h>
46 #include <sys/callout.h>
47 #include <sys/uio.h>
48 #include <machine/bus.h>
49 #include <sys/sysctl.h>
50 #include <sys/systm.h>
51 #include <sys/malloc.h>
52
53 #include <dev/mfi/mfireg.h>
54 #include <dev/mfi/mfi_ioctl.h>
55 #include <dev/mfi/mfivar.h>
56
57 struct mfi_cmd_tbolt *mfi_tbolt_get_cmd(struct mfi_softc *sc, struct mfi_command *);
58 union mfi_mpi2_request_descriptor *
59 mfi_tbolt_get_request_descriptor(struct mfi_softc *sc, uint16_t index);
60 void mfi_tbolt_complete_cmd(struct mfi_softc *sc);
61 int mfi_tbolt_build_io(struct mfi_softc *sc, struct mfi_command *mfi_cmd,
62 struct mfi_cmd_tbolt *cmd);
63 union mfi_mpi2_request_descriptor *mfi_tbolt_build_mpt_cmd(struct mfi_softc
64 *sc, struct mfi_command *cmd);
65 uint8_t
66 mfi_build_mpt_pass_thru(struct mfi_softc *sc, struct mfi_command *mfi_cmd);
67 union mfi_mpi2_request_descriptor *mfi_build_and_issue_cmd(struct mfi_softc
68 *sc, struct mfi_command *mfi_cmd);
69 void mfi_tbolt_build_ldio(struct mfi_softc *sc, struct mfi_command *mfi_cmd,
70 struct mfi_cmd_tbolt *cmd);
71 static int mfi_tbolt_make_sgl(struct mfi_softc *sc, struct mfi_command
72 *mfi_cmd, pMpi25IeeeSgeChain64_t sgl_ptr, struct mfi_cmd_tbolt *cmd);
73 void
74 map_tbolt_cmd_status(struct mfi_command *mfi_cmd, uint8_t status,
75 uint8_t ext_status);
76 static void mfi_issue_pending_cmds_again (struct mfi_softc *sc);
77 static void mfi_kill_hba (struct mfi_softc *sc);
78 static void mfi_process_fw_state_chg_isr(void *arg);
79 static void mfi_sync_map_complete(struct mfi_command *);
80 static void mfi_queue_map_sync(struct mfi_softc *sc);
81
82 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000008)
83
84 extern int mfi_polled_cmd_timeout;
85 static int mfi_fw_reset_test = 0;
86 #ifdef MFI_DEBUG
87 SYSCTL_INT(_hw_mfi, OID_AUTO, fw_reset_test, CTLFLAG_RWTUN, &mfi_fw_reset_test,
88 0, "Force a firmware reset condition");
89 #endif
90
91 void
mfi_tbolt_enable_intr_ppc(struct mfi_softc * sc)92 mfi_tbolt_enable_intr_ppc(struct mfi_softc *sc)
93 {
94 MFI_WRITE4(sc, MFI_OMSK, ~MFI_FUSION_ENABLE_INTERRUPT_MASK);
95 MFI_READ4(sc, MFI_OMSK);
96 }
97
98 void
mfi_tbolt_disable_intr_ppc(struct mfi_softc * sc)99 mfi_tbolt_disable_intr_ppc(struct mfi_softc *sc)
100 {
101 MFI_WRITE4(sc, MFI_OMSK, 0xFFFFFFFF);
102 MFI_READ4(sc, MFI_OMSK);
103 }
104
105 int32_t
mfi_tbolt_read_fw_status_ppc(struct mfi_softc * sc)106 mfi_tbolt_read_fw_status_ppc(struct mfi_softc *sc)
107 {
108 return MFI_READ4(sc, MFI_OSP0);
109 }
110
111 int32_t
mfi_tbolt_check_clear_intr_ppc(struct mfi_softc * sc)112 mfi_tbolt_check_clear_intr_ppc(struct mfi_softc *sc)
113 {
114 int32_t status, mfi_status = 0;
115
116 status = MFI_READ4(sc, MFI_OSTS);
117
118 if (status & 1) {
119 MFI_WRITE4(sc, MFI_OSTS, status);
120 MFI_READ4(sc, MFI_OSTS);
121 if (status & MFI_STATE_CHANGE_INTERRUPT) {
122 mfi_status |= MFI_FIRMWARE_STATE_CHANGE;
123 }
124
125 return mfi_status;
126 }
127 if (!(status & MFI_FUSION_ENABLE_INTERRUPT_MASK))
128 return 1;
129
130 MFI_READ4(sc, MFI_OSTS);
131 return 0;
132 }
133
134 void
mfi_tbolt_issue_cmd_ppc(struct mfi_softc * sc,bus_addr_t bus_add,uint32_t frame_cnt)135 mfi_tbolt_issue_cmd_ppc(struct mfi_softc *sc, bus_addr_t bus_add,
136 uint32_t frame_cnt)
137 {
138 bus_add |= (MFI_REQ_DESCRIPT_FLAGS_MFA
139 << MFI_REQ_DESCRIPT_FLAGS_TYPE_SHIFT);
140 MFI_WRITE4(sc, MFI_IQPL, (uint32_t)bus_add);
141 MFI_WRITE4(sc, MFI_IQPH, (uint32_t)((uint64_t)bus_add >> 32));
142 }
143
144 /*
145 * mfi_tbolt_adp_reset - For controller reset
146 * @regs: MFI register set
147 */
148 int
mfi_tbolt_adp_reset(struct mfi_softc * sc)149 mfi_tbolt_adp_reset(struct mfi_softc *sc)
150 {
151 int retry = 0, i = 0;
152 int HostDiag;
153
154 MFI_WRITE4(sc, MFI_WSR, 0xF);
155 MFI_WRITE4(sc, MFI_WSR, 4);
156 MFI_WRITE4(sc, MFI_WSR, 0xB);
157 MFI_WRITE4(sc, MFI_WSR, 2);
158 MFI_WRITE4(sc, MFI_WSR, 7);
159 MFI_WRITE4(sc, MFI_WSR, 0xD);
160
161 for (i = 0; i < 10000; i++) ;
162
163 HostDiag = (uint32_t)MFI_READ4(sc, MFI_HDR);
164
165 while (!( HostDiag & DIAG_WRITE_ENABLE)) {
166 for (i = 0; i < 1000; i++);
167 HostDiag = (uint32_t)MFI_READ4(sc, MFI_HDR);
168 device_printf(sc->mfi_dev, "ADP_RESET_TBOLT: retry time=%d, "
169 "hostdiag=%#x\n", retry, HostDiag);
170
171 if (retry++ >= 100)
172 return 1;
173 }
174
175 device_printf(sc->mfi_dev, "ADP_RESET_TBOLT: HostDiag=%#x\n", HostDiag);
176
177 MFI_WRITE4(sc, MFI_HDR, (HostDiag | DIAG_RESET_ADAPTER));
178
179 for (i=0; i < 10; i++) {
180 for (i = 0; i < 10000; i++);
181 }
182
183 HostDiag = (uint32_t)MFI_READ4(sc, MFI_RSR);
184 while (HostDiag & DIAG_RESET_ADAPTER) {
185 for (i = 0; i < 1000; i++) ;
186 HostDiag = (uint32_t)MFI_READ4(sc, MFI_RSR);
187 device_printf(sc->mfi_dev, "ADP_RESET_TBOLT: retry time=%d, "
188 "hostdiag=%#x\n", retry, HostDiag);
189
190 if (retry++ >= 1000)
191 return 1;
192 }
193 return 0;
194 }
195
196 /*
197 * This routine initialize Thunderbolt specific device information
198 */
199 void
mfi_tbolt_init_globals(struct mfi_softc * sc)200 mfi_tbolt_init_globals(struct mfi_softc *sc)
201 {
202 /* Initialize single reply size and Message size */
203 sc->reply_size = MEGASAS_THUNDERBOLT_REPLY_SIZE;
204 sc->raid_io_msg_size = MEGASAS_THUNDERBOLT_NEW_MSG_SIZE;
205
206 /*
207 * Calculating how many SGEs allowed in a allocated main message
208 * (size of the Message - Raid SCSI IO message size(except SGE))
209 * / size of SGE
210 * (0x100 - (0x90 - 0x10)) / 0x10 = 8
211 */
212 sc->max_SGEs_in_main_message =
213 (uint8_t)((sc->raid_io_msg_size
214 - (sizeof(struct mfi_mpi2_request_raid_scsi_io)
215 - sizeof(MPI2_SGE_IO_UNION))) / sizeof(MPI2_SGE_IO_UNION));
216 /*
217 * (Command frame size allocaed in SRB ext - Raid SCSI IO message size)
218 * / size of SGL ;
219 * (1280 - 256) / 16 = 64
220 */
221 sc->max_SGEs_in_chain_message = (MR_COMMAND_SIZE
222 - sc->raid_io_msg_size) / sizeof(MPI2_SGE_IO_UNION);
223 /*
224 * (0x08-1) + 0x40 = 0x47 - 0x01 = 0x46 one is left for command
225 * colscing
226 */
227 sc->mfi_max_sge = (sc->max_SGEs_in_main_message - 1)
228 + sc->max_SGEs_in_chain_message - 1;
229 /*
230 * This is the offset in number of 4 * 32bit words to the next chain
231 * (0x100 - 0x10)/0x10 = 0xF(15)
232 */
233 sc->chain_offset_value_for_main_message = (sc->raid_io_msg_size
234 - sizeof(MPI2_SGE_IO_UNION))/16;
235 sc->chain_offset_value_for_mpt_ptmsg
236 = offsetof(struct mfi_mpi2_request_raid_scsi_io, SGL)/16;
237 sc->mfi_cmd_pool_tbolt = NULL;
238 sc->request_desc_pool = NULL;
239 }
240
241 /*
242 * This function calculates the memory requirement for Thunderbolt
243 * controller, returns the total required memory in bytes
244 */
245
246 uint32_t
mfi_tbolt_get_memory_requirement(struct mfi_softc * sc)247 mfi_tbolt_get_memory_requirement(struct mfi_softc *sc)
248 {
249 uint32_t size;
250 size = MEGASAS_THUNDERBOLT_MSG_ALLIGNMENT; /* for Alignment */
251 size += sc->raid_io_msg_size * (sc->mfi_max_fw_cmds + 1);
252 size += sc->reply_size * sc->mfi_max_fw_cmds;
253 /* this is for SGL's */
254 size += MEGASAS_MAX_SZ_CHAIN_FRAME * sc->mfi_max_fw_cmds;
255 return size;
256 }
257
258 /*
259 * Description:
260 * This function will prepare message pools for the Thunderbolt controller
261 * Arguments:
262 * DevExt - HBA miniport driver's adapter data storage structure
263 * pMemLocation - start of the memory allocated for Thunderbolt.
264 * Return Value:
265 * TRUE if successful
266 * FALSE if failed
267 */
268 int
mfi_tbolt_init_desc_pool(struct mfi_softc * sc,uint8_t * mem_location,uint32_t tbolt_contg_length)269 mfi_tbolt_init_desc_pool(struct mfi_softc *sc, uint8_t* mem_location,
270 uint32_t tbolt_contg_length)
271 {
272 uint32_t offset = 0;
273 uint8_t *addr = mem_location;
274
275 /* Request Descriptor Base physical Address */
276
277 /* For Request Decriptors Virtual Memory */
278 /* Initialise the aligned IO Frames Virtual Memory Pointer */
279 if (((uintptr_t)addr) & (0xFF)) {
280 addr = &addr[sc->raid_io_msg_size];
281 addr = (uint8_t *)((uintptr_t)addr & (~0xFF));
282 sc->request_message_pool_align = addr;
283 } else
284 sc->request_message_pool_align = addr;
285
286 offset = sc->request_message_pool_align - sc->request_message_pool;
287 sc->request_msg_busaddr = sc->mfi_tb_busaddr + offset;
288
289 /* DJA XXX should this be bus dma ??? */
290 /* Skip request message pool */
291 addr = &addr[sc->raid_io_msg_size * (sc->mfi_max_fw_cmds + 1)];
292 /* Reply Frame Pool is initialized */
293 sc->reply_frame_pool = (struct mfi_mpi2_reply_header *) addr;
294 if (((uintptr_t)addr) & (0xFF)) {
295 addr = &addr[sc->reply_size];
296 addr = (uint8_t *)((uintptr_t)addr & (~0xFF));
297 }
298 sc->reply_frame_pool_align
299 = (struct mfi_mpi2_reply_header *)addr;
300
301 offset = (uintptr_t)sc->reply_frame_pool_align
302 - (uintptr_t)sc->request_message_pool;
303 sc->reply_frame_busaddr = sc->mfi_tb_busaddr + offset;
304
305 /* Skip Reply Frame Pool */
306 addr += sc->reply_size * sc->mfi_max_fw_cmds;
307 sc->reply_pool_limit = addr;
308
309 /* initializing reply address to 0xFFFFFFFF */
310 memset((uint8_t *)sc->reply_frame_pool, 0xFF,
311 (sc->reply_size * sc->mfi_max_fw_cmds));
312
313 offset = sc->reply_size * sc->mfi_max_fw_cmds;
314 sc->sg_frame_busaddr = sc->reply_frame_busaddr + offset;
315 /* initialize the last_reply_idx to 0 */
316 sc->last_reply_idx = 0;
317 MFI_WRITE4(sc, MFI_RFPI, sc->mfi_max_fw_cmds - 1);
318 MFI_WRITE4(sc, MFI_RPI, sc->last_reply_idx);
319 offset = (sc->sg_frame_busaddr + (MEGASAS_MAX_SZ_CHAIN_FRAME *
320 sc->mfi_max_fw_cmds)) - sc->mfi_tb_busaddr;
321 if (offset > tbolt_contg_length)
322 device_printf(sc->mfi_dev, "Error:Initialized more than "
323 "allocated\n");
324 return 0;
325 }
326
327 /*
328 * This routine prepare and issue INIT2 frame to the Firmware
329 */
330
331 int
mfi_tbolt_init_MFI_queue(struct mfi_softc * sc)332 mfi_tbolt_init_MFI_queue(struct mfi_softc *sc)
333 {
334 struct MPI2_IOC_INIT_REQUEST *mpi2IocInit;
335 struct mfi_init_frame *mfi_init;
336 uintptr_t offset = 0;
337 bus_addr_t phyAddress;
338 MFI_ADDRESS *mfiAddressTemp;
339 struct mfi_command *cm, cmd_tmp;
340 int error;
341
342 mtx_assert(&sc->mfi_io_lock, MA_OWNED);
343
344 /* Check if initialization is already completed */
345 if (sc->MFA_enabled) {
346 device_printf(sc->mfi_dev, "tbolt_init already initialised!\n");
347 return 1;
348 }
349
350 if ((cm = mfi_dequeue_free(sc)) == NULL) {
351 device_printf(sc->mfi_dev, "tbolt_init failed to get command "
352 " entry!\n");
353 return (EBUSY);
354 }
355
356 cmd_tmp.cm_frame = cm->cm_frame;
357 cmd_tmp.cm_frame_busaddr = cm->cm_frame_busaddr;
358 cmd_tmp.cm_dmamap = cm->cm_dmamap;
359
360 cm->cm_frame = (union mfi_frame *)((uintptr_t)sc->mfi_tb_init);
361 cm->cm_frame_busaddr = sc->mfi_tb_init_busaddr;
362 cm->cm_dmamap = sc->mfi_tb_init_dmamap;
363 cm->cm_frame->header.context = 0;
364
365 /*
366 * Abuse the SG list area of the frame to hold the init_qinfo
367 * object;
368 */
369 mfi_init = &cm->cm_frame->init;
370
371 mpi2IocInit = (struct MPI2_IOC_INIT_REQUEST *)sc->mfi_tb_ioc_init_desc;
372 bzero(mpi2IocInit, sizeof(struct MPI2_IOC_INIT_REQUEST));
373 mpi2IocInit->Function = MPI2_FUNCTION_IOC_INIT;
374 mpi2IocInit->WhoInit = MPI2_WHOINIT_HOST_DRIVER;
375
376 /* set MsgVersion and HeaderVersion host driver was built with */
377 mpi2IocInit->MsgVersion = MPI2_VERSION;
378 mpi2IocInit->HeaderVersion = MPI2_HEADER_VERSION;
379 mpi2IocInit->SystemRequestFrameSize = sc->raid_io_msg_size/4;
380 mpi2IocInit->ReplyDescriptorPostQueueDepth
381 = (uint16_t)sc->mfi_max_fw_cmds;
382 mpi2IocInit->ReplyFreeQueueDepth = 0; /* Not supported by MR. */
383
384 /* Get physical address of reply frame pool */
385 offset = (uintptr_t) sc->reply_frame_pool_align
386 - (uintptr_t)sc->request_message_pool;
387 phyAddress = sc->mfi_tb_busaddr + offset;
388 mfiAddressTemp =
389 (MFI_ADDRESS *)&mpi2IocInit->ReplyDescriptorPostQueueAddress;
390 mfiAddressTemp->u.addressLow = (uint32_t)phyAddress;
391 mfiAddressTemp->u.addressHigh = (uint32_t)((uint64_t)phyAddress >> 32);
392
393 /* Get physical address of request message pool */
394 offset = sc->request_message_pool_align - sc->request_message_pool;
395 phyAddress = sc->mfi_tb_busaddr + offset;
396 mfiAddressTemp = (MFI_ADDRESS *)&mpi2IocInit->SystemRequestFrameBaseAddress;
397 mfiAddressTemp->u.addressLow = (uint32_t)phyAddress;
398 mfiAddressTemp->u.addressHigh = (uint32_t)((uint64_t)phyAddress >> 32);
399 mpi2IocInit->ReplyFreeQueueAddress = 0; /* Not supported by MR. */
400 mpi2IocInit->TimeStamp = time_uptime;
401
402 if (sc->verbuf) {
403 snprintf((char *)sc->verbuf, strlen(MEGASAS_VERSION) + 2, "%s\n",
404 MEGASAS_VERSION);
405 mfi_init->driver_ver_lo = (uint32_t)sc->verbuf_h_busaddr;
406 mfi_init->driver_ver_hi =
407 (uint32_t)((uint64_t)sc->verbuf_h_busaddr >> 32);
408 }
409 /* Get the physical address of the mpi2 ioc init command */
410 phyAddress = sc->mfi_tb_ioc_init_busaddr;
411 mfi_init->qinfo_new_addr_lo = (uint32_t)phyAddress;
412 mfi_init->qinfo_new_addr_hi = (uint32_t)((uint64_t)phyAddress >> 32);
413 mfi_init->header.flags |= MFI_FRAME_DONT_POST_IN_REPLY_QUEUE;
414
415 mfi_init->header.cmd = MFI_CMD_INIT;
416 mfi_init->header.data_len = sizeof(struct MPI2_IOC_INIT_REQUEST);
417 mfi_init->header.cmd_status = MFI_STAT_INVALID_STATUS;
418
419 cm->cm_data = NULL;
420 cm->cm_flags |= MFI_CMD_POLLED;
421 cm->cm_timestamp = time_uptime;
422 if ((error = mfi_mapcmd(sc, cm)) != 0) {
423 device_printf(sc->mfi_dev, "failed to send IOC init2 "
424 "command %d at %lx\n", error, (long)cm->cm_frame_busaddr);
425 goto out;
426 }
427
428 if (mfi_init->header.cmd_status == MFI_STAT_OK) {
429 sc->MFA_enabled = 1;
430 } else {
431 device_printf(sc->mfi_dev, "Init command Failed %#x\n",
432 mfi_init->header.cmd_status);
433 error = mfi_init->header.cmd_status;
434 goto out;
435 }
436
437 out:
438 cm->cm_frame = cmd_tmp.cm_frame;
439 cm->cm_frame_busaddr = cmd_tmp.cm_frame_busaddr;
440 cm->cm_dmamap = cmd_tmp.cm_dmamap;
441 mfi_release_command(cm);
442
443 return (error);
444
445 }
446
447 int
mfi_tbolt_alloc_cmd(struct mfi_softc * sc)448 mfi_tbolt_alloc_cmd(struct mfi_softc *sc)
449 {
450 struct mfi_cmd_tbolt *cmd;
451 bus_addr_t io_req_base_phys;
452 uint8_t *io_req_base;
453 int i = 0, j = 0, offset = 0;
454
455 /*
456 * sc->mfi_cmd_pool_tbolt is an array of struct mfi_cmd_tbolt pointers.
457 * Allocate the dynamic array first and then allocate individual
458 * commands.
459 */
460 sc->request_desc_pool = malloc(sizeof(
461 union mfi_mpi2_request_descriptor) * sc->mfi_max_fw_cmds,
462 M_MFIBUF, M_NOWAIT|M_ZERO);
463
464 if (sc->request_desc_pool == NULL) {
465 device_printf(sc->mfi_dev, "Could not alloc "
466 "memory for request_desc_pool\n");
467 return (ENOMEM);
468 }
469
470 sc->mfi_cmd_pool_tbolt = malloc(sizeof(struct mfi_cmd_tbolt*)
471 * sc->mfi_max_fw_cmds, M_MFIBUF, M_NOWAIT|M_ZERO);
472
473 if (sc->mfi_cmd_pool_tbolt == NULL) {
474 free(sc->request_desc_pool, M_MFIBUF);
475 device_printf(sc->mfi_dev, "Could not alloc "
476 "memory for cmd_pool_tbolt\n");
477 return (ENOMEM);
478 }
479
480 for (i = 0; i < sc->mfi_max_fw_cmds; i++) {
481 sc->mfi_cmd_pool_tbolt[i] = malloc(sizeof(
482 struct mfi_cmd_tbolt),M_MFIBUF, M_NOWAIT|M_ZERO);
483
484 if (!sc->mfi_cmd_pool_tbolt[i]) {
485 device_printf(sc->mfi_dev, "Could not alloc "
486 "cmd_pool_tbolt entry\n");
487
488 for (j = 0; j < i; j++)
489 free(sc->mfi_cmd_pool_tbolt[j], M_MFIBUF);
490
491 free(sc->request_desc_pool, M_MFIBUF);
492 sc->request_desc_pool = NULL;
493 free(sc->mfi_cmd_pool_tbolt, M_MFIBUF);
494 sc->mfi_cmd_pool_tbolt = NULL;
495
496 return (ENOMEM);
497 }
498 }
499
500 /*
501 * The first 256 bytes (SMID 0) is not used. Don't add to the cmd
502 * list
503 */
504 io_req_base = sc->request_message_pool_align
505 + MEGASAS_THUNDERBOLT_NEW_MSG_SIZE;
506 io_req_base_phys = sc->request_msg_busaddr
507 + MEGASAS_THUNDERBOLT_NEW_MSG_SIZE;
508
509 /*
510 * Add all the commands to command pool (instance->cmd_pool)
511 */
512 /* SMID 0 is reserved. Set SMID/index from 1 */
513
514 for (i = 0; i < sc->mfi_max_fw_cmds; i++) {
515 cmd = sc->mfi_cmd_pool_tbolt[i];
516 offset = MEGASAS_THUNDERBOLT_NEW_MSG_SIZE * i;
517 cmd->index = i + 1;
518 cmd->request_desc = (union mfi_mpi2_request_descriptor *)
519 (sc->request_desc_pool + i);
520 cmd->io_request = (struct mfi_mpi2_request_raid_scsi_io *)
521 (io_req_base + offset);
522 cmd->io_request_phys_addr = io_req_base_phys + offset;
523 cmd->sg_frame = (MPI2_SGE_IO_UNION *)(sc->reply_pool_limit
524 + i * MEGASAS_MAX_SZ_CHAIN_FRAME);
525 cmd->sg_frame_phys_addr = sc->sg_frame_busaddr + i
526 * MEGASAS_MAX_SZ_CHAIN_FRAME;
527 cmd->sync_cmd_idx = sc->mfi_max_fw_cmds;
528
529 TAILQ_INSERT_TAIL(&(sc->mfi_cmd_tbolt_tqh), cmd, next);
530 }
531 return 0;
532 }
533
534 int
mfi_tbolt_reset(struct mfi_softc * sc)535 mfi_tbolt_reset(struct mfi_softc *sc)
536 {
537 uint32_t fw_state;
538
539 mtx_lock(&sc->mfi_io_lock);
540 if (sc->hw_crit_error) {
541 device_printf(sc->mfi_dev, "HW CRITICAL ERROR\n");
542 mtx_unlock(&sc->mfi_io_lock);
543 return 1;
544 }
545
546 if (sc->mfi_flags & MFI_FLAGS_TBOLT) {
547 fw_state = sc->mfi_read_fw_status(sc);
548 if ((fw_state & MFI_FWSTATE_FAULT) == MFI_FWSTATE_FAULT ||
549 mfi_fw_reset_test) {
550 if ((sc->disableOnlineCtrlReset == 0)
551 && (sc->adpreset == 0)) {
552 device_printf(sc->mfi_dev, "Adapter RESET "
553 "condition is detected\n");
554 sc->adpreset = 1;
555 sc->issuepend_done = 0;
556 sc->MFA_enabled = 0;
557 sc->last_reply_idx = 0;
558 mfi_process_fw_state_chg_isr((void *) sc);
559 }
560 mtx_unlock(&sc->mfi_io_lock);
561 return 0;
562 }
563 }
564 mtx_unlock(&sc->mfi_io_lock);
565 return 1;
566 }
567
568 /*
569 * mfi_intr_tbolt - isr entry point
570 */
571 void
mfi_intr_tbolt(void * arg)572 mfi_intr_tbolt(void *arg)
573 {
574 struct mfi_softc *sc = (struct mfi_softc *)arg;
575
576 if (sc->mfi_check_clear_intr(sc) == 1) {
577 return;
578 }
579 if (sc->mfi_detaching)
580 return;
581 mtx_lock(&sc->mfi_io_lock);
582 mfi_tbolt_complete_cmd(sc);
583 sc->mfi_flags &= ~MFI_FLAGS_QFRZN;
584 mfi_startio(sc);
585 mtx_unlock(&sc->mfi_io_lock);
586 return;
587 }
588
589 /*
590 * map_cmd_status - Maps FW cmd status to OS cmd status
591 * @cmd : Pointer to cmd
592 * @status : status of cmd returned by FW
593 * @ext_status : ext status of cmd returned by FW
594 */
595
596 void
map_tbolt_cmd_status(struct mfi_command * mfi_cmd,uint8_t status,uint8_t ext_status)597 map_tbolt_cmd_status(struct mfi_command *mfi_cmd, uint8_t status,
598 uint8_t ext_status)
599 {
600 switch (status) {
601 case MFI_STAT_OK:
602 mfi_cmd->cm_frame->header.cmd_status = MFI_STAT_OK;
603 mfi_cmd->cm_frame->dcmd.header.cmd_status = MFI_STAT_OK;
604 mfi_cmd->cm_error = MFI_STAT_OK;
605 break;
606
607 case MFI_STAT_SCSI_IO_FAILED:
608 case MFI_STAT_LD_INIT_IN_PROGRESS:
609 mfi_cmd->cm_frame->header.cmd_status = status;
610 mfi_cmd->cm_frame->header.scsi_status = ext_status;
611 mfi_cmd->cm_frame->dcmd.header.cmd_status = status;
612 mfi_cmd->cm_frame->dcmd.header.scsi_status
613 = ext_status;
614 break;
615
616 case MFI_STAT_SCSI_DONE_WITH_ERROR:
617 mfi_cmd->cm_frame->header.cmd_status = ext_status;
618 mfi_cmd->cm_frame->dcmd.header.cmd_status = ext_status;
619 break;
620
621 case MFI_STAT_LD_OFFLINE:
622 case MFI_STAT_DEVICE_NOT_FOUND:
623 mfi_cmd->cm_frame->header.cmd_status = status;
624 mfi_cmd->cm_frame->dcmd.header.cmd_status = status;
625 break;
626
627 default:
628 mfi_cmd->cm_frame->header.cmd_status = status;
629 mfi_cmd->cm_frame->dcmd.header.cmd_status = status;
630 break;
631 }
632 }
633
634 /*
635 * mfi_tbolt_return_cmd - Return a cmd to free command pool
636 * @instance: Adapter soft state
637 * @tbolt_cmd: Tbolt command packet to be returned to free command pool
638 * @mfi_cmd: Oning MFI command packe
639 */
640 void
mfi_tbolt_return_cmd(struct mfi_softc * sc,struct mfi_cmd_tbolt * tbolt_cmd,struct mfi_command * mfi_cmd)641 mfi_tbolt_return_cmd(struct mfi_softc *sc, struct mfi_cmd_tbolt *tbolt_cmd,
642 struct mfi_command *mfi_cmd)
643 {
644 mtx_assert(&sc->mfi_io_lock, MA_OWNED);
645
646 mfi_cmd->cm_flags &= ~MFI_CMD_TBOLT;
647 mfi_cmd->cm_extra_frames = 0;
648 tbolt_cmd->sync_cmd_idx = sc->mfi_max_fw_cmds;
649
650 TAILQ_INSERT_TAIL(&sc->mfi_cmd_tbolt_tqh, tbolt_cmd, next);
651 }
652
653 void
mfi_tbolt_complete_cmd(struct mfi_softc * sc)654 mfi_tbolt_complete_cmd(struct mfi_softc *sc)
655 {
656 struct mfi_mpi2_reply_header *desc, *reply_desc;
657 struct mfi_command *cmd_mfi; /* For MFA Cmds */
658 struct mfi_cmd_tbolt *cmd_tbolt;
659 uint16_t smid;
660 uint8_t reply_descript_type;
661 struct mfi_mpi2_request_raid_scsi_io *scsi_io_req;
662 uint32_t status, extStatus;
663 uint16_t num_completed;
664 union desc_value val;
665 mtx_assert(&sc->mfi_io_lock, MA_OWNED);
666
667 desc = (struct mfi_mpi2_reply_header *)
668 ((uintptr_t)sc->reply_frame_pool_align
669 + sc->last_reply_idx * sc->reply_size);
670 reply_desc = desc;
671
672 if (reply_desc == NULL) {
673 device_printf(sc->mfi_dev, "reply desc is NULL!!\n");
674 return;
675 }
676
677 reply_descript_type = reply_desc->ReplyFlags
678 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
679 if (reply_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
680 return;
681
682 num_completed = 0;
683 val.word = ((union mfi_mpi2_reply_descriptor *)desc)->words;
684
685 /* Read Reply descriptor */
686 while ((val.u.low != 0xFFFFFFFF) && (val.u.high != 0xFFFFFFFF)) {
687 smid = reply_desc->SMID;
688 if (smid == 0 || smid > sc->mfi_max_fw_cmds) {
689 device_printf(sc->mfi_dev, "smid is %d cannot "
690 "proceed - skipping\n", smid);
691 goto next;
692 }
693 cmd_tbolt = sc->mfi_cmd_pool_tbolt[smid - 1];
694 if (cmd_tbolt->sync_cmd_idx == sc->mfi_max_fw_cmds) {
695 device_printf(sc->mfi_dev, "cmd_tbolt %p "
696 "has invalid sync_cmd_idx=%d - skipping\n",
697 cmd_tbolt, cmd_tbolt->sync_cmd_idx);
698 goto next;
699 }
700 cmd_mfi = &sc->mfi_commands[cmd_tbolt->sync_cmd_idx];
701 scsi_io_req = cmd_tbolt->io_request;
702
703 status = cmd_mfi->cm_frame->dcmd.header.cmd_status;
704 extStatus = cmd_mfi->cm_frame->dcmd.header.scsi_status;
705 map_tbolt_cmd_status(cmd_mfi, status, extStatus);
706
707 /* mfi_tbolt_return_cmd is handled by mfi complete / return */
708 if ((cmd_mfi->cm_flags & MFI_CMD_SCSI) != 0 &&
709 (cmd_mfi->cm_flags & MFI_CMD_POLLED) != 0) {
710 /* polled LD/SYSPD IO command */
711 /* XXX mark okay for now DJA */
712 cmd_mfi->cm_frame->header.cmd_status = MFI_STAT_OK;
713
714 } else {
715 /* remove command from busy queue if not polled */
716 if ((cmd_mfi->cm_flags & MFI_ON_MFIQ_BUSY) != 0)
717 mfi_remove_busy(cmd_mfi);
718
719 /* complete the command */
720 mfi_complete(sc, cmd_mfi);
721 }
722
723 next:
724 sc->last_reply_idx++;
725 if (sc->last_reply_idx >= sc->mfi_max_fw_cmds) {
726 MFI_WRITE4(sc, MFI_RPI, sc->last_reply_idx);
727 sc->last_reply_idx = 0;
728 }
729
730 /* Set it back to all 0xfff */
731 ((union mfi_mpi2_reply_descriptor*)desc)->words =
732 ~((uint64_t)0x00);
733
734 num_completed++;
735
736 /* Get the next reply descriptor */
737 desc = (struct mfi_mpi2_reply_header *)
738 ((uintptr_t)sc->reply_frame_pool_align
739 + sc->last_reply_idx * sc->reply_size);
740 reply_desc = desc;
741 val.word = ((union mfi_mpi2_reply_descriptor*)desc)->words;
742 reply_descript_type = reply_desc->ReplyFlags
743 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
744 if (reply_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
745 break;
746 }
747
748 if (!num_completed)
749 return;
750
751 /* update replyIndex to FW */
752 if (sc->last_reply_idx)
753 MFI_WRITE4(sc, MFI_RPI, sc->last_reply_idx);
754
755 return;
756 }
757
758 /*
759 * mfi_get_cmd - Get a command from the free pool
760 * @instance: Adapter soft state
761 *
762 * Returns a free command from the pool
763 */
764
765 struct mfi_cmd_tbolt *
mfi_tbolt_get_cmd(struct mfi_softc * sc,struct mfi_command * mfi_cmd)766 mfi_tbolt_get_cmd(struct mfi_softc *sc, struct mfi_command *mfi_cmd)
767 {
768 struct mfi_cmd_tbolt *cmd = NULL;
769
770 mtx_assert(&sc->mfi_io_lock, MA_OWNED);
771
772 if ((cmd = TAILQ_FIRST(&sc->mfi_cmd_tbolt_tqh)) == NULL)
773 return (NULL);
774 TAILQ_REMOVE(&sc->mfi_cmd_tbolt_tqh, cmd, next);
775 memset((uint8_t *)cmd->sg_frame, 0, MEGASAS_MAX_SZ_CHAIN_FRAME);
776 memset((uint8_t *)cmd->io_request, 0,
777 MEGASAS_THUNDERBOLT_NEW_MSG_SIZE);
778
779 cmd->sync_cmd_idx = mfi_cmd->cm_index;
780 mfi_cmd->cm_extra_frames = cmd->index; /* Frame count used as SMID */
781 mfi_cmd->cm_flags |= MFI_CMD_TBOLT;
782
783 return cmd;
784 }
785
786 union mfi_mpi2_request_descriptor *
mfi_tbolt_get_request_descriptor(struct mfi_softc * sc,uint16_t index)787 mfi_tbolt_get_request_descriptor(struct mfi_softc *sc, uint16_t index)
788 {
789 uint8_t *p;
790
791 if (index >= sc->mfi_max_fw_cmds) {
792 device_printf(sc->mfi_dev, "Invalid SMID (0x%x)request "
793 "for descriptor\n", index);
794 return NULL;
795 }
796 p = sc->request_desc_pool + sizeof(union mfi_mpi2_request_descriptor)
797 * index;
798 memset(p, 0, sizeof(union mfi_mpi2_request_descriptor));
799 return (union mfi_mpi2_request_descriptor *)p;
800 }
801
802 /* Used to build IOCTL cmd */
803 uint8_t
mfi_build_mpt_pass_thru(struct mfi_softc * sc,struct mfi_command * mfi_cmd)804 mfi_build_mpt_pass_thru(struct mfi_softc *sc, struct mfi_command *mfi_cmd)
805 {
806 MPI25_IEEE_SGE_CHAIN64 *mpi25_ieee_chain;
807 struct mfi_mpi2_request_raid_scsi_io *io_req;
808 struct mfi_cmd_tbolt *cmd;
809
810 cmd = mfi_tbolt_get_cmd(sc, mfi_cmd);
811 if (!cmd)
812 return EBUSY;
813 io_req = cmd->io_request;
814 mpi25_ieee_chain = (MPI25_IEEE_SGE_CHAIN64 *)&io_req->SGL.IeeeChain;
815
816 io_req->Function = MPI2_FUNCTION_PASSTHRU_IO_REQUEST;
817 io_req->SGLOffset0 = offsetof(struct mfi_mpi2_request_raid_scsi_io,
818 SGL) / 4;
819 io_req->ChainOffset = sc->chain_offset_value_for_mpt_ptmsg;
820
821 mpi25_ieee_chain->Address = mfi_cmd->cm_frame_busaddr;
822
823 /*
824 In MFI pass thru, nextChainOffset will always be zero to
825 indicate the end of the chain.
826 */
827 mpi25_ieee_chain->Flags= MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT
828 | MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR;
829
830 /* setting the length to the maximum length */
831 mpi25_ieee_chain->Length = 1024;
832
833 return 0;
834 }
835
836 void
mfi_tbolt_build_ldio(struct mfi_softc * sc,struct mfi_command * mfi_cmd,struct mfi_cmd_tbolt * cmd)837 mfi_tbolt_build_ldio(struct mfi_softc *sc, struct mfi_command *mfi_cmd,
838 struct mfi_cmd_tbolt *cmd)
839 {
840 uint32_t start_lba_lo = 0, start_lba_hi = 0, device_id;
841 struct mfi_mpi2_request_raid_scsi_io *io_request;
842 struct IO_REQUEST_INFO io_info;
843
844 device_id = mfi_cmd->cm_frame->io.header.target_id;
845 io_request = cmd->io_request;
846 io_request->RaidContext.TargetID = device_id;
847 io_request->RaidContext.Status = 0;
848 io_request->RaidContext.exStatus = 0;
849 io_request->RaidContext.regLockFlags = 0;
850
851 start_lba_lo = mfi_cmd->cm_frame->io.lba_lo;
852 start_lba_hi = mfi_cmd->cm_frame->io.lba_hi;
853
854 memset(&io_info, 0, sizeof(struct IO_REQUEST_INFO));
855 io_info.ldStartBlock = ((uint64_t)start_lba_hi << 32) | start_lba_lo;
856 io_info.numBlocks = mfi_cmd->cm_frame->io.header.data_len;
857 io_info.ldTgtId = device_id;
858 if ((mfi_cmd->cm_frame->header.flags & MFI_FRAME_DIR_READ) ==
859 MFI_FRAME_DIR_READ)
860 io_info.isRead = 1;
861
862 io_request->RaidContext.timeoutValue
863 = MFI_FUSION_FP_DEFAULT_TIMEOUT;
864 io_request->Function = MPI2_FUNCTION_LD_IO_REQUEST;
865 io_request->DevHandle = device_id;
866 cmd->request_desc->header.RequestFlags
867 = (MFI_REQ_DESCRIPT_FLAGS_LD_IO
868 << MFI_REQ_DESCRIPT_FLAGS_TYPE_SHIFT);
869 if ((io_request->IoFlags == 6) && (io_info.numBlocks == 0))
870 io_request->RaidContext.RegLockLength = 0x100;
871 io_request->DataLength = mfi_cmd->cm_frame->io.header.data_len
872 * MFI_SECTOR_LEN;
873 }
874
875 int
mfi_tbolt_build_io(struct mfi_softc * sc,struct mfi_command * mfi_cmd,struct mfi_cmd_tbolt * cmd)876 mfi_tbolt_build_io(struct mfi_softc *sc, struct mfi_command *mfi_cmd,
877 struct mfi_cmd_tbolt *cmd)
878 {
879 struct mfi_mpi2_request_raid_scsi_io *io_request;
880 uint32_t sge_count;
881 uint8_t cdb_len;
882 int readop;
883 u_int64_t lba;
884
885 io_request = cmd->io_request;
886 if (!(mfi_cmd->cm_frame->header.cmd == MFI_CMD_LD_READ
887 || mfi_cmd->cm_frame->header.cmd == MFI_CMD_LD_WRITE))
888 return 1;
889
890 mfi_tbolt_build_ldio(sc, mfi_cmd, cmd);
891
892 /* Convert to SCSI command CDB */
893 bzero(io_request->CDB.CDB32, sizeof(io_request->CDB.CDB32));
894 if (mfi_cmd->cm_frame->header.cmd == MFI_CMD_LD_WRITE)
895 readop = 0;
896 else
897 readop = 1;
898
899 lba = mfi_cmd->cm_frame->io.lba_hi;
900 lba = (lba << 32) + mfi_cmd->cm_frame->io.lba_lo;
901 cdb_len = mfi_build_cdb(readop, 0, lba,
902 mfi_cmd->cm_frame->io.header.data_len, io_request->CDB.CDB32);
903
904 /* Just the CDB length, rest of the Flags are zero */
905 io_request->IoFlags = cdb_len;
906
907 /*
908 * Construct SGL
909 */
910 sge_count = mfi_tbolt_make_sgl(sc, mfi_cmd,
911 (pMpi25IeeeSgeChain64_t) &io_request->SGL, cmd);
912 if (sge_count > sc->mfi_max_sge) {
913 device_printf(sc->mfi_dev, "Error. sge_count (0x%x) exceeds "
914 "max (0x%x) allowed\n", sge_count, sc->mfi_max_sge);
915 return 1;
916 }
917 io_request->RaidContext.numSGE = sge_count;
918 io_request->SGLFlags = MPI2_SGE_FLAGS_64_BIT_ADDRESSING;
919
920 if (mfi_cmd->cm_frame->header.cmd == MFI_CMD_LD_WRITE)
921 io_request->Control = MPI2_SCSIIO_CONTROL_WRITE;
922 else
923 io_request->Control = MPI2_SCSIIO_CONTROL_READ;
924
925 io_request->SGLOffset0 = offsetof(
926 struct mfi_mpi2_request_raid_scsi_io, SGL)/4;
927
928 io_request->SenseBufferLowAddress = mfi_cmd->cm_sense_busaddr;
929 io_request->SenseBufferLength = MFI_SENSE_LEN;
930 io_request->RaidContext.Status = MFI_STAT_INVALID_STATUS;
931 io_request->RaidContext.exStatus = MFI_STAT_INVALID_STATUS;
932
933 return 0;
934 }
935
936 static int
mfi_tbolt_make_sgl(struct mfi_softc * sc,struct mfi_command * mfi_cmd,pMpi25IeeeSgeChain64_t sgl_ptr,struct mfi_cmd_tbolt * cmd)937 mfi_tbolt_make_sgl(struct mfi_softc *sc, struct mfi_command *mfi_cmd,
938 pMpi25IeeeSgeChain64_t sgl_ptr, struct mfi_cmd_tbolt *cmd)
939 {
940 uint8_t i, sg_processed, sg_to_process;
941 uint8_t sge_count, sge_idx;
942 union mfi_sgl *os_sgl;
943 pMpi25IeeeSgeChain64_t sgl_end;
944
945 /*
946 * Return 0 if there is no data transfer
947 */
948 if (!mfi_cmd->cm_sg || !mfi_cmd->cm_len) {
949 device_printf(sc->mfi_dev, "Buffer empty \n");
950 return 0;
951 }
952 os_sgl = mfi_cmd->cm_sg;
953 sge_count = mfi_cmd->cm_frame->header.sg_count;
954
955 if (sge_count > sc->mfi_max_sge) {
956 device_printf(sc->mfi_dev, "sgl ptr %p sg_cnt %d \n",
957 os_sgl, sge_count);
958 return sge_count;
959 }
960
961 if (sge_count > sc->max_SGEs_in_main_message)
962 /* One element to store the chain info */
963 sge_idx = sc->max_SGEs_in_main_message - 1;
964 else
965 sge_idx = sge_count;
966
967 if (sc->mfi_flags & (MFI_FLAGS_INVADER | MFI_FLAGS_FURY)) {
968 sgl_end = sgl_ptr + (sc->max_SGEs_in_main_message - 1);
969 sgl_end->Flags = 0;
970 }
971
972 for (i = 0; i < sge_idx; i++) {
973 /*
974 * For 32bit BSD we are getting 32 bit SGL's from OS
975 * but FW only take 64 bit SGL's so copying from 32 bit
976 * SGL's to 64.
977 */
978 if (sc->mfi_flags & MFI_FLAGS_SKINNY) {
979 sgl_ptr->Length = os_sgl->sg_skinny[i].len;
980 sgl_ptr->Address = os_sgl->sg_skinny[i].addr;
981 } else {
982 sgl_ptr->Length = os_sgl->sg32[i].len;
983 sgl_ptr->Address = os_sgl->sg32[i].addr;
984 }
985 if (i == sge_count - 1 &&
986 (sc->mfi_flags & (MFI_FLAGS_INVADER | MFI_FLAGS_FURY)))
987 sgl_ptr->Flags = MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
988 else
989 sgl_ptr->Flags = 0;
990 sgl_ptr++;
991 cmd->io_request->ChainOffset = 0;
992 }
993
994 sg_processed = i;
995
996 if (sg_processed < sge_count) {
997 pMpi25IeeeSgeChain64_t sg_chain;
998 sg_to_process = sge_count - sg_processed;
999 cmd->io_request->ChainOffset =
1000 sc->chain_offset_value_for_main_message;
1001 sg_chain = sgl_ptr;
1002 /* Prepare chain element */
1003 sg_chain->NextChainOffset = 0;
1004 if (sc->mfi_flags & (MFI_FLAGS_INVADER | MFI_FLAGS_FURY))
1005 sg_chain->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT;
1006 else
1007 sg_chain->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
1008 MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR;
1009 sg_chain->Length = (sizeof(MPI2_SGE_IO_UNION) *
1010 (sge_count - sg_processed));
1011 sg_chain->Address = cmd->sg_frame_phys_addr;
1012 sgl_ptr = (pMpi25IeeeSgeChain64_t)cmd->sg_frame;
1013 for (; i < sge_count; i++) {
1014 if (sc->mfi_flags & MFI_FLAGS_SKINNY) {
1015 sgl_ptr->Length = os_sgl->sg_skinny[i].len;
1016 sgl_ptr->Address = os_sgl->sg_skinny[i].addr;
1017 } else {
1018 sgl_ptr->Length = os_sgl->sg32[i].len;
1019 sgl_ptr->Address = os_sgl->sg32[i].addr;
1020 }
1021 if (i == sge_count - 1 &&
1022 (sc->mfi_flags &
1023 (MFI_FLAGS_INVADER | MFI_FLAGS_FURY)))
1024 sgl_ptr->Flags =
1025 MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1026 else
1027 sgl_ptr->Flags = 0;
1028 sgl_ptr++;
1029 }
1030 }
1031 return sge_count;
1032 }
1033
1034 union mfi_mpi2_request_descriptor *
mfi_build_and_issue_cmd(struct mfi_softc * sc,struct mfi_command * mfi_cmd)1035 mfi_build_and_issue_cmd(struct mfi_softc *sc, struct mfi_command *mfi_cmd)
1036 {
1037 struct mfi_cmd_tbolt *cmd;
1038 union mfi_mpi2_request_descriptor *req_desc = NULL;
1039 uint16_t index;
1040 cmd = mfi_tbolt_get_cmd(sc, mfi_cmd);
1041 if (cmd == NULL)
1042 return (NULL);
1043
1044 index = cmd->index;
1045 req_desc = mfi_tbolt_get_request_descriptor(sc, index-1);
1046 if (req_desc == NULL) {
1047 mfi_tbolt_return_cmd(sc, cmd, mfi_cmd);
1048 return (NULL);
1049 }
1050
1051 if (mfi_tbolt_build_io(sc, mfi_cmd, cmd) != 0) {
1052 mfi_tbolt_return_cmd(sc, cmd, mfi_cmd);
1053 return (NULL);
1054 }
1055 req_desc->header.SMID = index;
1056 return req_desc;
1057 }
1058
1059 union mfi_mpi2_request_descriptor *
mfi_tbolt_build_mpt_cmd(struct mfi_softc * sc,struct mfi_command * cmd)1060 mfi_tbolt_build_mpt_cmd(struct mfi_softc *sc, struct mfi_command *cmd)
1061 {
1062 union mfi_mpi2_request_descriptor *req_desc = NULL;
1063 uint16_t index;
1064 if (mfi_build_mpt_pass_thru(sc, cmd)) {
1065 device_printf(sc->mfi_dev, "Couldn't build MFI pass thru "
1066 "cmd\n");
1067 return NULL;
1068 }
1069 /* For fusion the frame_count variable is used for SMID */
1070 index = cmd->cm_extra_frames;
1071
1072 req_desc = mfi_tbolt_get_request_descriptor(sc, index - 1);
1073 if (req_desc == NULL)
1074 return NULL;
1075
1076 bzero(req_desc, sizeof(*req_desc));
1077 req_desc->header.RequestFlags = (MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO <<
1078 MFI_REQ_DESCRIPT_FLAGS_TYPE_SHIFT);
1079 req_desc->header.SMID = index;
1080 return req_desc;
1081 }
1082
1083 int
mfi_tbolt_send_frame(struct mfi_softc * sc,struct mfi_command * cm)1084 mfi_tbolt_send_frame(struct mfi_softc *sc, struct mfi_command *cm)
1085 {
1086 struct mfi_frame_header *hdr;
1087 uint8_t *cdb;
1088 union mfi_mpi2_request_descriptor *req_desc = NULL;
1089 int tm = mfi_polled_cmd_timeout * 1000;
1090
1091 hdr = &cm->cm_frame->header;
1092 cdb = cm->cm_frame->pass.cdb;
1093 if (sc->adpreset)
1094 return 1;
1095 if ((cm->cm_flags & MFI_CMD_POLLED) == 0) {
1096 cm->cm_timestamp = time_uptime;
1097 mfi_enqueue_busy(cm);
1098 } else { /* still get interrupts for it */
1099 hdr->cmd_status = MFI_STAT_INVALID_STATUS;
1100 hdr->flags |= MFI_FRAME_DONT_POST_IN_REPLY_QUEUE;
1101 }
1102
1103 if (hdr->cmd == MFI_CMD_PD_SCSI_IO) {
1104 /* check for inquiry commands coming from CLI */
1105 if ((req_desc = mfi_tbolt_build_mpt_cmd(sc, cm)) ==
1106 NULL) {
1107 device_printf(sc->mfi_dev, "Mapping from MFI "
1108 "to MPT Failed \n");
1109 return 1;
1110 }
1111 } else if (hdr->cmd == MFI_CMD_LD_SCSI_IO ||
1112 hdr->cmd == MFI_CMD_LD_READ || hdr->cmd == MFI_CMD_LD_WRITE) {
1113 cm->cm_flags |= MFI_CMD_SCSI;
1114 if ((req_desc = mfi_build_and_issue_cmd(sc, cm)) == NULL) {
1115 device_printf(sc->mfi_dev, "LDIO Failed \n");
1116 return 1;
1117 }
1118 } else if ((req_desc = mfi_tbolt_build_mpt_cmd(sc, cm)) == NULL) {
1119 device_printf(sc->mfi_dev, "Mapping from MFI to MPT Failed\n");
1120 return (1);
1121 }
1122
1123 if (cm->cm_flags & MFI_CMD_SCSI) {
1124 /*
1125 * LD IO needs to be posted since it doesn't get
1126 * acknowledged via a status update so have the
1127 * controller reply via mfi_tbolt_complete_cmd.
1128 */
1129 hdr->flags &= ~MFI_FRAME_DONT_POST_IN_REPLY_QUEUE;
1130 }
1131
1132 MFI_WRITE4(sc, MFI_ILQP, (req_desc->words & 0xFFFFFFFF));
1133 MFI_WRITE4(sc, MFI_IHQP, (req_desc->words >>0x20));
1134
1135 if ((cm->cm_flags & MFI_CMD_POLLED) == 0)
1136 return 0;
1137
1138 /*
1139 * This is a polled command, so busy-wait for it to complete.
1140 *
1141 * The value of hdr->cmd_status is updated directly by the hardware
1142 * so there is no guarantee that mfi_tbolt_complete_cmd is called
1143 * prior to this value changing.
1144 */
1145 while (hdr->cmd_status == MFI_STAT_INVALID_STATUS) {
1146 DELAY(1000);
1147 tm -= 1;
1148 if (tm <= 0)
1149 break;
1150 if (cm->cm_flags & MFI_CMD_SCSI) {
1151 /*
1152 * Force check reply queue.
1153 * This ensures that dump works correctly
1154 */
1155 mfi_tbolt_complete_cmd(sc);
1156 }
1157 }
1158
1159 /* ensure the command cleanup has been processed before returning */
1160 mfi_tbolt_complete_cmd(sc);
1161
1162 if (hdr->cmd_status == MFI_STAT_INVALID_STATUS) {
1163 device_printf(sc->mfi_dev, "Frame %p timed out "
1164 "command 0x%X\n", hdr, cm->cm_frame->dcmd.opcode);
1165 return (ETIMEDOUT);
1166 }
1167 return 0;
1168 }
1169
1170 static void
mfi_issue_pending_cmds_again(struct mfi_softc * sc)1171 mfi_issue_pending_cmds_again(struct mfi_softc *sc)
1172 {
1173 struct mfi_command *cm, *tmp;
1174 struct mfi_cmd_tbolt *cmd;
1175
1176 mtx_assert(&sc->mfi_io_lock, MA_OWNED);
1177 TAILQ_FOREACH_REVERSE_SAFE(cm, &sc->mfi_busy, BUSYQ, cm_link, tmp) {
1178 cm->retry_for_fw_reset++;
1179
1180 /*
1181 * If a command has continuously been tried multiple times
1182 * and causing a FW reset condition, no further recoveries
1183 * should be performed on the controller
1184 */
1185 if (cm->retry_for_fw_reset == 3) {
1186 device_printf(sc->mfi_dev, "megaraid_sas: command %p "
1187 "index=%d was tried multiple times during adapter "
1188 "reset - Shutting down the HBA\n", cm, cm->cm_index);
1189 mfi_kill_hba(sc);
1190 sc->hw_crit_error = 1;
1191 return;
1192 }
1193
1194 mfi_remove_busy(cm);
1195 if ((cm->cm_flags & MFI_CMD_TBOLT) != 0) {
1196 if (cm->cm_extra_frames != 0 && cm->cm_extra_frames <=
1197 sc->mfi_max_fw_cmds) {
1198 cmd = sc->mfi_cmd_pool_tbolt[cm->cm_extra_frames - 1];
1199 mfi_tbolt_return_cmd(sc, cmd, cm);
1200 } else {
1201 device_printf(sc->mfi_dev,
1202 "Invalid extra_frames: %d detected\n",
1203 cm->cm_extra_frames);
1204 }
1205 }
1206
1207 if (cm->cm_frame->dcmd.opcode != MFI_DCMD_CTRL_EVENT_WAIT) {
1208 device_printf(sc->mfi_dev,
1209 "APJ ****requeue command %p index=%d\n",
1210 cm, cm->cm_index);
1211 mfi_requeue_ready(cm);
1212 } else
1213 mfi_release_command(cm);
1214 }
1215 mfi_startio(sc);
1216 }
1217
1218 static void
mfi_kill_hba(struct mfi_softc * sc)1219 mfi_kill_hba(struct mfi_softc *sc)
1220 {
1221 if (sc->mfi_flags & MFI_FLAGS_TBOLT)
1222 MFI_WRITE4(sc, 0x00, MFI_STOP_ADP);
1223 else
1224 MFI_WRITE4(sc, MFI_IDB, MFI_STOP_ADP);
1225 }
1226
1227 static void
mfi_process_fw_state_chg_isr(void * arg)1228 mfi_process_fw_state_chg_isr(void *arg)
1229 {
1230 struct mfi_softc *sc= (struct mfi_softc *)arg;
1231 int error, status;
1232
1233 if (sc->adpreset == 1) {
1234 device_printf(sc->mfi_dev, "First stage of FW reset "
1235 "initiated...\n");
1236
1237 sc->mfi_adp_reset(sc);
1238 sc->mfi_enable_intr(sc);
1239
1240 device_printf(sc->mfi_dev, "First stage of reset complete, "
1241 "second stage initiated...\n");
1242
1243 sc->adpreset = 2;
1244
1245 /* waiting for about 20 second before start the second init */
1246 for (int wait = 0; wait < 20000; wait++)
1247 DELAY(1000);
1248 device_printf(sc->mfi_dev, "Second stage of FW reset "
1249 "initiated...\n");
1250 while ((status = MFI_READ4(sc, MFI_RSR)) & 0x04);
1251
1252 sc->mfi_disable_intr(sc);
1253
1254 /* We expect the FW state to be READY */
1255 if (mfi_transition_firmware(sc)) {
1256 device_printf(sc->mfi_dev, "controller is not in "
1257 "ready state\n");
1258 mfi_kill_hba(sc);
1259 sc->hw_crit_error = 1;
1260 return;
1261 }
1262 if ((error = mfi_tbolt_init_MFI_queue(sc)) != 0) {
1263 device_printf(sc->mfi_dev, "Failed to initialise MFI "
1264 "queue\n");
1265 mfi_kill_hba(sc);
1266 sc->hw_crit_error = 1;
1267 return;
1268 }
1269
1270 /* Init last reply index and max */
1271 MFI_WRITE4(sc, MFI_RFPI, sc->mfi_max_fw_cmds - 1);
1272 MFI_WRITE4(sc, MFI_RPI, sc->last_reply_idx);
1273
1274 sc->mfi_enable_intr(sc);
1275 sc->adpreset = 0;
1276 if (sc->mfi_aen_cm != NULL) {
1277 free(sc->mfi_aen_cm->cm_data, M_MFIBUF);
1278 mfi_remove_busy(sc->mfi_aen_cm);
1279 mfi_release_command(sc->mfi_aen_cm);
1280 sc->mfi_aen_cm = NULL;
1281 }
1282
1283 if (sc->mfi_map_sync_cm != NULL) {
1284 mfi_remove_busy(sc->mfi_map_sync_cm);
1285 mfi_release_command(sc->mfi_map_sync_cm);
1286 sc->mfi_map_sync_cm = NULL;
1287 }
1288 mfi_issue_pending_cmds_again(sc);
1289
1290 /*
1291 * Issue pending command can result in adapter being marked
1292 * dead because of too many re-tries. Check for that
1293 * condition before clearing the reset condition on the FW
1294 */
1295 if (!sc->hw_crit_error) {
1296 /*
1297 * Initiate AEN (Asynchronous Event Notification) &
1298 * Sync Map
1299 */
1300 mfi_aen_setup(sc, sc->last_seq_num);
1301 mfi_tbolt_sync_map_info(sc);
1302
1303 sc->issuepend_done = 1;
1304 device_printf(sc->mfi_dev, "second stage of reset "
1305 "complete, FW is ready now.\n");
1306 } else {
1307 device_printf(sc->mfi_dev, "second stage of reset "
1308 "never completed, hba was marked offline.\n");
1309 }
1310 } else {
1311 device_printf(sc->mfi_dev, "mfi_process_fw_state_chg_isr "
1312 "called with unhandled value:%d\n", sc->adpreset);
1313 }
1314 }
1315
1316 /*
1317 * The ThunderBolt HW has an option for the driver to directly
1318 * access the underlying disks and operate on the RAID. To
1319 * do this there needs to be a capability to keep the RAID controller
1320 * and driver in sync. The FreeBSD driver does not take advantage
1321 * of this feature since it adds a lot of complexity and slows down
1322 * performance. Performance is gained by using the controller's
1323 * cache etc.
1324 *
1325 * Even though this driver doesn't access the disks directly, an
1326 * AEN like command is used to inform the RAID firmware to "sync"
1327 * with all LD's via the MFI_DCMD_LD_MAP_GET_INFO command. This
1328 * command in write mode will return when the RAID firmware has
1329 * detected a change to the RAID state. Examples of this type
1330 * of change are removing a disk. Once the command returns then
1331 * the driver needs to acknowledge this and "sync" all LD's again.
1332 * This repeats until we shutdown. Then we need to cancel this
1333 * pending command.
1334 *
1335 * If this is not done right the RAID firmware will not remove a
1336 * pulled drive and the RAID won't go degraded etc. Effectively,
1337 * stopping any RAID mangement to functions.
1338 *
1339 * Doing another LD sync, requires the use of an event since the
1340 * driver needs to do a mfi_wait_command and can't do that in an
1341 * interrupt thread.
1342 *
1343 * The driver could get the RAID state via the MFI_DCMD_LD_MAP_GET_INFO
1344 * That requires a bunch of structure and it is simpler to just do
1345 * the MFI_DCMD_LD_GET_LIST versus walking the RAID map.
1346 */
1347
1348 void
mfi_tbolt_sync_map_info(struct mfi_softc * sc)1349 mfi_tbolt_sync_map_info(struct mfi_softc *sc)
1350 {
1351 int error = 0, i;
1352 struct mfi_command *cmd = NULL;
1353 struct mfi_dcmd_frame *dcmd = NULL;
1354 uint32_t context = 0;
1355 union mfi_ld_ref *ld_sync = NULL;
1356 size_t ld_size;
1357 struct mfi_frame_header *hdr;
1358 struct mfi_command *cm = NULL;
1359 struct mfi_ld_list *list = NULL;
1360
1361 mtx_assert(&sc->mfi_io_lock, MA_OWNED);
1362
1363 if (sc->mfi_map_sync_cm != NULL || sc->cm_map_abort)
1364 return;
1365
1366 error = mfi_dcmd_command(sc, &cm, MFI_DCMD_LD_GET_LIST,
1367 (void **)&list, sizeof(*list));
1368 if (error)
1369 goto out;
1370
1371 cm->cm_flags = MFI_CMD_POLLED | MFI_CMD_DATAIN;
1372
1373 if (mfi_wait_command(sc, cm) != 0) {
1374 device_printf(sc->mfi_dev, "Failed to get device listing\n");
1375 goto out;
1376 }
1377
1378 hdr = &cm->cm_frame->header;
1379 if (hdr->cmd_status != MFI_STAT_OK) {
1380 device_printf(sc->mfi_dev, "MFI_DCMD_LD_GET_LIST failed %x\n",
1381 hdr->cmd_status);
1382 goto out;
1383 }
1384
1385 ld_size = sizeof(*ld_sync) * list->ld_count;
1386 ld_sync = (union mfi_ld_ref *) malloc(ld_size, M_MFIBUF,
1387 M_NOWAIT | M_ZERO);
1388 if (ld_sync == NULL) {
1389 device_printf(sc->mfi_dev, "Failed to allocate sync\n");
1390 goto out;
1391 }
1392 for (i = 0; i < list->ld_count; i++)
1393 ld_sync[i].ref = list->ld_list[i].ld.ref;
1394
1395 if ((cmd = mfi_dequeue_free(sc)) == NULL) {
1396 device_printf(sc->mfi_dev, "Failed to get command\n");
1397 free(ld_sync, M_MFIBUF);
1398 goto out;
1399 }
1400
1401 context = cmd->cm_frame->header.context;
1402 bzero(cmd->cm_frame, sizeof(union mfi_frame));
1403 cmd->cm_frame->header.context = context;
1404
1405 dcmd = &cmd->cm_frame->dcmd;
1406 bzero(dcmd->mbox, MFI_MBOX_SIZE);
1407 dcmd->header.cmd = MFI_CMD_DCMD;
1408 dcmd->header.flags = MFI_FRAME_DIR_WRITE;
1409 dcmd->header.timeout = 0;
1410 dcmd->header.data_len = ld_size;
1411 dcmd->header.scsi_status = 0;
1412 dcmd->opcode = MFI_DCMD_LD_MAP_GET_INFO;
1413 cmd->cm_sg = &dcmd->sgl;
1414 cmd->cm_total_frame_size = MFI_DCMD_FRAME_SIZE;
1415 cmd->cm_data = ld_sync;
1416 cmd->cm_private = ld_sync;
1417
1418 cmd->cm_len = ld_size;
1419 cmd->cm_complete = mfi_sync_map_complete;
1420 sc->mfi_map_sync_cm = cmd;
1421
1422 cmd->cm_flags = MFI_CMD_DATAOUT;
1423 cmd->cm_frame->dcmd.mbox[0] = list->ld_count;
1424 cmd->cm_frame->dcmd.mbox[1] = MFI_DCMD_MBOX_PEND_FLAG;
1425
1426 if ((error = mfi_mapcmd(sc, cmd)) != 0) {
1427 device_printf(sc->mfi_dev, "failed to send map sync\n");
1428 free(ld_sync, M_MFIBUF);
1429 sc->mfi_map_sync_cm = NULL;
1430 mfi_release_command(cmd);
1431 goto out;
1432 }
1433
1434 out:
1435 if (list)
1436 free(list, M_MFIBUF);
1437 if (cm)
1438 mfi_release_command(cm);
1439 }
1440
1441 static void
mfi_sync_map_complete(struct mfi_command * cm)1442 mfi_sync_map_complete(struct mfi_command *cm)
1443 {
1444 struct mfi_frame_header *hdr;
1445 struct mfi_softc *sc;
1446 int aborted = 0;
1447
1448 sc = cm->cm_sc;
1449 mtx_assert(&sc->mfi_io_lock, MA_OWNED);
1450
1451 hdr = &cm->cm_frame->header;
1452
1453 if (sc->mfi_map_sync_cm == NULL)
1454 return;
1455
1456 if (sc->cm_map_abort ||
1457 hdr->cmd_status == MFI_STAT_INVALID_STATUS) {
1458 sc->cm_map_abort = 0;
1459 aborted = 1;
1460 }
1461
1462 free(cm->cm_data, M_MFIBUF);
1463 wakeup(&sc->mfi_map_sync_cm);
1464 sc->mfi_map_sync_cm = NULL;
1465 mfi_release_command(cm);
1466
1467 /* set it up again so the driver can catch more events */
1468 if (!aborted)
1469 mfi_queue_map_sync(sc);
1470 }
1471
1472 static void
mfi_queue_map_sync(struct mfi_softc * sc)1473 mfi_queue_map_sync(struct mfi_softc *sc)
1474 {
1475 mtx_assert(&sc->mfi_io_lock, MA_OWNED);
1476 taskqueue_enqueue(taskqueue_swi, &sc->mfi_map_sync_task);
1477 }
1478
1479 void
mfi_handle_map_sync(void * context,int pending)1480 mfi_handle_map_sync(void *context, int pending)
1481 {
1482 struct mfi_softc *sc;
1483
1484 sc = context;
1485 mtx_lock(&sc->mfi_io_lock);
1486 mfi_tbolt_sync_map_info(sc);
1487 mtx_unlock(&sc->mfi_io_lock);
1488 }
1489