1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/radeon_drm.h>
28 #include "radeon.h"
29 #include "radeon_asic.h"
30
31 #include "atom.h"
32 #include "atom-bits.h"
33
34 union atom_supported_devices {
35 struct _ATOM_SUPPORTED_DEVICES_INFO info;
36 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
37 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
38 };
39
radeon_lookup_i2c_gpio_quirks(struct radeon_device * rdev,ATOM_GPIO_I2C_ASSIGMENT * gpio,u8 index)40 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
41 ATOM_GPIO_I2C_ASSIGMENT *gpio,
42 u8 index)
43 {
44 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
45 if ((rdev->family == CHIP_R420) ||
46 (rdev->family == CHIP_R423) ||
47 (rdev->family == CHIP_RV410)) {
48 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
49 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
50 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
51 gpio->ucClkMaskShift = 0x19;
52 gpio->ucDataMaskShift = 0x18;
53 }
54 }
55
56 /* some evergreen boards have bad data for this entry */
57 if (ASIC_IS_DCE4(rdev)) {
58 if ((index == 7) &&
59 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
60 (gpio->sucI2cId.ucAccess == 0)) {
61 gpio->sucI2cId.ucAccess = 0x97;
62 gpio->ucDataMaskShift = 8;
63 gpio->ucDataEnShift = 8;
64 gpio->ucDataY_Shift = 8;
65 gpio->ucDataA_Shift = 8;
66 }
67 }
68
69 /* some DCE3 boards have bad data for this entry */
70 if (ASIC_IS_DCE3(rdev)) {
71 if ((index == 4) &&
72 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
73 (gpio->sucI2cId.ucAccess == 0x94))
74 gpio->sucI2cId.ucAccess = 0x14;
75 }
76 }
77
radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT * gpio)78 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
79 {
80 struct radeon_i2c_bus_rec i2c;
81
82 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
83
84 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
85 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
86 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
87 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
88 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
89 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
90 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
91 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
92 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
93 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
94 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
95 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
96 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
97 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
98 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
99 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
100
101 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
102 i2c.hw_capable = true;
103 else
104 i2c.hw_capable = false;
105
106 if (gpio->sucI2cId.ucAccess == 0xa0)
107 i2c.mm_i2c = true;
108 else
109 i2c.mm_i2c = false;
110
111 i2c.i2c_id = gpio->sucI2cId.ucAccess;
112
113 if (i2c.mask_clk_reg)
114 i2c.valid = true;
115 else
116 i2c.valid = false;
117
118 return i2c;
119 }
120
radeon_lookup_i2c_gpio(struct radeon_device * rdev,uint8_t id)121 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
122 uint8_t id)
123 {
124 struct atom_context *ctx = rdev->mode_info.atom_context;
125 ATOM_GPIO_I2C_ASSIGMENT *gpio;
126 struct radeon_i2c_bus_rec i2c;
127 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
128 struct _ATOM_GPIO_I2C_INFO *i2c_info;
129 uint16_t data_offset, size;
130 int i, num_indices;
131
132 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
133 i2c.valid = false;
134
135 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
136 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
137
138 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
139 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
140
141 gpio = &i2c_info->asGPIO_Info[0];
142 for (i = 0; i < num_indices; i++) {
143
144 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
145
146 if (gpio->sucI2cId.ucAccess == id) {
147 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
148 break;
149 }
150 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
151 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
152 }
153 }
154
155 return i2c;
156 }
157
radeon_atombios_i2c_init(struct radeon_device * rdev)158 void radeon_atombios_i2c_init(struct radeon_device *rdev)
159 {
160 struct atom_context *ctx = rdev->mode_info.atom_context;
161 ATOM_GPIO_I2C_ASSIGMENT *gpio;
162 struct radeon_i2c_bus_rec i2c;
163 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
164 struct _ATOM_GPIO_I2C_INFO *i2c_info;
165 uint16_t data_offset, size;
166 int i, num_indices;
167 char stmp[32];
168
169 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
170 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
171
172 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
173 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
174
175 gpio = &i2c_info->asGPIO_Info[0];
176 for (i = 0; i < num_indices; i++) {
177 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
178
179 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
180
181 if (i2c.valid) {
182 ksprintf(stmp, "0x%x", i2c.i2c_id);
183 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
184 }
185 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
186 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
187 }
188 }
189 }
190
radeon_atombios_lookup_gpio(struct radeon_device * rdev,u8 id)191 struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
192 u8 id)
193 {
194 struct atom_context *ctx = rdev->mode_info.atom_context;
195 struct radeon_gpio_rec gpio;
196 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
197 struct _ATOM_GPIO_PIN_LUT *gpio_info;
198 ATOM_GPIO_PIN_ASSIGNMENT *pin;
199 u16 data_offset, size;
200 int i, num_indices;
201
202 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
203 gpio.valid = false;
204
205 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
206 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
207
208 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
209 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
210
211 pin = gpio_info->asGPIO_Pin;
212 for (i = 0; i < num_indices; i++) {
213 if (id == pin->ucGPIO_ID) {
214 gpio.id = pin->ucGPIO_ID;
215 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
216 gpio.shift = pin->ucGpioPinBitShift;
217 gpio.mask = (1 << pin->ucGpioPinBitShift);
218 gpio.valid = true;
219 break;
220 }
221 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
222 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
223 }
224 }
225
226 return gpio;
227 }
228
radeon_atom_get_hpd_info_from_gpio(struct radeon_device * rdev,struct radeon_gpio_rec * gpio)229 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
230 struct radeon_gpio_rec *gpio)
231 {
232 struct radeon_hpd hpd;
233 u32 reg;
234
235 memset(&hpd, 0, sizeof(struct radeon_hpd));
236
237 if (ASIC_IS_DCE6(rdev))
238 reg = SI_DC_GPIO_HPD_A;
239 else if (ASIC_IS_DCE4(rdev))
240 reg = EVERGREEN_DC_GPIO_HPD_A;
241 else
242 reg = AVIVO_DC_GPIO_HPD_A;
243
244 hpd.gpio = *gpio;
245 if (gpio->reg == reg) {
246 switch(gpio->mask) {
247 case (1 << 0):
248 hpd.hpd = RADEON_HPD_1;
249 break;
250 case (1 << 8):
251 hpd.hpd = RADEON_HPD_2;
252 break;
253 case (1 << 16):
254 hpd.hpd = RADEON_HPD_3;
255 break;
256 case (1 << 24):
257 hpd.hpd = RADEON_HPD_4;
258 break;
259 case (1 << 26):
260 hpd.hpd = RADEON_HPD_5;
261 break;
262 case (1 << 28):
263 hpd.hpd = RADEON_HPD_6;
264 break;
265 default:
266 hpd.hpd = RADEON_HPD_NONE;
267 break;
268 }
269 } else
270 hpd.hpd = RADEON_HPD_NONE;
271 return hpd;
272 }
273
radeon_atom_apply_quirks(struct drm_device * dev,uint32_t supported_device,int * connector_type,struct radeon_i2c_bus_rec * i2c_bus,uint16_t * line_mux,struct radeon_hpd * hpd)274 static bool radeon_atom_apply_quirks(struct drm_device *dev,
275 uint32_t supported_device,
276 int *connector_type,
277 struct radeon_i2c_bus_rec *i2c_bus,
278 uint16_t *line_mux,
279 struct radeon_hpd *hpd)
280 {
281
282 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
283 if ((dev->pdev->device == 0x791e) &&
284 (dev->pdev->subsystem_vendor == 0x1043) &&
285 (dev->pdev->subsystem_device == 0x826d)) {
286 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
287 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
288 *connector_type = DRM_MODE_CONNECTOR_DVID;
289 }
290
291 /* Asrock RS600 board lists the DVI port as HDMI */
292 if ((dev->pdev->device == 0x7941) &&
293 (dev->pdev->subsystem_vendor == 0x1849) &&
294 (dev->pdev->subsystem_device == 0x7941)) {
295 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
296 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
297 *connector_type = DRM_MODE_CONNECTOR_DVID;
298 }
299
300 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
301 if ((dev->pdev->device == 0x796e) &&
302 (dev->pdev->subsystem_vendor == 0x1462) &&
303 (dev->pdev->subsystem_device == 0x7302)) {
304 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
305 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
306 return false;
307 }
308
309 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
310 if ((dev->pdev->device == 0x7941) &&
311 (dev->pdev->subsystem_vendor == 0x147b) &&
312 (dev->pdev->subsystem_device == 0x2412)) {
313 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
314 return false;
315 }
316
317 /* Falcon NW laptop lists vga ddc line for LVDS */
318 if ((dev->pdev->device == 0x5653) &&
319 (dev->pdev->subsystem_vendor == 0x1462) &&
320 (dev->pdev->subsystem_device == 0x0291)) {
321 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
322 i2c_bus->valid = false;
323 *line_mux = 53;
324 }
325 }
326
327 /* HIS X1300 is DVI+VGA, not DVI+DVI */
328 if ((dev->pdev->device == 0x7146) &&
329 (dev->pdev->subsystem_vendor == 0x17af) &&
330 (dev->pdev->subsystem_device == 0x2058)) {
331 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
332 return false;
333 }
334
335 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
336 if ((dev->pdev->device == 0x7142) &&
337 (dev->pdev->subsystem_vendor == 0x1458) &&
338 (dev->pdev->subsystem_device == 0x2134)) {
339 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
340 return false;
341 }
342
343
344 /* Funky macbooks */
345 if ((dev->pdev->device == 0x71C5) &&
346 (dev->pdev->subsystem_vendor == 0x106b) &&
347 (dev->pdev->subsystem_device == 0x0080)) {
348 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
349 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
350 return false;
351 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
352 *line_mux = 0x90;
353 }
354
355 /* mac rv630, rv730, others */
356 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
357 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
358 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
359 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
360 }
361
362 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
363 if ((dev->pdev->device == 0x9598) &&
364 (dev->pdev->subsystem_vendor == 0x1043) &&
365 (dev->pdev->subsystem_device == 0x01da)) {
366 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
367 *connector_type = DRM_MODE_CONNECTOR_DVII;
368 }
369 }
370
371 /* ASUS HD 3600 board lists the DVI port as HDMI */
372 if ((dev->pdev->device == 0x9598) &&
373 (dev->pdev->subsystem_vendor == 0x1043) &&
374 (dev->pdev->subsystem_device == 0x01e4)) {
375 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
376 *connector_type = DRM_MODE_CONNECTOR_DVII;
377 }
378 }
379
380 /* ASUS HD 3450 board lists the DVI port as HDMI */
381 if ((dev->pdev->device == 0x95C5) &&
382 (dev->pdev->subsystem_vendor == 0x1043) &&
383 (dev->pdev->subsystem_device == 0x01e2)) {
384 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
385 *connector_type = DRM_MODE_CONNECTOR_DVII;
386 }
387 }
388
389 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
390 * HDMI + VGA reporting as HDMI
391 */
392 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
393 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
394 *connector_type = DRM_MODE_CONNECTOR_VGA;
395 *line_mux = 0;
396 }
397 }
398
399 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
400 * on the laptop and a DVI port on the docking station and
401 * both share the same encoder, hpd pin, and ddc line.
402 * So while the bios table is technically correct,
403 * we drop the DVI port here since xrandr has no concept of
404 * encoders and will try and drive both connectors
405 * with different crtcs which isn't possible on the hardware
406 * side and leaves no crtcs for LVDS or VGA.
407 */
408 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
409 (dev->pdev->subsystem_vendor == 0x1025) &&
410 (dev->pdev->subsystem_device == 0x013c)) {
411 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
412 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
413 /* actually it's a DVI-D port not DVI-I */
414 *connector_type = DRM_MODE_CONNECTOR_DVID;
415 return false;
416 }
417 }
418
419 /* XFX Pine Group device rv730 reports no VGA DDC lines
420 * even though they are wired up to record 0x93
421 */
422 if ((dev->pdev->device == 0x9498) &&
423 (dev->pdev->subsystem_vendor == 0x1682) &&
424 (dev->pdev->subsystem_device == 0x2452) &&
425 (i2c_bus->valid == false) &&
426 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
427 struct radeon_device *rdev = dev->dev_private;
428 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
429 }
430
431 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
432 if (((dev->pdev->device == 0x9802) ||
433 (dev->pdev->device == 0x9805) ||
434 (dev->pdev->device == 0x9806)) &&
435 (dev->pdev->subsystem_vendor == 0x1734) &&
436 (dev->pdev->subsystem_device == 0x11bd)) {
437 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
438 *connector_type = DRM_MODE_CONNECTOR_DVII;
439 *line_mux = 0x3103;
440 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
441 *connector_type = DRM_MODE_CONNECTOR_DVII;
442 }
443 }
444
445 return true;
446 }
447
448 static const int supported_devices_connector_convert[] = {
449 DRM_MODE_CONNECTOR_Unknown,
450 DRM_MODE_CONNECTOR_VGA,
451 DRM_MODE_CONNECTOR_DVII,
452 DRM_MODE_CONNECTOR_DVID,
453 DRM_MODE_CONNECTOR_DVIA,
454 DRM_MODE_CONNECTOR_SVIDEO,
455 DRM_MODE_CONNECTOR_Composite,
456 DRM_MODE_CONNECTOR_LVDS,
457 DRM_MODE_CONNECTOR_Unknown,
458 DRM_MODE_CONNECTOR_Unknown,
459 DRM_MODE_CONNECTOR_HDMIA,
460 DRM_MODE_CONNECTOR_HDMIB,
461 DRM_MODE_CONNECTOR_Unknown,
462 DRM_MODE_CONNECTOR_Unknown,
463 DRM_MODE_CONNECTOR_9PinDIN,
464 DRM_MODE_CONNECTOR_DisplayPort
465 };
466
467 static const uint16_t supported_devices_connector_object_id_convert[] = {
468 CONNECTOR_OBJECT_ID_NONE,
469 CONNECTOR_OBJECT_ID_VGA,
470 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
471 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
472 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
473 CONNECTOR_OBJECT_ID_COMPOSITE,
474 CONNECTOR_OBJECT_ID_SVIDEO,
475 CONNECTOR_OBJECT_ID_LVDS,
476 CONNECTOR_OBJECT_ID_9PIN_DIN,
477 CONNECTOR_OBJECT_ID_9PIN_DIN,
478 CONNECTOR_OBJECT_ID_DISPLAYPORT,
479 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
480 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
481 CONNECTOR_OBJECT_ID_SVIDEO
482 };
483
484 static const int object_connector_convert[] = {
485 DRM_MODE_CONNECTOR_Unknown,
486 DRM_MODE_CONNECTOR_DVII,
487 DRM_MODE_CONNECTOR_DVII,
488 DRM_MODE_CONNECTOR_DVID,
489 DRM_MODE_CONNECTOR_DVID,
490 DRM_MODE_CONNECTOR_VGA,
491 DRM_MODE_CONNECTOR_Composite,
492 DRM_MODE_CONNECTOR_SVIDEO,
493 DRM_MODE_CONNECTOR_Unknown,
494 DRM_MODE_CONNECTOR_Unknown,
495 DRM_MODE_CONNECTOR_9PinDIN,
496 DRM_MODE_CONNECTOR_Unknown,
497 DRM_MODE_CONNECTOR_HDMIA,
498 DRM_MODE_CONNECTOR_HDMIB,
499 DRM_MODE_CONNECTOR_LVDS,
500 DRM_MODE_CONNECTOR_9PinDIN,
501 DRM_MODE_CONNECTOR_Unknown,
502 DRM_MODE_CONNECTOR_Unknown,
503 DRM_MODE_CONNECTOR_Unknown,
504 DRM_MODE_CONNECTOR_DisplayPort,
505 DRM_MODE_CONNECTOR_eDP,
506 DRM_MODE_CONNECTOR_Unknown
507 };
508
radeon_get_atom_connector_info_from_object_table(struct drm_device * dev)509 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
510 {
511 struct radeon_device *rdev = dev->dev_private;
512 struct radeon_mode_info *mode_info = &rdev->mode_info;
513 struct atom_context *ctx = mode_info->atom_context;
514 int index = GetIndexIntoMasterTable(DATA, Object_Header);
515 u16 size, data_offset;
516 u8 frev, crev;
517 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
518 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
519 ATOM_OBJECT_TABLE *router_obj;
520 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
521 ATOM_OBJECT_HEADER *obj_header;
522 int i, j, k, path_size, device_support;
523 int connector_type;
524 u16 igp_lane_info, conn_id, connector_object_id;
525 struct radeon_i2c_bus_rec ddc_bus;
526 struct radeon_router router;
527 struct radeon_gpio_rec gpio;
528 struct radeon_hpd hpd;
529
530 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
531 return false;
532
533 if (crev < 2)
534 return false;
535
536 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
537 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
538 (ctx->bios + data_offset +
539 le16_to_cpu(obj_header->usDisplayPathTableOffset));
540 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
541 (ctx->bios + data_offset +
542 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
543 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
544 (ctx->bios + data_offset +
545 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
546 router_obj = (ATOM_OBJECT_TABLE *)
547 (ctx->bios + data_offset +
548 le16_to_cpu(obj_header->usRouterObjectTableOffset));
549 device_support = le16_to_cpu(obj_header->usDeviceSupport);
550
551 path_size = 0;
552 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
553 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
554 ATOM_DISPLAY_OBJECT_PATH *path;
555 addr += path_size;
556 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
557 path_size += le16_to_cpu(path->usSize);
558
559 if (device_support & le16_to_cpu(path->usDeviceTag)) {
560 uint8_t con_obj_id, con_obj_num, con_obj_type;
561
562 con_obj_id =
563 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
564 >> OBJECT_ID_SHIFT;
565 con_obj_num =
566 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
567 >> ENUM_ID_SHIFT;
568 con_obj_type =
569 (le16_to_cpu(path->usConnObjectId) &
570 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
571
572 /* TODO CV support */
573 if (le16_to_cpu(path->usDeviceTag) ==
574 ATOM_DEVICE_CV_SUPPORT)
575 continue;
576
577 /* IGP chips */
578 if ((rdev->flags & RADEON_IS_IGP) &&
579 (con_obj_id ==
580 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
581 uint16_t igp_offset = 0;
582 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
583
584 index =
585 GetIndexIntoMasterTable(DATA,
586 IntegratedSystemInfo);
587
588 if (atom_parse_data_header(ctx, index, &size, &frev,
589 &crev, &igp_offset)) {
590
591 if (crev >= 2) {
592 igp_obj =
593 (ATOM_INTEGRATED_SYSTEM_INFO_V2
594 *) (ctx->bios + igp_offset);
595
596 if (igp_obj) {
597 uint32_t slot_config, ct;
598
599 if (con_obj_num == 1)
600 slot_config =
601 igp_obj->
602 ulDDISlot1Config;
603 else
604 slot_config =
605 igp_obj->
606 ulDDISlot2Config;
607
608 ct = (slot_config >> 16) & 0xff;
609 connector_type =
610 object_connector_convert
611 [ct];
612 connector_object_id = ct;
613 igp_lane_info =
614 slot_config & 0xffff;
615 } else
616 continue;
617 } else
618 continue;
619 } else {
620 igp_lane_info = 0;
621 connector_type =
622 object_connector_convert[con_obj_id];
623 connector_object_id = con_obj_id;
624 }
625 } else {
626 igp_lane_info = 0;
627 connector_type =
628 object_connector_convert[con_obj_id];
629 connector_object_id = con_obj_id;
630 }
631
632 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
633 continue;
634
635 router.ddc_valid = false;
636 router.cd_valid = false;
637 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
638 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
639
640 grph_obj_id =
641 (le16_to_cpu(path->usGraphicObjIds[j]) &
642 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
643 grph_obj_num =
644 (le16_to_cpu(path->usGraphicObjIds[j]) &
645 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
646 grph_obj_type =
647 (le16_to_cpu(path->usGraphicObjIds[j]) &
648 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
649
650 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
651 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
652 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
653 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
654 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
655 (ctx->bios + data_offset +
656 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
657 ATOM_ENCODER_CAP_RECORD *cap_record;
658 u16 caps = 0;
659
660 while (record->ucRecordSize > 0 &&
661 record->ucRecordType > 0 &&
662 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
663 switch (record->ucRecordType) {
664 case ATOM_ENCODER_CAP_RECORD_TYPE:
665 cap_record =(ATOM_ENCODER_CAP_RECORD *)
666 record;
667 caps = le16_to_cpu(cap_record->usEncoderCap);
668 break;
669 }
670 record = (ATOM_COMMON_RECORD_HEADER *)
671 ((char *)record + record->ucRecordSize);
672 }
673 radeon_add_atom_encoder(dev,
674 encoder_obj,
675 le16_to_cpu
676 (path->
677 usDeviceTag),
678 caps);
679 }
680 }
681 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
682 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
683 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
684 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
685 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
686 (ctx->bios + data_offset +
687 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
688 ATOM_I2C_RECORD *i2c_record;
689 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
690 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
691 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
692 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
693 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
694 (ctx->bios + data_offset +
695 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
696 u8 *num_dst_objs = (u8 *)
697 ((u8 *)router_src_dst_table + 1 +
698 (router_src_dst_table->ucNumberOfSrc * 2));
699 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
700 int enum_id;
701
702 router.router_id = router_obj_id;
703 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
704 if (le16_to_cpu(path->usConnObjectId) ==
705 le16_to_cpu(dst_objs[enum_id]))
706 break;
707 }
708
709 while (record->ucRecordSize > 0 &&
710 record->ucRecordType > 0 &&
711 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
712 switch (record->ucRecordType) {
713 case ATOM_I2C_RECORD_TYPE:
714 i2c_record =
715 (ATOM_I2C_RECORD *)
716 record;
717 i2c_config =
718 (ATOM_I2C_ID_CONFIG_ACCESS *)
719 &i2c_record->sucI2cId;
720 router.i2c_info =
721 radeon_lookup_i2c_gpio(rdev,
722 i2c_config->
723 ucAccess);
724 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
725 break;
726 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
727 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
728 record;
729 router.ddc_valid = true;
730 router.ddc_mux_type = ddc_path->ucMuxType;
731 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
732 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
733 break;
734 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
735 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
736 record;
737 router.cd_valid = true;
738 router.cd_mux_type = cd_path->ucMuxType;
739 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
740 router.cd_mux_state = cd_path->ucMuxState[enum_id];
741 break;
742 }
743 record = (ATOM_COMMON_RECORD_HEADER *)
744 ((char *)record + record->ucRecordSize);
745 }
746 }
747 }
748 }
749 }
750
751 /* look up gpio for ddc, hpd */
752 ddc_bus.valid = false;
753 hpd.hpd = RADEON_HPD_NONE;
754 if ((le16_to_cpu(path->usDeviceTag) &
755 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
756 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
757 if (le16_to_cpu(path->usConnObjectId) ==
758 le16_to_cpu(con_obj->asObjects[j].
759 usObjectID)) {
760 ATOM_COMMON_RECORD_HEADER
761 *record =
762 (ATOM_COMMON_RECORD_HEADER
763 *)
764 (ctx->bios + data_offset +
765 le16_to_cpu(con_obj->
766 asObjects[j].
767 usRecordOffset));
768 ATOM_I2C_RECORD *i2c_record;
769 ATOM_HPD_INT_RECORD *hpd_record;
770 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
771
772 while (record->ucRecordSize > 0 &&
773 record->ucRecordType > 0 &&
774 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
775 switch (record->ucRecordType) {
776 case ATOM_I2C_RECORD_TYPE:
777 i2c_record =
778 (ATOM_I2C_RECORD *)
779 record;
780 i2c_config =
781 (ATOM_I2C_ID_CONFIG_ACCESS *)
782 &i2c_record->sucI2cId;
783 ddc_bus = radeon_lookup_i2c_gpio(rdev,
784 i2c_config->
785 ucAccess);
786 break;
787 case ATOM_HPD_INT_RECORD_TYPE:
788 hpd_record =
789 (ATOM_HPD_INT_RECORD *)
790 record;
791 gpio = radeon_atombios_lookup_gpio(rdev,
792 hpd_record->ucHPDIntGPIOID);
793 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
794 hpd.plugged_state = hpd_record->ucPlugged_PinState;
795 break;
796 }
797 record =
798 (ATOM_COMMON_RECORD_HEADER
799 *) ((char *)record
800 +
801 record->
802 ucRecordSize);
803 }
804 break;
805 }
806 }
807 }
808
809 /* needed for aux chan transactions */
810 ddc_bus.hpd = hpd.hpd;
811
812 conn_id = le16_to_cpu(path->usConnObjectId);
813
814 if (!radeon_atom_apply_quirks
815 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
816 &ddc_bus, &conn_id, &hpd))
817 continue;
818
819 radeon_add_atom_connector(dev,
820 conn_id,
821 le16_to_cpu(path->
822 usDeviceTag),
823 connector_type, &ddc_bus,
824 igp_lane_info,
825 connector_object_id,
826 &hpd,
827 &router);
828
829 }
830 }
831
832 radeon_link_encoder_connector(dev);
833
834 radeon_setup_mst_connector(dev);
835 return true;
836 }
837
atombios_get_connector_object_id(struct drm_device * dev,int connector_type,uint16_t devices)838 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
839 int connector_type,
840 uint16_t devices)
841 {
842 struct radeon_device *rdev = dev->dev_private;
843
844 if (rdev->flags & RADEON_IS_IGP) {
845 return supported_devices_connector_object_id_convert
846 [connector_type];
847 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
848 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
849 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
850 struct radeon_mode_info *mode_info = &rdev->mode_info;
851 struct atom_context *ctx = mode_info->atom_context;
852 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
853 uint16_t size, data_offset;
854 uint8_t frev, crev;
855 ATOM_XTMDS_INFO *xtmds;
856
857 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
858 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
859
860 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
861 if (connector_type == DRM_MODE_CONNECTOR_DVII)
862 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
863 else
864 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
865 } else {
866 if (connector_type == DRM_MODE_CONNECTOR_DVII)
867 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
868 else
869 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
870 }
871 } else
872 return supported_devices_connector_object_id_convert
873 [connector_type];
874 } else {
875 return supported_devices_connector_object_id_convert
876 [connector_type];
877 }
878 }
879
880 struct bios_connector {
881 bool valid;
882 uint16_t line_mux;
883 uint16_t devices;
884 int connector_type;
885 struct radeon_i2c_bus_rec ddc_bus;
886 struct radeon_hpd hpd;
887 };
888
radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device * dev)889 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
890 drm_device
891 *dev)
892 {
893 struct radeon_device *rdev = dev->dev_private;
894 struct radeon_mode_info *mode_info = &rdev->mode_info;
895 struct atom_context *ctx = mode_info->atom_context;
896 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
897 uint16_t size, data_offset;
898 uint8_t frev, crev;
899 uint16_t device_support;
900 uint8_t dac;
901 union atom_supported_devices *supported_devices;
902 int i, j, max_device;
903 struct bios_connector *bios_connectors;
904 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
905 struct radeon_router router;
906
907 router.ddc_valid = false;
908 router.cd_valid = false;
909
910 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
911 if (!bios_connectors)
912 return false;
913
914 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
915 &data_offset)) {
916 kfree(bios_connectors);
917 return false;
918 }
919
920 supported_devices =
921 (union atom_supported_devices *)(ctx->bios + data_offset);
922
923 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
924
925 if (frev > 1)
926 max_device = ATOM_MAX_SUPPORTED_DEVICE;
927 else
928 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
929
930 for (i = 0; i < max_device; i++) {
931 ATOM_CONNECTOR_INFO_I2C ci =
932 supported_devices->info.asConnInfo[i];
933
934 bios_connectors[i].valid = false;
935
936 if (!(device_support & (1 << i))) {
937 continue;
938 }
939
940 if (i == ATOM_DEVICE_CV_INDEX) {
941 DRM_DEBUG_KMS("Skipping Component Video\n");
942 continue;
943 }
944
945 bios_connectors[i].connector_type =
946 supported_devices_connector_convert[ci.sucConnectorInfo.
947 sbfAccess.
948 bfConnectorType];
949
950 if (bios_connectors[i].connector_type ==
951 DRM_MODE_CONNECTOR_Unknown)
952 continue;
953
954 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
955
956 bios_connectors[i].line_mux =
957 ci.sucI2cId.ucAccess;
958
959 /* give tv unique connector ids */
960 if (i == ATOM_DEVICE_TV1_INDEX) {
961 bios_connectors[i].ddc_bus.valid = false;
962 bios_connectors[i].line_mux = 50;
963 } else if (i == ATOM_DEVICE_TV2_INDEX) {
964 bios_connectors[i].ddc_bus.valid = false;
965 bios_connectors[i].line_mux = 51;
966 } else if (i == ATOM_DEVICE_CV_INDEX) {
967 bios_connectors[i].ddc_bus.valid = false;
968 bios_connectors[i].line_mux = 52;
969 } else
970 bios_connectors[i].ddc_bus =
971 radeon_lookup_i2c_gpio(rdev,
972 bios_connectors[i].line_mux);
973
974 if ((crev > 1) && (frev > 1)) {
975 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
976 switch (isb) {
977 case 0x4:
978 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
979 break;
980 case 0xa:
981 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
982 break;
983 default:
984 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
985 break;
986 }
987 } else {
988 if (i == ATOM_DEVICE_DFP1_INDEX)
989 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
990 else if (i == ATOM_DEVICE_DFP2_INDEX)
991 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
992 else
993 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
994 }
995
996 /* Always set the connector type to VGA for CRT1/CRT2. if they are
997 * shared with a DVI port, we'll pick up the DVI connector when we
998 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
999 */
1000 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1001 bios_connectors[i].connector_type =
1002 DRM_MODE_CONNECTOR_VGA;
1003
1004 if (!radeon_atom_apply_quirks
1005 (dev, (1 << i), &bios_connectors[i].connector_type,
1006 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1007 &bios_connectors[i].hpd))
1008 continue;
1009
1010 bios_connectors[i].valid = true;
1011 bios_connectors[i].devices = (1 << i);
1012
1013 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1014 radeon_add_atom_encoder(dev,
1015 radeon_get_encoder_enum(dev,
1016 (1 << i),
1017 dac),
1018 (1 << i),
1019 0);
1020 else
1021 radeon_add_legacy_encoder(dev,
1022 radeon_get_encoder_enum(dev,
1023 (1 << i),
1024 dac),
1025 (1 << i));
1026 }
1027
1028 /* combine shared connectors */
1029 for (i = 0; i < max_device; i++) {
1030 if (bios_connectors[i].valid) {
1031 for (j = 0; j < max_device; j++) {
1032 if (bios_connectors[j].valid && (i != j)) {
1033 if (bios_connectors[i].line_mux ==
1034 bios_connectors[j].line_mux) {
1035 /* make sure not to combine LVDS */
1036 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1037 bios_connectors[i].line_mux = 53;
1038 bios_connectors[i].ddc_bus.valid = false;
1039 continue;
1040 }
1041 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1042 bios_connectors[j].line_mux = 53;
1043 bios_connectors[j].ddc_bus.valid = false;
1044 continue;
1045 }
1046 /* combine analog and digital for DVI-I */
1047 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1048 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1049 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1050 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1051 bios_connectors[i].devices |=
1052 bios_connectors[j].devices;
1053 bios_connectors[i].connector_type =
1054 DRM_MODE_CONNECTOR_DVII;
1055 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1056 bios_connectors[i].hpd =
1057 bios_connectors[j].hpd;
1058 bios_connectors[j].valid = false;
1059 }
1060 }
1061 }
1062 }
1063 }
1064 }
1065
1066 /* add the connectors */
1067 for (i = 0; i < max_device; i++) {
1068 if (bios_connectors[i].valid) {
1069 uint16_t connector_object_id =
1070 atombios_get_connector_object_id(dev,
1071 bios_connectors[i].connector_type,
1072 bios_connectors[i].devices);
1073 radeon_add_atom_connector(dev,
1074 bios_connectors[i].line_mux,
1075 bios_connectors[i].devices,
1076 bios_connectors[i].
1077 connector_type,
1078 &bios_connectors[i].ddc_bus,
1079 0,
1080 connector_object_id,
1081 &bios_connectors[i].hpd,
1082 &router);
1083 }
1084 }
1085
1086 radeon_link_encoder_connector(dev);
1087
1088 kfree(bios_connectors);
1089 return true;
1090 }
1091
1092 union firmware_info {
1093 ATOM_FIRMWARE_INFO info;
1094 ATOM_FIRMWARE_INFO_V1_2 info_12;
1095 ATOM_FIRMWARE_INFO_V1_3 info_13;
1096 ATOM_FIRMWARE_INFO_V1_4 info_14;
1097 ATOM_FIRMWARE_INFO_V2_1 info_21;
1098 ATOM_FIRMWARE_INFO_V2_2 info_22;
1099 };
1100
1101 union igp_info {
1102 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1103 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1104 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1105 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1106 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1107 };
1108
radeon_atombios_get_dentist_vco_freq(struct radeon_device * rdev)1109 static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev)
1110 {
1111 struct radeon_mode_info *mode_info = &rdev->mode_info;
1112 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1113 union igp_info *igp_info;
1114 u8 frev, crev;
1115 u16 data_offset;
1116
1117 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1118 &frev, &crev, &data_offset)) {
1119 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1120 data_offset);
1121 rdev->clock.vco_freq =
1122 le32_to_cpu(igp_info->info_6.ulDentistVCOFreq);
1123 }
1124 }
1125
radeon_atom_get_clock_info(struct drm_device * dev)1126 bool radeon_atom_get_clock_info(struct drm_device *dev)
1127 {
1128 struct radeon_device *rdev = dev->dev_private;
1129 struct radeon_mode_info *mode_info = &rdev->mode_info;
1130 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1131 union firmware_info *firmware_info;
1132 uint8_t frev, crev;
1133 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1134 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1135 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1136 struct radeon_pll *spll = &rdev->clock.spll;
1137 struct radeon_pll *mpll = &rdev->clock.mpll;
1138 uint16_t data_offset;
1139
1140 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1141 &frev, &crev, &data_offset)) {
1142 firmware_info =
1143 (union firmware_info *)(mode_info->atom_context->bios +
1144 data_offset);
1145 /* pixel clocks */
1146 p1pll->reference_freq =
1147 le16_to_cpu(firmware_info->info.usReferenceClock);
1148 p1pll->reference_div = 0;
1149
1150 if ((frev < 2) && (crev < 2))
1151 p1pll->pll_out_min =
1152 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1153 else
1154 p1pll->pll_out_min =
1155 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1156 p1pll->pll_out_max =
1157 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1158
1159 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) {
1160 p1pll->lcd_pll_out_min =
1161 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1162 if (p1pll->lcd_pll_out_min == 0)
1163 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1164 p1pll->lcd_pll_out_max =
1165 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1166 if (p1pll->lcd_pll_out_max == 0)
1167 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1168 } else {
1169 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1170 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1171 }
1172
1173 if (p1pll->pll_out_min == 0) {
1174 if (ASIC_IS_AVIVO(rdev))
1175 p1pll->pll_out_min = 64800;
1176 else
1177 p1pll->pll_out_min = 20000;
1178 }
1179
1180 p1pll->pll_in_min =
1181 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1182 p1pll->pll_in_max =
1183 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1184
1185 *p2pll = *p1pll;
1186
1187 /* system clock */
1188 if (ASIC_IS_DCE4(rdev))
1189 spll->reference_freq =
1190 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1191 else
1192 spll->reference_freq =
1193 le16_to_cpu(firmware_info->info.usReferenceClock);
1194 spll->reference_div = 0;
1195
1196 spll->pll_out_min =
1197 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1198 spll->pll_out_max =
1199 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1200
1201 /* ??? */
1202 if (spll->pll_out_min == 0) {
1203 if (ASIC_IS_AVIVO(rdev))
1204 spll->pll_out_min = 64800;
1205 else
1206 spll->pll_out_min = 20000;
1207 }
1208
1209 spll->pll_in_min =
1210 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1211 spll->pll_in_max =
1212 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1213
1214 /* memory clock */
1215 if (ASIC_IS_DCE4(rdev))
1216 mpll->reference_freq =
1217 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1218 else
1219 mpll->reference_freq =
1220 le16_to_cpu(firmware_info->info.usReferenceClock);
1221 mpll->reference_div = 0;
1222
1223 mpll->pll_out_min =
1224 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1225 mpll->pll_out_max =
1226 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1227
1228 /* ??? */
1229 if (mpll->pll_out_min == 0) {
1230 if (ASIC_IS_AVIVO(rdev))
1231 mpll->pll_out_min = 64800;
1232 else
1233 mpll->pll_out_min = 20000;
1234 }
1235
1236 mpll->pll_in_min =
1237 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1238 mpll->pll_in_max =
1239 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1240
1241 rdev->clock.default_sclk =
1242 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1243 rdev->clock.default_mclk =
1244 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1245
1246 if (ASIC_IS_DCE4(rdev)) {
1247 rdev->clock.default_dispclk =
1248 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1249 if (rdev->clock.default_dispclk == 0) {
1250 if (ASIC_IS_DCE6(rdev))
1251 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1252 else if (ASIC_IS_DCE5(rdev))
1253 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1254 else
1255 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1256 }
1257 /* set a reasonable default for DP */
1258 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1259 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1260 rdev->clock.default_dispclk / 100);
1261 rdev->clock.default_dispclk = 60000;
1262 }
1263 rdev->clock.dp_extclk =
1264 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1265 rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1266 }
1267 *dcpll = *p1pll;
1268
1269 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1270 if (rdev->clock.max_pixel_clock == 0)
1271 rdev->clock.max_pixel_clock = 40000;
1272
1273 /* not technically a clock, but... */
1274 rdev->mode_info.firmware_flags =
1275 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1276
1277 if (ASIC_IS_DCE8(rdev))
1278 rdev->clock.vco_freq =
1279 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq);
1280 else if (ASIC_IS_DCE5(rdev))
1281 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1282 else if (ASIC_IS_DCE41(rdev))
1283 radeon_atombios_get_dentist_vco_freq(rdev);
1284 else
1285 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1286
1287 if (rdev->clock.vco_freq == 0)
1288 rdev->clock.vco_freq = 360000; /* 3.6 GHz */
1289
1290 return true;
1291 }
1292
1293 return false;
1294 }
1295
radeon_atombios_sideport_present(struct radeon_device * rdev)1296 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1297 {
1298 struct radeon_mode_info *mode_info = &rdev->mode_info;
1299 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1300 union igp_info *igp_info;
1301 u8 frev, crev;
1302 u16 data_offset;
1303
1304 /* sideport is AMD only */
1305 if (rdev->family == CHIP_RS600)
1306 return false;
1307
1308 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1309 &frev, &crev, &data_offset)) {
1310 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1311 data_offset);
1312 switch (crev) {
1313 case 1:
1314 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1315 return true;
1316 break;
1317 case 2:
1318 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1319 return true;
1320 break;
1321 default:
1322 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1323 break;
1324 }
1325 }
1326 return false;
1327 }
1328
radeon_atombios_get_tmds_info(struct radeon_encoder * encoder,struct radeon_encoder_int_tmds * tmds)1329 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1330 struct radeon_encoder_int_tmds *tmds)
1331 {
1332 struct drm_device *dev = encoder->base.dev;
1333 struct radeon_device *rdev = dev->dev_private;
1334 struct radeon_mode_info *mode_info = &rdev->mode_info;
1335 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1336 uint16_t data_offset;
1337 struct _ATOM_TMDS_INFO *tmds_info;
1338 uint8_t frev, crev;
1339 uint16_t maxfreq;
1340 int i;
1341
1342 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1343 &frev, &crev, &data_offset)) {
1344 tmds_info =
1345 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1346 data_offset);
1347
1348 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1349 for (i = 0; i < 4; i++) {
1350 tmds->tmds_pll[i].freq =
1351 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1352 tmds->tmds_pll[i].value =
1353 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1354 tmds->tmds_pll[i].value |=
1355 (tmds_info->asMiscInfo[i].
1356 ucPLL_VCO_Gain & 0x3f) << 6;
1357 tmds->tmds_pll[i].value |=
1358 (tmds_info->asMiscInfo[i].
1359 ucPLL_DutyCycle & 0xf) << 12;
1360 tmds->tmds_pll[i].value |=
1361 (tmds_info->asMiscInfo[i].
1362 ucPLL_VoltageSwing & 0xf) << 16;
1363
1364 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1365 tmds->tmds_pll[i].freq,
1366 tmds->tmds_pll[i].value);
1367
1368 if (maxfreq == tmds->tmds_pll[i].freq) {
1369 tmds->tmds_pll[i].freq = 0xffffffff;
1370 break;
1371 }
1372 }
1373 return true;
1374 }
1375 return false;
1376 }
1377
radeon_atombios_get_ppll_ss_info(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id)1378 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1379 struct radeon_atom_ss *ss,
1380 int id)
1381 {
1382 struct radeon_mode_info *mode_info = &rdev->mode_info;
1383 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1384 uint16_t data_offset, size;
1385 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1386 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1387 uint8_t frev, crev;
1388 int i, num_indices;
1389
1390 memset(ss, 0, sizeof(struct radeon_atom_ss));
1391 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1392 &frev, &crev, &data_offset)) {
1393 ss_info =
1394 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1395
1396 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1397 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1398 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1399 ((u8 *)&ss_info->asSS_Info[0]);
1400 for (i = 0; i < num_indices; i++) {
1401 if (ss_assign->ucSS_Id == id) {
1402 ss->percentage =
1403 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
1404 ss->type = ss_assign->ucSpreadSpectrumType;
1405 ss->step = ss_assign->ucSS_Step;
1406 ss->delay = ss_assign->ucSS_Delay;
1407 ss->range = ss_assign->ucSS_Range;
1408 ss->refdiv = ss_assign->ucRecommendedRef_Div;
1409 return true;
1410 }
1411 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1412 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1413 }
1414 }
1415 return false;
1416 }
1417
radeon_atombios_get_igp_ss_overrides(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id)1418 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1419 struct radeon_atom_ss *ss,
1420 int id)
1421 {
1422 struct radeon_mode_info *mode_info = &rdev->mode_info;
1423 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1424 u16 data_offset, size;
1425 union igp_info *igp_info;
1426 u8 frev, crev;
1427 u16 percentage = 0, rate = 0;
1428
1429 /* get any igp specific overrides */
1430 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1431 &frev, &crev, &data_offset)) {
1432 igp_info = (union igp_info *)
1433 (mode_info->atom_context->bios + data_offset);
1434 switch (crev) {
1435 case 6:
1436 switch (id) {
1437 case ASIC_INTERNAL_SS_ON_TMDS:
1438 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1439 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1440 break;
1441 case ASIC_INTERNAL_SS_ON_HDMI:
1442 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1443 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1444 break;
1445 case ASIC_INTERNAL_SS_ON_LVDS:
1446 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1447 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1448 break;
1449 }
1450 break;
1451 case 7:
1452 switch (id) {
1453 case ASIC_INTERNAL_SS_ON_TMDS:
1454 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1455 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1456 break;
1457 case ASIC_INTERNAL_SS_ON_HDMI:
1458 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1459 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1460 break;
1461 case ASIC_INTERNAL_SS_ON_LVDS:
1462 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1463 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1464 break;
1465 }
1466 break;
1467 case 8:
1468 switch (id) {
1469 case ASIC_INTERNAL_SS_ON_TMDS:
1470 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1471 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1472 break;
1473 case ASIC_INTERNAL_SS_ON_HDMI:
1474 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1475 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1476 break;
1477 case ASIC_INTERNAL_SS_ON_LVDS:
1478 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1479 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1480 break;
1481 }
1482 break;
1483 default:
1484 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1485 break;
1486 }
1487 if (percentage)
1488 ss->percentage = percentage;
1489 if (rate)
1490 ss->rate = rate;
1491 }
1492 }
1493
1494 union asic_ss_info {
1495 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1496 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1497 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1498 };
1499
1500 union asic_ss_assignment {
1501 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
1502 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
1503 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
1504 };
1505
radeon_atombios_get_asic_ss_info(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id,u32 clock)1506 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1507 struct radeon_atom_ss *ss,
1508 int id, u32 clock)
1509 {
1510 struct radeon_mode_info *mode_info = &rdev->mode_info;
1511 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1512 uint16_t data_offset, size;
1513 union asic_ss_info *ss_info;
1514 union asic_ss_assignment *ss_assign;
1515 uint8_t frev, crev;
1516 int i, num_indices;
1517
1518 if (id == ASIC_INTERNAL_MEMORY_SS) {
1519 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1520 return false;
1521 }
1522 if (id == ASIC_INTERNAL_ENGINE_SS) {
1523 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1524 return false;
1525 }
1526
1527 memset(ss, 0, sizeof(struct radeon_atom_ss));
1528 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1529 &frev, &crev, &data_offset)) {
1530
1531 ss_info =
1532 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1533
1534 switch (frev) {
1535 case 1:
1536 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1537 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1538
1539 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
1540 for (i = 0; i < num_indices; i++) {
1541 if ((ss_assign->v1.ucClockIndication == id) &&
1542 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1543 ss->percentage =
1544 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1545 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1546 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1547 ss->percentage_divider = 100;
1548 return true;
1549 }
1550 ss_assign = (union asic_ss_assignment *)
1551 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1552 }
1553 break;
1554 case 2:
1555 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1556 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1557 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
1558 for (i = 0; i < num_indices; i++) {
1559 if ((ss_assign->v2.ucClockIndication == id) &&
1560 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1561 ss->percentage =
1562 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1563 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1564 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1565 ss->percentage_divider = 100;
1566 if ((crev == 2) &&
1567 ((id == ASIC_INTERNAL_ENGINE_SS) ||
1568 (id == ASIC_INTERNAL_MEMORY_SS)))
1569 ss->rate /= 100;
1570 return true;
1571 }
1572 ss_assign = (union asic_ss_assignment *)
1573 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1574 }
1575 break;
1576 case 3:
1577 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1578 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1579 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
1580 for (i = 0; i < num_indices; i++) {
1581 if ((ss_assign->v3.ucClockIndication == id) &&
1582 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1583 ss->percentage =
1584 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1585 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1586 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1587 if (ss_assign->v3.ucSpreadSpectrumMode &
1588 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
1589 ss->percentage_divider = 1000;
1590 else
1591 ss->percentage_divider = 100;
1592 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1593 (id == ASIC_INTERNAL_MEMORY_SS))
1594 ss->rate /= 100;
1595 if (rdev->flags & RADEON_IS_IGP)
1596 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1597 return true;
1598 }
1599 ss_assign = (union asic_ss_assignment *)
1600 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1601 }
1602 break;
1603 default:
1604 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1605 break;
1606 }
1607
1608 }
1609 return false;
1610 }
1611
1612 union lvds_info {
1613 struct _ATOM_LVDS_INFO info;
1614 struct _ATOM_LVDS_INFO_V12 info_12;
1615 };
1616
radeon_atombios_get_lvds_info(struct radeon_encoder * encoder)1617 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1618 radeon_encoder
1619 *encoder)
1620 {
1621 struct drm_device *dev = encoder->base.dev;
1622 struct radeon_device *rdev = dev->dev_private;
1623 struct radeon_mode_info *mode_info = &rdev->mode_info;
1624 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1625 uint16_t data_offset, misc;
1626 union lvds_info *lvds_info;
1627 uint8_t frev, crev;
1628 struct radeon_encoder_atom_dig *lvds = NULL;
1629 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1630
1631 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1632 &frev, &crev, &data_offset)) {
1633 lvds_info =
1634 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1635 lvds =
1636 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1637
1638 if (!lvds)
1639 return NULL;
1640
1641 lvds->native_mode.clock =
1642 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1643 lvds->native_mode.hdisplay =
1644 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1645 lvds->native_mode.vdisplay =
1646 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1647 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1648 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1649 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1650 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1651 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1652 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1653 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1654 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1655 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1656 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1657 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1658 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1659 lvds->panel_pwr_delay =
1660 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1661 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1662
1663 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1664 if (misc & ATOM_VSYNC_POLARITY)
1665 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1666 if (misc & ATOM_HSYNC_POLARITY)
1667 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1668 if (misc & ATOM_COMPOSITESYNC)
1669 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1670 if (misc & ATOM_INTERLACE)
1671 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1672 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1673 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1674
1675 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1676 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1677
1678 /* set crtc values */
1679 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1680
1681 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1682
1683 encoder->native_mode = lvds->native_mode;
1684
1685 if (encoder_enum == 2)
1686 lvds->linkb = true;
1687 else
1688 lvds->linkb = false;
1689
1690 /* parse the lcd record table */
1691 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1692 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1693 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1694 bool bad_record = false;
1695 u8 *record;
1696
1697 if ((frev == 1) && (crev < 2))
1698 /* absolute */
1699 record = (u8 *)(mode_info->atom_context->bios +
1700 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1701 else
1702 /* relative */
1703 record = (u8 *)(mode_info->atom_context->bios +
1704 data_offset +
1705 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1706 while (*record != ATOM_RECORD_END_TYPE) {
1707 switch (*record) {
1708 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1709 record += sizeof(ATOM_PATCH_RECORD_MODE);
1710 break;
1711 case LCD_RTS_RECORD_TYPE:
1712 record += sizeof(ATOM_LCD_RTS_RECORD);
1713 break;
1714 case LCD_CAP_RECORD_TYPE:
1715 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1716 break;
1717 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1718 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1719 if (fake_edid_record->ucFakeEDIDLength) {
1720 struct edid *edid;
1721 int edid_size =
1722 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1723 edid = kmalloc(edid_size, M_DRM, M_WAITOK);
1724 if (edid) {
1725 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1726 fake_edid_record->ucFakeEDIDLength);
1727
1728 if (drm_edid_is_valid(edid)) {
1729 rdev->mode_info.bios_hardcoded_edid = edid;
1730 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1731 } else
1732 kfree(edid);
1733 }
1734 }
1735 record += fake_edid_record->ucFakeEDIDLength ?
1736 fake_edid_record->ucFakeEDIDLength + 2 :
1737 sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1738 break;
1739 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1740 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1741 lvds->native_mode.width_mm = panel_res_record->usHSize;
1742 lvds->native_mode.height_mm = panel_res_record->usVSize;
1743 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1744 break;
1745 default:
1746 DRM_ERROR("Bad LCD record %d\n", *record);
1747 bad_record = true;
1748 break;
1749 }
1750 if (bad_record)
1751 break;
1752 }
1753 }
1754 }
1755 return lvds;
1756 }
1757
1758 struct radeon_encoder_primary_dac *
radeon_atombios_get_primary_dac_info(struct radeon_encoder * encoder)1759 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1760 {
1761 struct drm_device *dev = encoder->base.dev;
1762 struct radeon_device *rdev = dev->dev_private;
1763 struct radeon_mode_info *mode_info = &rdev->mode_info;
1764 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1765 uint16_t data_offset;
1766 struct _COMPASSIONATE_DATA *dac_info;
1767 uint8_t frev, crev;
1768 uint8_t bg, dac;
1769 struct radeon_encoder_primary_dac *p_dac = NULL;
1770
1771 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1772 &frev, &crev, &data_offset)) {
1773 dac_info = (struct _COMPASSIONATE_DATA *)
1774 (mode_info->atom_context->bios + data_offset);
1775
1776 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1777
1778 if (!p_dac)
1779 return NULL;
1780
1781 bg = dac_info->ucDAC1_BG_Adjustment;
1782 dac = dac_info->ucDAC1_DAC_Adjustment;
1783 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1784
1785 }
1786 return p_dac;
1787 }
1788
radeon_atom_get_tv_timings(struct radeon_device * rdev,int index,struct drm_display_mode * mode)1789 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1790 struct drm_display_mode *mode)
1791 {
1792 struct radeon_mode_info *mode_info = &rdev->mode_info;
1793 ATOM_ANALOG_TV_INFO *tv_info;
1794 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1795 ATOM_DTD_FORMAT *dtd_timings;
1796 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1797 u8 frev, crev;
1798 u16 data_offset, misc;
1799
1800 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1801 &frev, &crev, &data_offset))
1802 return false;
1803
1804 switch (crev) {
1805 case 1:
1806 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1807 if (index >= MAX_SUPPORTED_TV_TIMING)
1808 return false;
1809
1810 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1811 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1812 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1813 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1814 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1815
1816 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1817 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1818 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1819 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1820 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1821
1822 mode->flags = 0;
1823 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1824 if (misc & ATOM_VSYNC_POLARITY)
1825 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1826 if (misc & ATOM_HSYNC_POLARITY)
1827 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1828 if (misc & ATOM_COMPOSITESYNC)
1829 mode->flags |= DRM_MODE_FLAG_CSYNC;
1830 if (misc & ATOM_INTERLACE)
1831 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1832 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1833 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1834
1835 mode->crtc_clock = mode->clock =
1836 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1837
1838 if (index == 1) {
1839 /* PAL timings appear to have wrong values for totals */
1840 mode->crtc_htotal -= 1;
1841 mode->crtc_vtotal -= 1;
1842 }
1843 break;
1844 case 2:
1845 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1846 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1847 return false;
1848
1849 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1850 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1851 le16_to_cpu(dtd_timings->usHBlanking_Time);
1852 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1853 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1854 le16_to_cpu(dtd_timings->usHSyncOffset);
1855 mode->crtc_hsync_end = mode->crtc_hsync_start +
1856 le16_to_cpu(dtd_timings->usHSyncWidth);
1857
1858 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1859 le16_to_cpu(dtd_timings->usVBlanking_Time);
1860 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1861 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1862 le16_to_cpu(dtd_timings->usVSyncOffset);
1863 mode->crtc_vsync_end = mode->crtc_vsync_start +
1864 le16_to_cpu(dtd_timings->usVSyncWidth);
1865
1866 mode->flags = 0;
1867 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1868 if (misc & ATOM_VSYNC_POLARITY)
1869 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1870 if (misc & ATOM_HSYNC_POLARITY)
1871 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1872 if (misc & ATOM_COMPOSITESYNC)
1873 mode->flags |= DRM_MODE_FLAG_CSYNC;
1874 if (misc & ATOM_INTERLACE)
1875 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1876 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1877 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1878
1879 mode->crtc_clock = mode->clock =
1880 le16_to_cpu(dtd_timings->usPixClk) * 10;
1881 break;
1882 }
1883 return true;
1884 }
1885
1886 enum radeon_tv_std
radeon_atombios_get_tv_info(struct radeon_device * rdev)1887 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1888 {
1889 struct radeon_mode_info *mode_info = &rdev->mode_info;
1890 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1891 uint16_t data_offset;
1892 uint8_t frev, crev;
1893 struct _ATOM_ANALOG_TV_INFO *tv_info;
1894 enum radeon_tv_std tv_std = TV_STD_NTSC;
1895
1896 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1897 &frev, &crev, &data_offset)) {
1898
1899 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1900 (mode_info->atom_context->bios + data_offset);
1901
1902 switch (tv_info->ucTV_BootUpDefaultStandard) {
1903 case ATOM_TV_NTSC:
1904 tv_std = TV_STD_NTSC;
1905 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1906 break;
1907 case ATOM_TV_NTSCJ:
1908 tv_std = TV_STD_NTSC_J;
1909 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1910 break;
1911 case ATOM_TV_PAL:
1912 tv_std = TV_STD_PAL;
1913 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1914 break;
1915 case ATOM_TV_PALM:
1916 tv_std = TV_STD_PAL_M;
1917 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1918 break;
1919 case ATOM_TV_PALN:
1920 tv_std = TV_STD_PAL_N;
1921 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1922 break;
1923 case ATOM_TV_PALCN:
1924 tv_std = TV_STD_PAL_CN;
1925 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1926 break;
1927 case ATOM_TV_PAL60:
1928 tv_std = TV_STD_PAL_60;
1929 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1930 break;
1931 case ATOM_TV_SECAM:
1932 tv_std = TV_STD_SECAM;
1933 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1934 break;
1935 default:
1936 tv_std = TV_STD_NTSC;
1937 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1938 break;
1939 }
1940 }
1941 return tv_std;
1942 }
1943
1944 struct radeon_encoder_tv_dac *
radeon_atombios_get_tv_dac_info(struct radeon_encoder * encoder)1945 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1946 {
1947 struct drm_device *dev = encoder->base.dev;
1948 struct radeon_device *rdev = dev->dev_private;
1949 struct radeon_mode_info *mode_info = &rdev->mode_info;
1950 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1951 uint16_t data_offset;
1952 struct _COMPASSIONATE_DATA *dac_info;
1953 uint8_t frev, crev;
1954 uint8_t bg, dac;
1955 struct radeon_encoder_tv_dac *tv_dac = NULL;
1956
1957 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1958 &frev, &crev, &data_offset)) {
1959
1960 dac_info = (struct _COMPASSIONATE_DATA *)
1961 (mode_info->atom_context->bios + data_offset);
1962
1963 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1964
1965 if (!tv_dac)
1966 return NULL;
1967
1968 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1969 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1970 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1971
1972 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1973 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1974 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1975
1976 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1977 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1978 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1979
1980 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1981 }
1982 return tv_dac;
1983 }
1984
1985 static const char *thermal_controller_names[] = {
1986 "NONE",
1987 "lm63",
1988 "adm1032",
1989 "adm1030",
1990 "max6649",
1991 "lm63", /* lm64 */
1992 "f75375",
1993 "asc7xxx",
1994 };
1995
1996 static const char *pp_lib_thermal_controller_names[] = {
1997 "NONE",
1998 "lm63",
1999 "adm1032",
2000 "adm1030",
2001 "max6649",
2002 "lm63", /* lm64 */
2003 "f75375",
2004 "RV6xx",
2005 "RV770",
2006 "adt7473",
2007 "NONE",
2008 "External GPIO",
2009 "Evergreen",
2010 "emc2103",
2011 "Sumo",
2012 "Northern Islands",
2013 "Southern Islands",
2014 "lm96163",
2015 "Sea Islands",
2016 };
2017
2018 union power_info {
2019 struct _ATOM_POWERPLAY_INFO info;
2020 struct _ATOM_POWERPLAY_INFO_V2 info_2;
2021 struct _ATOM_POWERPLAY_INFO_V3 info_3;
2022 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2023 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2024 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2025 };
2026
2027 union pplib_clock_info {
2028 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2029 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2030 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2031 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2032 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
2033 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
2034 };
2035
2036 union pplib_power_state {
2037 struct _ATOM_PPLIB_STATE v1;
2038 struct _ATOM_PPLIB_STATE_V2 v2;
2039 };
2040
radeon_atombios_parse_misc_flags_1_3(struct radeon_device * rdev,int state_index,u32 misc,u32 misc2)2041 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2042 int state_index,
2043 u32 misc, u32 misc2)
2044 {
2045 rdev->pm.power_state[state_index].misc = misc;
2046 rdev->pm.power_state[state_index].misc2 = misc2;
2047 /* order matters! */
2048 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2049 rdev->pm.power_state[state_index].type =
2050 POWER_STATE_TYPE_POWERSAVE;
2051 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2052 rdev->pm.power_state[state_index].type =
2053 POWER_STATE_TYPE_BATTERY;
2054 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2055 rdev->pm.power_state[state_index].type =
2056 POWER_STATE_TYPE_BATTERY;
2057 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2058 rdev->pm.power_state[state_index].type =
2059 POWER_STATE_TYPE_BALANCED;
2060 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2061 rdev->pm.power_state[state_index].type =
2062 POWER_STATE_TYPE_PERFORMANCE;
2063 rdev->pm.power_state[state_index].flags &=
2064 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2065 }
2066 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2067 rdev->pm.power_state[state_index].type =
2068 POWER_STATE_TYPE_BALANCED;
2069 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2070 rdev->pm.power_state[state_index].type =
2071 POWER_STATE_TYPE_DEFAULT;
2072 rdev->pm.default_power_state_index = state_index;
2073 rdev->pm.power_state[state_index].default_clock_mode =
2074 &rdev->pm.power_state[state_index].clock_info[0];
2075 } else if (state_index == 0) {
2076 rdev->pm.power_state[state_index].clock_info[0].flags |=
2077 RADEON_PM_MODE_NO_DISPLAY;
2078 }
2079 }
2080
radeon_atombios_parse_power_table_1_3(struct radeon_device * rdev)2081 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2082 {
2083 struct radeon_mode_info *mode_info = &rdev->mode_info;
2084 u32 misc, misc2 = 0;
2085 int num_modes = 0, i;
2086 int state_index = 0;
2087 struct radeon_i2c_bus_rec i2c_bus;
2088 union power_info *power_info;
2089 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2090 u16 data_offset;
2091 u8 frev, crev;
2092
2093 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2094 &frev, &crev, &data_offset))
2095 return state_index;
2096 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2097
2098 /* add the i2c bus for thermal/fan chip */
2099 if ((power_info->info.ucOverdriveThermalController > 0) &&
2100 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2101 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2102 thermal_controller_names[power_info->info.ucOverdriveThermalController],
2103 power_info->info.ucOverdriveControllerAddress >> 1);
2104 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2105 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2106 if (rdev->pm.i2c_bus) {
2107 struct i2c_board_info info = { };
2108 const char *name = thermal_controller_names[power_info->info.
2109 ucOverdriveThermalController];
2110 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2111 strlcpy(info.type, name, sizeof(info.type));
2112 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2113 }
2114 }
2115 num_modes = power_info->info.ucNumOfPowerModeEntries;
2116 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2117 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2118 if (num_modes == 0)
2119 return state_index;
2120 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2121 if (!rdev->pm.power_state)
2122 return state_index;
2123 /* last mode is usually default, array is low to high */
2124 for (i = 0; i < num_modes; i++) {
2125 rdev->pm.power_state[state_index].clock_info =
2126 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2127 if (!rdev->pm.power_state[state_index].clock_info)
2128 return state_index;
2129 rdev->pm.power_state[state_index].num_clock_modes = 1;
2130 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2131 switch (frev) {
2132 case 1:
2133 rdev->pm.power_state[state_index].clock_info[0].mclk =
2134 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2135 rdev->pm.power_state[state_index].clock_info[0].sclk =
2136 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2137 /* skip invalid modes */
2138 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2139 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2140 continue;
2141 rdev->pm.power_state[state_index].pcie_lanes =
2142 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2143 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2144 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2145 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2146 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2147 VOLTAGE_GPIO;
2148 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2149 radeon_atombios_lookup_gpio(rdev,
2150 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2151 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2152 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2153 true;
2154 else
2155 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2156 false;
2157 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2158 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2159 VOLTAGE_VDDC;
2160 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2161 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2162 }
2163 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2164 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2165 state_index++;
2166 break;
2167 case 2:
2168 rdev->pm.power_state[state_index].clock_info[0].mclk =
2169 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2170 rdev->pm.power_state[state_index].clock_info[0].sclk =
2171 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2172 /* skip invalid modes */
2173 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2174 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2175 continue;
2176 rdev->pm.power_state[state_index].pcie_lanes =
2177 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2178 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2179 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2180 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2181 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2182 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2183 VOLTAGE_GPIO;
2184 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2185 radeon_atombios_lookup_gpio(rdev,
2186 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2187 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2188 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2189 true;
2190 else
2191 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2192 false;
2193 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2194 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2195 VOLTAGE_VDDC;
2196 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2197 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2198 }
2199 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2200 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2201 state_index++;
2202 break;
2203 case 3:
2204 rdev->pm.power_state[state_index].clock_info[0].mclk =
2205 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2206 rdev->pm.power_state[state_index].clock_info[0].sclk =
2207 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2208 /* skip invalid modes */
2209 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2210 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2211 continue;
2212 rdev->pm.power_state[state_index].pcie_lanes =
2213 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2214 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2215 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2216 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2217 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2218 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2219 VOLTAGE_GPIO;
2220 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2221 radeon_atombios_lookup_gpio(rdev,
2222 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2223 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2224 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2225 true;
2226 else
2227 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2228 false;
2229 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2230 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2231 VOLTAGE_VDDC;
2232 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2233 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2234 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2235 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2236 true;
2237 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2238 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2239 }
2240 }
2241 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2242 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2243 state_index++;
2244 break;
2245 }
2246 }
2247 /* last mode is usually default */
2248 if (rdev->pm.default_power_state_index == -1) {
2249 rdev->pm.power_state[state_index - 1].type =
2250 POWER_STATE_TYPE_DEFAULT;
2251 rdev->pm.default_power_state_index = state_index - 1;
2252 rdev->pm.power_state[state_index - 1].default_clock_mode =
2253 &rdev->pm.power_state[state_index - 1].clock_info[0];
2254 rdev->pm.power_state[state_index].flags &=
2255 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2256 rdev->pm.power_state[state_index].misc = 0;
2257 rdev->pm.power_state[state_index].misc2 = 0;
2258 }
2259 return state_index;
2260 }
2261
radeon_atombios_add_pplib_thermal_controller(struct radeon_device * rdev,ATOM_PPLIB_THERMALCONTROLLER * controller)2262 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2263 ATOM_PPLIB_THERMALCONTROLLER *controller)
2264 {
2265 struct radeon_i2c_bus_rec i2c_bus;
2266
2267 /* add the i2c bus for thermal/fan chip */
2268 if (controller->ucType > 0) {
2269 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN)
2270 rdev->pm.no_fan = true;
2271 rdev->pm.fan_pulses_per_revolution =
2272 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
2273 if (rdev->pm.fan_pulses_per_revolution) {
2274 rdev->pm.fan_min_rpm = controller->ucFanMinRPM;
2275 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM;
2276 }
2277 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2278 DRM_INFO("Internal thermal controller %s fan control\n",
2279 (controller->ucFanParameters &
2280 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2281 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2282 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2283 DRM_INFO("Internal thermal controller %s fan control\n",
2284 (controller->ucFanParameters &
2285 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2286 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2287 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2288 DRM_INFO("Internal thermal controller %s fan control\n",
2289 (controller->ucFanParameters &
2290 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2291 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2292 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2293 DRM_INFO("Internal thermal controller %s fan control\n",
2294 (controller->ucFanParameters &
2295 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2296 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2297 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2298 DRM_INFO("Internal thermal controller %s fan control\n",
2299 (controller->ucFanParameters &
2300 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2301 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2302 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2303 DRM_INFO("Internal thermal controller %s fan control\n",
2304 (controller->ucFanParameters &
2305 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2306 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2307 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2308 DRM_INFO("Internal thermal controller %s fan control\n",
2309 (controller->ucFanParameters &
2310 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2311 rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2312 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
2313 DRM_INFO("Internal thermal controller %s fan control\n",
2314 (controller->ucFanParameters &
2315 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2316 rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2317 } else if (controller->ucType ==
2318 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
2319 DRM_INFO("External GPIO thermal controller %s fan control\n",
2320 (controller->ucFanParameters &
2321 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2322 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
2323 } else if (controller->ucType ==
2324 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
2325 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
2326 (controller->ucFanParameters &
2327 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2328 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
2329 } else if (controller->ucType ==
2330 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
2331 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
2332 (controller->ucFanParameters &
2333 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2334 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2335 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2336 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2337 pp_lib_thermal_controller_names[controller->ucType],
2338 controller->ucI2cAddress >> 1,
2339 (controller->ucFanParameters &
2340 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2341 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
2342 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2343 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2344 if (rdev->pm.i2c_bus) {
2345 struct i2c_board_info info = { };
2346 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2347 info.addr = controller->ucI2cAddress >> 1;
2348 strlcpy(info.type, name, sizeof(info.type));
2349 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2350 }
2351 } else {
2352 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2353 controller->ucType,
2354 controller->ucI2cAddress >> 1,
2355 (controller->ucFanParameters &
2356 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2357 }
2358 }
2359 }
2360
radeon_atombios_get_default_voltages(struct radeon_device * rdev,u16 * vddc,u16 * vddci,u16 * mvdd)2361 void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2362 u16 *vddc, u16 *vddci, u16 *mvdd)
2363 {
2364 struct radeon_mode_info *mode_info = &rdev->mode_info;
2365 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2366 u8 frev, crev;
2367 u16 data_offset;
2368 union firmware_info *firmware_info;
2369
2370 *vddc = 0;
2371 *vddci = 0;
2372 *mvdd = 0;
2373
2374 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2375 &frev, &crev, &data_offset)) {
2376 firmware_info =
2377 (union firmware_info *)(mode_info->atom_context->bios +
2378 data_offset);
2379 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2380 if ((frev == 2) && (crev >= 2)) {
2381 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2382 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2383 }
2384 }
2385 }
2386
radeon_atombios_parse_pplib_non_clock_info(struct radeon_device * rdev,int state_index,int mode_index,struct _ATOM_PPLIB_NONCLOCK_INFO * non_clock_info)2387 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2388 int state_index, int mode_index,
2389 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2390 {
2391 int j;
2392 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2393 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2394 u16 vddc, vddci, mvdd;
2395
2396 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2397
2398 rdev->pm.power_state[state_index].misc = misc;
2399 rdev->pm.power_state[state_index].misc2 = misc2;
2400 rdev->pm.power_state[state_index].pcie_lanes =
2401 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2402 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2403 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2404 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2405 rdev->pm.power_state[state_index].type =
2406 POWER_STATE_TYPE_BATTERY;
2407 break;
2408 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2409 rdev->pm.power_state[state_index].type =
2410 POWER_STATE_TYPE_BALANCED;
2411 break;
2412 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2413 rdev->pm.power_state[state_index].type =
2414 POWER_STATE_TYPE_PERFORMANCE;
2415 break;
2416 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2417 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2418 rdev->pm.power_state[state_index].type =
2419 POWER_STATE_TYPE_PERFORMANCE;
2420 break;
2421 }
2422 rdev->pm.power_state[state_index].flags = 0;
2423 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2424 rdev->pm.power_state[state_index].flags |=
2425 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2426 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2427 rdev->pm.power_state[state_index].type =
2428 POWER_STATE_TYPE_DEFAULT;
2429 rdev->pm.default_power_state_index = state_index;
2430 rdev->pm.power_state[state_index].default_clock_mode =
2431 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2432 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2433 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2434 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2435 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2436 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2437 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2438 } else {
2439 u16 max_vddci = 0;
2440
2441 if (ASIC_IS_DCE4(rdev))
2442 radeon_atom_get_max_voltage(rdev,
2443 SET_VOLTAGE_TYPE_ASIC_VDDCI,
2444 &max_vddci);
2445 /* patch the table values with the default sclk/mclk from firmware info */
2446 for (j = 0; j < mode_index; j++) {
2447 rdev->pm.power_state[state_index].clock_info[j].mclk =
2448 rdev->clock.default_mclk;
2449 rdev->pm.power_state[state_index].clock_info[j].sclk =
2450 rdev->clock.default_sclk;
2451 if (vddc)
2452 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2453 vddc;
2454 if (max_vddci)
2455 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2456 max_vddci;
2457 }
2458 }
2459 }
2460 }
2461
radeon_atombios_parse_pplib_clock_info(struct radeon_device * rdev,int state_index,int mode_index,union pplib_clock_info * clock_info)2462 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2463 int state_index, int mode_index,
2464 union pplib_clock_info *clock_info)
2465 {
2466 u32 sclk, mclk;
2467 u16 vddc;
2468
2469 if (rdev->flags & RADEON_IS_IGP) {
2470 if (rdev->family >= CHIP_PALM) {
2471 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2472 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2473 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2474 } else {
2475 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2476 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2477 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2478 }
2479 } else if (rdev->family >= CHIP_BONAIRE) {
2480 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2481 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2482 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2483 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2484 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2485 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2486 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2487 VOLTAGE_NONE;
2488 } else if (rdev->family >= CHIP_TAHITI) {
2489 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2490 sclk |= clock_info->si.ucEngineClockHigh << 16;
2491 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2492 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2493 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2494 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2495 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2496 VOLTAGE_SW;
2497 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2498 le16_to_cpu(clock_info->si.usVDDC);
2499 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2500 le16_to_cpu(clock_info->si.usVDDCI);
2501 } else if (rdev->family >= CHIP_CEDAR) {
2502 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2503 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2504 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2505 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2506 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2507 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2508 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2509 VOLTAGE_SW;
2510 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2511 le16_to_cpu(clock_info->evergreen.usVDDC);
2512 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2513 le16_to_cpu(clock_info->evergreen.usVDDCI);
2514 } else {
2515 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2516 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2517 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2518 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2519 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2520 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2521 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2522 VOLTAGE_SW;
2523 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2524 le16_to_cpu(clock_info->r600.usVDDC);
2525 }
2526
2527 /* patch up vddc if necessary */
2528 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2529 case ATOM_VIRTUAL_VOLTAGE_ID0:
2530 case ATOM_VIRTUAL_VOLTAGE_ID1:
2531 case ATOM_VIRTUAL_VOLTAGE_ID2:
2532 case ATOM_VIRTUAL_VOLTAGE_ID3:
2533 case ATOM_VIRTUAL_VOLTAGE_ID4:
2534 case ATOM_VIRTUAL_VOLTAGE_ID5:
2535 case ATOM_VIRTUAL_VOLTAGE_ID6:
2536 case ATOM_VIRTUAL_VOLTAGE_ID7:
2537 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2538 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2539 &vddc) == 0)
2540 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2541 break;
2542 default:
2543 break;
2544 }
2545
2546 if (rdev->flags & RADEON_IS_IGP) {
2547 /* skip invalid modes */
2548 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2549 return false;
2550 } else {
2551 /* skip invalid modes */
2552 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2553 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2554 return false;
2555 }
2556 return true;
2557 }
2558
radeon_atombios_parse_power_table_4_5(struct radeon_device * rdev)2559 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2560 {
2561 struct radeon_mode_info *mode_info = &rdev->mode_info;
2562 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2563 union pplib_power_state *power_state;
2564 int i, j;
2565 int state_index = 0, mode_index = 0;
2566 union pplib_clock_info *clock_info;
2567 bool valid;
2568 union power_info *power_info;
2569 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2570 u16 data_offset;
2571 u8 frev, crev;
2572
2573 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2574 &frev, &crev, &data_offset))
2575 return state_index;
2576 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2577
2578 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2579 if (power_info->pplib.ucNumStates == 0)
2580 return state_index;
2581 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2582 power_info->pplib.ucNumStates, GFP_KERNEL);
2583 if (!rdev->pm.power_state)
2584 return state_index;
2585 /* first mode is usually default, followed by low to high */
2586 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2587 mode_index = 0;
2588 power_state = (union pplib_power_state *)
2589 (mode_info->atom_context->bios + data_offset +
2590 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2591 i * power_info->pplib.ucStateEntrySize);
2592 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2593 (mode_info->atom_context->bios + data_offset +
2594 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2595 (power_state->v1.ucNonClockStateIndex *
2596 power_info->pplib.ucNonClockSize));
2597 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2598 ((power_info->pplib.ucStateEntrySize - 1) ?
2599 (power_info->pplib.ucStateEntrySize - 1) : 1),
2600 GFP_KERNEL);
2601 if (!rdev->pm.power_state[i].clock_info)
2602 return state_index;
2603 if (power_info->pplib.ucStateEntrySize - 1) {
2604 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2605 clock_info = (union pplib_clock_info *)
2606 (mode_info->atom_context->bios + data_offset +
2607 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2608 (power_state->v1.ucClockStateIndices[j] *
2609 power_info->pplib.ucClockInfoSize));
2610 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2611 state_index, mode_index,
2612 clock_info);
2613 if (valid)
2614 mode_index++;
2615 }
2616 } else {
2617 rdev->pm.power_state[state_index].clock_info[0].mclk =
2618 rdev->clock.default_mclk;
2619 rdev->pm.power_state[state_index].clock_info[0].sclk =
2620 rdev->clock.default_sclk;
2621 mode_index++;
2622 }
2623 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2624 if (mode_index) {
2625 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2626 non_clock_info);
2627 state_index++;
2628 }
2629 }
2630 /* if multiple clock modes, mark the lowest as no display */
2631 for (i = 0; i < state_index; i++) {
2632 if (rdev->pm.power_state[i].num_clock_modes > 1)
2633 rdev->pm.power_state[i].clock_info[0].flags |=
2634 RADEON_PM_MODE_NO_DISPLAY;
2635 }
2636 /* first mode is usually default */
2637 if (rdev->pm.default_power_state_index == -1) {
2638 rdev->pm.power_state[0].type =
2639 POWER_STATE_TYPE_DEFAULT;
2640 rdev->pm.default_power_state_index = 0;
2641 rdev->pm.power_state[0].default_clock_mode =
2642 &rdev->pm.power_state[0].clock_info[0];
2643 }
2644 return state_index;
2645 }
2646
radeon_atombios_parse_power_table_6(struct radeon_device * rdev)2647 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2648 {
2649 struct radeon_mode_info *mode_info = &rdev->mode_info;
2650 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2651 union pplib_power_state *power_state;
2652 int i, j, non_clock_array_index, clock_array_index;
2653 int state_index = 0, mode_index = 0;
2654 union pplib_clock_info *clock_info;
2655 struct _StateArray *state_array;
2656 struct _ClockInfoArray *clock_info_array;
2657 struct _NonClockInfoArray *non_clock_info_array;
2658 bool valid;
2659 union power_info *power_info;
2660 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2661 u16 data_offset;
2662 u8 frev, crev;
2663 u8 *power_state_offset;
2664
2665 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2666 &frev, &crev, &data_offset))
2667 return state_index;
2668 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2669
2670 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2671 state_array = (struct _StateArray *)
2672 (mode_info->atom_context->bios + data_offset +
2673 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2674 clock_info_array = (struct _ClockInfoArray *)
2675 (mode_info->atom_context->bios + data_offset +
2676 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2677 non_clock_info_array = (struct _NonClockInfoArray *)
2678 (mode_info->atom_context->bios + data_offset +
2679 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2680 if (state_array->ucNumEntries == 0)
2681 return state_index;
2682 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2683 state_array->ucNumEntries, GFP_KERNEL);
2684 if (!rdev->pm.power_state)
2685 return state_index;
2686 power_state_offset = (u8 *)state_array->states;
2687 for (i = 0; i < state_array->ucNumEntries; i++) {
2688 mode_index = 0;
2689 power_state = (union pplib_power_state *)power_state_offset;
2690 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2691 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2692 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2693 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2694 (power_state->v2.ucNumDPMLevels ?
2695 power_state->v2.ucNumDPMLevels : 1),
2696 GFP_KERNEL);
2697 if (!rdev->pm.power_state[i].clock_info)
2698 return state_index;
2699 if (power_state->v2.ucNumDPMLevels) {
2700 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2701 clock_array_index = power_state->v2.clockInfoIndex[j];
2702 clock_info = (union pplib_clock_info *)
2703 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2704 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2705 state_index, mode_index,
2706 clock_info);
2707 if (valid)
2708 mode_index++;
2709 }
2710 } else {
2711 rdev->pm.power_state[state_index].clock_info[0].mclk =
2712 rdev->clock.default_mclk;
2713 rdev->pm.power_state[state_index].clock_info[0].sclk =
2714 rdev->clock.default_sclk;
2715 mode_index++;
2716 }
2717 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2718 if (mode_index) {
2719 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2720 non_clock_info);
2721 state_index++;
2722 }
2723 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2724 }
2725 /* if multiple clock modes, mark the lowest as no display */
2726 for (i = 0; i < state_index; i++) {
2727 if (rdev->pm.power_state[i].num_clock_modes > 1)
2728 rdev->pm.power_state[i].clock_info[0].flags |=
2729 RADEON_PM_MODE_NO_DISPLAY;
2730 }
2731 /* first mode is usually default */
2732 if (rdev->pm.default_power_state_index == -1) {
2733 rdev->pm.power_state[0].type =
2734 POWER_STATE_TYPE_DEFAULT;
2735 rdev->pm.default_power_state_index = 0;
2736 rdev->pm.power_state[0].default_clock_mode =
2737 &rdev->pm.power_state[0].clock_info[0];
2738 }
2739 return state_index;
2740 }
2741
radeon_atombios_get_power_modes(struct radeon_device * rdev)2742 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2743 {
2744 struct radeon_mode_info *mode_info = &rdev->mode_info;
2745 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2746 u16 data_offset;
2747 u8 frev, crev;
2748 int state_index = 0;
2749
2750 rdev->pm.default_power_state_index = -1;
2751
2752 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2753 &frev, &crev, &data_offset)) {
2754 switch (frev) {
2755 case 1:
2756 case 2:
2757 case 3:
2758 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2759 break;
2760 case 4:
2761 case 5:
2762 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2763 break;
2764 case 6:
2765 state_index = radeon_atombios_parse_power_table_6(rdev);
2766 break;
2767 default:
2768 break;
2769 }
2770 }
2771
2772 if (state_index == 0) {
2773 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2774 if (rdev->pm.power_state) {
2775 rdev->pm.power_state[0].clock_info =
2776 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2777 if (rdev->pm.power_state[0].clock_info) {
2778 /* add the default mode */
2779 rdev->pm.power_state[state_index].type =
2780 POWER_STATE_TYPE_DEFAULT;
2781 rdev->pm.power_state[state_index].num_clock_modes = 1;
2782 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2783 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2784 rdev->pm.power_state[state_index].default_clock_mode =
2785 &rdev->pm.power_state[state_index].clock_info[0];
2786 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2787 rdev->pm.power_state[state_index].pcie_lanes = 16;
2788 rdev->pm.default_power_state_index = state_index;
2789 rdev->pm.power_state[state_index].flags = 0;
2790 state_index++;
2791 }
2792 }
2793 }
2794
2795 rdev->pm.num_power_states = state_index;
2796
2797 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2798 rdev->pm.current_clock_mode_index = 0;
2799 if (rdev->pm.default_power_state_index >= 0)
2800 rdev->pm.current_vddc =
2801 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2802 else
2803 rdev->pm.current_vddc = 0;
2804 }
2805
2806 union get_clock_dividers {
2807 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2808 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2809 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2810 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2811 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2812 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2813 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2814 };
2815
radeon_atom_get_clock_dividers(struct radeon_device * rdev,u8 clock_type,u32 clock,bool strobe_mode,struct atom_clock_dividers * dividers)2816 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2817 u8 clock_type,
2818 u32 clock,
2819 bool strobe_mode,
2820 struct atom_clock_dividers *dividers)
2821 {
2822 union get_clock_dividers args;
2823 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2824 u8 frev, crev;
2825
2826 memset(&args, 0, sizeof(args));
2827 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2828
2829 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2830 return -EINVAL;
2831
2832 switch (crev) {
2833 case 1:
2834 /* r4xx, r5xx */
2835 args.v1.ucAction = clock_type;
2836 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
2837
2838 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2839
2840 dividers->post_div = args.v1.ucPostDiv;
2841 dividers->fb_div = args.v1.ucFbDiv;
2842 dividers->enable_post_div = true;
2843 break;
2844 case 2:
2845 case 3:
2846 case 5:
2847 /* r6xx, r7xx, evergreen, ni, si */
2848 if (rdev->family <= CHIP_RV770) {
2849 args.v2.ucAction = clock_type;
2850 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
2851
2852 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2853
2854 dividers->post_div = args.v2.ucPostDiv;
2855 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2856 dividers->ref_div = args.v2.ucAction;
2857 if (rdev->family == CHIP_RV770) {
2858 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2859 true : false;
2860 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2861 } else
2862 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2863 } else {
2864 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2865 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2866
2867 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2868
2869 dividers->post_div = args.v3.ucPostDiv;
2870 dividers->enable_post_div = (args.v3.ucCntlFlag &
2871 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2872 dividers->enable_dithen = (args.v3.ucCntlFlag &
2873 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2874 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2875 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2876 dividers->ref_div = args.v3.ucRefDiv;
2877 dividers->vco_mode = (args.v3.ucCntlFlag &
2878 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2879 } else {
2880 /* for SI we use ComputeMemoryClockParam for memory plls */
2881 if (rdev->family >= CHIP_TAHITI)
2882 return -EINVAL;
2883 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2884 if (strobe_mode)
2885 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2886
2887 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2888
2889 dividers->post_div = args.v5.ucPostDiv;
2890 dividers->enable_post_div = (args.v5.ucCntlFlag &
2891 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2892 dividers->enable_dithen = (args.v5.ucCntlFlag &
2893 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2894 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2895 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2896 dividers->ref_div = args.v5.ucRefDiv;
2897 dividers->vco_mode = (args.v5.ucCntlFlag &
2898 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2899 }
2900 }
2901 break;
2902 case 4:
2903 /* fusion */
2904 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
2905
2906 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2907
2908 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2909 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2910 break;
2911 case 6:
2912 /* CI */
2913 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2914 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2915 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2916
2917 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2918
2919 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2920 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2921 dividers->ref_div = args.v6_out.ucPllRefDiv;
2922 dividers->post_div = args.v6_out.ucPllPostDiv;
2923 dividers->flags = args.v6_out.ucPllCntlFlag;
2924 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2925 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2926 break;
2927 default:
2928 return -EINVAL;
2929 }
2930 return 0;
2931 }
2932
radeon_atom_get_memory_pll_dividers(struct radeon_device * rdev,u32 clock,bool strobe_mode,struct atom_mpll_param * mpll_param)2933 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2934 u32 clock,
2935 bool strobe_mode,
2936 struct atom_mpll_param *mpll_param)
2937 {
2938 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2939 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2940 u8 frev, crev;
2941
2942 memset(&args, 0, sizeof(args));
2943 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2944
2945 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2946 return -EINVAL;
2947
2948 switch (frev) {
2949 case 2:
2950 switch (crev) {
2951 case 1:
2952 /* SI */
2953 args.ulClock = cpu_to_le32(clock); /* 10 khz */
2954 args.ucInputFlag = 0;
2955 if (strobe_mode)
2956 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2957
2958 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2959
2960 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2961 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2962 mpll_param->post_div = args.ucPostDiv;
2963 mpll_param->dll_speed = args.ucDllSpeed;
2964 mpll_param->bwcntl = args.ucBWCntl;
2965 mpll_param->vco_mode =
2966 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
2967 mpll_param->yclk_sel =
2968 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2969 mpll_param->qdr =
2970 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2971 mpll_param->half_rate =
2972 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
2973 break;
2974 default:
2975 return -EINVAL;
2976 }
2977 break;
2978 default:
2979 return -EINVAL;
2980 }
2981 return 0;
2982 }
2983
radeon_atom_set_clock_gating(struct radeon_device * rdev,int enable)2984 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2985 {
2986 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2987 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2988
2989 args.ucEnable = enable;
2990
2991 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2992 }
2993
radeon_atom_get_engine_clock(struct radeon_device * rdev)2994 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2995 {
2996 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2997 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2998
2999 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3000 return le32_to_cpu(args.ulReturnEngineClock);
3001 }
3002
radeon_atom_get_memory_clock(struct radeon_device * rdev)3003 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
3004 {
3005 GET_MEMORY_CLOCK_PS_ALLOCATION args;
3006 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
3007
3008 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3009 return le32_to_cpu(args.ulReturnMemoryClock);
3010 }
3011
radeon_atom_set_engine_clock(struct radeon_device * rdev,uint32_t eng_clock)3012 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
3013 uint32_t eng_clock)
3014 {
3015 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3016 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
3017
3018 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
3019
3020 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3021 }
3022
radeon_atom_set_memory_clock(struct radeon_device * rdev,uint32_t mem_clock)3023 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
3024 uint32_t mem_clock)
3025 {
3026 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3027 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
3028
3029 if (rdev->flags & RADEON_IS_IGP)
3030 return;
3031
3032 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
3033
3034 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3035 }
3036
radeon_atom_set_engine_dram_timings(struct radeon_device * rdev,u32 eng_clock,u32 mem_clock)3037 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
3038 u32 eng_clock, u32 mem_clock)
3039 {
3040 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3041 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3042 u32 tmp;
3043
3044 memset(&args, 0, sizeof(args));
3045
3046 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
3047 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
3048
3049 args.ulTargetEngineClock = cpu_to_le32(tmp);
3050 if (mem_clock)
3051 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
3052
3053 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3054 }
3055
radeon_atom_update_memory_dll(struct radeon_device * rdev,u32 mem_clock)3056 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3057 u32 mem_clock)
3058 {
3059 u32 args;
3060 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3061
3062 args = cpu_to_le32(mem_clock); /* 10 khz */
3063
3064 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3065 }
3066
radeon_atom_set_ac_timing(struct radeon_device * rdev,u32 mem_clock)3067 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3068 u32 mem_clock)
3069 {
3070 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3071 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3072 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
3073
3074 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */
3075
3076 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3077 }
3078
3079 union set_voltage {
3080 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
3081 struct _SET_VOLTAGE_PARAMETERS v1;
3082 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
3083 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
3084 };
3085
radeon_atom_set_voltage(struct radeon_device * rdev,u16 voltage_level,u8 voltage_type)3086 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3087 {
3088 union set_voltage args;
3089 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3090 u8 frev, crev, volt_index = voltage_level;
3091
3092 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3093 return;
3094
3095 /* 0xff01 is a flag rather then an actual voltage */
3096 if (voltage_level == 0xff01)
3097 return;
3098
3099 switch (crev) {
3100 case 1:
3101 args.v1.ucVoltageType = voltage_type;
3102 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3103 args.v1.ucVoltageIndex = volt_index;
3104 break;
3105 case 2:
3106 args.v2.ucVoltageType = voltage_type;
3107 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3108 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3109 break;
3110 case 3:
3111 args.v3.ucVoltageType = voltage_type;
3112 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3113 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3114 break;
3115 default:
3116 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3117 return;
3118 }
3119
3120 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3121 }
3122
radeon_atom_get_max_vddc(struct radeon_device * rdev,u8 voltage_type,u16 voltage_id,u16 * voltage)3123 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3124 u16 voltage_id, u16 *voltage)
3125 {
3126 union set_voltage args;
3127 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3128 u8 frev, crev;
3129
3130 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3131 return -EINVAL;
3132
3133 switch (crev) {
3134 case 1:
3135 return -EINVAL;
3136 case 2:
3137 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3138 args.v2.ucVoltageMode = 0;
3139 args.v2.usVoltageLevel = 0;
3140
3141 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3142
3143 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3144 break;
3145 case 3:
3146 args.v3.ucVoltageType = voltage_type;
3147 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3148 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3149
3150 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3151
3152 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3153 break;
3154 default:
3155 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3156 return -EINVAL;
3157 }
3158
3159 return 0;
3160 }
3161
radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device * rdev,u16 * voltage,u16 leakage_idx)3162 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3163 u16 *voltage,
3164 u16 leakage_idx)
3165 {
3166 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3167 }
3168
radeon_atom_get_leakage_id_from_vbios(struct radeon_device * rdev,u16 * leakage_id)3169 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3170 u16 *leakage_id)
3171 {
3172 union set_voltage args;
3173 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3174 u8 frev, crev;
3175
3176 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3177 return -EINVAL;
3178
3179 switch (crev) {
3180 case 3:
3181 case 4:
3182 args.v3.ucVoltageType = 0;
3183 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
3184 args.v3.usVoltageLevel = 0;
3185
3186 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3187
3188 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
3189 break;
3190 default:
3191 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3192 return -EINVAL;
3193 }
3194
3195 return 0;
3196 }
3197
radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device * rdev,u16 * vddc,u16 * vddci,u16 virtual_voltage_id,u16 vbios_voltage_id)3198 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3199 u16 *vddc, u16 *vddci,
3200 u16 virtual_voltage_id,
3201 u16 vbios_voltage_id)
3202 {
3203 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
3204 u8 frev, crev;
3205 u16 data_offset, size;
3206 int i, j;
3207 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
3208 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
3209
3210 *vddc = 0;
3211 *vddci = 0;
3212
3213 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3214 &frev, &crev, &data_offset))
3215 return -EINVAL;
3216
3217 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
3218 (rdev->mode_info.atom_context->bios + data_offset);
3219
3220 switch (frev) {
3221 case 1:
3222 return -EINVAL;
3223 case 2:
3224 switch (crev) {
3225 case 1:
3226 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
3227 return -EINVAL;
3228 leakage_bin = (u16 *)
3229 (rdev->mode_info.atom_context->bios + data_offset +
3230 le16_to_cpu(profile->usLeakageBinArrayOffset));
3231 vddc_id_buf = (u16 *)
3232 (rdev->mode_info.atom_context->bios + data_offset +
3233 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
3234 vddc_buf = (u16 *)
3235 (rdev->mode_info.atom_context->bios + data_offset +
3236 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
3237 vddci_id_buf = (u16 *)
3238 (rdev->mode_info.atom_context->bios + data_offset +
3239 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
3240 vddci_buf = (u16 *)
3241 (rdev->mode_info.atom_context->bios + data_offset +
3242 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
3243
3244 if (profile->ucElbVDDC_Num > 0) {
3245 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
3246 if (vddc_id_buf[i] == virtual_voltage_id) {
3247 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3248 if (vbios_voltage_id <= leakage_bin[j]) {
3249 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
3250 break;
3251 }
3252 }
3253 break;
3254 }
3255 }
3256 }
3257 if (profile->ucElbVDDCI_Num > 0) {
3258 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
3259 if (vddci_id_buf[i] == virtual_voltage_id) {
3260 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3261 if (vbios_voltage_id <= leakage_bin[j]) {
3262 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
3263 break;
3264 }
3265 }
3266 break;
3267 }
3268 }
3269 }
3270 break;
3271 default:
3272 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3273 return -EINVAL;
3274 }
3275 break;
3276 default:
3277 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3278 return -EINVAL;
3279 }
3280
3281 return 0;
3282 }
3283
3284 union get_voltage_info {
3285 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
3286 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
3287 };
3288
radeon_atom_get_voltage_evv(struct radeon_device * rdev,u16 virtual_voltage_id,u16 * voltage)3289 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
3290 u16 virtual_voltage_id,
3291 u16 *voltage)
3292 {
3293 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
3294 u32 entry_id;
3295 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
3296 union get_voltage_info args;
3297
3298 for (entry_id = 0; entry_id < count; entry_id++) {
3299 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
3300 virtual_voltage_id)
3301 break;
3302 }
3303
3304 if (entry_id >= count)
3305 return -EINVAL;
3306
3307 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
3308 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
3309 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
3310 args.in.ulSCLKFreq =
3311 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
3312
3313 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3314
3315 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
3316
3317 return 0;
3318 }
3319
radeon_atom_get_voltage_gpio_settings(struct radeon_device * rdev,u16 voltage_level,u8 voltage_type,u32 * gpio_value,u32 * gpio_mask)3320 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3321 u16 voltage_level, u8 voltage_type,
3322 u32 *gpio_value, u32 *gpio_mask)
3323 {
3324 union set_voltage args;
3325 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3326 u8 frev, crev;
3327
3328 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3329 return -EINVAL;
3330
3331 switch (crev) {
3332 case 1:
3333 return -EINVAL;
3334 case 2:
3335 args.v2.ucVoltageType = voltage_type;
3336 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3337 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3338
3339 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3340
3341 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3342
3343 args.v2.ucVoltageType = voltage_type;
3344 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3345 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3346
3347 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3348
3349 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3350 break;
3351 default:
3352 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3353 return -EINVAL;
3354 }
3355
3356 return 0;
3357 }
3358
3359 union voltage_object_info {
3360 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3361 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3362 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3363 };
3364
3365 union voltage_object {
3366 struct _ATOM_VOLTAGE_OBJECT v1;
3367 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3368 union _ATOM_VOLTAGE_OBJECT_V3 v3;
3369 };
3370
atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO * v1,u8 voltage_type)3371 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3372 u8 voltage_type)
3373 {
3374 u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3375 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3376 u8 *start = (u8 *)v1;
3377
3378 while (offset < size) {
3379 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3380 if (vo->ucVoltageType == voltage_type)
3381 return vo;
3382 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3383 vo->asFormula.ucNumOfVoltageEntries;
3384 }
3385 return NULL;
3386 }
3387
atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 * v2,u8 voltage_type)3388 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3389 u8 voltage_type)
3390 {
3391 u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3392 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3393 u8 *start = (u8*)v2;
3394
3395 while (offset < size) {
3396 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3397 if (vo->ucVoltageType == voltage_type)
3398 return vo;
3399 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3400 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3401 }
3402 return NULL;
3403 }
3404
atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 * v3,u8 voltage_type,u8 voltage_mode)3405 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3406 u8 voltage_type, u8 voltage_mode)
3407 {
3408 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3409 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3410 u8 *start = (u8*)v3;
3411
3412 while (offset < size) {
3413 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3414 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3415 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3416 return vo;
3417 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3418 }
3419 return NULL;
3420 }
3421
3422 bool
radeon_atom_is_voltage_gpio(struct radeon_device * rdev,u8 voltage_type,u8 voltage_mode)3423 radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3424 u8 voltage_type, u8 voltage_mode)
3425 {
3426 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3427 u8 frev, crev;
3428 u16 data_offset, size;
3429 union voltage_object_info *voltage_info;
3430 union voltage_object *voltage_object = NULL;
3431
3432 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3433 &frev, &crev, &data_offset)) {
3434 voltage_info = (union voltage_object_info *)
3435 (rdev->mode_info.atom_context->bios + data_offset);
3436
3437 switch (frev) {
3438 case 1:
3439 case 2:
3440 switch (crev) {
3441 case 1:
3442 voltage_object = (union voltage_object *)
3443 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3444 if (voltage_object &&
3445 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3446 return true;
3447 break;
3448 case 2:
3449 voltage_object = (union voltage_object *)
3450 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3451 if (voltage_object &&
3452 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3453 return true;
3454 break;
3455 default:
3456 DRM_ERROR("unknown voltage object table\n");
3457 return false;
3458 }
3459 break;
3460 case 3:
3461 switch (crev) {
3462 case 1:
3463 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3464 voltage_type, voltage_mode))
3465 return true;
3466 break;
3467 default:
3468 DRM_ERROR("unknown voltage object table\n");
3469 return false;
3470 }
3471 break;
3472 default:
3473 DRM_ERROR("unknown voltage object table\n");
3474 return false;
3475 }
3476
3477 }
3478 return false;
3479 }
3480
radeon_atom_get_svi2_info(struct radeon_device * rdev,u8 voltage_type,u8 * svd_gpio_id,u8 * svc_gpio_id)3481 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
3482 u8 voltage_type,
3483 u8 *svd_gpio_id, u8 *svc_gpio_id)
3484 {
3485 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3486 u8 frev, crev;
3487 u16 data_offset, size;
3488 union voltage_object_info *voltage_info;
3489 union voltage_object *voltage_object = NULL;
3490
3491 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3492 &frev, &crev, &data_offset)) {
3493 voltage_info = (union voltage_object_info *)
3494 (rdev->mode_info.atom_context->bios + data_offset);
3495
3496 switch (frev) {
3497 case 3:
3498 switch (crev) {
3499 case 1:
3500 voltage_object = (union voltage_object *)
3501 atom_lookup_voltage_object_v3(&voltage_info->v3,
3502 voltage_type,
3503 VOLTAGE_OBJ_SVID2);
3504 if (voltage_object) {
3505 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
3506 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
3507 } else {
3508 return -EINVAL;
3509 }
3510 break;
3511 default:
3512 DRM_ERROR("unknown voltage object table\n");
3513 return -EINVAL;
3514 }
3515 break;
3516 default:
3517 DRM_ERROR("unknown voltage object table\n");
3518 return -EINVAL;
3519 }
3520
3521 }
3522 return 0;
3523 }
3524
radeon_atom_get_max_voltage(struct radeon_device * rdev,u8 voltage_type,u16 * max_voltage)3525 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3526 u8 voltage_type, u16 *max_voltage)
3527 {
3528 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3529 u8 frev, crev;
3530 u16 data_offset, size;
3531 union voltage_object_info *voltage_info;
3532 union voltage_object *voltage_object = NULL;
3533
3534 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3535 &frev, &crev, &data_offset)) {
3536 voltage_info = (union voltage_object_info *)
3537 (rdev->mode_info.atom_context->bios + data_offset);
3538
3539 switch (crev) {
3540 case 1:
3541 voltage_object = (union voltage_object *)
3542 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3543 if (voltage_object) {
3544 ATOM_VOLTAGE_FORMULA *formula =
3545 &voltage_object->v1.asFormula;
3546 if (formula->ucFlag & 1)
3547 *max_voltage =
3548 le16_to_cpu(formula->usVoltageBaseLevel) +
3549 formula->ucNumOfVoltageEntries / 2 *
3550 le16_to_cpu(formula->usVoltageStep);
3551 else
3552 *max_voltage =
3553 le16_to_cpu(formula->usVoltageBaseLevel) +
3554 (formula->ucNumOfVoltageEntries - 1) *
3555 le16_to_cpu(formula->usVoltageStep);
3556 return 0;
3557 }
3558 break;
3559 case 2:
3560 voltage_object = (union voltage_object *)
3561 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3562 if (voltage_object) {
3563 ATOM_VOLTAGE_FORMULA_V2 *formula =
3564 &voltage_object->v2.asFormula;
3565 if (formula->ucNumOfVoltageEntries) {
3566 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *)
3567 ((u8 *)&formula->asVIDAdjustEntries[0] +
3568 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
3569 *max_voltage =
3570 le16_to_cpu(lut->usVoltageValue);
3571 return 0;
3572 }
3573 }
3574 break;
3575 default:
3576 DRM_ERROR("unknown voltage object table\n");
3577 return -EINVAL;
3578 }
3579
3580 }
3581 return -EINVAL;
3582 }
3583
radeon_atom_get_min_voltage(struct radeon_device * rdev,u8 voltage_type,u16 * min_voltage)3584 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3585 u8 voltage_type, u16 *min_voltage)
3586 {
3587 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3588 u8 frev, crev;
3589 u16 data_offset, size;
3590 union voltage_object_info *voltage_info;
3591 union voltage_object *voltage_object = NULL;
3592
3593 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3594 &frev, &crev, &data_offset)) {
3595 voltage_info = (union voltage_object_info *)
3596 (rdev->mode_info.atom_context->bios + data_offset);
3597
3598 switch (crev) {
3599 case 1:
3600 voltage_object = (union voltage_object *)
3601 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3602 if (voltage_object) {
3603 ATOM_VOLTAGE_FORMULA *formula =
3604 &voltage_object->v1.asFormula;
3605 *min_voltage =
3606 le16_to_cpu(formula->usVoltageBaseLevel);
3607 return 0;
3608 }
3609 break;
3610 case 2:
3611 voltage_object = (union voltage_object *)
3612 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3613 if (voltage_object) {
3614 ATOM_VOLTAGE_FORMULA_V2 *formula =
3615 &voltage_object->v2.asFormula;
3616 if (formula->ucNumOfVoltageEntries) {
3617 *min_voltage =
3618 le16_to_cpu(formula->asVIDAdjustEntries[
3619 0
3620 ].usVoltageValue);
3621 return 0;
3622 }
3623 }
3624 break;
3625 default:
3626 DRM_ERROR("unknown voltage object table\n");
3627 return -EINVAL;
3628 }
3629
3630 }
3631 return -EINVAL;
3632 }
3633
radeon_atom_get_voltage_step(struct radeon_device * rdev,u8 voltage_type,u16 * voltage_step)3634 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3635 u8 voltage_type, u16 *voltage_step)
3636 {
3637 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3638 u8 frev, crev;
3639 u16 data_offset, size;
3640 union voltage_object_info *voltage_info;
3641 union voltage_object *voltage_object = NULL;
3642
3643 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3644 &frev, &crev, &data_offset)) {
3645 voltage_info = (union voltage_object_info *)
3646 (rdev->mode_info.atom_context->bios + data_offset);
3647
3648 switch (crev) {
3649 case 1:
3650 voltage_object = (union voltage_object *)
3651 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3652 if (voltage_object) {
3653 ATOM_VOLTAGE_FORMULA *formula =
3654 &voltage_object->v1.asFormula;
3655 if (formula->ucFlag & 1)
3656 *voltage_step =
3657 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3658 else
3659 *voltage_step =
3660 le16_to_cpu(formula->usVoltageStep);
3661 return 0;
3662 }
3663 break;
3664 case 2:
3665 return -EINVAL;
3666 default:
3667 DRM_ERROR("unknown voltage object table\n");
3668 return -EINVAL;
3669 }
3670
3671 }
3672 return -EINVAL;
3673 }
3674
radeon_atom_round_to_true_voltage(struct radeon_device * rdev,u8 voltage_type,u16 nominal_voltage,u16 * true_voltage)3675 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3676 u8 voltage_type,
3677 u16 nominal_voltage,
3678 u16 *true_voltage)
3679 {
3680 u16 min_voltage, max_voltage, voltage_step;
3681
3682 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3683 return -EINVAL;
3684 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3685 return -EINVAL;
3686 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3687 return -EINVAL;
3688
3689 if (nominal_voltage <= min_voltage)
3690 *true_voltage = min_voltage;
3691 else if (nominal_voltage >= max_voltage)
3692 *true_voltage = max_voltage;
3693 else
3694 *true_voltage = min_voltage +
3695 ((nominal_voltage - min_voltage) / voltage_step) *
3696 voltage_step;
3697
3698 return 0;
3699 }
3700
radeon_atom_get_voltage_table(struct radeon_device * rdev,u8 voltage_type,u8 voltage_mode,struct atom_voltage_table * voltage_table)3701 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3702 u8 voltage_type, u8 voltage_mode,
3703 struct atom_voltage_table *voltage_table)
3704 {
3705 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3706 u8 frev, crev;
3707 u16 data_offset, size;
3708 int i, ret;
3709 union voltage_object_info *voltage_info;
3710 union voltage_object *voltage_object = NULL;
3711
3712 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3713 &frev, &crev, &data_offset)) {
3714 voltage_info = (union voltage_object_info *)
3715 (rdev->mode_info.atom_context->bios + data_offset);
3716
3717 switch (frev) {
3718 case 1:
3719 case 2:
3720 switch (crev) {
3721 case 1:
3722 DRM_ERROR("old table version %d, %d\n", frev, crev);
3723 return -EINVAL;
3724 case 2:
3725 voltage_object = (union voltage_object *)
3726 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3727 if (voltage_object) {
3728 ATOM_VOLTAGE_FORMULA_V2 *formula =
3729 &voltage_object->v2.asFormula;
3730 VOLTAGE_LUT_ENTRY *lut;
3731 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3732 return -EINVAL;
3733 lut = &formula->asVIDAdjustEntries[0];
3734 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3735 voltage_table->entries[i].value =
3736 le16_to_cpu(lut->usVoltageValue);
3737 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3738 voltage_table->entries[i].value,
3739 voltage_type,
3740 &voltage_table->entries[i].smio_low,
3741 &voltage_table->mask_low);
3742 if (ret)
3743 return ret;
3744 lut = (VOLTAGE_LUT_ENTRY *)
3745 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
3746 }
3747 voltage_table->count = formula->ucNumOfVoltageEntries;
3748 return 0;
3749 }
3750 break;
3751 default:
3752 DRM_ERROR("unknown voltage object table\n");
3753 return -EINVAL;
3754 }
3755 break;
3756 case 3:
3757 switch (crev) {
3758 case 1:
3759 voltage_object = (union voltage_object *)
3760 atom_lookup_voltage_object_v3(&voltage_info->v3,
3761 voltage_type, voltage_mode);
3762 if (voltage_object) {
3763 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3764 &voltage_object->v3.asGpioVoltageObj;
3765 VOLTAGE_LUT_ENTRY_V2 *lut;
3766 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3767 return -EINVAL;
3768 lut = &gpio->asVolGpioLut[0];
3769 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3770 voltage_table->entries[i].value =
3771 le16_to_cpu(lut->usVoltageValue);
3772 voltage_table->entries[i].smio_low =
3773 le32_to_cpu(lut->ulVoltageId);
3774 lut = (VOLTAGE_LUT_ENTRY_V2 *)
3775 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
3776 }
3777 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3778 voltage_table->count = gpio->ucGpioEntryNum;
3779 voltage_table->phase_delay = gpio->ucPhaseDelay;
3780 return 0;
3781 }
3782 break;
3783 default:
3784 DRM_ERROR("unknown voltage object table\n");
3785 return -EINVAL;
3786 }
3787 break;
3788 default:
3789 DRM_ERROR("unknown voltage object table\n");
3790 return -EINVAL;
3791 }
3792 }
3793 return -EINVAL;
3794 }
3795
3796 union vram_info {
3797 struct _ATOM_VRAM_INFO_V3 v1_3;
3798 struct _ATOM_VRAM_INFO_V4 v1_4;
3799 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3800 };
3801
radeon_atom_get_memory_info(struct radeon_device * rdev,u8 module_index,struct atom_memory_info * mem_info)3802 int radeon_atom_get_memory_info(struct radeon_device *rdev,
3803 u8 module_index, struct atom_memory_info *mem_info)
3804 {
3805 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3806 u8 frev, crev, i;
3807 u16 data_offset, size;
3808 union vram_info *vram_info;
3809
3810 memset(mem_info, 0, sizeof(struct atom_memory_info));
3811
3812 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3813 &frev, &crev, &data_offset)) {
3814 vram_info = (union vram_info *)
3815 (rdev->mode_info.atom_context->bios + data_offset);
3816 switch (frev) {
3817 case 1:
3818 switch (crev) {
3819 case 3:
3820 /* r6xx */
3821 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3822 ATOM_VRAM_MODULE_V3 *vram_module =
3823 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3824
3825 for (i = 0; i < module_index; i++) {
3826 if (le16_to_cpu(vram_module->usSize) == 0)
3827 return -EINVAL;
3828 vram_module = (ATOM_VRAM_MODULE_V3 *)
3829 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3830 }
3831 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3832 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3833 } else
3834 return -EINVAL;
3835 break;
3836 case 4:
3837 /* r7xx, evergreen */
3838 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3839 ATOM_VRAM_MODULE_V4 *vram_module =
3840 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3841
3842 for (i = 0; i < module_index; i++) {
3843 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3844 return -EINVAL;
3845 vram_module = (ATOM_VRAM_MODULE_V4 *)
3846 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3847 }
3848 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3849 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3850 } else
3851 return -EINVAL;
3852 break;
3853 default:
3854 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3855 return -EINVAL;
3856 }
3857 break;
3858 case 2:
3859 switch (crev) {
3860 case 1:
3861 /* ni */
3862 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3863 ATOM_VRAM_MODULE_V7 *vram_module =
3864 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3865
3866 for (i = 0; i < module_index; i++) {
3867 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3868 return -EINVAL;
3869 vram_module = (ATOM_VRAM_MODULE_V7 *)
3870 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3871 }
3872 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3873 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3874 } else
3875 return -EINVAL;
3876 break;
3877 default:
3878 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3879 return -EINVAL;
3880 }
3881 break;
3882 default:
3883 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3884 return -EINVAL;
3885 }
3886 return 0;
3887 }
3888 return -EINVAL;
3889 }
3890
radeon_atom_get_mclk_range_table(struct radeon_device * rdev,bool gddr5,u8 module_index,struct atom_memory_clock_range_table * mclk_range_table)3891 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3892 bool gddr5, u8 module_index,
3893 struct atom_memory_clock_range_table *mclk_range_table)
3894 {
3895 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3896 u8 frev, crev, i;
3897 u16 data_offset, size;
3898 union vram_info *vram_info;
3899 u32 mem_timing_size = gddr5 ?
3900 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3901
3902 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3903
3904 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3905 &frev, &crev, &data_offset)) {
3906 vram_info = (union vram_info *)
3907 (rdev->mode_info.atom_context->bios + data_offset);
3908 switch (frev) {
3909 case 1:
3910 switch (crev) {
3911 case 3:
3912 DRM_ERROR("old table version %d, %d\n", frev, crev);
3913 return -EINVAL;
3914 case 4:
3915 /* r7xx, evergreen */
3916 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3917 ATOM_VRAM_MODULE_V4 *vram_module =
3918 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3919 ATOM_MEMORY_TIMING_FORMAT *format;
3920
3921 for (i = 0; i < module_index; i++) {
3922 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3923 return -EINVAL;
3924 vram_module = (ATOM_VRAM_MODULE_V4 *)
3925 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3926 }
3927 mclk_range_table->num_entries = (u8)
3928 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3929 mem_timing_size);
3930 format = &vram_module->asMemTiming[0];
3931 for (i = 0; i < mclk_range_table->num_entries; i++) {
3932 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3933 format = (ATOM_MEMORY_TIMING_FORMAT *)
3934 ((u8 *)format + mem_timing_size);
3935 }
3936 } else
3937 return -EINVAL;
3938 break;
3939 default:
3940 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3941 return -EINVAL;
3942 }
3943 break;
3944 case 2:
3945 DRM_ERROR("new table version %d, %d\n", frev, crev);
3946 return -EINVAL;
3947 default:
3948 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3949 return -EINVAL;
3950 }
3951 return 0;
3952 }
3953 return -EINVAL;
3954 }
3955
3956 #define MEM_ID_MASK 0xff000000
3957 #define MEM_ID_SHIFT 24
3958 #define CLOCK_RANGE_MASK 0x00ffffff
3959 #define CLOCK_RANGE_SHIFT 0
3960 #define LOW_NIBBLE_MASK 0xf
3961 #define DATA_EQU_PREV 0
3962 #define DATA_FROM_TABLE 4
3963
radeon_atom_init_mc_reg_table(struct radeon_device * rdev,u8 module_index,struct atom_mc_reg_table * reg_table)3964 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3965 u8 module_index,
3966 struct atom_mc_reg_table *reg_table)
3967 {
3968 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3969 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3970 u32 i = 0, j;
3971 u16 data_offset, size;
3972 union vram_info *vram_info;
3973
3974 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
3975
3976 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3977 &frev, &crev, &data_offset)) {
3978 vram_info = (union vram_info *)
3979 (rdev->mode_info.atom_context->bios + data_offset);
3980 switch (frev) {
3981 case 1:
3982 DRM_ERROR("old table version %d, %d\n", frev, crev);
3983 return -EINVAL;
3984 case 2:
3985 switch (crev) {
3986 case 1:
3987 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3988 ATOM_INIT_REG_BLOCK *reg_block =
3989 (ATOM_INIT_REG_BLOCK *)
3990 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
3991 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
3992 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
3993 ((u8 *)reg_block + (2 * sizeof(u16)) +
3994 le16_to_cpu(reg_block->usRegIndexTblSize));
3995 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
3996 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
3997 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
3998 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
3999 return -EINVAL;
4000 while (i < num_entries) {
4001 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
4002 break;
4003 reg_table->mc_reg_address[i].s1 =
4004 (u16)(le16_to_cpu(format->usRegIndex));
4005 reg_table->mc_reg_address[i].pre_reg_data =
4006 (u8)(format->ucPreRegDataLength);
4007 i++;
4008 format = (ATOM_INIT_REG_INDEX_FORMAT *)
4009 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
4010 }
4011 reg_table->last = i;
4012 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
4013 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
4014 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
4015 >> MEM_ID_SHIFT);
4016 if (module_index == t_mem_id) {
4017 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
4018 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
4019 >> CLOCK_RANGE_SHIFT);
4020 for (i = 0, j = 1; i < reg_table->last; i++) {
4021 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
4022 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4023 (u32)le32_to_cpu(*((u32 *)reg_data + j));
4024 j++;
4025 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
4026 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4027 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
4028 }
4029 }
4030 num_ranges++;
4031 }
4032 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4033 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
4034 }
4035 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
4036 return -EINVAL;
4037 reg_table->num_entries = num_ranges;
4038 } else
4039 return -EINVAL;
4040 break;
4041 default:
4042 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4043 return -EINVAL;
4044 }
4045 break;
4046 default:
4047 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4048 return -EINVAL;
4049 }
4050 return 0;
4051 }
4052 return -EINVAL;
4053 }
4054
radeon_atom_initialize_bios_scratch_regs(struct drm_device * dev)4055 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
4056 {
4057 struct radeon_device *rdev = dev->dev_private;
4058 uint32_t bios_2_scratch, bios_6_scratch;
4059
4060 if (rdev->family >= CHIP_R600) {
4061 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4062 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4063 } else {
4064 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4065 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4066 }
4067
4068 /* let the bios control the backlight */
4069 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
4070
4071 /* tell the bios not to handle mode switching */
4072 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
4073
4074 /* clear the vbios dpms state */
4075 if (ASIC_IS_DCE4(rdev))
4076 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
4077
4078 if (rdev->family >= CHIP_R600) {
4079 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4080 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4081 } else {
4082 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4083 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4084 }
4085
4086 }
4087
radeon_save_bios_scratch_regs(struct radeon_device * rdev)4088 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
4089 {
4090 uint32_t scratch_reg;
4091 int i;
4092
4093 if (rdev->family >= CHIP_R600)
4094 scratch_reg = R600_BIOS_0_SCRATCH;
4095 else
4096 scratch_reg = RADEON_BIOS_0_SCRATCH;
4097
4098 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4099 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
4100 }
4101
radeon_restore_bios_scratch_regs(struct radeon_device * rdev)4102 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
4103 {
4104 uint32_t scratch_reg;
4105 int i;
4106
4107 if (rdev->family >= CHIP_R600)
4108 scratch_reg = R600_BIOS_0_SCRATCH;
4109 else
4110 scratch_reg = RADEON_BIOS_0_SCRATCH;
4111
4112 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4113 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
4114 }
4115
radeon_atom_output_lock(struct drm_encoder * encoder,bool lock)4116 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
4117 {
4118 struct drm_device *dev = encoder->dev;
4119 struct radeon_device *rdev = dev->dev_private;
4120 uint32_t bios_6_scratch;
4121
4122 if (rdev->family >= CHIP_R600)
4123 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4124 else
4125 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4126
4127 if (lock) {
4128 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
4129 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
4130 } else {
4131 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
4132 bios_6_scratch |= ATOM_S6_ACC_MODE;
4133 }
4134
4135 if (rdev->family >= CHIP_R600)
4136 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4137 else
4138 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4139 }
4140
4141 /* at some point we may want to break this out into individual functions */
4142 void
radeon_atombios_connected_scratch_regs(struct drm_connector * connector,struct drm_encoder * encoder,bool connected)4143 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
4144 struct drm_encoder *encoder,
4145 bool connected)
4146 {
4147 struct drm_device *dev = connector->dev;
4148 struct radeon_device *rdev = dev->dev_private;
4149 struct radeon_connector *radeon_connector =
4150 to_radeon_connector(connector);
4151 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4152 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
4153
4154 if (rdev->family >= CHIP_R600) {
4155 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
4156 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4157 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4158 } else {
4159 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
4160 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4161 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4162 }
4163
4164 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
4165 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
4166 if (connected) {
4167 DRM_DEBUG_KMS("TV1 connected\n");
4168 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
4169 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
4170 } else {
4171 DRM_DEBUG_KMS("TV1 disconnected\n");
4172 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
4173 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
4174 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
4175 }
4176 }
4177 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
4178 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
4179 if (connected) {
4180 DRM_DEBUG_KMS("CV connected\n");
4181 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
4182 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
4183 } else {
4184 DRM_DEBUG_KMS("CV disconnected\n");
4185 bios_0_scratch &= ~ATOM_S0_CV_MASK;
4186 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
4187 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
4188 }
4189 }
4190 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
4191 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
4192 if (connected) {
4193 DRM_DEBUG_KMS("LCD1 connected\n");
4194 bios_0_scratch |= ATOM_S0_LCD1;
4195 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
4196 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
4197 } else {
4198 DRM_DEBUG_KMS("LCD1 disconnected\n");
4199 bios_0_scratch &= ~ATOM_S0_LCD1;
4200 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
4201 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
4202 }
4203 }
4204 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
4205 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
4206 if (connected) {
4207 DRM_DEBUG_KMS("CRT1 connected\n");
4208 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
4209 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
4210 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
4211 } else {
4212 DRM_DEBUG_KMS("CRT1 disconnected\n");
4213 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
4214 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
4215 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
4216 }
4217 }
4218 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
4219 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
4220 if (connected) {
4221 DRM_DEBUG_KMS("CRT2 connected\n");
4222 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
4223 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
4224 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
4225 } else {
4226 DRM_DEBUG_KMS("CRT2 disconnected\n");
4227 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
4228 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
4229 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
4230 }
4231 }
4232 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
4233 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
4234 if (connected) {
4235 DRM_DEBUG_KMS("DFP1 connected\n");
4236 bios_0_scratch |= ATOM_S0_DFP1;
4237 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
4238 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
4239 } else {
4240 DRM_DEBUG_KMS("DFP1 disconnected\n");
4241 bios_0_scratch &= ~ATOM_S0_DFP1;
4242 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
4243 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
4244 }
4245 }
4246 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
4247 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
4248 if (connected) {
4249 DRM_DEBUG_KMS("DFP2 connected\n");
4250 bios_0_scratch |= ATOM_S0_DFP2;
4251 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
4252 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
4253 } else {
4254 DRM_DEBUG_KMS("DFP2 disconnected\n");
4255 bios_0_scratch &= ~ATOM_S0_DFP2;
4256 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
4257 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
4258 }
4259 }
4260 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
4261 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
4262 if (connected) {
4263 DRM_DEBUG_KMS("DFP3 connected\n");
4264 bios_0_scratch |= ATOM_S0_DFP3;
4265 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
4266 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
4267 } else {
4268 DRM_DEBUG_KMS("DFP3 disconnected\n");
4269 bios_0_scratch &= ~ATOM_S0_DFP3;
4270 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
4271 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
4272 }
4273 }
4274 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
4275 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
4276 if (connected) {
4277 DRM_DEBUG_KMS("DFP4 connected\n");
4278 bios_0_scratch |= ATOM_S0_DFP4;
4279 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
4280 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
4281 } else {
4282 DRM_DEBUG_KMS("DFP4 disconnected\n");
4283 bios_0_scratch &= ~ATOM_S0_DFP4;
4284 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
4285 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
4286 }
4287 }
4288 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
4289 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
4290 if (connected) {
4291 DRM_DEBUG_KMS("DFP5 connected\n");
4292 bios_0_scratch |= ATOM_S0_DFP5;
4293 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
4294 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
4295 } else {
4296 DRM_DEBUG_KMS("DFP5 disconnected\n");
4297 bios_0_scratch &= ~ATOM_S0_DFP5;
4298 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
4299 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
4300 }
4301 }
4302 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4303 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4304 if (connected) {
4305 DRM_DEBUG_KMS("DFP6 connected\n");
4306 bios_0_scratch |= ATOM_S0_DFP6;
4307 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4308 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4309 } else {
4310 DRM_DEBUG_KMS("DFP6 disconnected\n");
4311 bios_0_scratch &= ~ATOM_S0_DFP6;
4312 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4313 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4314 }
4315 }
4316
4317 if (rdev->family >= CHIP_R600) {
4318 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4319 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4320 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4321 } else {
4322 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4323 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4324 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4325 }
4326 }
4327
4328 void
radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder * encoder,int crtc)4329 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4330 {
4331 struct drm_device *dev = encoder->dev;
4332 struct radeon_device *rdev = dev->dev_private;
4333 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4334 uint32_t bios_3_scratch;
4335
4336 if (ASIC_IS_DCE4(rdev))
4337 return;
4338
4339 if (rdev->family >= CHIP_R600)
4340 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4341 else
4342 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4343
4344 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4345 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4346 bios_3_scratch |= (crtc << 18);
4347 }
4348 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4349 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4350 bios_3_scratch |= (crtc << 24);
4351 }
4352 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4353 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4354 bios_3_scratch |= (crtc << 16);
4355 }
4356 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4357 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4358 bios_3_scratch |= (crtc << 20);
4359 }
4360 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4361 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4362 bios_3_scratch |= (crtc << 17);
4363 }
4364 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4365 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4366 bios_3_scratch |= (crtc << 19);
4367 }
4368 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4369 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4370 bios_3_scratch |= (crtc << 23);
4371 }
4372 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4373 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4374 bios_3_scratch |= (crtc << 25);
4375 }
4376
4377 if (rdev->family >= CHIP_R600)
4378 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4379 else
4380 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4381 }
4382
4383 void
radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder * encoder,bool on)4384 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4385 {
4386 struct drm_device *dev = encoder->dev;
4387 struct radeon_device *rdev = dev->dev_private;
4388 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4389 uint32_t bios_2_scratch;
4390
4391 if (ASIC_IS_DCE4(rdev))
4392 return;
4393
4394 if (rdev->family >= CHIP_R600)
4395 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4396 else
4397 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4398
4399 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4400 if (on)
4401 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4402 else
4403 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4404 }
4405 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4406 if (on)
4407 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4408 else
4409 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4410 }
4411 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4412 if (on)
4413 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4414 else
4415 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4416 }
4417 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4418 if (on)
4419 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4420 else
4421 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4422 }
4423 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4424 if (on)
4425 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4426 else
4427 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4428 }
4429 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4430 if (on)
4431 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4432 else
4433 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4434 }
4435 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4436 if (on)
4437 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4438 else
4439 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4440 }
4441 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4442 if (on)
4443 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4444 else
4445 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4446 }
4447 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4448 if (on)
4449 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4450 else
4451 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4452 }
4453 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4454 if (on)
4455 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4456 else
4457 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4458 }
4459
4460 if (rdev->family >= CHIP_R600)
4461 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4462 else
4463 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4464 }
4465