1 /******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD$*/
34
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
37 #include "ixgbe_dcb.h"
38 #include "ixgbe_dcb_82599.h"
39 #include "ixgbe_api.h"
40
41 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
42 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
43 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
44 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
45 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
46 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
47 u16 count);
48 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
49 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
51 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
52
53 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
54 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
55 u16 *san_mac_offset);
56 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
57 u16 words, u16 *data);
58 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
59 u16 words, u16 *data);
60 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
61 u16 offset);
62
63 /**
64 * ixgbe_init_ops_generic - Inits function ptrs
65 * @hw: pointer to the hardware structure
66 *
67 * Initialize the function pointers.
68 **/
ixgbe_init_ops_generic(struct ixgbe_hw * hw)69 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
70 {
71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
72 struct ixgbe_mac_info *mac = &hw->mac;
73 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
74
75 DEBUGFUNC("ixgbe_init_ops_generic");
76
77 /* EEPROM */
78 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
79 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
80 if (eec & IXGBE_EEC_PRES) {
81 eeprom->ops.read = ixgbe_read_eerd_generic;
82 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
83 } else {
84 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
85 eeprom->ops.read_buffer =
86 ixgbe_read_eeprom_buffer_bit_bang_generic;
87 }
88 eeprom->ops.write = ixgbe_write_eeprom_generic;
89 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
90 eeprom->ops.validate_checksum =
91 ixgbe_validate_eeprom_checksum_generic;
92 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
93 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
94
95 /* MAC */
96 mac->ops.init_hw = ixgbe_init_hw_generic;
97 mac->ops.reset_hw = NULL;
98 mac->ops.start_hw = ixgbe_start_hw_generic;
99 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
100 mac->ops.get_media_type = NULL;
101 mac->ops.get_supported_physical_layer = NULL;
102 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
103 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
104 mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
105 mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
106 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
107 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
108 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
109 mac->ops.prot_autoc_read = prot_autoc_read_generic;
110 mac->ops.prot_autoc_write = prot_autoc_write_generic;
111
112 /* LEDs */
113 mac->ops.led_on = ixgbe_led_on_generic;
114 mac->ops.led_off = ixgbe_led_off_generic;
115 mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
116 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
117
118 /* RAR, Multicast, VLAN */
119 mac->ops.set_rar = ixgbe_set_rar_generic;
120 mac->ops.clear_rar = ixgbe_clear_rar_generic;
121 mac->ops.insert_mac_addr = NULL;
122 mac->ops.set_vmdq = NULL;
123 mac->ops.clear_vmdq = NULL;
124 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
125 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
126 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
127 mac->ops.enable_mc = ixgbe_enable_mc_generic;
128 mac->ops.disable_mc = ixgbe_disable_mc_generic;
129 mac->ops.clear_vfta = NULL;
130 mac->ops.set_vfta = NULL;
131 mac->ops.set_vlvf = NULL;
132 mac->ops.init_uta_tables = NULL;
133 mac->ops.enable_rx = ixgbe_enable_rx_generic;
134 mac->ops.disable_rx = ixgbe_disable_rx_generic;
135
136 /* Flow Control */
137 mac->ops.fc_enable = ixgbe_fc_enable_generic;
138 mac->ops.setup_fc = ixgbe_setup_fc_generic;
139
140 /* Link */
141 mac->ops.get_link_capabilities = NULL;
142 mac->ops.setup_link = NULL;
143 mac->ops.check_link = NULL;
144 mac->ops.dmac_config = NULL;
145 mac->ops.dmac_update_tcs = NULL;
146 mac->ops.dmac_config_tcs = NULL;
147
148 return IXGBE_SUCCESS;
149 }
150
151 /**
152 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
153 * of flow control
154 * @hw: pointer to hardware structure
155 *
156 * This function returns TRUE if the device supports flow control
157 * autonegotiation, and FALSE if it does not.
158 *
159 **/
ixgbe_device_supports_autoneg_fc(struct ixgbe_hw * hw)160 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
161 {
162 bool supported = FALSE;
163 ixgbe_link_speed speed;
164 bool link_up;
165
166 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
167
168 switch (hw->phy.media_type) {
169 case ixgbe_media_type_fiber_fixed:
170 case ixgbe_media_type_fiber_qsfp:
171 case ixgbe_media_type_fiber:
172 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
173 /* if link is down, assume supported */
174 if (link_up)
175 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
176 TRUE : FALSE;
177 else
178 supported = TRUE;
179 break;
180 case ixgbe_media_type_backplane:
181 supported = TRUE;
182 break;
183 case ixgbe_media_type_copper:
184 /* only some copper devices support flow control autoneg */
185 switch (hw->device_id) {
186 case IXGBE_DEV_ID_82599_T3_LOM:
187 case IXGBE_DEV_ID_X540T:
188 case IXGBE_DEV_ID_X540T1:
189 case IXGBE_DEV_ID_X540_BYPASS:
190 case IXGBE_DEV_ID_X550T:
191 case IXGBE_DEV_ID_X550EM_X_10G_T:
192 supported = TRUE;
193 break;
194 default:
195 supported = FALSE;
196 }
197 default:
198 break;
199 }
200
201 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
202 "Device %x does not support flow control autoneg",
203 hw->device_id);
204 return supported;
205 }
206
207 /**
208 * ixgbe_setup_fc_generic - Set up flow control
209 * @hw: pointer to hardware structure
210 *
211 * Called at init time to set up flow control.
212 **/
ixgbe_setup_fc_generic(struct ixgbe_hw * hw)213 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
214 {
215 s32 ret_val = IXGBE_SUCCESS;
216 u32 reg = 0, reg_bp = 0;
217 u16 reg_cu = 0;
218 bool locked = FALSE;
219
220 DEBUGFUNC("ixgbe_setup_fc_generic");
221
222 /* Validate the requested mode */
223 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
224 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
225 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
226 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
227 goto out;
228 }
229
230 /*
231 * 10gig parts do not have a word in the EEPROM to determine the
232 * default flow control setting, so we explicitly set it to full.
233 */
234 if (hw->fc.requested_mode == ixgbe_fc_default)
235 hw->fc.requested_mode = ixgbe_fc_full;
236
237 /*
238 * Set up the 1G and 10G flow control advertisement registers so the
239 * HW will be able to do fc autoneg once the cable is plugged in. If
240 * we link at 10G, the 1G advertisement is harmless and vice versa.
241 */
242 switch (hw->phy.media_type) {
243 case ixgbe_media_type_backplane:
244 /* some MAC's need RMW protection on AUTOC */
245 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
246 if (ret_val != IXGBE_SUCCESS)
247 goto out;
248
249 /* only backplane uses autoc so fall though */
250 case ixgbe_media_type_fiber_fixed:
251 case ixgbe_media_type_fiber_qsfp:
252 case ixgbe_media_type_fiber:
253 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
254
255 break;
256 case ixgbe_media_type_copper:
257 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
258 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
259 break;
260 default:
261 break;
262 }
263
264 /*
265 * The possible values of fc.requested_mode are:
266 * 0: Flow control is completely disabled
267 * 1: Rx flow control is enabled (we can receive pause frames,
268 * but not send pause frames).
269 * 2: Tx flow control is enabled (we can send pause frames but
270 * we do not support receiving pause frames).
271 * 3: Both Rx and Tx flow control (symmetric) are enabled.
272 * other: Invalid.
273 */
274 switch (hw->fc.requested_mode) {
275 case ixgbe_fc_none:
276 /* Flow control completely disabled by software override. */
277 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
278 if (hw->phy.media_type == ixgbe_media_type_backplane)
279 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
280 IXGBE_AUTOC_ASM_PAUSE);
281 else if (hw->phy.media_type == ixgbe_media_type_copper)
282 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
283 break;
284 case ixgbe_fc_tx_pause:
285 /*
286 * Tx Flow control is enabled, and Rx Flow control is
287 * disabled by software override.
288 */
289 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
290 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
291 if (hw->phy.media_type == ixgbe_media_type_backplane) {
292 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
293 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
294 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
295 reg_cu |= IXGBE_TAF_ASM_PAUSE;
296 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
297 }
298 break;
299 case ixgbe_fc_rx_pause:
300 /*
301 * Rx Flow control is enabled and Tx Flow control is
302 * disabled by software override. Since there really
303 * isn't a way to advertise that we are capable of RX
304 * Pause ONLY, we will advertise that we support both
305 * symmetric and asymmetric Rx PAUSE, as such we fall
306 * through to the fc_full statement. Later, we will
307 * disable the adapter's ability to send PAUSE frames.
308 */
309 case ixgbe_fc_full:
310 /* Flow control (both Rx and Tx) is enabled by SW override. */
311 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
312 if (hw->phy.media_type == ixgbe_media_type_backplane)
313 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
314 IXGBE_AUTOC_ASM_PAUSE;
315 else if (hw->phy.media_type == ixgbe_media_type_copper)
316 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
317 break;
318 default:
319 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
320 "Flow control param set incorrectly\n");
321 ret_val = IXGBE_ERR_CONFIG;
322 goto out;
323 break;
324 }
325
326 if (hw->mac.type < ixgbe_mac_X540) {
327 /*
328 * Enable auto-negotiation between the MAC & PHY;
329 * the MAC will advertise clause 37 flow control.
330 */
331 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
332 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
333
334 /* Disable AN timeout */
335 if (hw->fc.strict_ieee)
336 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
337
338 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
339 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
340 }
341
342 /*
343 * AUTOC restart handles negotiation of 1G and 10G on backplane
344 * and copper. There is no need to set the PCS1GCTL register.
345 *
346 */
347 if (hw->phy.media_type == ixgbe_media_type_backplane) {
348 reg_bp |= IXGBE_AUTOC_AN_RESTART;
349 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
350 if (ret_val)
351 goto out;
352 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
353 (ixgbe_device_supports_autoneg_fc(hw))) {
354 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
355 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
356 }
357
358 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
359 out:
360 return ret_val;
361 }
362
363 /**
364 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
365 * @hw: pointer to hardware structure
366 *
367 * Starts the hardware by filling the bus info structure and media type, clears
368 * all on chip counters, initializes receive address registers, multicast
369 * table, VLAN filter table, calls routine to set up link and flow control
370 * settings, and leaves transmit and receive units disabled and uninitialized
371 **/
ixgbe_start_hw_generic(struct ixgbe_hw * hw)372 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
373 {
374 s32 ret_val;
375 u32 ctrl_ext;
376
377 DEBUGFUNC("ixgbe_start_hw_generic");
378
379 /* Set the media type */
380 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
381
382 /* PHY ops initialization must be done in reset_hw() */
383
384 /* Clear the VLAN filter table */
385 hw->mac.ops.clear_vfta(hw);
386
387 /* Clear statistics registers */
388 hw->mac.ops.clear_hw_cntrs(hw);
389
390 /* Set No Snoop Disable */
391 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
392 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
393 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
394 IXGBE_WRITE_FLUSH(hw);
395
396 /* Setup flow control */
397 ret_val = ixgbe_setup_fc(hw);
398 if (ret_val != IXGBE_SUCCESS)
399 goto out;
400
401 /* Clear adapter stopped flag */
402 hw->adapter_stopped = FALSE;
403
404 out:
405 return ret_val;
406 }
407
408 /**
409 * ixgbe_start_hw_gen2 - Init sequence for common device family
410 * @hw: pointer to hw structure
411 *
412 * Performs the init sequence common to the second generation
413 * of 10 GbE devices.
414 * Devices in the second generation:
415 * 82599
416 * X540
417 **/
ixgbe_start_hw_gen2(struct ixgbe_hw * hw)418 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
419 {
420 u32 i;
421 u32 regval;
422
423 /* Clear the rate limiters */
424 for (i = 0; i < hw->mac.max_tx_queues; i++) {
425 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
426 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
427 }
428 IXGBE_WRITE_FLUSH(hw);
429
430 /* Disable relaxed ordering */
431 for (i = 0; i < hw->mac.max_tx_queues; i++) {
432 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
433 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
434 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
435 }
436
437 for (i = 0; i < hw->mac.max_rx_queues; i++) {
438 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
439 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
440 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
441 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
442 }
443
444 return IXGBE_SUCCESS;
445 }
446
447 /**
448 * ixgbe_init_hw_generic - Generic hardware initialization
449 * @hw: pointer to hardware structure
450 *
451 * Initialize the hardware by resetting the hardware, filling the bus info
452 * structure and media type, clears all on chip counters, initializes receive
453 * address registers, multicast table, VLAN filter table, calls routine to set
454 * up link and flow control settings, and leaves transmit and receive units
455 * disabled and uninitialized
456 **/
ixgbe_init_hw_generic(struct ixgbe_hw * hw)457 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
458 {
459 s32 status;
460
461 DEBUGFUNC("ixgbe_init_hw_generic");
462
463 /* Reset the hardware */
464 status = hw->mac.ops.reset_hw(hw);
465
466 if (status == IXGBE_SUCCESS) {
467 /* Start the HW */
468 status = hw->mac.ops.start_hw(hw);
469 }
470
471 return status;
472 }
473
474 /**
475 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
476 * @hw: pointer to hardware structure
477 *
478 * Clears all hardware statistics counters by reading them from the hardware
479 * Statistics counters are clear on read.
480 **/
ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw * hw)481 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
482 {
483 u16 i = 0;
484
485 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
486
487 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
488 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
489 IXGBE_READ_REG(hw, IXGBE_ERRBC);
490 IXGBE_READ_REG(hw, IXGBE_MSPDC);
491 for (i = 0; i < 8; i++)
492 IXGBE_READ_REG(hw, IXGBE_MPC(i));
493
494 IXGBE_READ_REG(hw, IXGBE_MLFC);
495 IXGBE_READ_REG(hw, IXGBE_MRFC);
496 IXGBE_READ_REG(hw, IXGBE_RLEC);
497 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
498 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
499 if (hw->mac.type >= ixgbe_mac_82599EB) {
500 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
501 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
502 } else {
503 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
504 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
505 }
506
507 for (i = 0; i < 8; i++) {
508 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
509 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
510 if (hw->mac.type >= ixgbe_mac_82599EB) {
511 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
512 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
513 } else {
514 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
515 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
516 }
517 }
518 if (hw->mac.type >= ixgbe_mac_82599EB)
519 for (i = 0; i < 8; i++)
520 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
521 IXGBE_READ_REG(hw, IXGBE_PRC64);
522 IXGBE_READ_REG(hw, IXGBE_PRC127);
523 IXGBE_READ_REG(hw, IXGBE_PRC255);
524 IXGBE_READ_REG(hw, IXGBE_PRC511);
525 IXGBE_READ_REG(hw, IXGBE_PRC1023);
526 IXGBE_READ_REG(hw, IXGBE_PRC1522);
527 IXGBE_READ_REG(hw, IXGBE_GPRC);
528 IXGBE_READ_REG(hw, IXGBE_BPRC);
529 IXGBE_READ_REG(hw, IXGBE_MPRC);
530 IXGBE_READ_REG(hw, IXGBE_GPTC);
531 IXGBE_READ_REG(hw, IXGBE_GORCL);
532 IXGBE_READ_REG(hw, IXGBE_GORCH);
533 IXGBE_READ_REG(hw, IXGBE_GOTCL);
534 IXGBE_READ_REG(hw, IXGBE_GOTCH);
535 if (hw->mac.type == ixgbe_mac_82598EB)
536 for (i = 0; i < 8; i++)
537 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
538 IXGBE_READ_REG(hw, IXGBE_RUC);
539 IXGBE_READ_REG(hw, IXGBE_RFC);
540 IXGBE_READ_REG(hw, IXGBE_ROC);
541 IXGBE_READ_REG(hw, IXGBE_RJC);
542 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
543 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
544 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
545 IXGBE_READ_REG(hw, IXGBE_TORL);
546 IXGBE_READ_REG(hw, IXGBE_TORH);
547 IXGBE_READ_REG(hw, IXGBE_TPR);
548 IXGBE_READ_REG(hw, IXGBE_TPT);
549 IXGBE_READ_REG(hw, IXGBE_PTC64);
550 IXGBE_READ_REG(hw, IXGBE_PTC127);
551 IXGBE_READ_REG(hw, IXGBE_PTC255);
552 IXGBE_READ_REG(hw, IXGBE_PTC511);
553 IXGBE_READ_REG(hw, IXGBE_PTC1023);
554 IXGBE_READ_REG(hw, IXGBE_PTC1522);
555 IXGBE_READ_REG(hw, IXGBE_MPTC);
556 IXGBE_READ_REG(hw, IXGBE_BPTC);
557 for (i = 0; i < 16; i++) {
558 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
559 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
560 if (hw->mac.type >= ixgbe_mac_82599EB) {
561 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
562 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
563 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
564 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
565 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
566 } else {
567 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
568 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
569 }
570 }
571
572 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
573 if (hw->phy.id == 0)
574 ixgbe_identify_phy(hw);
575 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
576 IXGBE_MDIO_PCS_DEV_TYPE, &i);
577 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
578 IXGBE_MDIO_PCS_DEV_TYPE, &i);
579 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
580 IXGBE_MDIO_PCS_DEV_TYPE, &i);
581 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
582 IXGBE_MDIO_PCS_DEV_TYPE, &i);
583 }
584
585 return IXGBE_SUCCESS;
586 }
587
588 /**
589 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
590 * @hw: pointer to hardware structure
591 * @pba_num: stores the part number string from the EEPROM
592 * @pba_num_size: part number string buffer length
593 *
594 * Reads the part number string from the EEPROM.
595 **/
ixgbe_read_pba_string_generic(struct ixgbe_hw * hw,u8 * pba_num,u32 pba_num_size)596 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
597 u32 pba_num_size)
598 {
599 s32 ret_val;
600 u16 data;
601 u16 pba_ptr;
602 u16 offset;
603 u16 length;
604
605 DEBUGFUNC("ixgbe_read_pba_string_generic");
606
607 if (pba_num == NULL) {
608 DEBUGOUT("PBA string buffer was null\n");
609 return IXGBE_ERR_INVALID_ARGUMENT;
610 }
611
612 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
613 if (ret_val) {
614 DEBUGOUT("NVM Read Error\n");
615 return ret_val;
616 }
617
618 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
619 if (ret_val) {
620 DEBUGOUT("NVM Read Error\n");
621 return ret_val;
622 }
623
624 /*
625 * if data is not ptr guard the PBA must be in legacy format which
626 * means pba_ptr is actually our second data word for the PBA number
627 * and we can decode it into an ascii string
628 */
629 if (data != IXGBE_PBANUM_PTR_GUARD) {
630 DEBUGOUT("NVM PBA number is not stored as string\n");
631
632 /* we will need 11 characters to store the PBA */
633 if (pba_num_size < 11) {
634 DEBUGOUT("PBA string buffer too small\n");
635 return IXGBE_ERR_NO_SPACE;
636 }
637
638 /* extract hex string from data and pba_ptr */
639 pba_num[0] = (data >> 12) & 0xF;
640 pba_num[1] = (data >> 8) & 0xF;
641 pba_num[2] = (data >> 4) & 0xF;
642 pba_num[3] = data & 0xF;
643 pba_num[4] = (pba_ptr >> 12) & 0xF;
644 pba_num[5] = (pba_ptr >> 8) & 0xF;
645 pba_num[6] = '-';
646 pba_num[7] = 0;
647 pba_num[8] = (pba_ptr >> 4) & 0xF;
648 pba_num[9] = pba_ptr & 0xF;
649
650 /* put a null character on the end of our string */
651 pba_num[10] = '\0';
652
653 /* switch all the data but the '-' to hex char */
654 for (offset = 0; offset < 10; offset++) {
655 if (pba_num[offset] < 0xA)
656 pba_num[offset] += '0';
657 else if (pba_num[offset] < 0x10)
658 pba_num[offset] += 'A' - 0xA;
659 }
660
661 return IXGBE_SUCCESS;
662 }
663
664 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
665 if (ret_val) {
666 DEBUGOUT("NVM Read Error\n");
667 return ret_val;
668 }
669
670 if (length == 0xFFFF || length == 0) {
671 DEBUGOUT("NVM PBA number section invalid length\n");
672 return IXGBE_ERR_PBA_SECTION;
673 }
674
675 /* check if pba_num buffer is big enough */
676 if (pba_num_size < (((u32)length * 2) - 1)) {
677 DEBUGOUT("PBA string buffer too small\n");
678 return IXGBE_ERR_NO_SPACE;
679 }
680
681 /* trim pba length from start of string */
682 pba_ptr++;
683 length--;
684
685 for (offset = 0; offset < length; offset++) {
686 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
687 if (ret_val) {
688 DEBUGOUT("NVM Read Error\n");
689 return ret_val;
690 }
691 pba_num[offset * 2] = (u8)(data >> 8);
692 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
693 }
694 pba_num[offset * 2] = '\0';
695
696 return IXGBE_SUCCESS;
697 }
698
699 /**
700 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
701 * @hw: pointer to hardware structure
702 * @pba_num: stores the part number from the EEPROM
703 *
704 * Reads the part number from the EEPROM.
705 **/
ixgbe_read_pba_num_generic(struct ixgbe_hw * hw,u32 * pba_num)706 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
707 {
708 s32 ret_val;
709 u16 data;
710
711 DEBUGFUNC("ixgbe_read_pba_num_generic");
712
713 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
714 if (ret_val) {
715 DEBUGOUT("NVM Read Error\n");
716 return ret_val;
717 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
718 DEBUGOUT("NVM Not supported\n");
719 return IXGBE_NOT_IMPLEMENTED;
720 }
721 *pba_num = (u32)(data << 16);
722
723 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
724 if (ret_val) {
725 DEBUGOUT("NVM Read Error\n");
726 return ret_val;
727 }
728 *pba_num |= data;
729
730 return IXGBE_SUCCESS;
731 }
732
733 /**
734 * ixgbe_read_pba_raw
735 * @hw: pointer to the HW structure
736 * @eeprom_buf: optional pointer to EEPROM image
737 * @eeprom_buf_size: size of EEPROM image in words
738 * @max_pba_block_size: PBA block size limit
739 * @pba: pointer to output PBA structure
740 *
741 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
742 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
743 *
744 **/
ixgbe_read_pba_raw(struct ixgbe_hw * hw,u16 * eeprom_buf,u32 eeprom_buf_size,u16 max_pba_block_size,struct ixgbe_pba * pba)745 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
746 u32 eeprom_buf_size, u16 max_pba_block_size,
747 struct ixgbe_pba *pba)
748 {
749 s32 ret_val;
750 u16 pba_block_size;
751
752 if (pba == NULL)
753 return IXGBE_ERR_PARAM;
754
755 if (eeprom_buf == NULL) {
756 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
757 &pba->word[0]);
758 if (ret_val)
759 return ret_val;
760 } else {
761 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
762 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
763 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
764 } else {
765 return IXGBE_ERR_PARAM;
766 }
767 }
768
769 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
770 if (pba->pba_block == NULL)
771 return IXGBE_ERR_PARAM;
772
773 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
774 eeprom_buf_size,
775 &pba_block_size);
776 if (ret_val)
777 return ret_val;
778
779 if (pba_block_size > max_pba_block_size)
780 return IXGBE_ERR_PARAM;
781
782 if (eeprom_buf == NULL) {
783 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
784 pba_block_size,
785 pba->pba_block);
786 if (ret_val)
787 return ret_val;
788 } else {
789 if (eeprom_buf_size > (u32)(pba->word[1] +
790 pba_block_size)) {
791 memcpy(pba->pba_block,
792 &eeprom_buf[pba->word[1]],
793 pba_block_size * sizeof(u16));
794 } else {
795 return IXGBE_ERR_PARAM;
796 }
797 }
798 }
799
800 return IXGBE_SUCCESS;
801 }
802
803 /**
804 * ixgbe_write_pba_raw
805 * @hw: pointer to the HW structure
806 * @eeprom_buf: optional pointer to EEPROM image
807 * @eeprom_buf_size: size of EEPROM image in words
808 * @pba: pointer to PBA structure
809 *
810 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
811 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
812 *
813 **/
ixgbe_write_pba_raw(struct ixgbe_hw * hw,u16 * eeprom_buf,u32 eeprom_buf_size,struct ixgbe_pba * pba)814 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
815 u32 eeprom_buf_size, struct ixgbe_pba *pba)
816 {
817 s32 ret_val;
818
819 if (pba == NULL)
820 return IXGBE_ERR_PARAM;
821
822 if (eeprom_buf == NULL) {
823 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
824 &pba->word[0]);
825 if (ret_val)
826 return ret_val;
827 } else {
828 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
829 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
830 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
831 } else {
832 return IXGBE_ERR_PARAM;
833 }
834 }
835
836 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
837 if (pba->pba_block == NULL)
838 return IXGBE_ERR_PARAM;
839
840 if (eeprom_buf == NULL) {
841 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
842 pba->pba_block[0],
843 pba->pba_block);
844 if (ret_val)
845 return ret_val;
846 } else {
847 if (eeprom_buf_size > (u32)(pba->word[1] +
848 pba->pba_block[0])) {
849 memcpy(&eeprom_buf[pba->word[1]],
850 pba->pba_block,
851 pba->pba_block[0] * sizeof(u16));
852 } else {
853 return IXGBE_ERR_PARAM;
854 }
855 }
856 }
857
858 return IXGBE_SUCCESS;
859 }
860
861 /**
862 * ixgbe_get_pba_block_size
863 * @hw: pointer to the HW structure
864 * @eeprom_buf: optional pointer to EEPROM image
865 * @eeprom_buf_size: size of EEPROM image in words
866 * @pba_data_size: pointer to output variable
867 *
868 * Returns the size of the PBA block in words. Function operates on EEPROM
869 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
870 * EEPROM device.
871 *
872 **/
ixgbe_get_pba_block_size(struct ixgbe_hw * hw,u16 * eeprom_buf,u32 eeprom_buf_size,u16 * pba_block_size)873 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
874 u32 eeprom_buf_size, u16 *pba_block_size)
875 {
876 s32 ret_val;
877 u16 pba_word[2];
878 u16 length;
879
880 DEBUGFUNC("ixgbe_get_pba_block_size");
881
882 if (eeprom_buf == NULL) {
883 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
884 &pba_word[0]);
885 if (ret_val)
886 return ret_val;
887 } else {
888 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
889 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
890 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
891 } else {
892 return IXGBE_ERR_PARAM;
893 }
894 }
895
896 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
897 if (eeprom_buf == NULL) {
898 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
899 &length);
900 if (ret_val)
901 return ret_val;
902 } else {
903 if (eeprom_buf_size > pba_word[1])
904 length = eeprom_buf[pba_word[1] + 0];
905 else
906 return IXGBE_ERR_PARAM;
907 }
908
909 if (length == 0xFFFF || length == 0)
910 return IXGBE_ERR_PBA_SECTION;
911 } else {
912 /* PBA number in legacy format, there is no PBA Block. */
913 length = 0;
914 }
915
916 if (pba_block_size != NULL)
917 *pba_block_size = length;
918
919 return IXGBE_SUCCESS;
920 }
921
922 /**
923 * ixgbe_get_mac_addr_generic - Generic get MAC address
924 * @hw: pointer to hardware structure
925 * @mac_addr: Adapter MAC address
926 *
927 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
928 * A reset of the adapter must be performed prior to calling this function
929 * in order for the MAC address to have been loaded from the EEPROM into RAR0
930 **/
ixgbe_get_mac_addr_generic(struct ixgbe_hw * hw,u8 * mac_addr)931 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
932 {
933 u32 rar_high;
934 u32 rar_low;
935 u16 i;
936
937 DEBUGFUNC("ixgbe_get_mac_addr_generic");
938
939 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
940 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
941
942 for (i = 0; i < 4; i++)
943 mac_addr[i] = (u8)(rar_low >> (i*8));
944
945 for (i = 0; i < 2; i++)
946 mac_addr[i+4] = (u8)(rar_high >> (i*8));
947
948 return IXGBE_SUCCESS;
949 }
950
951 /**
952 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
953 * @hw: pointer to hardware structure
954 * @link_status: the link status returned by the PCI config space
955 *
956 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
957 **/
ixgbe_set_pci_config_data_generic(struct ixgbe_hw * hw,u16 link_status)958 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
959 {
960 struct ixgbe_mac_info *mac = &hw->mac;
961
962 if (hw->bus.type == ixgbe_bus_type_unknown)
963 hw->bus.type = ixgbe_bus_type_pci_express;
964
965 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
966 case IXGBE_PCI_LINK_WIDTH_1:
967 hw->bus.width = ixgbe_bus_width_pcie_x1;
968 break;
969 case IXGBE_PCI_LINK_WIDTH_2:
970 hw->bus.width = ixgbe_bus_width_pcie_x2;
971 break;
972 case IXGBE_PCI_LINK_WIDTH_4:
973 hw->bus.width = ixgbe_bus_width_pcie_x4;
974 break;
975 case IXGBE_PCI_LINK_WIDTH_8:
976 hw->bus.width = ixgbe_bus_width_pcie_x8;
977 break;
978 default:
979 hw->bus.width = ixgbe_bus_width_unknown;
980 break;
981 }
982
983 switch (link_status & IXGBE_PCI_LINK_SPEED) {
984 case IXGBE_PCI_LINK_SPEED_2500:
985 hw->bus.speed = ixgbe_bus_speed_2500;
986 break;
987 case IXGBE_PCI_LINK_SPEED_5000:
988 hw->bus.speed = ixgbe_bus_speed_5000;
989 break;
990 case IXGBE_PCI_LINK_SPEED_8000:
991 hw->bus.speed = ixgbe_bus_speed_8000;
992 break;
993 default:
994 hw->bus.speed = ixgbe_bus_speed_unknown;
995 break;
996 }
997
998 mac->ops.set_lan_id(hw);
999 }
1000
1001 /**
1002 * ixgbe_get_bus_info_generic - Generic set PCI bus info
1003 * @hw: pointer to hardware structure
1004 *
1005 * Gets the PCI bus info (speed, width, type) then calls helper function to
1006 * store this data within the ixgbe_hw structure.
1007 **/
ixgbe_get_bus_info_generic(struct ixgbe_hw * hw)1008 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1009 {
1010 u16 link_status;
1011
1012 DEBUGFUNC("ixgbe_get_bus_info_generic");
1013
1014 /* Get the negotiated link width and speed from PCI config space */
1015 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1016
1017 ixgbe_set_pci_config_data_generic(hw, link_status);
1018
1019 return IXGBE_SUCCESS;
1020 }
1021
1022 /**
1023 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1024 * @hw: pointer to the HW structure
1025 *
1026 * Determines the LAN function id by reading memory-mapped registers
1027 * and swaps the port value if requested.
1028 **/
ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw * hw)1029 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1030 {
1031 struct ixgbe_bus_info *bus = &hw->bus;
1032 u32 reg;
1033
1034 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1035
1036 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1037 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1038 bus->lan_id = bus->func;
1039
1040 /* check for a port swap */
1041 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
1042 if (reg & IXGBE_FACTPS_LFS)
1043 bus->func ^= 0x1;
1044 }
1045
1046 /**
1047 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1048 * @hw: pointer to hardware structure
1049 *
1050 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1051 * disables transmit and receive units. The adapter_stopped flag is used by
1052 * the shared code and drivers to determine if the adapter is in a stopped
1053 * state and should not touch the hardware.
1054 **/
ixgbe_stop_adapter_generic(struct ixgbe_hw * hw)1055 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1056 {
1057 u32 reg_val;
1058 u16 i;
1059
1060 DEBUGFUNC("ixgbe_stop_adapter_generic");
1061
1062 /*
1063 * Set the adapter_stopped flag so other driver functions stop touching
1064 * the hardware
1065 */
1066 hw->adapter_stopped = TRUE;
1067
1068 /* Disable the receive unit */
1069 ixgbe_disable_rx(hw);
1070
1071 /* Clear interrupt mask to stop interrupts from being generated */
1072 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1073
1074 /* Clear any pending interrupts, flush previous writes */
1075 IXGBE_READ_REG(hw, IXGBE_EICR);
1076
1077 /* Disable the transmit unit. Each queue must be disabled. */
1078 for (i = 0; i < hw->mac.max_tx_queues; i++)
1079 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1080
1081 /* Disable the receive unit by stopping each queue */
1082 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1083 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1084 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1085 reg_val |= IXGBE_RXDCTL_SWFLSH;
1086 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1087 }
1088
1089 /* flush all queues disables */
1090 IXGBE_WRITE_FLUSH(hw);
1091 msec_delay(2);
1092
1093 /*
1094 * Prevent the PCI-E bus from hanging by disabling PCI-E master
1095 * access and verify no pending requests
1096 */
1097 return ixgbe_disable_pcie_master(hw);
1098 }
1099
1100 /**
1101 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1102 * @hw: pointer to hardware structure
1103 * @index: led number to turn on
1104 **/
ixgbe_led_on_generic(struct ixgbe_hw * hw,u32 index)1105 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1106 {
1107 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1108
1109 DEBUGFUNC("ixgbe_led_on_generic");
1110
1111 /* To turn on the LED, set mode to ON. */
1112 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1113 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1114 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1115 IXGBE_WRITE_FLUSH(hw);
1116
1117 return IXGBE_SUCCESS;
1118 }
1119
1120 /**
1121 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1122 * @hw: pointer to hardware structure
1123 * @index: led number to turn off
1124 **/
ixgbe_led_off_generic(struct ixgbe_hw * hw,u32 index)1125 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1126 {
1127 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1128
1129 DEBUGFUNC("ixgbe_led_off_generic");
1130
1131 /* To turn off the LED, set mode to OFF. */
1132 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1133 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1134 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1135 IXGBE_WRITE_FLUSH(hw);
1136
1137 return IXGBE_SUCCESS;
1138 }
1139
1140 /**
1141 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1142 * @hw: pointer to hardware structure
1143 *
1144 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1145 * ixgbe_hw struct in order to set up EEPROM access.
1146 **/
ixgbe_init_eeprom_params_generic(struct ixgbe_hw * hw)1147 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1148 {
1149 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1150 u32 eec;
1151 u16 eeprom_size;
1152
1153 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1154
1155 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1156 eeprom->type = ixgbe_eeprom_none;
1157 /* Set default semaphore delay to 10ms which is a well
1158 * tested value */
1159 eeprom->semaphore_delay = 10;
1160 /* Clear EEPROM page size, it will be initialized as needed */
1161 eeprom->word_page_size = 0;
1162
1163 /*
1164 * Check for EEPROM present first.
1165 * If not present leave as none
1166 */
1167 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1168 if (eec & IXGBE_EEC_PRES) {
1169 eeprom->type = ixgbe_eeprom_spi;
1170
1171 /*
1172 * SPI EEPROM is assumed here. This code would need to
1173 * change if a future EEPROM is not SPI.
1174 */
1175 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1176 IXGBE_EEC_SIZE_SHIFT);
1177 eeprom->word_size = 1 << (eeprom_size +
1178 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1179 }
1180
1181 if (eec & IXGBE_EEC_ADDR_SIZE)
1182 eeprom->address_bits = 16;
1183 else
1184 eeprom->address_bits = 8;
1185 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1186 "%d\n", eeprom->type, eeprom->word_size,
1187 eeprom->address_bits);
1188 }
1189
1190 return IXGBE_SUCCESS;
1191 }
1192
1193 /**
1194 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1195 * @hw: pointer to hardware structure
1196 * @offset: offset within the EEPROM to write
1197 * @words: number of word(s)
1198 * @data: 16 bit word(s) to write to EEPROM
1199 *
1200 * Reads 16 bit word(s) from EEPROM through bit-bang method
1201 **/
ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1202 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1203 u16 words, u16 *data)
1204 {
1205 s32 status = IXGBE_SUCCESS;
1206 u16 i, count;
1207
1208 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1209
1210 hw->eeprom.ops.init_params(hw);
1211
1212 if (words == 0) {
1213 status = IXGBE_ERR_INVALID_ARGUMENT;
1214 goto out;
1215 }
1216
1217 if (offset + words > hw->eeprom.word_size) {
1218 status = IXGBE_ERR_EEPROM;
1219 goto out;
1220 }
1221
1222 /*
1223 * The EEPROM page size cannot be queried from the chip. We do lazy
1224 * initialization. It is worth to do that when we write large buffer.
1225 */
1226 if ((hw->eeprom.word_page_size == 0) &&
1227 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1228 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1229
1230 /*
1231 * We cannot hold synchronization semaphores for too long
1232 * to avoid other entity starvation. However it is more efficient
1233 * to read in bursts than synchronizing access for each word.
1234 */
1235 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1236 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1237 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1238 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1239 count, &data[i]);
1240
1241 if (status != IXGBE_SUCCESS)
1242 break;
1243 }
1244
1245 out:
1246 return status;
1247 }
1248
1249 /**
1250 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1251 * @hw: pointer to hardware structure
1252 * @offset: offset within the EEPROM to be written to
1253 * @words: number of word(s)
1254 * @data: 16 bit word(s) to be written to the EEPROM
1255 *
1256 * If ixgbe_eeprom_update_checksum is not called after this function, the
1257 * EEPROM will most likely contain an invalid checksum.
1258 **/
ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1259 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1260 u16 words, u16 *data)
1261 {
1262 s32 status;
1263 u16 word;
1264 u16 page_size;
1265 u16 i;
1266 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1267
1268 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1269
1270 /* Prepare the EEPROM for writing */
1271 status = ixgbe_acquire_eeprom(hw);
1272
1273 if (status == IXGBE_SUCCESS) {
1274 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1275 ixgbe_release_eeprom(hw);
1276 status = IXGBE_ERR_EEPROM;
1277 }
1278 }
1279
1280 if (status == IXGBE_SUCCESS) {
1281 for (i = 0; i < words; i++) {
1282 ixgbe_standby_eeprom(hw);
1283
1284 /* Send the WRITE ENABLE command (8 bit opcode ) */
1285 ixgbe_shift_out_eeprom_bits(hw,
1286 IXGBE_EEPROM_WREN_OPCODE_SPI,
1287 IXGBE_EEPROM_OPCODE_BITS);
1288
1289 ixgbe_standby_eeprom(hw);
1290
1291 /*
1292 * Some SPI eeproms use the 8th address bit embedded
1293 * in the opcode
1294 */
1295 if ((hw->eeprom.address_bits == 8) &&
1296 ((offset + i) >= 128))
1297 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1298
1299 /* Send the Write command (8-bit opcode + addr) */
1300 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1301 IXGBE_EEPROM_OPCODE_BITS);
1302 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1303 hw->eeprom.address_bits);
1304
1305 page_size = hw->eeprom.word_page_size;
1306
1307 /* Send the data in burst via SPI*/
1308 do {
1309 word = data[i];
1310 word = (word >> 8) | (word << 8);
1311 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1312
1313 if (page_size == 0)
1314 break;
1315
1316 /* do not wrap around page */
1317 if (((offset + i) & (page_size - 1)) ==
1318 (page_size - 1))
1319 break;
1320 } while (++i < words);
1321
1322 ixgbe_standby_eeprom(hw);
1323 msec_delay(10);
1324 }
1325 /* Done with writing - release the EEPROM */
1326 ixgbe_release_eeprom(hw);
1327 }
1328
1329 return status;
1330 }
1331
1332 /**
1333 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1334 * @hw: pointer to hardware structure
1335 * @offset: offset within the EEPROM to be written to
1336 * @data: 16 bit word to be written to the EEPROM
1337 *
1338 * If ixgbe_eeprom_update_checksum is not called after this function, the
1339 * EEPROM will most likely contain an invalid checksum.
1340 **/
ixgbe_write_eeprom_generic(struct ixgbe_hw * hw,u16 offset,u16 data)1341 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1342 {
1343 s32 status;
1344
1345 DEBUGFUNC("ixgbe_write_eeprom_generic");
1346
1347 hw->eeprom.ops.init_params(hw);
1348
1349 if (offset >= hw->eeprom.word_size) {
1350 status = IXGBE_ERR_EEPROM;
1351 goto out;
1352 }
1353
1354 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1355
1356 out:
1357 return status;
1358 }
1359
1360 /**
1361 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1362 * @hw: pointer to hardware structure
1363 * @offset: offset within the EEPROM to be read
1364 * @data: read 16 bit words(s) from EEPROM
1365 * @words: number of word(s)
1366 *
1367 * Reads 16 bit word(s) from EEPROM through bit-bang method
1368 **/
ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1369 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1370 u16 words, u16 *data)
1371 {
1372 s32 status = IXGBE_SUCCESS;
1373 u16 i, count;
1374
1375 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1376
1377 hw->eeprom.ops.init_params(hw);
1378
1379 if (words == 0) {
1380 status = IXGBE_ERR_INVALID_ARGUMENT;
1381 goto out;
1382 }
1383
1384 if (offset + words > hw->eeprom.word_size) {
1385 status = IXGBE_ERR_EEPROM;
1386 goto out;
1387 }
1388
1389 /*
1390 * We cannot hold synchronization semaphores for too long
1391 * to avoid other entity starvation. However it is more efficient
1392 * to read in bursts than synchronizing access for each word.
1393 */
1394 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1395 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1396 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1397
1398 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1399 count, &data[i]);
1400
1401 if (status != IXGBE_SUCCESS)
1402 break;
1403 }
1404
1405 out:
1406 return status;
1407 }
1408
1409 /**
1410 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1411 * @hw: pointer to hardware structure
1412 * @offset: offset within the EEPROM to be read
1413 * @words: number of word(s)
1414 * @data: read 16 bit word(s) from EEPROM
1415 *
1416 * Reads 16 bit word(s) from EEPROM through bit-bang method
1417 **/
ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1418 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1419 u16 words, u16 *data)
1420 {
1421 s32 status;
1422 u16 word_in;
1423 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1424 u16 i;
1425
1426 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1427
1428 /* Prepare the EEPROM for reading */
1429 status = ixgbe_acquire_eeprom(hw);
1430
1431 if (status == IXGBE_SUCCESS) {
1432 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1433 ixgbe_release_eeprom(hw);
1434 status = IXGBE_ERR_EEPROM;
1435 }
1436 }
1437
1438 if (status == IXGBE_SUCCESS) {
1439 for (i = 0; i < words; i++) {
1440 ixgbe_standby_eeprom(hw);
1441 /*
1442 * Some SPI eeproms use the 8th address bit embedded
1443 * in the opcode
1444 */
1445 if ((hw->eeprom.address_bits == 8) &&
1446 ((offset + i) >= 128))
1447 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1448
1449 /* Send the READ command (opcode + addr) */
1450 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1451 IXGBE_EEPROM_OPCODE_BITS);
1452 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1453 hw->eeprom.address_bits);
1454
1455 /* Read the data. */
1456 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1457 data[i] = (word_in >> 8) | (word_in << 8);
1458 }
1459
1460 /* End this read operation */
1461 ixgbe_release_eeprom(hw);
1462 }
1463
1464 return status;
1465 }
1466
1467 /**
1468 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1469 * @hw: pointer to hardware structure
1470 * @offset: offset within the EEPROM to be read
1471 * @data: read 16 bit value from EEPROM
1472 *
1473 * Reads 16 bit value from EEPROM through bit-bang method
1474 **/
ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw * hw,u16 offset,u16 * data)1475 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1476 u16 *data)
1477 {
1478 s32 status;
1479
1480 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1481
1482 hw->eeprom.ops.init_params(hw);
1483
1484 if (offset >= hw->eeprom.word_size) {
1485 status = IXGBE_ERR_EEPROM;
1486 goto out;
1487 }
1488
1489 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1490
1491 out:
1492 return status;
1493 }
1494
1495 /**
1496 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1497 * @hw: pointer to hardware structure
1498 * @offset: offset of word in the EEPROM to read
1499 * @words: number of word(s)
1500 * @data: 16 bit word(s) from the EEPROM
1501 *
1502 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1503 **/
ixgbe_read_eerd_buffer_generic(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1504 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1505 u16 words, u16 *data)
1506 {
1507 u32 eerd;
1508 s32 status = IXGBE_SUCCESS;
1509 u32 i;
1510
1511 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1512
1513 hw->eeprom.ops.init_params(hw);
1514
1515 if (words == 0) {
1516 status = IXGBE_ERR_INVALID_ARGUMENT;
1517 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1518 goto out;
1519 }
1520
1521 if (offset >= hw->eeprom.word_size) {
1522 status = IXGBE_ERR_EEPROM;
1523 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1524 goto out;
1525 }
1526
1527 for (i = 0; i < words; i++) {
1528 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1529 IXGBE_EEPROM_RW_REG_START;
1530
1531 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1532 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1533
1534 if (status == IXGBE_SUCCESS) {
1535 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1536 IXGBE_EEPROM_RW_REG_DATA);
1537 } else {
1538 DEBUGOUT("Eeprom read timed out\n");
1539 goto out;
1540 }
1541 }
1542 out:
1543 return status;
1544 }
1545
1546 /**
1547 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1548 * @hw: pointer to hardware structure
1549 * @offset: offset within the EEPROM to be used as a scratch pad
1550 *
1551 * Discover EEPROM page size by writing marching data at given offset.
1552 * This function is called only when we are writing a new large buffer
1553 * at given offset so the data would be overwritten anyway.
1554 **/
ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw * hw,u16 offset)1555 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1556 u16 offset)
1557 {
1558 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1559 s32 status = IXGBE_SUCCESS;
1560 u16 i;
1561
1562 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1563
1564 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1565 data[i] = i;
1566
1567 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1568 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1569 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1570 hw->eeprom.word_page_size = 0;
1571 if (status != IXGBE_SUCCESS)
1572 goto out;
1573
1574 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1575 if (status != IXGBE_SUCCESS)
1576 goto out;
1577
1578 /*
1579 * When writing in burst more than the actual page size
1580 * EEPROM address wraps around current page.
1581 */
1582 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1583
1584 DEBUGOUT1("Detected EEPROM page size = %d words.",
1585 hw->eeprom.word_page_size);
1586 out:
1587 return status;
1588 }
1589
1590 /**
1591 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1592 * @hw: pointer to hardware structure
1593 * @offset: offset of word in the EEPROM to read
1594 * @data: word read from the EEPROM
1595 *
1596 * Reads a 16 bit word from the EEPROM using the EERD register.
1597 **/
ixgbe_read_eerd_generic(struct ixgbe_hw * hw,u16 offset,u16 * data)1598 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1599 {
1600 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1601 }
1602
1603 /**
1604 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1605 * @hw: pointer to hardware structure
1606 * @offset: offset of word in the EEPROM to write
1607 * @words: number of word(s)
1608 * @data: word(s) write to the EEPROM
1609 *
1610 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1611 **/
ixgbe_write_eewr_buffer_generic(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1612 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1613 u16 words, u16 *data)
1614 {
1615 u32 eewr;
1616 s32 status = IXGBE_SUCCESS;
1617 u16 i;
1618
1619 DEBUGFUNC("ixgbe_write_eewr_generic");
1620
1621 hw->eeprom.ops.init_params(hw);
1622
1623 if (words == 0) {
1624 status = IXGBE_ERR_INVALID_ARGUMENT;
1625 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1626 goto out;
1627 }
1628
1629 if (offset >= hw->eeprom.word_size) {
1630 status = IXGBE_ERR_EEPROM;
1631 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1632 goto out;
1633 }
1634
1635 for (i = 0; i < words; i++) {
1636 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1637 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1638 IXGBE_EEPROM_RW_REG_START;
1639
1640 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1641 if (status != IXGBE_SUCCESS) {
1642 DEBUGOUT("Eeprom write EEWR timed out\n");
1643 goto out;
1644 }
1645
1646 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1647
1648 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1649 if (status != IXGBE_SUCCESS) {
1650 DEBUGOUT("Eeprom write EEWR timed out\n");
1651 goto out;
1652 }
1653 }
1654
1655 out:
1656 return status;
1657 }
1658
1659 /**
1660 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1661 * @hw: pointer to hardware structure
1662 * @offset: offset of word in the EEPROM to write
1663 * @data: word write to the EEPROM
1664 *
1665 * Write a 16 bit word to the EEPROM using the EEWR register.
1666 **/
ixgbe_write_eewr_generic(struct ixgbe_hw * hw,u16 offset,u16 data)1667 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1668 {
1669 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1670 }
1671
1672 /**
1673 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1674 * @hw: pointer to hardware structure
1675 * @ee_reg: EEPROM flag for polling
1676 *
1677 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1678 * read or write is done respectively.
1679 **/
ixgbe_poll_eerd_eewr_done(struct ixgbe_hw * hw,u32 ee_reg)1680 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1681 {
1682 u32 i;
1683 u32 reg;
1684 s32 status = IXGBE_ERR_EEPROM;
1685
1686 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1687
1688 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1689 if (ee_reg == IXGBE_NVM_POLL_READ)
1690 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1691 else
1692 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1693
1694 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1695 status = IXGBE_SUCCESS;
1696 break;
1697 }
1698 usec_delay(5);
1699 }
1700
1701 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1702 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1703 "EEPROM read/write done polling timed out");
1704
1705 return status;
1706 }
1707
1708 /**
1709 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1710 * @hw: pointer to hardware structure
1711 *
1712 * Prepares EEPROM for access using bit-bang method. This function should
1713 * be called before issuing a command to the EEPROM.
1714 **/
ixgbe_acquire_eeprom(struct ixgbe_hw * hw)1715 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1716 {
1717 s32 status = IXGBE_SUCCESS;
1718 u32 eec;
1719 u32 i;
1720
1721 DEBUGFUNC("ixgbe_acquire_eeprom");
1722
1723 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1724 != IXGBE_SUCCESS)
1725 status = IXGBE_ERR_SWFW_SYNC;
1726
1727 if (status == IXGBE_SUCCESS) {
1728 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1729
1730 /* Request EEPROM Access */
1731 eec |= IXGBE_EEC_REQ;
1732 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1733
1734 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1735 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1736 if (eec & IXGBE_EEC_GNT)
1737 break;
1738 usec_delay(5);
1739 }
1740
1741 /* Release if grant not acquired */
1742 if (!(eec & IXGBE_EEC_GNT)) {
1743 eec &= ~IXGBE_EEC_REQ;
1744 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1745 DEBUGOUT("Could not acquire EEPROM grant\n");
1746
1747 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1748 status = IXGBE_ERR_EEPROM;
1749 }
1750
1751 /* Setup EEPROM for Read/Write */
1752 if (status == IXGBE_SUCCESS) {
1753 /* Clear CS and SK */
1754 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1755 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1756 IXGBE_WRITE_FLUSH(hw);
1757 usec_delay(1);
1758 }
1759 }
1760 return status;
1761 }
1762
1763 /**
1764 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1765 * @hw: pointer to hardware structure
1766 *
1767 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1768 **/
ixgbe_get_eeprom_semaphore(struct ixgbe_hw * hw)1769 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1770 {
1771 s32 status = IXGBE_ERR_EEPROM;
1772 u32 timeout = 2000;
1773 u32 i;
1774 u32 swsm;
1775
1776 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1777
1778
1779 /* Get SMBI software semaphore between device drivers first */
1780 for (i = 0; i < timeout; i++) {
1781 /*
1782 * If the SMBI bit is 0 when we read it, then the bit will be
1783 * set and we have the semaphore
1784 */
1785 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1786 if (!(swsm & IXGBE_SWSM_SMBI)) {
1787 status = IXGBE_SUCCESS;
1788 break;
1789 }
1790 usec_delay(50);
1791 }
1792
1793 if (i == timeout) {
1794 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1795 "not granted.\n");
1796 /*
1797 * this release is particularly important because our attempts
1798 * above to get the semaphore may have succeeded, and if there
1799 * was a timeout, we should unconditionally clear the semaphore
1800 * bits to free the driver to make progress
1801 */
1802 ixgbe_release_eeprom_semaphore(hw);
1803
1804 usec_delay(50);
1805 /*
1806 * one last try
1807 * If the SMBI bit is 0 when we read it, then the bit will be
1808 * set and we have the semaphore
1809 */
1810 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1811 if (!(swsm & IXGBE_SWSM_SMBI))
1812 status = IXGBE_SUCCESS;
1813 }
1814
1815 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1816 if (status == IXGBE_SUCCESS) {
1817 for (i = 0; i < timeout; i++) {
1818 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1819
1820 /* Set the SW EEPROM semaphore bit to request access */
1821 swsm |= IXGBE_SWSM_SWESMBI;
1822 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1823
1824 /*
1825 * If we set the bit successfully then we got the
1826 * semaphore.
1827 */
1828 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1829 if (swsm & IXGBE_SWSM_SWESMBI)
1830 break;
1831
1832 usec_delay(50);
1833 }
1834
1835 /*
1836 * Release semaphores and return error if SW EEPROM semaphore
1837 * was not granted because we don't have access to the EEPROM
1838 */
1839 if (i >= timeout) {
1840 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1841 "SWESMBI Software EEPROM semaphore not granted.\n");
1842 ixgbe_release_eeprom_semaphore(hw);
1843 status = IXGBE_ERR_EEPROM;
1844 }
1845 } else {
1846 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1847 "Software semaphore SMBI between device drivers "
1848 "not granted.\n");
1849 }
1850
1851 return status;
1852 }
1853
1854 /**
1855 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1856 * @hw: pointer to hardware structure
1857 *
1858 * This function clears hardware semaphore bits.
1859 **/
ixgbe_release_eeprom_semaphore(struct ixgbe_hw * hw)1860 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1861 {
1862 u32 swsm;
1863
1864 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1865
1866 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1867
1868 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1869 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1870 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1871 IXGBE_WRITE_FLUSH(hw);
1872 }
1873
1874 /**
1875 * ixgbe_ready_eeprom - Polls for EEPROM ready
1876 * @hw: pointer to hardware structure
1877 **/
ixgbe_ready_eeprom(struct ixgbe_hw * hw)1878 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1879 {
1880 s32 status = IXGBE_SUCCESS;
1881 u16 i;
1882 u8 spi_stat_reg;
1883
1884 DEBUGFUNC("ixgbe_ready_eeprom");
1885
1886 /*
1887 * Read "Status Register" repeatedly until the LSB is cleared. The
1888 * EEPROM will signal that the command has been completed by clearing
1889 * bit 0 of the internal status register. If it's not cleared within
1890 * 5 milliseconds, then error out.
1891 */
1892 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1893 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1894 IXGBE_EEPROM_OPCODE_BITS);
1895 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1896 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1897 break;
1898
1899 usec_delay(5);
1900 ixgbe_standby_eeprom(hw);
1901 };
1902
1903 /*
1904 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1905 * devices (and only 0-5mSec on 5V devices)
1906 */
1907 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1908 DEBUGOUT("SPI EEPROM Status error\n");
1909 status = IXGBE_ERR_EEPROM;
1910 }
1911
1912 return status;
1913 }
1914
1915 /**
1916 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1917 * @hw: pointer to hardware structure
1918 **/
ixgbe_standby_eeprom(struct ixgbe_hw * hw)1919 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1920 {
1921 u32 eec;
1922
1923 DEBUGFUNC("ixgbe_standby_eeprom");
1924
1925 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1926
1927 /* Toggle CS to flush commands */
1928 eec |= IXGBE_EEC_CS;
1929 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1930 IXGBE_WRITE_FLUSH(hw);
1931 usec_delay(1);
1932 eec &= ~IXGBE_EEC_CS;
1933 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1934 IXGBE_WRITE_FLUSH(hw);
1935 usec_delay(1);
1936 }
1937
1938 /**
1939 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1940 * @hw: pointer to hardware structure
1941 * @data: data to send to the EEPROM
1942 * @count: number of bits to shift out
1943 **/
ixgbe_shift_out_eeprom_bits(struct ixgbe_hw * hw,u16 data,u16 count)1944 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1945 u16 count)
1946 {
1947 u32 eec;
1948 u32 mask;
1949 u32 i;
1950
1951 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
1952
1953 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1954
1955 /*
1956 * Mask is used to shift "count" bits of "data" out to the EEPROM
1957 * one bit at a time. Determine the starting bit based on count
1958 */
1959 mask = 0x01 << (count - 1);
1960
1961 for (i = 0; i < count; i++) {
1962 /*
1963 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1964 * "1", and then raising and then lowering the clock (the SK
1965 * bit controls the clock input to the EEPROM). A "0" is
1966 * shifted out to the EEPROM by setting "DI" to "0" and then
1967 * raising and then lowering the clock.
1968 */
1969 if (data & mask)
1970 eec |= IXGBE_EEC_DI;
1971 else
1972 eec &= ~IXGBE_EEC_DI;
1973
1974 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1975 IXGBE_WRITE_FLUSH(hw);
1976
1977 usec_delay(1);
1978
1979 ixgbe_raise_eeprom_clk(hw, &eec);
1980 ixgbe_lower_eeprom_clk(hw, &eec);
1981
1982 /*
1983 * Shift mask to signify next bit of data to shift in to the
1984 * EEPROM
1985 */
1986 mask = mask >> 1;
1987 };
1988
1989 /* We leave the "DI" bit set to "0" when we leave this routine. */
1990 eec &= ~IXGBE_EEC_DI;
1991 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1992 IXGBE_WRITE_FLUSH(hw);
1993 }
1994
1995 /**
1996 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1997 * @hw: pointer to hardware structure
1998 **/
ixgbe_shift_in_eeprom_bits(struct ixgbe_hw * hw,u16 count)1999 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2000 {
2001 u32 eec;
2002 u32 i;
2003 u16 data = 0;
2004
2005 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2006
2007 /*
2008 * In order to read a register from the EEPROM, we need to shift
2009 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2010 * the clock input to the EEPROM (setting the SK bit), and then reading
2011 * the value of the "DO" bit. During this "shifting in" process the
2012 * "DI" bit should always be clear.
2013 */
2014 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2015
2016 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2017
2018 for (i = 0; i < count; i++) {
2019 data = data << 1;
2020 ixgbe_raise_eeprom_clk(hw, &eec);
2021
2022 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2023
2024 eec &= ~(IXGBE_EEC_DI);
2025 if (eec & IXGBE_EEC_DO)
2026 data |= 1;
2027
2028 ixgbe_lower_eeprom_clk(hw, &eec);
2029 }
2030
2031 return data;
2032 }
2033
2034 /**
2035 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2036 * @hw: pointer to hardware structure
2037 * @eec: EEC register's current value
2038 **/
ixgbe_raise_eeprom_clk(struct ixgbe_hw * hw,u32 * eec)2039 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2040 {
2041 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2042
2043 /*
2044 * Raise the clock input to the EEPROM
2045 * (setting the SK bit), then delay
2046 */
2047 *eec = *eec | IXGBE_EEC_SK;
2048 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
2049 IXGBE_WRITE_FLUSH(hw);
2050 usec_delay(1);
2051 }
2052
2053 /**
2054 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2055 * @hw: pointer to hardware structure
2056 * @eecd: EECD's current value
2057 **/
ixgbe_lower_eeprom_clk(struct ixgbe_hw * hw,u32 * eec)2058 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2059 {
2060 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2061
2062 /*
2063 * Lower the clock input to the EEPROM (clearing the SK bit), then
2064 * delay
2065 */
2066 *eec = *eec & ~IXGBE_EEC_SK;
2067 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
2068 IXGBE_WRITE_FLUSH(hw);
2069 usec_delay(1);
2070 }
2071
2072 /**
2073 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2074 * @hw: pointer to hardware structure
2075 **/
ixgbe_release_eeprom(struct ixgbe_hw * hw)2076 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2077 {
2078 u32 eec;
2079
2080 DEBUGFUNC("ixgbe_release_eeprom");
2081
2082 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2083
2084 eec |= IXGBE_EEC_CS; /* Pull CS high */
2085 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2086
2087 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
2088 IXGBE_WRITE_FLUSH(hw);
2089
2090 usec_delay(1);
2091
2092 /* Stop requesting EEPROM access */
2093 eec &= ~IXGBE_EEC_REQ;
2094 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
2095
2096 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2097
2098 /* Delay before attempt to obtain semaphore again to allow FW access */
2099 msec_delay(hw->eeprom.semaphore_delay);
2100 }
2101
2102 /**
2103 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2104 * @hw: pointer to hardware structure
2105 *
2106 * Returns a negative error code on error, or the 16-bit checksum
2107 **/
ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw * hw)2108 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2109 {
2110 u16 i;
2111 u16 j;
2112 u16 checksum = 0;
2113 u16 length = 0;
2114 u16 pointer = 0;
2115 u16 word = 0;
2116
2117 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2118
2119 /* Include 0x0-0x3F in the checksum */
2120 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2121 if (hw->eeprom.ops.read(hw, i, &word)) {
2122 DEBUGOUT("EEPROM read failed\n");
2123 return IXGBE_ERR_EEPROM;
2124 }
2125 checksum += word;
2126 }
2127
2128 /* Include all data from pointers except for the fw pointer */
2129 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2130 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2131 DEBUGOUT("EEPROM read failed\n");
2132 return IXGBE_ERR_EEPROM;
2133 }
2134
2135 /* If the pointer seems invalid */
2136 if (pointer == 0xFFFF || pointer == 0)
2137 continue;
2138
2139 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2140 DEBUGOUT("EEPROM read failed\n");
2141 return IXGBE_ERR_EEPROM;
2142 }
2143
2144 if (length == 0xFFFF || length == 0)
2145 continue;
2146
2147 for (j = pointer + 1; j <= pointer + length; j++) {
2148 if (hw->eeprom.ops.read(hw, j, &word)) {
2149 DEBUGOUT("EEPROM read failed\n");
2150 return IXGBE_ERR_EEPROM;
2151 }
2152 checksum += word;
2153 }
2154 }
2155
2156 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2157
2158 return (s32)checksum;
2159 }
2160
2161 /**
2162 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2163 * @hw: pointer to hardware structure
2164 * @checksum_val: calculated checksum
2165 *
2166 * Performs checksum calculation and validates the EEPROM checksum. If the
2167 * caller does not need checksum_val, the value can be NULL.
2168 **/
ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw * hw,u16 * checksum_val)2169 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2170 u16 *checksum_val)
2171 {
2172 s32 status;
2173 u16 checksum;
2174 u16 read_checksum = 0;
2175
2176 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2177
2178 /* Read the first word from the EEPROM. If this times out or fails, do
2179 * not continue or we could be in for a very long wait while every
2180 * EEPROM read fails
2181 */
2182 status = hw->eeprom.ops.read(hw, 0, &checksum);
2183 if (status) {
2184 DEBUGOUT("EEPROM read failed\n");
2185 return status;
2186 }
2187
2188 status = hw->eeprom.ops.calc_checksum(hw);
2189 if (status < 0)
2190 return status;
2191
2192 checksum = (u16)(status & 0xffff);
2193
2194 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2195 if (status) {
2196 DEBUGOUT("EEPROM read failed\n");
2197 return status;
2198 }
2199
2200 /* Verify read checksum from EEPROM is the same as
2201 * calculated checksum
2202 */
2203 if (read_checksum != checksum)
2204 status = IXGBE_ERR_EEPROM_CHECKSUM;
2205
2206 /* If the user cares, return the calculated checksum */
2207 if (checksum_val)
2208 *checksum_val = checksum;
2209
2210 return status;
2211 }
2212
2213 /**
2214 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2215 * @hw: pointer to hardware structure
2216 **/
ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw * hw)2217 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2218 {
2219 s32 status;
2220 u16 checksum;
2221
2222 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2223
2224 /* Read the first word from the EEPROM. If this times out or fails, do
2225 * not continue or we could be in for a very long wait while every
2226 * EEPROM read fails
2227 */
2228 status = hw->eeprom.ops.read(hw, 0, &checksum);
2229 if (status) {
2230 DEBUGOUT("EEPROM read failed\n");
2231 return status;
2232 }
2233
2234 status = hw->eeprom.ops.calc_checksum(hw);
2235 if (status < 0)
2236 return status;
2237
2238 checksum = (u16)(status & 0xffff);
2239
2240 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2241
2242 return status;
2243 }
2244
2245 /**
2246 * ixgbe_validate_mac_addr - Validate MAC address
2247 * @mac_addr: pointer to MAC address.
2248 *
2249 * Tests a MAC address to ensure it is a valid Individual Address
2250 **/
ixgbe_validate_mac_addr(u8 * mac_addr)2251 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2252 {
2253 s32 status = IXGBE_SUCCESS;
2254
2255 DEBUGFUNC("ixgbe_validate_mac_addr");
2256
2257 /* Make sure it is not a multicast address */
2258 if (IXGBE_IS_MULTICAST(mac_addr)) {
2259 DEBUGOUT("MAC address is multicast\n");
2260 status = IXGBE_ERR_INVALID_MAC_ADDR;
2261 /* Not a broadcast address */
2262 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2263 DEBUGOUT("MAC address is broadcast\n");
2264 status = IXGBE_ERR_INVALID_MAC_ADDR;
2265 /* Reject the zero address */
2266 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2267 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2268 DEBUGOUT("MAC address is all zeros\n");
2269 status = IXGBE_ERR_INVALID_MAC_ADDR;
2270 }
2271 return status;
2272 }
2273
2274 /**
2275 * ixgbe_set_rar_generic - Set Rx address register
2276 * @hw: pointer to hardware structure
2277 * @index: Receive address register to write
2278 * @addr: Address to put into receive address register
2279 * @vmdq: VMDq "set" or "pool" index
2280 * @enable_addr: set flag that address is active
2281 *
2282 * Puts an ethernet address into a receive address register.
2283 **/
ixgbe_set_rar_generic(struct ixgbe_hw * hw,u32 index,u8 * addr,u32 vmdq,u32 enable_addr)2284 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2285 u32 enable_addr)
2286 {
2287 u32 rar_low, rar_high;
2288 u32 rar_entries = hw->mac.num_rar_entries;
2289
2290 DEBUGFUNC("ixgbe_set_rar_generic");
2291
2292 /* Make sure we are using a valid rar index range */
2293 if (index >= rar_entries) {
2294 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2295 "RAR index %d is out of range.\n", index);
2296 return IXGBE_ERR_INVALID_ARGUMENT;
2297 }
2298
2299 /* setup VMDq pool selection before this RAR gets enabled */
2300 hw->mac.ops.set_vmdq(hw, index, vmdq);
2301
2302 /*
2303 * HW expects these in little endian so we reverse the byte
2304 * order from network order (big endian) to little endian
2305 */
2306 rar_low = ((u32)addr[0] |
2307 ((u32)addr[1] << 8) |
2308 ((u32)addr[2] << 16) |
2309 ((u32)addr[3] << 24));
2310 /*
2311 * Some parts put the VMDq setting in the extra RAH bits,
2312 * so save everything except the lower 16 bits that hold part
2313 * of the address and the address valid bit.
2314 */
2315 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2316 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2317 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2318
2319 if (enable_addr != 0)
2320 rar_high |= IXGBE_RAH_AV;
2321
2322 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2323 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2324
2325 return IXGBE_SUCCESS;
2326 }
2327
2328 /**
2329 * ixgbe_clear_rar_generic - Remove Rx address register
2330 * @hw: pointer to hardware structure
2331 * @index: Receive address register to write
2332 *
2333 * Clears an ethernet address from a receive address register.
2334 **/
ixgbe_clear_rar_generic(struct ixgbe_hw * hw,u32 index)2335 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2336 {
2337 u32 rar_high;
2338 u32 rar_entries = hw->mac.num_rar_entries;
2339
2340 DEBUGFUNC("ixgbe_clear_rar_generic");
2341
2342 /* Make sure we are using a valid rar index range */
2343 if (index >= rar_entries) {
2344 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2345 "RAR index %d is out of range.\n", index);
2346 return IXGBE_ERR_INVALID_ARGUMENT;
2347 }
2348
2349 /*
2350 * Some parts put the VMDq setting in the extra RAH bits,
2351 * so save everything except the lower 16 bits that hold part
2352 * of the address and the address valid bit.
2353 */
2354 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2355 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2356
2357 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2358 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2359
2360 /* clear VMDq pool/queue selection for this RAR */
2361 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2362
2363 return IXGBE_SUCCESS;
2364 }
2365
2366 /**
2367 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2368 * @hw: pointer to hardware structure
2369 *
2370 * Places the MAC address in receive address register 0 and clears the rest
2371 * of the receive address registers. Clears the multicast table. Assumes
2372 * the receiver is in reset when the routine is called.
2373 **/
ixgbe_init_rx_addrs_generic(struct ixgbe_hw * hw)2374 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2375 {
2376 u32 i;
2377 u32 rar_entries = hw->mac.num_rar_entries;
2378
2379 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2380
2381 /*
2382 * If the current mac address is valid, assume it is a software override
2383 * to the permanent address.
2384 * Otherwise, use the permanent address from the eeprom.
2385 */
2386 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2387 IXGBE_ERR_INVALID_MAC_ADDR) {
2388 /* Get the MAC address from the RAR0 for later reference */
2389 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2390
2391 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2392 hw->mac.addr[0], hw->mac.addr[1],
2393 hw->mac.addr[2]);
2394 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2395 hw->mac.addr[4], hw->mac.addr[5]);
2396 } else {
2397 /* Setup the receive address. */
2398 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2399 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2400 hw->mac.addr[0], hw->mac.addr[1],
2401 hw->mac.addr[2]);
2402 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2403 hw->mac.addr[4], hw->mac.addr[5]);
2404
2405 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2406
2407 /* clear VMDq pool/queue selection for RAR 0 */
2408 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2409 }
2410 hw->addr_ctrl.overflow_promisc = 0;
2411
2412 hw->addr_ctrl.rar_used_count = 1;
2413
2414 /* Zero out the other receive addresses. */
2415 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2416 for (i = 1; i < rar_entries; i++) {
2417 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2418 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2419 }
2420
2421 /* Clear the MTA */
2422 hw->addr_ctrl.mta_in_use = 0;
2423 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2424
2425 DEBUGOUT(" Clearing MTA\n");
2426 for (i = 0; i < hw->mac.mcft_size; i++)
2427 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2428
2429 ixgbe_init_uta_tables(hw);
2430
2431 return IXGBE_SUCCESS;
2432 }
2433
2434 /**
2435 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2436 * @hw: pointer to hardware structure
2437 * @addr: new address
2438 *
2439 * Adds it to unused receive address register or goes into promiscuous mode.
2440 **/
ixgbe_add_uc_addr(struct ixgbe_hw * hw,u8 * addr,u32 vmdq)2441 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2442 {
2443 u32 rar_entries = hw->mac.num_rar_entries;
2444 u32 rar;
2445
2446 DEBUGFUNC("ixgbe_add_uc_addr");
2447
2448 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2449 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2450
2451 /*
2452 * Place this address in the RAR if there is room,
2453 * else put the controller into promiscuous mode
2454 */
2455 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2456 rar = hw->addr_ctrl.rar_used_count;
2457 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2458 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2459 hw->addr_ctrl.rar_used_count++;
2460 } else {
2461 hw->addr_ctrl.overflow_promisc++;
2462 }
2463
2464 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2465 }
2466
2467 /**
2468 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2469 * @hw: pointer to hardware structure
2470 * @addr_list: the list of new addresses
2471 * @addr_count: number of addresses
2472 * @next: iterator function to walk the address list
2473 *
2474 * The given list replaces any existing list. Clears the secondary addrs from
2475 * receive address registers. Uses unused receive address registers for the
2476 * first secondary addresses, and falls back to promiscuous mode as needed.
2477 *
2478 * Drivers using secondary unicast addresses must set user_set_promisc when
2479 * manually putting the device into promiscuous mode.
2480 **/
ixgbe_update_uc_addr_list_generic(struct ixgbe_hw * hw,u8 * addr_list,u32 addr_count,ixgbe_mc_addr_itr next)2481 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2482 u32 addr_count, ixgbe_mc_addr_itr next)
2483 {
2484 u8 *addr;
2485 u32 i;
2486 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2487 u32 uc_addr_in_use;
2488 u32 fctrl;
2489 u32 vmdq;
2490
2491 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2492
2493 /*
2494 * Clear accounting of old secondary address list,
2495 * don't count RAR[0]
2496 */
2497 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2498 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2499 hw->addr_ctrl.overflow_promisc = 0;
2500
2501 /* Zero out the other receive addresses */
2502 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2503 for (i = 0; i < uc_addr_in_use; i++) {
2504 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2505 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2506 }
2507
2508 /* Add the new addresses */
2509 for (i = 0; i < addr_count; i++) {
2510 DEBUGOUT(" Adding the secondary addresses:\n");
2511 addr = next(hw, &addr_list, &vmdq);
2512 ixgbe_add_uc_addr(hw, addr, vmdq);
2513 }
2514
2515 if (hw->addr_ctrl.overflow_promisc) {
2516 /* enable promisc if not already in overflow or set by user */
2517 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2518 DEBUGOUT(" Entering address overflow promisc mode\n");
2519 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2520 fctrl |= IXGBE_FCTRL_UPE;
2521 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2522 }
2523 } else {
2524 /* only disable if set by overflow, not by user */
2525 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2526 DEBUGOUT(" Leaving address overflow promisc mode\n");
2527 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2528 fctrl &= ~IXGBE_FCTRL_UPE;
2529 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2530 }
2531 }
2532
2533 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2534 return IXGBE_SUCCESS;
2535 }
2536
2537 /**
2538 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2539 * @hw: pointer to hardware structure
2540 * @mc_addr: the multicast address
2541 *
2542 * Extracts the 12 bits, from a multicast address, to determine which
2543 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2544 * incoming rx multicast addresses, to determine the bit-vector to check in
2545 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2546 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2547 * to mc_filter_type.
2548 **/
ixgbe_mta_vector(struct ixgbe_hw * hw,u8 * mc_addr)2549 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2550 {
2551 u32 vector = 0;
2552
2553 DEBUGFUNC("ixgbe_mta_vector");
2554
2555 switch (hw->mac.mc_filter_type) {
2556 case 0: /* use bits [47:36] of the address */
2557 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2558 break;
2559 case 1: /* use bits [46:35] of the address */
2560 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2561 break;
2562 case 2: /* use bits [45:34] of the address */
2563 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2564 break;
2565 case 3: /* use bits [43:32] of the address */
2566 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2567 break;
2568 default: /* Invalid mc_filter_type */
2569 DEBUGOUT("MC filter type param set incorrectly\n");
2570 ASSERT(0);
2571 break;
2572 }
2573
2574 /* vector can only be 12-bits or boundary will be exceeded */
2575 vector &= 0xFFF;
2576 return vector;
2577 }
2578
2579 /**
2580 * ixgbe_set_mta - Set bit-vector in multicast table
2581 * @hw: pointer to hardware structure
2582 * @hash_value: Multicast address hash value
2583 *
2584 * Sets the bit-vector in the multicast table.
2585 **/
ixgbe_set_mta(struct ixgbe_hw * hw,u8 * mc_addr)2586 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2587 {
2588 u32 vector;
2589 u32 vector_bit;
2590 u32 vector_reg;
2591
2592 DEBUGFUNC("ixgbe_set_mta");
2593
2594 hw->addr_ctrl.mta_in_use++;
2595
2596 vector = ixgbe_mta_vector(hw, mc_addr);
2597 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2598
2599 /*
2600 * The MTA is a register array of 128 32-bit registers. It is treated
2601 * like an array of 4096 bits. We want to set bit
2602 * BitArray[vector_value]. So we figure out what register the bit is
2603 * in, read it, OR in the new bit, then write back the new value. The
2604 * register is determined by the upper 7 bits of the vector value and
2605 * the bit within that register are determined by the lower 5 bits of
2606 * the value.
2607 */
2608 vector_reg = (vector >> 5) & 0x7F;
2609 vector_bit = vector & 0x1F;
2610 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2611 }
2612
2613 /**
2614 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2615 * @hw: pointer to hardware structure
2616 * @mc_addr_list: the list of new multicast addresses
2617 * @mc_addr_count: number of addresses
2618 * @next: iterator function to walk the multicast address list
2619 * @clear: flag, when set clears the table beforehand
2620 *
2621 * When the clear flag is set, the given list replaces any existing list.
2622 * Hashes the given addresses into the multicast table.
2623 **/
ixgbe_update_mc_addr_list_generic(struct ixgbe_hw * hw,u8 * mc_addr_list,u32 mc_addr_count,ixgbe_mc_addr_itr next,bool clear)2624 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2625 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2626 bool clear)
2627 {
2628 u32 i;
2629 u32 vmdq;
2630
2631 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2632
2633 /*
2634 * Set the new number of MC addresses that we are being requested to
2635 * use.
2636 */
2637 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2638 hw->addr_ctrl.mta_in_use = 0;
2639
2640 /* Clear mta_shadow */
2641 if (clear) {
2642 DEBUGOUT(" Clearing MTA\n");
2643 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2644 }
2645
2646 /* Update mta_shadow */
2647 for (i = 0; i < mc_addr_count; i++) {
2648 DEBUGOUT(" Adding the multicast addresses:\n");
2649 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2650 }
2651
2652 /* Enable mta */
2653 for (i = 0; i < hw->mac.mcft_size; i++)
2654 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2655 hw->mac.mta_shadow[i]);
2656
2657 if (hw->addr_ctrl.mta_in_use > 0)
2658 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2659 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2660
2661 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2662 return IXGBE_SUCCESS;
2663 }
2664
2665 /**
2666 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2667 * @hw: pointer to hardware structure
2668 *
2669 * Enables multicast address in RAR and the use of the multicast hash table.
2670 **/
ixgbe_enable_mc_generic(struct ixgbe_hw * hw)2671 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2672 {
2673 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2674
2675 DEBUGFUNC("ixgbe_enable_mc_generic");
2676
2677 if (a->mta_in_use > 0)
2678 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2679 hw->mac.mc_filter_type);
2680
2681 return IXGBE_SUCCESS;
2682 }
2683
2684 /**
2685 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2686 * @hw: pointer to hardware structure
2687 *
2688 * Disables multicast address in RAR and the use of the multicast hash table.
2689 **/
ixgbe_disable_mc_generic(struct ixgbe_hw * hw)2690 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2691 {
2692 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2693
2694 DEBUGFUNC("ixgbe_disable_mc_generic");
2695
2696 if (a->mta_in_use > 0)
2697 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2698
2699 return IXGBE_SUCCESS;
2700 }
2701
2702 /**
2703 * ixgbe_fc_enable_generic - Enable flow control
2704 * @hw: pointer to hardware structure
2705 *
2706 * Enable flow control according to the current settings.
2707 **/
ixgbe_fc_enable_generic(struct ixgbe_hw * hw)2708 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2709 {
2710 s32 ret_val = IXGBE_SUCCESS;
2711 u32 mflcn_reg, fccfg_reg;
2712 u32 reg;
2713 u32 fcrtl, fcrth;
2714 int i;
2715
2716 DEBUGFUNC("ixgbe_fc_enable_generic");
2717
2718 /* Validate the water mark configuration */
2719 if (!hw->fc.pause_time) {
2720 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2721 goto out;
2722 }
2723
2724 /* Low water mark of zero causes XOFF floods */
2725 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2726 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2727 hw->fc.high_water[i]) {
2728 if (!hw->fc.low_water[i] ||
2729 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2730 DEBUGOUT("Invalid water mark configuration\n");
2731 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2732 goto out;
2733 }
2734 }
2735 }
2736
2737 /* Negotiate the fc mode to use */
2738 ixgbe_fc_autoneg(hw);
2739
2740 /* Disable any previous flow control settings */
2741 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2742 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2743
2744 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2745 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2746
2747 /*
2748 * The possible values of fc.current_mode are:
2749 * 0: Flow control is completely disabled
2750 * 1: Rx flow control is enabled (we can receive pause frames,
2751 * but not send pause frames).
2752 * 2: Tx flow control is enabled (we can send pause frames but
2753 * we do not support receiving pause frames).
2754 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2755 * other: Invalid.
2756 */
2757 switch (hw->fc.current_mode) {
2758 case ixgbe_fc_none:
2759 /*
2760 * Flow control is disabled by software override or autoneg.
2761 * The code below will actually disable it in the HW.
2762 */
2763 break;
2764 case ixgbe_fc_rx_pause:
2765 /*
2766 * Rx Flow control is enabled and Tx Flow control is
2767 * disabled by software override. Since there really
2768 * isn't a way to advertise that we are capable of RX
2769 * Pause ONLY, we will advertise that we support both
2770 * symmetric and asymmetric Rx PAUSE. Later, we will
2771 * disable the adapter's ability to send PAUSE frames.
2772 */
2773 mflcn_reg |= IXGBE_MFLCN_RFCE;
2774 break;
2775 case ixgbe_fc_tx_pause:
2776 /*
2777 * Tx Flow control is enabled, and Rx Flow control is
2778 * disabled by software override.
2779 */
2780 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2781 break;
2782 case ixgbe_fc_full:
2783 /* Flow control (both Rx and Tx) is enabled by SW override. */
2784 mflcn_reg |= IXGBE_MFLCN_RFCE;
2785 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2786 break;
2787 default:
2788 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2789 "Flow control param set incorrectly\n");
2790 ret_val = IXGBE_ERR_CONFIG;
2791 goto out;
2792 break;
2793 }
2794
2795 /* Set 802.3x based flow control settings. */
2796 mflcn_reg |= IXGBE_MFLCN_DPF;
2797 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2798 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2799
2800
2801 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2802 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2803 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2804 hw->fc.high_water[i]) {
2805 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2806 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2807 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2808 } else {
2809 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2810 /*
2811 * In order to prevent Tx hangs when the internal Tx
2812 * switch is enabled we must set the high water mark
2813 * to the Rx packet buffer size - 24KB. This allows
2814 * the Tx switch to function even under heavy Rx
2815 * workloads.
2816 */
2817 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2818 }
2819
2820 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2821 }
2822
2823 /* Configure pause time (2 TCs per register) */
2824 reg = hw->fc.pause_time * 0x00010001;
2825 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2826 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2827
2828 /* Configure flow control refresh threshold value */
2829 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2830
2831 out:
2832 return ret_val;
2833 }
2834
2835 /**
2836 * ixgbe_negotiate_fc - Negotiate flow control
2837 * @hw: pointer to hardware structure
2838 * @adv_reg: flow control advertised settings
2839 * @lp_reg: link partner's flow control settings
2840 * @adv_sym: symmetric pause bit in advertisement
2841 * @adv_asm: asymmetric pause bit in advertisement
2842 * @lp_sym: symmetric pause bit in link partner advertisement
2843 * @lp_asm: asymmetric pause bit in link partner advertisement
2844 *
2845 * Find the intersection between advertised settings and link partner's
2846 * advertised settings
2847 **/
ixgbe_negotiate_fc(struct ixgbe_hw * hw,u32 adv_reg,u32 lp_reg,u32 adv_sym,u32 adv_asm,u32 lp_sym,u32 lp_asm)2848 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2849 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2850 {
2851 if ((!(adv_reg)) || (!(lp_reg))) {
2852 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2853 "Local or link partner's advertised flow control "
2854 "settings are NULL. Local: %x, link partner: %x\n",
2855 adv_reg, lp_reg);
2856 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2857 }
2858
2859 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2860 /*
2861 * Now we need to check if the user selected Rx ONLY
2862 * of pause frames. In this case, we had to advertise
2863 * FULL flow control because we could not advertise RX
2864 * ONLY. Hence, we must now check to see if we need to
2865 * turn OFF the TRANSMISSION of PAUSE frames.
2866 */
2867 if (hw->fc.requested_mode == ixgbe_fc_full) {
2868 hw->fc.current_mode = ixgbe_fc_full;
2869 DEBUGOUT("Flow Control = FULL.\n");
2870 } else {
2871 hw->fc.current_mode = ixgbe_fc_rx_pause;
2872 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2873 }
2874 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2875 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2876 hw->fc.current_mode = ixgbe_fc_tx_pause;
2877 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2878 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2879 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2880 hw->fc.current_mode = ixgbe_fc_rx_pause;
2881 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2882 } else {
2883 hw->fc.current_mode = ixgbe_fc_none;
2884 DEBUGOUT("Flow Control = NONE.\n");
2885 }
2886 return IXGBE_SUCCESS;
2887 }
2888
2889 /**
2890 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2891 * @hw: pointer to hardware structure
2892 *
2893 * Enable flow control according on 1 gig fiber.
2894 **/
ixgbe_fc_autoneg_fiber(struct ixgbe_hw * hw)2895 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2896 {
2897 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2898 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2899
2900 /*
2901 * On multispeed fiber at 1g, bail out if
2902 * - link is up but AN did not complete, or if
2903 * - link is up and AN completed but timed out
2904 */
2905
2906 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2907 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2908 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2909 DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
2910 goto out;
2911 }
2912
2913 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2914 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2915
2916 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2917 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2918 IXGBE_PCS1GANA_ASM_PAUSE,
2919 IXGBE_PCS1GANA_SYM_PAUSE,
2920 IXGBE_PCS1GANA_ASM_PAUSE);
2921
2922 out:
2923 return ret_val;
2924 }
2925
2926 /**
2927 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2928 * @hw: pointer to hardware structure
2929 *
2930 * Enable flow control according to IEEE clause 37.
2931 **/
ixgbe_fc_autoneg_backplane(struct ixgbe_hw * hw)2932 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2933 {
2934 u32 links2, anlp1_reg, autoc_reg, links;
2935 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2936
2937 /*
2938 * On backplane, bail out if
2939 * - backplane autoneg was not completed, or if
2940 * - we are 82599 and link partner is not AN enabled
2941 */
2942 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2943 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
2944 DEBUGOUT("Auto-Negotiation did not complete\n");
2945 goto out;
2946 }
2947
2948 if (hw->mac.type == ixgbe_mac_82599EB) {
2949 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2950 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2951 DEBUGOUT("Link partner is not AN enabled\n");
2952 goto out;
2953 }
2954 }
2955 /*
2956 * Read the 10g AN autoc and LP ability registers and resolve
2957 * local flow control settings accordingly
2958 */
2959 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2960 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2961
2962 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2963 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2964 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2965
2966 out:
2967 return ret_val;
2968 }
2969
2970 /**
2971 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2972 * @hw: pointer to hardware structure
2973 *
2974 * Enable flow control according to IEEE clause 37.
2975 **/
ixgbe_fc_autoneg_copper(struct ixgbe_hw * hw)2976 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2977 {
2978 u16 technology_ability_reg = 0;
2979 u16 lp_technology_ability_reg = 0;
2980
2981 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2982 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2983 &technology_ability_reg);
2984 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
2985 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2986 &lp_technology_ability_reg);
2987
2988 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2989 (u32)lp_technology_ability_reg,
2990 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2991 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2992 }
2993
2994 /**
2995 * ixgbe_fc_autoneg - Configure flow control
2996 * @hw: pointer to hardware structure
2997 *
2998 * Compares our advertised flow control capabilities to those advertised by
2999 * our link partner, and determines the proper flow control mode to use.
3000 **/
ixgbe_fc_autoneg(struct ixgbe_hw * hw)3001 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
3002 {
3003 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3004 ixgbe_link_speed speed;
3005 bool link_up;
3006
3007 DEBUGFUNC("ixgbe_fc_autoneg");
3008
3009 /*
3010 * AN should have completed when the cable was plugged in.
3011 * Look for reasons to bail out. Bail out if:
3012 * - FC autoneg is disabled, or if
3013 * - link is not up.
3014 */
3015 if (hw->fc.disable_fc_autoneg) {
3016 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3017 "Flow control autoneg is disabled");
3018 goto out;
3019 }
3020
3021 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
3022 if (!link_up) {
3023 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3024 goto out;
3025 }
3026
3027 switch (hw->phy.media_type) {
3028 /* Autoneg flow control on fiber adapters */
3029 case ixgbe_media_type_fiber_fixed:
3030 case ixgbe_media_type_fiber_qsfp:
3031 case ixgbe_media_type_fiber:
3032 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3033 ret_val = ixgbe_fc_autoneg_fiber(hw);
3034 break;
3035
3036 /* Autoneg flow control on backplane adapters */
3037 case ixgbe_media_type_backplane:
3038 ret_val = ixgbe_fc_autoneg_backplane(hw);
3039 break;
3040
3041 /* Autoneg flow control on copper adapters */
3042 case ixgbe_media_type_copper:
3043 if (ixgbe_device_supports_autoneg_fc(hw))
3044 ret_val = ixgbe_fc_autoneg_copper(hw);
3045 break;
3046
3047 default:
3048 break;
3049 }
3050
3051 out:
3052 if (ret_val == IXGBE_SUCCESS) {
3053 hw->fc.fc_was_autonegged = TRUE;
3054 } else {
3055 hw->fc.fc_was_autonegged = FALSE;
3056 hw->fc.current_mode = hw->fc.requested_mode;
3057 }
3058 }
3059
3060 /*
3061 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3062 * @hw: pointer to hardware structure
3063 *
3064 * System-wide timeout range is encoded in PCIe Device Control2 register.
3065 *
3066 * Add 10% to specified maximum and return the number of times to poll for
3067 * completion timeout, in units of 100 microsec. Never return less than
3068 * 800 = 80 millisec.
3069 */
ixgbe_pcie_timeout_poll(struct ixgbe_hw * hw)3070 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3071 {
3072 s16 devctl2;
3073 u32 pollcnt;
3074
3075 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3076 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3077
3078 switch (devctl2) {
3079 case IXGBE_PCIDEVCTRL2_65_130ms:
3080 pollcnt = 1300; /* 130 millisec */
3081 break;
3082 case IXGBE_PCIDEVCTRL2_260_520ms:
3083 pollcnt = 5200; /* 520 millisec */
3084 break;
3085 case IXGBE_PCIDEVCTRL2_1_2s:
3086 pollcnt = 20000; /* 2 sec */
3087 break;
3088 case IXGBE_PCIDEVCTRL2_4_8s:
3089 pollcnt = 80000; /* 8 sec */
3090 break;
3091 case IXGBE_PCIDEVCTRL2_17_34s:
3092 pollcnt = 34000; /* 34 sec */
3093 break;
3094 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3095 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3096 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3097 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3098 default:
3099 pollcnt = 800; /* 80 millisec minimum */
3100 break;
3101 }
3102
3103 /* add 10% to spec maximum */
3104 return (pollcnt * 11) / 10;
3105 }
3106
3107 /**
3108 * ixgbe_disable_pcie_master - Disable PCI-express master access
3109 * @hw: pointer to hardware structure
3110 *
3111 * Disables PCI-Express master access and verifies there are no pending
3112 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3113 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3114 * is returned signifying master requests disabled.
3115 **/
ixgbe_disable_pcie_master(struct ixgbe_hw * hw)3116 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3117 {
3118 s32 status = IXGBE_SUCCESS;
3119 u32 i, poll;
3120 u16 value;
3121
3122 DEBUGFUNC("ixgbe_disable_pcie_master");
3123
3124 /* Always set this bit to ensure any future transactions are blocked */
3125 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3126
3127 /* Exit if master requests are blocked */
3128 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3129 IXGBE_REMOVED(hw->hw_addr))
3130 goto out;
3131
3132 /* Poll for master request bit to clear */
3133 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3134 usec_delay(100);
3135 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3136 goto out;
3137 }
3138
3139 /*
3140 * Two consecutive resets are required via CTRL.RST per datasheet
3141 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3142 * of this need. The first reset prevents new master requests from
3143 * being issued by our device. We then must wait 1usec or more for any
3144 * remaining completions from the PCIe bus to trickle in, and then reset
3145 * again to clear out any effects they may have had on our device.
3146 */
3147 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3148 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3149
3150 /*
3151 * Before proceeding, make sure that the PCIe block does not have
3152 * transactions pending.
3153 */
3154 poll = ixgbe_pcie_timeout_poll(hw);
3155 for (i = 0; i < poll; i++) {
3156 usec_delay(100);
3157 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3158 if (IXGBE_REMOVED(hw->hw_addr))
3159 goto out;
3160 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3161 goto out;
3162 }
3163
3164 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3165 "PCIe transaction pending bit also did not clear.\n");
3166 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3167
3168 out:
3169 return status;
3170 }
3171
3172 /**
3173 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3174 * @hw: pointer to hardware structure
3175 * @mask: Mask to specify which semaphore to acquire
3176 *
3177 * Acquires the SWFW semaphore through the GSSR register for the specified
3178 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3179 **/
ixgbe_acquire_swfw_sync(struct ixgbe_hw * hw,u32 mask)3180 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3181 {
3182 u32 gssr = 0;
3183 u32 swmask = mask;
3184 u32 fwmask = mask << 5;
3185 u32 timeout = 200;
3186 u32 i;
3187
3188 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3189
3190 for (i = 0; i < timeout; i++) {
3191 /*
3192 * SW NVM semaphore bit is used for access to all
3193 * SW_FW_SYNC bits (not just NVM)
3194 */
3195 if (ixgbe_get_eeprom_semaphore(hw))
3196 return IXGBE_ERR_SWFW_SYNC;
3197
3198 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3199 if (!(gssr & (fwmask | swmask))) {
3200 gssr |= swmask;
3201 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3202 ixgbe_release_eeprom_semaphore(hw);
3203 return IXGBE_SUCCESS;
3204 } else {
3205 /* Resource is currently in use by FW or SW */
3206 ixgbe_release_eeprom_semaphore(hw);
3207 msec_delay(5);
3208 }
3209 }
3210
3211 /* If time expired clear the bits holding the lock and retry */
3212 if (gssr & (fwmask | swmask))
3213 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3214
3215 msec_delay(5);
3216 return IXGBE_ERR_SWFW_SYNC;
3217 }
3218
3219 /**
3220 * ixgbe_release_swfw_sync - Release SWFW semaphore
3221 * @hw: pointer to hardware structure
3222 * @mask: Mask to specify which semaphore to release
3223 *
3224 * Releases the SWFW semaphore through the GSSR register for the specified
3225 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3226 **/
ixgbe_release_swfw_sync(struct ixgbe_hw * hw,u32 mask)3227 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3228 {
3229 u32 gssr;
3230 u32 swmask = mask;
3231
3232 DEBUGFUNC("ixgbe_release_swfw_sync");
3233
3234 ixgbe_get_eeprom_semaphore(hw);
3235
3236 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3237 gssr &= ~swmask;
3238 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3239
3240 ixgbe_release_eeprom_semaphore(hw);
3241 }
3242
3243 /**
3244 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3245 * @hw: pointer to hardware structure
3246 *
3247 * Stops the receive data path and waits for the HW to internally empty
3248 * the Rx security block
3249 **/
ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw * hw)3250 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3251 {
3252 #define IXGBE_MAX_SECRX_POLL 40
3253
3254 int i;
3255 int secrxreg;
3256
3257 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3258
3259
3260 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3261 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3262 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3263 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3264 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3265 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3266 break;
3267 else
3268 /* Use interrupt-safe sleep just in case */
3269 usec_delay(1000);
3270 }
3271
3272 /* For informational purposes only */
3273 if (i >= IXGBE_MAX_SECRX_POLL)
3274 DEBUGOUT("Rx unit being enabled before security "
3275 "path fully disabled. Continuing with init.\n");
3276
3277 return IXGBE_SUCCESS;
3278 }
3279
3280 /**
3281 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3282 * @hw: pointer to hardware structure
3283 * @reg_val: Value we read from AUTOC
3284 *
3285 * The default case requires no protection so just to the register read.
3286 */
prot_autoc_read_generic(struct ixgbe_hw * hw,bool * locked,u32 * reg_val)3287 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3288 {
3289 *locked = FALSE;
3290 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3291 return IXGBE_SUCCESS;
3292 }
3293
3294 /**
3295 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3296 * @hw: pointer to hardware structure
3297 * @reg_val: value to write to AUTOC
3298 * @locked: bool to indicate whether the SW/FW lock was already taken by
3299 * previous read.
3300 *
3301 * The default case requires no protection so just to the register write.
3302 */
prot_autoc_write_generic(struct ixgbe_hw * hw,u32 reg_val,bool locked)3303 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3304 {
3305 UNREFERENCED_1PARAMETER(locked);
3306
3307 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3308 return IXGBE_SUCCESS;
3309 }
3310
3311 /**
3312 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3313 * @hw: pointer to hardware structure
3314 *
3315 * Enables the receive data path.
3316 **/
ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw * hw)3317 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3318 {
3319 int secrxreg;
3320
3321 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3322
3323 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3324 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3325 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3326 IXGBE_WRITE_FLUSH(hw);
3327
3328 return IXGBE_SUCCESS;
3329 }
3330
3331 /**
3332 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3333 * @hw: pointer to hardware structure
3334 * @regval: register value to write to RXCTRL
3335 *
3336 * Enables the Rx DMA unit
3337 **/
ixgbe_enable_rx_dma_generic(struct ixgbe_hw * hw,u32 regval)3338 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3339 {
3340 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3341
3342 if (regval & IXGBE_RXCTRL_RXEN)
3343 ixgbe_enable_rx(hw);
3344 else
3345 ixgbe_disable_rx(hw);
3346
3347 return IXGBE_SUCCESS;
3348 }
3349
3350 /**
3351 * ixgbe_blink_led_start_generic - Blink LED based on index.
3352 * @hw: pointer to hardware structure
3353 * @index: led number to blink
3354 **/
ixgbe_blink_led_start_generic(struct ixgbe_hw * hw,u32 index)3355 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3356 {
3357 ixgbe_link_speed speed = 0;
3358 bool link_up = 0;
3359 u32 autoc_reg = 0;
3360 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3361 s32 ret_val = IXGBE_SUCCESS;
3362 bool locked = FALSE;
3363
3364 DEBUGFUNC("ixgbe_blink_led_start_generic");
3365
3366 /*
3367 * Link must be up to auto-blink the LEDs;
3368 * Force it if link is down.
3369 */
3370 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
3371
3372 if (!link_up) {
3373 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3374 if (ret_val != IXGBE_SUCCESS)
3375 goto out;
3376
3377 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3378 autoc_reg |= IXGBE_AUTOC_FLU;
3379
3380 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3381 if (ret_val != IXGBE_SUCCESS)
3382 goto out;
3383
3384 IXGBE_WRITE_FLUSH(hw);
3385 msec_delay(10);
3386 }
3387
3388 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3389 led_reg |= IXGBE_LED_BLINK(index);
3390 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3391 IXGBE_WRITE_FLUSH(hw);
3392
3393 out:
3394 return ret_val;
3395 }
3396
3397 /**
3398 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3399 * @hw: pointer to hardware structure
3400 * @index: led number to stop blinking
3401 **/
ixgbe_blink_led_stop_generic(struct ixgbe_hw * hw,u32 index)3402 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3403 {
3404 u32 autoc_reg = 0;
3405 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3406 s32 ret_val = IXGBE_SUCCESS;
3407 bool locked = FALSE;
3408
3409 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3410
3411 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3412 if (ret_val != IXGBE_SUCCESS)
3413 goto out;
3414
3415 autoc_reg &= ~IXGBE_AUTOC_FLU;
3416 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3417
3418 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3419 if (ret_val != IXGBE_SUCCESS)
3420 goto out;
3421
3422 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3423 led_reg &= ~IXGBE_LED_BLINK(index);
3424 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3425 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3426 IXGBE_WRITE_FLUSH(hw);
3427
3428 out:
3429 return ret_val;
3430 }
3431
3432 /**
3433 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3434 * @hw: pointer to hardware structure
3435 * @san_mac_offset: SAN MAC address offset
3436 *
3437 * This function will read the EEPROM location for the SAN MAC address
3438 * pointer, and returns the value at that location. This is used in both
3439 * get and set mac_addr routines.
3440 **/
ixgbe_get_san_mac_addr_offset(struct ixgbe_hw * hw,u16 * san_mac_offset)3441 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3442 u16 *san_mac_offset)
3443 {
3444 s32 ret_val;
3445
3446 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3447
3448 /*
3449 * First read the EEPROM pointer to see if the MAC addresses are
3450 * available.
3451 */
3452 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3453 san_mac_offset);
3454 if (ret_val) {
3455 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3456 "eeprom at offset %d failed",
3457 IXGBE_SAN_MAC_ADDR_PTR);
3458 }
3459
3460 return ret_val;
3461 }
3462
3463 /**
3464 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3465 * @hw: pointer to hardware structure
3466 * @san_mac_addr: SAN MAC address
3467 *
3468 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3469 * per-port, so set_lan_id() must be called before reading the addresses.
3470 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3471 * upon for non-SFP connections, so we must call it here.
3472 **/
ixgbe_get_san_mac_addr_generic(struct ixgbe_hw * hw,u8 * san_mac_addr)3473 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3474 {
3475 u16 san_mac_data, san_mac_offset;
3476 u8 i;
3477 s32 ret_val;
3478
3479 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3480
3481 /*
3482 * First read the EEPROM pointer to see if the MAC addresses are
3483 * available. If they're not, no point in calling set_lan_id() here.
3484 */
3485 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3486 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3487 goto san_mac_addr_out;
3488
3489 /* make sure we know which port we need to program */
3490 hw->mac.ops.set_lan_id(hw);
3491 /* apply the port offset to the address offset */
3492 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3493 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3494 for (i = 0; i < 3; i++) {
3495 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3496 &san_mac_data);
3497 if (ret_val) {
3498 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3499 "eeprom read at offset %d failed",
3500 san_mac_offset);
3501 goto san_mac_addr_out;
3502 }
3503 san_mac_addr[i * 2] = (u8)(san_mac_data);
3504 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3505 san_mac_offset++;
3506 }
3507 return IXGBE_SUCCESS;
3508
3509 san_mac_addr_out:
3510 /*
3511 * No addresses available in this EEPROM. It's not an
3512 * error though, so just wipe the local address and return.
3513 */
3514 for (i = 0; i < 6; i++)
3515 san_mac_addr[i] = 0xFF;
3516 return IXGBE_SUCCESS;
3517 }
3518
3519 /**
3520 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3521 * @hw: pointer to hardware structure
3522 * @san_mac_addr: SAN MAC address
3523 *
3524 * Write a SAN MAC address to the EEPROM.
3525 **/
ixgbe_set_san_mac_addr_generic(struct ixgbe_hw * hw,u8 * san_mac_addr)3526 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3527 {
3528 s32 ret_val;
3529 u16 san_mac_data, san_mac_offset;
3530 u8 i;
3531
3532 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3533
3534 /* Look for SAN mac address pointer. If not defined, return */
3535 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3536 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3537 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3538
3539 /* Make sure we know which port we need to write */
3540 hw->mac.ops.set_lan_id(hw);
3541 /* Apply the port offset to the address offset */
3542 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3543 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3544
3545 for (i = 0; i < 3; i++) {
3546 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3547 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3548 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3549 san_mac_offset++;
3550 }
3551
3552 return IXGBE_SUCCESS;
3553 }
3554
3555 /**
3556 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3557 * @hw: pointer to hardware structure
3558 *
3559 * Read PCIe configuration space, and get the MSI-X vector count from
3560 * the capabilities table.
3561 **/
ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw * hw)3562 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3563 {
3564 u16 msix_count = 1;
3565 u16 max_msix_count;
3566 u16 pcie_offset;
3567
3568 switch (hw->mac.type) {
3569 case ixgbe_mac_82598EB:
3570 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3571 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3572 break;
3573 case ixgbe_mac_82599EB:
3574 case ixgbe_mac_X540:
3575 case ixgbe_mac_X550:
3576 case ixgbe_mac_X550EM_x:
3577 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3578 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3579 break;
3580 default:
3581 return msix_count;
3582 }
3583
3584 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3585 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3586 if (IXGBE_REMOVED(hw->hw_addr))
3587 msix_count = 0;
3588 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3589
3590 /* MSI-X count is zero-based in HW */
3591 msix_count++;
3592
3593 if (msix_count > max_msix_count)
3594 msix_count = max_msix_count;
3595
3596 return msix_count;
3597 }
3598
3599 /**
3600 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3601 * @hw: pointer to hardware structure
3602 * @addr: Address to put into receive address register
3603 * @vmdq: VMDq pool to assign
3604 *
3605 * Puts an ethernet address into a receive address register, or
3606 * finds the rar that it is aleady in; adds to the pool list
3607 **/
ixgbe_insert_mac_addr_generic(struct ixgbe_hw * hw,u8 * addr,u32 vmdq)3608 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3609 {
3610 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3611 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3612 u32 rar;
3613 u32 rar_low, rar_high;
3614 u32 addr_low, addr_high;
3615
3616 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3617
3618 /* swap bytes for HW little endian */
3619 addr_low = addr[0] | (addr[1] << 8)
3620 | (addr[2] << 16)
3621 | (addr[3] << 24);
3622 addr_high = addr[4] | (addr[5] << 8);
3623
3624 /*
3625 * Either find the mac_id in rar or find the first empty space.
3626 * rar_highwater points to just after the highest currently used
3627 * rar in order to shorten the search. It grows when we add a new
3628 * rar to the top.
3629 */
3630 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3631 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3632
3633 if (((IXGBE_RAH_AV & rar_high) == 0)
3634 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3635 first_empty_rar = rar;
3636 } else if ((rar_high & 0xFFFF) == addr_high) {
3637 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3638 if (rar_low == addr_low)
3639 break; /* found it already in the rars */
3640 }
3641 }
3642
3643 if (rar < hw->mac.rar_highwater) {
3644 /* already there so just add to the pool bits */
3645 ixgbe_set_vmdq(hw, rar, vmdq);
3646 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3647 /* stick it into first empty RAR slot we found */
3648 rar = first_empty_rar;
3649 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3650 } else if (rar == hw->mac.rar_highwater) {
3651 /* add it to the top of the list and inc the highwater mark */
3652 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3653 hw->mac.rar_highwater++;
3654 } else if (rar >= hw->mac.num_rar_entries) {
3655 return IXGBE_ERR_INVALID_MAC_ADDR;
3656 }
3657
3658 /*
3659 * If we found rar[0], make sure the default pool bit (we use pool 0)
3660 * remains cleared to be sure default pool packets will get delivered
3661 */
3662 if (rar == 0)
3663 ixgbe_clear_vmdq(hw, rar, 0);
3664
3665 return rar;
3666 }
3667
3668 /**
3669 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3670 * @hw: pointer to hardware struct
3671 * @rar: receive address register index to disassociate
3672 * @vmdq: VMDq pool index to remove from the rar
3673 **/
ixgbe_clear_vmdq_generic(struct ixgbe_hw * hw,u32 rar,u32 vmdq)3674 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3675 {
3676 u32 mpsar_lo, mpsar_hi;
3677 u32 rar_entries = hw->mac.num_rar_entries;
3678
3679 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3680
3681 /* Make sure we are using a valid rar index range */
3682 if (rar >= rar_entries) {
3683 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3684 "RAR index %d is out of range.\n", rar);
3685 return IXGBE_ERR_INVALID_ARGUMENT;
3686 }
3687
3688 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3689 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3690
3691 if (IXGBE_REMOVED(hw->hw_addr))
3692 goto done;
3693
3694 if (!mpsar_lo && !mpsar_hi)
3695 goto done;
3696
3697 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3698 if (mpsar_lo) {
3699 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3700 mpsar_lo = 0;
3701 }
3702 if (mpsar_hi) {
3703 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3704 mpsar_hi = 0;
3705 }
3706 } else if (vmdq < 32) {
3707 mpsar_lo &= ~(1 << vmdq);
3708 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3709 } else {
3710 mpsar_hi &= ~(1 << (vmdq - 32));
3711 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3712 }
3713
3714 /* was that the last pool using this rar? */
3715 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3716 hw->mac.ops.clear_rar(hw, rar);
3717 done:
3718 return IXGBE_SUCCESS;
3719 }
3720
3721 /**
3722 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3723 * @hw: pointer to hardware struct
3724 * @rar: receive address register index to associate with a VMDq index
3725 * @vmdq: VMDq pool index
3726 **/
ixgbe_set_vmdq_generic(struct ixgbe_hw * hw,u32 rar,u32 vmdq)3727 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3728 {
3729 u32 mpsar;
3730 u32 rar_entries = hw->mac.num_rar_entries;
3731
3732 DEBUGFUNC("ixgbe_set_vmdq_generic");
3733
3734 /* Make sure we are using a valid rar index range */
3735 if (rar >= rar_entries) {
3736 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3737 "RAR index %d is out of range.\n", rar);
3738 return IXGBE_ERR_INVALID_ARGUMENT;
3739 }
3740
3741 if (vmdq < 32) {
3742 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3743 mpsar |= 1 << vmdq;
3744 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3745 } else {
3746 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3747 mpsar |= 1 << (vmdq - 32);
3748 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3749 }
3750 return IXGBE_SUCCESS;
3751 }
3752
3753 /**
3754 * This function should only be involved in the IOV mode.
3755 * In IOV mode, Default pool is next pool after the number of
3756 * VFs advertized and not 0.
3757 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3758 *
3759 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3760 * @hw: pointer to hardware struct
3761 * @vmdq: VMDq pool index
3762 **/
ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw * hw,u32 vmdq)3763 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3764 {
3765 u32 rar = hw->mac.san_mac_rar_index;
3766
3767 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3768
3769 if (vmdq < 32) {
3770 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3771 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3772 } else {
3773 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3774 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3775 }
3776
3777 return IXGBE_SUCCESS;
3778 }
3779
3780 /**
3781 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3782 * @hw: pointer to hardware structure
3783 **/
ixgbe_init_uta_tables_generic(struct ixgbe_hw * hw)3784 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3785 {
3786 int i;
3787
3788 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3789 DEBUGOUT(" Clearing UTA\n");
3790
3791 for (i = 0; i < 128; i++)
3792 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3793
3794 return IXGBE_SUCCESS;
3795 }
3796
3797 /**
3798 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3799 * @hw: pointer to hardware structure
3800 * @vlan: VLAN id to write to VLAN filter
3801 *
3802 * return the VLVF index where this VLAN id should be placed
3803 *
3804 **/
ixgbe_find_vlvf_slot(struct ixgbe_hw * hw,u32 vlan)3805 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
3806 {
3807 u32 bits = 0;
3808 u32 first_empty_slot = 0;
3809 s32 regindex;
3810
3811 /* short cut the special case */
3812 if (vlan == 0)
3813 return 0;
3814
3815 /*
3816 * Search for the vlan id in the VLVF entries. Save off the first empty
3817 * slot found along the way
3818 */
3819 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3820 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3821 if (!bits && !(first_empty_slot))
3822 first_empty_slot = regindex;
3823 else if ((bits & 0x0FFF) == vlan)
3824 break;
3825 }
3826
3827 /*
3828 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3829 * in the VLVF. Else use the first empty VLVF register for this
3830 * vlan id.
3831 */
3832 if (regindex >= IXGBE_VLVF_ENTRIES) {
3833 if (first_empty_slot)
3834 regindex = first_empty_slot;
3835 else {
3836 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
3837 "No space in VLVF.\n");
3838 regindex = IXGBE_ERR_NO_SPACE;
3839 }
3840 }
3841
3842 return regindex;
3843 }
3844
3845 /**
3846 * ixgbe_set_vfta_generic - Set VLAN filter table
3847 * @hw: pointer to hardware structure
3848 * @vlan: VLAN id to write to VLAN filter
3849 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3850 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3851 *
3852 * Turn on/off specified VLAN in the VLAN filter table.
3853 **/
ixgbe_set_vfta_generic(struct ixgbe_hw * hw,u32 vlan,u32 vind,bool vlan_on)3854 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3855 bool vlan_on)
3856 {
3857 s32 regindex;
3858 u32 bitindex;
3859 u32 vfta;
3860 u32 targetbit;
3861 s32 ret_val = IXGBE_SUCCESS;
3862 bool vfta_changed = FALSE;
3863
3864 DEBUGFUNC("ixgbe_set_vfta_generic");
3865
3866 if (vlan > 4095)
3867 return IXGBE_ERR_PARAM;
3868
3869 /*
3870 * this is a 2 part operation - first the VFTA, then the
3871 * VLVF and VLVFB if VT Mode is set
3872 * We don't write the VFTA until we know the VLVF part succeeded.
3873 */
3874
3875 /* Part 1
3876 * The VFTA is a bitstring made up of 128 32-bit registers
3877 * that enable the particular VLAN id, much like the MTA:
3878 * bits[11-5]: which register
3879 * bits[4-0]: which bit in the register
3880 */
3881 regindex = (vlan >> 5) & 0x7F;
3882 bitindex = vlan & 0x1F;
3883 targetbit = (1 << bitindex);
3884 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3885
3886 if (vlan_on) {
3887 if (!(vfta & targetbit)) {
3888 vfta |= targetbit;
3889 vfta_changed = TRUE;
3890 }
3891 } else {
3892 if ((vfta & targetbit)) {
3893 vfta &= ~targetbit;
3894 vfta_changed = TRUE;
3895 }
3896 }
3897
3898 /* Part 2
3899 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3900 */
3901 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,
3902 &vfta_changed);
3903 if (ret_val != IXGBE_SUCCESS)
3904 return ret_val;
3905
3906 if (vfta_changed)
3907 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3908
3909 return IXGBE_SUCCESS;
3910 }
3911
3912 /**
3913 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3914 * @hw: pointer to hardware structure
3915 * @vlan: VLAN id to write to VLAN filter
3916 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3917 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3918 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
3919 * should be changed
3920 *
3921 * Turn on/off specified bit in VLVF table.
3922 **/
ixgbe_set_vlvf_generic(struct ixgbe_hw * hw,u32 vlan,u32 vind,bool vlan_on,bool * vfta_changed)3923 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3924 bool vlan_on, bool *vfta_changed)
3925 {
3926 u32 vt;
3927
3928 DEBUGFUNC("ixgbe_set_vlvf_generic");
3929
3930 if (vlan > 4095)
3931 return IXGBE_ERR_PARAM;
3932
3933 /* If VT Mode is set
3934 * Either vlan_on
3935 * make sure the vlan is in VLVF
3936 * set the vind bit in the matching VLVFB
3937 * Or !vlan_on
3938 * clear the pool bit and possibly the vind
3939 */
3940 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3941 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3942 s32 vlvf_index;
3943 u32 bits;
3944
3945 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3946 if (vlvf_index < 0)
3947 return vlvf_index;
3948
3949 if (vlan_on) {
3950 /* set the pool bit */
3951 if (vind < 32) {
3952 bits = IXGBE_READ_REG(hw,
3953 IXGBE_VLVFB(vlvf_index * 2));
3954 bits |= (1 << vind);
3955 IXGBE_WRITE_REG(hw,
3956 IXGBE_VLVFB(vlvf_index * 2),
3957 bits);
3958 } else {
3959 bits = IXGBE_READ_REG(hw,
3960 IXGBE_VLVFB((vlvf_index * 2) + 1));
3961 bits |= (1 << (vind - 32));
3962 IXGBE_WRITE_REG(hw,
3963 IXGBE_VLVFB((vlvf_index * 2) + 1),
3964 bits);
3965 }
3966 } else {
3967 /* clear the pool bit */
3968 if (vind < 32) {
3969 bits = IXGBE_READ_REG(hw,
3970 IXGBE_VLVFB(vlvf_index * 2));
3971 bits &= ~(1 << vind);
3972 IXGBE_WRITE_REG(hw,
3973 IXGBE_VLVFB(vlvf_index * 2),
3974 bits);
3975 bits |= IXGBE_READ_REG(hw,
3976 IXGBE_VLVFB((vlvf_index * 2) + 1));
3977 } else {
3978 bits = IXGBE_READ_REG(hw,
3979 IXGBE_VLVFB((vlvf_index * 2) + 1));
3980 bits &= ~(1 << (vind - 32));
3981 IXGBE_WRITE_REG(hw,
3982 IXGBE_VLVFB((vlvf_index * 2) + 1),
3983 bits);
3984 bits |= IXGBE_READ_REG(hw,
3985 IXGBE_VLVFB(vlvf_index * 2));
3986 }
3987 }
3988
3989 /*
3990 * If there are still bits set in the VLVFB registers
3991 * for the VLAN ID indicated we need to see if the
3992 * caller is requesting that we clear the VFTA entry bit.
3993 * If the caller has requested that we clear the VFTA
3994 * entry bit but there are still pools/VFs using this VLAN
3995 * ID entry then ignore the request. We're not worried
3996 * about the case where we're turning the VFTA VLAN ID
3997 * entry bit on, only when requested to turn it off as
3998 * there may be multiple pools and/or VFs using the
3999 * VLAN ID entry. In that case we cannot clear the
4000 * VFTA bit until all pools/VFs using that VLAN ID have also
4001 * been cleared. This will be indicated by "bits" being
4002 * zero.
4003 */
4004 if (bits) {
4005 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
4006 (IXGBE_VLVF_VIEN | vlan));
4007 if ((!vlan_on) && (vfta_changed != NULL)) {
4008 /* someone wants to clear the vfta entry
4009 * but some pools/VFs are still using it.
4010 * Ignore it. */
4011 *vfta_changed = FALSE;
4012 }
4013 } else
4014 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4015 }
4016
4017 return IXGBE_SUCCESS;
4018 }
4019
4020 /**
4021 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4022 * @hw: pointer to hardware structure
4023 *
4024 * Clears the VLAN filer table, and the VMDq index associated with the filter
4025 **/
ixgbe_clear_vfta_generic(struct ixgbe_hw * hw)4026 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4027 {
4028 u32 offset;
4029
4030 DEBUGFUNC("ixgbe_clear_vfta_generic");
4031
4032 for (offset = 0; offset < hw->mac.vft_size; offset++)
4033 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4034
4035 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4036 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4037 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4038 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
4039 }
4040
4041 return IXGBE_SUCCESS;
4042 }
4043
4044 /**
4045 * ixgbe_check_mac_link_generic - Determine link and speed status
4046 * @hw: pointer to hardware structure
4047 * @speed: pointer to link speed
4048 * @link_up: TRUE when link is up
4049 * @link_up_wait_to_complete: bool used to wait for link up or not
4050 *
4051 * Reads the links register to determine if link is up and the current speed
4052 **/
ixgbe_check_mac_link_generic(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * link_up,bool link_up_wait_to_complete)4053 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4054 bool *link_up, bool link_up_wait_to_complete)
4055 {
4056 u32 links_reg, links_orig;
4057 u32 i;
4058
4059 DEBUGFUNC("ixgbe_check_mac_link_generic");
4060
4061 /* clear the old state */
4062 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4063
4064 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4065
4066 if (links_orig != links_reg) {
4067 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4068 links_orig, links_reg);
4069 }
4070
4071 if (link_up_wait_to_complete) {
4072 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
4073 if (links_reg & IXGBE_LINKS_UP) {
4074 *link_up = TRUE;
4075 break;
4076 } else {
4077 *link_up = FALSE;
4078 }
4079 msec_delay(100);
4080 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4081 }
4082 } else {
4083 if (links_reg & IXGBE_LINKS_UP)
4084 *link_up = TRUE;
4085 else
4086 *link_up = FALSE;
4087 }
4088
4089 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4090 case IXGBE_LINKS_SPEED_10G_82599:
4091 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4092 if (hw->mac.type >= ixgbe_mac_X550) {
4093 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4094 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4095 }
4096 break;
4097 case IXGBE_LINKS_SPEED_1G_82599:
4098 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4099 break;
4100 case IXGBE_LINKS_SPEED_100_82599:
4101 *speed = IXGBE_LINK_SPEED_100_FULL;
4102 if (hw->mac.type >= ixgbe_mac_X550) {
4103 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4104 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4105 }
4106 break;
4107 default:
4108 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4109 }
4110
4111 return IXGBE_SUCCESS;
4112 }
4113
4114 /**
4115 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4116 * the EEPROM
4117 * @hw: pointer to hardware structure
4118 * @wwnn_prefix: the alternative WWNN prefix
4119 * @wwpn_prefix: the alternative WWPN prefix
4120 *
4121 * This function will read the EEPROM from the alternative SAN MAC address
4122 * block to check the support for the alternative WWNN/WWPN prefix support.
4123 **/
ixgbe_get_wwn_prefix_generic(struct ixgbe_hw * hw,u16 * wwnn_prefix,u16 * wwpn_prefix)4124 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4125 u16 *wwpn_prefix)
4126 {
4127 u16 offset, caps;
4128 u16 alt_san_mac_blk_offset;
4129
4130 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4131
4132 /* clear output first */
4133 *wwnn_prefix = 0xFFFF;
4134 *wwpn_prefix = 0xFFFF;
4135
4136 /* check if alternative SAN MAC is supported */
4137 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4138 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4139 goto wwn_prefix_err;
4140
4141 if ((alt_san_mac_blk_offset == 0) ||
4142 (alt_san_mac_blk_offset == 0xFFFF))
4143 goto wwn_prefix_out;
4144
4145 /* check capability in alternative san mac address block */
4146 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4147 if (hw->eeprom.ops.read(hw, offset, &caps))
4148 goto wwn_prefix_err;
4149 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4150 goto wwn_prefix_out;
4151
4152 /* get the corresponding prefix for WWNN/WWPN */
4153 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4154 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4155 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4156 "eeprom read at offset %d failed", offset);
4157 }
4158
4159 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4160 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4161 goto wwn_prefix_err;
4162
4163 wwn_prefix_out:
4164 return IXGBE_SUCCESS;
4165
4166 wwn_prefix_err:
4167 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4168 "eeprom read at offset %d failed", offset);
4169 return IXGBE_SUCCESS;
4170 }
4171
4172 /**
4173 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4174 * @hw: pointer to hardware structure
4175 * @bs: the fcoe boot status
4176 *
4177 * This function will read the FCOE boot status from the iSCSI FCOE block
4178 **/
ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw * hw,u16 * bs)4179 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4180 {
4181 u16 offset, caps, flags;
4182 s32 status;
4183
4184 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4185
4186 /* clear output first */
4187 *bs = ixgbe_fcoe_bootstatus_unavailable;
4188
4189 /* check if FCOE IBA block is present */
4190 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4191 status = hw->eeprom.ops.read(hw, offset, &caps);
4192 if (status != IXGBE_SUCCESS)
4193 goto out;
4194
4195 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4196 goto out;
4197
4198 /* check if iSCSI FCOE block is populated */
4199 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4200 if (status != IXGBE_SUCCESS)
4201 goto out;
4202
4203 if ((offset == 0) || (offset == 0xFFFF))
4204 goto out;
4205
4206 /* read fcoe flags in iSCSI FCOE block */
4207 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4208 status = hw->eeprom.ops.read(hw, offset, &flags);
4209 if (status != IXGBE_SUCCESS)
4210 goto out;
4211
4212 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4213 *bs = ixgbe_fcoe_bootstatus_enabled;
4214 else
4215 *bs = ixgbe_fcoe_bootstatus_disabled;
4216
4217 out:
4218 return status;
4219 }
4220
4221 /**
4222 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4223 * @hw: pointer to hardware structure
4224 * @enable: enable or disable switch for anti-spoofing
4225 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
4226 *
4227 **/
ixgbe_set_mac_anti_spoofing(struct ixgbe_hw * hw,bool enable,int pf)4228 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
4229 {
4230 int j;
4231 int pf_target_reg = pf >> 3;
4232 int pf_target_shift = pf % 8;
4233 u32 pfvfspoof = 0;
4234
4235 if (hw->mac.type == ixgbe_mac_82598EB)
4236 return;
4237
4238 if (enable)
4239 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
4240
4241 /*
4242 * PFVFSPOOF register array is size 8 with 8 bits assigned to
4243 * MAC anti-spoof enables in each register array element.
4244 */
4245 for (j = 0; j < pf_target_reg; j++)
4246 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4247
4248 /*
4249 * The PF should be allowed to spoof so that it can support
4250 * emulation mode NICs. Do not set the bits assigned to the PF
4251 */
4252 pfvfspoof &= (1 << pf_target_shift) - 1;
4253 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4254
4255 /*
4256 * Remaining pools belong to the PF so they do not need to have
4257 * anti-spoofing enabled.
4258 */
4259 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
4260 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
4261 }
4262
4263 /**
4264 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4265 * @hw: pointer to hardware structure
4266 * @enable: enable or disable switch for VLAN anti-spoofing
4267 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4268 *
4269 **/
ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw * hw,bool enable,int vf)4270 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4271 {
4272 int vf_target_reg = vf >> 3;
4273 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4274 u32 pfvfspoof;
4275
4276 if (hw->mac.type == ixgbe_mac_82598EB)
4277 return;
4278
4279 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4280 if (enable)
4281 pfvfspoof |= (1 << vf_target_shift);
4282 else
4283 pfvfspoof &= ~(1 << vf_target_shift);
4284 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4285 }
4286
4287 /**
4288 * ixgbe_get_device_caps_generic - Get additional device capabilities
4289 * @hw: pointer to hardware structure
4290 * @device_caps: the EEPROM word with the extra device capabilities
4291 *
4292 * This function will read the EEPROM location for the device capabilities,
4293 * and return the word through device_caps.
4294 **/
ixgbe_get_device_caps_generic(struct ixgbe_hw * hw,u16 * device_caps)4295 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4296 {
4297 DEBUGFUNC("ixgbe_get_device_caps_generic");
4298
4299 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4300
4301 return IXGBE_SUCCESS;
4302 }
4303
4304 /**
4305 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4306 * @hw: pointer to hardware structure
4307 *
4308 **/
ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw * hw)4309 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4310 {
4311 u32 regval;
4312 u32 i;
4313
4314 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4315
4316 /* Enable relaxed ordering */
4317 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4318 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4319 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4320 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4321 }
4322
4323 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4324 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4325 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4326 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4327 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4328 }
4329
4330 }
4331
4332 /**
4333 * ixgbe_calculate_checksum - Calculate checksum for buffer
4334 * @buffer: pointer to EEPROM
4335 * @length: size of EEPROM to calculate a checksum for
4336 * Calculates the checksum for some buffer on a specified length. The
4337 * checksum calculated is returned.
4338 **/
ixgbe_calculate_checksum(u8 * buffer,u32 length)4339 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4340 {
4341 u32 i;
4342 u8 sum = 0;
4343
4344 DEBUGFUNC("ixgbe_calculate_checksum");
4345
4346 if (!buffer)
4347 return 0;
4348
4349 for (i = 0; i < length; i++)
4350 sum += buffer[i];
4351
4352 return (u8) (0 - sum);
4353 }
4354
4355 /**
4356 * ixgbe_host_interface_command - Issue command to manageability block
4357 * @hw: pointer to the HW structure
4358 * @buffer: contains the command to write and where the return status will
4359 * be placed
4360 * @length: length of buffer, must be multiple of 4 bytes
4361 * @timeout: time in ms to wait for command completion
4362 * @return_data: read and return data from the buffer (TRUE) or not (FALSE)
4363 * Needed because FW structures are big endian and decoding of
4364 * these fields can be 8 bit or 16 bit based on command. Decoding
4365 * is not easily understood without making a table of commands.
4366 * So we will leave this up to the caller to read back the data
4367 * in these cases.
4368 *
4369 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4370 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
4371 **/
ixgbe_host_interface_command(struct ixgbe_hw * hw,u32 * buffer,u32 length,u32 timeout,bool return_data)4372 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4373 u32 length, u32 timeout, bool return_data)
4374 {
4375 u32 hicr, i, bi, fwsts;
4376 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4377 u16 buf_len;
4378 u16 dword_len;
4379
4380 DEBUGFUNC("ixgbe_host_interface_command");
4381
4382 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4383 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4384 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4385 }
4386 /* Set bit 9 of FWSTS clearing FW reset indication */
4387 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4388 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4389
4390 /* Check that the host interface is enabled. */
4391 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4392 if ((hicr & IXGBE_HICR_EN) == 0) {
4393 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4394 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4395 }
4396
4397 /* Calculate length in DWORDs. We must be DWORD aligned */
4398 if ((length % (sizeof(u32))) != 0) {
4399 DEBUGOUT("Buffer length failure, not aligned to dword");
4400 return IXGBE_ERR_INVALID_ARGUMENT;
4401 }
4402
4403 dword_len = length >> 2;
4404
4405 /* The device driver writes the relevant command block
4406 * into the ram area.
4407 */
4408 for (i = 0; i < dword_len; i++)
4409 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4410 i, IXGBE_CPU_TO_LE32(buffer[i]));
4411
4412 /* Setting this bit tells the ARC that a new command is pending. */
4413 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4414
4415 for (i = 0; i < timeout; i++) {
4416 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4417 if (!(hicr & IXGBE_HICR_C))
4418 break;
4419 msec_delay(1);
4420 }
4421
4422 /* Check command completion */
4423 if ((timeout != 0 && i == timeout) ||
4424 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4425 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4426 "Command has failed with no status valid.\n");
4427 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4428 }
4429
4430 if (!return_data)
4431 return 0;
4432
4433 /* Calculate length in DWORDs */
4434 dword_len = hdr_size >> 2;
4435
4436 /* first pull in the header so we know the buffer length */
4437 for (bi = 0; bi < dword_len; bi++) {
4438 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4439 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4440 }
4441
4442 /* If there is any thing in data position pull it in */
4443 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
4444 if (buf_len == 0)
4445 return 0;
4446
4447 if (length < buf_len + hdr_size) {
4448 DEBUGOUT("Buffer not large enough for reply message.\n");
4449 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4450 }
4451
4452 /* Calculate length in DWORDs, add 3 for odd lengths */
4453 dword_len = (buf_len + 3) >> 2;
4454
4455 /* Pull in the rest of the buffer (bi is where we left off) */
4456 for (; bi <= dword_len; bi++) {
4457 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4458 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4459 }
4460
4461 return 0;
4462 }
4463
4464 /**
4465 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4466 * @hw: pointer to the HW structure
4467 * @maj: driver version major number
4468 * @min: driver version minor number
4469 * @build: driver version build number
4470 * @sub: driver version sub build number
4471 *
4472 * Sends driver version number to firmware through the manageability
4473 * block. On success return IXGBE_SUCCESS
4474 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4475 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4476 **/
ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw * hw,u8 maj,u8 min,u8 build,u8 sub)4477 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4478 u8 build, u8 sub)
4479 {
4480 struct ixgbe_hic_drv_info fw_cmd;
4481 int i;
4482 s32 ret_val = IXGBE_SUCCESS;
4483
4484 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4485
4486 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)
4487 != IXGBE_SUCCESS) {
4488 ret_val = IXGBE_ERR_SWFW_SYNC;
4489 goto out;
4490 }
4491
4492 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4493 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4494 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4495 fw_cmd.port_num = (u8)hw->bus.func;
4496 fw_cmd.ver_maj = maj;
4497 fw_cmd.ver_min = min;
4498 fw_cmd.ver_build = build;
4499 fw_cmd.ver_sub = sub;
4500 fw_cmd.hdr.checksum = 0;
4501 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4502 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4503 fw_cmd.pad = 0;
4504 fw_cmd.pad2 = 0;
4505
4506 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4507 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4508 sizeof(fw_cmd),
4509 IXGBE_HI_COMMAND_TIMEOUT,
4510 TRUE);
4511 if (ret_val != IXGBE_SUCCESS)
4512 continue;
4513
4514 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4515 FW_CEM_RESP_STATUS_SUCCESS)
4516 ret_val = IXGBE_SUCCESS;
4517 else
4518 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4519
4520 break;
4521 }
4522
4523 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4524 out:
4525 return ret_val;
4526 }
4527
4528 /**
4529 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4530 * @hw: pointer to hardware structure
4531 * @num_pb: number of packet buffers to allocate
4532 * @headroom: reserve n KB of headroom
4533 * @strategy: packet buffer allocation strategy
4534 **/
ixgbe_set_rxpba_generic(struct ixgbe_hw * hw,int num_pb,u32 headroom,int strategy)4535 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4536 int strategy)
4537 {
4538 u32 pbsize = hw->mac.rx_pb_size;
4539 int i = 0;
4540 u32 rxpktsize, txpktsize, txpbthresh;
4541
4542 /* Reserve headroom */
4543 pbsize -= headroom;
4544
4545 if (!num_pb)
4546 num_pb = 1;
4547
4548 /* Divide remaining packet buffer space amongst the number of packet
4549 * buffers requested using supplied strategy.
4550 */
4551 switch (strategy) {
4552 case PBA_STRATEGY_WEIGHTED:
4553 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4554 * buffer with 5/8 of the packet buffer space.
4555 */
4556 rxpktsize = (pbsize * 5) / (num_pb * 4);
4557 pbsize -= rxpktsize * (num_pb / 2);
4558 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4559 for (; i < (num_pb / 2); i++)
4560 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4561 /* Fall through to configure remaining packet buffers */
4562 case PBA_STRATEGY_EQUAL:
4563 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4564 for (; i < num_pb; i++)
4565 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4566 break;
4567 default:
4568 break;
4569 }
4570
4571 /* Only support an equally distributed Tx packet buffer strategy. */
4572 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4573 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4574 for (i = 0; i < num_pb; i++) {
4575 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4576 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4577 }
4578
4579 /* Clear unused TCs, if any, to zero buffer size*/
4580 for (; i < IXGBE_MAX_PB; i++) {
4581 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4582 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4583 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4584 }
4585 }
4586
4587 /**
4588 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4589 * @hw: pointer to the hardware structure
4590 *
4591 * The 82599 and x540 MACs can experience issues if TX work is still pending
4592 * when a reset occurs. This function prevents this by flushing the PCIe
4593 * buffers on the system.
4594 **/
ixgbe_clear_tx_pending(struct ixgbe_hw * hw)4595 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4596 {
4597 u32 gcr_ext, hlreg0, i, poll;
4598 u16 value;
4599
4600 /*
4601 * If double reset is not requested then all transactions should
4602 * already be clear and as such there is no work to do
4603 */
4604 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4605 return;
4606
4607 /*
4608 * Set loopback enable to prevent any transmits from being sent
4609 * should the link come up. This assumes that the RXCTRL.RXEN bit
4610 * has already been cleared.
4611 */
4612 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4613 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4614
4615 /* Wait for a last completion before clearing buffers */
4616 IXGBE_WRITE_FLUSH(hw);
4617 msec_delay(3);
4618
4619 /*
4620 * Before proceeding, make sure that the PCIe block does not have
4621 * transactions pending.
4622 */
4623 poll = ixgbe_pcie_timeout_poll(hw);
4624 for (i = 0; i < poll; i++) {
4625 usec_delay(100);
4626 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
4627 if (IXGBE_REMOVED(hw->hw_addr))
4628 goto out;
4629 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
4630 goto out;
4631 }
4632
4633 out:
4634 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4635 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4636 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4637 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4638
4639 /* Flush all writes and allow 20usec for all transactions to clear */
4640 IXGBE_WRITE_FLUSH(hw);
4641 usec_delay(20);
4642
4643 /* restore previous register values */
4644 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4645 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4646 }
4647
4648
4649 /**
4650 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
4651 * @hw: pointer to hardware structure
4652 * @map: pointer to u8 arr for returning map
4653 *
4654 * Read the rtrup2tc HW register and resolve its content into map
4655 **/
ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw * hw,u8 * map)4656 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
4657 {
4658 u32 reg, i;
4659
4660 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
4661 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
4662 map[i] = IXGBE_RTRUP2TC_UP_MASK &
4663 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
4664 return;
4665 }
4666
ixgbe_disable_rx_generic(struct ixgbe_hw * hw)4667 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
4668 {
4669 u32 pfdtxgswc;
4670 u32 rxctrl;
4671
4672 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4673 if (rxctrl & IXGBE_RXCTRL_RXEN) {
4674 if (hw->mac.type != ixgbe_mac_82598EB) {
4675 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4676 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
4677 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4678 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4679 hw->mac.set_lben = TRUE;
4680 } else {
4681 hw->mac.set_lben = FALSE;
4682 }
4683 }
4684 rxctrl &= ~IXGBE_RXCTRL_RXEN;
4685 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
4686 }
4687 }
4688
ixgbe_enable_rx_generic(struct ixgbe_hw * hw)4689 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
4690 {
4691 u32 pfdtxgswc;
4692 u32 rxctrl;
4693
4694 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4695 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
4696
4697 if (hw->mac.type != ixgbe_mac_82598EB) {
4698 if (hw->mac.set_lben) {
4699 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4700 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
4701 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4702 hw->mac.set_lben = FALSE;
4703 }
4704 }
4705 }
4706
4707 /**
4708 * ixgbe_mng_present - returns TRUE when management capability is present
4709 * @hw: pointer to hardware structure
4710 */
ixgbe_mng_present(struct ixgbe_hw * hw)4711 bool ixgbe_mng_present(struct ixgbe_hw *hw)
4712 {
4713 u32 fwsm;
4714
4715 if (hw->mac.type < ixgbe_mac_82599EB)
4716 return FALSE;
4717
4718 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
4719 fwsm &= IXGBE_FWSM_MODE_MASK;
4720 return fwsm == IXGBE_FWSM_FW_MODE_PT;
4721 }
4722
4723 /**
4724 * ixgbe_mng_enabled - Is the manageability engine enabled?
4725 * @hw: pointer to hardware structure
4726 *
4727 * Returns TRUE if the manageability engine is enabled.
4728 **/
ixgbe_mng_enabled(struct ixgbe_hw * hw)4729 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
4730 {
4731 u32 fwsm, manc, factps;
4732
4733 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
4734 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
4735 return FALSE;
4736
4737 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
4738 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
4739 return FALSE;
4740
4741 if (hw->mac.type <= ixgbe_mac_X540) {
4742 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
4743 if (factps & IXGBE_FACTPS_MNGCG)
4744 return FALSE;
4745 }
4746
4747 return TRUE;
4748 }
4749
4750 /**
4751 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
4752 * @hw: pointer to hardware structure
4753 * @speed: new link speed
4754 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
4755 *
4756 * Set the link speed in the MAC and/or PHY register and restarts link.
4757 **/
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait_to_complete)4758 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
4759 ixgbe_link_speed speed,
4760 bool autoneg_wait_to_complete)
4761 {
4762 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4763 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4764 s32 status = IXGBE_SUCCESS;
4765 u32 speedcnt = 0;
4766 u32 i = 0;
4767 bool autoneg, link_up = FALSE;
4768
4769 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
4770
4771 /* Mask off requested but non-supported speeds */
4772 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
4773 if (status != IXGBE_SUCCESS)
4774 return status;
4775
4776 speed &= link_speed;
4777
4778 /* Try each speed one by one, highest priority first. We do this in
4779 * software because 10Gb fiber doesn't support speed autonegotiation.
4780 */
4781 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
4782 speedcnt++;
4783 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
4784
4785 /* If we already have link at this speed, just jump out */
4786 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
4787 if (status != IXGBE_SUCCESS)
4788 return status;
4789
4790 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
4791 goto out;
4792
4793 /* Set the module link speed */
4794 switch (hw->phy.media_type) {
4795 case ixgbe_media_type_fiber_fixed:
4796 case ixgbe_media_type_fiber:
4797 ixgbe_set_rate_select_speed(hw,
4798 IXGBE_LINK_SPEED_10GB_FULL);
4799 break;
4800 case ixgbe_media_type_fiber_qsfp:
4801 /* QSFP module automatically detects MAC link speed */
4802 break;
4803 default:
4804 DEBUGOUT("Unexpected media type.\n");
4805 break;
4806 }
4807
4808 /* Allow module to change analog characteristics (1G->10G) */
4809 msec_delay(40);
4810
4811 status = ixgbe_setup_mac_link(hw,
4812 IXGBE_LINK_SPEED_10GB_FULL,
4813 autoneg_wait_to_complete);
4814 if (status != IXGBE_SUCCESS)
4815 return status;
4816
4817 /* Flap the Tx laser if it has not already been done */
4818 ixgbe_flap_tx_laser(hw);
4819
4820 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
4821 * Section 73.10.2, we may have to wait up to 500ms if KR is
4822 * attempted. 82599 uses the same timing for 10g SFI.
4823 */
4824 for (i = 0; i < 5; i++) {
4825 /* Wait for the link partner to also set speed */
4826 msec_delay(100);
4827
4828 /* If we have link, just jump out */
4829 status = ixgbe_check_link(hw, &link_speed,
4830 &link_up, FALSE);
4831 if (status != IXGBE_SUCCESS)
4832 return status;
4833
4834 if (link_up)
4835 goto out;
4836 }
4837 }
4838
4839 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
4840 speedcnt++;
4841 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
4842 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
4843
4844 /* If we already have link at this speed, just jump out */
4845 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
4846 if (status != IXGBE_SUCCESS)
4847 return status;
4848
4849 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
4850 goto out;
4851
4852 /* Set the module link speed */
4853 switch (hw->phy.media_type) {
4854 case ixgbe_media_type_fiber_fixed:
4855 case ixgbe_media_type_fiber:
4856 ixgbe_set_rate_select_speed(hw,
4857 IXGBE_LINK_SPEED_1GB_FULL);
4858 break;
4859 case ixgbe_media_type_fiber_qsfp:
4860 /* QSFP module automatically detects link speed */
4861 break;
4862 default:
4863 DEBUGOUT("Unexpected media type.\n");
4864 break;
4865 }
4866
4867 /* Allow module to change analog characteristics (10G->1G) */
4868 msec_delay(40);
4869
4870 status = ixgbe_setup_mac_link(hw,
4871 IXGBE_LINK_SPEED_1GB_FULL,
4872 autoneg_wait_to_complete);
4873 if (status != IXGBE_SUCCESS)
4874 return status;
4875
4876 /* Flap the Tx laser if it has not already been done */
4877 ixgbe_flap_tx_laser(hw);
4878
4879 /* Wait for the link partner to also set speed */
4880 msec_delay(100);
4881
4882 /* If we have link, just jump out */
4883 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
4884 if (status != IXGBE_SUCCESS)
4885 return status;
4886
4887 if (link_up)
4888 goto out;
4889 }
4890
4891 /* We didn't get link. Configure back to the highest speed we tried,
4892 * (if there was more than one). We call ourselves back with just the
4893 * single highest speed that the user requested.
4894 */
4895 if (speedcnt > 1)
4896 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
4897 highest_link_speed,
4898 autoneg_wait_to_complete);
4899
4900 out:
4901 /* Set autoneg_advertised value based on input link speed */
4902 hw->phy.autoneg_advertised = 0;
4903
4904 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4905 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
4906
4907 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
4908 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
4909
4910 return status;
4911 }
4912
4913 /**
4914 * ixgbe_set_soft_rate_select_speed - Set module link speed
4915 * @hw: pointer to hardware structure
4916 * @speed: link speed to set
4917 *
4918 * Set module link speed via the soft rate select.
4919 */
ixgbe_set_soft_rate_select_speed(struct ixgbe_hw * hw,ixgbe_link_speed speed)4920 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
4921 ixgbe_link_speed speed)
4922 {
4923 s32 status;
4924 u8 rs, eeprom_data;
4925
4926 switch (speed) {
4927 case IXGBE_LINK_SPEED_10GB_FULL:
4928 /* one bit mask same as setting on */
4929 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
4930 break;
4931 case IXGBE_LINK_SPEED_1GB_FULL:
4932 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
4933 break;
4934 default:
4935 DEBUGOUT("Invalid fixed module speed\n");
4936 return;
4937 }
4938
4939 /* Set RS0 */
4940 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
4941 IXGBE_I2C_EEPROM_DEV_ADDR2,
4942 &eeprom_data);
4943 if (status) {
4944 DEBUGOUT("Failed to read Rx Rate Select RS0\n");
4945 goto out;
4946 }
4947
4948 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
4949
4950 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
4951 IXGBE_I2C_EEPROM_DEV_ADDR2,
4952 eeprom_data);
4953 if (status) {
4954 DEBUGOUT("Failed to write Rx Rate Select RS0\n");
4955 goto out;
4956 }
4957
4958 /* Set RS1 */
4959 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
4960 IXGBE_I2C_EEPROM_DEV_ADDR2,
4961 &eeprom_data);
4962 if (status) {
4963 DEBUGOUT("Failed to read Rx Rate Select RS1\n");
4964 goto out;
4965 }
4966
4967 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
4968
4969 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
4970 IXGBE_I2C_EEPROM_DEV_ADDR2,
4971 eeprom_data);
4972 if (status) {
4973 DEBUGOUT("Failed to write Rx Rate Select RS1\n");
4974 goto out;
4975 }
4976 out:
4977 return;
4978 }
4979