1 /******************************************************************************
2
3 Copyright (c) 2001-2017, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD$*/
34
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
37 #include "ixgbe_dcb.h"
38 #include "ixgbe_dcb_82599.h"
39 #include "ixgbe_api.h"
40
41 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
42 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
43 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
44 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
45 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
46 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
47 u16 count);
48 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
49 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
51 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
52
53 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
54 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
55 u16 *san_mac_offset);
56 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
57 u16 words, u16 *data);
58 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
59 u16 words, u16 *data);
60 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
61 u16 offset);
62
63 /**
64 * ixgbe_init_ops_generic - Inits function ptrs
65 * @hw: pointer to the hardware structure
66 *
67 * Initialize the function pointers.
68 **/
ixgbe_init_ops_generic(struct ixgbe_hw * hw)69 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
70 {
71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
72 struct ixgbe_mac_info *mac = &hw->mac;
73 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
74
75 DEBUGFUNC("ixgbe_init_ops_generic");
76
77 /* EEPROM */
78 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
79 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
80 if (eec & IXGBE_EEC_PRES) {
81 eeprom->ops.read = ixgbe_read_eerd_generic;
82 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
83 } else {
84 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
85 eeprom->ops.read_buffer =
86 ixgbe_read_eeprom_buffer_bit_bang_generic;
87 }
88 eeprom->ops.write = ixgbe_write_eeprom_generic;
89 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
90 eeprom->ops.validate_checksum =
91 ixgbe_validate_eeprom_checksum_generic;
92 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
93 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
94
95 /* MAC */
96 mac->ops.init_hw = ixgbe_init_hw_generic;
97 mac->ops.reset_hw = NULL;
98 mac->ops.start_hw = ixgbe_start_hw_generic;
99 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
100 mac->ops.get_media_type = NULL;
101 mac->ops.get_supported_physical_layer = NULL;
102 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
103 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
104 mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
105 mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
106 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
107 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
108 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
109 mac->ops.prot_autoc_read = prot_autoc_read_generic;
110 mac->ops.prot_autoc_write = prot_autoc_write_generic;
111
112 /* LEDs */
113 mac->ops.led_on = ixgbe_led_on_generic;
114 mac->ops.led_off = ixgbe_led_off_generic;
115 mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
116 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
117 mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic;
118
119 /* RAR, Multicast, VLAN */
120 mac->ops.set_rar = ixgbe_set_rar_generic;
121 mac->ops.clear_rar = ixgbe_clear_rar_generic;
122 mac->ops.insert_mac_addr = NULL;
123 mac->ops.set_vmdq = NULL;
124 mac->ops.clear_vmdq = NULL;
125 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
126 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
127 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
128 mac->ops.enable_mc = ixgbe_enable_mc_generic;
129 mac->ops.disable_mc = ixgbe_disable_mc_generic;
130 mac->ops.clear_vfta = NULL;
131 mac->ops.set_vfta = NULL;
132 mac->ops.set_vlvf = NULL;
133 mac->ops.init_uta_tables = NULL;
134 mac->ops.enable_rx = ixgbe_enable_rx_generic;
135 mac->ops.disable_rx = ixgbe_disable_rx_generic;
136
137 /* Flow Control */
138 mac->ops.fc_enable = ixgbe_fc_enable_generic;
139 mac->ops.setup_fc = ixgbe_setup_fc_generic;
140 mac->ops.fc_autoneg = ixgbe_fc_autoneg;
141
142 /* Link */
143 mac->ops.get_link_capabilities = NULL;
144 mac->ops.setup_link = NULL;
145 mac->ops.check_link = NULL;
146 mac->ops.dmac_config = NULL;
147 mac->ops.dmac_update_tcs = NULL;
148 mac->ops.dmac_config_tcs = NULL;
149
150 return IXGBE_SUCCESS;
151 }
152
153 /**
154 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
155 * of flow control
156 * @hw: pointer to hardware structure
157 *
158 * This function returns TRUE if the device supports flow control
159 * autonegotiation, and FALSE if it does not.
160 *
161 **/
ixgbe_device_supports_autoneg_fc(struct ixgbe_hw * hw)162 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
163 {
164 bool supported = FALSE;
165 ixgbe_link_speed speed;
166 bool link_up;
167
168 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
169
170 switch (hw->phy.media_type) {
171 case ixgbe_media_type_fiber_fixed:
172 case ixgbe_media_type_fiber_qsfp:
173 case ixgbe_media_type_fiber:
174 /* flow control autoneg black list */
175 switch (hw->device_id) {
176 case IXGBE_DEV_ID_X550EM_A_SFP:
177 case IXGBE_DEV_ID_X550EM_A_SFP_N:
178 case IXGBE_DEV_ID_X550EM_A_QSFP:
179 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
180 supported = FALSE;
181 break;
182 default:
183 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
184 /* if link is down, assume supported */
185 if (link_up)
186 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
187 TRUE : FALSE;
188 else
189 supported = TRUE;
190 }
191
192 break;
193 case ixgbe_media_type_backplane:
194 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI)
195 supported = FALSE;
196 else
197 supported = TRUE;
198 break;
199 case ixgbe_media_type_copper:
200 /* only some copper devices support flow control autoneg */
201 switch (hw->device_id) {
202 case IXGBE_DEV_ID_82599_T3_LOM:
203 case IXGBE_DEV_ID_X540T:
204 case IXGBE_DEV_ID_X540T1:
205 case IXGBE_DEV_ID_X540_BYPASS:
206 case IXGBE_DEV_ID_X550T:
207 case IXGBE_DEV_ID_X550T1:
208 case IXGBE_DEV_ID_X550EM_X_10G_T:
209 case IXGBE_DEV_ID_X550EM_A_10G_T:
210 case IXGBE_DEV_ID_X550EM_A_1G_T:
211 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
212 supported = TRUE;
213 break;
214 default:
215 supported = FALSE;
216 }
217 default:
218 break;
219 }
220
221 if (!supported)
222 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
223 "Device %x does not support flow control autoneg",
224 hw->device_id);
225 return supported;
226 }
227
228 /**
229 * ixgbe_setup_fc_generic - Set up flow control
230 * @hw: pointer to hardware structure
231 *
232 * Called at init time to set up flow control.
233 **/
ixgbe_setup_fc_generic(struct ixgbe_hw * hw)234 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
235 {
236 s32 ret_val = IXGBE_SUCCESS;
237 u32 reg = 0, reg_bp = 0;
238 u16 reg_cu = 0;
239 bool locked = FALSE;
240
241 DEBUGFUNC("ixgbe_setup_fc_generic");
242
243 /* Validate the requested mode */
244 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
245 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
246 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
247 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
248 goto out;
249 }
250
251 /*
252 * 10gig parts do not have a word in the EEPROM to determine the
253 * default flow control setting, so we explicitly set it to full.
254 */
255 if (hw->fc.requested_mode == ixgbe_fc_default)
256 hw->fc.requested_mode = ixgbe_fc_full;
257
258 /*
259 * Set up the 1G and 10G flow control advertisement registers so the
260 * HW will be able to do fc autoneg once the cable is plugged in. If
261 * we link at 10G, the 1G advertisement is harmless and vice versa.
262 */
263 switch (hw->phy.media_type) {
264 case ixgbe_media_type_backplane:
265 /* some MAC's need RMW protection on AUTOC */
266 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
267 if (ret_val != IXGBE_SUCCESS)
268 goto out;
269
270 /* only backplane uses autoc */
271 /* FALLTHROUGH */
272 case ixgbe_media_type_fiber_fixed:
273 case ixgbe_media_type_fiber_qsfp:
274 case ixgbe_media_type_fiber:
275 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
276
277 break;
278 case ixgbe_media_type_copper:
279 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
280 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
281 break;
282 default:
283 break;
284 }
285
286 /*
287 * The possible values of fc.requested_mode are:
288 * 0: Flow control is completely disabled
289 * 1: Rx flow control is enabled (we can receive pause frames,
290 * but not send pause frames).
291 * 2: Tx flow control is enabled (we can send pause frames but
292 * we do not support receiving pause frames).
293 * 3: Both Rx and Tx flow control (symmetric) are enabled.
294 * other: Invalid.
295 */
296 switch (hw->fc.requested_mode) {
297 case ixgbe_fc_none:
298 /* Flow control completely disabled by software override. */
299 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
300 if (hw->phy.media_type == ixgbe_media_type_backplane)
301 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
302 IXGBE_AUTOC_ASM_PAUSE);
303 else if (hw->phy.media_type == ixgbe_media_type_copper)
304 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
305 break;
306 case ixgbe_fc_tx_pause:
307 /*
308 * Tx Flow control is enabled, and Rx Flow control is
309 * disabled by software override.
310 */
311 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
312 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
313 if (hw->phy.media_type == ixgbe_media_type_backplane) {
314 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
315 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
316 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
317 reg_cu |= IXGBE_TAF_ASM_PAUSE;
318 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
319 }
320 break;
321 case ixgbe_fc_rx_pause:
322 /*
323 * Rx Flow control is enabled and Tx Flow control is
324 * disabled by software override. Since there really
325 * isn't a way to advertise that we are capable of RX
326 * Pause ONLY, we will advertise that we support both
327 * symmetric and asymmetric Rx PAUSE, as such we fall
328 * through to the fc_full statement. Later, we will
329 * disable the adapter's ability to send PAUSE frames.
330 */
331 case ixgbe_fc_full:
332 /* Flow control (both Rx and Tx) is enabled by SW override. */
333 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
334 if (hw->phy.media_type == ixgbe_media_type_backplane)
335 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
336 IXGBE_AUTOC_ASM_PAUSE;
337 else if (hw->phy.media_type == ixgbe_media_type_copper)
338 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
339 break;
340 default:
341 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
342 "Flow control param set incorrectly\n");
343 ret_val = IXGBE_ERR_CONFIG;
344 goto out;
345 break;
346 }
347
348 if (hw->mac.type < ixgbe_mac_X540) {
349 /*
350 * Enable auto-negotiation between the MAC & PHY;
351 * the MAC will advertise clause 37 flow control.
352 */
353 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
354 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
355
356 /* Disable AN timeout */
357 if (hw->fc.strict_ieee)
358 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
359
360 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
361 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
362 }
363
364 /*
365 * AUTOC restart handles negotiation of 1G and 10G on backplane
366 * and copper. There is no need to set the PCS1GCTL register.
367 *
368 */
369 if (hw->phy.media_type == ixgbe_media_type_backplane) {
370 reg_bp |= IXGBE_AUTOC_AN_RESTART;
371 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
372 if (ret_val)
373 goto out;
374 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
375 (ixgbe_device_supports_autoneg_fc(hw))) {
376 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
377 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
378 }
379
380 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
381 out:
382 return ret_val;
383 }
384
385 /**
386 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
387 * @hw: pointer to hardware structure
388 *
389 * Starts the hardware by filling the bus info structure and media type, clears
390 * all on chip counters, initializes receive address registers, multicast
391 * table, VLAN filter table, calls routine to set up link and flow control
392 * settings, and leaves transmit and receive units disabled and uninitialized
393 **/
ixgbe_start_hw_generic(struct ixgbe_hw * hw)394 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
395 {
396 s32 ret_val;
397 u32 ctrl_ext;
398 u16 device_caps;
399
400 DEBUGFUNC("ixgbe_start_hw_generic");
401
402 /* Set the media type */
403 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
404
405 /* PHY ops initialization must be done in reset_hw() */
406
407 /* Clear the VLAN filter table */
408 hw->mac.ops.clear_vfta(hw);
409
410 /* Clear statistics registers */
411 hw->mac.ops.clear_hw_cntrs(hw);
412
413 /* Set No Snoop Disable */
414 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
415 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
416 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
417 IXGBE_WRITE_FLUSH(hw);
418
419 /* Setup flow control */
420 ret_val = ixgbe_setup_fc(hw);
421 if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED) {
422 DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val);
423 return ret_val;
424 }
425
426 /* Cache bit indicating need for crosstalk fix */
427 switch (hw->mac.type) {
428 case ixgbe_mac_82599EB:
429 case ixgbe_mac_X550EM_x:
430 case ixgbe_mac_X550EM_a:
431 hw->mac.ops.get_device_caps(hw, &device_caps);
432 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
433 hw->need_crosstalk_fix = FALSE;
434 else
435 hw->need_crosstalk_fix = TRUE;
436 break;
437 default:
438 hw->need_crosstalk_fix = FALSE;
439 break;
440 }
441
442 /* Clear adapter stopped flag */
443 hw->adapter_stopped = FALSE;
444
445 return IXGBE_SUCCESS;
446 }
447
448 /**
449 * ixgbe_start_hw_gen2 - Init sequence for common device family
450 * @hw: pointer to hw structure
451 *
452 * Performs the init sequence common to the second generation
453 * of 10 GbE devices.
454 * Devices in the second generation:
455 * 82599
456 * X540
457 **/
ixgbe_start_hw_gen2(struct ixgbe_hw * hw)458 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
459 {
460 u32 i;
461 u32 regval;
462
463 /* Clear the rate limiters */
464 for (i = 0; i < hw->mac.max_tx_queues; i++) {
465 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
466 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
467 }
468 IXGBE_WRITE_FLUSH(hw);
469
470 /* Disable relaxed ordering */
471 for (i = 0; i < hw->mac.max_tx_queues; i++) {
472 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
473 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
474 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
475 }
476
477 for (i = 0; i < hw->mac.max_rx_queues; i++) {
478 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
479 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
480 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
481 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
482 }
483
484 return IXGBE_SUCCESS;
485 }
486
487 /**
488 * ixgbe_init_hw_generic - Generic hardware initialization
489 * @hw: pointer to hardware structure
490 *
491 * Initialize the hardware by resetting the hardware, filling the bus info
492 * structure and media type, clears all on chip counters, initializes receive
493 * address registers, multicast table, VLAN filter table, calls routine to set
494 * up link and flow control settings, and leaves transmit and receive units
495 * disabled and uninitialized
496 **/
ixgbe_init_hw_generic(struct ixgbe_hw * hw)497 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
498 {
499 s32 status;
500
501 DEBUGFUNC("ixgbe_init_hw_generic");
502
503 /* Reset the hardware */
504 status = hw->mac.ops.reset_hw(hw);
505
506 if (status == IXGBE_SUCCESS || status == IXGBE_ERR_SFP_NOT_PRESENT) {
507 /* Start the HW */
508 status = hw->mac.ops.start_hw(hw);
509 }
510
511 /* Initialize the LED link active for LED blink support */
512 if (hw->mac.ops.init_led_link_act)
513 hw->mac.ops.init_led_link_act(hw);
514
515 if (status != IXGBE_SUCCESS)
516 DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status);
517
518 return status;
519 }
520
521 /**
522 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
523 * @hw: pointer to hardware structure
524 *
525 * Clears all hardware statistics counters by reading them from the hardware
526 * Statistics counters are clear on read.
527 **/
ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw * hw)528 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
529 {
530 u16 i = 0;
531
532 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
533
534 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
535 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
536 IXGBE_READ_REG(hw, IXGBE_ERRBC);
537 IXGBE_READ_REG(hw, IXGBE_MSPDC);
538 for (i = 0; i < 8; i++)
539 IXGBE_READ_REG(hw, IXGBE_MPC(i));
540
541 IXGBE_READ_REG(hw, IXGBE_MLFC);
542 IXGBE_READ_REG(hw, IXGBE_MRFC);
543 IXGBE_READ_REG(hw, IXGBE_RLEC);
544 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
545 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
546 if (hw->mac.type >= ixgbe_mac_82599EB) {
547 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
548 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
549 } else {
550 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
551 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
552 }
553
554 for (i = 0; i < 8; i++) {
555 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
556 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
557 if (hw->mac.type >= ixgbe_mac_82599EB) {
558 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
559 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
560 } else {
561 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
562 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
563 }
564 }
565 if (hw->mac.type >= ixgbe_mac_82599EB)
566 for (i = 0; i < 8; i++)
567 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
568 IXGBE_READ_REG(hw, IXGBE_PRC64);
569 IXGBE_READ_REG(hw, IXGBE_PRC127);
570 IXGBE_READ_REG(hw, IXGBE_PRC255);
571 IXGBE_READ_REG(hw, IXGBE_PRC511);
572 IXGBE_READ_REG(hw, IXGBE_PRC1023);
573 IXGBE_READ_REG(hw, IXGBE_PRC1522);
574 IXGBE_READ_REG(hw, IXGBE_GPRC);
575 IXGBE_READ_REG(hw, IXGBE_BPRC);
576 IXGBE_READ_REG(hw, IXGBE_MPRC);
577 IXGBE_READ_REG(hw, IXGBE_GPTC);
578 IXGBE_READ_REG(hw, IXGBE_GORCL);
579 IXGBE_READ_REG(hw, IXGBE_GORCH);
580 IXGBE_READ_REG(hw, IXGBE_GOTCL);
581 IXGBE_READ_REG(hw, IXGBE_GOTCH);
582 if (hw->mac.type == ixgbe_mac_82598EB)
583 for (i = 0; i < 8; i++)
584 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
585 IXGBE_READ_REG(hw, IXGBE_RUC);
586 IXGBE_READ_REG(hw, IXGBE_RFC);
587 IXGBE_READ_REG(hw, IXGBE_ROC);
588 IXGBE_READ_REG(hw, IXGBE_RJC);
589 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
590 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
591 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
592 IXGBE_READ_REG(hw, IXGBE_TORL);
593 IXGBE_READ_REG(hw, IXGBE_TORH);
594 IXGBE_READ_REG(hw, IXGBE_TPR);
595 IXGBE_READ_REG(hw, IXGBE_TPT);
596 IXGBE_READ_REG(hw, IXGBE_PTC64);
597 IXGBE_READ_REG(hw, IXGBE_PTC127);
598 IXGBE_READ_REG(hw, IXGBE_PTC255);
599 IXGBE_READ_REG(hw, IXGBE_PTC511);
600 IXGBE_READ_REG(hw, IXGBE_PTC1023);
601 IXGBE_READ_REG(hw, IXGBE_PTC1522);
602 IXGBE_READ_REG(hw, IXGBE_MPTC);
603 IXGBE_READ_REG(hw, IXGBE_BPTC);
604 for (i = 0; i < 16; i++) {
605 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
606 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
607 if (hw->mac.type >= ixgbe_mac_82599EB) {
608 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
609 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
610 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
611 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
612 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
613 } else {
614 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
615 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
616 }
617 }
618
619 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
620 if (hw->phy.id == 0)
621 ixgbe_identify_phy(hw);
622 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
623 IXGBE_MDIO_PCS_DEV_TYPE, &i);
624 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
625 IXGBE_MDIO_PCS_DEV_TYPE, &i);
626 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
627 IXGBE_MDIO_PCS_DEV_TYPE, &i);
628 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
629 IXGBE_MDIO_PCS_DEV_TYPE, &i);
630 }
631
632 return IXGBE_SUCCESS;
633 }
634
635 /**
636 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
637 * @hw: pointer to hardware structure
638 * @pba_num: stores the part number string from the EEPROM
639 * @pba_num_size: part number string buffer length
640 *
641 * Reads the part number string from the EEPROM.
642 **/
ixgbe_read_pba_string_generic(struct ixgbe_hw * hw,u8 * pba_num,u32 pba_num_size)643 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
644 u32 pba_num_size)
645 {
646 s32 ret_val;
647 u16 data;
648 u16 pba_ptr;
649 u16 offset;
650 u16 length;
651
652 DEBUGFUNC("ixgbe_read_pba_string_generic");
653
654 if (pba_num == NULL) {
655 DEBUGOUT("PBA string buffer was null\n");
656 return IXGBE_ERR_INVALID_ARGUMENT;
657 }
658
659 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
660 if (ret_val) {
661 DEBUGOUT("NVM Read Error\n");
662 return ret_val;
663 }
664
665 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
666 if (ret_val) {
667 DEBUGOUT("NVM Read Error\n");
668 return ret_val;
669 }
670
671 /*
672 * if data is not ptr guard the PBA must be in legacy format which
673 * means pba_ptr is actually our second data word for the PBA number
674 * and we can decode it into an ascii string
675 */
676 if (data != IXGBE_PBANUM_PTR_GUARD) {
677 DEBUGOUT("NVM PBA number is not stored as string\n");
678
679 /* we will need 11 characters to store the PBA */
680 if (pba_num_size < 11) {
681 DEBUGOUT("PBA string buffer too small\n");
682 return IXGBE_ERR_NO_SPACE;
683 }
684
685 /* extract hex string from data and pba_ptr */
686 pba_num[0] = (data >> 12) & 0xF;
687 pba_num[1] = (data >> 8) & 0xF;
688 pba_num[2] = (data >> 4) & 0xF;
689 pba_num[3] = data & 0xF;
690 pba_num[4] = (pba_ptr >> 12) & 0xF;
691 pba_num[5] = (pba_ptr >> 8) & 0xF;
692 pba_num[6] = '-';
693 pba_num[7] = 0;
694 pba_num[8] = (pba_ptr >> 4) & 0xF;
695 pba_num[9] = pba_ptr & 0xF;
696
697 /* put a null character on the end of our string */
698 pba_num[10] = '\0';
699
700 /* switch all the data but the '-' to hex char */
701 for (offset = 0; offset < 10; offset++) {
702 if (pba_num[offset] < 0xA)
703 pba_num[offset] += '0';
704 else if (pba_num[offset] < 0x10)
705 pba_num[offset] += 'A' - 0xA;
706 }
707
708 return IXGBE_SUCCESS;
709 }
710
711 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
712 if (ret_val) {
713 DEBUGOUT("NVM Read Error\n");
714 return ret_val;
715 }
716
717 if (length == 0xFFFF || length == 0) {
718 DEBUGOUT("NVM PBA number section invalid length\n");
719 return IXGBE_ERR_PBA_SECTION;
720 }
721
722 /* check if pba_num buffer is big enough */
723 if (pba_num_size < (((u32)length * 2) - 1)) {
724 DEBUGOUT("PBA string buffer too small\n");
725 return IXGBE_ERR_NO_SPACE;
726 }
727
728 /* trim pba length from start of string */
729 pba_ptr++;
730 length--;
731
732 for (offset = 0; offset < length; offset++) {
733 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
734 if (ret_val) {
735 DEBUGOUT("NVM Read Error\n");
736 return ret_val;
737 }
738 pba_num[offset * 2] = (u8)(data >> 8);
739 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
740 }
741 pba_num[offset * 2] = '\0';
742
743 return IXGBE_SUCCESS;
744 }
745
746 /**
747 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
748 * @hw: pointer to hardware structure
749 * @pba_num: stores the part number from the EEPROM
750 *
751 * Reads the part number from the EEPROM.
752 **/
ixgbe_read_pba_num_generic(struct ixgbe_hw * hw,u32 * pba_num)753 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
754 {
755 s32 ret_val;
756 u16 data;
757
758 DEBUGFUNC("ixgbe_read_pba_num_generic");
759
760 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
761 if (ret_val) {
762 DEBUGOUT("NVM Read Error\n");
763 return ret_val;
764 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
765 DEBUGOUT("NVM Not supported\n");
766 return IXGBE_NOT_IMPLEMENTED;
767 }
768 *pba_num = (u32)(data << 16);
769
770 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
771 if (ret_val) {
772 DEBUGOUT("NVM Read Error\n");
773 return ret_val;
774 }
775 *pba_num |= data;
776
777 return IXGBE_SUCCESS;
778 }
779
780 /**
781 * ixgbe_read_pba_raw
782 * @hw: pointer to the HW structure
783 * @eeprom_buf: optional pointer to EEPROM image
784 * @eeprom_buf_size: size of EEPROM image in words
785 * @max_pba_block_size: PBA block size limit
786 * @pba: pointer to output PBA structure
787 *
788 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
789 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
790 *
791 **/
ixgbe_read_pba_raw(struct ixgbe_hw * hw,u16 * eeprom_buf,u32 eeprom_buf_size,u16 max_pba_block_size,struct ixgbe_pba * pba)792 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
793 u32 eeprom_buf_size, u16 max_pba_block_size,
794 struct ixgbe_pba *pba)
795 {
796 s32 ret_val;
797 u16 pba_block_size;
798
799 if (pba == NULL)
800 return IXGBE_ERR_PARAM;
801
802 if (eeprom_buf == NULL) {
803 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
804 &pba->word[0]);
805 if (ret_val)
806 return ret_val;
807 } else {
808 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
809 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
810 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
811 } else {
812 return IXGBE_ERR_PARAM;
813 }
814 }
815
816 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
817 if (pba->pba_block == NULL)
818 return IXGBE_ERR_PARAM;
819
820 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
821 eeprom_buf_size,
822 &pba_block_size);
823 if (ret_val)
824 return ret_val;
825
826 if (pba_block_size > max_pba_block_size)
827 return IXGBE_ERR_PARAM;
828
829 if (eeprom_buf == NULL) {
830 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
831 pba_block_size,
832 pba->pba_block);
833 if (ret_val)
834 return ret_val;
835 } else {
836 if (eeprom_buf_size > (u32)(pba->word[1] +
837 pba_block_size)) {
838 memcpy(pba->pba_block,
839 &eeprom_buf[pba->word[1]],
840 pba_block_size * sizeof(u16));
841 } else {
842 return IXGBE_ERR_PARAM;
843 }
844 }
845 }
846
847 return IXGBE_SUCCESS;
848 }
849
850 /**
851 * ixgbe_write_pba_raw
852 * @hw: pointer to the HW structure
853 * @eeprom_buf: optional pointer to EEPROM image
854 * @eeprom_buf_size: size of EEPROM image in words
855 * @pba: pointer to PBA structure
856 *
857 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
858 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
859 *
860 **/
ixgbe_write_pba_raw(struct ixgbe_hw * hw,u16 * eeprom_buf,u32 eeprom_buf_size,struct ixgbe_pba * pba)861 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
862 u32 eeprom_buf_size, struct ixgbe_pba *pba)
863 {
864 s32 ret_val;
865
866 if (pba == NULL)
867 return IXGBE_ERR_PARAM;
868
869 if (eeprom_buf == NULL) {
870 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
871 &pba->word[0]);
872 if (ret_val)
873 return ret_val;
874 } else {
875 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
876 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
877 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
878 } else {
879 return IXGBE_ERR_PARAM;
880 }
881 }
882
883 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
884 if (pba->pba_block == NULL)
885 return IXGBE_ERR_PARAM;
886
887 if (eeprom_buf == NULL) {
888 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
889 pba->pba_block[0],
890 pba->pba_block);
891 if (ret_val)
892 return ret_val;
893 } else {
894 if (eeprom_buf_size > (u32)(pba->word[1] +
895 pba->pba_block[0])) {
896 memcpy(&eeprom_buf[pba->word[1]],
897 pba->pba_block,
898 pba->pba_block[0] * sizeof(u16));
899 } else {
900 return IXGBE_ERR_PARAM;
901 }
902 }
903 }
904
905 return IXGBE_SUCCESS;
906 }
907
908 /**
909 * ixgbe_get_pba_block_size
910 * @hw: pointer to the HW structure
911 * @eeprom_buf: optional pointer to EEPROM image
912 * @eeprom_buf_size: size of EEPROM image in words
913 * @pba_data_size: pointer to output variable
914 *
915 * Returns the size of the PBA block in words. Function operates on EEPROM
916 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
917 * EEPROM device.
918 *
919 **/
ixgbe_get_pba_block_size(struct ixgbe_hw * hw,u16 * eeprom_buf,u32 eeprom_buf_size,u16 * pba_block_size)920 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
921 u32 eeprom_buf_size, u16 *pba_block_size)
922 {
923 s32 ret_val;
924 u16 pba_word[2];
925 u16 length;
926
927 DEBUGFUNC("ixgbe_get_pba_block_size");
928
929 if (eeprom_buf == NULL) {
930 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
931 &pba_word[0]);
932 if (ret_val)
933 return ret_val;
934 } else {
935 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
936 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
937 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
938 } else {
939 return IXGBE_ERR_PARAM;
940 }
941 }
942
943 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
944 if (eeprom_buf == NULL) {
945 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
946 &length);
947 if (ret_val)
948 return ret_val;
949 } else {
950 if (eeprom_buf_size > pba_word[1])
951 length = eeprom_buf[pba_word[1] + 0];
952 else
953 return IXGBE_ERR_PARAM;
954 }
955
956 if (length == 0xFFFF || length == 0)
957 return IXGBE_ERR_PBA_SECTION;
958 } else {
959 /* PBA number in legacy format, there is no PBA Block. */
960 length = 0;
961 }
962
963 if (pba_block_size != NULL)
964 *pba_block_size = length;
965
966 return IXGBE_SUCCESS;
967 }
968
969 /**
970 * ixgbe_get_mac_addr_generic - Generic get MAC address
971 * @hw: pointer to hardware structure
972 * @mac_addr: Adapter MAC address
973 *
974 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
975 * A reset of the adapter must be performed prior to calling this function
976 * in order for the MAC address to have been loaded from the EEPROM into RAR0
977 **/
ixgbe_get_mac_addr_generic(struct ixgbe_hw * hw,u8 * mac_addr)978 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
979 {
980 u32 rar_high;
981 u32 rar_low;
982 u16 i;
983
984 DEBUGFUNC("ixgbe_get_mac_addr_generic");
985
986 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
987 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
988
989 for (i = 0; i < 4; i++)
990 mac_addr[i] = (u8)(rar_low >> (i*8));
991
992 for (i = 0; i < 2; i++)
993 mac_addr[i+4] = (u8)(rar_high >> (i*8));
994
995 return IXGBE_SUCCESS;
996 }
997
998 /**
999 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
1000 * @hw: pointer to hardware structure
1001 * @link_status: the link status returned by the PCI config space
1002 *
1003 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
1004 **/
ixgbe_set_pci_config_data_generic(struct ixgbe_hw * hw,u16 link_status)1005 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
1006 {
1007 struct ixgbe_mac_info *mac = &hw->mac;
1008
1009 if (hw->bus.type == ixgbe_bus_type_unknown)
1010 hw->bus.type = ixgbe_bus_type_pci_express;
1011
1012 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
1013 case IXGBE_PCI_LINK_WIDTH_1:
1014 hw->bus.width = ixgbe_bus_width_pcie_x1;
1015 break;
1016 case IXGBE_PCI_LINK_WIDTH_2:
1017 hw->bus.width = ixgbe_bus_width_pcie_x2;
1018 break;
1019 case IXGBE_PCI_LINK_WIDTH_4:
1020 hw->bus.width = ixgbe_bus_width_pcie_x4;
1021 break;
1022 case IXGBE_PCI_LINK_WIDTH_8:
1023 hw->bus.width = ixgbe_bus_width_pcie_x8;
1024 break;
1025 default:
1026 hw->bus.width = ixgbe_bus_width_unknown;
1027 break;
1028 }
1029
1030 switch (link_status & IXGBE_PCI_LINK_SPEED) {
1031 case IXGBE_PCI_LINK_SPEED_2500:
1032 hw->bus.speed = ixgbe_bus_speed_2500;
1033 break;
1034 case IXGBE_PCI_LINK_SPEED_5000:
1035 hw->bus.speed = ixgbe_bus_speed_5000;
1036 break;
1037 case IXGBE_PCI_LINK_SPEED_8000:
1038 hw->bus.speed = ixgbe_bus_speed_8000;
1039 break;
1040 default:
1041 hw->bus.speed = ixgbe_bus_speed_unknown;
1042 break;
1043 }
1044
1045 mac->ops.set_lan_id(hw);
1046 }
1047
1048 /**
1049 * ixgbe_get_bus_info_generic - Generic set PCI bus info
1050 * @hw: pointer to hardware structure
1051 *
1052 * Gets the PCI bus info (speed, width, type) then calls helper function to
1053 * store this data within the ixgbe_hw structure.
1054 **/
ixgbe_get_bus_info_generic(struct ixgbe_hw * hw)1055 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1056 {
1057 u16 link_status;
1058
1059 DEBUGFUNC("ixgbe_get_bus_info_generic");
1060
1061 /* Get the negotiated link width and speed from PCI config space */
1062 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1063
1064 ixgbe_set_pci_config_data_generic(hw, link_status);
1065
1066 return IXGBE_SUCCESS;
1067 }
1068
1069 /**
1070 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1071 * @hw: pointer to the HW structure
1072 *
1073 * Determines the LAN function id by reading memory-mapped registers and swaps
1074 * the port value if requested, and set MAC instance for devices that share
1075 * CS4227.
1076 **/
ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw * hw)1077 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1078 {
1079 struct ixgbe_bus_info *bus = &hw->bus;
1080 u32 reg;
1081 u16 ee_ctrl_4;
1082
1083 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1084
1085 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1086 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1087 bus->lan_id = (u8)bus->func;
1088
1089 /* check for a port swap */
1090 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
1091 if (reg & IXGBE_FACTPS_LFS)
1092 bus->func ^= 0x1;
1093
1094 /* Get MAC instance from EEPROM for configuring CS4227 */
1095 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
1096 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
1097 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>
1098 IXGBE_EE_CTRL_4_INST_ID_SHIFT;
1099 }
1100 }
1101
1102 /**
1103 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1104 * @hw: pointer to hardware structure
1105 *
1106 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1107 * disables transmit and receive units. The adapter_stopped flag is used by
1108 * the shared code and drivers to determine if the adapter is in a stopped
1109 * state and should not touch the hardware.
1110 **/
ixgbe_stop_adapter_generic(struct ixgbe_hw * hw)1111 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1112 {
1113 u32 reg_val;
1114 u16 i;
1115
1116 DEBUGFUNC("ixgbe_stop_adapter_generic");
1117
1118 /*
1119 * Set the adapter_stopped flag so other driver functions stop touching
1120 * the hardware
1121 */
1122 hw->adapter_stopped = TRUE;
1123
1124 /* Disable the receive unit */
1125 ixgbe_disable_rx(hw);
1126
1127 /* Clear interrupt mask to stop interrupts from being generated */
1128 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1129
1130 /* Clear any pending interrupts, flush previous writes */
1131 IXGBE_READ_REG(hw, IXGBE_EICR);
1132
1133 /* Disable the transmit unit. Each queue must be disabled. */
1134 for (i = 0; i < hw->mac.max_tx_queues; i++)
1135 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1136
1137 /* Disable the receive unit by stopping each queue */
1138 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1139 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1140 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1141 reg_val |= IXGBE_RXDCTL_SWFLSH;
1142 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1143 }
1144
1145 /* flush all queues disables */
1146 IXGBE_WRITE_FLUSH(hw);
1147 msec_delay(2);
1148
1149 /*
1150 * Prevent the PCI-E bus from hanging by disabling PCI-E master
1151 * access and verify no pending requests
1152 */
1153 return ixgbe_disable_pcie_master(hw);
1154 }
1155
1156 /**
1157 * ixgbe_init_led_link_act_generic - Store the LED index link/activity.
1158 * @hw: pointer to hardware structure
1159 *
1160 * Store the index for the link active LED. This will be used to support
1161 * blinking the LED.
1162 **/
ixgbe_init_led_link_act_generic(struct ixgbe_hw * hw)1163 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw)
1164 {
1165 struct ixgbe_mac_info *mac = &hw->mac;
1166 u32 led_reg, led_mode;
1167 u8 i;
1168
1169 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1170
1171 /* Get LED link active from the LEDCTL register */
1172 for (i = 0; i < 4; i++) {
1173 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i);
1174
1175 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) ==
1176 IXGBE_LED_LINK_ACTIVE) {
1177 mac->led_link_act = i;
1178 return IXGBE_SUCCESS;
1179 }
1180 }
1181
1182 /*
1183 * If LEDCTL register does not have the LED link active set, then use
1184 * known MAC defaults.
1185 */
1186 switch (hw->mac.type) {
1187 case ixgbe_mac_X550EM_a:
1188 case ixgbe_mac_X550EM_x:
1189 mac->led_link_act = 1;
1190 break;
1191 default:
1192 mac->led_link_act = 2;
1193 }
1194 return IXGBE_SUCCESS;
1195 }
1196
1197 /**
1198 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1199 * @hw: pointer to hardware structure
1200 * @index: led number to turn on
1201 **/
ixgbe_led_on_generic(struct ixgbe_hw * hw,u32 index)1202 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1203 {
1204 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1205
1206 DEBUGFUNC("ixgbe_led_on_generic");
1207
1208 if (index > 3)
1209 return IXGBE_ERR_PARAM;
1210
1211 /* To turn on the LED, set mode to ON. */
1212 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1213 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1214 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1215 IXGBE_WRITE_FLUSH(hw);
1216
1217 return IXGBE_SUCCESS;
1218 }
1219
1220 /**
1221 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1222 * @hw: pointer to hardware structure
1223 * @index: led number to turn off
1224 **/
ixgbe_led_off_generic(struct ixgbe_hw * hw,u32 index)1225 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1226 {
1227 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1228
1229 DEBUGFUNC("ixgbe_led_off_generic");
1230
1231 if (index > 3)
1232 return IXGBE_ERR_PARAM;
1233
1234 /* To turn off the LED, set mode to OFF. */
1235 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1236 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1237 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1238 IXGBE_WRITE_FLUSH(hw);
1239
1240 return IXGBE_SUCCESS;
1241 }
1242
1243 /**
1244 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1245 * @hw: pointer to hardware structure
1246 *
1247 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1248 * ixgbe_hw struct in order to set up EEPROM access.
1249 **/
ixgbe_init_eeprom_params_generic(struct ixgbe_hw * hw)1250 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1251 {
1252 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1253 u32 eec;
1254 u16 eeprom_size;
1255
1256 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1257
1258 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1259 eeprom->type = ixgbe_eeprom_none;
1260 /* Set default semaphore delay to 10ms which is a well
1261 * tested value */
1262 eeprom->semaphore_delay = 10;
1263 /* Clear EEPROM page size, it will be initialized as needed */
1264 eeprom->word_page_size = 0;
1265
1266 /*
1267 * Check for EEPROM present first.
1268 * If not present leave as none
1269 */
1270 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1271 if (eec & IXGBE_EEC_PRES) {
1272 eeprom->type = ixgbe_eeprom_spi;
1273
1274 /*
1275 * SPI EEPROM is assumed here. This code would need to
1276 * change if a future EEPROM is not SPI.
1277 */
1278 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1279 IXGBE_EEC_SIZE_SHIFT);
1280 eeprom->word_size = 1 << (eeprom_size +
1281 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1282 }
1283
1284 if (eec & IXGBE_EEC_ADDR_SIZE)
1285 eeprom->address_bits = 16;
1286 else
1287 eeprom->address_bits = 8;
1288 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1289 "%d\n", eeprom->type, eeprom->word_size,
1290 eeprom->address_bits);
1291 }
1292
1293 return IXGBE_SUCCESS;
1294 }
1295
1296 /**
1297 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1298 * @hw: pointer to hardware structure
1299 * @offset: offset within the EEPROM to write
1300 * @words: number of word(s)
1301 * @data: 16 bit word(s) to write to EEPROM
1302 *
1303 * Reads 16 bit word(s) from EEPROM through bit-bang method
1304 **/
ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1305 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1306 u16 words, u16 *data)
1307 {
1308 s32 status = IXGBE_SUCCESS;
1309 u16 i, count;
1310
1311 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1312
1313 hw->eeprom.ops.init_params(hw);
1314
1315 if (words == 0) {
1316 status = IXGBE_ERR_INVALID_ARGUMENT;
1317 goto out;
1318 }
1319
1320 if (offset + words > hw->eeprom.word_size) {
1321 status = IXGBE_ERR_EEPROM;
1322 goto out;
1323 }
1324
1325 /*
1326 * The EEPROM page size cannot be queried from the chip. We do lazy
1327 * initialization. It is worth to do that when we write large buffer.
1328 */
1329 if ((hw->eeprom.word_page_size == 0) &&
1330 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1331 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1332
1333 /*
1334 * We cannot hold synchronization semaphores for too long
1335 * to avoid other entity starvation. However it is more efficient
1336 * to read in bursts than synchronizing access for each word.
1337 */
1338 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1339 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1340 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1341 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1342 count, &data[i]);
1343
1344 if (status != IXGBE_SUCCESS)
1345 break;
1346 }
1347
1348 out:
1349 return status;
1350 }
1351
1352 /**
1353 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1354 * @hw: pointer to hardware structure
1355 * @offset: offset within the EEPROM to be written to
1356 * @words: number of word(s)
1357 * @data: 16 bit word(s) to be written to the EEPROM
1358 *
1359 * If ixgbe_eeprom_update_checksum is not called after this function, the
1360 * EEPROM will most likely contain an invalid checksum.
1361 **/
ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1362 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1363 u16 words, u16 *data)
1364 {
1365 s32 status;
1366 u16 word;
1367 u16 page_size;
1368 u16 i;
1369 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1370
1371 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1372
1373 /* Prepare the EEPROM for writing */
1374 status = ixgbe_acquire_eeprom(hw);
1375
1376 if (status == IXGBE_SUCCESS) {
1377 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1378 ixgbe_release_eeprom(hw);
1379 status = IXGBE_ERR_EEPROM;
1380 }
1381 }
1382
1383 if (status == IXGBE_SUCCESS) {
1384 for (i = 0; i < words; i++) {
1385 ixgbe_standby_eeprom(hw);
1386
1387 /* Send the WRITE ENABLE command (8 bit opcode ) */
1388 ixgbe_shift_out_eeprom_bits(hw,
1389 IXGBE_EEPROM_WREN_OPCODE_SPI,
1390 IXGBE_EEPROM_OPCODE_BITS);
1391
1392 ixgbe_standby_eeprom(hw);
1393
1394 /*
1395 * Some SPI eeproms use the 8th address bit embedded
1396 * in the opcode
1397 */
1398 if ((hw->eeprom.address_bits == 8) &&
1399 ((offset + i) >= 128))
1400 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1401
1402 /* Send the Write command (8-bit opcode + addr) */
1403 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1404 IXGBE_EEPROM_OPCODE_BITS);
1405 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1406 hw->eeprom.address_bits);
1407
1408 page_size = hw->eeprom.word_page_size;
1409
1410 /* Send the data in burst via SPI*/
1411 do {
1412 word = data[i];
1413 word = (word >> 8) | (word << 8);
1414 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1415
1416 if (page_size == 0)
1417 break;
1418
1419 /* do not wrap around page */
1420 if (((offset + i) & (page_size - 1)) ==
1421 (page_size - 1))
1422 break;
1423 } while (++i < words);
1424
1425 ixgbe_standby_eeprom(hw);
1426 msec_delay(10);
1427 }
1428 /* Done with writing - release the EEPROM */
1429 ixgbe_release_eeprom(hw);
1430 }
1431
1432 return status;
1433 }
1434
1435 /**
1436 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1437 * @hw: pointer to hardware structure
1438 * @offset: offset within the EEPROM to be written to
1439 * @data: 16 bit word to be written to the EEPROM
1440 *
1441 * If ixgbe_eeprom_update_checksum is not called after this function, the
1442 * EEPROM will most likely contain an invalid checksum.
1443 **/
ixgbe_write_eeprom_generic(struct ixgbe_hw * hw,u16 offset,u16 data)1444 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1445 {
1446 s32 status;
1447
1448 DEBUGFUNC("ixgbe_write_eeprom_generic");
1449
1450 hw->eeprom.ops.init_params(hw);
1451
1452 if (offset >= hw->eeprom.word_size) {
1453 status = IXGBE_ERR_EEPROM;
1454 goto out;
1455 }
1456
1457 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1458
1459 out:
1460 return status;
1461 }
1462
1463 /**
1464 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1465 * @hw: pointer to hardware structure
1466 * @offset: offset within the EEPROM to be read
1467 * @data: read 16 bit words(s) from EEPROM
1468 * @words: number of word(s)
1469 *
1470 * Reads 16 bit word(s) from EEPROM through bit-bang method
1471 **/
ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1472 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1473 u16 words, u16 *data)
1474 {
1475 s32 status = IXGBE_SUCCESS;
1476 u16 i, count;
1477
1478 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1479
1480 hw->eeprom.ops.init_params(hw);
1481
1482 if (words == 0) {
1483 status = IXGBE_ERR_INVALID_ARGUMENT;
1484 goto out;
1485 }
1486
1487 if (offset + words > hw->eeprom.word_size) {
1488 status = IXGBE_ERR_EEPROM;
1489 goto out;
1490 }
1491
1492 /*
1493 * We cannot hold synchronization semaphores for too long
1494 * to avoid other entity starvation. However it is more efficient
1495 * to read in bursts than synchronizing access for each word.
1496 */
1497 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1498 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1499 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1500
1501 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1502 count, &data[i]);
1503
1504 if (status != IXGBE_SUCCESS)
1505 break;
1506 }
1507
1508 out:
1509 return status;
1510 }
1511
1512 /**
1513 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1514 * @hw: pointer to hardware structure
1515 * @offset: offset within the EEPROM to be read
1516 * @words: number of word(s)
1517 * @data: read 16 bit word(s) from EEPROM
1518 *
1519 * Reads 16 bit word(s) from EEPROM through bit-bang method
1520 **/
ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1521 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1522 u16 words, u16 *data)
1523 {
1524 s32 status;
1525 u16 word_in;
1526 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1527 u16 i;
1528
1529 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1530
1531 /* Prepare the EEPROM for reading */
1532 status = ixgbe_acquire_eeprom(hw);
1533
1534 if (status == IXGBE_SUCCESS) {
1535 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1536 ixgbe_release_eeprom(hw);
1537 status = IXGBE_ERR_EEPROM;
1538 }
1539 }
1540
1541 if (status == IXGBE_SUCCESS) {
1542 for (i = 0; i < words; i++) {
1543 ixgbe_standby_eeprom(hw);
1544 /*
1545 * Some SPI eeproms use the 8th address bit embedded
1546 * in the opcode
1547 */
1548 if ((hw->eeprom.address_bits == 8) &&
1549 ((offset + i) >= 128))
1550 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1551
1552 /* Send the READ command (opcode + addr) */
1553 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1554 IXGBE_EEPROM_OPCODE_BITS);
1555 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1556 hw->eeprom.address_bits);
1557
1558 /* Read the data. */
1559 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1560 data[i] = (word_in >> 8) | (word_in << 8);
1561 }
1562
1563 /* End this read operation */
1564 ixgbe_release_eeprom(hw);
1565 }
1566
1567 return status;
1568 }
1569
1570 /**
1571 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1572 * @hw: pointer to hardware structure
1573 * @offset: offset within the EEPROM to be read
1574 * @data: read 16 bit value from EEPROM
1575 *
1576 * Reads 16 bit value from EEPROM through bit-bang method
1577 **/
ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw * hw,u16 offset,u16 * data)1578 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1579 u16 *data)
1580 {
1581 s32 status;
1582
1583 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1584
1585 hw->eeprom.ops.init_params(hw);
1586
1587 if (offset >= hw->eeprom.word_size) {
1588 status = IXGBE_ERR_EEPROM;
1589 goto out;
1590 }
1591
1592 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1593
1594 out:
1595 return status;
1596 }
1597
1598 /**
1599 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1600 * @hw: pointer to hardware structure
1601 * @offset: offset of word in the EEPROM to read
1602 * @words: number of word(s)
1603 * @data: 16 bit word(s) from the EEPROM
1604 *
1605 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1606 **/
ixgbe_read_eerd_buffer_generic(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1607 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1608 u16 words, u16 *data)
1609 {
1610 u32 eerd;
1611 s32 status = IXGBE_SUCCESS;
1612 u32 i;
1613
1614 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1615
1616 hw->eeprom.ops.init_params(hw);
1617
1618 if (words == 0) {
1619 status = IXGBE_ERR_INVALID_ARGUMENT;
1620 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1621 goto out;
1622 }
1623
1624 if (offset >= hw->eeprom.word_size) {
1625 status = IXGBE_ERR_EEPROM;
1626 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1627 goto out;
1628 }
1629
1630 for (i = 0; i < words; i++) {
1631 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1632 IXGBE_EEPROM_RW_REG_START;
1633
1634 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1635 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1636
1637 if (status == IXGBE_SUCCESS) {
1638 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1639 IXGBE_EEPROM_RW_REG_DATA);
1640 } else {
1641 DEBUGOUT("Eeprom read timed out\n");
1642 goto out;
1643 }
1644 }
1645 out:
1646 return status;
1647 }
1648
1649 /**
1650 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1651 * @hw: pointer to hardware structure
1652 * @offset: offset within the EEPROM to be used as a scratch pad
1653 *
1654 * Discover EEPROM page size by writing marching data at given offset.
1655 * This function is called only when we are writing a new large buffer
1656 * at given offset so the data would be overwritten anyway.
1657 **/
ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw * hw,u16 offset)1658 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1659 u16 offset)
1660 {
1661 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1662 s32 status = IXGBE_SUCCESS;
1663 u16 i;
1664
1665 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1666
1667 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1668 data[i] = i;
1669
1670 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1671 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1672 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1673 hw->eeprom.word_page_size = 0;
1674 if (status != IXGBE_SUCCESS)
1675 goto out;
1676
1677 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1678 if (status != IXGBE_SUCCESS)
1679 goto out;
1680
1681 /*
1682 * When writing in burst more than the actual page size
1683 * EEPROM address wraps around current page.
1684 */
1685 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1686
1687 DEBUGOUT1("Detected EEPROM page size = %d words.",
1688 hw->eeprom.word_page_size);
1689 out:
1690 return status;
1691 }
1692
1693 /**
1694 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1695 * @hw: pointer to hardware structure
1696 * @offset: offset of word in the EEPROM to read
1697 * @data: word read from the EEPROM
1698 *
1699 * Reads a 16 bit word from the EEPROM using the EERD register.
1700 **/
ixgbe_read_eerd_generic(struct ixgbe_hw * hw,u16 offset,u16 * data)1701 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1702 {
1703 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1704 }
1705
1706 /**
1707 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1708 * @hw: pointer to hardware structure
1709 * @offset: offset of word in the EEPROM to write
1710 * @words: number of word(s)
1711 * @data: word(s) write to the EEPROM
1712 *
1713 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1714 **/
ixgbe_write_eewr_buffer_generic(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1715 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1716 u16 words, u16 *data)
1717 {
1718 u32 eewr;
1719 s32 status = IXGBE_SUCCESS;
1720 u16 i;
1721
1722 DEBUGFUNC("ixgbe_write_eewr_generic");
1723
1724 hw->eeprom.ops.init_params(hw);
1725
1726 if (words == 0) {
1727 status = IXGBE_ERR_INVALID_ARGUMENT;
1728 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1729 goto out;
1730 }
1731
1732 if (offset >= hw->eeprom.word_size) {
1733 status = IXGBE_ERR_EEPROM;
1734 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1735 goto out;
1736 }
1737
1738 for (i = 0; i < words; i++) {
1739 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1740 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1741 IXGBE_EEPROM_RW_REG_START;
1742
1743 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1744 if (status != IXGBE_SUCCESS) {
1745 DEBUGOUT("Eeprom write EEWR timed out\n");
1746 goto out;
1747 }
1748
1749 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1750
1751 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1752 if (status != IXGBE_SUCCESS) {
1753 DEBUGOUT("Eeprom write EEWR timed out\n");
1754 goto out;
1755 }
1756 }
1757
1758 out:
1759 return status;
1760 }
1761
1762 /**
1763 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1764 * @hw: pointer to hardware structure
1765 * @offset: offset of word in the EEPROM to write
1766 * @data: word write to the EEPROM
1767 *
1768 * Write a 16 bit word to the EEPROM using the EEWR register.
1769 **/
ixgbe_write_eewr_generic(struct ixgbe_hw * hw,u16 offset,u16 data)1770 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1771 {
1772 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1773 }
1774
1775 /**
1776 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1777 * @hw: pointer to hardware structure
1778 * @ee_reg: EEPROM flag for polling
1779 *
1780 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1781 * read or write is done respectively.
1782 **/
ixgbe_poll_eerd_eewr_done(struct ixgbe_hw * hw,u32 ee_reg)1783 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1784 {
1785 u32 i;
1786 u32 reg;
1787 s32 status = IXGBE_ERR_EEPROM;
1788
1789 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1790
1791 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1792 if (ee_reg == IXGBE_NVM_POLL_READ)
1793 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1794 else
1795 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1796
1797 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1798 status = IXGBE_SUCCESS;
1799 break;
1800 }
1801 usec_delay(5);
1802 }
1803
1804 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1805 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1806 "EEPROM read/write done polling timed out");
1807
1808 return status;
1809 }
1810
1811 /**
1812 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1813 * @hw: pointer to hardware structure
1814 *
1815 * Prepares EEPROM for access using bit-bang method. This function should
1816 * be called before issuing a command to the EEPROM.
1817 **/
ixgbe_acquire_eeprom(struct ixgbe_hw * hw)1818 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1819 {
1820 s32 status = IXGBE_SUCCESS;
1821 u32 eec;
1822 u32 i;
1823
1824 DEBUGFUNC("ixgbe_acquire_eeprom");
1825
1826 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1827 != IXGBE_SUCCESS)
1828 status = IXGBE_ERR_SWFW_SYNC;
1829
1830 if (status == IXGBE_SUCCESS) {
1831 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1832
1833 /* Request EEPROM Access */
1834 eec |= IXGBE_EEC_REQ;
1835 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1836
1837 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1838 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1839 if (eec & IXGBE_EEC_GNT)
1840 break;
1841 usec_delay(5);
1842 }
1843
1844 /* Release if grant not acquired */
1845 if (!(eec & IXGBE_EEC_GNT)) {
1846 eec &= ~IXGBE_EEC_REQ;
1847 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1848 DEBUGOUT("Could not acquire EEPROM grant\n");
1849
1850 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1851 status = IXGBE_ERR_EEPROM;
1852 }
1853
1854 /* Setup EEPROM for Read/Write */
1855 if (status == IXGBE_SUCCESS) {
1856 /* Clear CS and SK */
1857 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1858 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1859 IXGBE_WRITE_FLUSH(hw);
1860 usec_delay(1);
1861 }
1862 }
1863 return status;
1864 }
1865
1866 /**
1867 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1868 * @hw: pointer to hardware structure
1869 *
1870 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1871 **/
ixgbe_get_eeprom_semaphore(struct ixgbe_hw * hw)1872 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1873 {
1874 s32 status = IXGBE_ERR_EEPROM;
1875 u32 timeout = 2000;
1876 u32 i;
1877 u32 swsm;
1878
1879 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1880
1881
1882 /* Get SMBI software semaphore between device drivers first */
1883 for (i = 0; i < timeout; i++) {
1884 /*
1885 * If the SMBI bit is 0 when we read it, then the bit will be
1886 * set and we have the semaphore
1887 */
1888 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1889 if (!(swsm & IXGBE_SWSM_SMBI)) {
1890 status = IXGBE_SUCCESS;
1891 break;
1892 }
1893 usec_delay(50);
1894 }
1895
1896 if (i == timeout) {
1897 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1898 "not granted.\n");
1899 /*
1900 * this release is particularly important because our attempts
1901 * above to get the semaphore may have succeeded, and if there
1902 * was a timeout, we should unconditionally clear the semaphore
1903 * bits to free the driver to make progress
1904 */
1905 ixgbe_release_eeprom_semaphore(hw);
1906
1907 usec_delay(50);
1908 /*
1909 * one last try
1910 * If the SMBI bit is 0 when we read it, then the bit will be
1911 * set and we have the semaphore
1912 */
1913 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1914 if (!(swsm & IXGBE_SWSM_SMBI))
1915 status = IXGBE_SUCCESS;
1916 }
1917
1918 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1919 if (status == IXGBE_SUCCESS) {
1920 for (i = 0; i < timeout; i++) {
1921 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1922
1923 /* Set the SW EEPROM semaphore bit to request access */
1924 swsm |= IXGBE_SWSM_SWESMBI;
1925 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
1926
1927 /*
1928 * If we set the bit successfully then we got the
1929 * semaphore.
1930 */
1931 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1932 if (swsm & IXGBE_SWSM_SWESMBI)
1933 break;
1934
1935 usec_delay(50);
1936 }
1937
1938 /*
1939 * Release semaphores and return error if SW EEPROM semaphore
1940 * was not granted because we don't have access to the EEPROM
1941 */
1942 if (i >= timeout) {
1943 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1944 "SWESMBI Software EEPROM semaphore not granted.\n");
1945 ixgbe_release_eeprom_semaphore(hw);
1946 status = IXGBE_ERR_EEPROM;
1947 }
1948 } else {
1949 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1950 "Software semaphore SMBI between device drivers "
1951 "not granted.\n");
1952 }
1953
1954 return status;
1955 }
1956
1957 /**
1958 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1959 * @hw: pointer to hardware structure
1960 *
1961 * This function clears hardware semaphore bits.
1962 **/
ixgbe_release_eeprom_semaphore(struct ixgbe_hw * hw)1963 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1964 {
1965 u32 swsm;
1966
1967 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1968
1969 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1970
1971 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1972 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1973 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1974 IXGBE_WRITE_FLUSH(hw);
1975 }
1976
1977 /**
1978 * ixgbe_ready_eeprom - Polls for EEPROM ready
1979 * @hw: pointer to hardware structure
1980 **/
ixgbe_ready_eeprom(struct ixgbe_hw * hw)1981 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1982 {
1983 s32 status = IXGBE_SUCCESS;
1984 u16 i;
1985 u8 spi_stat_reg;
1986
1987 DEBUGFUNC("ixgbe_ready_eeprom");
1988
1989 /*
1990 * Read "Status Register" repeatedly until the LSB is cleared. The
1991 * EEPROM will signal that the command has been completed by clearing
1992 * bit 0 of the internal status register. If it's not cleared within
1993 * 5 milliseconds, then error out.
1994 */
1995 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1996 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1997 IXGBE_EEPROM_OPCODE_BITS);
1998 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1999 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
2000 break;
2001
2002 usec_delay(5);
2003 ixgbe_standby_eeprom(hw);
2004 };
2005
2006 /*
2007 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
2008 * devices (and only 0-5mSec on 5V devices)
2009 */
2010 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
2011 DEBUGOUT("SPI EEPROM Status error\n");
2012 status = IXGBE_ERR_EEPROM;
2013 }
2014
2015 return status;
2016 }
2017
2018 /**
2019 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
2020 * @hw: pointer to hardware structure
2021 **/
ixgbe_standby_eeprom(struct ixgbe_hw * hw)2022 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
2023 {
2024 u32 eec;
2025
2026 DEBUGFUNC("ixgbe_standby_eeprom");
2027
2028 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2029
2030 /* Toggle CS to flush commands */
2031 eec |= IXGBE_EEC_CS;
2032 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2033 IXGBE_WRITE_FLUSH(hw);
2034 usec_delay(1);
2035 eec &= ~IXGBE_EEC_CS;
2036 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2037 IXGBE_WRITE_FLUSH(hw);
2038 usec_delay(1);
2039 }
2040
2041 /**
2042 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
2043 * @hw: pointer to hardware structure
2044 * @data: data to send to the EEPROM
2045 * @count: number of bits to shift out
2046 **/
ixgbe_shift_out_eeprom_bits(struct ixgbe_hw * hw,u16 data,u16 count)2047 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
2048 u16 count)
2049 {
2050 u32 eec;
2051 u32 mask;
2052 u32 i;
2053
2054 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
2055
2056 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2057
2058 /*
2059 * Mask is used to shift "count" bits of "data" out to the EEPROM
2060 * one bit at a time. Determine the starting bit based on count
2061 */
2062 mask = 0x01 << (count - 1);
2063
2064 for (i = 0; i < count; i++) {
2065 /*
2066 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
2067 * "1", and then raising and then lowering the clock (the SK
2068 * bit controls the clock input to the EEPROM). A "0" is
2069 * shifted out to the EEPROM by setting "DI" to "0" and then
2070 * raising and then lowering the clock.
2071 */
2072 if (data & mask)
2073 eec |= IXGBE_EEC_DI;
2074 else
2075 eec &= ~IXGBE_EEC_DI;
2076
2077 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2078 IXGBE_WRITE_FLUSH(hw);
2079
2080 usec_delay(1);
2081
2082 ixgbe_raise_eeprom_clk(hw, &eec);
2083 ixgbe_lower_eeprom_clk(hw, &eec);
2084
2085 /*
2086 * Shift mask to signify next bit of data to shift in to the
2087 * EEPROM
2088 */
2089 mask = mask >> 1;
2090 };
2091
2092 /* We leave the "DI" bit set to "0" when we leave this routine. */
2093 eec &= ~IXGBE_EEC_DI;
2094 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2095 IXGBE_WRITE_FLUSH(hw);
2096 }
2097
2098 /**
2099 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
2100 * @hw: pointer to hardware structure
2101 **/
ixgbe_shift_in_eeprom_bits(struct ixgbe_hw * hw,u16 count)2102 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2103 {
2104 u32 eec;
2105 u32 i;
2106 u16 data = 0;
2107
2108 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2109
2110 /*
2111 * In order to read a register from the EEPROM, we need to shift
2112 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2113 * the clock input to the EEPROM (setting the SK bit), and then reading
2114 * the value of the "DO" bit. During this "shifting in" process the
2115 * "DI" bit should always be clear.
2116 */
2117 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2118
2119 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2120
2121 for (i = 0; i < count; i++) {
2122 data = data << 1;
2123 ixgbe_raise_eeprom_clk(hw, &eec);
2124
2125 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2126
2127 eec &= ~(IXGBE_EEC_DI);
2128 if (eec & IXGBE_EEC_DO)
2129 data |= 1;
2130
2131 ixgbe_lower_eeprom_clk(hw, &eec);
2132 }
2133
2134 return data;
2135 }
2136
2137 /**
2138 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2139 * @hw: pointer to hardware structure
2140 * @eec: EEC register's current value
2141 **/
ixgbe_raise_eeprom_clk(struct ixgbe_hw * hw,u32 * eec)2142 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2143 {
2144 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2145
2146 /*
2147 * Raise the clock input to the EEPROM
2148 * (setting the SK bit), then delay
2149 */
2150 *eec = *eec | IXGBE_EEC_SK;
2151 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2152 IXGBE_WRITE_FLUSH(hw);
2153 usec_delay(1);
2154 }
2155
2156 /**
2157 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2158 * @hw: pointer to hardware structure
2159 * @eecd: EECD's current value
2160 **/
ixgbe_lower_eeprom_clk(struct ixgbe_hw * hw,u32 * eec)2161 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2162 {
2163 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2164
2165 /*
2166 * Lower the clock input to the EEPROM (clearing the SK bit), then
2167 * delay
2168 */
2169 *eec = *eec & ~IXGBE_EEC_SK;
2170 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2171 IXGBE_WRITE_FLUSH(hw);
2172 usec_delay(1);
2173 }
2174
2175 /**
2176 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2177 * @hw: pointer to hardware structure
2178 **/
ixgbe_release_eeprom(struct ixgbe_hw * hw)2179 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2180 {
2181 u32 eec;
2182
2183 DEBUGFUNC("ixgbe_release_eeprom");
2184
2185 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2186
2187 eec |= IXGBE_EEC_CS; /* Pull CS high */
2188 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2189
2190 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2191 IXGBE_WRITE_FLUSH(hw);
2192
2193 usec_delay(1);
2194
2195 /* Stop requesting EEPROM access */
2196 eec &= ~IXGBE_EEC_REQ;
2197 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2198
2199 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2200
2201 /* Delay before attempt to obtain semaphore again to allow FW access */
2202 msec_delay(hw->eeprom.semaphore_delay);
2203 }
2204
2205 /**
2206 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2207 * @hw: pointer to hardware structure
2208 *
2209 * Returns a negative error code on error, or the 16-bit checksum
2210 **/
ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw * hw)2211 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2212 {
2213 u16 i;
2214 u16 j;
2215 u16 checksum = 0;
2216 u16 length = 0;
2217 u16 pointer = 0;
2218 u16 word = 0;
2219
2220 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2221
2222 /* Include 0x0-0x3F in the checksum */
2223 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2224 if (hw->eeprom.ops.read(hw, i, &word)) {
2225 DEBUGOUT("EEPROM read failed\n");
2226 return IXGBE_ERR_EEPROM;
2227 }
2228 checksum += word;
2229 }
2230
2231 /* Include all data from pointers except for the fw pointer */
2232 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2233 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2234 DEBUGOUT("EEPROM read failed\n");
2235 return IXGBE_ERR_EEPROM;
2236 }
2237
2238 /* If the pointer seems invalid */
2239 if (pointer == 0xFFFF || pointer == 0)
2240 continue;
2241
2242 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2243 DEBUGOUT("EEPROM read failed\n");
2244 return IXGBE_ERR_EEPROM;
2245 }
2246
2247 if (length == 0xFFFF || length == 0)
2248 continue;
2249
2250 for (j = pointer + 1; j <= pointer + length; j++) {
2251 if (hw->eeprom.ops.read(hw, j, &word)) {
2252 DEBUGOUT("EEPROM read failed\n");
2253 return IXGBE_ERR_EEPROM;
2254 }
2255 checksum += word;
2256 }
2257 }
2258
2259 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2260
2261 return (s32)checksum;
2262 }
2263
2264 /**
2265 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2266 * @hw: pointer to hardware structure
2267 * @checksum_val: calculated checksum
2268 *
2269 * Performs checksum calculation and validates the EEPROM checksum. If the
2270 * caller does not need checksum_val, the value can be NULL.
2271 **/
ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw * hw,u16 * checksum_val)2272 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2273 u16 *checksum_val)
2274 {
2275 s32 status;
2276 u16 checksum;
2277 u16 read_checksum = 0;
2278
2279 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2280
2281 /* Read the first word from the EEPROM. If this times out or fails, do
2282 * not continue or we could be in for a very long wait while every
2283 * EEPROM read fails
2284 */
2285 status = hw->eeprom.ops.read(hw, 0, &checksum);
2286 if (status) {
2287 DEBUGOUT("EEPROM read failed\n");
2288 return status;
2289 }
2290
2291 status = hw->eeprom.ops.calc_checksum(hw);
2292 if (status < 0)
2293 return status;
2294
2295 checksum = (u16)(status & 0xffff);
2296
2297 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2298 if (status) {
2299 DEBUGOUT("EEPROM read failed\n");
2300 return status;
2301 }
2302
2303 /* Verify read checksum from EEPROM is the same as
2304 * calculated checksum
2305 */
2306 if (read_checksum != checksum)
2307 status = IXGBE_ERR_EEPROM_CHECKSUM;
2308
2309 /* If the user cares, return the calculated checksum */
2310 if (checksum_val)
2311 *checksum_val = checksum;
2312
2313 return status;
2314 }
2315
2316 /**
2317 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2318 * @hw: pointer to hardware structure
2319 **/
ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw * hw)2320 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2321 {
2322 s32 status;
2323 u16 checksum;
2324
2325 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2326
2327 /* Read the first word from the EEPROM. If this times out or fails, do
2328 * not continue or we could be in for a very long wait while every
2329 * EEPROM read fails
2330 */
2331 status = hw->eeprom.ops.read(hw, 0, &checksum);
2332 if (status) {
2333 DEBUGOUT("EEPROM read failed\n");
2334 return status;
2335 }
2336
2337 status = hw->eeprom.ops.calc_checksum(hw);
2338 if (status < 0)
2339 return status;
2340
2341 checksum = (u16)(status & 0xffff);
2342
2343 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2344
2345 return status;
2346 }
2347
2348 /**
2349 * ixgbe_validate_mac_addr - Validate MAC address
2350 * @mac_addr: pointer to MAC address.
2351 *
2352 * Tests a MAC address to ensure it is a valid Individual Address.
2353 **/
ixgbe_validate_mac_addr(u8 * mac_addr)2354 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2355 {
2356 s32 status = IXGBE_SUCCESS;
2357
2358 DEBUGFUNC("ixgbe_validate_mac_addr");
2359
2360 /* Make sure it is not a multicast address */
2361 if (IXGBE_IS_MULTICAST(mac_addr)) {
2362 status = IXGBE_ERR_INVALID_MAC_ADDR;
2363 /* Not a broadcast address */
2364 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2365 status = IXGBE_ERR_INVALID_MAC_ADDR;
2366 /* Reject the zero address */
2367 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2368 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2369 status = IXGBE_ERR_INVALID_MAC_ADDR;
2370 }
2371 return status;
2372 }
2373
2374 /**
2375 * ixgbe_set_rar_generic - Set Rx address register
2376 * @hw: pointer to hardware structure
2377 * @index: Receive address register to write
2378 * @addr: Address to put into receive address register
2379 * @vmdq: VMDq "set" or "pool" index
2380 * @enable_addr: set flag that address is active
2381 *
2382 * Puts an ethernet address into a receive address register.
2383 **/
ixgbe_set_rar_generic(struct ixgbe_hw * hw,u32 index,u8 * addr,u32 vmdq,u32 enable_addr)2384 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2385 u32 enable_addr)
2386 {
2387 u32 rar_low, rar_high;
2388 u32 rar_entries = hw->mac.num_rar_entries;
2389
2390 DEBUGFUNC("ixgbe_set_rar_generic");
2391
2392 /* Make sure we are using a valid rar index range */
2393 if (index >= rar_entries) {
2394 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2395 "RAR index %d is out of range.\n", index);
2396 return IXGBE_ERR_INVALID_ARGUMENT;
2397 }
2398
2399 /* setup VMDq pool selection before this RAR gets enabled */
2400 hw->mac.ops.set_vmdq(hw, index, vmdq);
2401
2402 /*
2403 * HW expects these in little endian so we reverse the byte
2404 * order from network order (big endian) to little endian
2405 */
2406 rar_low = ((u32)addr[0] |
2407 ((u32)addr[1] << 8) |
2408 ((u32)addr[2] << 16) |
2409 ((u32)addr[3] << 24));
2410 /*
2411 * Some parts put the VMDq setting in the extra RAH bits,
2412 * so save everything except the lower 16 bits that hold part
2413 * of the address and the address valid bit.
2414 */
2415 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2416 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2417 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2418
2419 if (enable_addr != 0)
2420 rar_high |= IXGBE_RAH_AV;
2421
2422 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2423 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2424
2425 return IXGBE_SUCCESS;
2426 }
2427
2428 /**
2429 * ixgbe_clear_rar_generic - Remove Rx address register
2430 * @hw: pointer to hardware structure
2431 * @index: Receive address register to write
2432 *
2433 * Clears an ethernet address from a receive address register.
2434 **/
ixgbe_clear_rar_generic(struct ixgbe_hw * hw,u32 index)2435 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2436 {
2437 u32 rar_high;
2438 u32 rar_entries = hw->mac.num_rar_entries;
2439
2440 DEBUGFUNC("ixgbe_clear_rar_generic");
2441
2442 /* Make sure we are using a valid rar index range */
2443 if (index >= rar_entries) {
2444 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2445 "RAR index %d is out of range.\n", index);
2446 return IXGBE_ERR_INVALID_ARGUMENT;
2447 }
2448
2449 /*
2450 * Some parts put the VMDq setting in the extra RAH bits,
2451 * so save everything except the lower 16 bits that hold part
2452 * of the address and the address valid bit.
2453 */
2454 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2455 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2456
2457 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2458 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2459
2460 /* clear VMDq pool/queue selection for this RAR */
2461 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2462
2463 return IXGBE_SUCCESS;
2464 }
2465
2466 /**
2467 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2468 * @hw: pointer to hardware structure
2469 *
2470 * Places the MAC address in receive address register 0 and clears the rest
2471 * of the receive address registers. Clears the multicast table. Assumes
2472 * the receiver is in reset when the routine is called.
2473 **/
ixgbe_init_rx_addrs_generic(struct ixgbe_hw * hw)2474 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2475 {
2476 u32 i;
2477 u32 rar_entries = hw->mac.num_rar_entries;
2478
2479 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2480
2481 /*
2482 * If the current mac address is valid, assume it is a software override
2483 * to the permanent address.
2484 * Otherwise, use the permanent address from the eeprom.
2485 */
2486 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2487 IXGBE_ERR_INVALID_MAC_ADDR) {
2488 /* Get the MAC address from the RAR0 for later reference */
2489 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2490
2491 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2492 hw->mac.addr[0], hw->mac.addr[1],
2493 hw->mac.addr[2]);
2494 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2495 hw->mac.addr[4], hw->mac.addr[5]);
2496 } else {
2497 /* Setup the receive address. */
2498 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2499 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2500 hw->mac.addr[0], hw->mac.addr[1],
2501 hw->mac.addr[2]);
2502 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2503 hw->mac.addr[4], hw->mac.addr[5]);
2504
2505 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2506 }
2507
2508 /* clear VMDq pool/queue selection for RAR 0 */
2509 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2510
2511 hw->addr_ctrl.overflow_promisc = 0;
2512
2513 hw->addr_ctrl.rar_used_count = 1;
2514
2515 /* Zero out the other receive addresses. */
2516 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2517 for (i = 1; i < rar_entries; i++) {
2518 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2519 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2520 }
2521
2522 /* Clear the MTA */
2523 hw->addr_ctrl.mta_in_use = 0;
2524 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2525
2526 DEBUGOUT(" Clearing MTA\n");
2527 for (i = 0; i < hw->mac.mcft_size; i++)
2528 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2529
2530 ixgbe_init_uta_tables(hw);
2531
2532 return IXGBE_SUCCESS;
2533 }
2534
2535 /**
2536 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2537 * @hw: pointer to hardware structure
2538 * @addr: new address
2539 *
2540 * Adds it to unused receive address register or goes into promiscuous mode.
2541 **/
ixgbe_add_uc_addr(struct ixgbe_hw * hw,u8 * addr,u32 vmdq)2542 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2543 {
2544 u32 rar_entries = hw->mac.num_rar_entries;
2545 u32 rar;
2546
2547 DEBUGFUNC("ixgbe_add_uc_addr");
2548
2549 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2550 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2551
2552 /*
2553 * Place this address in the RAR if there is room,
2554 * else put the controller into promiscuous mode
2555 */
2556 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2557 rar = hw->addr_ctrl.rar_used_count;
2558 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2559 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2560 hw->addr_ctrl.rar_used_count++;
2561 } else {
2562 hw->addr_ctrl.overflow_promisc++;
2563 }
2564
2565 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2566 }
2567
2568 /**
2569 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2570 * @hw: pointer to hardware structure
2571 * @addr_list: the list of new addresses
2572 * @addr_count: number of addresses
2573 * @next: iterator function to walk the address list
2574 *
2575 * The given list replaces any existing list. Clears the secondary addrs from
2576 * receive address registers. Uses unused receive address registers for the
2577 * first secondary addresses, and falls back to promiscuous mode as needed.
2578 *
2579 * Drivers using secondary unicast addresses must set user_set_promisc when
2580 * manually putting the device into promiscuous mode.
2581 **/
ixgbe_update_uc_addr_list_generic(struct ixgbe_hw * hw,u8 * addr_list,u32 addr_count,ixgbe_mc_addr_itr next)2582 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2583 u32 addr_count, ixgbe_mc_addr_itr next)
2584 {
2585 u8 *addr;
2586 u32 i;
2587 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2588 u32 uc_addr_in_use;
2589 u32 fctrl;
2590 u32 vmdq;
2591
2592 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2593
2594 /*
2595 * Clear accounting of old secondary address list,
2596 * don't count RAR[0]
2597 */
2598 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2599 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2600 hw->addr_ctrl.overflow_promisc = 0;
2601
2602 /* Zero out the other receive addresses */
2603 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2604 for (i = 0; i < uc_addr_in_use; i++) {
2605 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2606 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2607 }
2608
2609 /* Add the new addresses */
2610 for (i = 0; i < addr_count; i++) {
2611 DEBUGOUT(" Adding the secondary addresses:\n");
2612 addr = next(hw, &addr_list, &vmdq);
2613 ixgbe_add_uc_addr(hw, addr, vmdq);
2614 }
2615
2616 if (hw->addr_ctrl.overflow_promisc) {
2617 /* enable promisc if not already in overflow or set by user */
2618 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2619 DEBUGOUT(" Entering address overflow promisc mode\n");
2620 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2621 fctrl |= IXGBE_FCTRL_UPE;
2622 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2623 }
2624 } else {
2625 /* only disable if set by overflow, not by user */
2626 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2627 DEBUGOUT(" Leaving address overflow promisc mode\n");
2628 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2629 fctrl &= ~IXGBE_FCTRL_UPE;
2630 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2631 }
2632 }
2633
2634 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2635 return IXGBE_SUCCESS;
2636 }
2637
2638 /**
2639 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2640 * @hw: pointer to hardware structure
2641 * @mc_addr: the multicast address
2642 *
2643 * Extracts the 12 bits, from a multicast address, to determine which
2644 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2645 * incoming rx multicast addresses, to determine the bit-vector to check in
2646 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2647 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2648 * to mc_filter_type.
2649 **/
ixgbe_mta_vector(struct ixgbe_hw * hw,u8 * mc_addr)2650 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2651 {
2652 u32 vector = 0;
2653
2654 DEBUGFUNC("ixgbe_mta_vector");
2655
2656 switch (hw->mac.mc_filter_type) {
2657 case 0: /* use bits [47:36] of the address */
2658 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2659 break;
2660 case 1: /* use bits [46:35] of the address */
2661 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2662 break;
2663 case 2: /* use bits [45:34] of the address */
2664 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2665 break;
2666 case 3: /* use bits [43:32] of the address */
2667 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2668 break;
2669 default: /* Invalid mc_filter_type */
2670 DEBUGOUT("MC filter type param set incorrectly\n");
2671 ASSERT(0);
2672 break;
2673 }
2674
2675 /* vector can only be 12-bits or boundary will be exceeded */
2676 vector &= 0xFFF;
2677 return vector;
2678 }
2679
2680 /**
2681 * ixgbe_set_mta - Set bit-vector in multicast table
2682 * @hw: pointer to hardware structure
2683 * @hash_value: Multicast address hash value
2684 *
2685 * Sets the bit-vector in the multicast table.
2686 **/
ixgbe_set_mta(struct ixgbe_hw * hw,u8 * mc_addr)2687 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2688 {
2689 u32 vector;
2690 u32 vector_bit;
2691 u32 vector_reg;
2692
2693 DEBUGFUNC("ixgbe_set_mta");
2694
2695 hw->addr_ctrl.mta_in_use++;
2696
2697 vector = ixgbe_mta_vector(hw, mc_addr);
2698 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2699
2700 /*
2701 * The MTA is a register array of 128 32-bit registers. It is treated
2702 * like an array of 4096 bits. We want to set bit
2703 * BitArray[vector_value]. So we figure out what register the bit is
2704 * in, read it, OR in the new bit, then write back the new value. The
2705 * register is determined by the upper 7 bits of the vector value and
2706 * the bit within that register are determined by the lower 5 bits of
2707 * the value.
2708 */
2709 vector_reg = (vector >> 5) & 0x7F;
2710 vector_bit = vector & 0x1F;
2711 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2712 }
2713
2714 /**
2715 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2716 * @hw: pointer to hardware structure
2717 * @mc_addr_list: the list of new multicast addresses
2718 * @mc_addr_count: number of addresses
2719 * @next: iterator function to walk the multicast address list
2720 * @clear: flag, when set clears the table beforehand
2721 *
2722 * When the clear flag is set, the given list replaces any existing list.
2723 * Hashes the given addresses into the multicast table.
2724 **/
ixgbe_update_mc_addr_list_generic(struct ixgbe_hw * hw,u8 * mc_addr_list,u32 mc_addr_count,ixgbe_mc_addr_itr next,bool clear)2725 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2726 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2727 bool clear)
2728 {
2729 u32 i;
2730 u32 vmdq;
2731
2732 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2733
2734 /*
2735 * Set the new number of MC addresses that we are being requested to
2736 * use.
2737 */
2738 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2739 hw->addr_ctrl.mta_in_use = 0;
2740
2741 /* Clear mta_shadow */
2742 if (clear) {
2743 DEBUGOUT(" Clearing MTA\n");
2744 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2745 }
2746
2747 /* Update mta_shadow */
2748 for (i = 0; i < mc_addr_count; i++) {
2749 DEBUGOUT(" Adding the multicast addresses:\n");
2750 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2751 }
2752
2753 /* Enable mta */
2754 for (i = 0; i < hw->mac.mcft_size; i++)
2755 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2756 hw->mac.mta_shadow[i]);
2757
2758 if (hw->addr_ctrl.mta_in_use > 0)
2759 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2760 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2761
2762 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2763 return IXGBE_SUCCESS;
2764 }
2765
2766 /**
2767 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2768 * @hw: pointer to hardware structure
2769 *
2770 * Enables multicast address in RAR and the use of the multicast hash table.
2771 **/
ixgbe_enable_mc_generic(struct ixgbe_hw * hw)2772 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2773 {
2774 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2775
2776 DEBUGFUNC("ixgbe_enable_mc_generic");
2777
2778 if (a->mta_in_use > 0)
2779 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2780 hw->mac.mc_filter_type);
2781
2782 return IXGBE_SUCCESS;
2783 }
2784
2785 /**
2786 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2787 * @hw: pointer to hardware structure
2788 *
2789 * Disables multicast address in RAR and the use of the multicast hash table.
2790 **/
ixgbe_disable_mc_generic(struct ixgbe_hw * hw)2791 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2792 {
2793 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2794
2795 DEBUGFUNC("ixgbe_disable_mc_generic");
2796
2797 if (a->mta_in_use > 0)
2798 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2799
2800 return IXGBE_SUCCESS;
2801 }
2802
2803 /**
2804 * ixgbe_fc_enable_generic - Enable flow control
2805 * @hw: pointer to hardware structure
2806 *
2807 * Enable flow control according to the current settings.
2808 **/
ixgbe_fc_enable_generic(struct ixgbe_hw * hw)2809 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2810 {
2811 s32 ret_val = IXGBE_SUCCESS;
2812 u32 mflcn_reg, fccfg_reg;
2813 u32 reg;
2814 u32 fcrtl, fcrth;
2815 int i;
2816
2817 DEBUGFUNC("ixgbe_fc_enable_generic");
2818
2819 /* Validate the water mark configuration */
2820 if (!hw->fc.pause_time) {
2821 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2822 goto out;
2823 }
2824
2825 /* Low water mark of zero causes XOFF floods */
2826 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2827 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2828 hw->fc.high_water[i]) {
2829 if (!hw->fc.low_water[i] ||
2830 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2831 DEBUGOUT("Invalid water mark configuration\n");
2832 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2833 goto out;
2834 }
2835 }
2836 }
2837
2838 /* Negotiate the fc mode to use */
2839 hw->mac.ops.fc_autoneg(hw);
2840
2841 /* Disable any previous flow control settings */
2842 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2843 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2844
2845 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2846 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2847
2848 /*
2849 * The possible values of fc.current_mode are:
2850 * 0: Flow control is completely disabled
2851 * 1: Rx flow control is enabled (we can receive pause frames,
2852 * but not send pause frames).
2853 * 2: Tx flow control is enabled (we can send pause frames but
2854 * we do not support receiving pause frames).
2855 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2856 * other: Invalid.
2857 */
2858 switch (hw->fc.current_mode) {
2859 case ixgbe_fc_none:
2860 /*
2861 * Flow control is disabled by software override or autoneg.
2862 * The code below will actually disable it in the HW.
2863 */
2864 break;
2865 case ixgbe_fc_rx_pause:
2866 /*
2867 * Rx Flow control is enabled and Tx Flow control is
2868 * disabled by software override. Since there really
2869 * isn't a way to advertise that we are capable of RX
2870 * Pause ONLY, we will advertise that we support both
2871 * symmetric and asymmetric Rx PAUSE. Later, we will
2872 * disable the adapter's ability to send PAUSE frames.
2873 */
2874 mflcn_reg |= IXGBE_MFLCN_RFCE;
2875 break;
2876 case ixgbe_fc_tx_pause:
2877 /*
2878 * Tx Flow control is enabled, and Rx Flow control is
2879 * disabled by software override.
2880 */
2881 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2882 break;
2883 case ixgbe_fc_full:
2884 /* Flow control (both Rx and Tx) is enabled by SW override. */
2885 mflcn_reg |= IXGBE_MFLCN_RFCE;
2886 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2887 break;
2888 default:
2889 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2890 "Flow control param set incorrectly\n");
2891 ret_val = IXGBE_ERR_CONFIG;
2892 goto out;
2893 break;
2894 }
2895
2896 /* Set 802.3x based flow control settings. */
2897 mflcn_reg |= IXGBE_MFLCN_DPF;
2898 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2899 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2900
2901
2902 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2903 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2904 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2905 hw->fc.high_water[i]) {
2906 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2907 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2908 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2909 } else {
2910 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2911 /*
2912 * In order to prevent Tx hangs when the internal Tx
2913 * switch is enabled we must set the high water mark
2914 * to the Rx packet buffer size - 24KB. This allows
2915 * the Tx switch to function even under heavy Rx
2916 * workloads.
2917 */
2918 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2919 }
2920
2921 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2922 }
2923
2924 /* Configure pause time (2 TCs per register) */
2925 reg = hw->fc.pause_time * 0x00010001;
2926 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2927 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2928
2929 /* Configure flow control refresh threshold value */
2930 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2931
2932 out:
2933 return ret_val;
2934 }
2935
2936 /**
2937 * ixgbe_negotiate_fc - Negotiate flow control
2938 * @hw: pointer to hardware structure
2939 * @adv_reg: flow control advertised settings
2940 * @lp_reg: link partner's flow control settings
2941 * @adv_sym: symmetric pause bit in advertisement
2942 * @adv_asm: asymmetric pause bit in advertisement
2943 * @lp_sym: symmetric pause bit in link partner advertisement
2944 * @lp_asm: asymmetric pause bit in link partner advertisement
2945 *
2946 * Find the intersection between advertised settings and link partner's
2947 * advertised settings
2948 **/
ixgbe_negotiate_fc(struct ixgbe_hw * hw,u32 adv_reg,u32 lp_reg,u32 adv_sym,u32 adv_asm,u32 lp_sym,u32 lp_asm)2949 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2950 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2951 {
2952 if ((!(adv_reg)) || (!(lp_reg))) {
2953 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2954 "Local or link partner's advertised flow control "
2955 "settings are NULL. Local: %x, link partner: %x\n",
2956 adv_reg, lp_reg);
2957 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2958 }
2959
2960 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2961 /*
2962 * Now we need to check if the user selected Rx ONLY
2963 * of pause frames. In this case, we had to advertise
2964 * FULL flow control because we could not advertise RX
2965 * ONLY. Hence, we must now check to see if we need to
2966 * turn OFF the TRANSMISSION of PAUSE frames.
2967 */
2968 if (hw->fc.requested_mode == ixgbe_fc_full) {
2969 hw->fc.current_mode = ixgbe_fc_full;
2970 DEBUGOUT("Flow Control = FULL.\n");
2971 } else {
2972 hw->fc.current_mode = ixgbe_fc_rx_pause;
2973 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2974 }
2975 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2976 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2977 hw->fc.current_mode = ixgbe_fc_tx_pause;
2978 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2979 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2980 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2981 hw->fc.current_mode = ixgbe_fc_rx_pause;
2982 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2983 } else {
2984 hw->fc.current_mode = ixgbe_fc_none;
2985 DEBUGOUT("Flow Control = NONE.\n");
2986 }
2987 return IXGBE_SUCCESS;
2988 }
2989
2990 /**
2991 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2992 * @hw: pointer to hardware structure
2993 *
2994 * Enable flow control according on 1 gig fiber.
2995 **/
ixgbe_fc_autoneg_fiber(struct ixgbe_hw * hw)2996 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2997 {
2998 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2999 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3000
3001 /*
3002 * On multispeed fiber at 1g, bail out if
3003 * - link is up but AN did not complete, or if
3004 * - link is up and AN completed but timed out
3005 */
3006
3007 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
3008 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
3009 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
3010 DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
3011 goto out;
3012 }
3013
3014 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
3015 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
3016
3017 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
3018 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
3019 IXGBE_PCS1GANA_ASM_PAUSE,
3020 IXGBE_PCS1GANA_SYM_PAUSE,
3021 IXGBE_PCS1GANA_ASM_PAUSE);
3022
3023 out:
3024 return ret_val;
3025 }
3026
3027 /**
3028 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
3029 * @hw: pointer to hardware structure
3030 *
3031 * Enable flow control according to IEEE clause 37.
3032 **/
ixgbe_fc_autoneg_backplane(struct ixgbe_hw * hw)3033 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
3034 {
3035 u32 links2, anlp1_reg, autoc_reg, links;
3036 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3037
3038 /*
3039 * On backplane, bail out if
3040 * - backplane autoneg was not completed, or if
3041 * - we are 82599 and link partner is not AN enabled
3042 */
3043 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
3044 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
3045 DEBUGOUT("Auto-Negotiation did not complete\n");
3046 goto out;
3047 }
3048
3049 if (hw->mac.type == ixgbe_mac_82599EB) {
3050 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
3051 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
3052 DEBUGOUT("Link partner is not AN enabled\n");
3053 goto out;
3054 }
3055 }
3056 /*
3057 * Read the 10g AN autoc and LP ability registers and resolve
3058 * local flow control settings accordingly
3059 */
3060 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3061 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
3062
3063 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
3064 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
3065 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
3066
3067 out:
3068 return ret_val;
3069 }
3070
3071 /**
3072 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
3073 * @hw: pointer to hardware structure
3074 *
3075 * Enable flow control according to IEEE clause 37.
3076 **/
ixgbe_fc_autoneg_copper(struct ixgbe_hw * hw)3077 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
3078 {
3079 u16 technology_ability_reg = 0;
3080 u16 lp_technology_ability_reg = 0;
3081
3082 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
3083 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3084 &technology_ability_reg);
3085 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
3086 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3087 &lp_technology_ability_reg);
3088
3089 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
3090 (u32)lp_technology_ability_reg,
3091 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
3092 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
3093 }
3094
3095 /**
3096 * ixgbe_fc_autoneg - Configure flow control
3097 * @hw: pointer to hardware structure
3098 *
3099 * Compares our advertised flow control capabilities to those advertised by
3100 * our link partner, and determines the proper flow control mode to use.
3101 **/
ixgbe_fc_autoneg(struct ixgbe_hw * hw)3102 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
3103 {
3104 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3105 ixgbe_link_speed speed;
3106 bool link_up;
3107
3108 DEBUGFUNC("ixgbe_fc_autoneg");
3109
3110 /*
3111 * AN should have completed when the cable was plugged in.
3112 * Look for reasons to bail out. Bail out if:
3113 * - FC autoneg is disabled, or if
3114 * - link is not up.
3115 */
3116 if (hw->fc.disable_fc_autoneg) {
3117 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3118 "Flow control autoneg is disabled");
3119 goto out;
3120 }
3121
3122 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
3123 if (!link_up) {
3124 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3125 goto out;
3126 }
3127
3128 switch (hw->phy.media_type) {
3129 /* Autoneg flow control on fiber adapters */
3130 case ixgbe_media_type_fiber_fixed:
3131 case ixgbe_media_type_fiber_qsfp:
3132 case ixgbe_media_type_fiber:
3133 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3134 ret_val = ixgbe_fc_autoneg_fiber(hw);
3135 break;
3136
3137 /* Autoneg flow control on backplane adapters */
3138 case ixgbe_media_type_backplane:
3139 ret_val = ixgbe_fc_autoneg_backplane(hw);
3140 break;
3141
3142 /* Autoneg flow control on copper adapters */
3143 case ixgbe_media_type_copper:
3144 if (ixgbe_device_supports_autoneg_fc(hw))
3145 ret_val = ixgbe_fc_autoneg_copper(hw);
3146 break;
3147
3148 default:
3149 break;
3150 }
3151
3152 out:
3153 if (ret_val == IXGBE_SUCCESS) {
3154 hw->fc.fc_was_autonegged = TRUE;
3155 } else {
3156 hw->fc.fc_was_autonegged = FALSE;
3157 hw->fc.current_mode = hw->fc.requested_mode;
3158 }
3159 }
3160
3161 /*
3162 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3163 * @hw: pointer to hardware structure
3164 *
3165 * System-wide timeout range is encoded in PCIe Device Control2 register.
3166 *
3167 * Add 10% to specified maximum and return the number of times to poll for
3168 * completion timeout, in units of 100 microsec. Never return less than
3169 * 800 = 80 millisec.
3170 */
ixgbe_pcie_timeout_poll(struct ixgbe_hw * hw)3171 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3172 {
3173 s16 devctl2;
3174 u32 pollcnt;
3175
3176 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3177 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3178
3179 switch (devctl2) {
3180 case IXGBE_PCIDEVCTRL2_65_130ms:
3181 pollcnt = 1300; /* 130 millisec */
3182 break;
3183 case IXGBE_PCIDEVCTRL2_260_520ms:
3184 pollcnt = 5200; /* 520 millisec */
3185 break;
3186 case IXGBE_PCIDEVCTRL2_1_2s:
3187 pollcnt = 20000; /* 2 sec */
3188 break;
3189 case IXGBE_PCIDEVCTRL2_4_8s:
3190 pollcnt = 80000; /* 8 sec */
3191 break;
3192 case IXGBE_PCIDEVCTRL2_17_34s:
3193 pollcnt = 34000; /* 34 sec */
3194 break;
3195 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3196 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3197 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3198 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3199 default:
3200 pollcnt = 800; /* 80 millisec minimum */
3201 break;
3202 }
3203
3204 /* add 10% to spec maximum */
3205 return (pollcnt * 11) / 10;
3206 }
3207
3208 /**
3209 * ixgbe_disable_pcie_master - Disable PCI-express master access
3210 * @hw: pointer to hardware structure
3211 *
3212 * Disables PCI-Express master access and verifies there are no pending
3213 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3214 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3215 * is returned signifying master requests disabled.
3216 **/
ixgbe_disable_pcie_master(struct ixgbe_hw * hw)3217 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3218 {
3219 s32 status = IXGBE_SUCCESS;
3220 u32 i, poll;
3221 u16 value;
3222
3223 DEBUGFUNC("ixgbe_disable_pcie_master");
3224
3225 /* Always set this bit to ensure any future transactions are blocked */
3226 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3227
3228 /* Exit if master requests are blocked */
3229 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3230 IXGBE_REMOVED(hw->hw_addr))
3231 goto out;
3232
3233 /* Poll for master request bit to clear */
3234 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3235 usec_delay(100);
3236 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3237 goto out;
3238 }
3239
3240 /*
3241 * Two consecutive resets are required via CTRL.RST per datasheet
3242 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3243 * of this need. The first reset prevents new master requests from
3244 * being issued by our device. We then must wait 1usec or more for any
3245 * remaining completions from the PCIe bus to trickle in, and then reset
3246 * again to clear out any effects they may have had on our device.
3247 */
3248 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3249 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3250
3251 if (hw->mac.type >= ixgbe_mac_X550)
3252 goto out;
3253
3254 /*
3255 * Before proceeding, make sure that the PCIe block does not have
3256 * transactions pending.
3257 */
3258 poll = ixgbe_pcie_timeout_poll(hw);
3259 for (i = 0; i < poll; i++) {
3260 usec_delay(100);
3261 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3262 if (IXGBE_REMOVED(hw->hw_addr))
3263 goto out;
3264 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3265 goto out;
3266 }
3267
3268 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3269 "PCIe transaction pending bit also did not clear.\n");
3270 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3271
3272 out:
3273 return status;
3274 }
3275
3276 /**
3277 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3278 * @hw: pointer to hardware structure
3279 * @mask: Mask to specify which semaphore to acquire
3280 *
3281 * Acquires the SWFW semaphore through the GSSR register for the specified
3282 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3283 **/
ixgbe_acquire_swfw_sync(struct ixgbe_hw * hw,u32 mask)3284 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3285 {
3286 u32 gssr = 0;
3287 u32 swmask = mask;
3288 u32 fwmask = mask << 5;
3289 u32 timeout = 200;
3290 u32 i;
3291
3292 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3293
3294 for (i = 0; i < timeout; i++) {
3295 /*
3296 * SW NVM semaphore bit is used for access to all
3297 * SW_FW_SYNC bits (not just NVM)
3298 */
3299 if (ixgbe_get_eeprom_semaphore(hw))
3300 return IXGBE_ERR_SWFW_SYNC;
3301
3302 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3303 if (!(gssr & (fwmask | swmask))) {
3304 gssr |= swmask;
3305 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3306 ixgbe_release_eeprom_semaphore(hw);
3307 return IXGBE_SUCCESS;
3308 } else {
3309 /* Resource is currently in use by FW or SW */
3310 ixgbe_release_eeprom_semaphore(hw);
3311 msec_delay(5);
3312 }
3313 }
3314
3315 /* If time expired clear the bits holding the lock and retry */
3316 if (gssr & (fwmask | swmask))
3317 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3318
3319 msec_delay(5);
3320 return IXGBE_ERR_SWFW_SYNC;
3321 }
3322
3323 /**
3324 * ixgbe_release_swfw_sync - Release SWFW semaphore
3325 * @hw: pointer to hardware structure
3326 * @mask: Mask to specify which semaphore to release
3327 *
3328 * Releases the SWFW semaphore through the GSSR register for the specified
3329 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3330 **/
ixgbe_release_swfw_sync(struct ixgbe_hw * hw,u32 mask)3331 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3332 {
3333 u32 gssr;
3334 u32 swmask = mask;
3335
3336 DEBUGFUNC("ixgbe_release_swfw_sync");
3337
3338 ixgbe_get_eeprom_semaphore(hw);
3339
3340 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3341 gssr &= ~swmask;
3342 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3343
3344 ixgbe_release_eeprom_semaphore(hw);
3345 }
3346
3347 /**
3348 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3349 * @hw: pointer to hardware structure
3350 *
3351 * Stops the receive data path and waits for the HW to internally empty
3352 * the Rx security block
3353 **/
ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw * hw)3354 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3355 {
3356 #define IXGBE_MAX_SECRX_POLL 40
3357
3358 int i;
3359 int secrxreg;
3360
3361 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3362
3363
3364 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3365 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3366 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3367 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3368 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3369 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3370 break;
3371 else
3372 /* Use interrupt-safe sleep just in case */
3373 usec_delay(1000);
3374 }
3375
3376 /* For informational purposes only */
3377 if (i >= IXGBE_MAX_SECRX_POLL)
3378 DEBUGOUT("Rx unit being enabled before security "
3379 "path fully disabled. Continuing with init.\n");
3380
3381 return IXGBE_SUCCESS;
3382 }
3383
3384 /**
3385 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3386 * @hw: pointer to hardware structure
3387 * @reg_val: Value we read from AUTOC
3388 *
3389 * The default case requires no protection so just to the register read.
3390 */
prot_autoc_read_generic(struct ixgbe_hw * hw,bool * locked,u32 * reg_val)3391 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3392 {
3393 *locked = FALSE;
3394 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3395 return IXGBE_SUCCESS;
3396 }
3397
3398 /**
3399 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3400 * @hw: pointer to hardware structure
3401 * @reg_val: value to write to AUTOC
3402 * @locked: bool to indicate whether the SW/FW lock was already taken by
3403 * previous read.
3404 *
3405 * The default case requires no protection so just to the register write.
3406 */
prot_autoc_write_generic(struct ixgbe_hw * hw,u32 reg_val,bool locked)3407 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3408 {
3409 UNREFERENCED_1PARAMETER(locked);
3410
3411 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3412 return IXGBE_SUCCESS;
3413 }
3414
3415 /**
3416 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3417 * @hw: pointer to hardware structure
3418 *
3419 * Enables the receive data path.
3420 **/
ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw * hw)3421 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3422 {
3423 u32 secrxreg;
3424
3425 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3426
3427 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3428 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3429 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3430 IXGBE_WRITE_FLUSH(hw);
3431
3432 return IXGBE_SUCCESS;
3433 }
3434
3435 /**
3436 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3437 * @hw: pointer to hardware structure
3438 * @regval: register value to write to RXCTRL
3439 *
3440 * Enables the Rx DMA unit
3441 **/
ixgbe_enable_rx_dma_generic(struct ixgbe_hw * hw,u32 regval)3442 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3443 {
3444 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3445
3446 if (regval & IXGBE_RXCTRL_RXEN)
3447 ixgbe_enable_rx(hw);
3448 else
3449 ixgbe_disable_rx(hw);
3450
3451 return IXGBE_SUCCESS;
3452 }
3453
3454 /**
3455 * ixgbe_blink_led_start_generic - Blink LED based on index.
3456 * @hw: pointer to hardware structure
3457 * @index: led number to blink
3458 **/
ixgbe_blink_led_start_generic(struct ixgbe_hw * hw,u32 index)3459 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3460 {
3461 ixgbe_link_speed speed = 0;
3462 bool link_up = 0;
3463 u32 autoc_reg = 0;
3464 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3465 s32 ret_val = IXGBE_SUCCESS;
3466 bool locked = FALSE;
3467
3468 DEBUGFUNC("ixgbe_blink_led_start_generic");
3469
3470 if (index > 3)
3471 return IXGBE_ERR_PARAM;
3472
3473 /*
3474 * Link must be up to auto-blink the LEDs;
3475 * Force it if link is down.
3476 */
3477 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
3478
3479 if (!link_up) {
3480 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3481 if (ret_val != IXGBE_SUCCESS)
3482 goto out;
3483
3484 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3485 autoc_reg |= IXGBE_AUTOC_FLU;
3486
3487 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3488 if (ret_val != IXGBE_SUCCESS)
3489 goto out;
3490
3491 IXGBE_WRITE_FLUSH(hw);
3492 msec_delay(10);
3493 }
3494
3495 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3496 led_reg |= IXGBE_LED_BLINK(index);
3497 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3498 IXGBE_WRITE_FLUSH(hw);
3499
3500 out:
3501 return ret_val;
3502 }
3503
3504 /**
3505 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3506 * @hw: pointer to hardware structure
3507 * @index: led number to stop blinking
3508 **/
ixgbe_blink_led_stop_generic(struct ixgbe_hw * hw,u32 index)3509 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3510 {
3511 u32 autoc_reg = 0;
3512 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3513 s32 ret_val = IXGBE_SUCCESS;
3514 bool locked = FALSE;
3515
3516 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3517
3518 if (index > 3)
3519 return IXGBE_ERR_PARAM;
3520
3521
3522 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3523 if (ret_val != IXGBE_SUCCESS)
3524 goto out;
3525
3526 autoc_reg &= ~IXGBE_AUTOC_FLU;
3527 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3528
3529 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3530 if (ret_val != IXGBE_SUCCESS)
3531 goto out;
3532
3533 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3534 led_reg &= ~IXGBE_LED_BLINK(index);
3535 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3536 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3537 IXGBE_WRITE_FLUSH(hw);
3538
3539 out:
3540 return ret_val;
3541 }
3542
3543 /**
3544 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3545 * @hw: pointer to hardware structure
3546 * @san_mac_offset: SAN MAC address offset
3547 *
3548 * This function will read the EEPROM location for the SAN MAC address
3549 * pointer, and returns the value at that location. This is used in both
3550 * get and set mac_addr routines.
3551 **/
ixgbe_get_san_mac_addr_offset(struct ixgbe_hw * hw,u16 * san_mac_offset)3552 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3553 u16 *san_mac_offset)
3554 {
3555 s32 ret_val;
3556
3557 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3558
3559 /*
3560 * First read the EEPROM pointer to see if the MAC addresses are
3561 * available.
3562 */
3563 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3564 san_mac_offset);
3565 if (ret_val) {
3566 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3567 "eeprom at offset %d failed",
3568 IXGBE_SAN_MAC_ADDR_PTR);
3569 }
3570
3571 return ret_val;
3572 }
3573
3574 /**
3575 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3576 * @hw: pointer to hardware structure
3577 * @san_mac_addr: SAN MAC address
3578 *
3579 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3580 * per-port, so set_lan_id() must be called before reading the addresses.
3581 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3582 * upon for non-SFP connections, so we must call it here.
3583 **/
ixgbe_get_san_mac_addr_generic(struct ixgbe_hw * hw,u8 * san_mac_addr)3584 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3585 {
3586 u16 san_mac_data, san_mac_offset;
3587 u8 i;
3588 s32 ret_val;
3589
3590 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3591
3592 /*
3593 * First read the EEPROM pointer to see if the MAC addresses are
3594 * available. If they're not, no point in calling set_lan_id() here.
3595 */
3596 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3597 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3598 goto san_mac_addr_out;
3599
3600 /* make sure we know which port we need to program */
3601 hw->mac.ops.set_lan_id(hw);
3602 /* apply the port offset to the address offset */
3603 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3604 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3605 for (i = 0; i < 3; i++) {
3606 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3607 &san_mac_data);
3608 if (ret_val) {
3609 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3610 "eeprom read at offset %d failed",
3611 san_mac_offset);
3612 goto san_mac_addr_out;
3613 }
3614 san_mac_addr[i * 2] = (u8)(san_mac_data);
3615 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3616 san_mac_offset++;
3617 }
3618 return IXGBE_SUCCESS;
3619
3620 san_mac_addr_out:
3621 /*
3622 * No addresses available in this EEPROM. It's not an
3623 * error though, so just wipe the local address and return.
3624 */
3625 for (i = 0; i < 6; i++)
3626 san_mac_addr[i] = 0xFF;
3627 return IXGBE_SUCCESS;
3628 }
3629
3630 /**
3631 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3632 * @hw: pointer to hardware structure
3633 * @san_mac_addr: SAN MAC address
3634 *
3635 * Write a SAN MAC address to the EEPROM.
3636 **/
ixgbe_set_san_mac_addr_generic(struct ixgbe_hw * hw,u8 * san_mac_addr)3637 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3638 {
3639 s32 ret_val;
3640 u16 san_mac_data, san_mac_offset;
3641 u8 i;
3642
3643 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3644
3645 /* Look for SAN mac address pointer. If not defined, return */
3646 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3647 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3648 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3649
3650 /* Make sure we know which port we need to write */
3651 hw->mac.ops.set_lan_id(hw);
3652 /* Apply the port offset to the address offset */
3653 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3654 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3655
3656 for (i = 0; i < 3; i++) {
3657 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3658 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3659 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3660 san_mac_offset++;
3661 }
3662
3663 return IXGBE_SUCCESS;
3664 }
3665
3666 /**
3667 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3668 * @hw: pointer to hardware structure
3669 *
3670 * Read PCIe configuration space, and get the MSI-X vector count from
3671 * the capabilities table.
3672 **/
ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw * hw)3673 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3674 {
3675 u16 msix_count = 1;
3676 u16 max_msix_count;
3677 u16 pcie_offset;
3678
3679 switch (hw->mac.type) {
3680 case ixgbe_mac_82598EB:
3681 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3682 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3683 break;
3684 case ixgbe_mac_82599EB:
3685 case ixgbe_mac_X540:
3686 case ixgbe_mac_X550:
3687 case ixgbe_mac_X550EM_x:
3688 case ixgbe_mac_X550EM_a:
3689 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3690 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3691 break;
3692 default:
3693 return msix_count;
3694 }
3695
3696 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3697 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3698 if (IXGBE_REMOVED(hw->hw_addr))
3699 msix_count = 0;
3700 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3701
3702 /* MSI-X count is zero-based in HW */
3703 msix_count++;
3704
3705 if (msix_count > max_msix_count)
3706 msix_count = max_msix_count;
3707
3708 return msix_count;
3709 }
3710
3711 /**
3712 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3713 * @hw: pointer to hardware structure
3714 * @addr: Address to put into receive address register
3715 * @vmdq: VMDq pool to assign
3716 *
3717 * Puts an ethernet address into a receive address register, or
3718 * finds the rar that it is aleady in; adds to the pool list
3719 **/
ixgbe_insert_mac_addr_generic(struct ixgbe_hw * hw,u8 * addr,u32 vmdq)3720 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3721 {
3722 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3723 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3724 u32 rar;
3725 u32 rar_low, rar_high;
3726 u32 addr_low, addr_high;
3727
3728 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3729
3730 /* swap bytes for HW little endian */
3731 addr_low = addr[0] | (addr[1] << 8)
3732 | (addr[2] << 16)
3733 | (addr[3] << 24);
3734 addr_high = addr[4] | (addr[5] << 8);
3735
3736 /*
3737 * Either find the mac_id in rar or find the first empty space.
3738 * rar_highwater points to just after the highest currently used
3739 * rar in order to shorten the search. It grows when we add a new
3740 * rar to the top.
3741 */
3742 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3743 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3744
3745 if (((IXGBE_RAH_AV & rar_high) == 0)
3746 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3747 first_empty_rar = rar;
3748 } else if ((rar_high & 0xFFFF) == addr_high) {
3749 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3750 if (rar_low == addr_low)
3751 break; /* found it already in the rars */
3752 }
3753 }
3754
3755 if (rar < hw->mac.rar_highwater) {
3756 /* already there so just add to the pool bits */
3757 ixgbe_set_vmdq(hw, rar, vmdq);
3758 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3759 /* stick it into first empty RAR slot we found */
3760 rar = first_empty_rar;
3761 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3762 } else if (rar == hw->mac.rar_highwater) {
3763 /* add it to the top of the list and inc the highwater mark */
3764 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3765 hw->mac.rar_highwater++;
3766 } else if (rar >= hw->mac.num_rar_entries) {
3767 return IXGBE_ERR_INVALID_MAC_ADDR;
3768 }
3769
3770 /*
3771 * If we found rar[0], make sure the default pool bit (we use pool 0)
3772 * remains cleared to be sure default pool packets will get delivered
3773 */
3774 if (rar == 0)
3775 ixgbe_clear_vmdq(hw, rar, 0);
3776
3777 return rar;
3778 }
3779
3780 /**
3781 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3782 * @hw: pointer to hardware struct
3783 * @rar: receive address register index to disassociate
3784 * @vmdq: VMDq pool index to remove from the rar
3785 **/
ixgbe_clear_vmdq_generic(struct ixgbe_hw * hw,u32 rar,u32 vmdq)3786 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3787 {
3788 u32 mpsar_lo, mpsar_hi;
3789 u32 rar_entries = hw->mac.num_rar_entries;
3790
3791 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3792
3793 /* Make sure we are using a valid rar index range */
3794 if (rar >= rar_entries) {
3795 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3796 "RAR index %d is out of range.\n", rar);
3797 return IXGBE_ERR_INVALID_ARGUMENT;
3798 }
3799
3800 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3801 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3802
3803 if (IXGBE_REMOVED(hw->hw_addr))
3804 goto done;
3805
3806 if (!mpsar_lo && !mpsar_hi)
3807 goto done;
3808
3809 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3810 if (mpsar_lo) {
3811 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3812 mpsar_lo = 0;
3813 }
3814 if (mpsar_hi) {
3815 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3816 mpsar_hi = 0;
3817 }
3818 } else if (vmdq < 32) {
3819 mpsar_lo &= ~(1 << vmdq);
3820 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3821 } else {
3822 mpsar_hi &= ~(1 << (vmdq - 32));
3823 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3824 }
3825
3826 /* was that the last pool using this rar? */
3827 if (mpsar_lo == 0 && mpsar_hi == 0 &&
3828 rar != 0 && rar != hw->mac.san_mac_rar_index)
3829 hw->mac.ops.clear_rar(hw, rar);
3830 done:
3831 return IXGBE_SUCCESS;
3832 }
3833
3834 /**
3835 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3836 * @hw: pointer to hardware struct
3837 * @rar: receive address register index to associate with a VMDq index
3838 * @vmdq: VMDq pool index
3839 **/
ixgbe_set_vmdq_generic(struct ixgbe_hw * hw,u32 rar,u32 vmdq)3840 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3841 {
3842 u32 mpsar;
3843 u32 rar_entries = hw->mac.num_rar_entries;
3844
3845 DEBUGFUNC("ixgbe_set_vmdq_generic");
3846
3847 /* Make sure we are using a valid rar index range */
3848 if (rar >= rar_entries) {
3849 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3850 "RAR index %d is out of range.\n", rar);
3851 return IXGBE_ERR_INVALID_ARGUMENT;
3852 }
3853
3854 if (vmdq < 32) {
3855 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3856 mpsar |= 1 << vmdq;
3857 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3858 } else {
3859 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3860 mpsar |= 1 << (vmdq - 32);
3861 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3862 }
3863 return IXGBE_SUCCESS;
3864 }
3865
3866 /**
3867 * This function should only be involved in the IOV mode.
3868 * In IOV mode, Default pool is next pool after the number of
3869 * VFs advertized and not 0.
3870 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3871 *
3872 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3873 * @hw: pointer to hardware struct
3874 * @vmdq: VMDq pool index
3875 **/
ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw * hw,u32 vmdq)3876 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3877 {
3878 u32 rar = hw->mac.san_mac_rar_index;
3879
3880 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3881
3882 if (vmdq < 32) {
3883 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3884 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3885 } else {
3886 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3887 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3888 }
3889
3890 return IXGBE_SUCCESS;
3891 }
3892
3893 /**
3894 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3895 * @hw: pointer to hardware structure
3896 **/
ixgbe_init_uta_tables_generic(struct ixgbe_hw * hw)3897 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3898 {
3899 int i;
3900
3901 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3902 DEBUGOUT(" Clearing UTA\n");
3903
3904 for (i = 0; i < 128; i++)
3905 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3906
3907 return IXGBE_SUCCESS;
3908 }
3909
3910 /**
3911 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3912 * @hw: pointer to hardware structure
3913 * @vlan: VLAN id to write to VLAN filter
3914 *
3915 * return the VLVF index where this VLAN id should be placed
3916 *
3917 **/
ixgbe_find_vlvf_slot(struct ixgbe_hw * hw,u32 vlan,bool vlvf_bypass)3918 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
3919 {
3920 s32 regindex, first_empty_slot;
3921 u32 bits;
3922
3923 /* short cut the special case */
3924 if (vlan == 0)
3925 return 0;
3926
3927 /* if vlvf_bypass is set we don't want to use an empty slot, we
3928 * will simply bypass the VLVF if there are no entries present in the
3929 * VLVF that contain our VLAN
3930 */
3931 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0;
3932
3933 /* add VLAN enable bit for comparison */
3934 vlan |= IXGBE_VLVF_VIEN;
3935
3936 /* Search for the vlan id in the VLVF entries. Save off the first empty
3937 * slot found along the way.
3938 *
3939 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
3940 */
3941 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) {
3942 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3943 if (bits == vlan)
3944 return regindex;
3945 if (!first_empty_slot && !bits)
3946 first_empty_slot = regindex;
3947 }
3948
3949 /* If we are here then we didn't find the VLAN. Return first empty
3950 * slot we found during our search, else error.
3951 */
3952 if (!first_empty_slot)
3953 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n");
3954
3955 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE;
3956 }
3957
3958 /**
3959 * ixgbe_set_vfta_generic - Set VLAN filter table
3960 * @hw: pointer to hardware structure
3961 * @vlan: VLAN id to write to VLAN filter
3962 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
3963 * @vlan_on: boolean flag to turn on/off VLAN
3964 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3965 *
3966 * Turn on/off specified VLAN in the VLAN filter table.
3967 **/
ixgbe_set_vfta_generic(struct ixgbe_hw * hw,u32 vlan,u32 vind,bool vlan_on,bool vlvf_bypass)3968 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3969 bool vlan_on, bool vlvf_bypass)
3970 {
3971 u32 regidx, vfta_delta, vfta;
3972 s32 ret_val;
3973
3974 DEBUGFUNC("ixgbe_set_vfta_generic");
3975
3976 if (vlan > 4095 || vind > 63)
3977 return IXGBE_ERR_PARAM;
3978
3979 /*
3980 * this is a 2 part operation - first the VFTA, then the
3981 * VLVF and VLVFB if VT Mode is set
3982 * We don't write the VFTA until we know the VLVF part succeeded.
3983 */
3984
3985 /* Part 1
3986 * The VFTA is a bitstring made up of 128 32-bit registers
3987 * that enable the particular VLAN id, much like the MTA:
3988 * bits[11-5]: which register
3989 * bits[4-0]: which bit in the register
3990 */
3991 regidx = vlan / 32;
3992 vfta_delta = 1 << (vlan % 32);
3993 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
3994
3995 /*
3996 * vfta_delta represents the difference between the current value
3997 * of vfta and the value we want in the register. Since the diff
3998 * is an XOR mask we can just update the vfta using an XOR
3999 */
4000 vfta_delta &= vlan_on ? ~vfta : vfta;
4001 vfta ^= vfta_delta;
4002
4003 /* Part 2
4004 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
4005 */
4006 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta,
4007 vfta, vlvf_bypass);
4008 if (ret_val != IXGBE_SUCCESS) {
4009 if (vlvf_bypass)
4010 goto vfta_update;
4011 return ret_val;
4012 }
4013
4014 vfta_update:
4015 /* Update VFTA now that we are ready for traffic */
4016 if (vfta_delta)
4017 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
4018
4019 return IXGBE_SUCCESS;
4020 }
4021
4022 /**
4023 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
4024 * @hw: pointer to hardware structure
4025 * @vlan: VLAN id to write to VLAN filter
4026 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
4027 * @vlan_on: boolean flag to turn on/off VLAN in VLVF
4028 * @vfta_delta: pointer to the difference between the current value of VFTA
4029 * and the desired value
4030 * @vfta: the desired value of the VFTA
4031 * @vlvf_bypass: boolean flag indicating updating default pool is okay
4032 *
4033 * Turn on/off specified bit in VLVF table.
4034 **/
ixgbe_set_vlvf_generic(struct ixgbe_hw * hw,u32 vlan,u32 vind,bool vlan_on,u32 * vfta_delta,u32 vfta,bool vlvf_bypass)4035 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
4036 bool vlan_on, u32 *vfta_delta, u32 vfta,
4037 bool vlvf_bypass)
4038 {
4039 u32 bits;
4040 s32 vlvf_index;
4041
4042 DEBUGFUNC("ixgbe_set_vlvf_generic");
4043
4044 if (vlan > 4095 || vind > 63)
4045 return IXGBE_ERR_PARAM;
4046
4047 /* If VT Mode is set
4048 * Either vlan_on
4049 * make sure the vlan is in VLVF
4050 * set the vind bit in the matching VLVFB
4051 * Or !vlan_on
4052 * clear the pool bit and possibly the vind
4053 */
4054 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE))
4055 return IXGBE_SUCCESS;
4056
4057 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
4058 if (vlvf_index < 0)
4059 return vlvf_index;
4060
4061 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
4062
4063 /* set the pool bit */
4064 bits |= 1 << (vind % 32);
4065 if (vlan_on)
4066 goto vlvf_update;
4067
4068 /* clear the pool bit */
4069 bits ^= 1 << (vind % 32);
4070
4071 if (!bits &&
4072 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
4073 /* Clear VFTA first, then disable VLVF. Otherwise
4074 * we run the risk of stray packets leaking into
4075 * the PF via the default pool
4076 */
4077 if (*vfta_delta)
4078 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta);
4079
4080 /* disable VLVF and clear remaining bit from pool */
4081 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4082 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0);
4083
4084 return IXGBE_SUCCESS;
4085 }
4086
4087 /* If there are still bits set in the VLVFB registers
4088 * for the VLAN ID indicated we need to see if the
4089 * caller is requesting that we clear the VFTA entry bit.
4090 * If the caller has requested that we clear the VFTA
4091 * entry bit but there are still pools/VFs using this VLAN
4092 * ID entry then ignore the request. We're not worried
4093 * about the case where we're turning the VFTA VLAN ID
4094 * entry bit on, only when requested to turn it off as
4095 * there may be multiple pools and/or VFs using the
4096 * VLAN ID entry. In that case we cannot clear the
4097 * VFTA bit until all pools/VFs using that VLAN ID have also
4098 * been cleared. This will be indicated by "bits" being
4099 * zero.
4100 */
4101 *vfta_delta = 0;
4102
4103 vlvf_update:
4104 /* record pool change and enable VLAN ID if not already enabled */
4105 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);
4106 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan);
4107
4108 return IXGBE_SUCCESS;
4109 }
4110
4111 /**
4112 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4113 * @hw: pointer to hardware structure
4114 *
4115 * Clears the VLAN filer table, and the VMDq index associated with the filter
4116 **/
ixgbe_clear_vfta_generic(struct ixgbe_hw * hw)4117 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4118 {
4119 u32 offset;
4120
4121 DEBUGFUNC("ixgbe_clear_vfta_generic");
4122
4123 for (offset = 0; offset < hw->mac.vft_size; offset++)
4124 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4125
4126 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4127 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4128 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4129 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0);
4130 }
4131
4132 return IXGBE_SUCCESS;
4133 }
4134
4135 /**
4136 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
4137 * @hw: pointer to hardware structure
4138 *
4139 * Contains the logic to identify if we need to verify link for the
4140 * crosstalk fix
4141 **/
ixgbe_need_crosstalk_fix(struct ixgbe_hw * hw)4142 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
4143 {
4144
4145 /* Does FW say we need the fix */
4146 if (!hw->need_crosstalk_fix)
4147 return FALSE;
4148
4149 /* Only consider SFP+ PHYs i.e. media type fiber */
4150 switch (hw->mac.ops.get_media_type(hw)) {
4151 case ixgbe_media_type_fiber:
4152 case ixgbe_media_type_fiber_qsfp:
4153 break;
4154 default:
4155 return FALSE;
4156 }
4157
4158 return TRUE;
4159 }
4160
4161 /**
4162 * ixgbe_check_mac_link_generic - Determine link and speed status
4163 * @hw: pointer to hardware structure
4164 * @speed: pointer to link speed
4165 * @link_up: TRUE when link is up
4166 * @link_up_wait_to_complete: bool used to wait for link up or not
4167 *
4168 * Reads the links register to determine if link is up and the current speed
4169 **/
ixgbe_check_mac_link_generic(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * link_up,bool link_up_wait_to_complete)4170 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4171 bool *link_up, bool link_up_wait_to_complete)
4172 {
4173 u32 links_reg, links_orig;
4174 u32 i;
4175
4176 DEBUGFUNC("ixgbe_check_mac_link_generic");
4177
4178 /* If Crosstalk fix enabled do the sanity check of making sure
4179 * the SFP+ cage is full.
4180 */
4181 if (ixgbe_need_crosstalk_fix(hw)) {
4182 u32 sfp_cage_full;
4183
4184 switch (hw->mac.type) {
4185 case ixgbe_mac_82599EB:
4186 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4187 IXGBE_ESDP_SDP2;
4188 break;
4189 case ixgbe_mac_X550EM_x:
4190 case ixgbe_mac_X550EM_a:
4191 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4192 IXGBE_ESDP_SDP0;
4193 break;
4194 default:
4195 /* sanity check - No SFP+ devices here */
4196 sfp_cage_full = FALSE;
4197 break;
4198 }
4199
4200 if (!sfp_cage_full) {
4201 *link_up = FALSE;
4202 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4203 return IXGBE_SUCCESS;
4204 }
4205 }
4206
4207 /* clear the old state */
4208 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4209
4210 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4211
4212 if (links_orig != links_reg) {
4213 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4214 links_orig, links_reg);
4215 }
4216
4217 if (link_up_wait_to_complete) {
4218 for (i = 0; i < hw->mac.max_link_up_time; i++) {
4219 if (links_reg & IXGBE_LINKS_UP) {
4220 *link_up = TRUE;
4221 break;
4222 } else {
4223 *link_up = FALSE;
4224 }
4225 msec_delay(100);
4226 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4227 }
4228 } else {
4229 if (links_reg & IXGBE_LINKS_UP)
4230 *link_up = TRUE;
4231 else
4232 *link_up = FALSE;
4233 }
4234
4235 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4236 case IXGBE_LINKS_SPEED_10G_82599:
4237 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4238 if (hw->mac.type >= ixgbe_mac_X550) {
4239 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4240 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4241 }
4242 break;
4243 case IXGBE_LINKS_SPEED_1G_82599:
4244 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4245 break;
4246 case IXGBE_LINKS_SPEED_100_82599:
4247 *speed = IXGBE_LINK_SPEED_100_FULL;
4248 if (hw->mac.type == ixgbe_mac_X550) {
4249 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4250 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4251 }
4252 break;
4253 case IXGBE_LINKS_SPEED_10_X550EM_A:
4254 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4255 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4256 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
4257 *speed = IXGBE_LINK_SPEED_10_FULL;
4258 }
4259 break;
4260 default:
4261 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4262 }
4263
4264 return IXGBE_SUCCESS;
4265 }
4266
4267 /**
4268 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4269 * the EEPROM
4270 * @hw: pointer to hardware structure
4271 * @wwnn_prefix: the alternative WWNN prefix
4272 * @wwpn_prefix: the alternative WWPN prefix
4273 *
4274 * This function will read the EEPROM from the alternative SAN MAC address
4275 * block to check the support for the alternative WWNN/WWPN prefix support.
4276 **/
ixgbe_get_wwn_prefix_generic(struct ixgbe_hw * hw,u16 * wwnn_prefix,u16 * wwpn_prefix)4277 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4278 u16 *wwpn_prefix)
4279 {
4280 u16 offset, caps;
4281 u16 alt_san_mac_blk_offset;
4282
4283 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4284
4285 /* clear output first */
4286 *wwnn_prefix = 0xFFFF;
4287 *wwpn_prefix = 0xFFFF;
4288
4289 /* check if alternative SAN MAC is supported */
4290 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4291 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4292 goto wwn_prefix_err;
4293
4294 if ((alt_san_mac_blk_offset == 0) ||
4295 (alt_san_mac_blk_offset == 0xFFFF))
4296 goto wwn_prefix_out;
4297
4298 /* check capability in alternative san mac address block */
4299 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4300 if (hw->eeprom.ops.read(hw, offset, &caps))
4301 goto wwn_prefix_err;
4302 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4303 goto wwn_prefix_out;
4304
4305 /* get the corresponding prefix for WWNN/WWPN */
4306 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4307 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4308 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4309 "eeprom read at offset %d failed", offset);
4310 }
4311
4312 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4313 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4314 goto wwn_prefix_err;
4315
4316 wwn_prefix_out:
4317 return IXGBE_SUCCESS;
4318
4319 wwn_prefix_err:
4320 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4321 "eeprom read at offset %d failed", offset);
4322 return IXGBE_SUCCESS;
4323 }
4324
4325 /**
4326 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4327 * @hw: pointer to hardware structure
4328 * @bs: the fcoe boot status
4329 *
4330 * This function will read the FCOE boot status from the iSCSI FCOE block
4331 **/
ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw * hw,u16 * bs)4332 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4333 {
4334 u16 offset, caps, flags;
4335 s32 status;
4336
4337 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4338
4339 /* clear output first */
4340 *bs = ixgbe_fcoe_bootstatus_unavailable;
4341
4342 /* check if FCOE IBA block is present */
4343 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4344 status = hw->eeprom.ops.read(hw, offset, &caps);
4345 if (status != IXGBE_SUCCESS)
4346 goto out;
4347
4348 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4349 goto out;
4350
4351 /* check if iSCSI FCOE block is populated */
4352 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4353 if (status != IXGBE_SUCCESS)
4354 goto out;
4355
4356 if ((offset == 0) || (offset == 0xFFFF))
4357 goto out;
4358
4359 /* read fcoe flags in iSCSI FCOE block */
4360 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4361 status = hw->eeprom.ops.read(hw, offset, &flags);
4362 if (status != IXGBE_SUCCESS)
4363 goto out;
4364
4365 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4366 *bs = ixgbe_fcoe_bootstatus_enabled;
4367 else
4368 *bs = ixgbe_fcoe_bootstatus_disabled;
4369
4370 out:
4371 return status;
4372 }
4373
4374 /**
4375 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4376 * @hw: pointer to hardware structure
4377 * @enable: enable or disable switch for MAC anti-spoofing
4378 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
4379 *
4380 **/
ixgbe_set_mac_anti_spoofing(struct ixgbe_hw * hw,bool enable,int vf)4381 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4382 {
4383 int vf_target_reg = vf >> 3;
4384 int vf_target_shift = vf % 8;
4385 u32 pfvfspoof;
4386
4387 if (hw->mac.type == ixgbe_mac_82598EB)
4388 return;
4389
4390 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4391 if (enable)
4392 pfvfspoof |= (1 << vf_target_shift);
4393 else
4394 pfvfspoof &= ~(1 << vf_target_shift);
4395 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4396 }
4397
4398 /**
4399 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4400 * @hw: pointer to hardware structure
4401 * @enable: enable or disable switch for VLAN anti-spoofing
4402 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4403 *
4404 **/
ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw * hw,bool enable,int vf)4405 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4406 {
4407 int vf_target_reg = vf >> 3;
4408 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4409 u32 pfvfspoof;
4410
4411 if (hw->mac.type == ixgbe_mac_82598EB)
4412 return;
4413
4414 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4415 if (enable)
4416 pfvfspoof |= (1 << vf_target_shift);
4417 else
4418 pfvfspoof &= ~(1 << vf_target_shift);
4419 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4420 }
4421
4422 /**
4423 * ixgbe_get_device_caps_generic - Get additional device capabilities
4424 * @hw: pointer to hardware structure
4425 * @device_caps: the EEPROM word with the extra device capabilities
4426 *
4427 * This function will read the EEPROM location for the device capabilities,
4428 * and return the word through device_caps.
4429 **/
ixgbe_get_device_caps_generic(struct ixgbe_hw * hw,u16 * device_caps)4430 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4431 {
4432 DEBUGFUNC("ixgbe_get_device_caps_generic");
4433
4434 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4435
4436 return IXGBE_SUCCESS;
4437 }
4438
4439 /**
4440 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4441 * @hw: pointer to hardware structure
4442 *
4443 **/
ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw * hw)4444 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4445 {
4446 u32 regval;
4447 u32 i;
4448
4449 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4450
4451 /* Enable relaxed ordering */
4452 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4453 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4454 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4455 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4456 }
4457
4458 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4459 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4460 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4461 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4462 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4463 }
4464
4465 }
4466
4467 /**
4468 * ixgbe_calculate_checksum - Calculate checksum for buffer
4469 * @buffer: pointer to EEPROM
4470 * @length: size of EEPROM to calculate a checksum for
4471 * Calculates the checksum for some buffer on a specified length. The
4472 * checksum calculated is returned.
4473 **/
ixgbe_calculate_checksum(u8 * buffer,u32 length)4474 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4475 {
4476 u32 i;
4477 u8 sum = 0;
4478
4479 DEBUGFUNC("ixgbe_calculate_checksum");
4480
4481 if (!buffer)
4482 return 0;
4483
4484 for (i = 0; i < length; i++)
4485 sum += buffer[i];
4486
4487 return (u8) (0 - sum);
4488 }
4489
4490 /**
4491 * ixgbe_hic_unlocked - Issue command to manageability block unlocked
4492 * @hw: pointer to the HW structure
4493 * @buffer: command to write and where the return status will be placed
4494 * @length: length of buffer, must be multiple of 4 bytes
4495 * @timeout: time in ms to wait for command completion
4496 *
4497 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4498 * else returns semaphore error when encountering an error acquiring
4499 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4500 *
4501 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held
4502 * by the caller.
4503 **/
ixgbe_hic_unlocked(struct ixgbe_hw * hw,u32 * buffer,u32 length,u32 timeout)4504 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,
4505 u32 timeout)
4506 {
4507 u32 hicr, i, fwsts;
4508 u16 dword_len;
4509
4510 DEBUGFUNC("ixgbe_hic_unlocked");
4511
4512 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4513 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4514 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4515 }
4516
4517 /* Set bit 9 of FWSTS clearing FW reset indication */
4518 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4519 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4520
4521 /* Check that the host interface is enabled. */
4522 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4523 if (!(hicr & IXGBE_HICR_EN)) {
4524 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4525 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4526 }
4527
4528 /* Calculate length in DWORDs. We must be DWORD aligned */
4529 if (length % sizeof(u32)) {
4530 DEBUGOUT("Buffer length failure, not aligned to dword");
4531 return IXGBE_ERR_INVALID_ARGUMENT;
4532 }
4533
4534 dword_len = length >> 2;
4535
4536 /* The device driver writes the relevant command block
4537 * into the ram area.
4538 */
4539 for (i = 0; i < dword_len; i++)
4540 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4541 i, IXGBE_CPU_TO_LE32(buffer[i]));
4542
4543 /* Setting this bit tells the ARC that a new command is pending. */
4544 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4545
4546 for (i = 0; i < timeout; i++) {
4547 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4548 if (!(hicr & IXGBE_HICR_C))
4549 break;
4550 msec_delay(1);
4551 }
4552
4553 /* Check command completion */
4554 if ((timeout && i == timeout) ||
4555 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4556 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4557 "Command has failed with no status valid.\n");
4558 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4559 }
4560
4561 return IXGBE_SUCCESS;
4562 }
4563
4564 /**
4565 * ixgbe_host_interface_command - Issue command to manageability block
4566 * @hw: pointer to the HW structure
4567 * @buffer: contains the command to write and where the return status will
4568 * be placed
4569 * @length: length of buffer, must be multiple of 4 bytes
4570 * @timeout: time in ms to wait for command completion
4571 * @return_data: read and return data from the buffer (TRUE) or not (FALSE)
4572 * Needed because FW structures are big endian and decoding of
4573 * these fields can be 8 bit or 16 bit based on command. Decoding
4574 * is not easily understood without making a table of commands.
4575 * So we will leave this up to the caller to read back the data
4576 * in these cases.
4577 *
4578 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4579 * else returns semaphore error when encountering an error acquiring
4580 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4581 **/
ixgbe_host_interface_command(struct ixgbe_hw * hw,u32 * buffer,u32 length,u32 timeout,bool return_data)4582 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4583 u32 length, u32 timeout, bool return_data)
4584 {
4585 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4586 u16 dword_len;
4587 u16 buf_len;
4588 s32 status;
4589 u32 bi;
4590
4591 DEBUGFUNC("ixgbe_host_interface_command");
4592
4593 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4594 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4595 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4596 }
4597
4598 /* Take management host interface semaphore */
4599 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4600 if (status)
4601 return status;
4602
4603 status = ixgbe_hic_unlocked(hw, buffer, length, timeout);
4604 if (status)
4605 goto rel_out;
4606
4607 if (!return_data)
4608 goto rel_out;
4609
4610 /* Calculate length in DWORDs */
4611 dword_len = hdr_size >> 2;
4612
4613 /* first pull in the header so we know the buffer length */
4614 for (bi = 0; bi < dword_len; bi++) {
4615 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4616 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4617 }
4618
4619 /* If there is any thing in data position pull it in */
4620 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
4621 if (!buf_len)
4622 goto rel_out;
4623
4624 if (length < buf_len + hdr_size) {
4625 DEBUGOUT("Buffer not large enough for reply message.\n");
4626 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4627 goto rel_out;
4628 }
4629
4630 /* Calculate length in DWORDs, add 3 for odd lengths */
4631 dword_len = (buf_len + 3) >> 2;
4632
4633 /* Pull in the rest of the buffer (bi is where we left off) */
4634 for (; bi <= dword_len; bi++) {
4635 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4636 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4637 }
4638
4639 rel_out:
4640 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4641
4642 return status;
4643 }
4644
4645 /**
4646 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4647 * @hw: pointer to the HW structure
4648 * @maj: driver version major number
4649 * @min: driver version minor number
4650 * @build: driver version build number
4651 * @sub: driver version sub build number
4652 *
4653 * Sends driver version number to firmware through the manageability
4654 * block. On success return IXGBE_SUCCESS
4655 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4656 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4657 **/
ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw * hw,u8 maj,u8 min,u8 build,u8 sub,u16 len,const char * driver_ver)4658 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4659 u8 build, u8 sub, u16 len,
4660 const char *driver_ver)
4661 {
4662 struct ixgbe_hic_drv_info fw_cmd;
4663 int i;
4664 s32 ret_val = IXGBE_SUCCESS;
4665
4666 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4667 UNREFERENCED_2PARAMETER(len, driver_ver);
4668
4669 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4670 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4671 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4672 fw_cmd.port_num = (u8)hw->bus.func;
4673 fw_cmd.ver_maj = maj;
4674 fw_cmd.ver_min = min;
4675 fw_cmd.ver_build = build;
4676 fw_cmd.ver_sub = sub;
4677 fw_cmd.hdr.checksum = 0;
4678 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4679 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4680 fw_cmd.pad = 0;
4681 fw_cmd.pad2 = 0;
4682
4683 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4684 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4685 sizeof(fw_cmd),
4686 IXGBE_HI_COMMAND_TIMEOUT,
4687 TRUE);
4688 if (ret_val != IXGBE_SUCCESS)
4689 continue;
4690
4691 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4692 FW_CEM_RESP_STATUS_SUCCESS)
4693 ret_val = IXGBE_SUCCESS;
4694 else
4695 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4696
4697 break;
4698 }
4699
4700 return ret_val;
4701 }
4702
4703 /**
4704 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4705 * @hw: pointer to hardware structure
4706 * @num_pb: number of packet buffers to allocate
4707 * @headroom: reserve n KB of headroom
4708 * @strategy: packet buffer allocation strategy
4709 **/
ixgbe_set_rxpba_generic(struct ixgbe_hw * hw,int num_pb,u32 headroom,int strategy)4710 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4711 int strategy)
4712 {
4713 u32 pbsize = hw->mac.rx_pb_size;
4714 int i = 0;
4715 u32 rxpktsize, txpktsize, txpbthresh;
4716
4717 /* Reserve headroom */
4718 pbsize -= headroom;
4719
4720 if (!num_pb)
4721 num_pb = 1;
4722
4723 /* Divide remaining packet buffer space amongst the number of packet
4724 * buffers requested using supplied strategy.
4725 */
4726 switch (strategy) {
4727 case PBA_STRATEGY_WEIGHTED:
4728 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4729 * buffer with 5/8 of the packet buffer space.
4730 */
4731 rxpktsize = (pbsize * 5) / (num_pb * 4);
4732 pbsize -= rxpktsize * (num_pb / 2);
4733 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4734 for (; i < (num_pb / 2); i++)
4735 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4736 /* configure remaining packet buffers */
4737 /* FALLTHROUGH */
4738 case PBA_STRATEGY_EQUAL:
4739 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4740 for (; i < num_pb; i++)
4741 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4742 break;
4743 default:
4744 break;
4745 }
4746
4747 /* Only support an equally distributed Tx packet buffer strategy. */
4748 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4749 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4750 for (i = 0; i < num_pb; i++) {
4751 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4752 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4753 }
4754
4755 /* Clear unused TCs, if any, to zero buffer size*/
4756 for (; i < IXGBE_MAX_PB; i++) {
4757 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4758 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4759 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4760 }
4761 }
4762
4763 /**
4764 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4765 * @hw: pointer to the hardware structure
4766 *
4767 * The 82599 and x540 MACs can experience issues if TX work is still pending
4768 * when a reset occurs. This function prevents this by flushing the PCIe
4769 * buffers on the system.
4770 **/
ixgbe_clear_tx_pending(struct ixgbe_hw * hw)4771 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4772 {
4773 u32 gcr_ext, hlreg0, i, poll;
4774 u16 value;
4775
4776 /*
4777 * If double reset is not requested then all transactions should
4778 * already be clear and as such there is no work to do
4779 */
4780 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4781 return;
4782
4783 /*
4784 * Set loopback enable to prevent any transmits from being sent
4785 * should the link come up. This assumes that the RXCTRL.RXEN bit
4786 * has already been cleared.
4787 */
4788 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4789 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4790
4791 /* Wait for a last completion before clearing buffers */
4792 IXGBE_WRITE_FLUSH(hw);
4793 msec_delay(3);
4794
4795 /*
4796 * Before proceeding, make sure that the PCIe block does not have
4797 * transactions pending.
4798 */
4799 poll = ixgbe_pcie_timeout_poll(hw);
4800 for (i = 0; i < poll; i++) {
4801 usec_delay(100);
4802 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
4803 if (IXGBE_REMOVED(hw->hw_addr))
4804 goto out;
4805 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
4806 goto out;
4807 }
4808
4809 out:
4810 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4811 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4812 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4813 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4814
4815 /* Flush all writes and allow 20usec for all transactions to clear */
4816 IXGBE_WRITE_FLUSH(hw);
4817 usec_delay(20);
4818
4819 /* restore previous register values */
4820 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4821 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4822 }
4823
4824 /**
4825 * ixgbe_bypass_rw_generic - Bit bang data into by_pass FW
4826 *
4827 * @hw: pointer to hardware structure
4828 * @cmd: Command we send to the FW
4829 * @status: The reply from the FW
4830 *
4831 * Bit-bangs the cmd to the by_pass FW status points to what is returned.
4832 **/
4833 #define IXGBE_BYPASS_BB_WAIT 1
ixgbe_bypass_rw_generic(struct ixgbe_hw * hw,u32 cmd,u32 * status)4834 s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status)
4835 {
4836 int i;
4837 u32 sck, sdi, sdo, dir_sck, dir_sdi, dir_sdo;
4838 u32 esdp;
4839
4840 if (!status)
4841 return IXGBE_ERR_PARAM;
4842
4843 *status = 0;
4844
4845 /* SDP vary by MAC type */
4846 switch (hw->mac.type) {
4847 case ixgbe_mac_82599EB:
4848 sck = IXGBE_ESDP_SDP7;
4849 sdi = IXGBE_ESDP_SDP0;
4850 sdo = IXGBE_ESDP_SDP6;
4851 dir_sck = IXGBE_ESDP_SDP7_DIR;
4852 dir_sdi = IXGBE_ESDP_SDP0_DIR;
4853 dir_sdo = IXGBE_ESDP_SDP6_DIR;
4854 break;
4855 case ixgbe_mac_X540:
4856 sck = IXGBE_ESDP_SDP2;
4857 sdi = IXGBE_ESDP_SDP0;
4858 sdo = IXGBE_ESDP_SDP1;
4859 dir_sck = IXGBE_ESDP_SDP2_DIR;
4860 dir_sdi = IXGBE_ESDP_SDP0_DIR;
4861 dir_sdo = IXGBE_ESDP_SDP1_DIR;
4862 break;
4863 default:
4864 return IXGBE_ERR_DEVICE_NOT_SUPPORTED;
4865 }
4866
4867 /* Set SDP pins direction */
4868 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4869 esdp |= dir_sck; /* SCK as output */
4870 esdp |= dir_sdi; /* SDI as output */
4871 esdp &= ~dir_sdo; /* SDO as input */
4872 esdp |= sck;
4873 esdp |= sdi;
4874 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4875 IXGBE_WRITE_FLUSH(hw);
4876 msec_delay(IXGBE_BYPASS_BB_WAIT);
4877
4878 /* Generate start condition */
4879 esdp &= ~sdi;
4880 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4881 IXGBE_WRITE_FLUSH(hw);
4882 msec_delay(IXGBE_BYPASS_BB_WAIT);
4883
4884 esdp &= ~sck;
4885 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4886 IXGBE_WRITE_FLUSH(hw);
4887 msec_delay(IXGBE_BYPASS_BB_WAIT);
4888
4889 /* Clock out the new control word and clock in the status */
4890 for (i = 0; i < 32; i++) {
4891 if ((cmd >> (31 - i)) & 0x01) {
4892 esdp |= sdi;
4893 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4894 } else {
4895 esdp &= ~sdi;
4896 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4897 }
4898 IXGBE_WRITE_FLUSH(hw);
4899 msec_delay(IXGBE_BYPASS_BB_WAIT);
4900
4901 esdp |= sck;
4902 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4903 IXGBE_WRITE_FLUSH(hw);
4904 msec_delay(IXGBE_BYPASS_BB_WAIT);
4905
4906 esdp &= ~sck;
4907 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4908 IXGBE_WRITE_FLUSH(hw);
4909 msec_delay(IXGBE_BYPASS_BB_WAIT);
4910
4911 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4912 if (esdp & sdo)
4913 *status = (*status << 1) | 0x01;
4914 else
4915 *status = (*status << 1) | 0x00;
4916 msec_delay(IXGBE_BYPASS_BB_WAIT);
4917 }
4918
4919 /* stop condition */
4920 esdp |= sck;
4921 esdp &= ~sdi;
4922 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4923 IXGBE_WRITE_FLUSH(hw);
4924 msec_delay(IXGBE_BYPASS_BB_WAIT);
4925
4926 esdp |= sdi;
4927 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4928 IXGBE_WRITE_FLUSH(hw);
4929
4930 /* set the page bits to match the cmd that the status it belongs to */
4931 *status = (*status & 0x3fffffff) | (cmd & 0xc0000000);
4932
4933 return IXGBE_SUCCESS;
4934 }
4935
4936 /**
4937 * ixgbe_bypass_valid_rd_generic - Verify valid return from bit-bang.
4938 *
4939 * If we send a write we can't be sure it took until we can read back
4940 * that same register. It can be a problem as some of the feilds may
4941 * for valid reasons change inbetween the time wrote the register and
4942 * we read it again to verify. So this function check everything we
4943 * can check and then assumes it worked.
4944 *
4945 * @u32 in_reg - The register cmd for the bit-bang read.
4946 * @u32 out_reg - The register returned from a bit-bang read.
4947 **/
ixgbe_bypass_valid_rd_generic(u32 in_reg,u32 out_reg)4948 bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg)
4949 {
4950 u32 mask;
4951
4952 /* Page must match for all control pages */
4953 if ((in_reg & BYPASS_PAGE_M) != (out_reg & BYPASS_PAGE_M))
4954 return FALSE;
4955
4956 switch (in_reg & BYPASS_PAGE_M) {
4957 case BYPASS_PAGE_CTL0:
4958 /* All the following can't change since the last write
4959 * - All the event actions
4960 * - The timeout value
4961 */
4962 mask = BYPASS_AUX_ON_M | BYPASS_MAIN_ON_M |
4963 BYPASS_MAIN_OFF_M | BYPASS_AUX_OFF_M |
4964 BYPASS_WDTIMEOUT_M |
4965 BYPASS_WDT_VALUE_M;
4966 if ((out_reg & mask) != (in_reg & mask))
4967 return FALSE;
4968
4969 /* 0x0 is never a valid value for bypass status */
4970 if (!(out_reg & BYPASS_STATUS_OFF_M))
4971 return FALSE;
4972 break;
4973 case BYPASS_PAGE_CTL1:
4974 /* All the following can't change since the last write
4975 * - time valid bit
4976 * - time we last sent
4977 */
4978 mask = BYPASS_CTL1_VALID_M | BYPASS_CTL1_TIME_M;
4979 if ((out_reg & mask) != (in_reg & mask))
4980 return FALSE;
4981 break;
4982 case BYPASS_PAGE_CTL2:
4983 /* All we can check in this page is control number
4984 * which is already done above.
4985 */
4986 break;
4987 }
4988
4989 /* We are as sure as we can be return TRUE */
4990 return TRUE;
4991 }
4992
4993 /**
4994 * ixgbe_bypass_set_generic - Set a bypass field in the FW CTRL Regiter.
4995 *
4996 * @hw: pointer to hardware structure
4997 * @cmd: The control word we are setting.
4998 * @event: The event we are setting in the FW. This also happens to
4999 * be the mask for the event we are setting (handy)
5000 * @action: The action we set the event to in the FW. This is in a
5001 * bit field that happens to be what we want to put in
5002 * the event spot (also handy)
5003 **/
ixgbe_bypass_set_generic(struct ixgbe_hw * hw,u32 ctrl,u32 event,u32 action)5004 s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event,
5005 u32 action)
5006 {
5007 u32 by_ctl = 0;
5008 u32 cmd, verify;
5009 u32 count = 0;
5010
5011 /* Get current values */
5012 cmd = ctrl; /* just reading only need control number */
5013 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl))
5014 return IXGBE_ERR_INVALID_ARGUMENT;
5015
5016 /* Set to new action */
5017 cmd = (by_ctl & ~event) | BYPASS_WE | action;
5018 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl))
5019 return IXGBE_ERR_INVALID_ARGUMENT;
5020
5021 /* Page 0 force a FW eeprom write which is slow so verify */
5022 if ((cmd & BYPASS_PAGE_M) == BYPASS_PAGE_CTL0) {
5023 verify = BYPASS_PAGE_CTL0;
5024 do {
5025 if (count++ > 5)
5026 return IXGBE_BYPASS_FW_WRITE_FAILURE;
5027
5028 if (ixgbe_bypass_rw_generic(hw, verify, &by_ctl))
5029 return IXGBE_ERR_INVALID_ARGUMENT;
5030 } while (!ixgbe_bypass_valid_rd_generic(cmd, by_ctl));
5031 } else {
5032 /* We have give the FW time for the write to stick */
5033 msec_delay(100);
5034 }
5035
5036 return IXGBE_SUCCESS;
5037 }
5038
5039 /**
5040 * ixgbe_bypass_rd_eep_generic - Read the bypass FW eeprom addres.
5041 *
5042 * @hw: pointer to hardware structure
5043 * @addr: The bypass eeprom address to read.
5044 * @value: The 8b of data at the address above.
5045 **/
ixgbe_bypass_rd_eep_generic(struct ixgbe_hw * hw,u32 addr,u8 * value)5046 s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value)
5047 {
5048 u32 cmd;
5049 u32 status;
5050
5051
5052 /* send the request */
5053 cmd = BYPASS_PAGE_CTL2 | BYPASS_WE;
5054 cmd |= (addr << BYPASS_CTL2_OFFSET_SHIFT) & BYPASS_CTL2_OFFSET_M;
5055 if (ixgbe_bypass_rw_generic(hw, cmd, &status))
5056 return IXGBE_ERR_INVALID_ARGUMENT;
5057
5058 /* We have give the FW time for the write to stick */
5059 msec_delay(100);
5060
5061 /* now read the results */
5062 cmd &= ~BYPASS_WE;
5063 if (ixgbe_bypass_rw_generic(hw, cmd, &status))
5064 return IXGBE_ERR_INVALID_ARGUMENT;
5065
5066 *value = status & BYPASS_CTL2_DATA_M;
5067
5068 return IXGBE_SUCCESS;
5069 }
5070
5071
5072 /**
5073 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
5074 * @hw: pointer to hardware structure
5075 * @map: pointer to u8 arr for returning map
5076 *
5077 * Read the rtrup2tc HW register and resolve its content into map
5078 **/
ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw * hw,u8 * map)5079 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
5080 {
5081 u32 reg, i;
5082
5083 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
5084 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
5085 map[i] = IXGBE_RTRUP2TC_UP_MASK &
5086 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
5087 return;
5088 }
5089
ixgbe_disable_rx_generic(struct ixgbe_hw * hw)5090 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
5091 {
5092 u32 pfdtxgswc;
5093 u32 rxctrl;
5094
5095 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5096 if (rxctrl & IXGBE_RXCTRL_RXEN) {
5097 if (hw->mac.type != ixgbe_mac_82598EB) {
5098 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5099 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
5100 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5101 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
5102 hw->mac.set_lben = TRUE;
5103 } else {
5104 hw->mac.set_lben = FALSE;
5105 }
5106 }
5107 rxctrl &= ~IXGBE_RXCTRL_RXEN;
5108 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
5109 }
5110 }
5111
ixgbe_enable_rx_generic(struct ixgbe_hw * hw)5112 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
5113 {
5114 u32 pfdtxgswc;
5115 u32 rxctrl;
5116
5117 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5118 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
5119
5120 if (hw->mac.type != ixgbe_mac_82598EB) {
5121 if (hw->mac.set_lben) {
5122 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5123 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
5124 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
5125 hw->mac.set_lben = FALSE;
5126 }
5127 }
5128 }
5129
5130 /**
5131 * ixgbe_mng_present - returns TRUE when management capability is present
5132 * @hw: pointer to hardware structure
5133 */
ixgbe_mng_present(struct ixgbe_hw * hw)5134 bool ixgbe_mng_present(struct ixgbe_hw *hw)
5135 {
5136 u32 fwsm;
5137
5138 if (hw->mac.type < ixgbe_mac_82599EB)
5139 return FALSE;
5140
5141 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5142 fwsm &= IXGBE_FWSM_MODE_MASK;
5143 return fwsm == IXGBE_FWSM_FW_MODE_PT;
5144 }
5145
5146 /**
5147 * ixgbe_mng_enabled - Is the manageability engine enabled?
5148 * @hw: pointer to hardware structure
5149 *
5150 * Returns TRUE if the manageability engine is enabled.
5151 **/
ixgbe_mng_enabled(struct ixgbe_hw * hw)5152 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
5153 {
5154 u32 fwsm, manc, factps;
5155
5156 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5157 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
5158 return FALSE;
5159
5160 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
5161 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
5162 return FALSE;
5163
5164 if (hw->mac.type <= ixgbe_mac_X540) {
5165 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
5166 if (factps & IXGBE_FACTPS_MNGCG)
5167 return FALSE;
5168 }
5169
5170 return TRUE;
5171 }
5172
5173 /**
5174 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
5175 * @hw: pointer to hardware structure
5176 * @speed: new link speed
5177 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
5178 *
5179 * Set the link speed in the MAC and/or PHY register and restarts link.
5180 **/
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait_to_complete)5181 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
5182 ixgbe_link_speed speed,
5183 bool autoneg_wait_to_complete)
5184 {
5185 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5186 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5187 s32 status = IXGBE_SUCCESS;
5188 u32 speedcnt = 0;
5189 u32 i = 0;
5190 bool autoneg, link_up = FALSE;
5191
5192 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
5193
5194 /* Mask off requested but non-supported speeds */
5195 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
5196 if (status != IXGBE_SUCCESS)
5197 return status;
5198
5199 speed &= link_speed;
5200
5201 /* Try each speed one by one, highest priority first. We do this in
5202 * software because 10Gb fiber doesn't support speed autonegotiation.
5203 */
5204 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
5205 speedcnt++;
5206 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5207
5208 /* Set the module link speed */
5209 switch (hw->phy.media_type) {
5210 case ixgbe_media_type_fiber_fixed:
5211 case ixgbe_media_type_fiber:
5212 ixgbe_set_rate_select_speed(hw,
5213 IXGBE_LINK_SPEED_10GB_FULL);
5214 break;
5215 case ixgbe_media_type_fiber_qsfp:
5216 /* QSFP module automatically detects MAC link speed */
5217 break;
5218 default:
5219 DEBUGOUT("Unexpected media type.\n");
5220 break;
5221 }
5222
5223 /* Allow module to change analog characteristics (1G->10G) */
5224 msec_delay(40);
5225
5226 status = ixgbe_setup_mac_link(hw,
5227 IXGBE_LINK_SPEED_10GB_FULL,
5228 autoneg_wait_to_complete);
5229 if (status != IXGBE_SUCCESS)
5230 return status;
5231
5232 /* Flap the Tx laser if it has not already been done */
5233 ixgbe_flap_tx_laser(hw);
5234
5235 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
5236 * Section 73.10.2, we may have to wait up to 500ms if KR is
5237 * attempted. 82599 uses the same timing for 10g SFI.
5238 */
5239 for (i = 0; i < 5; i++) {
5240 /* Wait for the link partner to also set speed */
5241 msec_delay(100);
5242
5243 /* If we have link, just jump out */
5244 status = ixgbe_check_link(hw, &link_speed,
5245 &link_up, FALSE);
5246 if (status != IXGBE_SUCCESS)
5247 return status;
5248
5249 if (link_up)
5250 goto out;
5251 }
5252 }
5253
5254 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
5255 speedcnt++;
5256 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
5257 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
5258
5259 /* Set the module link speed */
5260 switch (hw->phy.media_type) {
5261 case ixgbe_media_type_fiber_fixed:
5262 case ixgbe_media_type_fiber:
5263 ixgbe_set_rate_select_speed(hw,
5264 IXGBE_LINK_SPEED_1GB_FULL);
5265 break;
5266 case ixgbe_media_type_fiber_qsfp:
5267 /* QSFP module automatically detects link speed */
5268 break;
5269 default:
5270 DEBUGOUT("Unexpected media type.\n");
5271 break;
5272 }
5273
5274 /* Allow module to change analog characteristics (10G->1G) */
5275 msec_delay(40);
5276
5277 status = ixgbe_setup_mac_link(hw,
5278 IXGBE_LINK_SPEED_1GB_FULL,
5279 autoneg_wait_to_complete);
5280 if (status != IXGBE_SUCCESS)
5281 return status;
5282
5283 /* Flap the Tx laser if it has not already been done */
5284 ixgbe_flap_tx_laser(hw);
5285
5286 /* Wait for the link partner to also set speed */
5287 msec_delay(100);
5288
5289 /* If we have link, just jump out */
5290 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
5291 if (status != IXGBE_SUCCESS)
5292 return status;
5293
5294 if (link_up)
5295 goto out;
5296 }
5297
5298 /* We didn't get link. Configure back to the highest speed we tried,
5299 * (if there was more than one). We call ourselves back with just the
5300 * single highest speed that the user requested.
5301 */
5302 if (speedcnt > 1)
5303 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
5304 highest_link_speed,
5305 autoneg_wait_to_complete);
5306
5307 out:
5308 /* Set autoneg_advertised value based on input link speed */
5309 hw->phy.autoneg_advertised = 0;
5310
5311 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
5312 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
5313
5314 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
5315 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
5316
5317 return status;
5318 }
5319
5320 /**
5321 * ixgbe_set_soft_rate_select_speed - Set module link speed
5322 * @hw: pointer to hardware structure
5323 * @speed: link speed to set
5324 *
5325 * Set module link speed via the soft rate select.
5326 */
ixgbe_set_soft_rate_select_speed(struct ixgbe_hw * hw,ixgbe_link_speed speed)5327 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
5328 ixgbe_link_speed speed)
5329 {
5330 s32 status;
5331 u8 rs, eeprom_data;
5332
5333 switch (speed) {
5334 case IXGBE_LINK_SPEED_10GB_FULL:
5335 /* one bit mask same as setting on */
5336 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
5337 break;
5338 case IXGBE_LINK_SPEED_1GB_FULL:
5339 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
5340 break;
5341 default:
5342 DEBUGOUT("Invalid fixed module speed\n");
5343 return;
5344 }
5345
5346 /* Set RS0 */
5347 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5348 IXGBE_I2C_EEPROM_DEV_ADDR2,
5349 &eeprom_data);
5350 if (status) {
5351 DEBUGOUT("Failed to read Rx Rate Select RS0\n");
5352 goto out;
5353 }
5354
5355 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5356
5357 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5358 IXGBE_I2C_EEPROM_DEV_ADDR2,
5359 eeprom_data);
5360 if (status) {
5361 DEBUGOUT("Failed to write Rx Rate Select RS0\n");
5362 goto out;
5363 }
5364
5365 /* Set RS1 */
5366 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5367 IXGBE_I2C_EEPROM_DEV_ADDR2,
5368 &eeprom_data);
5369 if (status) {
5370 DEBUGOUT("Failed to read Rx Rate Select RS1\n");
5371 goto out;
5372 }
5373
5374 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5375
5376 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5377 IXGBE_I2C_EEPROM_DEV_ADDR2,
5378 eeprom_data);
5379 if (status) {
5380 DEBUGOUT("Failed to write Rx Rate Select RS1\n");
5381 goto out;
5382 }
5383 out:
5384 return;
5385 }
5386