1 /* $NetBSD: ixgbe_common.c,v 1.48 2025/02/17 22:56:46 andvar Exp $ */
2
3 /******************************************************************************
4 SPDX-License-Identifier: BSD-3-Clause
5
6 Copyright (c) 2001-2020, Intel Corporation
7 All rights reserved.
8
9 Redistribution and use in source and binary forms, with or without
10 modification, are permitted provided that the following conditions are met:
11
12 1. Redistributions of source code must retain the above copyright notice,
13 this list of conditions and the following disclaimer.
14
15 2. Redistributions in binary form must reproduce the above copyright
16 notice, this list of conditions and the following disclaimer in the
17 documentation and/or other materials provided with the distribution.
18
19 3. Neither the name of the Intel Corporation nor the names of its
20 contributors may be used to endorse or promote products derived from
21 this software without specific prior written permission.
22
23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 POSSIBILITY OF SUCH DAMAGE.
34
35 ******************************************************************************/
36 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.c 331224 2018-03-19 20:55:05Z erj $*/
37
38 #include <sys/cdefs.h>
39 __KERNEL_RCSID(0, "$NetBSD: ixgbe_common.c,v 1.48 2025/02/17 22:56:46 andvar Exp $");
40
41 #include "ixgbe_common.h"
42 #include "ixgbe_phy.h"
43 #include "ixgbe_dcb.h"
44 #include "ixgbe_dcb_82599.h"
45 #include "ixgbe_api.h"
46
47 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
48 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
49 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
50 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
51 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
52 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
53 u16 count);
54 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
55 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
56 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
57 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
58
59 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
60 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
61 u16 *san_mac_offset);
62 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
63 u16 words, u16 *data);
64 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
65 u16 words, u16 *data);
66 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
67 u16 offset);
68
69 /**
70 * ixgbe_init_ops_generic - Inits function ptrs
71 * @hw: pointer to the hardware structure
72 *
73 * Initialize the function pointers.
74 **/
ixgbe_init_ops_generic(struct ixgbe_hw * hw)75 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
76 {
77 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
78 struct ixgbe_mac_info *mac = &hw->mac;
79 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
80
81 DEBUGFUNC("ixgbe_init_ops_generic");
82
83 /* EEPROM */
84 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
85 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
86 if (eec & IXGBE_EEC_PRES) {
87 eeprom->ops.read = ixgbe_read_eerd_generic;
88 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
89 } else {
90 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
91 eeprom->ops.read_buffer =
92 ixgbe_read_eeprom_buffer_bit_bang_generic;
93 }
94 eeprom->ops.write = ixgbe_write_eeprom_generic;
95 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
96 eeprom->ops.validate_checksum =
97 ixgbe_validate_eeprom_checksum_generic;
98 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
99 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
100
101 /* MAC */
102 mac->ops.init_hw = ixgbe_init_hw_generic;
103 mac->ops.reset_hw = NULL;
104 mac->ops.start_hw = ixgbe_start_hw_generic;
105 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
106 mac->ops.get_media_type = NULL;
107 mac->ops.get_supported_physical_layer = NULL;
108 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
109 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
110 mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
111 mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
112 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
113 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
114 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
115 mac->ops.prot_autoc_read = prot_autoc_read_generic;
116 mac->ops.prot_autoc_write = prot_autoc_write_generic;
117
118 /* LEDs */
119 mac->ops.led_on = ixgbe_led_on_generic;
120 mac->ops.led_off = ixgbe_led_off_generic;
121 mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
122 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
123 mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic;
124
125 /* RAR, Multicast, VLAN */
126 mac->ops.set_rar = ixgbe_set_rar_generic;
127 mac->ops.clear_rar = ixgbe_clear_rar_generic;
128 mac->ops.insert_mac_addr = NULL;
129 mac->ops.set_vmdq = NULL;
130 mac->ops.clear_vmdq = NULL;
131 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
132 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
133 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
134 mac->ops.enable_mc = ixgbe_enable_mc_generic;
135 mac->ops.disable_mc = ixgbe_disable_mc_generic;
136 mac->ops.clear_vfta = NULL;
137 mac->ops.set_vfta = NULL;
138 mac->ops.set_vlvf = NULL;
139 mac->ops.init_uta_tables = NULL;
140 mac->ops.enable_rx = ixgbe_enable_rx_generic;
141 mac->ops.disable_rx = ixgbe_disable_rx_generic;
142 mac->ops.toggle_txdctl = ixgbe_toggle_txdctl_generic;
143
144 /* Flow Control */
145 mac->ops.fc_enable = ixgbe_fc_enable_generic;
146 mac->ops.setup_fc = ixgbe_setup_fc_generic;
147 mac->ops.fc_autoneg = ixgbe_fc_autoneg;
148
149 /* Link */
150 mac->ops.get_link_capabilities = NULL;
151 mac->ops.setup_link = NULL;
152 mac->ops.check_link = NULL;
153 mac->ops.dmac_config = NULL;
154 mac->ops.dmac_update_tcs = NULL;
155 mac->ops.dmac_config_tcs = NULL;
156
157 return IXGBE_SUCCESS;
158 }
159
160 /**
161 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
162 * of flow control
163 * @hw: pointer to hardware structure
164 *
165 * This function returns TRUE if the device supports flow control
166 * autonegotiation, and FALSE if it does not.
167 *
168 **/
ixgbe_device_supports_autoneg_fc(struct ixgbe_hw * hw)169 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
170 {
171 bool supported = FALSE;
172 ixgbe_link_speed speed;
173 bool link_up;
174
175 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
176
177 switch (hw->phy.media_type) {
178 case ixgbe_media_type_fiber_fixed:
179 case ixgbe_media_type_fiber_qsfp:
180 case ixgbe_media_type_fiber:
181 /* flow control autoneg block list */
182 switch (hw->device_id) {
183 case IXGBE_DEV_ID_X550EM_A_SFP:
184 case IXGBE_DEV_ID_X550EM_A_SFP_N:
185 case IXGBE_DEV_ID_X550EM_A_QSFP:
186 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
187 supported = FALSE;
188 break;
189 default:
190 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
191 /* if link is down, assume supported */
192 if (link_up)
193 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
194 TRUE : FALSE;
195 else
196 supported = TRUE;
197 }
198
199 break;
200 case ixgbe_media_type_backplane:
201 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI)
202 supported = FALSE;
203 else
204 supported = TRUE;
205 break;
206 case ixgbe_media_type_copper:
207 /* only some copper devices support flow control autoneg */
208 switch (hw->device_id) {
209 case IXGBE_DEV_ID_82599_T3_LOM:
210 case IXGBE_DEV_ID_X540T:
211 case IXGBE_DEV_ID_X540T1:
212 case IXGBE_DEV_ID_X540_BYPASS:
213 case IXGBE_DEV_ID_X550T:
214 case IXGBE_DEV_ID_X550T1:
215 case IXGBE_DEV_ID_X550EM_X_10G_T:
216 case IXGBE_DEV_ID_X550EM_A_10G_T:
217 case IXGBE_DEV_ID_X550EM_A_1G_T:
218 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
219 supported = TRUE;
220 break;
221 default:
222 supported = FALSE;
223 }
224 default:
225 break;
226 }
227
228 return supported;
229 }
230
231 /**
232 * ixgbe_setup_fc_generic - Set up flow control
233 * @hw: pointer to hardware structure
234 *
235 * Called at init time to set up flow control.
236 **/
ixgbe_setup_fc_generic(struct ixgbe_hw * hw)237 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
238 {
239 s32 ret_val = IXGBE_SUCCESS;
240 u32 reg = 0, reg_bp = 0;
241 u16 reg_cu = 0;
242 bool locked = FALSE;
243
244 DEBUGFUNC("ixgbe_setup_fc_generic");
245
246 /* Validate the requested mode */
247 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
248 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
249 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
250 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
251 goto out;
252 }
253
254 /*
255 * 10gig parts do not have a word in the EEPROM to determine the
256 * default flow control setting, so we explicitly set it to full.
257 */
258 if (hw->fc.requested_mode == ixgbe_fc_default)
259 hw->fc.requested_mode = ixgbe_fc_full;
260
261 /*
262 * Set up the 1G and 10G flow control advertisement registers so the
263 * HW will be able to do fc autoneg once the cable is plugged in. If
264 * we link at 10G, the 1G advertisement is harmless and vice versa.
265 */
266 switch (hw->phy.media_type) {
267 case ixgbe_media_type_backplane:
268 /* some MAC's need RMW protection on AUTOC */
269 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
270 if (ret_val != IXGBE_SUCCESS)
271 goto out;
272
273 /* fall through - only backplane uses autoc */
274 case ixgbe_media_type_fiber_fixed:
275 case ixgbe_media_type_fiber_qsfp:
276 case ixgbe_media_type_fiber:
277 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
278
279 break;
280 case ixgbe_media_type_copper:
281 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
282 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
283 break;
284 default:
285 break;
286 }
287
288 /*
289 * The possible values of fc.requested_mode are:
290 * 0: Flow control is completely disabled
291 * 1: Rx flow control is enabled (we can receive pause frames,
292 * but not send pause frames).
293 * 2: Tx flow control is enabled (we can send pause frames but
294 * we do not support receiving pause frames).
295 * 3: Both Rx and Tx flow control (symmetric) are enabled.
296 * other: Invalid.
297 */
298 switch (hw->fc.requested_mode) {
299 case ixgbe_fc_none:
300 /* Flow control completely disabled by software override. */
301 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
302 if (hw->phy.media_type == ixgbe_media_type_backplane)
303 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
304 IXGBE_AUTOC_ASM_PAUSE);
305 else if (hw->phy.media_type == ixgbe_media_type_copper)
306 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
307 break;
308 case ixgbe_fc_tx_pause:
309 /*
310 * Tx Flow control is enabled, and Rx Flow control is
311 * disabled by software override.
312 */
313 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
314 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
315 if (hw->phy.media_type == ixgbe_media_type_backplane) {
316 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
317 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
318 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
319 reg_cu |= IXGBE_TAF_ASM_PAUSE;
320 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
321 }
322 break;
323 case ixgbe_fc_rx_pause:
324 /*
325 * Rx Flow control is enabled and Tx Flow control is
326 * disabled by software override. Since there really
327 * isn't a way to advertise that we are capable of RX
328 * Pause ONLY, we will advertise that we support both
329 * symmetric and asymmetric Rx PAUSE, as such we fall
330 * through to the fc_full statement. Later, we will
331 * disable the adapter's ability to send PAUSE frames.
332 */
333 case ixgbe_fc_full:
334 /* Flow control (both Rx and Tx) is enabled by SW override. */
335 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
336 if (hw->phy.media_type == ixgbe_media_type_backplane)
337 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
338 IXGBE_AUTOC_ASM_PAUSE;
339 else if (hw->phy.media_type == ixgbe_media_type_copper)
340 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
341 break;
342 default:
343 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
344 "Flow control param set incorrectly\n");
345 ret_val = IXGBE_ERR_CONFIG;
346 goto out;
347 break;
348 }
349
350 if (hw->mac.type < ixgbe_mac_X540) {
351 /*
352 * Enable auto-negotiation between the MAC & PHY;
353 * the MAC will advertise clause 37 flow control.
354 */
355 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
356 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
357
358 /* Disable AN timeout */
359 if (hw->fc.strict_ieee)
360 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
361
362 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
363 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
364 }
365
366 /*
367 * AUTOC restart handles negotiation of 1G and 10G on backplane
368 * and copper. There is no need to set the PCS1GCTL register.
369 *
370 */
371 if (hw->phy.media_type == ixgbe_media_type_backplane) {
372 reg_bp |= IXGBE_AUTOC_AN_RESTART;
373 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
374 if (ret_val)
375 goto out;
376 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
377 (ixgbe_device_supports_autoneg_fc(hw))) {
378 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
379 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
380 }
381
382 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
383 out:
384 return ret_val;
385 }
386
387 /**
388 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
389 * @hw: pointer to hardware structure
390 *
391 * Starts the hardware by filling the bus info structure and media type, clears
392 * all on chip counters, initializes receive address registers, multicast
393 * table, VLAN filter table, calls routine to set up link and flow control
394 * settings, and leaves transmit and receive units disabled and uninitialized
395 **/
ixgbe_start_hw_generic(struct ixgbe_hw * hw)396 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
397 {
398 s32 ret_val;
399 u32 ctrl_ext;
400 u16 device_caps;
401
402 DEBUGFUNC("ixgbe_start_hw_generic");
403
404 /* Set the media type */
405 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
406
407 /* PHY ops initialization must be done in reset_hw() */
408
409 /* Clear the VLAN filter table */
410 hw->mac.ops.clear_vfta(hw);
411
412 /* Clear statistics registers */
413 hw->mac.ops.clear_hw_cntrs(hw);
414
415 /* Set No Snoop Disable */
416 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
417 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
418 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
419 IXGBE_WRITE_FLUSH(hw);
420
421 /* Setup flow control */
422 ret_val = ixgbe_setup_fc(hw);
423 if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED) {
424 DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val);
425 return ret_val;
426 }
427
428 /* Cache bit indicating need for crosstalk fix */
429 switch (hw->mac.type) {
430 case ixgbe_mac_82599EB:
431 case ixgbe_mac_X550EM_x:
432 case ixgbe_mac_X550EM_a:
433 hw->mac.ops.get_device_caps(hw, &device_caps);
434 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
435 hw->need_crosstalk_fix = FALSE;
436 else
437 hw->need_crosstalk_fix = TRUE;
438 break;
439 default:
440 hw->need_crosstalk_fix = FALSE;
441 break;
442 }
443
444 /* Clear adapter stopped flag */
445 hw->adapter_stopped = FALSE;
446
447 return IXGBE_SUCCESS;
448 }
449
450 /**
451 * ixgbe_start_hw_gen2 - Init sequence for common device family
452 * @hw: pointer to hw structure
453 *
454 * Performs the init sequence common to the second generation
455 * of 10 GbE devices.
456 * Devices in the second generation:
457 * 82599
458 * X540
459 **/
ixgbe_start_hw_gen2(struct ixgbe_hw * hw)460 void ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
461 {
462 u32 i;
463 u32 regval;
464
465 DEBUGFUNC("ixgbe_start_hw_gen2");
466
467 /* Clear the rate limiters */
468 for (i = 0; i < hw->mac.max_tx_queues; i++) {
469 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
470 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
471 }
472 IXGBE_WRITE_FLUSH(hw);
473
474 /* Disable relaxed ordering */
475 for (i = 0; i < hw->mac.max_tx_queues; i++) {
476 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
477 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
478 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
479 }
480
481 for (i = 0; i < hw->mac.max_rx_queues; i++) {
482 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
483 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
484 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
485 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
486 }
487 }
488
489 /**
490 * ixgbe_init_hw_generic - Generic hardware initialization
491 * @hw: pointer to hardware structure
492 *
493 * Initialize the hardware by resetting the hardware, filling the bus info
494 * structure and media type, clears all on chip counters, initializes receive
495 * address registers, multicast table, VLAN filter table, calls routine to set
496 * up link and flow control settings, and leaves transmit and receive units
497 * disabled and uninitialized
498 **/
ixgbe_init_hw_generic(struct ixgbe_hw * hw)499 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
500 {
501 s32 status;
502
503 DEBUGFUNC("ixgbe_init_hw_generic");
504
505 /* Reset the hardware */
506 status = hw->mac.ops.reset_hw(hw);
507
508 if (status == IXGBE_SUCCESS || status == IXGBE_ERR_SFP_NOT_PRESENT) {
509 /* Start the HW */
510 status = hw->mac.ops.start_hw(hw);
511 }
512
513 /* Initialize the LED link active for LED blink support */
514 if (hw->mac.ops.init_led_link_act)
515 hw->mac.ops.init_led_link_act(hw);
516
517 if (status != IXGBE_SUCCESS)
518 DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status);
519
520 return status;
521 }
522
523 /**
524 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
525 * @hw: pointer to hardware structure
526 *
527 * Clears all hardware statistics counters by reading them from the hardware
528 * Statistics counters are clear on read.
529 **/
ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw * hw)530 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
531 {
532 u16 i = 0;
533
534 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
535
536 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
537 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
538 IXGBE_READ_REG(hw, IXGBE_ERRBC);
539 IXGBE_READ_REG(hw, IXGBE_MSPDC);
540 if (hw->mac.type >= ixgbe_mac_X550)
541 IXGBE_READ_REG(hw, IXGBE_MBSDC);
542 for (i = 0; i < 8; i++)
543 IXGBE_READ_REG(hw, IXGBE_MPC(i));
544
545 IXGBE_READ_REG(hw, IXGBE_MLFC);
546 IXGBE_READ_REG(hw, IXGBE_MRFC);
547 if (hw->mac.type == ixgbe_mac_X550EM_a)
548 IXGBE_READ_REG(hw, IXGBE_LINK_DN_CNT);
549 IXGBE_READ_REG(hw, IXGBE_RLEC);
550 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
551 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
552 if (hw->mac.type >= ixgbe_mac_82599EB) {
553 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
554 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
555 } else {
556 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
557 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
558 }
559
560 for (i = 0; i < 8; i++) {
561 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
562 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
563 if (hw->mac.type >= ixgbe_mac_82599EB) {
564 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
565 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
566 } else {
567 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
568 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
569 }
570 }
571 if (hw->mac.type >= ixgbe_mac_82599EB)
572 for (i = 0; i < 8; i++)
573 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
574 IXGBE_READ_REG(hw, IXGBE_PRC64);
575 IXGBE_READ_REG(hw, IXGBE_PRC127);
576 IXGBE_READ_REG(hw, IXGBE_PRC255);
577 IXGBE_READ_REG(hw, IXGBE_PRC511);
578 IXGBE_READ_REG(hw, IXGBE_PRC1023);
579 IXGBE_READ_REG(hw, IXGBE_PRC1522);
580 IXGBE_READ_REG(hw, IXGBE_GPRC);
581 IXGBE_READ_REG(hw, IXGBE_BPRC);
582 IXGBE_READ_REG(hw, IXGBE_MPRC);
583 IXGBE_READ_REG(hw, IXGBE_GPTC);
584 IXGBE_READ_REG(hw, IXGBE_GORCL);
585 IXGBE_READ_REG(hw, IXGBE_GORCH);
586 IXGBE_READ_REG(hw, IXGBE_GOTCL);
587 IXGBE_READ_REG(hw, IXGBE_GOTCH);
588 if (hw->mac.type == ixgbe_mac_82598EB)
589 for (i = 0; i < 8; i++)
590 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
591 IXGBE_READ_REG(hw, IXGBE_RUC);
592 IXGBE_READ_REG(hw, IXGBE_RFC);
593 IXGBE_READ_REG(hw, IXGBE_ROC);
594 IXGBE_READ_REG(hw, IXGBE_RJC);
595 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
596 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
597 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
598 IXGBE_READ_REG(hw, IXGBE_TORL);
599 IXGBE_READ_REG(hw, IXGBE_TORH);
600 IXGBE_READ_REG(hw, IXGBE_TPR);
601 IXGBE_READ_REG(hw, IXGBE_TPT);
602 IXGBE_READ_REG(hw, IXGBE_PTC64);
603 IXGBE_READ_REG(hw, IXGBE_PTC127);
604 IXGBE_READ_REG(hw, IXGBE_PTC255);
605 IXGBE_READ_REG(hw, IXGBE_PTC511);
606 IXGBE_READ_REG(hw, IXGBE_PTC1023);
607 IXGBE_READ_REG(hw, IXGBE_PTC1522);
608 IXGBE_READ_REG(hw, IXGBE_MPTC);
609 IXGBE_READ_REG(hw, IXGBE_BPTC);
610 for (i = 0; i < 16; i++) {
611 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
612 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
613 if (hw->mac.type >= ixgbe_mac_82599EB) {
614 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
615 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
616 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
617 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
618 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
619 } else {
620 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
621 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
622 }
623 }
624
625 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
626 if (hw->phy.id == 0)
627 ixgbe_identify_phy(hw);
628 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
629 IXGBE_MDIO_PCS_DEV_TYPE, &i);
630 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
631 IXGBE_MDIO_PCS_DEV_TYPE, &i);
632 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
633 IXGBE_MDIO_PCS_DEV_TYPE, &i);
634 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
635 IXGBE_MDIO_PCS_DEV_TYPE, &i);
636 }
637
638 return IXGBE_SUCCESS;
639 }
640
641 /**
642 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
643 * @hw: pointer to hardware structure
644 * @pba_num: stores the part number string from the EEPROM
645 * @pba_num_size: part number string buffer length
646 *
647 * Reads the part number string from the EEPROM.
648 **/
ixgbe_read_pba_string_generic(struct ixgbe_hw * hw,u8 * pba_num,u32 pba_num_size)649 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
650 u32 pba_num_size)
651 {
652 s32 ret_val;
653 u16 data;
654 u16 pba_ptr;
655 u16 offset;
656 u16 length;
657
658 DEBUGFUNC("ixgbe_read_pba_string_generic");
659
660 if (pba_num == NULL) {
661 DEBUGOUT("PBA string buffer was null\n");
662 return IXGBE_ERR_INVALID_ARGUMENT;
663 }
664
665 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
666 if (ret_val) {
667 DEBUGOUT("NVM Read Error\n");
668 return ret_val;
669 }
670
671 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
672 if (ret_val) {
673 DEBUGOUT("NVM Read Error\n");
674 return ret_val;
675 }
676
677 /*
678 * if data is not ptr guard the PBA must be in legacy format which
679 * means pba_ptr is actually our second data word for the PBA number
680 * and we can decode it into an ascii string
681 */
682 if (data != IXGBE_PBANUM_PTR_GUARD) {
683 DEBUGOUT("NVM PBA number is not stored as string\n");
684
685 /* we will need 11 characters to store the PBA */
686 if (pba_num_size < 11) {
687 DEBUGOUT("PBA string buffer too small\n");
688 return IXGBE_ERR_NO_SPACE;
689 }
690
691 /* extract hex string from data and pba_ptr */
692 pba_num[0] = (data >> 12) & 0xF;
693 pba_num[1] = (data >> 8) & 0xF;
694 pba_num[2] = (data >> 4) & 0xF;
695 pba_num[3] = data & 0xF;
696 pba_num[4] = (pba_ptr >> 12) & 0xF;
697 pba_num[5] = (pba_ptr >> 8) & 0xF;
698 pba_num[6] = '-';
699 pba_num[7] = 0;
700 pba_num[8] = (pba_ptr >> 4) & 0xF;
701 pba_num[9] = pba_ptr & 0xF;
702
703 /* put a null character on the end of our string */
704 pba_num[10] = '\0';
705
706 /* switch all the data but the '-' to hex char */
707 for (offset = 0; offset < 10; offset++) {
708 if (pba_num[offset] < 0xA)
709 pba_num[offset] += '0';
710 else if (pba_num[offset] < 0x10)
711 pba_num[offset] += 'A' - 0xA;
712 }
713
714 return IXGBE_SUCCESS;
715 }
716
717 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
718 if (ret_val) {
719 DEBUGOUT("NVM Read Error\n");
720 return ret_val;
721 }
722
723 if (length == 0xFFFF || length == 0) {
724 DEBUGOUT("NVM PBA number section invalid length\n");
725 return IXGBE_ERR_PBA_SECTION;
726 }
727
728 /* check if pba_num buffer is big enough */
729 if (pba_num_size < (((u32)length * 2) - 1)) {
730 DEBUGOUT("PBA string buffer too small\n");
731 return IXGBE_ERR_NO_SPACE;
732 }
733
734 /* trim pba length from start of string */
735 pba_ptr++;
736 length--;
737
738 for (offset = 0; offset < length; offset++) {
739 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
740 if (ret_val) {
741 DEBUGOUT("NVM Read Error\n");
742 return ret_val;
743 }
744 pba_num[offset * 2] = (u8)(data >> 8);
745 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
746 }
747 pba_num[offset * 2] = '\0';
748
749 return IXGBE_SUCCESS;
750 }
751
752 /**
753 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
754 * @hw: pointer to hardware structure
755 * @pba_num: stores the part number from the EEPROM
756 *
757 * Reads the part number from the EEPROM.
758 **/
ixgbe_read_pba_num_generic(struct ixgbe_hw * hw,u32 * pba_num)759 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
760 {
761 s32 ret_val;
762 u16 data;
763
764 DEBUGFUNC("ixgbe_read_pba_num_generic");
765
766 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
767 if (ret_val) {
768 DEBUGOUT("NVM Read Error\n");
769 return ret_val;
770 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
771 DEBUGOUT("NVM Not supported\n");
772 return IXGBE_NOT_IMPLEMENTED;
773 }
774 *pba_num = (u32)(data << 16);
775
776 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
777 if (ret_val) {
778 DEBUGOUT("NVM Read Error\n");
779 return ret_val;
780 }
781 *pba_num |= (u32)data;
782
783 return IXGBE_SUCCESS;
784 }
785
786 /**
787 * ixgbe_read_pba_raw
788 * @hw: pointer to the HW structure
789 * @eeprom_buf: optional pointer to EEPROM image
790 * @eeprom_buf_size: size of EEPROM image in words
791 * @max_pba_block_size: PBA block size limit
792 * @pba: pointer to output PBA structure
793 *
794 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
795 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
796 *
797 **/
ixgbe_read_pba_raw(struct ixgbe_hw * hw,u16 * eeprom_buf,u32 eeprom_buf_size,u16 max_pba_block_size,struct ixgbe_pba * pba)798 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
799 u32 eeprom_buf_size, u16 max_pba_block_size,
800 struct ixgbe_pba *pba)
801 {
802 s32 ret_val;
803 u16 pba_block_size;
804
805 if (pba == NULL)
806 return IXGBE_ERR_PARAM;
807
808 if (eeprom_buf == NULL) {
809 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
810 &pba->word[0]);
811 if (ret_val)
812 return ret_val;
813 } else {
814 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
815 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
816 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
817 } else {
818 return IXGBE_ERR_PARAM;
819 }
820 }
821
822 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
823 if (pba->pba_block == NULL)
824 return IXGBE_ERR_PARAM;
825
826 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
827 eeprom_buf_size,
828 &pba_block_size);
829 if (ret_val)
830 return ret_val;
831
832 if (pba_block_size > max_pba_block_size)
833 return IXGBE_ERR_PARAM;
834
835 if (eeprom_buf == NULL) {
836 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
837 pba_block_size,
838 pba->pba_block);
839 if (ret_val)
840 return ret_val;
841 } else {
842 if (eeprom_buf_size > (u32)(pba->word[1] +
843 pba_block_size)) {
844 memcpy(pba->pba_block,
845 &eeprom_buf[pba->word[1]],
846 pba_block_size * sizeof(u16));
847 } else {
848 return IXGBE_ERR_PARAM;
849 }
850 }
851 }
852
853 return IXGBE_SUCCESS;
854 }
855
856 /**
857 * ixgbe_write_pba_raw
858 * @hw: pointer to the HW structure
859 * @eeprom_buf: optional pointer to EEPROM image
860 * @eeprom_buf_size: size of EEPROM image in words
861 * @pba: pointer to PBA structure
862 *
863 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
864 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
865 *
866 **/
ixgbe_write_pba_raw(struct ixgbe_hw * hw,u16 * eeprom_buf,u32 eeprom_buf_size,struct ixgbe_pba * pba)867 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
868 u32 eeprom_buf_size, struct ixgbe_pba *pba)
869 {
870 s32 ret_val;
871
872 if (pba == NULL)
873 return IXGBE_ERR_PARAM;
874
875 if (eeprom_buf == NULL) {
876 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
877 &pba->word[0]);
878 if (ret_val)
879 return ret_val;
880 } else {
881 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
882 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
883 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
884 } else {
885 return IXGBE_ERR_PARAM;
886 }
887 }
888
889 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
890 if (pba->pba_block == NULL)
891 return IXGBE_ERR_PARAM;
892
893 if (eeprom_buf == NULL) {
894 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
895 pba->pba_block[0],
896 pba->pba_block);
897 if (ret_val)
898 return ret_val;
899 } else {
900 if (eeprom_buf_size > (u32)(pba->word[1] +
901 pba->pba_block[0])) {
902 memcpy(&eeprom_buf[pba->word[1]],
903 pba->pba_block,
904 pba->pba_block[0] * sizeof(u16));
905 } else {
906 return IXGBE_ERR_PARAM;
907 }
908 }
909 }
910
911 return IXGBE_SUCCESS;
912 }
913
914 /**
915 * ixgbe_get_pba_block_size
916 * @hw: pointer to the HW structure
917 * @eeprom_buf: optional pointer to EEPROM image
918 * @eeprom_buf_size: size of EEPROM image in words
919 * @pba_data_size: pointer to output variable
920 *
921 * Returns the size of the PBA block in words. Function operates on EEPROM
922 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
923 * EEPROM device.
924 *
925 **/
ixgbe_get_pba_block_size(struct ixgbe_hw * hw,u16 * eeprom_buf,u32 eeprom_buf_size,u16 * pba_block_size)926 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
927 u32 eeprom_buf_size, u16 *pba_block_size)
928 {
929 s32 ret_val;
930 u16 pba_word[2];
931 u16 length;
932
933 DEBUGFUNC("ixgbe_get_pba_block_size");
934
935 if (eeprom_buf == NULL) {
936 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
937 &pba_word[0]);
938 if (ret_val)
939 return ret_val;
940 } else {
941 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
942 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
943 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
944 } else {
945 return IXGBE_ERR_PARAM;
946 }
947 }
948
949 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
950 if (eeprom_buf == NULL) {
951 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
952 &length);
953 if (ret_val)
954 return ret_val;
955 } else {
956 if (eeprom_buf_size > pba_word[1])
957 length = eeprom_buf[pba_word[1] + 0];
958 else
959 return IXGBE_ERR_PARAM;
960 }
961
962 if (length == 0xFFFF || length == 0)
963 return IXGBE_ERR_PBA_SECTION;
964 } else {
965 /* PBA number in legacy format, there is no PBA Block. */
966 length = 0;
967 }
968
969 if (pba_block_size != NULL)
970 *pba_block_size = length;
971
972 return IXGBE_SUCCESS;
973 }
974
975 /**
976 * ixgbe_get_mac_addr_generic - Generic get MAC address
977 * @hw: pointer to hardware structure
978 * @mac_addr: Adapter MAC address
979 *
980 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
981 * A reset of the adapter must be performed prior to calling this function
982 * in order for the MAC address to have been loaded from the EEPROM into RAR0
983 **/
ixgbe_get_mac_addr_generic(struct ixgbe_hw * hw,u8 * mac_addr)984 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
985 {
986 u32 rar_high;
987 u32 rar_low;
988 u16 i;
989
990 DEBUGFUNC("ixgbe_get_mac_addr_generic");
991
992 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
993 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
994
995 for (i = 0; i < 4; i++)
996 mac_addr[i] = (u8)(rar_low >> (i*8));
997
998 for (i = 0; i < 2; i++)
999 mac_addr[i+4] = (u8)(rar_high >> (i*8));
1000
1001 return IXGBE_SUCCESS;
1002 }
1003
1004 /**
1005 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
1006 * @hw: pointer to hardware structure
1007 * @link_status: the link status returned by the PCI config space
1008 *
1009 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
1010 **/
ixgbe_set_pci_config_data_generic(struct ixgbe_hw * hw,u16 link_status)1011 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
1012 {
1013 struct ixgbe_mac_info *mac = &hw->mac;
1014
1015 if (hw->bus.type == ixgbe_bus_type_unknown)
1016 hw->bus.type = ixgbe_bus_type_pci_express;
1017
1018 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
1019 case IXGBE_PCI_LINK_WIDTH_1:
1020 hw->bus.width = ixgbe_bus_width_pcie_x1;
1021 break;
1022 case IXGBE_PCI_LINK_WIDTH_2:
1023 hw->bus.width = ixgbe_bus_width_pcie_x2;
1024 break;
1025 case IXGBE_PCI_LINK_WIDTH_4:
1026 hw->bus.width = ixgbe_bus_width_pcie_x4;
1027 break;
1028 case IXGBE_PCI_LINK_WIDTH_8:
1029 hw->bus.width = ixgbe_bus_width_pcie_x8;
1030 break;
1031 default:
1032 hw->bus.width = ixgbe_bus_width_unknown;
1033 break;
1034 }
1035
1036 switch (link_status & IXGBE_PCI_LINK_SPEED) {
1037 case IXGBE_PCI_LINK_SPEED_2500:
1038 hw->bus.speed = ixgbe_bus_speed_2500;
1039 break;
1040 case IXGBE_PCI_LINK_SPEED_5000:
1041 hw->bus.speed = ixgbe_bus_speed_5000;
1042 break;
1043 case IXGBE_PCI_LINK_SPEED_8000:
1044 hw->bus.speed = ixgbe_bus_speed_8000;
1045 break;
1046 default:
1047 hw->bus.speed = ixgbe_bus_speed_unknown;
1048 break;
1049 }
1050
1051 mac->ops.set_lan_id(hw);
1052 }
1053
1054 /**
1055 * ixgbe_get_bus_info_generic - Generic set PCI bus info
1056 * @hw: pointer to hardware structure
1057 *
1058 * Gets the PCI bus info (speed, width, type) then calls helper function to
1059 * store this data within the ixgbe_hw structure.
1060 **/
ixgbe_get_bus_info_generic(struct ixgbe_hw * hw)1061 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1062 {
1063 u16 link_status;
1064
1065 DEBUGFUNC("ixgbe_get_bus_info_generic");
1066
1067 /* Get the negotiated link width and speed from PCI config space */
1068 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1069
1070 ixgbe_set_pci_config_data_generic(hw, link_status);
1071
1072 return IXGBE_SUCCESS;
1073 }
1074
1075 /**
1076 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1077 * @hw: pointer to the HW structure
1078 *
1079 * Determines the LAN function id by reading memory-mapped registers and swaps
1080 * the port value if requested, and set MAC instance for devices that share
1081 * CS4227.
1082 **/
ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw * hw)1083 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1084 {
1085 struct ixgbe_bus_info *bus = &hw->bus;
1086 u32 reg;
1087 u16 ee_ctrl_4;
1088
1089 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1090
1091 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1092 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1093 bus->lan_id = (u8)bus->func;
1094
1095 /* check for a port swap */
1096 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
1097 if (reg & IXGBE_FACTPS_LFS)
1098 bus->func ^= 0x1;
1099
1100 /* Get MAC instance from EEPROM for configuring CS4227 */
1101 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
1102 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
1103 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>
1104 IXGBE_EE_CTRL_4_INST_ID_SHIFT;
1105 }
1106 }
1107
1108 /**
1109 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1110 * @hw: pointer to hardware structure
1111 *
1112 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1113 * disables transmit and receive units. The adapter_stopped flag is used by
1114 * the shared code and drivers to determine if the adapter is in a stopped
1115 * state and should not touch the hardware.
1116 **/
ixgbe_stop_adapter_generic(struct ixgbe_hw * hw)1117 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1118 {
1119 u32 reg_val;
1120 u16 i;
1121
1122 DEBUGFUNC("ixgbe_stop_adapter_generic");
1123
1124 /*
1125 * Set the adapter_stopped flag so other driver functions stop touching
1126 * the hardware
1127 */
1128 hw->adapter_stopped = TRUE;
1129
1130 /* Disable the receive unit */
1131 ixgbe_disable_rx(hw);
1132
1133 /* Clear interrupt mask to stop interrupts from being generated */
1134 /*
1135 * XXX
1136 * This function is called in the state of both interrupt disabled
1137 * and interrupt enabled, e.g.
1138 * + interrupt disabled case:
1139 * - ixgbe_stop_locked()
1140 * - ixgbe_disable_intr() // interrupt disabled here
1141 * - ixgbe_stop_adapter()
1142 * - hw->mac.ops.stop_adapter()
1143 * == this function
1144 * + interrupt enabled case:
1145 * - ixgbe_local_timer1()
1146 * - ixgbe_init_locked()
1147 * - ixgbe_stop_adapter()
1148 * - hw->mac.ops.stop_adapter()
1149 * == this function
1150 * Therefore, it causes nest status breaking to nest the status
1151 * (that is, que->im_nest++) at all times. So, this function must
1152 * use ixgbe_ensure_disabled_intr() instead of ixgbe_disable_intr().
1153 */
1154 ixgbe_ensure_disabled_intr(hw->back);
1155
1156 /* Clear any pending interrupts, flush previous writes */
1157 IXGBE_READ_REG(hw, IXGBE_EICR);
1158
1159 /* Disable the transmit unit. Each queue must be disabled. */
1160 for (i = 0; i < hw->mac.max_tx_queues; i++)
1161 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1162
1163 /* Disable the receive unit by stopping each queue */
1164 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1165 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1166 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1167 reg_val |= IXGBE_RXDCTL_SWFLSH;
1168 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1169 }
1170
1171 /* flush all queues disables */
1172 IXGBE_WRITE_FLUSH(hw);
1173 msec_delay(2);
1174
1175 /*
1176 * Prevent the PCI-E bus from hanging by disabling PCI-E primary
1177 * access and verify no pending requests
1178 */
1179 return ixgbe_disable_pcie_primary(hw);
1180 }
1181
1182 /**
1183 * ixgbe_init_led_link_act_generic - Store the LED index link/activity.
1184 * @hw: pointer to hardware structure
1185 *
1186 * Store the index for the link active LED. This will be used to support
1187 * blinking the LED.
1188 **/
ixgbe_init_led_link_act_generic(struct ixgbe_hw * hw)1189 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw)
1190 {
1191 struct ixgbe_mac_info *mac = &hw->mac;
1192 u32 led_reg, led_mode;
1193 u8 i;
1194
1195 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1196
1197 /* Get LED link active from the LEDCTL register */
1198 for (i = 0; i < 4; i++) {
1199 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i);
1200
1201 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) ==
1202 IXGBE_LED_LINK_ACTIVE) {
1203 mac->led_link_act = i;
1204 return IXGBE_SUCCESS;
1205 }
1206 }
1207
1208 /*
1209 * If LEDCTL register does not have the LED link active set, then use
1210 * known MAC defaults.
1211 */
1212 switch (hw->mac.type) {
1213 case ixgbe_mac_X550EM_a:
1214 case ixgbe_mac_X550EM_x:
1215 mac->led_link_act = 1;
1216 break;
1217 default:
1218 mac->led_link_act = 2;
1219 }
1220 return IXGBE_SUCCESS;
1221 }
1222
1223 /**
1224 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1225 * @hw: pointer to hardware structure
1226 * @index: led number to turn on
1227 **/
ixgbe_led_on_generic(struct ixgbe_hw * hw,u32 index)1228 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1229 {
1230 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1231
1232 DEBUGFUNC("ixgbe_led_on_generic");
1233
1234 if (index > 3)
1235 return IXGBE_ERR_PARAM;
1236
1237 /* To turn on the LED, set mode to ON. */
1238 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1239 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1240 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1241 IXGBE_WRITE_FLUSH(hw);
1242
1243 return IXGBE_SUCCESS;
1244 }
1245
1246 /**
1247 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1248 * @hw: pointer to hardware structure
1249 * @index: led number to turn off
1250 **/
ixgbe_led_off_generic(struct ixgbe_hw * hw,u32 index)1251 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1252 {
1253 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1254
1255 DEBUGFUNC("ixgbe_led_off_generic");
1256
1257 if (index > 3)
1258 return IXGBE_ERR_PARAM;
1259
1260 /* To turn off the LED, set mode to OFF. */
1261 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1262 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1263 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1264 IXGBE_WRITE_FLUSH(hw);
1265
1266 return IXGBE_SUCCESS;
1267 }
1268
1269 /**
1270 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1271 * @hw: pointer to hardware structure
1272 *
1273 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1274 * ixgbe_hw struct in order to set up EEPROM access.
1275 **/
ixgbe_init_eeprom_params_generic(struct ixgbe_hw * hw)1276 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1277 {
1278 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1279 u32 eec;
1280 u16 eeprom_size;
1281
1282 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1283
1284 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1285 eeprom->type = ixgbe_eeprom_none;
1286 /* Set default semaphore delay to 10ms which is a well
1287 * tested value */
1288 eeprom->semaphore_delay = 10;
1289 /* Clear EEPROM page size, it will be initialized as needed */
1290 eeprom->word_page_size = 0;
1291
1292 /*
1293 * Check for EEPROM present first.
1294 * If not present leave as none
1295 */
1296 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1297 if (eec & IXGBE_EEC_PRES) {
1298 eeprom->type = ixgbe_eeprom_spi;
1299
1300 /*
1301 * SPI EEPROM is assumed here. This code would need to
1302 * change if a future EEPROM is not SPI.
1303 */
1304 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1305 IXGBE_EEC_SIZE_SHIFT);
1306 eeprom->word_size = 1 << (eeprom_size +
1307 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1308 }
1309
1310 if (eec & IXGBE_EEC_ADDR_SIZE)
1311 eeprom->address_bits = 16;
1312 else
1313 eeprom->address_bits = 8;
1314 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1315 "%d\n", eeprom->type, eeprom->word_size,
1316 eeprom->address_bits);
1317 }
1318
1319 return IXGBE_SUCCESS;
1320 }
1321
1322 /**
1323 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1324 * @hw: pointer to hardware structure
1325 * @offset: offset within the EEPROM to write
1326 * @words: number of word(s)
1327 * @data: 16 bit word(s) to write to EEPROM
1328 *
1329 * Reads 16 bit word(s) from EEPROM through bit-bang method
1330 **/
ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1331 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1332 u16 words, u16 *data)
1333 {
1334 s32 status = IXGBE_SUCCESS;
1335 u16 i, count;
1336
1337 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1338
1339 hw->eeprom.ops.init_params(hw);
1340
1341 if (words == 0) {
1342 status = IXGBE_ERR_INVALID_ARGUMENT;
1343 goto out;
1344 }
1345
1346 if (offset + words > hw->eeprom.word_size) {
1347 status = IXGBE_ERR_EEPROM;
1348 goto out;
1349 }
1350
1351 /*
1352 * The EEPROM page size cannot be queried from the chip. We do lazy
1353 * initialization. It is worth to do that when we write large buffer.
1354 */
1355 if ((hw->eeprom.word_page_size == 0) &&
1356 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1357 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1358
1359 /*
1360 * We cannot hold synchronization semaphores for too long
1361 * to avoid other entity starvation. However it is more efficient
1362 * to read in bursts than synchronizing access for each word.
1363 */
1364 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1365 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1366 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1367 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1368 count, &data[i]);
1369
1370 if (status != IXGBE_SUCCESS)
1371 break;
1372 }
1373
1374 out:
1375 return status;
1376 }
1377
1378 /**
1379 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1380 * @hw: pointer to hardware structure
1381 * @offset: offset within the EEPROM to be written to
1382 * @words: number of word(s)
1383 * @data: 16 bit word(s) to be written to the EEPROM
1384 *
1385 * If ixgbe_eeprom_update_checksum is not called after this function, the
1386 * EEPROM will most likely contain an invalid checksum.
1387 **/
ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1388 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1389 u16 words, u16 *data)
1390 {
1391 s32 status;
1392 u16 word;
1393 u16 page_size;
1394 u16 i;
1395 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1396
1397 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1398
1399 /* Prepare the EEPROM for writing */
1400 status = ixgbe_acquire_eeprom(hw);
1401
1402 if (status == IXGBE_SUCCESS) {
1403 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1404 ixgbe_release_eeprom(hw);
1405 status = IXGBE_ERR_EEPROM;
1406 }
1407 }
1408
1409 if (status == IXGBE_SUCCESS) {
1410 for (i = 0; i < words; i++) {
1411 ixgbe_standby_eeprom(hw);
1412
1413 /* Send the WRITE ENABLE command (8 bit opcode ) */
1414 ixgbe_shift_out_eeprom_bits(hw,
1415 IXGBE_EEPROM_WREN_OPCODE_SPI,
1416 IXGBE_EEPROM_OPCODE_BITS);
1417
1418 ixgbe_standby_eeprom(hw);
1419
1420 /*
1421 * Some SPI eeproms use the 8th address bit embedded
1422 * in the opcode
1423 */
1424 if ((hw->eeprom.address_bits == 8) &&
1425 ((offset + i) >= 128))
1426 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1427
1428 /* Send the Write command (8-bit opcode + addr) */
1429 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1430 IXGBE_EEPROM_OPCODE_BITS);
1431 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1432 hw->eeprom.address_bits);
1433
1434 page_size = hw->eeprom.word_page_size;
1435
1436 /* Send the data in burst via SPI*/
1437 do {
1438 word = data[i];
1439 word = (word >> 8) | (word << 8);
1440 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1441
1442 if (page_size == 0)
1443 break;
1444
1445 /* do not wrap around page */
1446 if (((offset + i) & (page_size - 1)) ==
1447 (page_size - 1))
1448 break;
1449 } while (++i < words);
1450
1451 ixgbe_standby_eeprom(hw);
1452 msec_delay(10);
1453 }
1454 /* Done with writing - release the EEPROM */
1455 ixgbe_release_eeprom(hw);
1456 }
1457
1458 return status;
1459 }
1460
1461 /**
1462 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1463 * @hw: pointer to hardware structure
1464 * @offset: offset within the EEPROM to be written to
1465 * @data: 16 bit word to be written to the EEPROM
1466 *
1467 * If ixgbe_eeprom_update_checksum is not called after this function, the
1468 * EEPROM will most likely contain an invalid checksum.
1469 **/
ixgbe_write_eeprom_generic(struct ixgbe_hw * hw,u16 offset,u16 data)1470 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1471 {
1472 s32 status;
1473
1474 DEBUGFUNC("ixgbe_write_eeprom_generic");
1475
1476 hw->eeprom.ops.init_params(hw);
1477
1478 if (offset >= hw->eeprom.word_size) {
1479 status = IXGBE_ERR_EEPROM;
1480 goto out;
1481 }
1482
1483 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1484
1485 out:
1486 return status;
1487 }
1488
1489 /**
1490 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1491 * @hw: pointer to hardware structure
1492 * @offset: offset within the EEPROM to be read
1493 * @data: read 16 bit words(s) from EEPROM
1494 * @words: number of word(s)
1495 *
1496 * Reads 16 bit word(s) from EEPROM through bit-bang method
1497 **/
ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1498 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1499 u16 words, u16 *data)
1500 {
1501 s32 status = IXGBE_SUCCESS;
1502 u16 i, count;
1503
1504 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1505
1506 hw->eeprom.ops.init_params(hw);
1507
1508 if (words == 0) {
1509 status = IXGBE_ERR_INVALID_ARGUMENT;
1510 goto out;
1511 }
1512
1513 if (offset + words > hw->eeprom.word_size) {
1514 status = IXGBE_ERR_EEPROM;
1515 goto out;
1516 }
1517
1518 /*
1519 * We cannot hold synchronization semaphores for too long
1520 * to avoid other entity starvation. However it is more efficient
1521 * to read in bursts than synchronizing access for each word.
1522 */
1523 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1524 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1525 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1526
1527 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1528 count, &data[i]);
1529
1530 if (status != IXGBE_SUCCESS)
1531 break;
1532 }
1533
1534 out:
1535 return status;
1536 }
1537
1538 /**
1539 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1540 * @hw: pointer to hardware structure
1541 * @offset: offset within the EEPROM to be read
1542 * @words: number of word(s)
1543 * @data: read 16 bit word(s) from EEPROM
1544 *
1545 * Reads 16 bit word(s) from EEPROM through bit-bang method
1546 **/
ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1547 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1548 u16 words, u16 *data)
1549 {
1550 s32 status;
1551 u16 word_in;
1552 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1553 u16 i;
1554
1555 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1556
1557 /* Prepare the EEPROM for reading */
1558 status = ixgbe_acquire_eeprom(hw);
1559
1560 if (status == IXGBE_SUCCESS) {
1561 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1562 ixgbe_release_eeprom(hw);
1563 status = IXGBE_ERR_EEPROM;
1564 }
1565 }
1566
1567 if (status == IXGBE_SUCCESS) {
1568 for (i = 0; i < words; i++) {
1569 ixgbe_standby_eeprom(hw);
1570 /*
1571 * Some SPI eeproms use the 8th address bit embedded
1572 * in the opcode
1573 */
1574 if ((hw->eeprom.address_bits == 8) &&
1575 ((offset + i) >= 128))
1576 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1577
1578 /* Send the READ command (opcode + addr) */
1579 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1580 IXGBE_EEPROM_OPCODE_BITS);
1581 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1582 hw->eeprom.address_bits);
1583
1584 /* Read the data. */
1585 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1586 data[i] = (word_in >> 8) | (word_in << 8);
1587 }
1588
1589 /* End this read operation */
1590 ixgbe_release_eeprom(hw);
1591 }
1592
1593 return status;
1594 }
1595
1596 /**
1597 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1598 * @hw: pointer to hardware structure
1599 * @offset: offset within the EEPROM to be read
1600 * @data: read 16 bit value from EEPROM
1601 *
1602 * Reads 16 bit value from EEPROM through bit-bang method
1603 **/
ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw * hw,u16 offset,u16 * data)1604 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1605 u16 *data)
1606 {
1607 s32 status;
1608
1609 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1610
1611 hw->eeprom.ops.init_params(hw);
1612
1613 if (offset >= hw->eeprom.word_size) {
1614 status = IXGBE_ERR_EEPROM;
1615 goto out;
1616 }
1617
1618 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1619
1620 out:
1621 return status;
1622 }
1623
1624 /**
1625 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1626 * @hw: pointer to hardware structure
1627 * @offset: offset of word in the EEPROM to read
1628 * @words: number of word(s)
1629 * @data: 16 bit word(s) from the EEPROM
1630 *
1631 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1632 **/
ixgbe_read_eerd_buffer_generic(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1633 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1634 u16 words, u16 *data)
1635 {
1636 u32 eerd;
1637 s32 status = IXGBE_SUCCESS;
1638 u32 i;
1639
1640 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1641
1642 hw->eeprom.ops.init_params(hw);
1643
1644 if (words == 0) {
1645 status = IXGBE_ERR_INVALID_ARGUMENT;
1646 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1647 goto out;
1648 }
1649
1650 if (offset >= hw->eeprom.word_size) {
1651 status = IXGBE_ERR_EEPROM;
1652 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1653 goto out;
1654 }
1655
1656 for (i = 0; i < words; i++) {
1657 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1658 IXGBE_EEPROM_RW_REG_START;
1659
1660 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1661 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1662
1663 if (status == IXGBE_SUCCESS) {
1664 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1665 IXGBE_EEPROM_RW_REG_DATA);
1666 } else {
1667 DEBUGOUT("Eeprom read timed out\n");
1668 goto out;
1669 }
1670 }
1671 out:
1672 return status;
1673 }
1674
1675 /**
1676 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1677 * @hw: pointer to hardware structure
1678 * @offset: offset within the EEPROM to be used as a scratch pad
1679 *
1680 * Discover EEPROM page size by writing marching data at given offset.
1681 * This function is called only when we are writing a new large buffer
1682 * at given offset so the data would be overwritten anyway.
1683 **/
ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw * hw,u16 offset)1684 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1685 u16 offset)
1686 {
1687 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1688 s32 status = IXGBE_SUCCESS;
1689 u16 i;
1690
1691 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1692
1693 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1694 data[i] = i;
1695
1696 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1697 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1698 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1699 hw->eeprom.word_page_size = 0;
1700 if (status != IXGBE_SUCCESS)
1701 goto out;
1702
1703 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1704 if (status != IXGBE_SUCCESS)
1705 goto out;
1706
1707 /*
1708 * When writing in burst more than the actual page size
1709 * EEPROM address wraps around current page.
1710 */
1711 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1712
1713 DEBUGOUT1("Detected EEPROM page size = %d words.",
1714 hw->eeprom.word_page_size);
1715 out:
1716 return status;
1717 }
1718
1719 /**
1720 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1721 * @hw: pointer to hardware structure
1722 * @offset: offset of word in the EEPROM to read
1723 * @data: word read from the EEPROM
1724 *
1725 * Reads a 16 bit word from the EEPROM using the EERD register.
1726 **/
ixgbe_read_eerd_generic(struct ixgbe_hw * hw,u16 offset,u16 * data)1727 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1728 {
1729 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1730 }
1731
1732 /**
1733 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1734 * @hw: pointer to hardware structure
1735 * @offset: offset of word in the EEPROM to write
1736 * @words: number of word(s)
1737 * @data: word(s) write to the EEPROM
1738 *
1739 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1740 **/
ixgbe_write_eewr_buffer_generic(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1741 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1742 u16 words, u16 *data)
1743 {
1744 u32 eewr;
1745 s32 status = IXGBE_SUCCESS;
1746 u16 i;
1747
1748 DEBUGFUNC("ixgbe_write_eewr_generic");
1749
1750 hw->eeprom.ops.init_params(hw);
1751
1752 if (words == 0) {
1753 status = IXGBE_ERR_INVALID_ARGUMENT;
1754 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1755 goto out;
1756 }
1757
1758 if (offset >= hw->eeprom.word_size) {
1759 status = IXGBE_ERR_EEPROM;
1760 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1761 goto out;
1762 }
1763
1764 for (i = 0; i < words; i++) {
1765 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1766 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1767 IXGBE_EEPROM_RW_REG_START;
1768
1769 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1770 if (status != IXGBE_SUCCESS) {
1771 DEBUGOUT("Eeprom write EEWR timed out\n");
1772 goto out;
1773 }
1774
1775 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1776
1777 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1778 if (status != IXGBE_SUCCESS) {
1779 DEBUGOUT("Eeprom write EEWR timed out\n");
1780 goto out;
1781 }
1782 }
1783
1784 out:
1785 return status;
1786 }
1787
1788 /**
1789 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1790 * @hw: pointer to hardware structure
1791 * @offset: offset of word in the EEPROM to write
1792 * @data: word write to the EEPROM
1793 *
1794 * Write a 16 bit word to the EEPROM using the EEWR register.
1795 **/
ixgbe_write_eewr_generic(struct ixgbe_hw * hw,u16 offset,u16 data)1796 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1797 {
1798 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1799 }
1800
1801 /**
1802 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1803 * @hw: pointer to hardware structure
1804 * @ee_reg: EEPROM flag for polling
1805 *
1806 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1807 * read or write is done respectively.
1808 **/
ixgbe_poll_eerd_eewr_done(struct ixgbe_hw * hw,u32 ee_reg)1809 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1810 {
1811 u32 i;
1812 u32 reg;
1813 s32 status = IXGBE_ERR_EEPROM;
1814
1815 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1816
1817 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1818 if (ee_reg == IXGBE_NVM_POLL_READ)
1819 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1820 else
1821 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1822
1823 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1824 status = IXGBE_SUCCESS;
1825 break;
1826 }
1827 usec_delay(5);
1828 }
1829
1830 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1831 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1832 "EEPROM read/write done polling timed out");
1833
1834 return status;
1835 }
1836
1837 /**
1838 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1839 * @hw: pointer to hardware structure
1840 *
1841 * Prepares EEPROM for access using bit-bang method. This function should
1842 * be called before issuing a command to the EEPROM.
1843 **/
ixgbe_acquire_eeprom(struct ixgbe_hw * hw)1844 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1845 {
1846 s32 status = IXGBE_SUCCESS;
1847 u32 eec;
1848 u32 i;
1849
1850 DEBUGFUNC("ixgbe_acquire_eeprom");
1851
1852 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1853 != IXGBE_SUCCESS)
1854 status = IXGBE_ERR_SWFW_SYNC;
1855
1856 if (status == IXGBE_SUCCESS) {
1857 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1858
1859 /* Request EEPROM Access */
1860 eec |= IXGBE_EEC_REQ;
1861 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1862
1863 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1864 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1865 if (eec & IXGBE_EEC_GNT)
1866 break;
1867 usec_delay(5);
1868 }
1869
1870 /* Release if grant not acquired */
1871 if (!(eec & IXGBE_EEC_GNT)) {
1872 eec &= ~IXGBE_EEC_REQ;
1873 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1874 DEBUGOUT("Could not acquire EEPROM grant\n");
1875
1876 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1877 status = IXGBE_ERR_EEPROM;
1878 }
1879
1880 /* Setup EEPROM for Read/Write */
1881 if (status == IXGBE_SUCCESS) {
1882 /* Clear CS and SK */
1883 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1884 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1885 IXGBE_WRITE_FLUSH(hw);
1886 usec_delay(1);
1887 }
1888 }
1889 return status;
1890 }
1891
1892 /**
1893 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1894 * @hw: pointer to hardware structure
1895 *
1896 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1897 **/
ixgbe_get_eeprom_semaphore(struct ixgbe_hw * hw)1898 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1899 {
1900 s32 status = IXGBE_ERR_EEPROM;
1901 u32 timeout = 2000;
1902 u32 i;
1903 u32 swsm;
1904
1905 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1906
1907 /* Get SMBI software semaphore between device drivers first */
1908 for (i = 0; i < timeout; i++) {
1909 /*
1910 * If the SMBI bit is 0 when we read it, then the bit will be
1911 * set and we have the semaphore
1912 */
1913 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1914 if (!(swsm & IXGBE_SWSM_SMBI)) {
1915 status = IXGBE_SUCCESS;
1916 break;
1917 }
1918 usec_delay(50);
1919 }
1920
1921 if (i == timeout) {
1922 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1923 "not granted.\n");
1924 /*
1925 * this release is particularly important because our attempts
1926 * above to get the semaphore may have succeeded, and if there
1927 * was a timeout, we should unconditionally clear the semaphore
1928 * bits to free the driver to make progress
1929 */
1930 ixgbe_release_eeprom_semaphore(hw);
1931
1932 usec_delay(50);
1933 /*
1934 * one last try
1935 * If the SMBI bit is 0 when we read it, then the bit will be
1936 * set and we have the semaphore
1937 */
1938 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1939 if (!(swsm & IXGBE_SWSM_SMBI))
1940 status = IXGBE_SUCCESS;
1941 }
1942
1943 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1944 if (status == IXGBE_SUCCESS) {
1945 for (i = 0; i < timeout; i++) {
1946 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1947
1948 /* Set the SW EEPROM semaphore bit to request access */
1949 swsm |= IXGBE_SWSM_SWESMBI;
1950 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
1951
1952 /*
1953 * If we set the bit successfully then we got the
1954 * semaphore.
1955 */
1956 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1957 if (swsm & IXGBE_SWSM_SWESMBI)
1958 break;
1959
1960 usec_delay(50);
1961 }
1962
1963 /*
1964 * Release semaphores and return error if SW EEPROM semaphore
1965 * was not granted because we don't have access to the EEPROM
1966 */
1967 if (i >= timeout) {
1968 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1969 "SWESMBI Software EEPROM semaphore not granted.\n");
1970 ixgbe_release_eeprom_semaphore(hw);
1971 status = IXGBE_ERR_EEPROM;
1972 }
1973 } else {
1974 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1975 "Software semaphore SMBI between device drivers "
1976 "not granted.\n");
1977 }
1978
1979 return status;
1980 }
1981
1982 /**
1983 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1984 * @hw: pointer to hardware structure
1985 *
1986 * This function clears hardware semaphore bits.
1987 **/
ixgbe_release_eeprom_semaphore(struct ixgbe_hw * hw)1988 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1989 {
1990 u32 swsm;
1991
1992 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1993
1994 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1995
1996 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1997 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1998 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1999 IXGBE_WRITE_FLUSH(hw);
2000 }
2001
2002 /**
2003 * ixgbe_ready_eeprom - Polls for EEPROM ready
2004 * @hw: pointer to hardware structure
2005 **/
ixgbe_ready_eeprom(struct ixgbe_hw * hw)2006 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
2007 {
2008 s32 status = IXGBE_SUCCESS;
2009 u16 i;
2010 u8 spi_stat_reg;
2011
2012 DEBUGFUNC("ixgbe_ready_eeprom");
2013
2014 /*
2015 * Read "Status Register" repeatedly until the LSB is cleared. The
2016 * EEPROM will signal that the command has been completed by clearing
2017 * bit 0 of the internal status register. If it's not cleared within
2018 * 5 milliseconds, then error out.
2019 */
2020 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
2021 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
2022 IXGBE_EEPROM_OPCODE_BITS);
2023 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
2024 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
2025 break;
2026
2027 usec_delay(5);
2028 ixgbe_standby_eeprom(hw);
2029 }
2030
2031 /*
2032 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
2033 * devices (and only 0-5mSec on 5V devices)
2034 */
2035 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
2036 DEBUGOUT("SPI EEPROM Status error\n");
2037 status = IXGBE_ERR_EEPROM;
2038 }
2039
2040 return status;
2041 }
2042
2043 /**
2044 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
2045 * @hw: pointer to hardware structure
2046 **/
ixgbe_standby_eeprom(struct ixgbe_hw * hw)2047 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
2048 {
2049 u32 eec;
2050
2051 DEBUGFUNC("ixgbe_standby_eeprom");
2052
2053 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2054
2055 /* Toggle CS to flush commands */
2056 eec |= IXGBE_EEC_CS;
2057 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2058 IXGBE_WRITE_FLUSH(hw);
2059 usec_delay(1);
2060 eec &= ~IXGBE_EEC_CS;
2061 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2062 IXGBE_WRITE_FLUSH(hw);
2063 usec_delay(1);
2064 }
2065
2066 /**
2067 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
2068 * @hw: pointer to hardware structure
2069 * @data: data to send to the EEPROM
2070 * @count: number of bits to shift out
2071 **/
ixgbe_shift_out_eeprom_bits(struct ixgbe_hw * hw,u16 data,u16 count)2072 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
2073 u16 count)
2074 {
2075 u32 eec;
2076 u32 mask;
2077 u32 i;
2078
2079 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
2080
2081 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2082
2083 /*
2084 * Mask is used to shift "count" bits of "data" out to the EEPROM
2085 * one bit at a time. Determine the starting bit based on count
2086 */
2087 mask = 0x01 << (count - 1);
2088
2089 for (i = 0; i < count; i++) {
2090 /*
2091 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
2092 * "1", and then raising and then lowering the clock (the SK
2093 * bit controls the clock input to the EEPROM). A "0" is
2094 * shifted out to the EEPROM by setting "DI" to "0" and then
2095 * raising and then lowering the clock.
2096 */
2097 if (data & mask)
2098 eec |= IXGBE_EEC_DI;
2099 else
2100 eec &= ~IXGBE_EEC_DI;
2101
2102 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2103 IXGBE_WRITE_FLUSH(hw);
2104
2105 usec_delay(1);
2106
2107 ixgbe_raise_eeprom_clk(hw, &eec);
2108 ixgbe_lower_eeprom_clk(hw, &eec);
2109
2110 /*
2111 * Shift mask to signify next bit of data to shift in to the
2112 * EEPROM
2113 */
2114 mask = mask >> 1;
2115 }
2116
2117 /* We leave the "DI" bit set to "0" when we leave this routine. */
2118 eec &= ~IXGBE_EEC_DI;
2119 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2120 IXGBE_WRITE_FLUSH(hw);
2121 }
2122
2123 /**
2124 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
2125 * @hw: pointer to hardware structure
2126 * @count: number of bits to shift
2127 **/
ixgbe_shift_in_eeprom_bits(struct ixgbe_hw * hw,u16 count)2128 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2129 {
2130 u32 eec;
2131 u32 i;
2132 u16 data = 0;
2133
2134 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2135
2136 /*
2137 * In order to read a register from the EEPROM, we need to shift
2138 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2139 * the clock input to the EEPROM (setting the SK bit), and then reading
2140 * the value of the "DO" bit. During this "shifting in" process the
2141 * "DI" bit should always be clear.
2142 */
2143 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2144
2145 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2146
2147 for (i = 0; i < count; i++) {
2148 data = data << 1;
2149 ixgbe_raise_eeprom_clk(hw, &eec);
2150
2151 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2152
2153 eec &= ~(IXGBE_EEC_DI);
2154 if (eec & IXGBE_EEC_DO)
2155 data |= 1;
2156
2157 ixgbe_lower_eeprom_clk(hw, &eec);
2158 }
2159
2160 return data;
2161 }
2162
2163 /**
2164 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2165 * @hw: pointer to hardware structure
2166 * @eec: EEC register's current value
2167 **/
ixgbe_raise_eeprom_clk(struct ixgbe_hw * hw,u32 * eec)2168 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2169 {
2170 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2171
2172 /*
2173 * Raise the clock input to the EEPROM
2174 * (setting the SK bit), then delay
2175 */
2176 *eec = *eec | IXGBE_EEC_SK;
2177 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2178 IXGBE_WRITE_FLUSH(hw);
2179 usec_delay(1);
2180 }
2181
2182 /**
2183 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2184 * @hw: pointer to hardware structure
2185 * @eec: EEC's current value
2186 **/
ixgbe_lower_eeprom_clk(struct ixgbe_hw * hw,u32 * eec)2187 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2188 {
2189 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2190
2191 /*
2192 * Lower the clock input to the EEPROM (clearing the SK bit), then
2193 * delay
2194 */
2195 *eec = *eec & ~IXGBE_EEC_SK;
2196 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2197 IXGBE_WRITE_FLUSH(hw);
2198 usec_delay(1);
2199 }
2200
2201 /**
2202 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2203 * @hw: pointer to hardware structure
2204 **/
ixgbe_release_eeprom(struct ixgbe_hw * hw)2205 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2206 {
2207 u32 eec;
2208
2209 DEBUGFUNC("ixgbe_release_eeprom");
2210
2211 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2212
2213 eec |= IXGBE_EEC_CS; /* Pull CS high */
2214 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2215
2216 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2217 IXGBE_WRITE_FLUSH(hw);
2218
2219 usec_delay(1);
2220
2221 /* Stop requesting EEPROM access */
2222 eec &= ~IXGBE_EEC_REQ;
2223 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2224
2225 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2226
2227 /* Delay before attempt to obtain semaphore again to allow FW access */
2228 msec_delay(hw->eeprom.semaphore_delay);
2229 }
2230
2231 /**
2232 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2233 * @hw: pointer to hardware structure
2234 *
2235 * Returns a negative error code on error, or the 16-bit checksum
2236 **/
ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw * hw)2237 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2238 {
2239 u16 i;
2240 u16 j;
2241 u16 checksum = 0;
2242 u16 length = 0;
2243 u16 pointer = 0;
2244 u16 word = 0;
2245
2246 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2247
2248 /* Include 0x0-0x3F in the checksum */
2249 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2250 if (hw->eeprom.ops.read(hw, i, &word)) {
2251 DEBUGOUT("EEPROM read failed\n");
2252 return IXGBE_ERR_EEPROM;
2253 }
2254 checksum += word;
2255 }
2256
2257 /* Include all data from pointers except for the fw pointer */
2258 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2259 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2260 DEBUGOUT("EEPROM read failed\n");
2261 return IXGBE_ERR_EEPROM;
2262 }
2263
2264 /* If the pointer seems invalid */
2265 if (pointer == 0xFFFF || pointer == 0)
2266 continue;
2267
2268 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2269 DEBUGOUT("EEPROM read failed\n");
2270 return IXGBE_ERR_EEPROM;
2271 }
2272
2273 if (length == 0xFFFF || length == 0)
2274 continue;
2275
2276 for (j = pointer + 1; j <= pointer + length; j++) {
2277 if (hw->eeprom.ops.read(hw, j, &word)) {
2278 DEBUGOUT("EEPROM read failed\n");
2279 return IXGBE_ERR_EEPROM;
2280 }
2281 checksum += word;
2282 }
2283 }
2284
2285 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2286
2287 return (s32)checksum;
2288 }
2289
2290 /**
2291 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2292 * @hw: pointer to hardware structure
2293 * @checksum_val: calculated checksum
2294 *
2295 * Performs checksum calculation and validates the EEPROM checksum. If the
2296 * caller does not need checksum_val, the value can be NULL.
2297 **/
ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw * hw,u16 * checksum_val)2298 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2299 u16 *checksum_val)
2300 {
2301 s32 status;
2302 u16 checksum;
2303 u16 read_checksum = 0;
2304
2305 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2306
2307 /* Read the first word from the EEPROM. If this times out or fails, do
2308 * not continue or we could be in for a very long wait while every
2309 * EEPROM read fails
2310 */
2311 status = hw->eeprom.ops.read(hw, 0, &checksum);
2312 if (status) {
2313 DEBUGOUT("EEPROM read failed\n");
2314 return status;
2315 }
2316
2317 status = hw->eeprom.ops.calc_checksum(hw);
2318 if (status < 0)
2319 return status;
2320
2321 checksum = (u16)(status & 0xffff);
2322
2323 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2324 if (status) {
2325 DEBUGOUT("EEPROM read failed\n");
2326 return status;
2327 }
2328
2329 /* Verify read checksum from EEPROM is the same as
2330 * calculated checksum
2331 */
2332 if (read_checksum != checksum)
2333 status = IXGBE_ERR_EEPROM_CHECKSUM;
2334
2335 /* If the user cares, return the calculated checksum */
2336 if (checksum_val)
2337 *checksum_val = checksum;
2338
2339 return status;
2340 }
2341
2342 /**
2343 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2344 * @hw: pointer to hardware structure
2345 **/
ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw * hw)2346 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2347 {
2348 s32 status;
2349 u16 checksum;
2350
2351 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2352
2353 /* Read the first word from the EEPROM. If this times out or fails, do
2354 * not continue or we could be in for a very long wait while every
2355 * EEPROM read fails
2356 */
2357 status = hw->eeprom.ops.read(hw, 0, &checksum);
2358 if (status) {
2359 DEBUGOUT("EEPROM read failed\n");
2360 return status;
2361 }
2362
2363 status = hw->eeprom.ops.calc_checksum(hw);
2364 if (status < 0)
2365 return status;
2366
2367 checksum = (u16)(status & 0xffff);
2368
2369 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2370
2371 return status;
2372 }
2373
2374 /**
2375 * ixgbe_validate_mac_addr - Validate MAC address
2376 * @mac_addr: pointer to MAC address.
2377 *
2378 * Tests a MAC address to ensure it is a valid Individual Address.
2379 **/
ixgbe_validate_mac_addr(u8 * mac_addr)2380 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2381 {
2382 s32 status = IXGBE_SUCCESS;
2383
2384 DEBUGFUNC("ixgbe_validate_mac_addr");
2385
2386 /* Make sure it is not a multicast address */
2387 if (IXGBE_IS_MULTICAST(mac_addr)) {
2388 status = IXGBE_ERR_INVALID_MAC_ADDR;
2389 /* Not a broadcast address */
2390 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2391 status = IXGBE_ERR_INVALID_MAC_ADDR;
2392 /* Reject the zero address */
2393 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2394 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2395 status = IXGBE_ERR_INVALID_MAC_ADDR;
2396 }
2397 return status;
2398 }
2399
2400 /**
2401 * ixgbe_set_rar_generic - Set Rx address register
2402 * @hw: pointer to hardware structure
2403 * @index: Receive address register to write
2404 * @addr: Address to put into receive address register
2405 * @vmdq: VMDq "set" or "pool" index
2406 * @enable_addr: set flag that address is active
2407 *
2408 * Puts an ethernet address into a receive address register.
2409 **/
ixgbe_set_rar_generic(struct ixgbe_hw * hw,u32 index,u8 * addr,u32 vmdq,u32 enable_addr)2410 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2411 u32 enable_addr)
2412 {
2413 u32 rar_low, rar_high;
2414 u32 rar_entries = hw->mac.num_rar_entries;
2415
2416 DEBUGFUNC("ixgbe_set_rar_generic");
2417
2418 /* Make sure we are using a valid rar index range */
2419 if (index >= rar_entries) {
2420 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2421 "RAR index %d is out of range.\n", index);
2422 return IXGBE_ERR_INVALID_ARGUMENT;
2423 }
2424
2425 /* setup VMDq pool selection before this RAR gets enabled */
2426 hw->mac.ops.set_vmdq(hw, index, vmdq);
2427
2428 /*
2429 * HW expects these in little endian so we reverse the byte
2430 * order from network order (big endian) to little endian
2431 */
2432 rar_low = ((u32)addr[0] |
2433 ((u32)addr[1] << 8) |
2434 ((u32)addr[2] << 16) |
2435 ((u32)addr[3] << 24));
2436 /*
2437 * Some parts put the VMDq setting in the extra RAH bits,
2438 * so save everything except the lower 16 bits that hold part
2439 * of the address and the address valid bit.
2440 */
2441 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2442 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2443 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2444
2445 if (enable_addr != 0)
2446 rar_high |= IXGBE_RAH_AV;
2447
2448 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2449 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2450
2451 return IXGBE_SUCCESS;
2452 }
2453
2454 /**
2455 * ixgbe_clear_rar_generic - Remove Rx address register
2456 * @hw: pointer to hardware structure
2457 * @index: Receive address register to write
2458 *
2459 * Clears an ethernet address from a receive address register.
2460 **/
ixgbe_clear_rar_generic(struct ixgbe_hw * hw,u32 index)2461 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2462 {
2463 u32 rar_high;
2464 u32 rar_entries = hw->mac.num_rar_entries;
2465
2466 DEBUGFUNC("ixgbe_clear_rar_generic");
2467
2468 /* Make sure we are using a valid rar index range */
2469 if (index >= rar_entries) {
2470 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2471 "RAR index %d is out of range.\n", index);
2472 return IXGBE_ERR_INVALID_ARGUMENT;
2473 }
2474
2475 /*
2476 * Some parts put the VMDq setting in the extra RAH bits,
2477 * so save everything except the lower 16 bits that hold part
2478 * of the address and the address valid bit.
2479 */
2480 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2481 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2482
2483 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2484 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2485
2486 /* clear VMDq pool/queue selection for this RAR */
2487 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2488
2489 return IXGBE_SUCCESS;
2490 }
2491
2492 /**
2493 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2494 * @hw: pointer to hardware structure
2495 *
2496 * Places the MAC address in receive address register 0 and clears the rest
2497 * of the receive address registers. Clears the multicast table. Assumes
2498 * the receiver is in reset when the routine is called.
2499 **/
ixgbe_init_rx_addrs_generic(struct ixgbe_hw * hw)2500 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2501 {
2502 u32 i;
2503 u32 rar_entries = hw->mac.num_rar_entries;
2504
2505 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2506
2507 /*
2508 * If the current mac address is valid, assume it is a software override
2509 * to the permanent address.
2510 * Otherwise, use the permanent address from the eeprom.
2511 */
2512 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2513 IXGBE_ERR_INVALID_MAC_ADDR) {
2514 /* Get the MAC address from the RAR0 for later reference */
2515 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2516
2517 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2518 hw->mac.addr[0], hw->mac.addr[1],
2519 hw->mac.addr[2]);
2520 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2521 hw->mac.addr[4], hw->mac.addr[5]);
2522 } else {
2523 /* Setup the receive address. */
2524 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2525 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2526 hw->mac.addr[0], hw->mac.addr[1],
2527 hw->mac.addr[2]);
2528 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2529 hw->mac.addr[4], hw->mac.addr[5]);
2530
2531 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2532 }
2533
2534 /* clear VMDq pool/queue selection for RAR 0 */
2535 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2536
2537 hw->addr_ctrl.overflow_promisc = 0;
2538
2539 hw->addr_ctrl.rar_used_count = 1;
2540
2541 /* Zero out the other receive addresses. */
2542 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2543 for (i = 1; i < rar_entries; i++) {
2544 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2545 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2546 }
2547
2548 /* Clear the MTA */
2549 hw->addr_ctrl.mta_in_use = 0;
2550 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2551
2552 DEBUGOUT(" Clearing MTA\n");
2553 for (i = 0; i < hw->mac.mcft_size; i++)
2554 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2555
2556 ixgbe_init_uta_tables(hw);
2557
2558 return IXGBE_SUCCESS;
2559 }
2560
2561 /**
2562 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2563 * @hw: pointer to hardware structure
2564 * @addr: new address
2565 * @vmdq: VMDq "set" or "pool" index
2566 *
2567 * Adds it to unused receive address register or goes into promiscuous mode.
2568 **/
ixgbe_add_uc_addr(struct ixgbe_hw * hw,u8 * addr,u32 vmdq)2569 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2570 {
2571 u32 rar_entries = hw->mac.num_rar_entries;
2572 u32 rar;
2573
2574 DEBUGFUNC("ixgbe_add_uc_addr");
2575
2576 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2577 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2578
2579 /*
2580 * Place this address in the RAR if there is room,
2581 * else put the controller into promiscuous mode
2582 */
2583 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2584 rar = hw->addr_ctrl.rar_used_count;
2585 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2586 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2587 hw->addr_ctrl.rar_used_count++;
2588 } else {
2589 hw->addr_ctrl.overflow_promisc++;
2590 }
2591
2592 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2593 }
2594
2595 /**
2596 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2597 * @hw: pointer to hardware structure
2598 * @addr_list: the list of new addresses
2599 * @addr_count: number of addresses
2600 * @next: iterator function to walk the address list
2601 *
2602 * The given list replaces any existing list. Clears the secondary addrs from
2603 * receive address registers. Uses unused receive address registers for the
2604 * first secondary addresses, and falls back to promiscuous mode as needed.
2605 *
2606 * Drivers using secondary unicast addresses must set user_set_promisc when
2607 * manually putting the device into promiscuous mode.
2608 **/
ixgbe_update_uc_addr_list_generic(struct ixgbe_hw * hw,u8 * addr_list,u32 addr_count,ixgbe_mc_addr_itr next)2609 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2610 u32 addr_count, ixgbe_mc_addr_itr next)
2611 {
2612 u8 *addr;
2613 u32 i;
2614 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2615 u32 uc_addr_in_use;
2616 u32 fctrl;
2617 u32 vmdq;
2618
2619 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2620
2621 /*
2622 * Clear accounting of old secondary address list,
2623 * don't count RAR[0]
2624 */
2625 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2626 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2627 hw->addr_ctrl.overflow_promisc = 0;
2628
2629 /* Zero out the other receive addresses */
2630 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2631 for (i = 0; i < uc_addr_in_use; i++) {
2632 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2633 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2634 }
2635
2636 /* Add the new addresses */
2637 for (i = 0; i < addr_count; i++) {
2638 DEBUGOUT(" Adding the secondary addresses:\n");
2639 addr = next(hw, &addr_list, &vmdq);
2640 ixgbe_add_uc_addr(hw, addr, vmdq);
2641 }
2642
2643 if (hw->addr_ctrl.overflow_promisc) {
2644 /* enable promisc if not already in overflow or set by user */
2645 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2646 DEBUGOUT(" Entering address overflow promisc mode\n");
2647 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2648 fctrl |= IXGBE_FCTRL_UPE;
2649 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2650 }
2651 } else {
2652 /* only disable if set by overflow, not by user */
2653 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2654 DEBUGOUT(" Leaving address overflow promisc mode\n");
2655 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2656 fctrl &= ~IXGBE_FCTRL_UPE;
2657 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2658 }
2659 }
2660
2661 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2662 return IXGBE_SUCCESS;
2663 }
2664
2665 /**
2666 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2667 * @hw: pointer to hardware structure
2668 * @mc_addr: the multicast address
2669 *
2670 * Extracts the 12 bits, from a multicast address, to determine which
2671 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2672 * incoming rx multicast addresses, to determine the bit-vector to check in
2673 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2674 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2675 * to mc_filter_type.
2676 **/
ixgbe_mta_vector(struct ixgbe_hw * hw,u8 * mc_addr)2677 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2678 {
2679 u32 vector = 0;
2680
2681 DEBUGFUNC("ixgbe_mta_vector");
2682
2683 switch (hw->mac.mc_filter_type) {
2684 case 0: /* use bits [47:36] of the address */
2685 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2686 break;
2687 case 1: /* use bits [46:35] of the address */
2688 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2689 break;
2690 case 2: /* use bits [45:34] of the address */
2691 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2692 break;
2693 case 3: /* use bits [43:32] of the address */
2694 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2695 break;
2696 default: /* Invalid mc_filter_type */
2697 DEBUGOUT("MC filter type param set incorrectly\n");
2698 ASSERT(0);
2699 break;
2700 }
2701
2702 /* vector can only be 12-bits or boundary will be exceeded */
2703 vector &= 0xFFF;
2704 return vector;
2705 }
2706
2707 /**
2708 * ixgbe_set_mta - Set bit-vector in multicast table
2709 * @hw: pointer to hardware structure
2710 * @mc_addr: Multicast address
2711 *
2712 * Sets the bit-vector in the multicast table.
2713 **/
ixgbe_set_mta(struct ixgbe_hw * hw,u8 * mc_addr)2714 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2715 {
2716 u32 vector;
2717 u32 vector_bit;
2718 u32 vector_reg;
2719
2720 DEBUGFUNC("ixgbe_set_mta");
2721
2722 hw->addr_ctrl.mta_in_use++;
2723
2724 vector = ixgbe_mta_vector(hw, mc_addr);
2725 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2726
2727 /*
2728 * The MTA is a register array of 128 32-bit registers. It is treated
2729 * like an array of 4096 bits. We want to set bit
2730 * BitArray[vector_value]. So we figure out what register the bit is
2731 * in, read it, OR in the new bit, then write back the new value. The
2732 * register is determined by the upper 7 bits of the vector value and
2733 * the bit within that register are determined by the lower 5 bits of
2734 * the value.
2735 */
2736 vector_reg = (vector >> 5) & 0x7F;
2737 vector_bit = vector & 0x1F;
2738 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2739 }
2740
2741 /**
2742 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2743 * @hw: pointer to hardware structure
2744 * @mc_addr_list: the list of new multicast addresses
2745 * @mc_addr_count: number of addresses
2746 * @next: iterator function to walk the multicast address list
2747 * @clear: flag, when set clears the table beforehand
2748 *
2749 * When the clear flag is set, the given list replaces any existing list.
2750 * Hashes the given addresses into the multicast table.
2751 **/
ixgbe_update_mc_addr_list_generic(struct ixgbe_hw * hw,u8 * mc_addr_list,u32 mc_addr_count,ixgbe_mc_addr_itr next,bool clear)2752 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2753 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2754 bool clear)
2755 {
2756 u32 i;
2757 u32 vmdq;
2758
2759 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2760
2761 /*
2762 * Set the new number of MC addresses that we are being requested to
2763 * use.
2764 */
2765 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2766 hw->addr_ctrl.mta_in_use = 0;
2767
2768 /* Clear mta_shadow */
2769 if (clear) {
2770 DEBUGOUT(" Clearing MTA\n");
2771 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2772 }
2773
2774 /* Update mta_shadow */
2775 for (i = 0; i < mc_addr_count; i++) {
2776 DEBUGOUT(" Adding the multicast addresses:\n");
2777 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2778 }
2779
2780 /* Enable mta */
2781 for (i = 0; i < hw->mac.mcft_size; i++)
2782 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2783 hw->mac.mta_shadow[i]);
2784
2785 if (hw->addr_ctrl.mta_in_use > 0)
2786 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2787 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2788
2789 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2790 return IXGBE_SUCCESS;
2791 }
2792
2793 /**
2794 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2795 * @hw: pointer to hardware structure
2796 *
2797 * Enables multicast address in RAR and the use of the multicast hash table.
2798 **/
ixgbe_enable_mc_generic(struct ixgbe_hw * hw)2799 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2800 {
2801 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2802
2803 DEBUGFUNC("ixgbe_enable_mc_generic");
2804
2805 if (a->mta_in_use > 0)
2806 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2807 hw->mac.mc_filter_type);
2808
2809 return IXGBE_SUCCESS;
2810 }
2811
2812 /**
2813 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2814 * @hw: pointer to hardware structure
2815 *
2816 * Disables multicast address in RAR and the use of the multicast hash table.
2817 **/
ixgbe_disable_mc_generic(struct ixgbe_hw * hw)2818 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2819 {
2820 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2821
2822 DEBUGFUNC("ixgbe_disable_mc_generic");
2823
2824 if (a->mta_in_use > 0)
2825 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2826
2827 return IXGBE_SUCCESS;
2828 }
2829
2830 /**
2831 * ixgbe_fc_enable_generic - Enable flow control
2832 * @hw: pointer to hardware structure
2833 *
2834 * Enable flow control according to the current settings.
2835 **/
ixgbe_fc_enable_generic(struct ixgbe_hw * hw)2836 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2837 {
2838 s32 ret_val = IXGBE_SUCCESS;
2839 u32 mflcn_reg, fccfg_reg;
2840 u32 reg;
2841 u32 fcrtl, fcrth;
2842 int i;
2843
2844 DEBUGFUNC("ixgbe_fc_enable_generic");
2845
2846 /* Validate the water mark configuration */
2847 if (!hw->fc.pause_time) {
2848 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2849 goto out;
2850 }
2851
2852 /* Low water mark of zero causes XOFF floods */
2853 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2854 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2855 hw->fc.high_water[i]) {
2856 if (!hw->fc.low_water[i] ||
2857 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2858 DEBUGOUT("Invalid water mark configuration\n");
2859 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2860 goto out;
2861 }
2862 }
2863 }
2864
2865 /* Negotiate the fc mode to use */
2866 hw->mac.ops.fc_autoneg(hw);
2867
2868 /* Disable any previous flow control settings */
2869 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2870 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2871
2872 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2873 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2874
2875 /*
2876 * The possible values of fc.current_mode are:
2877 * 0: Flow control is completely disabled
2878 * 1: Rx flow control is enabled (we can receive pause frames,
2879 * but not send pause frames).
2880 * 2: Tx flow control is enabled (we can send pause frames but
2881 * we do not support receiving pause frames).
2882 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2883 * other: Invalid.
2884 */
2885 switch (hw->fc.current_mode) {
2886 case ixgbe_fc_none:
2887 /*
2888 * Flow control is disabled by software override or autoneg.
2889 * The code below will actually disable it in the HW.
2890 */
2891 break;
2892 case ixgbe_fc_rx_pause:
2893 /*
2894 * Rx Flow control is enabled and Tx Flow control is
2895 * disabled by software override. Since there really
2896 * isn't a way to advertise that we are capable of RX
2897 * Pause ONLY, we will advertise that we support both
2898 * symmetric and asymmetric Rx PAUSE. Later, we will
2899 * disable the adapter's ability to send PAUSE frames.
2900 */
2901 mflcn_reg |= IXGBE_MFLCN_RFCE;
2902 break;
2903 case ixgbe_fc_tx_pause:
2904 /*
2905 * Tx Flow control is enabled, and Rx Flow control is
2906 * disabled by software override.
2907 */
2908 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2909 break;
2910 case ixgbe_fc_full:
2911 /* Flow control (both Rx and Tx) is enabled by SW override. */
2912 mflcn_reg |= IXGBE_MFLCN_RFCE;
2913 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2914 break;
2915 default:
2916 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2917 "Flow control param set incorrectly\n");
2918 ret_val = IXGBE_ERR_CONFIG;
2919 goto out;
2920 break;
2921 }
2922
2923 /* Set 802.3x based flow control settings. */
2924 mflcn_reg |= IXGBE_MFLCN_DPF;
2925 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2926 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2927
2928
2929 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2930 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2931 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2932 hw->fc.high_water[i]) {
2933 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2934 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2935 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2936 } else {
2937 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2938 /*
2939 * In order to prevent Tx hangs when the internal Tx
2940 * switch is enabled we must set the high water mark
2941 * to the Rx packet buffer size - 24KB. This allows
2942 * the Tx switch to function even under heavy Rx
2943 * workloads.
2944 */
2945 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2946 }
2947
2948 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2949 }
2950
2951 /* Configure pause time (2 TCs per register) */
2952 reg = (u32)hw->fc.pause_time * 0x00010001;
2953 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2954 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2955
2956 /* Configure flow control refresh threshold value */
2957 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2958
2959 out:
2960 return ret_val;
2961 }
2962
2963 /**
2964 * ixgbe_negotiate_fc - Negotiate flow control
2965 * @hw: pointer to hardware structure
2966 * @adv_reg: flow control advertised settings
2967 * @lp_reg: link partner's flow control settings
2968 * @adv_sym: symmetric pause bit in advertisement
2969 * @adv_asm: asymmetric pause bit in advertisement
2970 * @lp_sym: symmetric pause bit in link partner advertisement
2971 * @lp_asm: asymmetric pause bit in link partner advertisement
2972 *
2973 * Find the intersection between advertised settings and link partner's
2974 * advertised settings
2975 **/
ixgbe_negotiate_fc(struct ixgbe_hw * hw,u32 adv_reg,u32 lp_reg,u32 adv_sym,u32 adv_asm,u32 lp_sym,u32 lp_asm)2976 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2977 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2978 {
2979 if ((!(adv_reg)) || (!(lp_reg))) {
2980 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2981 "Local or link partner's advertised flow control "
2982 "settings are NULL. Local: %x, link partner: %x\n",
2983 adv_reg, lp_reg);
2984 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2985 }
2986
2987 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2988 /*
2989 * Now we need to check if the user selected Rx ONLY
2990 * of pause frames. In this case, we had to advertise
2991 * FULL flow control because we could not advertise RX
2992 * ONLY. Hence, we must now check to see if we need to
2993 * turn OFF the TRANSMISSION of PAUSE frames.
2994 */
2995 if (hw->fc.requested_mode == ixgbe_fc_full) {
2996 hw->fc.current_mode = ixgbe_fc_full;
2997 DEBUGOUT("Flow Control = FULL.\n");
2998 } else {
2999 hw->fc.current_mode = ixgbe_fc_rx_pause;
3000 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
3001 }
3002 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
3003 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
3004 hw->fc.current_mode = ixgbe_fc_tx_pause;
3005 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
3006 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
3007 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
3008 hw->fc.current_mode = ixgbe_fc_rx_pause;
3009 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
3010 } else {
3011 hw->fc.current_mode = ixgbe_fc_none;
3012 DEBUGOUT("Flow Control = NONE.\n");
3013 }
3014 return IXGBE_SUCCESS;
3015 }
3016
3017 /**
3018 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
3019 * @hw: pointer to hardware structure
3020 *
3021 * Enable flow control according on 1 gig fiber.
3022 **/
ixgbe_fc_autoneg_fiber(struct ixgbe_hw * hw)3023 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
3024 {
3025 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
3026 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3027
3028 /*
3029 * On multispeed fiber at 1g, bail out if
3030 * - link is up but AN did not complete, or if
3031 * - link is up and AN completed but timed out
3032 */
3033
3034 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
3035 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
3036 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
3037 DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
3038 goto out;
3039 }
3040
3041 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
3042 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
3043
3044 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
3045 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
3046 IXGBE_PCS1GANA_ASM_PAUSE,
3047 IXGBE_PCS1GANA_SYM_PAUSE,
3048 IXGBE_PCS1GANA_ASM_PAUSE);
3049
3050 out:
3051 return ret_val;
3052 }
3053
3054 /**
3055 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
3056 * @hw: pointer to hardware structure
3057 *
3058 * Enable flow control according to IEEE clause 37.
3059 **/
ixgbe_fc_autoneg_backplane(struct ixgbe_hw * hw)3060 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
3061 {
3062 u32 links2, anlp1_reg, autoc_reg, links;
3063 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3064
3065 /*
3066 * On backplane, bail out if
3067 * - backplane autoneg was not completed, or if
3068 * - we are 82599 and link partner is not AN enabled
3069 */
3070 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
3071 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
3072 DEBUGOUT("Auto-Negotiation did not complete\n");
3073 goto out;
3074 }
3075
3076 if (hw->mac.type == ixgbe_mac_82599EB) {
3077 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
3078 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
3079 DEBUGOUT("Link partner is not AN enabled\n");
3080 goto out;
3081 }
3082 }
3083 /*
3084 * Read the 10g AN autoc and LP ability registers and resolve
3085 * local flow control settings accordingly
3086 */
3087 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3088 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
3089
3090 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
3091 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
3092 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
3093
3094 out:
3095 return ret_val;
3096 }
3097
3098 /**
3099 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
3100 * @hw: pointer to hardware structure
3101 *
3102 * Enable flow control according to IEEE clause 37.
3103 **/
ixgbe_fc_autoneg_copper(struct ixgbe_hw * hw)3104 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
3105 {
3106 u16 technology_ability_reg = 0;
3107 u16 lp_technology_ability_reg = 0;
3108
3109 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
3110 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3111 &technology_ability_reg);
3112 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
3113 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3114 &lp_technology_ability_reg);
3115
3116 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
3117 (u32)lp_technology_ability_reg,
3118 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
3119 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
3120 }
3121
3122 /**
3123 * ixgbe_fc_autoneg - Configure flow control
3124 * @hw: pointer to hardware structure
3125 *
3126 * Compares our advertised flow control capabilities to those advertised by
3127 * our link partner, and determines the proper flow control mode to use.
3128 **/
ixgbe_fc_autoneg(struct ixgbe_hw * hw)3129 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
3130 {
3131 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3132 ixgbe_link_speed speed;
3133 bool link_up;
3134
3135 DEBUGFUNC("ixgbe_fc_autoneg");
3136
3137 /*
3138 * AN should have completed when the cable was plugged in.
3139 * Look for reasons to bail out. Bail out if:
3140 * - FC autoneg is disabled, or if
3141 * - link is not up.
3142 */
3143 if (hw->fc.disable_fc_autoneg) {
3144 /* TODO: This should be just an informative log */
3145 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
3146 "Flow control autoneg is disabled");
3147 goto out;
3148 }
3149
3150 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
3151 if (!link_up) {
3152 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3153 goto out;
3154 }
3155
3156 switch (hw->phy.media_type) {
3157 /* Autoneg flow control on fiber adapters */
3158 case ixgbe_media_type_fiber_fixed:
3159 case ixgbe_media_type_fiber_qsfp:
3160 case ixgbe_media_type_fiber:
3161 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3162 ret_val = ixgbe_fc_autoneg_fiber(hw);
3163 break;
3164
3165 /* Autoneg flow control on backplane adapters */
3166 case ixgbe_media_type_backplane:
3167 ret_val = ixgbe_fc_autoneg_backplane(hw);
3168 break;
3169
3170 /* Autoneg flow control on copper adapters */
3171 case ixgbe_media_type_copper:
3172 if (ixgbe_device_supports_autoneg_fc(hw))
3173 ret_val = ixgbe_fc_autoneg_copper(hw);
3174 break;
3175
3176 default:
3177 break;
3178 }
3179
3180 out:
3181 if (ret_val == IXGBE_SUCCESS) {
3182 hw->fc.fc_was_autonegged = TRUE;
3183 } else {
3184 hw->fc.fc_was_autonegged = FALSE;
3185 hw->fc.current_mode = hw->fc.requested_mode;
3186 }
3187 }
3188
3189 /*
3190 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3191 * @hw: pointer to hardware structure
3192 *
3193 * System-wide timeout range is encoded in PCIe Device Control2 register.
3194 *
3195 * Add 10% to specified maximum and return the number of times to poll for
3196 * completion timeout, in units of 100 microsec. Never return less than
3197 * 800 = 80 millisec.
3198 */
ixgbe_pcie_timeout_poll(struct ixgbe_hw * hw)3199 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3200 {
3201 s16 devctl2;
3202 u32 pollcnt;
3203
3204 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3205 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3206
3207 switch (devctl2) {
3208 case IXGBE_PCIDEVCTRL2_65_130ms:
3209 pollcnt = 1300; /* 130 millisec */
3210 break;
3211 case IXGBE_PCIDEVCTRL2_260_520ms:
3212 pollcnt = 5200; /* 520 millisec */
3213 break;
3214 case IXGBE_PCIDEVCTRL2_1_2s:
3215 pollcnt = 20000; /* 2 sec */
3216 break;
3217 case IXGBE_PCIDEVCTRL2_4_8s:
3218 pollcnt = 80000; /* 8 sec */
3219 break;
3220 case IXGBE_PCIDEVCTRL2_17_34s:
3221 pollcnt = 34000; /* 34 sec */
3222 break;
3223 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3224 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3225 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3226 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3227 default:
3228 pollcnt = 800; /* 80 millisec minimum */
3229 break;
3230 }
3231
3232 /* add 10% to spec maximum */
3233 return (pollcnt * 11) / 10;
3234 }
3235
3236 /**
3237 * ixgbe_disable_pcie_primary - Disable PCI-express primary access
3238 * @hw: pointer to hardware structure
3239 *
3240 * Disables PCI-Express primary access and verifies there are no pending
3241 * requests. IXGBE_ERR_PRIMARY_REQUESTS_PENDING is returned if primary disable
3242 * bit hasn't caused the primary requests to be disabled, else IXGBE_SUCCESS
3243 * is returned signifying primary requests disabled.
3244 **/
ixgbe_disable_pcie_primary(struct ixgbe_hw * hw)3245 s32 ixgbe_disable_pcie_primary(struct ixgbe_hw *hw)
3246 {
3247 s32 status = IXGBE_SUCCESS;
3248 u32 i, poll;
3249 u16 value;
3250
3251 DEBUGFUNC("ixgbe_disable_pcie_primary");
3252
3253 /* Always set this bit to ensure any future transactions are blocked */
3254 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3255
3256 /* Exit if primary requests are blocked */
3257 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3258 IXGBE_REMOVED(hw->hw_addr))
3259 goto out;
3260
3261 /* Poll for primary request bit to clear */
3262 for (i = 0; i < IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT; i++) {
3263 usec_delay(100);
3264 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3265 goto out;
3266 }
3267
3268 /*
3269 * Two consecutive resets are required via CTRL.RST per datasheet
3270 * 5.2.5.3.2 Primary Disable. We set a flag to inform the reset routine
3271 * of this need. The first reset prevents new primary requests from
3272 * being issued by our device. We then must wait 1usec or more for any
3273 * remaining completions from the PCIe bus to trickle in, and then reset
3274 * again to clear out any effects they may have had on our device.
3275 */
3276 DEBUGOUT("GIO Primary Disable bit didn't clear - requesting resets\n");
3277 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3278
3279 if (hw->mac.type >= ixgbe_mac_X550)
3280 goto out;
3281
3282 /*
3283 * Before proceeding, make sure that the PCIe block does not have
3284 * transactions pending.
3285 */
3286 poll = ixgbe_pcie_timeout_poll(hw);
3287 for (i = 0; i < poll; i++) {
3288 usec_delay(100);
3289 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3290 if (IXGBE_REMOVED(hw->hw_addr))
3291 goto out;
3292 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3293 goto out;
3294 }
3295
3296 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3297 "PCIe transaction pending bit also did not clear.\n");
3298 status = IXGBE_ERR_PRIMARY_REQUESTS_PENDING;
3299
3300 out:
3301 return status;
3302 }
3303
3304 /**
3305 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3306 * @hw: pointer to hardware structure
3307 * @mask: Mask to specify which semaphore to acquire
3308 *
3309 * Acquires the SWFW semaphore through the GSSR register for the specified
3310 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3311 **/
ixgbe_acquire_swfw_sync(struct ixgbe_hw * hw,u32 mask)3312 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3313 {
3314 u32 gssr = 0;
3315 u32 swmask = mask;
3316 u32 fwmask = mask << 5;
3317 u32 timeout = 200;
3318 u32 i;
3319
3320 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3321
3322 for (i = 0; i < timeout; i++) {
3323 /*
3324 * SW NVM semaphore bit is used for access to all
3325 * SW_FW_SYNC bits (not just NVM)
3326 */
3327 if (ixgbe_get_eeprom_semaphore(hw))
3328 return IXGBE_ERR_SWFW_SYNC;
3329
3330 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3331 if (!(gssr & (fwmask | swmask))) {
3332 gssr |= swmask;
3333 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3334 ixgbe_release_eeprom_semaphore(hw);
3335 return IXGBE_SUCCESS;
3336 } else {
3337 /* Resource is currently in use by FW or SW */
3338 ixgbe_release_eeprom_semaphore(hw);
3339 msec_delay(5);
3340 }
3341 }
3342
3343 /* If time expired clear the bits holding the lock and retry */
3344 if (gssr & (fwmask | swmask))
3345 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3346
3347 msec_delay(5);
3348 return IXGBE_ERR_SWFW_SYNC;
3349 }
3350
3351 /**
3352 * ixgbe_release_swfw_sync - Release SWFW semaphore
3353 * @hw: pointer to hardware structure
3354 * @mask: Mask to specify which semaphore to release
3355 *
3356 * Releases the SWFW semaphore through the GSSR register for the specified
3357 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3358 **/
ixgbe_release_swfw_sync(struct ixgbe_hw * hw,u32 mask)3359 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3360 {
3361 u32 gssr;
3362 u32 swmask = mask;
3363
3364 DEBUGFUNC("ixgbe_release_swfw_sync");
3365
3366 ixgbe_get_eeprom_semaphore(hw);
3367
3368 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3369 gssr &= ~swmask;
3370 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3371
3372 ixgbe_release_eeprom_semaphore(hw);
3373 }
3374
3375 /**
3376 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3377 * @hw: pointer to hardware structure
3378 *
3379 * Stops the receive data path and waits for the HW to internally empty
3380 * the Rx security block
3381 **/
ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw * hw)3382 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3383 {
3384 #define IXGBE_MAX_SECRX_POLL 4000
3385
3386 int i;
3387 int secrxreg;
3388
3389 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3390
3391 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3392 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3393 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3394 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3395 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3396 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3397 break;
3398 else
3399 /* Use interrupt-safe sleep just in case */
3400 usec_delay(10);
3401 }
3402
3403 /* For informational purposes only */
3404 if (i >= IXGBE_MAX_SECRX_POLL)
3405 DEBUGOUT("Rx unit being enabled before security "
3406 "path fully disabled. Continuing with init.\n");
3407
3408 return IXGBE_SUCCESS;
3409 }
3410
3411 /**
3412 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3413 * @hw: pointer to hardware structure
3414 * @locked: bool to indicate whether the SW/FW lock was taken
3415 * @reg_val: Value we read from AUTOC
3416 *
3417 * The default case requires no protection so just to the register read.
3418 */
prot_autoc_read_generic(struct ixgbe_hw * hw,bool * locked,u32 * reg_val)3419 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3420 {
3421 *locked = FALSE;
3422 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3423 return IXGBE_SUCCESS;
3424 }
3425
3426 /**
3427 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3428 * @hw: pointer to hardware structure
3429 * @reg_val: value to write to AUTOC
3430 * @locked: bool to indicate whether the SW/FW lock was already taken by
3431 * previous read.
3432 *
3433 * The default case requires no protection so just to the register write.
3434 */
prot_autoc_write_generic(struct ixgbe_hw * hw,u32 reg_val,bool locked)3435 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3436 {
3437 UNREFERENCED_1PARAMETER(locked);
3438
3439 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3440 return IXGBE_SUCCESS;
3441 }
3442
3443 /**
3444 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3445 * @hw: pointer to hardware structure
3446 *
3447 * Enables the receive data path.
3448 **/
ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw * hw)3449 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3450 {
3451 u32 secrxreg;
3452
3453 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3454
3455 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3456 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3457 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3458 IXGBE_WRITE_FLUSH(hw);
3459
3460 return IXGBE_SUCCESS;
3461 }
3462
3463 /**
3464 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3465 * @hw: pointer to hardware structure
3466 * @regval: register value to write to RXCTRL
3467 *
3468 * Enables the Rx DMA unit
3469 **/
ixgbe_enable_rx_dma_generic(struct ixgbe_hw * hw,u32 regval)3470 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3471 {
3472 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3473
3474 if (regval & IXGBE_RXCTRL_RXEN)
3475 ixgbe_enable_rx(hw);
3476 else
3477 ixgbe_disable_rx(hw);
3478
3479 return IXGBE_SUCCESS;
3480 }
3481
3482 /**
3483 * ixgbe_blink_led_start_generic - Blink LED based on index.
3484 * @hw: pointer to hardware structure
3485 * @index: led number to blink
3486 **/
ixgbe_blink_led_start_generic(struct ixgbe_hw * hw,u32 index)3487 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3488 {
3489 ixgbe_link_speed speed = 0;
3490 bool link_up = 0;
3491 u32 autoc_reg = 0;
3492 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3493 s32 ret_val = IXGBE_SUCCESS;
3494 bool locked = FALSE;
3495
3496 DEBUGFUNC("ixgbe_blink_led_start_generic");
3497
3498 if (index > 3)
3499 return IXGBE_ERR_PARAM;
3500
3501 /*
3502 * Link must be up to auto-blink the LEDs;
3503 * Force it if link is down.
3504 */
3505 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
3506
3507 if (!link_up) {
3508 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3509 if (ret_val != IXGBE_SUCCESS)
3510 goto out;
3511
3512 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3513 autoc_reg |= IXGBE_AUTOC_FLU;
3514
3515 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3516 if (ret_val != IXGBE_SUCCESS)
3517 goto out;
3518
3519 IXGBE_WRITE_FLUSH(hw);
3520 msec_delay(10);
3521 }
3522
3523 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3524 led_reg |= IXGBE_LED_BLINK(index);
3525 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3526 IXGBE_WRITE_FLUSH(hw);
3527
3528 out:
3529 return ret_val;
3530 }
3531
3532 /**
3533 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3534 * @hw: pointer to hardware structure
3535 * @index: led number to stop blinking
3536 **/
ixgbe_blink_led_stop_generic(struct ixgbe_hw * hw,u32 index)3537 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3538 {
3539 u32 autoc_reg = 0;
3540 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3541 s32 ret_val = IXGBE_SUCCESS;
3542 bool locked = FALSE;
3543
3544 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3545
3546 if (index > 3)
3547 return IXGBE_ERR_PARAM;
3548
3549 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3550 if (ret_val != IXGBE_SUCCESS)
3551 goto out;
3552
3553 autoc_reg &= ~IXGBE_AUTOC_FLU;
3554 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3555
3556 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3557 if (ret_val != IXGBE_SUCCESS)
3558 goto out;
3559
3560 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3561 led_reg &= ~IXGBE_LED_BLINK(index);
3562 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3563 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3564 IXGBE_WRITE_FLUSH(hw);
3565
3566 out:
3567 return ret_val;
3568 }
3569
3570 /**
3571 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3572 * @hw: pointer to hardware structure
3573 * @san_mac_offset: SAN MAC address offset
3574 *
3575 * This function will read the EEPROM location for the SAN MAC address
3576 * pointer, and returns the value at that location. This is used in both
3577 * get and set mac_addr routines.
3578 **/
ixgbe_get_san_mac_addr_offset(struct ixgbe_hw * hw,u16 * san_mac_offset)3579 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3580 u16 *san_mac_offset)
3581 {
3582 s32 ret_val;
3583
3584 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3585
3586 /*
3587 * First read the EEPROM pointer to see if the MAC addresses are
3588 * available.
3589 */
3590 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3591 san_mac_offset);
3592 if (ret_val) {
3593 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3594 "eeprom at offset %d failed",
3595 IXGBE_SAN_MAC_ADDR_PTR);
3596 }
3597
3598 return ret_val;
3599 }
3600
3601 /**
3602 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3603 * @hw: pointer to hardware structure
3604 * @san_mac_addr: SAN MAC address
3605 *
3606 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3607 * per-port, so set_lan_id() must be called before reading the addresses.
3608 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3609 * upon for non-SFP connections, so we must call it here.
3610 **/
ixgbe_get_san_mac_addr_generic(struct ixgbe_hw * hw,u8 * san_mac_addr)3611 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3612 {
3613 u16 san_mac_data, san_mac_offset;
3614 u8 i;
3615 s32 ret_val;
3616
3617 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3618
3619 /*
3620 * First read the EEPROM pointer to see if the MAC addresses are
3621 * available. If they're not, no point in calling set_lan_id() here.
3622 */
3623 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3624 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3625 goto san_mac_addr_out;
3626
3627 /* make sure we know which port we need to program */
3628 hw->mac.ops.set_lan_id(hw);
3629 /* apply the port offset to the address offset */
3630 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3631 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3632 for (i = 0; i < 3; i++) {
3633 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3634 &san_mac_data);
3635 if (ret_val) {
3636 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3637 "eeprom read at offset %d failed",
3638 san_mac_offset);
3639 goto san_mac_addr_out;
3640 }
3641 san_mac_addr[i * 2] = (u8)(san_mac_data);
3642 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3643 san_mac_offset++;
3644 }
3645 return IXGBE_SUCCESS;
3646
3647 san_mac_addr_out:
3648 /*
3649 * No addresses available in this EEPROM. It's not an
3650 * error though, so just wipe the local address and return.
3651 */
3652 for (i = 0; i < 6; i++)
3653 san_mac_addr[i] = 0xFF;
3654 return IXGBE_SUCCESS;
3655 }
3656
3657 /**
3658 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3659 * @hw: pointer to hardware structure
3660 * @san_mac_addr: SAN MAC address
3661 *
3662 * Write a SAN MAC address to the EEPROM.
3663 **/
ixgbe_set_san_mac_addr_generic(struct ixgbe_hw * hw,u8 * san_mac_addr)3664 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3665 {
3666 s32 ret_val;
3667 u16 san_mac_data, san_mac_offset;
3668 u8 i;
3669
3670 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3671
3672 /* Look for SAN mac address pointer. If not defined, return */
3673 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3674 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3675 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3676
3677 /* Make sure we know which port we need to write */
3678 hw->mac.ops.set_lan_id(hw);
3679 /* Apply the port offset to the address offset */
3680 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3681 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3682
3683 for (i = 0; i < 3; i++) {
3684 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3685 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3686 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3687 san_mac_offset++;
3688 }
3689
3690 return IXGBE_SUCCESS;
3691 }
3692
3693 /**
3694 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3695 * @hw: pointer to hardware structure
3696 *
3697 * Read PCIe configuration space, and get the MSI-X vector count from
3698 * the capabilities table.
3699 **/
ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw * hw)3700 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3701 {
3702 u16 msix_count = 1;
3703 u16 max_msix_count;
3704 u16 pcie_offset;
3705
3706 switch (hw->mac.type) {
3707 case ixgbe_mac_82598EB:
3708 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3709 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3710 break;
3711 case ixgbe_mac_82599EB:
3712 case ixgbe_mac_X540:
3713 case ixgbe_mac_X550:
3714 case ixgbe_mac_X550EM_x:
3715 case ixgbe_mac_X550EM_a:
3716 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3717 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3718 break;
3719 default:
3720 return msix_count;
3721 }
3722
3723 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3724 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3725 if (IXGBE_REMOVED(hw->hw_addr))
3726 msix_count = 0;
3727 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3728
3729 /* MSI-X count is zero-based in HW */
3730 msix_count++;
3731
3732 if (msix_count > max_msix_count)
3733 msix_count = max_msix_count;
3734
3735 return msix_count;
3736 }
3737
3738 /**
3739 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3740 * @hw: pointer to hardware structure
3741 * @addr: Address to put into receive address register
3742 * @vmdq: VMDq pool to assign
3743 *
3744 * Puts an ethernet address into a receive address register, or
3745 * finds the rar that it is already in; adds to the pool list
3746 **/
ixgbe_insert_mac_addr_generic(struct ixgbe_hw * hw,u8 * addr,u32 vmdq)3747 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3748 {
3749 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3750 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3751 u32 rar;
3752 u32 rar_low, rar_high;
3753 u32 addr_low, addr_high;
3754
3755 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3756
3757 /* swap bytes for HW little endian */
3758 addr_low = addr[0] | (addr[1] << 8)
3759 | (addr[2] << 16)
3760 | (addr[3] << 24);
3761 addr_high = addr[4] | (addr[5] << 8);
3762
3763 /*
3764 * Either find the mac_id in rar or find the first empty space.
3765 * rar_highwater points to just after the highest currently used
3766 * rar in order to shorten the search. It grows when we add a new
3767 * rar to the top.
3768 */
3769 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3770 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3771
3772 if (((IXGBE_RAH_AV & rar_high) == 0)
3773 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3774 first_empty_rar = rar;
3775 } else if ((rar_high & 0xFFFF) == addr_high) {
3776 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3777 if (rar_low == addr_low)
3778 break; /* found it already in the rars */
3779 }
3780 }
3781
3782 if (rar < hw->mac.rar_highwater) {
3783 /* already there so just add to the pool bits */
3784 ixgbe_set_vmdq(hw, rar, vmdq);
3785 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3786 /* stick it into first empty RAR slot we found */
3787 rar = first_empty_rar;
3788 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3789 } else if (rar == hw->mac.rar_highwater) {
3790 /* add it to the top of the list and inc the highwater mark */
3791 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3792 hw->mac.rar_highwater++;
3793 } else if (rar >= hw->mac.num_rar_entries) {
3794 return IXGBE_ERR_INVALID_MAC_ADDR;
3795 }
3796
3797 /*
3798 * If we found rar[0], make sure the default pool bit (we use pool 0)
3799 * remains cleared to be sure default pool packets will get delivered
3800 */
3801 if (rar == 0)
3802 ixgbe_clear_vmdq(hw, rar, 0);
3803
3804 return rar;
3805 }
3806
3807 /**
3808 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3809 * @hw: pointer to hardware struct
3810 * @rar: receive address register index to disassociate
3811 * @vmdq: VMDq pool index to remove from the rar
3812 **/
ixgbe_clear_vmdq_generic(struct ixgbe_hw * hw,u32 rar,u32 vmdq)3813 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3814 {
3815 u32 mpsar_lo, mpsar_hi;
3816 u32 rar_entries = hw->mac.num_rar_entries;
3817
3818 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3819
3820 /* Make sure we are using a valid rar index range */
3821 if (rar >= rar_entries) {
3822 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3823 "RAR index %d is out of range.\n", rar);
3824 return IXGBE_ERR_INVALID_ARGUMENT;
3825 }
3826
3827 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3828 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3829
3830 if (IXGBE_REMOVED(hw->hw_addr))
3831 goto done;
3832
3833 if (!mpsar_lo && !mpsar_hi)
3834 goto done;
3835
3836 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3837 if (mpsar_lo) {
3838 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3839 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3840 }
3841 if (mpsar_hi) {
3842 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3843 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3844 }
3845 } else if (vmdq < 32) {
3846 mpsar_lo &= ~(1 << vmdq);
3847 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3848 } else {
3849 mpsar_hi &= ~(1 << (vmdq - 32));
3850 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3851 }
3852
3853 /* was that the last pool using this rar? */
3854 if (mpsar_lo == 0 && mpsar_hi == 0 &&
3855 rar != 0 && rar != hw->mac.san_mac_rar_index)
3856 hw->mac.ops.clear_rar(hw, rar);
3857 done:
3858 return IXGBE_SUCCESS;
3859 }
3860
3861 /**
3862 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3863 * @hw: pointer to hardware struct
3864 * @rar: receive address register index to associate with a VMDq index
3865 * @vmdq: VMDq pool index
3866 **/
ixgbe_set_vmdq_generic(struct ixgbe_hw * hw,u32 rar,u32 vmdq)3867 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3868 {
3869 u32 mpsar;
3870 u32 rar_entries = hw->mac.num_rar_entries;
3871
3872 DEBUGFUNC("ixgbe_set_vmdq_generic");
3873
3874 /* Make sure we are using a valid rar index range */
3875 if (rar >= rar_entries) {
3876 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3877 "RAR index %d is out of range.\n", rar);
3878 return IXGBE_ERR_INVALID_ARGUMENT;
3879 }
3880
3881 if (vmdq < 32) {
3882 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3883 mpsar |= 1 << vmdq;
3884 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3885 } else {
3886 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3887 mpsar |= 1 << (vmdq - 32);
3888 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3889 }
3890 return IXGBE_SUCCESS;
3891 }
3892
3893 /**
3894 * This function should only be involved in the IOV mode.
3895 * In IOV mode, Default pool is next pool after the number of
3896 * VFs advertized and not 0.
3897 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3898 *
3899 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3900 * @hw: pointer to hardware struct
3901 * @vmdq: VMDq pool index
3902 **/
ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw * hw,u32 vmdq)3903 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3904 {
3905 u32 rar = hw->mac.san_mac_rar_index;
3906
3907 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3908
3909 if (vmdq < 32) {
3910 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3911 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3912 } else {
3913 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3914 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3915 }
3916
3917 return IXGBE_SUCCESS;
3918 }
3919
3920 /**
3921 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3922 * @hw: pointer to hardware structure
3923 **/
ixgbe_init_uta_tables_generic(struct ixgbe_hw * hw)3924 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3925 {
3926 int i;
3927
3928 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3929 DEBUGOUT(" Clearing UTA\n");
3930
3931 for (i = 0; i < 128; i++)
3932 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3933
3934 return IXGBE_SUCCESS;
3935 }
3936
3937 /**
3938 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3939 * @hw: pointer to hardware structure
3940 * @vlan: VLAN id to write to VLAN filter
3941 * @vlvf_bypass: TRUE to find vlanid only, FALSE returns first empty slot if
3942 * vlanid not found
3943 *
3944 *
3945 * return the VLVF index where this VLAN id should be placed
3946 *
3947 **/
ixgbe_find_vlvf_slot(struct ixgbe_hw * hw,u32 vlan,bool vlvf_bypass)3948 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
3949 {
3950 s32 regindex, first_empty_slot;
3951 u32 bits;
3952
3953 /* short cut the special case */
3954 if (vlan == 0)
3955 return 0;
3956
3957 /* if vlvf_bypass is set we don't want to use an empty slot, we
3958 * will simply bypass the VLVF if there are no entries present in the
3959 * VLVF that contain our VLAN
3960 */
3961 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0;
3962
3963 /* add VLAN enable bit for comparison */
3964 vlan |= IXGBE_VLVF_VIEN;
3965
3966 /* Search for the vlan id in the VLVF entries. Save off the first empty
3967 * slot found along the way.
3968 *
3969 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
3970 */
3971 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) {
3972 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3973 if (bits == vlan)
3974 return regindex;
3975 if (!first_empty_slot && !bits)
3976 first_empty_slot = regindex;
3977 }
3978
3979 /* If we are here then we didn't find the VLAN. Return first empty
3980 * slot we found during our search, else error.
3981 */
3982 if (!first_empty_slot)
3983 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n");
3984
3985 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE;
3986 }
3987
3988 /**
3989 * ixgbe_set_vfta_generic - Set VLAN filter table
3990 * @hw: pointer to hardware structure
3991 * @vlan: VLAN id to write to VLAN filter
3992 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
3993 * @vlan_on: boolean flag to turn on/off VLAN
3994 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3995 *
3996 * Turn on/off specified VLAN in the VLAN filter table.
3997 **/
ixgbe_set_vfta_generic(struct ixgbe_hw * hw,u32 vlan,u32 vind,bool vlan_on,bool vlvf_bypass)3998 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3999 bool vlan_on, bool vlvf_bypass)
4000 {
4001 u32 regidx, vfta_delta, vfta;
4002 s32 ret_val;
4003
4004 DEBUGFUNC("ixgbe_set_vfta_generic");
4005
4006 if (vlan > 4095 || vind > 63)
4007 return IXGBE_ERR_PARAM;
4008
4009 /*
4010 * this is a 2 part operation - first the VFTA, then the
4011 * VLVF and VLVFB if VT Mode is set
4012 * We don't write the VFTA until we know the VLVF part succeeded.
4013 */
4014
4015 /* Part 1
4016 * The VFTA is a bitstring made up of 128 32-bit registers
4017 * that enable the particular VLAN id, much like the MTA:
4018 * bits[11-5]: which register
4019 * bits[4-0]: which bit in the register
4020 */
4021 regidx = vlan / 32;
4022 vfta_delta = (u32)1 << (vlan % 32);
4023 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
4024
4025 /*
4026 * vfta_delta represents the difference between the current value
4027 * of vfta and the value we want in the register. Since the diff
4028 * is an XOR mask we can just update the vfta using an XOR
4029 */
4030 vfta_delta &= vlan_on ? ~vfta : vfta;
4031 vfta ^= vfta_delta;
4032
4033 /* Part 2
4034 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
4035 */
4036 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta,
4037 vfta, vlvf_bypass);
4038 if (ret_val != IXGBE_SUCCESS) {
4039 if (vlvf_bypass)
4040 goto vfta_update;
4041 return ret_val;
4042 }
4043
4044 vfta_update:
4045 /* Update VFTA now that we are ready for traffic */
4046 if (vfta_delta)
4047 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
4048
4049 return IXGBE_SUCCESS;
4050 }
4051
4052 /**
4053 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
4054 * @hw: pointer to hardware structure
4055 * @vlan: VLAN id to write to VLAN filter
4056 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
4057 * @vlan_on: boolean flag to turn on/off VLAN in VLVF
4058 * @vfta_delta: pointer to the difference between the current value of VFTA
4059 * and the desired value
4060 * @vfta: the desired value of the VFTA
4061 * @vlvf_bypass: boolean flag indicating updating default pool is okay
4062 *
4063 * Turn on/off specified bit in VLVF table.
4064 **/
ixgbe_set_vlvf_generic(struct ixgbe_hw * hw,u32 vlan,u32 vind,bool vlan_on,u32 * vfta_delta,u32 vfta,bool vlvf_bypass)4065 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
4066 bool vlan_on, u32 *vfta_delta, u32 vfta,
4067 bool vlvf_bypass)
4068 {
4069 u32 bits;
4070 s32 vlvf_index;
4071
4072 DEBUGFUNC("ixgbe_set_vlvf_generic");
4073
4074 if (vlan > 4095 || vind > 63)
4075 return IXGBE_ERR_PARAM;
4076
4077 /* If VT Mode is set
4078 * Either vlan_on
4079 * make sure the vlan is in VLVF
4080 * set the vind bit in the matching VLVFB
4081 * Or !vlan_on
4082 * clear the pool bit and possibly the vind
4083 */
4084 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE))
4085 return IXGBE_SUCCESS;
4086
4087 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
4088 if (vlvf_index < 0)
4089 return vlvf_index;
4090
4091 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
4092
4093 /* set the pool bit */
4094 bits |= 1 << (vind % 32);
4095 if (vlan_on)
4096 goto vlvf_update;
4097
4098 /* clear the pool bit */
4099 bits ^= 1 << (vind % 32);
4100
4101 if (!bits &&
4102 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
4103 /* Clear VFTA first, then disable VLVF. Otherwise
4104 * we run the risk of stray packets leaking into
4105 * the PF via the default pool
4106 */
4107 if (*vfta_delta)
4108 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta);
4109
4110 /* disable VLVF and clear remaining bit from pool */
4111 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4112 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0);
4113
4114 return IXGBE_SUCCESS;
4115 }
4116
4117 /* If there are still bits set in the VLVFB registers
4118 * for the VLAN ID indicated we need to see if the
4119 * caller is requesting that we clear the VFTA entry bit.
4120 * If the caller has requested that we clear the VFTA
4121 * entry bit but there are still pools/VFs using this VLAN
4122 * ID entry then ignore the request. We're not worried
4123 * about the case where we're turning the VFTA VLAN ID
4124 * entry bit on, only when requested to turn it off as
4125 * there may be multiple pools and/or VFs using the
4126 * VLAN ID entry. In that case we cannot clear the
4127 * VFTA bit until all pools/VFs using that VLAN ID have also
4128 * been cleared. This will be indicated by "bits" being
4129 * zero.
4130 */
4131 *vfta_delta = 0;
4132
4133 vlvf_update:
4134 /* record pool change and enable VLAN ID if not already enabled */
4135 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);
4136 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan);
4137
4138 return IXGBE_SUCCESS;
4139 }
4140
4141 /**
4142 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4143 * @hw: pointer to hardware structure
4144 *
4145 * Clears the VLAN filter table, and the VMDq index associated with the filter
4146 **/
ixgbe_clear_vfta_generic(struct ixgbe_hw * hw)4147 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4148 {
4149 u32 offset;
4150
4151 DEBUGFUNC("ixgbe_clear_vfta_generic");
4152
4153 for (offset = 0; offset < hw->mac.vft_size; offset++)
4154 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4155
4156 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4157 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4158 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4159 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
4160 }
4161
4162 return IXGBE_SUCCESS;
4163 }
4164
4165 /**
4166 * ixgbe_toggle_txdctl_generic - Toggle VF's queues
4167 * @hw: pointer to hardware structure
4168 * @vf_number: VF index
4169 *
4170 * Enable and disable each queue in VF.
4171 */
ixgbe_toggle_txdctl_generic(struct ixgbe_hw * hw,u32 vf_number)4172 s32 ixgbe_toggle_txdctl_generic(struct ixgbe_hw *hw, u32 vf_number)
4173 {
4174 u8 queue_count, i;
4175 u32 offset, reg;
4176
4177 if (vf_number > 63)
4178 return IXGBE_ERR_PARAM;
4179
4180 /*
4181 * Determine number of queues by checking
4182 * number of virtual functions
4183 */
4184 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4185 switch (reg & IXGBE_GCR_EXT_VT_MODE_MASK) {
4186 case IXGBE_GCR_EXT_VT_MODE_64:
4187 queue_count = 2;
4188 break;
4189 case IXGBE_GCR_EXT_VT_MODE_32:
4190 queue_count = 4;
4191 break;
4192 case IXGBE_GCR_EXT_VT_MODE_16:
4193 queue_count = 8;
4194 break;
4195 default:
4196 return IXGBE_ERR_CONFIG;
4197 }
4198
4199 /* Toggle queues */
4200 for (i = 0; i < queue_count; ++i) {
4201 /* Calculate offset of current queue */
4202 offset = queue_count * vf_number + i;
4203
4204 /* Enable queue */
4205 reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset));
4206 reg |= IXGBE_TXDCTL_ENABLE;
4207 IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg);
4208 IXGBE_WRITE_FLUSH(hw);
4209
4210 /* Disable queue */
4211 reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset));
4212 reg &= ~IXGBE_TXDCTL_ENABLE;
4213 IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg);
4214 IXGBE_WRITE_FLUSH(hw);
4215 }
4216
4217 return IXGBE_SUCCESS;
4218 }
4219
4220 /**
4221 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
4222 * @hw: pointer to hardware structure
4223 *
4224 * Contains the logic to identify if we need to verify link for the
4225 * crosstalk fix
4226 **/
ixgbe_need_crosstalk_fix(struct ixgbe_hw * hw)4227 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
4228 {
4229
4230 /* Does FW say we need the fix */
4231 if (!hw->need_crosstalk_fix)
4232 return FALSE;
4233
4234 /* Only consider SFP+ PHYs i.e. media type fiber */
4235 switch (hw->mac.ops.get_media_type(hw)) {
4236 case ixgbe_media_type_fiber:
4237 case ixgbe_media_type_fiber_qsfp:
4238 break;
4239 default:
4240 return FALSE;
4241 }
4242
4243 return TRUE;
4244 }
4245
4246 /**
4247 * ixgbe_check_mac_link_generic - Determine link and speed status
4248 * @hw: pointer to hardware structure
4249 * @speed: pointer to link speed
4250 * @link_up: TRUE when link is up
4251 * @link_up_wait_to_complete: bool used to wait for link up or not
4252 *
4253 * Reads the links register to determine if link is up and the current speed
4254 **/
ixgbe_check_mac_link_generic(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * link_up,bool link_up_wait_to_complete)4255 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4256 bool *link_up, bool link_up_wait_to_complete)
4257 {
4258 u32 links_reg, links_orig;
4259 u32 i;
4260
4261 DEBUGFUNC("ixgbe_check_mac_link_generic");
4262
4263 /* If Crosstalk fix enabled do the sanity check of making sure
4264 * the SFP+ cage is full.
4265 */
4266 if (ixgbe_need_crosstalk_fix(hw)) {
4267 if ((hw->mac.type != ixgbe_mac_82598EB) &&
4268 !ixgbe_sfp_cage_full(hw)) {
4269 *link_up = FALSE;
4270 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4271 return IXGBE_SUCCESS;
4272 }
4273 }
4274
4275 /* clear the old state */
4276 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4277
4278 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4279
4280 if (links_orig != links_reg) {
4281 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4282 links_orig, links_reg);
4283 }
4284
4285 if (link_up_wait_to_complete) {
4286 for (i = 0; i < hw->mac.max_link_up_time; i++) {
4287 if (links_reg & IXGBE_LINKS_UP) {
4288 *link_up = TRUE;
4289 break;
4290 } else {
4291 *link_up = FALSE;
4292 }
4293 msec_delay(100);
4294 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4295 }
4296 } else {
4297 if (links_reg & IXGBE_LINKS_UP) {
4298 if (ixgbe_need_crosstalk_fix(hw)) {
4299 /* Check the link state again after a delay
4300 * to filter out spurious link up
4301 * notifications.
4302 */
4303 msec_delay(5);
4304 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4305 if (!(links_reg & IXGBE_LINKS_UP)) {
4306 *link_up = false;
4307 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4308 return IXGBE_SUCCESS;
4309 }
4310
4311 }
4312 *link_up = TRUE;
4313 } else {
4314 *link_up = FALSE;
4315 }
4316 }
4317
4318 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4319 case IXGBE_LINKS_SPEED_10G_82599:
4320 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4321 if (hw->mac.type >= ixgbe_mac_X550) {
4322 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4323 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4324 }
4325 break;
4326 case IXGBE_LINKS_SPEED_1G_82599:
4327 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4328 break;
4329 case IXGBE_LINKS_SPEED_100_82599:
4330 *speed = IXGBE_LINK_SPEED_100_FULL;
4331 if (hw->mac.type >= ixgbe_mac_X550) {
4332 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4333 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4334 }
4335 break;
4336 case IXGBE_LINKS_SPEED_10_X550EM_A:
4337 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4338 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4339 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4340 *speed = IXGBE_LINK_SPEED_10_FULL;
4341 break;
4342 default:
4343 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4344 }
4345
4346 return IXGBE_SUCCESS;
4347 }
4348
4349 /**
4350 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4351 * the EEPROM
4352 * @hw: pointer to hardware structure
4353 * @wwnn_prefix: the alternative WWNN prefix
4354 * @wwpn_prefix: the alternative WWPN prefix
4355 *
4356 * This function will read the EEPROM from the alternative SAN MAC address
4357 * block to check the support for the alternative WWNN/WWPN prefix support.
4358 **/
ixgbe_get_wwn_prefix_generic(struct ixgbe_hw * hw,u16 * wwnn_prefix,u16 * wwpn_prefix)4359 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4360 u16 *wwpn_prefix)
4361 {
4362 u16 offset, caps;
4363 u16 alt_san_mac_blk_offset;
4364
4365 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4366
4367 /* clear output first */
4368 *wwnn_prefix = 0xFFFF;
4369 *wwpn_prefix = 0xFFFF;
4370
4371 /* check if alternative SAN MAC is supported */
4372 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4373 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4374 goto wwn_prefix_err;
4375
4376 if ((alt_san_mac_blk_offset == 0) ||
4377 (alt_san_mac_blk_offset == 0xFFFF))
4378 goto wwn_prefix_out;
4379
4380 /* check capability in alternative san mac address block */
4381 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4382 if (hw->eeprom.ops.read(hw, offset, &caps))
4383 goto wwn_prefix_err;
4384 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4385 goto wwn_prefix_out;
4386
4387 /* get the corresponding prefix for WWNN/WWPN */
4388 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4389 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4390 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4391 "eeprom read at offset %d failed", offset);
4392 }
4393
4394 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4395 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4396 goto wwn_prefix_err;
4397
4398 wwn_prefix_out:
4399 return IXGBE_SUCCESS;
4400
4401 wwn_prefix_err:
4402 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4403 "eeprom read at offset %d failed", offset);
4404 return IXGBE_SUCCESS;
4405 }
4406
4407 /**
4408 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4409 * @hw: pointer to hardware structure
4410 * @bs: the fcoe boot status
4411 *
4412 * This function will read the FCOE boot status from the iSCSI FCOE block
4413 **/
ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw * hw,u16 * bs)4414 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4415 {
4416 u16 offset, caps, flags;
4417 s32 status;
4418
4419 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4420
4421 /* clear output first */
4422 *bs = ixgbe_fcoe_bootstatus_unavailable;
4423
4424 /* check if FCOE IBA block is present */
4425 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4426 status = hw->eeprom.ops.read(hw, offset, &caps);
4427 if (status != IXGBE_SUCCESS)
4428 goto out;
4429
4430 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4431 goto out;
4432
4433 /* check if iSCSI FCOE block is populated */
4434 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4435 if (status != IXGBE_SUCCESS)
4436 goto out;
4437
4438 if ((offset == 0) || (offset == 0xFFFF))
4439 goto out;
4440
4441 /* read fcoe flags in iSCSI FCOE block */
4442 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4443 status = hw->eeprom.ops.read(hw, offset, &flags);
4444 if (status != IXGBE_SUCCESS)
4445 goto out;
4446
4447 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4448 *bs = ixgbe_fcoe_bootstatus_enabled;
4449 else
4450 *bs = ixgbe_fcoe_bootstatus_disabled;
4451
4452 out:
4453 return status;
4454 }
4455
4456 /**
4457 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4458 * @hw: pointer to hardware structure
4459 * @enable: enable or disable switch for MAC anti-spoofing
4460 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
4461 *
4462 **/
ixgbe_set_mac_anti_spoofing(struct ixgbe_hw * hw,bool enable,int vf)4463 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4464 {
4465 int vf_target_reg = vf >> 3;
4466 int vf_target_shift = vf % 8;
4467 u32 pfvfspoof;
4468
4469 if (hw->mac.type == ixgbe_mac_82598EB)
4470 return;
4471
4472 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4473 if (enable)
4474 pfvfspoof |= (1 << vf_target_shift);
4475 else
4476 pfvfspoof &= ~(1 << vf_target_shift);
4477 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4478 }
4479
4480 /**
4481 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4482 * @hw: pointer to hardware structure
4483 * @enable: enable or disable switch for VLAN anti-spoofing
4484 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4485 *
4486 **/
ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw * hw,bool enable,int vf)4487 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4488 {
4489 int vf_target_reg = vf >> 3;
4490 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4491 u32 pfvfspoof;
4492
4493 if (hw->mac.type == ixgbe_mac_82598EB)
4494 return;
4495
4496 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4497 if (enable)
4498 pfvfspoof |= (1 << vf_target_shift);
4499 else
4500 pfvfspoof &= ~(1 << vf_target_shift);
4501 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4502 }
4503
4504 /**
4505 * ixgbe_get_device_caps_generic - Get additional device capabilities
4506 * @hw: pointer to hardware structure
4507 * @device_caps: the EEPROM word with the extra device capabilities
4508 *
4509 * This function will read the EEPROM location for the device capabilities,
4510 * and return the word through device_caps.
4511 **/
ixgbe_get_device_caps_generic(struct ixgbe_hw * hw,u16 * device_caps)4512 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4513 {
4514 DEBUGFUNC("ixgbe_get_device_caps_generic");
4515
4516 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4517
4518 return IXGBE_SUCCESS;
4519 }
4520
4521 /**
4522 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4523 * @hw: pointer to hardware structure
4524 *
4525 **/
ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw * hw)4526 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4527 {
4528 u32 regval;
4529 u32 i;
4530
4531 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4532
4533 /* Enable relaxed ordering */
4534 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4535 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4536 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4537 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4538 }
4539
4540 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4541 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4542 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4543 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4544 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4545 }
4546
4547 }
4548
4549 /**
4550 * ixgbe_calculate_checksum - Calculate checksum for buffer
4551 * @buffer: pointer to EEPROM
4552 * @length: size of EEPROM to calculate a checksum for
4553 * Calculates the checksum for some buffer on a specified length. The
4554 * checksum calculated is returned.
4555 **/
ixgbe_calculate_checksum(u8 * buffer,u32 length)4556 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4557 {
4558 u32 i;
4559 u8 sum = 0;
4560
4561 DEBUGFUNC("ixgbe_calculate_checksum");
4562
4563 if (!buffer)
4564 return 0;
4565
4566 for (i = 0; i < length; i++)
4567 sum += buffer[i];
4568
4569 return (u8) (0 - sum);
4570 }
4571
4572 /**
4573 * ixgbe_hic_unlocked - Issue command to manageability block unlocked
4574 * @hw: pointer to the HW structure
4575 * @buffer: command to write and where the return status will be placed
4576 * @length: length of buffer, must be multiple of 4 bytes
4577 * @timeout: time in ms to wait for command completion
4578 *
4579 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4580 * else returns semaphore error when encountering an error acquiring
4581 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4582 *
4583 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held
4584 * by the caller.
4585 **/
ixgbe_hic_unlocked(struct ixgbe_hw * hw,u32 * buffer,u32 length,u32 timeout)4586 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,
4587 u32 timeout)
4588 {
4589 u32 hicr, i, fwsts;
4590 u16 dword_len;
4591
4592 DEBUGFUNC("ixgbe_hic_unlocked");
4593
4594 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4595 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4596 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4597 }
4598
4599 /* Set bit 9 of FWSTS clearing FW reset indication */
4600 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4601 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4602
4603 /* Check that the host interface is enabled. */
4604 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4605 if (!(hicr & IXGBE_HICR_EN)) {
4606 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4607 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4608 }
4609
4610 /* Calculate length in DWORDs. We must be DWORD aligned */
4611 if (length % sizeof(u32)) {
4612 DEBUGOUT("Buffer length failure, not aligned to dword");
4613 return IXGBE_ERR_INVALID_ARGUMENT;
4614 }
4615
4616 dword_len = length >> 2;
4617
4618 /* The device driver writes the relevant command block
4619 * into the ram area.
4620 */
4621 for (i = 0; i < dword_len; i++)
4622 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4623 i, IXGBE_CPU_TO_LE32(buffer[i]));
4624
4625 /* Setting this bit tells the ARC that a new command is pending. */
4626 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4627
4628 for (i = 0; i < timeout; i++) {
4629 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4630 if (!(hicr & IXGBE_HICR_C))
4631 break;
4632 msec_delay(1);
4633 }
4634
4635 /* For each command except "Apply Update" perform
4636 * status checks in the HICR registry.
4637 */
4638 if ((buffer[0] & IXGBE_HOST_INTERFACE_MASK_CMD) ==
4639 IXGBE_HOST_INTERFACE_APPLY_UPDATE_CMD)
4640 return IXGBE_SUCCESS;
4641
4642 /* Check command completion */
4643 if ((timeout && i == timeout) ||
4644 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4645 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4646 "Command has failed with no status valid.\n");
4647 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4648 }
4649
4650 return IXGBE_SUCCESS;
4651 }
4652
4653 /**
4654 * ixgbe_host_interface_command - Issue command to manageability block
4655 * @hw: pointer to the HW structure
4656 * @buffer: contains the command to write and where the return status will
4657 * be placed
4658 * @length: length of buffer, must be multiple of 4 bytes
4659 * @timeout: time in ms to wait for command completion
4660 * @return_data: read and return data from the buffer (TRUE) or not (FALSE)
4661 * Needed because FW structures are big endian and decoding of
4662 * these fields can be 8 bit or 16 bit based on command. Decoding
4663 * is not easily understood without making a table of commands.
4664 * So we will leave this up to the caller to read back the data
4665 * in these cases.
4666 *
4667 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4668 * else returns semaphore error when encountering an error acquiring
4669 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4670 **/
ixgbe_host_interface_command(struct ixgbe_hw * hw,u32 * buffer,u32 length,u32 timeout,bool return_data)4671 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4672 u32 length, u32 timeout, bool return_data)
4673 {
4674 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4675 struct ixgbe_hic_hdr *resp = (struct ixgbe_hic_hdr *)buffer;
4676 u16 buf_len;
4677 s32 status;
4678 u32 bi;
4679 u32 dword_len;
4680
4681 DEBUGFUNC("ixgbe_host_interface_command");
4682
4683 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4684 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4685 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4686 }
4687
4688 /* Take management host interface semaphore */
4689 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4690 if (status)
4691 return status;
4692
4693 status = ixgbe_hic_unlocked(hw, buffer, length, timeout);
4694 if (status)
4695 goto rel_out;
4696
4697 if (!return_data)
4698 goto rel_out;
4699
4700 /* Calculate length in DWORDs */
4701 dword_len = hdr_size >> 2;
4702
4703 /* first pull in the header so we know the buffer length */
4704 for (bi = 0; bi < dword_len; bi++) {
4705 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4706 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4707 }
4708
4709 /*
4710 * If there is any thing in data position pull it in
4711 * Read Flash command requires reading buffer length from
4712 * two bytes instead of one byte
4713 */
4714 if (resp->cmd == IXGBE_HOST_INTERFACE_FLASH_READ_CMD ||
4715 resp->cmd == IXGBE_HOST_INTERFACE_SHADOW_RAM_READ_CMD) {
4716 for (; bi < dword_len + 2; bi++) {
4717 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4718 bi);
4719 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4720 }
4721 buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3)
4722 & 0xF00) | resp->buf_len;
4723 hdr_size += (2 << 2);
4724 } else {
4725 buf_len = resp->buf_len;
4726 }
4727 if (!buf_len)
4728 goto rel_out;
4729
4730 if (length < buf_len + hdr_size) {
4731 DEBUGOUT("Buffer not large enough for reply message.\n");
4732 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4733 goto rel_out;
4734 }
4735
4736 /* Calculate length in DWORDs, add 3 for odd lengths */
4737 dword_len = (buf_len + 3) >> 2;
4738
4739 /* Pull in the rest of the buffer (bi is where we left off) */
4740 for (; bi <= dword_len; bi++) {
4741 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4742 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4743 }
4744
4745 rel_out:
4746 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4747
4748 return status;
4749 }
4750
4751 /**
4752 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4753 * @hw: pointer to the HW structure
4754 * @maj: driver version major number
4755 * @minr: driver version minor number
4756 * @build: driver version build number
4757 * @sub: driver version sub build number
4758 * @len: unused
4759 * @driver_ver: unused
4760 *
4761 * Sends driver version number to firmware through the manageability
4762 * block. On success return IXGBE_SUCCESS
4763 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4764 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4765 **/
ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw * hw,u8 maj,u8 minr,u8 build,u8 sub,u16 len,const char * driver_ver)4766 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 minr,
4767 u8 build, u8 sub, u16 len,
4768 const char *driver_ver)
4769 {
4770 struct ixgbe_hic_drv_info fw_cmd;
4771 int i;
4772 s32 ret_val = IXGBE_SUCCESS;
4773
4774 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4775 UNREFERENCED_2PARAMETER(len, driver_ver);
4776
4777 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4778 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4779 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4780 fw_cmd.port_num = (u8)hw->bus.func;
4781 fw_cmd.ver_maj = maj;
4782 fw_cmd.ver_min = minr;
4783 fw_cmd.ver_build = build;
4784 fw_cmd.ver_sub = sub;
4785 fw_cmd.hdr.checksum = 0;
4786 fw_cmd.pad = 0;
4787 fw_cmd.pad2 = 0;
4788 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4789 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4790
4791 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4792 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4793 sizeof(fw_cmd),
4794 IXGBE_HI_COMMAND_TIMEOUT,
4795 TRUE);
4796 if (ret_val != IXGBE_SUCCESS)
4797 continue;
4798
4799 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4800 FW_CEM_RESP_STATUS_SUCCESS)
4801 ret_val = IXGBE_SUCCESS;
4802 else
4803 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4804
4805 break;
4806 }
4807
4808 return ret_val;
4809 }
4810
4811 /**
4812 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4813 * @hw: pointer to hardware structure
4814 * @num_pb: number of packet buffers to allocate
4815 * @headroom: reserve n KB of headroom
4816 * @strategy: packet buffer allocation strategy
4817 **/
ixgbe_set_rxpba_generic(struct ixgbe_hw * hw,int num_pb,u32 headroom,int strategy)4818 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4819 int strategy)
4820 {
4821 u32 pbsize = hw->mac.rx_pb_size;
4822 int i = 0;
4823 u32 rxpktsize, txpktsize, txpbthresh;
4824
4825 /* Reserve headroom */
4826 pbsize -= headroom;
4827
4828 if (!num_pb)
4829 num_pb = 1;
4830
4831 /* Divide remaining packet buffer space amongst the number of packet
4832 * buffers requested using supplied strategy.
4833 */
4834 switch (strategy) {
4835 case PBA_STRATEGY_WEIGHTED:
4836 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4837 * buffer with 5/8 of the packet buffer space.
4838 */
4839 rxpktsize = (pbsize * 5) / (num_pb * 4);
4840 pbsize -= rxpktsize * (num_pb / 2);
4841 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4842 for (; i < (num_pb / 2); i++)
4843 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4844 /* fall through - configure remaining packet buffers */
4845 case PBA_STRATEGY_EQUAL:
4846 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4847 for (; i < num_pb; i++)
4848 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4849 break;
4850 default:
4851 break;
4852 }
4853
4854 /* Only support an equally distributed Tx packet buffer strategy. */
4855 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4856 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4857 for (i = 0; i < num_pb; i++) {
4858 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4859 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4860 }
4861
4862 /* Clear unused TCs, if any, to zero buffer size*/
4863 for (; i < IXGBE_MAX_PB; i++) {
4864 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4865 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4866 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4867 }
4868 }
4869
4870 /**
4871 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4872 * @hw: pointer to the hardware structure
4873 *
4874 * The 82599 and x540 MACs can experience issues if TX work is still pending
4875 * when a reset occurs. This function prevents this by flushing the PCIe
4876 * buffers on the system.
4877 **/
ixgbe_clear_tx_pending(struct ixgbe_hw * hw)4878 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4879 {
4880 u32 gcr_ext, hlreg0, i, poll;
4881 u16 value;
4882
4883 /*
4884 * If double reset is not requested then all transactions should
4885 * already be clear and as such there is no work to do
4886 */
4887 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4888 return;
4889
4890 /*
4891 * Set loopback enable to prevent any transmits from being sent
4892 * should the link come up. This assumes that the RXCTRL.RXEN bit
4893 * has already been cleared.
4894 */
4895 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4896 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4897
4898 /* Wait for a last completion before clearing buffers */
4899 IXGBE_WRITE_FLUSH(hw);
4900 msec_delay(3);
4901
4902 /*
4903 * Before proceeding, make sure that the PCIe block does not have
4904 * transactions pending.
4905 */
4906 poll = ixgbe_pcie_timeout_poll(hw);
4907 for (i = 0; i < poll; i++) {
4908 usec_delay(100);
4909 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
4910 if (IXGBE_REMOVED(hw->hw_addr))
4911 goto out;
4912 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
4913 goto out;
4914 }
4915
4916 out:
4917 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4918 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4919 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4920 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4921
4922 /* Flush all writes and allow 20usec for all transactions to clear */
4923 IXGBE_WRITE_FLUSH(hw);
4924 usec_delay(20);
4925
4926 /* restore previous register values */
4927 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4928 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4929 }
4930
4931 #define IXGBE_BYPASS_BB_WAIT 1
4932
4933 /**
4934 * ixgbe_bypass_rw_generic - Bit bang data into by_pass FW
4935 * @hw: pointer to hardware structure
4936 * @cmd: Command we send to the FW
4937 * @status: The reply from the FW
4938 *
4939 * Bit-bangs the cmd to the by_pass FW status points to what is returned.
4940 **/
ixgbe_bypass_rw_generic(struct ixgbe_hw * hw,u32 cmd,u32 * status)4941 s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status)
4942 {
4943 int i;
4944 u32 sck, sdi, sdo, dir_sck, dir_sdi, dir_sdo;
4945 u32 esdp;
4946
4947 if (!status)
4948 return IXGBE_ERR_PARAM;
4949
4950 *status = 0;
4951
4952 /* SDP vary by MAC type */
4953 switch (hw->mac.type) {
4954 case ixgbe_mac_82599EB:
4955 sck = IXGBE_ESDP_SDP7;
4956 sdi = IXGBE_ESDP_SDP0;
4957 sdo = IXGBE_ESDP_SDP6;
4958 dir_sck = IXGBE_ESDP_SDP7_DIR;
4959 dir_sdi = IXGBE_ESDP_SDP0_DIR;
4960 dir_sdo = IXGBE_ESDP_SDP6_DIR;
4961 break;
4962 case ixgbe_mac_X540:
4963 sck = IXGBE_ESDP_SDP2;
4964 sdi = IXGBE_ESDP_SDP0;
4965 sdo = IXGBE_ESDP_SDP1;
4966 dir_sck = IXGBE_ESDP_SDP2_DIR;
4967 dir_sdi = IXGBE_ESDP_SDP0_DIR;
4968 dir_sdo = IXGBE_ESDP_SDP1_DIR;
4969 break;
4970 default:
4971 return IXGBE_ERR_DEVICE_NOT_SUPPORTED;
4972 }
4973
4974 /* Set SDP pins direction */
4975 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4976 esdp |= dir_sck; /* SCK as output */
4977 esdp |= dir_sdi; /* SDI as output */
4978 esdp &= ~dir_sdo; /* SDO as input */
4979 esdp |= sck;
4980 esdp |= sdi;
4981 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4982 IXGBE_WRITE_FLUSH(hw);
4983 msec_delay(IXGBE_BYPASS_BB_WAIT);
4984
4985 /* Generate start condition */
4986 esdp &= ~sdi;
4987 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4988 IXGBE_WRITE_FLUSH(hw);
4989 msec_delay(IXGBE_BYPASS_BB_WAIT);
4990
4991 esdp &= ~sck;
4992 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4993 IXGBE_WRITE_FLUSH(hw);
4994 msec_delay(IXGBE_BYPASS_BB_WAIT);
4995
4996 /* Clock out the new control word and clock in the status */
4997 for (i = 0; i < 32; i++) {
4998 if ((cmd >> (31 - i)) & 0x01) {
4999 esdp |= sdi;
5000 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5001 } else {
5002 esdp &= ~sdi;
5003 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5004 }
5005 IXGBE_WRITE_FLUSH(hw);
5006 msec_delay(IXGBE_BYPASS_BB_WAIT);
5007
5008 esdp |= sck;
5009 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5010 IXGBE_WRITE_FLUSH(hw);
5011 msec_delay(IXGBE_BYPASS_BB_WAIT);
5012
5013 esdp &= ~sck;
5014 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5015 IXGBE_WRITE_FLUSH(hw);
5016 msec_delay(IXGBE_BYPASS_BB_WAIT);
5017
5018 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5019 if (esdp & sdo)
5020 *status = (*status << 1) | 0x01;
5021 else
5022 *status = (*status << 1) | 0x00;
5023 msec_delay(IXGBE_BYPASS_BB_WAIT);
5024 }
5025
5026 /* stop condition */
5027 esdp |= sck;
5028 esdp &= ~sdi;
5029 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5030 IXGBE_WRITE_FLUSH(hw);
5031 msec_delay(IXGBE_BYPASS_BB_WAIT);
5032
5033 esdp |= sdi;
5034 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5035 IXGBE_WRITE_FLUSH(hw);
5036
5037 /* set the page bits to match the cmd that the status it belongs to */
5038 *status = (*status & 0x3fffffff) | (cmd & 0xc0000000);
5039
5040 return IXGBE_SUCCESS;
5041 }
5042
5043 /**
5044 * ixgbe_bypass_valid_rd_generic - Verify valid return from bit-bang.
5045 * @in_reg: The register cmd for the bit-bang read.
5046 * @out_reg: The register returned from a bit-bang read.
5047 *
5048 * If we send a write we can't be sure it took until we can read back
5049 * that same register. It can be a problem as some of the fields may
5050 * for valid reasons change in-between the time wrote the register and
5051 * we read it again to verify. So this function check everything we
5052 * can check and then assumes it worked.
5053 **/
ixgbe_bypass_valid_rd_generic(u32 in_reg,u32 out_reg)5054 bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg)
5055 {
5056 u32 mask;
5057
5058 /* Page must match for all control pages */
5059 if ((in_reg & BYPASS_PAGE_M) != (out_reg & BYPASS_PAGE_M))
5060 return FALSE;
5061
5062 switch (in_reg & BYPASS_PAGE_M) {
5063 case BYPASS_PAGE_CTL0:
5064 /* All the following can't change since the last write
5065 * - All the event actions
5066 * - The timeout value
5067 */
5068 mask = BYPASS_AUX_ON_M | BYPASS_MAIN_ON_M |
5069 BYPASS_MAIN_OFF_M | BYPASS_AUX_OFF_M |
5070 BYPASS_WDTIMEOUT_M |
5071 BYPASS_WDT_VALUE_M;
5072 if ((out_reg & mask) != (in_reg & mask))
5073 return FALSE;
5074
5075 /* 0x0 is never a valid value for bypass status */
5076 if (!(out_reg & BYPASS_STATUS_OFF_M))
5077 return FALSE;
5078 break;
5079 case BYPASS_PAGE_CTL1:
5080 /* All the following can't change since the last write
5081 * - time valid bit
5082 * - time we last sent
5083 */
5084 mask = BYPASS_CTL1_VALID_M | BYPASS_CTL1_TIME_M;
5085 if ((out_reg & mask) != (in_reg & mask))
5086 return FALSE;
5087 break;
5088 case BYPASS_PAGE_CTL2:
5089 /* All we can check in this page is control number
5090 * which is already done above.
5091 */
5092 break;
5093 }
5094
5095 /* We are as sure as we can be return TRUE */
5096 return TRUE;
5097 }
5098
5099 /**
5100 * ixgbe_bypass_set_generic - Set a bypass field in the FW CTRL Register.
5101 * @hw: pointer to hardware structure
5102 * @ctrl: The control word we are setting.
5103 * @event: The event we are setting in the FW. This also happens to
5104 * be the mask for the event we are setting (handy)
5105 * @action: The action we set the event to in the FW. This is in a
5106 * bit field that happens to be what we want to put in
5107 * the event spot (also handy)
5108 **/
ixgbe_bypass_set_generic(struct ixgbe_hw * hw,u32 ctrl,u32 event,u32 action)5109 s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event,
5110 u32 action)
5111 {
5112 u32 by_ctl = 0;
5113 u32 cmd, verify;
5114 u32 count = 0;
5115
5116 /* Get current values */
5117 cmd = ctrl; /* just reading only need control number */
5118 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl))
5119 return IXGBE_ERR_INVALID_ARGUMENT;
5120
5121 /* Set to new action */
5122 cmd = (by_ctl & ~event) | BYPASS_WE | action;
5123 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl))
5124 return IXGBE_ERR_INVALID_ARGUMENT;
5125
5126 /* Page 0 force a FW eeprom write which is slow so verify */
5127 if ((cmd & BYPASS_PAGE_M) == BYPASS_PAGE_CTL0) {
5128 verify = BYPASS_PAGE_CTL0;
5129 do {
5130 if (count++ > 5)
5131 return IXGBE_BYPASS_FW_WRITE_FAILURE;
5132
5133 if (ixgbe_bypass_rw_generic(hw, verify, &by_ctl))
5134 return IXGBE_ERR_INVALID_ARGUMENT;
5135 } while (!ixgbe_bypass_valid_rd_generic(cmd, by_ctl));
5136 } else {
5137 /* We have give the FW time for the write to stick */
5138 msec_delay(100);
5139 }
5140
5141 return IXGBE_SUCCESS;
5142 }
5143
5144 /**
5145 * ixgbe_bypass_rd_eep_generic - Read the bypass FW eeprom address.
5146 *
5147 * @hw: pointer to hardware structure
5148 * @addr: The bypass eeprom address to read.
5149 * @value: The 8b of data at the address above.
5150 **/
ixgbe_bypass_rd_eep_generic(struct ixgbe_hw * hw,u32 addr,u8 * value)5151 s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value)
5152 {
5153 u32 cmd;
5154 u32 status;
5155
5156
5157 /* send the request */
5158 cmd = BYPASS_PAGE_CTL2 | BYPASS_WE;
5159 cmd |= (addr << BYPASS_CTL2_OFFSET_SHIFT) & BYPASS_CTL2_OFFSET_M;
5160 if (ixgbe_bypass_rw_generic(hw, cmd, &status))
5161 return IXGBE_ERR_INVALID_ARGUMENT;
5162
5163 /* We have give the FW time for the write to stick */
5164 msec_delay(100);
5165
5166 /* now read the results */
5167 cmd &= ~BYPASS_WE;
5168 if (ixgbe_bypass_rw_generic(hw, cmd, &status))
5169 return IXGBE_ERR_INVALID_ARGUMENT;
5170
5171 *value = status & BYPASS_CTL2_DATA_M;
5172
5173 return IXGBE_SUCCESS;
5174 }
5175
5176 /**
5177 * ixgbe_get_orom_version - Return option ROM from EEPROM
5178 *
5179 * @hw: pointer to hardware structure
5180 * @nvm_ver: pointer to output structure
5181 *
5182 * if valid option ROM version, nvm_ver->or_valid set to TRUE
5183 * else nvm_ver->or_valid is FALSE.
5184 **/
ixgbe_get_orom_version(struct ixgbe_hw * hw,struct ixgbe_nvm_version * nvm_ver)5185 void ixgbe_get_orom_version(struct ixgbe_hw *hw,
5186 struct ixgbe_nvm_version *nvm_ver)
5187 {
5188 u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl;
5189
5190 nvm_ver->or_valid = FALSE;
5191 /* Option Rom may or may not be present. Start with pointer */
5192 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset);
5193
5194 /* make sure offset is valid */
5195 if ((offset == 0x0) || (offset == NVM_INVALID_PTR))
5196 return;
5197
5198 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh);
5199 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl);
5200
5201 /* option rom exists and is valid */
5202 if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 ||
5203 eeprom_cfg_blkl == NVM_VER_INVALID ||
5204 eeprom_cfg_blkh == NVM_VER_INVALID)
5205 return;
5206
5207 nvm_ver->or_valid = TRUE;
5208 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT;
5209 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) |
5210 (eeprom_cfg_blkh >> NVM_OROM_SHIFT);
5211 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK;
5212 }
5213
5214 /**
5215 * ixgbe_get_oem_prod_version - Return OEM Product version
5216 *
5217 * @hw: pointer to hardware structure
5218 * @nvm_ver: pointer to output structure
5219 *
5220 * if valid OEM product version, nvm_ver->oem_valid set to TRUE
5221 * else nvm_ver->oem_valid is FALSE.
5222 **/
ixgbe_get_oem_prod_version(struct ixgbe_hw * hw,struct ixgbe_nvm_version * nvm_ver)5223 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,
5224 struct ixgbe_nvm_version *nvm_ver)
5225 {
5226 u16 rel_num, prod_ver, mod_len, cap, offset;
5227
5228 nvm_ver->oem_valid = FALSE;
5229 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset);
5230
5231 /* Return if offset to OEM Product Version block is invalid */
5232 if (offset == 0x0 || offset == NVM_INVALID_PTR)
5233 return;
5234
5235 /* Read product version block */
5236 hw->eeprom.ops.read(hw, offset, &mod_len);
5237 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap);
5238
5239 /* Return if OEM product version block is invalid */
5240 if (mod_len != NVM_OEM_PROD_VER_MOD_LEN ||
5241 (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0)
5242 return;
5243
5244 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver);
5245 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num);
5246
5247 /* Return if version is invalid */
5248 if ((rel_num | prod_ver) == 0x0 ||
5249 rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID)
5250 return;
5251
5252 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT;
5253 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK;
5254 nvm_ver->oem_release = rel_num;
5255 nvm_ver->oem_valid = TRUE;
5256 }
5257
5258 /**
5259 * ixgbe_get_etk_id - Return Etrack ID from EEPROM
5260 *
5261 * @hw: pointer to hardware structure
5262 * @nvm_ver: pointer to output structure
5263 *
5264 * word read errors will return 0xFFFF
5265 **/
ixgbe_get_etk_id(struct ixgbe_hw * hw,struct ixgbe_nvm_version * nvm_ver)5266 void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver)
5267 {
5268 u16 etk_id_l, etk_id_h;
5269
5270 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l))
5271 etk_id_l = NVM_VER_INVALID;
5272 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h))
5273 etk_id_h = NVM_VER_INVALID;
5274
5275 /* The word order for the version format is determined by high order
5276 * word bit 15.
5277 */
5278 if ((etk_id_h & NVM_ETK_VALID) == 0) {
5279 nvm_ver->etk_id = etk_id_h;
5280 nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT);
5281 } else {
5282 nvm_ver->etk_id = etk_id_l;
5283 nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT);
5284 }
5285 }
5286
5287
5288 /**
5289 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
5290 * @hw: pointer to hardware structure
5291 * @map: pointer to u8 arr for returning map
5292 *
5293 * Read the rtrup2tc HW register and resolve its content into map
5294 **/
ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw * hw,u8 * map)5295 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
5296 {
5297 u32 reg, i;
5298
5299 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
5300 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
5301 map[i] = IXGBE_RTRUP2TC_UP_MASK &
5302 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
5303 return;
5304 }
5305
ixgbe_disable_rx_generic(struct ixgbe_hw * hw)5306 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
5307 {
5308 u32 pfdtxgswc;
5309 u32 rxctrl;
5310
5311 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5312 if (rxctrl & IXGBE_RXCTRL_RXEN) {
5313 if (hw->mac.type != ixgbe_mac_82598EB) {
5314 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5315 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
5316 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5317 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
5318 hw->mac.set_lben = TRUE;
5319 } else {
5320 hw->mac.set_lben = FALSE;
5321 }
5322 }
5323 rxctrl &= ~IXGBE_RXCTRL_RXEN;
5324 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
5325 }
5326 }
5327
ixgbe_enable_rx_generic(struct ixgbe_hw * hw)5328 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
5329 {
5330 u32 pfdtxgswc;
5331 u32 rxctrl;
5332
5333 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5334 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
5335
5336 if (hw->mac.type != ixgbe_mac_82598EB) {
5337 if (hw->mac.set_lben) {
5338 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5339 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
5340 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
5341 hw->mac.set_lben = FALSE;
5342 }
5343 }
5344 }
5345
5346 /**
5347 * ixgbe_mng_present - returns TRUE when management capability is present
5348 * @hw: pointer to hardware structure
5349 */
ixgbe_mng_present(struct ixgbe_hw * hw)5350 bool ixgbe_mng_present(struct ixgbe_hw *hw)
5351 {
5352 u32 fwsm;
5353
5354 if (hw->mac.type < ixgbe_mac_82599EB)
5355 return FALSE;
5356
5357 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5358 return !!(fwsm & IXGBE_FWSM_FW_MODE_PT);
5359 }
5360
5361 /**
5362 * ixgbe_mng_enabled - Is the manageability engine enabled?
5363 * @hw: pointer to hardware structure
5364 *
5365 * Returns TRUE if the manageability engine is enabled.
5366 **/
ixgbe_mng_enabled(struct ixgbe_hw * hw)5367 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
5368 {
5369 u32 fwsm, manc, factps;
5370
5371 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5372 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
5373 return FALSE;
5374
5375 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
5376 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
5377 return FALSE;
5378
5379 if (hw->mac.type <= ixgbe_mac_X540) {
5380 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
5381 if (factps & IXGBE_FACTPS_MNGCG)
5382 return FALSE;
5383 }
5384
5385 return TRUE;
5386 }
5387
5388 /**
5389 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
5390 * @hw: pointer to hardware structure
5391 * @speed: new link speed
5392 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
5393 *
5394 * Set the link speed in the MAC and/or PHY register and restarts link.
5395 **/
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait_to_complete)5396 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
5397 ixgbe_link_speed speed,
5398 bool autoneg_wait_to_complete)
5399 {
5400 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5401 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5402 s32 status = IXGBE_SUCCESS;
5403 u32 speedcnt = 0;
5404 u32 i = 0;
5405 bool autoneg, link_up = FALSE;
5406
5407 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
5408
5409 /* Mask off requested but non-supported speeds */
5410 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
5411 if (status != IXGBE_SUCCESS)
5412 return status;
5413
5414 speed &= link_speed;
5415
5416 /* Try each speed one by one, highest priority first. We do this in
5417 * software because 10Gb fiber doesn't support speed autonegotiation.
5418 */
5419 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
5420 speedcnt++;
5421 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5422
5423 /* Set the module link speed */
5424 switch (hw->phy.media_type) {
5425 case ixgbe_media_type_fiber_fixed:
5426 case ixgbe_media_type_fiber:
5427 ixgbe_set_rate_select_speed(hw,
5428 IXGBE_LINK_SPEED_10GB_FULL);
5429 break;
5430 case ixgbe_media_type_fiber_qsfp:
5431 /* QSFP module automatically detects MAC link speed */
5432 break;
5433 default:
5434 DEBUGOUT("Unexpected media type.\n");
5435 break;
5436 }
5437
5438 /* Allow module to change analog characteristics (1G->10G) */
5439 msec_delay(40);
5440
5441 status = ixgbe_setup_mac_link(hw,
5442 IXGBE_LINK_SPEED_10GB_FULL,
5443 autoneg_wait_to_complete);
5444 if (status != IXGBE_SUCCESS)
5445 return status;
5446
5447 /* Flap the Tx laser if it has not already been done */
5448 ixgbe_flap_tx_laser(hw);
5449
5450 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
5451 * Section 73.10.2, we may have to wait up to 1000ms if KR is
5452 * attempted. 82599 uses the same timing for 10g SFI.
5453 */
5454 for (i = 0; i < 10; i++) {
5455 /* Wait for the link partner to also set speed */
5456 msec_delay(100);
5457
5458 /* If we have link, just jump out */
5459 status = ixgbe_check_link(hw, &link_speed,
5460 &link_up, FALSE);
5461 if (status != IXGBE_SUCCESS)
5462 return status;
5463
5464 if (link_up)
5465 goto out;
5466 }
5467 }
5468
5469 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
5470 speedcnt++;
5471 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
5472 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
5473
5474 /* Set the module link speed */
5475 switch (hw->phy.media_type) {
5476 case ixgbe_media_type_fiber_fixed:
5477 case ixgbe_media_type_fiber:
5478 ixgbe_set_rate_select_speed(hw,
5479 IXGBE_LINK_SPEED_1GB_FULL);
5480 break;
5481 case ixgbe_media_type_fiber_qsfp:
5482 /* QSFP module automatically detects link speed */
5483 break;
5484 default:
5485 DEBUGOUT("Unexpected media type.\n");
5486 break;
5487 }
5488
5489 /* Allow module to change analog characteristics (10G->1G) */
5490 msec_delay(40);
5491
5492 status = ixgbe_setup_mac_link(hw,
5493 IXGBE_LINK_SPEED_1GB_FULL,
5494 autoneg_wait_to_complete);
5495 if (status != IXGBE_SUCCESS)
5496 return status;
5497
5498 /* Flap the Tx laser if it has not already been done */
5499 ixgbe_flap_tx_laser(hw);
5500
5501 /* Wait for the link partner to also set speed */
5502 msec_delay(100);
5503
5504 /* If we have link, just jump out */
5505 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
5506 if (status != IXGBE_SUCCESS)
5507 return status;
5508
5509 if (link_up)
5510 goto out;
5511 }
5512
5513 if (speed == 0) {
5514 /* Disable the Tx laser for media none */
5515 ixgbe_disable_tx_laser(hw);
5516
5517 goto out;
5518 }
5519
5520 /* We didn't get link. Configure back to the highest speed we tried,
5521 * (if there was more than one). We call ourselves back with just the
5522 * single highest speed that the user requested.
5523 */
5524 if (speedcnt > 1)
5525 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
5526 highest_link_speed,
5527 autoneg_wait_to_complete);
5528
5529 out:
5530 /* Set autoneg_advertised value based on input link speed */
5531 hw->phy.autoneg_advertised = 0;
5532
5533 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
5534 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
5535
5536 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
5537 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
5538
5539 return status;
5540 }
5541
5542 /**
5543 * ixgbe_set_soft_rate_select_speed - Set module link speed
5544 * @hw: pointer to hardware structure
5545 * @speed: link speed to set
5546 *
5547 * Set module link speed via the soft rate select.
5548 */
ixgbe_set_soft_rate_select_speed(struct ixgbe_hw * hw,ixgbe_link_speed speed)5549 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
5550 ixgbe_link_speed speed)
5551 {
5552 s32 status;
5553 u8 rs, eeprom_data;
5554
5555 switch (speed) {
5556 case IXGBE_LINK_SPEED_10GB_FULL:
5557 /* one bit mask same as setting on */
5558 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
5559 break;
5560 case IXGBE_LINK_SPEED_1GB_FULL:
5561 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
5562 break;
5563 default:
5564 DEBUGOUT("Invalid fixed module speed\n");
5565 return;
5566 }
5567
5568 /* Set RS0 */
5569 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5570 IXGBE_I2C_EEPROM_DEV_ADDR2,
5571 &eeprom_data);
5572 if (status) {
5573 DEBUGOUT("Failed to read Rx Rate Select RS0\n");
5574 goto out;
5575 }
5576
5577 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5578
5579 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5580 IXGBE_I2C_EEPROM_DEV_ADDR2,
5581 eeprom_data);
5582 if (status) {
5583 DEBUGOUT("Failed to write Rx Rate Select RS0\n");
5584 goto out;
5585 }
5586
5587 /* Set RS1 */
5588 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5589 IXGBE_I2C_EEPROM_DEV_ADDR2,
5590 &eeprom_data);
5591 if (status) {
5592 DEBUGOUT("Failed to read Rx Rate Select RS1\n");
5593 goto out;
5594 }
5595
5596 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5597
5598 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5599 IXGBE_I2C_EEPROM_DEV_ADDR2,
5600 eeprom_data);
5601 if (status) {
5602 DEBUGOUT("Failed to write Rx Rate Select RS1\n");
5603 goto out;
5604 }
5605 out:
5606 return;
5607 }
5608